286 changes: 1 addition & 285 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1040,7 +1040,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setJumpIsExpensive();

setTargetDAGCombine({ISD::INTRINSIC_WO_CHAIN, ISD::ADD, ISD::SUB, ISD::AND,
ISD::OR, ISD::XOR, ISD::SETCC, ISD::SELECT, ISD::MUL});
ISD::OR, ISD::XOR, ISD::SETCC, ISD::SELECT});
if (Subtarget.is64Bit())
setTargetDAGCombine(ISD::SRA);

Expand All @@ -1064,8 +1064,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setTargetDAGCombine({ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER,
ISD::VP_GATHER, ISD::VP_SCATTER, ISD::SRA, ISD::SRL,
ISD::SHL, ISD::STORE, ISD::SPLAT_VECTOR});
if (Subtarget.hasVendorXTHeadMemPair())
setTargetDAGCombine({ISD::LOAD, ISD::STORE});
if (Subtarget.useRVVForFixedLengthVectors())
setTargetDAGCombine(ISD::BITCAST);

Expand Down Expand Up @@ -8646,134 +8644,6 @@ static SDValue combineDeMorganOfBoolean(SDNode *N, SelectionDAG &DAG) {
return DAG.getNode(ISD::XOR, DL, VT, Logic, DAG.getConstant(1, DL, VT));
}

static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
SDLoc DL(N);
const MVT XLenVT = Subtarget.getXLenVT();
const EVT VT = N->getValueType(0);

// An MUL is usually smaller than any alternative sequence for legal type.
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (DAG.getMachineFunction().getFunction().hasMinSize() &&
TLI.isOperationLegal(ISD::MUL, VT))
return SDValue();

SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
ConstantSDNode *ConstOp = dyn_cast<ConstantSDNode>(N1);
// Any optimization requires a constant RHS.
if (!ConstOp)
return SDValue();

const APInt &C = ConstOp->getAPIntValue();
// A multiply-by-pow2 will be reduced to a shift by the
// architecture-independent code.
if (C.isPowerOf2())
return SDValue();

// The below optimizations only work for non-negative constants
if (!C.isNonNegative())
return SDValue();

auto Shl = [&](SDValue Value, unsigned ShiftAmount) {
if (!ShiftAmount)
return Value;

SDValue ShiftAmountConst = DAG.getConstant(ShiftAmount, DL, XLenVT);
return DAG.getNode(ISD::SHL, DL, Value.getValueType(), Value,
ShiftAmountConst);
};
auto Add = [&](SDValue Addend1, SDValue Addend2) {
return DAG.getNode(ISD::ADD, DL, Addend1.getValueType(), Addend1, Addend2);
};

if (Subtarget.hasVendorXTHeadBa()) {
// We try to simplify using shift-and-add instructions into up to
// 3 instructions (e.g. 2x shift-and-add and 1x shift).

auto isDivisibleByShiftedAddConst = [&](APInt C, APInt &N,
APInt &Quotient) {
unsigned BitWidth = C.getBitWidth();
for (unsigned i = 3; i >= 1; --i) {
APInt X(BitWidth, (1 << i) + 1);
APInt Remainder;
APInt::sdivrem(C, X, Quotient, Remainder);
if (Remainder == 0) {
N = X;
return true;
}
}
return false;
};
auto isShiftedAddConst = [&](APInt C, APInt &N) {
APInt Quotient;
return isDivisibleByShiftedAddConst(C, N, Quotient) && Quotient == 1;
};
auto isSmallShiftAmount = [](APInt C) {
return (C == 2) || (C == 4) || (C == 8);
};

auto ShiftAndAdd = [&](SDValue Value, unsigned ShiftAmount,
SDValue Addend) {
return Add(Shl(Value, ShiftAmount), Addend);
};
auto AnyExt = [&](SDValue Value) {
return DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Value);
};
auto Trunc = [&](SDValue Value) {
return DAG.getNode(ISD::TRUNCATE, DL, VT, Value);
};

unsigned TrailingZeroes = C.countTrailingZeros();
const APInt ShiftedC = C.ashr(TrailingZeroes);
const APInt ShiftedCMinusOne = ShiftedC - 1;

// the below comments use the following notation:
// n, m .. a shift-amount for a shift-and-add instruction
// (i.e. in { 2, 4, 8 })
// k .. a power-of-2 that is equivalent to shifting by
// TrailingZeroes bits
// i, j .. a power-of-2

APInt ShiftAmt1;
APInt ShiftAmt2;
APInt Quotient;

// C = (m + 1) * k
if (isShiftedAddConst(ShiftedC, ShiftAmt1)) {
SDValue Op0 = AnyExt(N0);
SDValue Result = ShiftAndAdd(Op0, ShiftAmt1.logBase2(), Op0);
return Trunc(Shl(Result, TrailingZeroes));
}
// C = (m + 1) * (n + 1) * k
if (isDivisibleByShiftedAddConst(ShiftedC, ShiftAmt1, Quotient) &&
isShiftedAddConst(Quotient, ShiftAmt2)) {
SDValue Op0 = AnyExt(N0);
SDValue Result = ShiftAndAdd(Op0, ShiftAmt1.logBase2(), Op0);
Result = ShiftAndAdd(Result, ShiftAmt2.logBase2(), Result);
return Trunc(Shl(Result, TrailingZeroes));
}
// C = ((m + 1) * n + 1) * k
if (isDivisibleByShiftedAddConst(ShiftedCMinusOne, ShiftAmt1, ShiftAmt2) &&
isSmallShiftAmount(ShiftAmt2)) {
SDValue Op0 = AnyExt(N0);
SDValue Result = ShiftAndAdd(Op0, ShiftAmt1.logBase2(), Op0);
Result = ShiftAndAdd(Result, Quotient.logBase2(), Op0);
return Trunc(Shl(Result, TrailingZeroes));
}

// C has 2 bits set: synthesize using 2 shifts and 1 add (which may
// see one of the shifts merged into a shift-and-add, if feasible)
if (C.countPopulation() == 2) {
APInt HighBit(C.getBitWidth(), (1 << C.logBase2()));
APInt LowBit = C - HighBit;
return Add(Shl(N0, HighBit.logBase2()), Shl(N0, LowBit.logBase2()));
}
}

return SDValue();
}

static SDValue performTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
SDValue N0 = N->getOperand(0);
Expand Down Expand Up @@ -9766,145 +9636,6 @@ combineBinOp_VLToVWBinOp_VL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
return InputRootReplacement;
}

// Helper function for performMemPairCombine.
// Try to combine the memory loads/stores LSNode1 and LSNode2
// into a single memory pair operation.
static SDValue tryMemPairCombine(SelectionDAG &DAG, LSBaseSDNode *LSNode1,
LSBaseSDNode *LSNode2, SDValue BasePtr,
uint64_t Imm) {
SmallPtrSet<const SDNode *, 32> Visited;
SmallVector<const SDNode *, 8> Worklist = {LSNode1, LSNode2};

if (SDNode::hasPredecessorHelper(LSNode1, Visited, Worklist) ||
SDNode::hasPredecessorHelper(LSNode2, Visited, Worklist))
return SDValue();

MachineFunction &MF = DAG.getMachineFunction();
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();

// The new operation has twice the width.
MVT XLenVT = Subtarget.getXLenVT();
EVT MemVT = LSNode1->getMemoryVT();
EVT NewMemVT = (MemVT == MVT::i32) ? MVT::i64 : MVT::i128;
MachineMemOperand *MMO = LSNode1->getMemOperand();
MachineMemOperand *NewMMO = MF.getMachineMemOperand(
MMO, MMO->getPointerInfo(), MemVT == MVT::i32 ? 8 : 16);

if (LSNode1->getOpcode() == ISD::LOAD) {
auto Ext = cast<LoadSDNode>(LSNode1)->getExtensionType();
unsigned Opcode;
if (MemVT == MVT::i32)
Opcode = (Ext == ISD::ZEXTLOAD) ? RISCVISD::TH_LWUD : RISCVISD::TH_LWD;
else
Opcode = RISCVISD::TH_LDD;

SDValue Res = DAG.getMemIntrinsicNode(
Opcode, SDLoc(LSNode1), DAG.getVTList({XLenVT, XLenVT, MVT::Other}),
{LSNode1->getChain(), BasePtr,
DAG.getConstant(Imm, SDLoc(LSNode1), XLenVT)},
NewMemVT, NewMMO);

SDValue Node1 =
DAG.getMergeValues({Res.getValue(0), Res.getValue(2)}, SDLoc(LSNode1));
SDValue Node2 =
DAG.getMergeValues({Res.getValue(1), Res.getValue(2)}, SDLoc(LSNode2));

DAG.ReplaceAllUsesWith(LSNode2, Node2.getNode());
return Node1;
} else {
unsigned Opcode = (MemVT == MVT::i32) ? RISCVISD::TH_SWD : RISCVISD::TH_SDD;

SDValue Res = DAG.getMemIntrinsicNode(
Opcode, SDLoc(LSNode1), DAG.getVTList(MVT::Other),
{LSNode1->getChain(), LSNode1->getOperand(1), LSNode2->getOperand(1),
BasePtr, DAG.getConstant(Imm, SDLoc(LSNode1), XLenVT)},
NewMemVT, NewMMO);

DAG.ReplaceAllUsesWith(LSNode2, Res.getNode());
return Res;
}
}

// Try to combine two adjacent loads/stores to a single pair instruction from
// the XTHeadMemPair vendor extension.
static SDValue performMemPairCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
SelectionDAG &DAG = DCI.DAG;
MachineFunction &MF = DAG.getMachineFunction();
const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();

// Target does not support load/store pair.
if (!Subtarget.hasVendorXTHeadMemPair())
return SDValue();

LSBaseSDNode *LSNode1 = cast<LSBaseSDNode>(N);
EVT MemVT = LSNode1->getMemoryVT();
unsigned OpNum = LSNode1->getOpcode() == ISD::LOAD ? 1 : 2;

// No volatile, indexed or atomic loads/stores.
if (!LSNode1->isSimple() || LSNode1->isIndexed())
return SDValue();

// Function to get a base + constant representation from a memory value.
auto ExtractBaseAndOffset = [](SDValue Ptr) -> std::pair<SDValue, uint64_t> {
if (Ptr->getOpcode() == ISD::ADD) {
if (auto *C1 = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
return {Ptr->getOperand(0), C1->getZExtValue()};
}
}
return {Ptr, 0};
};

auto [Base1, Offset1] = ExtractBaseAndOffset(LSNode1->getOperand(OpNum));

SDValue Chain = N->getOperand(0);
for (SDNode::use_iterator UI = Chain->use_begin(), UE = Chain->use_end();
UI != UE; ++UI) {
SDUse &Use = UI.getUse();
if (Use.getUser() != N && Use.getResNo() == 0 &&
Use.getUser()->getOpcode() == N->getOpcode()) {
LSBaseSDNode *LSNode2 = cast<LSBaseSDNode>(Use.getUser());

// No volatile, indexed or atomic loads/stores.
if (!LSNode2->isSimple() || LSNode2->isIndexed())
continue;

// Check if LSNode1 and LSNode2 have the same type and extension.
if (LSNode1->getOpcode() == ISD::LOAD)
if (cast<LoadSDNode>(LSNode2)->getExtensionType() !=
cast<LoadSDNode>(LSNode1)->getExtensionType())
continue;

if (LSNode1->getMemoryVT() != LSNode2->getMemoryVT())
continue;

auto [Base2, Offset2] = ExtractBaseAndOffset(LSNode2->getOperand(OpNum));

// Check if the base pointer is the same for both instruction.
if (Base1 != Base2)
continue;

// Check if the offsets match the XTHeadMemPair encoding contraints.
if (MemVT == MVT::i32) {
// Check for adjucent i32 values and a 2-bit index.
if ((Offset1 + 4 != Offset2) || !isShiftedUInt<2, 3>(Offset1))
continue;
} else {
// Check for adjucent i64 values and a 2-bit index.
if ((Offset1 + 8 != Offset2) || !isShiftedUInt<2, 4>(Offset1))
continue;
}

// Try to combine.
if (SDValue Res =
tryMemPairCombine(DAG, LSNode1, LSNode2, Base1, Offset1))
return Res;
}
}

return SDValue();
}

// Fold
// (fp_to_int (froundeven X)) -> fcvt X, rne
// (fp_to_int (ftrunc X)) -> fcvt X, rtz
Expand Down Expand Up @@ -10562,8 +10293,6 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return performADDCombine(N, DAG, Subtarget);
case ISD::SUB:
return performSUBCombine(N, DAG, Subtarget);
case ISD::MUL:
return performMULCombine(N, DAG, Subtarget);
case ISD::AND:
return performANDCombine(N, DCI, Subtarget);
case ISD::OR:
Expand Down Expand Up @@ -10876,15 +10605,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), A, B, C, Mask,
VL);
}
case ISD::LOAD:
case ISD::STORE: {
if (DCI.isAfterLegalizeDAG())
if (SDValue V = performMemPairCombine(N, DCI))
return V;

if (N->getOpcode() != ISD::STORE)
break;

auto *Store = cast<StoreSDNode>(N);
SDValue Val = Store->getValue();
// Combine store of vmv.x.s/vfmv.f.s to vse with VL of 1.
Expand Down Expand Up @@ -13730,11 +13451,6 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(ORC_B)
NODE_NAME_CASE(ZIP)
NODE_NAME_CASE(UNZIP)
NODE_NAME_CASE(TH_LWD)
NODE_NAME_CASE(TH_LWUD)
NODE_NAME_CASE(TH_LDD)
NODE_NAME_CASE(TH_SWD)
NODE_NAME_CASE(TH_SDD)
NODE_NAME_CASE(VMV_V_X_VL)
NODE_NAME_CASE(VFMV_V_F_VL)
NODE_NAME_CASE(VMV_X_S)
Expand Down
6 changes: 0 additions & 6 deletions llvm/lib/Target/RISCV/RISCVISelLowering.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -336,12 +336,6 @@ enum NodeType : unsigned {
// Load address.
LA = ISD::FIRST_TARGET_MEMORY_OPCODE,
LA_TLS_IE,

TH_LWD,
TH_LWUD,
TH_LDD,
TH_SWD,
TH_SDD,
};
} // namespace RISCVISD

Expand Down
153 changes: 61 additions & 92 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,26 +10,6 @@
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// T-HEAD C specific DAG Nodes.
//===----------------------------------------------------------------------===//

def SDT_TDBLD : SDTypeProfile<2, 2,
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 3>, SDTCisPtrTy<2>, SDTCisVT<3, XLenVT>]>;
def SDT_TDBST : SDTypeProfile<0, 4,
[SDTCisSameAs<0, 1>, SDTCisSameAs<1, 3>, SDTCisPtrTy<2>, SDTCisVT<3, XLenVT>]>;

def TH_TLWUD : SDNode<"RISCVISD::TH_LWUD", SDT_TDBLD,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def TH_TLWD : SDNode<"RISCVISD::TH_LWD", SDT_TDBLD,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def TH_TLDD : SDNode<"RISCVISD::TH_LDD", SDT_TDBLD,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def TH_TSWD : SDNode<"RISCVISD::TH_SWD", SDT_TDBST,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def TH_TSDD : SDNode<"RISCVISD::TH_SDD", SDT_TDBST,
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;

//===----------------------------------------------------------------------===//
// Instruction class templates
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -116,29 +96,6 @@ class THMulAccumulate_rr<bits<7> funct7, string opcodestr>
let Constraints = "$rd_wb = $rd";
}

let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "THeadMemPair",
hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class THLoadPair<bits<5> funct5, string opcodestr>
: RVInstR<!shl(funct5, 2), 0b100, OPC_CUSTOM_0,
(outs GPR:$rd, GPR:$rs2), (ins GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
bits<2> uimm2;
let Inst{26-25} = uimm2;
let DecoderMethod = "decodeXTHeadMemPair";
let Constraints = "@earlyclobber $rd,@earlyclobber $rs2";
}

let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "THeadMemPair",
hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class THStorePair<bits<5> funct5, string opcodestr>
: RVInstR<!shl(funct5, 2), 0b101, OPC_CUSTOM_0,
(outs), (ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
bits<2> uimm2;
let Inst{26-25} = uimm2;
let DecoderMethod = "decodeXTHeadMemPair";
}


//===----------------------------------------------------------------------===//
// Combination of instruction classes.
Expand Down Expand Up @@ -197,23 +154,6 @@ def TH_MULAW : THMulAccumulate_rr<0b0010010, "th.mulaw">;
def TH_MULSW : THMulAccumulate_rr<0b0010011, "th.mulsw">;
} // Predicates = [HasVendorXTHeadMac, IsRV64]

let Predicates = [HasVendorXTHeadMemPair] in {
def TH_LWUD : THLoadPair<0b11110, "th.lwud">,
Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
def TH_SWD : THStorePair<0b11100, "th.swd">,
Sched<[WriteSTW, WriteSTW, ReadStoreData, ReadMemBase]>;
let IsSignExtendingOpW = 1 in
def TH_LWD : THLoadPair<0b11100, "th.lwd">,
Sched<[WriteLDW, WriteLDW, ReadMemBase]>;
}

let Predicates = [HasVendorXTHeadMemPair, IsRV64] in {
def TH_LDD : THLoadPair<0b11111, "th.ldd">,
Sched<[WriteLDD, WriteLDD, ReadMemBase]>;
def TH_SDD : THStorePair<0b11111, "th.sdd">,
Sched<[WriteSTD, WriteSTD, ReadStoreData, ReadMemBase]>;
}

let Predicates = [HasVendorXTHeadVdot],
Constraints = "@earlyclobber $vd",
RVVConstraint = WidenV in {
Expand Down Expand Up @@ -300,6 +240,67 @@ def : Pat<(add sh2add_op:$rs1, non_imm12:$rs2),
(TH_ADDSL GPR:$rs2, sh2add_op:$rs1, 2)>;
def : Pat<(add sh3add_op:$rs1, non_imm12:$rs2),
(TH_ADDSL GPR:$rs2, sh3add_op:$rs1, 3)>;

def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 6)), GPR:$rs2),
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 1), 1)>;
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 10)), GPR:$rs2),
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 2), 1)>;
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 18)), GPR:$rs2),
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 3), 1)>;
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 12)), GPR:$rs2),
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 1), 2)>;
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 20)), GPR:$rs2),
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 2), 2)>;
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 36)), GPR:$rs2),
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 3), 2)>;
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 24)), GPR:$rs2),
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 1), 3)>;
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2),
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 2), 3)>;
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2),
(TH_ADDSL GPR:$rs2, (TH_ADDSL GPR:$rs1, GPR:$rs1, 3), 3)>;

def : Pat<(add GPR:$r, CSImm12MulBy4:$i),
(TH_ADDSL GPR:$r, (ADDI X0, (SimmShiftRightBy2XForm CSImm12MulBy4:$i)), 2)>;
def : Pat<(add GPR:$r, CSImm12MulBy8:$i),
(TH_ADDSL GPR:$r, (ADDI X0, (SimmShiftRightBy3XForm CSImm12MulBy8:$i)), 3)>;

def : Pat<(mul GPR:$r, C3LeftShift:$i),
(SLLI (TH_ADDSL GPR:$r, GPR:$r, 1),
(TrailingZeros C3LeftShift:$i))>;
def : Pat<(mul GPR:$r, C5LeftShift:$i),
(SLLI (TH_ADDSL GPR:$r, GPR:$r, 2),
(TrailingZeros C5LeftShift:$i))>;
def : Pat<(mul GPR:$r, C9LeftShift:$i),
(SLLI (TH_ADDSL GPR:$r, GPR:$r, 3),
(TrailingZeros C9LeftShift:$i))>;

def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 11)),
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 2), 1)>;
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 19)),
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 3), 1)>;
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 13)),
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 1), 2)>;
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 21)),
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 2), 2)>;
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 37)),
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 3), 2)>;
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 25)),
(TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 2), (TH_ADDSL GPR:$r, GPR:$r, 2), 2)>;
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 41)),
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 2), 3)>;
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 73)),
(TH_ADDSL GPR:$r, (TH_ADDSL GPR:$r, GPR:$r, 3), 3)>;
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 27)),
(TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 3), (TH_ADDSL GPR:$r, GPR:$r, 3), 1)>;
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 45)),
(TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 3), (TH_ADDSL GPR:$r, GPR:$r, 3), 2)>;
def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 81)),
(TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 3), (TH_ADDSL GPR:$r, GPR:$r, 3), 3)>;

def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 200)),
(SLLI (TH_ADDSL (TH_ADDSL GPR:$r, GPR:$r, 2),
(TH_ADDSL GPR:$r, GPR:$r, 2), 2), 3)>;
} // Predicates = [HasVendorXTHeadBa]

let Predicates = [HasVendorXTHeadBb] in {
Expand Down Expand Up @@ -392,35 +393,3 @@ defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqau", "PseudoTHVdotVMAQAU", AllQu
defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqasu","PseudoTHVdotVMAQASU",AllQuadWidenableInt8NoVLMulVectors>;
defm : VPatTernaryVMAQA_VX<"int_riscv_th_vmaqaus", "PseudoTHVdotVMAQAUS",AllQuadWidenableInt8NoVLMulVectors>;
}

def uimm2_3_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((N->getZExtValue() >> 3) & 0x3,
SDLoc(N), Subtarget->getXLenVT());
}]>;

def uimm2_3 : Operand<XLenVT>, ImmLeaf<XLenVT, [{
return isShiftedUInt<2, 3>(Imm);
}], uimm2_3_XFORM>;

def uimm2_4_XFORM : SDNodeXForm<imm, [{
return CurDAG->getTargetConstant((N->getZExtValue() >> 4) & 0x3,
SDLoc(N), Subtarget->getXLenVT());
}]>;

def uimm2_4 : Operand<XLenVT>, ImmLeaf<XLenVT, [{
return isShiftedUInt<2, 4>(Imm);
}], uimm2_4_XFORM>;

let Predicates = [HasVendorXTHeadMemPair, IsRV64] in {
def : Pat<(TH_TLWUD i64:$rs1, uimm2_3:$uimm2_3), (TH_LWUD i64:$rs1, uimm2_3:$uimm2_3, 3)>;
def : Pat<(TH_TLDD i64:$rs1, uimm2_4:$uimm2_4), (TH_LDD i64:$rs1, uimm2_4:$uimm2_4, 4)>;

def : Pat<(TH_TSDD i64:$rd1, i64:$rd2, i64:$rs1, uimm2_4:$uimm2_4),
(TH_SDD i64:$rd1, i64:$rd2, i64:$rs1, uimm2_4:$uimm2_4, 4)>;
}

let Predicates = [HasVendorXTHeadMemPair] in {
def : Pat<(TH_TLWD GPR:$rs1, uimm2_3:$uimm2_3), (TH_LWD GPR:$rs1, uimm2_3:$uimm2_3, 3)>;
def : Pat<(TH_TSWD GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3),
(TH_SWD GPR:$rd1, GPR:$rd2, GPR:$rs1, uimm2_3:$uimm2_3, 3)>;
}
4 changes: 0 additions & 4 deletions llvm/test/CodeGen/RISCV/attributes.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,6 @@
; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac %s -o - | FileCheck --check-prefixes=CHECK,RV32XTHEADMAC %s
; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCB %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCD %s
Expand Down Expand Up @@ -96,7 +95,6 @@
; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADBB %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadbs %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADBS %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADMAC %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV64XTHEADMEMPAIR %s
; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefixes=CHECK,RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefixes=CHECK,RV64ZTSO %s
Expand Down Expand Up @@ -149,7 +147,6 @@
; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
; RV32XTHEADMAC: .attribute 5, "rv32i2p0_xtheadmac1p0"
; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p0_xtheadmempair1p0"
; RV32ZCA: .attribute 5, "rv32i2p0_zca1p0"
; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0"
; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
Expand Down Expand Up @@ -203,7 +200,6 @@
; RV64XTHEADBB: .attribute 5, "rv64i2p0_xtheadbb1p0"
; RV64XTHEADBS: .attribute 5, "rv64i2p0_xtheadbs1p0"
; RV64XTHEADMAC: .attribute 5, "rv64i2p0_xtheadmac1p0"
; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p0_xtheadmempair1p0"
; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0"
Expand Down
227 changes: 0 additions & 227 deletions llvm/test/CodeGen/RISCV/xtheadmempair.ll
View file

This file was deleted.

20 changes: 0 additions & 20 deletions llvm/test/MC/RISCV/rv32xtheadmempair-invalid.s
View file

This file was deleted.

18 changes: 0 additions & 18 deletions llvm/test/MC/RISCV/rv32xtheadmempair-valid.s
View file

This file was deleted.

18 changes: 0 additions & 18 deletions llvm/test/MC/RISCV/rv64xtheadmempair-invalid.s
View file

This file was deleted.

26 changes: 0 additions & 26 deletions llvm/test/MC/RISCV/rv64xtheadmempair-valid.s
View file

This file was deleted.