419 changes: 170 additions & 249 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
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26 changes: 12 additions & 14 deletions llvm/test/CodeGen/RISCV/split-offsets.ll
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -riscv-enable-sink-fold < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -riscv-enable-sink-fold < %s \
; RUN: | FileCheck %s -check-prefix=RV64I

; Check that memory accesses to array elements with large offsets have those
Expand Down Expand Up @@ -157,23 +157,21 @@ define void @test4(ptr %dest) {
; RV32I-LABEL: test4:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 2047
; RV32I-NEXT: addi a1, a0, 1
; RV32I-NEXT: li a2, 1
; RV32I-NEXT: sb a2, 1(a0)
; RV32I-NEXT: sb a2, 1(a1)
; RV32I-NEXT: sb a2, 2(a1)
; RV32I-NEXT: sb a2, 3(a1)
; RV32I-NEXT: li a1, 1
; RV32I-NEXT: sb a1, 1(a0)
; RV32I-NEXT: sb a1, 2(a0)
; RV32I-NEXT: sb a1, 3(a0)
; RV32I-NEXT: sb a1, 4(a0)
; RV32I-NEXT: ret
;
; RV64I-LABEL: test4:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 2047
; RV64I-NEXT: addi a1, a0, 1
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: sb a2, 1(a0)
; RV64I-NEXT: sb a2, 1(a1)
; RV64I-NEXT: sb a2, 2(a1)
; RV64I-NEXT: sb a2, 3(a1)
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: sb a1, 1(a0)
; RV64I-NEXT: sb a1, 2(a0)
; RV64I-NEXT: sb a1, 3(a0)
; RV64I-NEXT: sb a1, 4(a0)
; RV64I-NEXT: ret
%p1 = getelementptr i8, ptr %dest, i32 2048
store i8 1, ptr %p1
Expand Down
108 changes: 54 additions & 54 deletions llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -riscv-enable-sink-fold < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs -riscv-enable-sink-fold < %s \
; RUN: | FileCheck -check-prefix=RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -riscv-enable-sink-fold < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs -riscv-enable-sink-fold < %s \
; RUN: | FileCheck -check-prefix=RV64IM %s

define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) nounwind {
Expand Down Expand Up @@ -1085,49 +1085,49 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind {
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s1, 24(a1)
; RV32I-NEXT: lw s2, 28(a1)
; RV32I-NEXT: lw s3, 16(a1)
; RV32I-NEXT: lw s4, 20(a1)
; RV32I-NEXT: lw s5, 8(a1)
; RV32I-NEXT: lw s6, 12(a1)
; RV32I-NEXT: lw s0, 24(a1)
; RV32I-NEXT: lw s1, 28(a1)
; RV32I-NEXT: lw s2, 16(a1)
; RV32I-NEXT: lw s3, 20(a1)
; RV32I-NEXT: lw s4, 8(a1)
; RV32I-NEXT: lw s5, 12(a1)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: li a2, 1
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: mv s8, a1
; RV32I-NEXT: li a2, 654
; RV32I-NEXT: mv a0, s5
; RV32I-NEXT: mv a1, s6
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: mv s6, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: li a2, 23
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv s4, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a2, a0, 1327
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: sw a1, 28(s0)
; RV32I-NEXT: sw a0, 24(s0)
; RV32I-NEXT: sw s4, 20(s0)
; RV32I-NEXT: sw s3, 16(s0)
; RV32I-NEXT: sw s6, 12(s0)
; RV32I-NEXT: sw s5, 8(s0)
; RV32I-NEXT: sw s8, 4(s0)
; RV32I-NEXT: sw s7, 0(s0)
; RV32I-NEXT: sw a1, 28(s6)
; RV32I-NEXT: sw a0, 24(s6)
; RV32I-NEXT: sw s3, 20(s6)
; RV32I-NEXT: sw s2, 16(s6)
; RV32I-NEXT: sw s5, 12(s6)
; RV32I-NEXT: sw s4, 8(s6)
; RV32I-NEXT: sw s8, 4(s6)
; RV32I-NEXT: sw s7, 0(s6)
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
Expand All @@ -1154,49 +1154,49 @@ define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) nounwind {
; RV32IM-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw s1, 24(a1)
; RV32IM-NEXT: lw s2, 28(a1)
; RV32IM-NEXT: lw s3, 16(a1)
; RV32IM-NEXT: lw s4, 20(a1)
; RV32IM-NEXT: lw s5, 8(a1)
; RV32IM-NEXT: lw s6, 12(a1)
; RV32IM-NEXT: lw s0, 24(a1)
; RV32IM-NEXT: lw s1, 28(a1)
; RV32IM-NEXT: lw s2, 16(a1)
; RV32IM-NEXT: lw s3, 20(a1)
; RV32IM-NEXT: lw s4, 8(a1)
; RV32IM-NEXT: lw s5, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1)
; RV32IM-NEXT: mv s0, a0
; RV32IM-NEXT: mv s6, a0
; RV32IM-NEXT: li a2, 1
; RV32IM-NEXT: mv a0, a3
; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: mv s7, a0
; RV32IM-NEXT: mv s8, a1
; RV32IM-NEXT: li a2, 654
; RV32IM-NEXT: mv a0, s5
; RV32IM-NEXT: mv a1, s6
; RV32IM-NEXT: mv a0, s4
; RV32IM-NEXT: mv a1, s5
; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: mv s5, a0
; RV32IM-NEXT: mv s6, a1
; RV32IM-NEXT: mv s4, a0
; RV32IM-NEXT: mv s5, a1
; RV32IM-NEXT: li a2, 23
; RV32IM-NEXT: mv a0, s3
; RV32IM-NEXT: mv a1, s4
; RV32IM-NEXT: mv a0, s2
; RV32IM-NEXT: mv a1, s3
; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: mv s3, a0
; RV32IM-NEXT: mv s4, a1
; RV32IM-NEXT: mv s2, a0
; RV32IM-NEXT: mv s3, a1
; RV32IM-NEXT: lui a0, 1
; RV32IM-NEXT: addi a2, a0, 1327
; RV32IM-NEXT: mv a0, s1
; RV32IM-NEXT: mv a1, s2
; RV32IM-NEXT: mv a0, s0
; RV32IM-NEXT: mv a1, s1
; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: sw a1, 28(s0)
; RV32IM-NEXT: sw a0, 24(s0)
; RV32IM-NEXT: sw s4, 20(s0)
; RV32IM-NEXT: sw s3, 16(s0)
; RV32IM-NEXT: sw s6, 12(s0)
; RV32IM-NEXT: sw s5, 8(s0)
; RV32IM-NEXT: sw s8, 4(s0)
; RV32IM-NEXT: sw s7, 0(s0)
; RV32IM-NEXT: sw a1, 28(s6)
; RV32IM-NEXT: sw a0, 24(s6)
; RV32IM-NEXT: sw s3, 20(s6)
; RV32IM-NEXT: sw s2, 16(s6)
; RV32IM-NEXT: sw s5, 12(s6)
; RV32IM-NEXT: sw s4, 8(s6)
; RV32IM-NEXT: sw s8, 4(s6)
; RV32IM-NEXT: sw s7, 0(s6)
; RV32IM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
Expand Down
108 changes: 54 additions & 54 deletions llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
View file
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -riscv-enable-sink-fold < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs -riscv-enable-sink-fold < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV32IM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -riscv-enable-sink-fold < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs -riscv-enable-sink-fold < %s \
; RUN: | FileCheck -check-prefixes=CHECK,RV64IM %s


Expand Down Expand Up @@ -791,49 +791,49 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind {
; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s1, 24(a1)
; RV32I-NEXT: lw s2, 28(a1)
; RV32I-NEXT: lw s3, 16(a1)
; RV32I-NEXT: lw s4, 20(a1)
; RV32I-NEXT: lw s5, 8(a1)
; RV32I-NEXT: lw s6, 12(a1)
; RV32I-NEXT: lw s0, 24(a1)
; RV32I-NEXT: lw s1, 28(a1)
; RV32I-NEXT: lw s2, 16(a1)
; RV32I-NEXT: lw s3, 20(a1)
; RV32I-NEXT: lw s4, 8(a1)
; RV32I-NEXT: lw s5, 12(a1)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s6, a0
; RV32I-NEXT: li a2, 1
; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: mv s7, a0
; RV32I-NEXT: mv s8, a1
; RV32I-NEXT: li a2, 654
; RV32I-NEXT: mv a0, s5
; RV32I-NEXT: mv a1, s6
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s5
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: mv s5, a0
; RV32I-NEXT: mv s6, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv s5, a1
; RV32I-NEXT: li a2, 23
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: mv s4, a1
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: lui a0, 1
; RV32I-NEXT: addi a2, a0, 1327
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: sw a1, 28(s0)
; RV32I-NEXT: sw a0, 24(s0)
; RV32I-NEXT: sw s4, 20(s0)
; RV32I-NEXT: sw s3, 16(s0)
; RV32I-NEXT: sw s6, 12(s0)
; RV32I-NEXT: sw s5, 8(s0)
; RV32I-NEXT: sw s8, 4(s0)
; RV32I-NEXT: sw s7, 0(s0)
; RV32I-NEXT: sw a1, 28(s6)
; RV32I-NEXT: sw a0, 24(s6)
; RV32I-NEXT: sw s3, 20(s6)
; RV32I-NEXT: sw s2, 16(s6)
; RV32I-NEXT: sw s5, 12(s6)
; RV32I-NEXT: sw s4, 8(s6)
; RV32I-NEXT: sw s8, 4(s6)
; RV32I-NEXT: sw s7, 0(s6)
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
Expand All @@ -860,49 +860,49 @@ define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) nounwind {
; RV32IM-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s8, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw s1, 24(a1)
; RV32IM-NEXT: lw s2, 28(a1)
; RV32IM-NEXT: lw s3, 16(a1)
; RV32IM-NEXT: lw s4, 20(a1)
; RV32IM-NEXT: lw s5, 8(a1)
; RV32IM-NEXT: lw s6, 12(a1)
; RV32IM-NEXT: lw s0, 24(a1)
; RV32IM-NEXT: lw s1, 28(a1)
; RV32IM-NEXT: lw s2, 16(a1)
; RV32IM-NEXT: lw s3, 20(a1)
; RV32IM-NEXT: lw s4, 8(a1)
; RV32IM-NEXT: lw s5, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1)
; RV32IM-NEXT: mv s0, a0
; RV32IM-NEXT: mv s6, a0
; RV32IM-NEXT: li a2, 1
; RV32IM-NEXT: mv a0, a3
; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: mv s7, a0
; RV32IM-NEXT: mv s8, a1
; RV32IM-NEXT: li a2, 654
; RV32IM-NEXT: mv a0, s5
; RV32IM-NEXT: mv a1, s6
; RV32IM-NEXT: mv a0, s4
; RV32IM-NEXT: mv a1, s5
; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: mv s5, a0
; RV32IM-NEXT: mv s6, a1
; RV32IM-NEXT: mv s4, a0
; RV32IM-NEXT: mv s5, a1
; RV32IM-NEXT: li a2, 23
; RV32IM-NEXT: mv a0, s3
; RV32IM-NEXT: mv a1, s4
; RV32IM-NEXT: mv a0, s2
; RV32IM-NEXT: mv a1, s3
; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: mv s3, a0
; RV32IM-NEXT: mv s4, a1
; RV32IM-NEXT: mv s2, a0
; RV32IM-NEXT: mv s3, a1
; RV32IM-NEXT: lui a0, 1
; RV32IM-NEXT: addi a2, a0, 1327
; RV32IM-NEXT: mv a0, s1
; RV32IM-NEXT: mv a1, s2
; RV32IM-NEXT: mv a0, s0
; RV32IM-NEXT: mv a1, s1
; RV32IM-NEXT: li a3, 0
; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: sw a1, 28(s0)
; RV32IM-NEXT: sw a0, 24(s0)
; RV32IM-NEXT: sw s4, 20(s0)
; RV32IM-NEXT: sw s3, 16(s0)
; RV32IM-NEXT: sw s6, 12(s0)
; RV32IM-NEXT: sw s5, 8(s0)
; RV32IM-NEXT: sw s8, 4(s0)
; RV32IM-NEXT: sw s7, 0(s0)
; RV32IM-NEXT: sw a1, 28(s6)
; RV32IM-NEXT: sw a0, 24(s6)
; RV32IM-NEXT: sw s3, 20(s6)
; RV32IM-NEXT: sw s2, 16(s6)
; RV32IM-NEXT: sw s5, 12(s6)
; RV32IM-NEXT: sw s4, 8(s6)
; RV32IM-NEXT: sw s8, 4(s6)
; RV32IM-NEXT: sw s7, 0(s6)
; RV32IM-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
Expand Down