175 changes: 101 additions & 74 deletions llvm/test/Analysis/CostModel/X86/min-legal-vector-width.ll
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79 changes: 53 additions & 26 deletions llvm/test/Analysis/CostModel/X86/trunc.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -408,32 +408,59 @@ define i32 @trunc_vXi1() {
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64i8 = trunc <64 x i8> undef to <64 x i1>
; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX512-LABEL: 'trunc_vXi1'
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V32i64 = trunc <32 x i64> undef to <32 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64i64 = trunc <64 x i64> undef to <64 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V2i32 = trunc <2 x i32> undef to <2 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V4i32 = trunc <4 x i32> undef to <4 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V8i32 = trunc <8 x i32> undef to <8 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V16i32 = trunc <16 x i32> undef to <16 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V32i32 = trunc <32 x i32> undef to <32 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64i32 = trunc <64 x i32> undef to <64 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V2i16 = trunc <2 x i16> undef to <2 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V4i16 = trunc <4 x i16> undef to <4 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V8i16 = trunc <8 x i16> undef to <8 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V16i16 = trunc <16 x i16> undef to <16 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V2i8 = trunc <2 x i8> undef to <2 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V4i8 = trunc <4 x i8> undef to <4 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V8i8 = trunc <8 x i8> undef to <8 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V16i8 = trunc <16 x i8> undef to <16 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V32i8 = trunc <32 x i8> undef to <32 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V64i8 = trunc <64 x i8> undef to <64 x i1>
; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
; AVX512F-LABEL: 'trunc_vXi1'
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32i64 = trunc <32 x i64> undef to <32 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V64i64 = trunc <64 x i64> undef to <64 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2i32 = trunc <2 x i32> undef to <2 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i32 = trunc <4 x i32> undef to <4 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i32 = trunc <8 x i32> undef to <8 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i32 = trunc <16 x i32> undef to <16 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V32i32 = trunc <32 x i32> undef to <32 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64i32 = trunc <64 x i32> undef to <64 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2i16 = trunc <2 x i16> undef to <2 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4i16 = trunc <4 x i16> undef to <4 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8i16 = trunc <8 x i16> undef to <8 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16i16 = trunc <16 x i16> undef to <16 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2i8 = trunc <2 x i8> undef to <2 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V4i8 = trunc <4 x i8> undef to <4 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V8i8 = trunc <8 x i8> undef to <8 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V16i8 = trunc <16 x i8> undef to <16 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32i8 = trunc <32 x i8> undef to <32 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V64i8 = trunc <64 x i8> undef to <64 x i1>
; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
; AVX512BW-LABEL: 'trunc_vXi1'
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i64 = trunc <2 x i64> undef to <2 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i64 = trunc <4 x i64> undef to <4 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i64 = trunc <8 x i64> undef to <8 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V16i64 = trunc <16 x i64> undef to <16 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32i64 = trunc <32 x i64> undef to <32 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %V64i64 = trunc <64 x i64> undef to <64 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2i32 = trunc <2 x i32> undef to <2 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i32 = trunc <4 x i32> undef to <4 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i32 = trunc <8 x i32> undef to <8 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i32 = trunc <16 x i32> undef to <16 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V32i32 = trunc <32 x i32> undef to <32 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V64i32 = trunc <64 x i32> undef to <64 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i16 = trunc <2 x i16> undef to <2 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i16 = trunc <4 x i16> undef to <4 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i16 = trunc <8 x i16> undef to <8 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i16 = trunc <16 x i16> undef to <16 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32i16 = trunc <32 x i16> undef to <32 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64i16 = trunc <64 x i16> undef to <64 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2i8 = trunc <2 x i8> undef to <2 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4i8 = trunc <4 x i8> undef to <4 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8i8 = trunc <8 x i8> undef to <8 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16i8 = trunc <16 x i8> undef to <16 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32i8 = trunc <32 x i8> undef to <32 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64i8 = trunc <64 x i8> undef to <64 x i1>
; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
;
%V2i64 = trunc <2 x i64> undef to <2 x i1>
%V4i64 = trunc <4 x i64> undef to <4 x i1>
Expand Down
104 changes: 104 additions & 0 deletions llvm/test/CodeGen/X86/sbb.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -245,3 +245,107 @@ end:
ret void
}

; Cases for PR45700
define i32 @ult_zext_add(i32 %0, i32 %1, i32 %2) {
; CHECK-LABEL: ult_zext_add:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: cmpl %edx, %esi
; CHECK-NEXT: adcl $0, %eax
; CHECK-NEXT: retq
%4 = icmp ult i32 %1, %2
%5 = zext i1 %4 to i32
%6 = add nsw i32 %5, %0
ret i32 %6
}

define i32 @ule_zext_add(i32 %0, i32 %1, i32 %2) {
; CHECK-LABEL: ule_zext_add:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: cmpl %esi, %edx
; CHECK-NEXT: sbbl $-1, %eax
; CHECK-NEXT: retq
%4 = icmp ule i32 %1, %2
%5 = zext i1 %4 to i32
%6 = add nsw i32 %5, %0
ret i32 %6
}

define i32 @ugt_zext_add(i32 %0, i32 %1, i32 %2) {
; CHECK-LABEL: ugt_zext_add:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: cmpl %esi, %edx
; CHECK-NEXT: adcl $0, %eax
; CHECK-NEXT: retq
%4 = icmp ugt i32 %1, %2
%5 = zext i1 %4 to i32
%6 = add nsw i32 %5, %0
ret i32 %6
}

define i32 @uge_zext_add(i32 %0, i32 %1, i32 %2) {
; CHECK-LABEL: uge_zext_add:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: cmpl %edx, %esi
; CHECK-NEXT: sbbl $-1, %eax
; CHECK-NEXT: retq
%4 = icmp uge i32 %1, %2
%5 = zext i1 %4 to i32
%6 = add nsw i32 %5, %0
ret i32 %6
}

define i32 @ult_sext_add(i32 %0, i32 %1, i32 %2) {
; CHECK-LABEL: ult_sext_add:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: cmpl %edx, %esi
; CHECK-NEXT: sbbl $0, %eax
; CHECK-NEXT: retq
%4 = icmp ult i32 %1, %2
%5 = sext i1 %4 to i32
%6 = add nsw i32 %5, %0
ret i32 %6
}

define i32 @ule_sext_add(i32 %0, i32 %1, i32 %2) {
; CHECK-LABEL: ule_sext_add:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: cmpl %esi, %edx
; CHECK-NEXT: adcl $-1, %eax
; CHECK-NEXT: retq
%4 = icmp ule i32 %1, %2
%5 = sext i1 %4 to i32
%6 = add nsw i32 %5, %0
ret i32 %6
}

define i32 @ugt_sext_add(i32 %0, i32 %1, i32 %2) {
; CHECK-LABEL: ugt_sext_add:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: cmpl %esi, %edx
; CHECK-NEXT: sbbl $0, %eax
; CHECK-NEXT: retq
%4 = icmp ugt i32 %1, %2
%5 = sext i1 %4 to i32
%6 = add nsw i32 %5, %0
ret i32 %6
}

define i32 @uge_sext_add(i32 %0, i32 %1, i32 %2) {
; CHECK-LABEL: uge_sext_add:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: cmpl %edx, %esi
; CHECK-NEXT: adcl $-1, %eax
; CHECK-NEXT: retq
%4 = icmp uge i32 %1, %2
%5 = sext i1 %4 to i32
%6 = add nsw i32 %5, %0
ret i32 %6
}
44 changes: 17 additions & 27 deletions llvm/test/CodeGen/X86/scheduler-backtracking.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -700,43 +700,37 @@ define i64 @test4(i64 %a, i64 %b) nounwind {
; ILP-NEXT: movl $0, %edx
; ILP-NEXT: sbbq %rdx, %rdx
; ILP-NEXT: sbbq %rcx, %rcx
; ILP-NEXT: setae %cl
; ILP-NEXT: movzbl %cl, %ecx
; ILP-NEXT: subq %rcx, %rax
; ILP-NEXT: adcq $-1, %rax
; ILP-NEXT: retq
;
; HYBRID-LABEL: test4:
; HYBRID: # %bb.0:
; HYBRID-NEXT: xorl %eax, %eax
; HYBRID-NEXT: xorl %ecx, %ecx
; HYBRID-NEXT: xorl %edx, %edx
; HYBRID-NEXT: incq %rsi
; HYBRID-NEXT: sete %cl
; HYBRID-NEXT: sete %dl
; HYBRID-NEXT: movl $2, %eax
; HYBRID-NEXT: cmpq %rdi, %rsi
; HYBRID-NEXT: sbbq $0, %rcx
; HYBRID-NEXT: movl $0, %ecx
; HYBRID-NEXT: sbbq $0, %rdx
; HYBRID-NEXT: movl $0, %edx
; HYBRID-NEXT: sbbq %rdx, %rdx
; HYBRID-NEXT: sbbq %rcx, %rcx
; HYBRID-NEXT: sbbq %rax, %rax
; HYBRID-NEXT: setae %al
; HYBRID-NEXT: movzbl %al, %ecx
; HYBRID-NEXT: movl $2, %eax
; HYBRID-NEXT: subq %rcx, %rax
; HYBRID-NEXT: adcq $-1, %rax
; HYBRID-NEXT: retq
;
; BURR-LABEL: test4:
; BURR: # %bb.0:
; BURR-NEXT: xorl %eax, %eax
; BURR-NEXT: xorl %ecx, %ecx
; BURR-NEXT: xorl %edx, %edx
; BURR-NEXT: incq %rsi
; BURR-NEXT: sete %cl
; BURR-NEXT: sete %dl
; BURR-NEXT: movl $2, %eax
; BURR-NEXT: cmpq %rdi, %rsi
; BURR-NEXT: sbbq $0, %rcx
; BURR-NEXT: movl $0, %ecx
; BURR-NEXT: sbbq $0, %rdx
; BURR-NEXT: movl $0, %edx
; BURR-NEXT: sbbq %rdx, %rdx
; BURR-NEXT: sbbq %rcx, %rcx
; BURR-NEXT: sbbq %rax, %rax
; BURR-NEXT: setae %al
; BURR-NEXT: movzbl %al, %ecx
; BURR-NEXT: movl $2, %eax
; BURR-NEXT: subq %rcx, %rax
; BURR-NEXT: adcq $-1, %rax
; BURR-NEXT: retq
;
; SRC-LABEL: test4:
Expand All @@ -750,10 +744,8 @@ define i64 @test4(i64 %a, i64 %b) nounwind {
; SRC-NEXT: movl $0, %eax
; SRC-NEXT: sbbq %rax, %rax
; SRC-NEXT: sbbq %rcx, %rcx
; SRC-NEXT: setae %al
; SRC-NEXT: movzbl %al, %ecx
; SRC-NEXT: movl $2, %eax
; SRC-NEXT: subq %rcx, %rax
; SRC-NEXT: adcq $-1, %rax
; SRC-NEXT: retq
;
; LIN-LABEL: test4:
Expand All @@ -768,9 +760,7 @@ define i64 @test4(i64 %a, i64 %b) nounwind {
; LIN-NEXT: movl $0, %edx
; LIN-NEXT: sbbq %rdx, %rdx
; LIN-NEXT: sbbq %rcx, %rcx
; LIN-NEXT: setae %cl
; LIN-NEXT: movzbl %cl, %ecx
; LIN-NEXT: subq %rcx, %rax
; LIN-NEXT: adcq $-1, %rax
; LIN-NEXT: retq
%r = zext i64 %b to i256
%u = add i256 %r, 1
Expand Down
28 changes: 17 additions & 11 deletions llvm/test/CodeGen/X86/select.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -904,29 +904,35 @@ define i32 @test13(i32 %a, i32 %b) nounwind {
}

define i32 @test14(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test14:
; CHECK: ## %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: cmpl %esi, %edi
; CHECK-NEXT: setae %al
; CHECK-NEXT: negl %eax
; CHECK-NEXT: retq
; GENERIC-LABEL: test14:
; GENERIC: ## %bb.0:
; GENERIC-NEXT: xorl %eax, %eax
; GENERIC-NEXT: cmpl %esi, %edi
; GENERIC-NEXT: adcl $-1, %eax
; GENERIC-NEXT: retq
;
; ATOM-LABEL: test14:
; ATOM: ## %bb.0:
; ATOM-NEXT: xorl %eax, %eax
; ATOM-NEXT: cmpl %esi, %edi
; ATOM-NEXT: adcl $-1, %eax
; ATOM-NEXT: nop
; ATOM-NEXT: nop
; ATOM-NEXT: retq
;
; ATHLON-LABEL: test14:
; ATHLON: ## %bb.0:
; ATHLON-NEXT: movl {{[0-9]+}}(%esp), %ecx
; ATHLON-NEXT: xorl %eax, %eax
; ATHLON-NEXT: cmpl {{[0-9]+}}(%esp), %ecx
; ATHLON-NEXT: setae %al
; ATHLON-NEXT: negl %eax
; ATHLON-NEXT: adcl $-1, %eax
; ATHLON-NEXT: retl
;
; MCU-LABEL: test14:
; MCU: # %bb.0:
; MCU-NEXT: xorl %ecx, %ecx
; MCU-NEXT: cmpl %edx, %eax
; MCU-NEXT: setae %cl
; MCU-NEXT: negl %ecx
; MCU-NEXT: adcl $-1, %ecx
; MCU-NEXT: movl %ecx, %eax
; MCU-NEXT: retl
%c = icmp uge i32 %a, %b
Expand Down