88 changes: 88 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_FMI.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=ADD8FI,ADD32FI,ADD8PI,ADD32PI,ADD8JI,ADD32JI

#------------------------------------------------------------------------------
# MxBiArOp_FMI class used for binary arithmetic operations and operates on
# memory and immediate data. It uses MxArithImmEncoding class.
#------------------------------------------------------------------------------


--- # ARII
# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# OPWORD x x x x x x x x | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# ADD8FI: 0 0 0 0 0 1 1 0 . 0 0 1 1 0 0 0 0
# ADD8FI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# ADD8FI-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------------------------------
# ADD8FI-SAME: 0 0 0 0 0 1 1 0 . 0 0 1 1 0 0 1 1
# ADD8FI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ADD8FI-SAME: 1 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1
# -------------------------------+-------------------------------
# ADD32FI-SAME: 0 0 0 0 0 1 1 0 . 1 0 1 1 0 0 1 0
# ADD32FI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ADD32FI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ADD32FI-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 1 1 0 1
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxBiArOp_FMI_ARII
body: |
bb.0:
ADD8fi 0, $a0, $d0, -1, implicit-def $ccr
ADD8fi -1, $a3, $a1, 0, implicit-def $ccr
ADD32fi 13, $a2, $d1, -1, implicit-def $ccr
...
--- # ARID
# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# OPWORD x x x x x x x x | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# ADD8PI-SAME: 0 0 0 0 0 1 1 0 . 0 0 1 0 1 0 0 0
# ADD8PI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# ADD8PI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------------------------------
# ADD8PI-SAME: 0 0 0 0 0 1 1 0 . 0 0 1 0 1 0 1 1
# ADD8PI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ADD8PI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------------------------------
# ADD32PI-SAME: 0 0 0 0 0 1 1 0 . 1 0 1 0 1 0 1 0
# ADD32PI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ADD32PI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ADD32PI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 1 1 0 1
name: MxBiArOp_FMI_ARID
body: |
bb.0:
ADD8pi 0, $a0, -1, implicit-def $ccr
ADD8pi -1, $a3, 0, implicit-def $ccr
ADD32pi 13, $a2, -1, implicit-def $ccr
...
--- # ARI
# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# OPWORD x x x x x x x x | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# ADD8JI-SAME: 0 0 0 0 0 1 1 0 . 0 0 0 1 0 0 0 0
# ADD8JI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# -------------------------------+-------------------------------
# ADD8JI-SAME: 0 0 0 0 0 1 1 0 . 0 0 0 1 0 0 1 1
# ADD8JI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------------------------------
# ADD32JI-SAME: 0 0 0 0 0 1 1 0 . 1 0 0 1 0 0 1 0
# ADD32JI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ADD32JI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
name: MxBiArOp_FMI_ARI
body: |
bb.0:
ADD8ji $a0, -1, implicit-def $ccr
ADD8ji $a3, 0, implicit-def $ccr
ADD32ji $a2, -1, implicit-def $ccr
...
73 changes: 73 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_FMR.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=ADD8FD,ADD32FD,ADD8PD,ADD32PD,ADD8JD,ADD32JD

#------------------------------------------------------------------------------
# MxBiArOp_FMR class used for binary arithmetic operations and operates on
# register and memory; the result is store to memory. It uses MxArithEncoding
# encoding class and MxOpModeEAd opmode class.
#------------------------------------------------------------------------------

--- # ARII
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# ADD8FD: 1 1 0 1 0 0 0 1 . 0 0 1 1 0 0 0 0
# ADD8FD-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# ADD8FD-SAME: 1 1 0 1 0 0 0 1 . 0 0 1 1 0 0 0 0
# ADD8FD-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1
# ---------------------------------------------------------------
# ADD32FD-SAME: 1 1 0 1 0 0 0 1 . 1 0 1 1 0 0 0 1
# ADD32FD-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# ADD32FD-SAME: 1 1 0 1 0 0 1 1 . 1 0 1 1 0 0 1 0
# ADD32FD-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxBiArOp_FMR_ARII
body: |
bb.0:
ADD8fd 0, $a0, $d1, $bd0, implicit-def $ccr
ADD8fd -1, $a0, $d1, $bd0, implicit-def $ccr
ADD32fd 0, $a1, $d1, $d0, implicit-def $ccr
ADD32fd 0, $a2, $a2, $d1, implicit-def $ccr
...
--- # ARID
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# ADD8PD-SAME: 1 1 0 1 0 0 0 1 . 0 0 1 0 1 0 0 0
# ADD8PD-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# ADD32PD-SAME: 1 1 0 1 0 0 0 1 . 1 0 1 0 1 0 0 1
# ADD32PD-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
name: MxBiArOp_FMR_ARID
body: |
bb.0:
ADD8pd 0, $a0, $bd0, implicit-def $ccr
ADD32pd -1, $a1, $d0, implicit-def $ccr
...
--- # ARI
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# ADD8JD-SAME: 1 1 0 1 0 0 0 1 . 0 0 0 1 0 0 0 0
# ---------------------------------------------------------------
# ADD32JD-SAME: 1 1 0 1 0 1 1 1 . 1 0 0 1 0 0 0 1
name: MxBiArOp_FMR_ARI
body: |
bb.0:
ADD8jd $a0, $bd0, implicit-def $ccr
ADD32jd $a1, $d3, implicit-def $ccr
...
41 changes: 41 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRI.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=XOR16DI,XOR32DI

#------------------------------------------------------------------------------
# MxBiArOp_RFRI class used for binary arithmetic operations and operates on
# register and immediate data. It uses MxArithImmEncoding class. This is special
# case for XOR.
#------------------------------------------------------------------------------


# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# x x x x x x x x | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# XOR16DI: 0 0 0 0 1 0 1 0 . 0 1 0 0 0 0 0 0
# XOR16DI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------------------------------
# XOR16DI-SAME: 0 0 0 0 1 0 1 0 . 0 1 0 0 0 0 1 1
# XOR16DI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------------------------------
# XOR32DI-SAME: 0 0 0 0 1 0 1 0 . 1 0 0 0 0 0 0 0
# XOR32DI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# XOR32DI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------------------------------
# XOR32DI-SAME: 0 0 0 0 1 0 1 0 . 1 0 0 0 0 0 0 0
# XOR32DI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1
# XOR32DI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------------------------------
# XOR32DI-SAME: 0 0 0 0 1 0 1 0 . 1 0 0 0 0 1 1 1
# XOR32DI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 1 1 1
# XOR32DI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
name: MxBiArOp_RFRI
body: |
bb.0:
$wd0 = XOR16di $wd0, 0, implicit-def $ccr
$wd3 = XOR16di $wd3, -1, implicit-def $ccr
$d0 = XOR32di $d0, -1, implicit-def $ccr
$d0 = XOR32di $d0, 131071, implicit-def $ccr
$d7 = XOR32di $d7, 458752, implicit-def $ccr
45 changes: 45 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRI_xEA.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=ADD16DI,ADD32RI

#------------------------------------------------------------------------------
# MxBiArOp_RFRI_xEA class used for binary arithmetic operations and operates on
# register and immediate data. It uses MxArithEncoding(yes for immediates) class
# and either MxOpModeNdEA or MxOpmodeNrEA opmode classes.
#------------------------------------------------------------------------------


# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# x x x x | REG | OPMODE | MODE | REG
# ADD16DI: 1 1 0 1 0 0 0 0 . 0 1 1 1 1 1 0 0
# ADD16DI: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------+-----------+-----------+-----------+-----------
# ADD16DI-SAME: 1 1 0 1 0 1 1 0 . 0 1 1 1 1 1 0 0
# ADD16DI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ---------------+-----------+-----------+-----------+-----------
# ADD32RI-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 1 1 1 0 0
# ADD32RI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ADD32RI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ---------------+-----------+-----------+-----------+-----------
# ADD32RI-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 1 1 1 0 0
# ADD32RI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1
# ADD32RI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ---------------+-----------+-----------+-----------+-----------
# ADD32RI-SAME: 1 1 0 1 1 1 1 0 . 1 0 1 1 1 1 0 0
# ADD32RI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 1 1 1
# ADD32RI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------+-----------+-----------+-----------+-----------
# ADD32RI-SAME: 1 1 0 1 0 0 0 1 . 1 1 1 1 1 1 0 0
# ADD32RI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ADD32RI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
name: MxBiArOp_RFRI_xEA
body: |
bb.0:
$wd0 = ADD16di $wd0, 0, implicit-def $ccr
$wd3 = ADD16di $wd3, -1, implicit-def $ccr
$d0 = ADD32ri $d0, -1, implicit-def $ccr
$d0 = ADD32ri $d0, 131071, implicit-def $ccr
$d7 = ADD32ri $d7, 458752, implicit-def $ccr
$a0 = ADD32ri $a0, 0, implicit-def $ccr
123 changes: 123 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRM.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=ADD8DK,ADD32RK,ADD8DQ,ADD32RQ,ADD8DF,ADD32RF
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=ADD8DP,ADD32RP,ADD8DJ,ADD32RJ

#------------------------------------------------------------------------------
# MxBiArOp_RFRM class used for binary arithmetic operations and operates on
# register and memory. It uses MxArithEncoding encoding class and either
# MxOpModeNdEA or MxOpModeNrEA opmode classes.
#------------------------------------------------------------------------------

--- # PCI
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# ADD8DK: 1 1 0 1 0 0 0 0 . 0 0 1 1 1 0 1 1
# ADD8DK-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# ADD8DK-SAME: 1 1 0 1 0 0 0 0 . 0 0 1 1 1 0 1 1
# ADD8DK-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1
# ---------------------------------------------------------------
# ADD32RK-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 1 1 0 1 1
# ADD32RK-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# ADD32RK-SAME: 1 1 0 1 0 0 1 1 . 1 1 1 1 1 0 1 1
# ADD32RK-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxBiArOp_RFRM_PCI
body: |
bb.0:
$bd0 = ADD8dk $bd0, 0, $d1, implicit-def $ccr
$bd0 = ADD8dk $bd0, -1, $d1, implicit-def $ccr
$d0 = ADD32rk $d0, 0, $d1, implicit-def $ccr
$a1 = ADD32rk $a1, 0, $a2, implicit-def $ccr
...
--- # PCD
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# ADD8DQ-SAME: 1 1 0 1 0 0 0 0 . 0 0 1 1 1 0 1 0
# ADD8DQ-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# ADD32RQ-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 1 1 0 1 0
# ADD32RQ-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
name: MxBiArOp_RFRM_PCD
body: |
bb.0:
$bd0 = ADD8dq $bd0, 0, implicit-def $ccr
$d0 = ADD32rq $d0, -1, implicit-def $ccr
...
--- # ARII
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# ADD8DF-SAME: 1 1 0 1 0 0 0 0 . 0 0 1 1 0 0 0 0
# ADD8DF-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# ADD8DF-SAME: 1 1 0 1 0 0 0 0 . 0 0 1 1 0 0 0 0
# ADD8DF-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1
# ---------------------------------------------------------------
# ADD32RF-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 1 0 0 0 1
# ADD32RF-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# ADD32RF-SAME: 1 1 0 1 0 0 1 1 . 1 1 1 1 0 0 1 0
# ADD32RF-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxBiArOp_RFRM_ARII
body: |
bb.0:
$bd0 = ADD8df $bd0, 0, $a0, $d1, implicit-def $ccr
$bd0 = ADD8df $bd0, -1, $a0, $d1, implicit-def $ccr
$d0 = ADD32rf $d0, 0, $a1, $d1, implicit-def $ccr
$a1 = ADD32rf $a1, 0, $a2, $a2, implicit-def $ccr
...
--- # ARID
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# ADD8DP: 1 1 0 1 0 0 0 0 . 0 0 1 0 1 0 0 0
# ADD8DP-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# ADD32RP-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 0 1 0 0 1
# ADD32RP-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
name: MxBiArOp_RFRM_ARID
body: |
bb.0:
$bd0 = ADD8dp $bd0, 0, $a0, implicit-def $ccr
$d0 = ADD32rp $d0, -1, $a1, implicit-def $ccr
...
--- # ARI
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# ADD8DJ-SAME: 1 1 0 1 0 0 0 0 . 0 0 0 1 0 0 0 0
# ---------------------------------------------------------------
# ADD32RJ-SAME: 1 1 0 1 0 1 1 1 . 1 1 0 1 0 0 0 1
name: MxBiArOp_RFRM_ARI
body: |
bb.0:
$bd0 = ADD8dj $bd0, $a0, implicit-def $ccr
$a3 = ADD32rj $a3, $a1, implicit-def $ccr
...
27 changes: 27 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRRF.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=ADDX16DD,ADDX32DD

#------------------------------------------------------------------------------
# MxBiArOp_RFRRF class used for carry-aware binary arithmetic operations and
# operates on both data and address registers only. It uses MxArithXEncoding
# encoding class and either MxOpModeNdEA or MxOpModeNrEA opmode classes.
#------------------------------------------------------------------------------


# ---------------------------------------------------------------
# F E D C | B A 9 | 8 | 7 6 | 5 4 | 3 | 2 1 0
# ---------------+-----------+---+-------+-------+---+-----------
# x x x x | REG Rx | 1 | SIZE | 0 0 | M | REG Ry
# ---------------+-----------+---+-------+-------+---+-----------
# ADDX16DD: 1 1 0 1 0 0 0 1 . 0 1 0 0 0 0 0 1
# ADDX16DD-SAME: 1 1 0 1 0 1 1 1 . 0 1 0 0 0 0 1 0
# ADDX32DD-SAME: 1 1 0 1 0 0 0 1 . 1 0 0 0 0 0 0 1
# ADDX32DD-SAME: 1 1 0 1 1 1 1 1 . 1 0 0 0 0 0 0 1
name: MxBiArOp_RFRRF
body: |
bb.0:
$wd0 = ADDX16dd $wd0, $wd1, implicit $ccr, implicit-def $ccr
$wd3 = ADDX16dd $wd3, $wd2, implicit $ccr, implicit-def $ccr
$d0 = ADDX32dd $d0, $d1, implicit $ccr, implicit-def $ccr
$d7 = ADDX32dd $d7, $d1, implicit $ccr, implicit-def $ccr
26 changes: 26 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRR_EAd.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=XOR16DD,XOR32DD

#------------------------------------------------------------------------------
# MxBiArOp_RFRR_EAd class used for binary arithmetic operations and operates on
# both data and address registers only. It uses MxArithEncoding encoding class
# and MxOpModeEAd opmode class. This is a special case for XOR(EOR).
#------------------------------------------------------------------------------


# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# x x x x | REG | OPMODE | MODE | REG
# XOR16DD: 1 0 1 1 0 0 1 1 . 0 1 0 0 0 0 0 0
# XOR16DD-SAME: 1 0 1 1 0 1 0 1 . 0 1 0 0 0 0 1 1
# XOR32DD-SAME: 1 0 1 1 0 0 1 1 . 1 0 0 0 0 0 0 0
# XOR32DD-SAME: 1 0 1 1 0 0 1 1 . 1 0 0 0 0 1 1 1
name: MxBiArOp_RFRR_EAd
body: |
bb.0:
$wd0 = XOR16dd $wd0, $wd1, implicit-def $ccr
$wd3 = XOR16dd $wd3, $wd2, implicit-def $ccr
$d0 = XOR32dd $d0, $d1, implicit-def $ccr
$d7 = XOR32dd $d7, $d1, implicit-def $ccr
30 changes: 30 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxBiArOp_RFRR_xEA.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=ADD16DD,ADD32RR

#------------------------------------------------------------------------------
# MxBiArOp_RFRR_xEA class used for binary arithmetic operations and operates on
# both data and address registers only. It uses MxArithEncoding encoding class
# and either MxOpModeNdEA or MxOpmodeNrEA opmode classes.
#------------------------------------------------------------------------------


# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# x x x x | REG | OPMODE | MODE | REG
# ADD16DD: 1 1 0 1 0 0 0 0 . 0 1 0 0 0 0 0 1
# ADD16DD-SAME: 1 1 0 1 0 1 1 0 . 0 1 0 0 0 0 1 0
# ADD32RR-SAME: 1 1 0 1 0 0 0 0 . 1 0 0 0 0 0 0 1
# ADD32RR-SAME: 1 1 0 1 0 0 0 0 . 1 0 0 0 1 0 0 1
# ADD32RR-SAME: 1 1 0 1 1 1 1 0 . 1 0 0 0 1 0 0 1
# ADD32RR-SAME: 1 1 0 1 0 0 0 1 . 1 1 0 0 0 0 0 1
name: MxBiArOp_RFRR_xEA
body: |
bb.0:
$wd0 = ADD16dd $wd0, $wd1, implicit-def $ccr
$wd3 = ADD16dd $wd3, $wd2, implicit-def $ccr
$d0 = ADD32rr $d0, $d1, implicit-def $ccr
$d0 = ADD32rr $d0, $a1, implicit-def $ccr
$d7 = ADD32rr $d7, $a1, implicit-def $ccr
$a0 = ADD32rr $a0, $d1, implicit-def $ccr
44 changes: 44 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_BI.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=CMP8BI,CMP32BI

#------------------------------------------------------------------------------
# MxCMP_BI class used for compare operations and operates on absolute memory
# locations and immediate data. It uses MxArithImmEncoding encoding class.
# NOTE: CMP is calculated by subtracting LHS(Imm) from RHS(ABS)
#------------------------------------------------------------------------------


# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# CMP8BI: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 0 1
# CMP8BI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP8BI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP8BI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# CMP8BI-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 0 1
# CMP8BI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# CMP8BI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP8BI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP32BI-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 0 1
# CMP32BI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32BI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32BI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP32BI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP32BI-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 0 1
# CMP32BI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP32BI-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
# CMP32BI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32BI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
name: MxCMP_BI
body: |
bb.0:
CMP8bi 0, -1, implicit-def $ccr
CMP8bi -1, 0, implicit-def $ccr
CMP32bi -1, 0, implicit-def $ccr
CMP32bi 42, -1, implicit-def $ccr
174 changes: 174 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_MI.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=CMP8KI,CMP32KI,CMP8QI,CMP32QI,CMP8FI,CMP32FI
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=CMP8PI,CMP32PI,CMP8JI,CMP32JI

#------------------------------------------------------------------------------
# MxCMP_MI class used for compare operations and operates on memory data and
# immediate data. It uses MxArithImmEncoding encoding class.
# NOTE: CMP is calculated by subtracting LHS(Imm) from RHS(Mem)
#------------------------------------------------------------------------------


--- # PCI
# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# CMP8KI: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 1 1
# CMP8KI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP8KI-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# CMP8KI-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 1 1
# CMP8KI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# CMP8KI-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP32KI-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 1 1
# CMP32KI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32KI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32KI-SAME: 0 1 1 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP32KI-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 1 1
# CMP32KI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP32KI-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
# CMP32KI-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxCMP_MI_PCI
body: |
bb.0:
CMP8ki 0, -1, $d1, implicit-def $ccr
CMP8ki -1, 0, $d0, implicit-def $ccr
CMP32ki -1, 0, $d7, implicit-def $ccr
CMP32ki 42, -1, $d1, implicit-def $ccr
...
--- # PCD
# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# CMP8QI-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 1 0
# CMP8QI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP8QI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP8QI-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 1 0
# CMP8QI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# CMP8QI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# CMP32QI-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 1 0
# CMP32QI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32QI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32QI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP32QI-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 1 0
# CMP32QI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP32QI-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
# CMP32QI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
name: MxCMP_MI_PCD
body: |
bb.0:
CMP8qi 0, 0, implicit-def $ccr
CMP8qi -1, -1, implicit-def $ccr
CMP32qi -1, 0, implicit-def $ccr
CMP32qi 42, 0, implicit-def $ccr
...
--- # ARII
# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# CMP8FI-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 0 0 0 1
# CMP8FI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP8FI-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# CMP8FI-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 0 0 0 0
# CMP8FI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# CMP8FI-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP32FI-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 0 1 1 0
# CMP32FI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32FI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32FI-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP32FI-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 0 0 0 1
# CMP32FI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP32FI-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
# CMP32FI-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxCMP_MI_ARII
body: |
bb.0:
CMP8fi 0, -1, $a1, $a0, implicit-def $ccr
CMP8fi -1, 0, $a0, $a0, implicit-def $ccr
CMP32fi -1, 0, $a6, $a0, implicit-def $ccr
CMP32fi 42, -1, $a1, $a0, implicit-def $ccr
...
--- # ARID
# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# CMP8PI: 0 0 0 0 1 1 0 0 . 0 0 1 0 1 0 0 1
# CMP8PI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP8PI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# CMP8PI-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 0 1 0 0 0
# CMP8PI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# CMP8PI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP32PI-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 0 1 1 1 0
# CMP32PI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32PI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CMP32PI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP32PI-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 0 1 0 0 1
# CMP32PI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP32PI-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
# CMP32PI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
name: MxCMP_MI_ARID
body: |
bb.0:
CMP8pi 0, -1, $a1, implicit-def $ccr
CMP8pi -1, 0, $a0, implicit-def $ccr
CMP32pi -1, 0, $a6, implicit-def $ccr
CMP32pi 42, -1, $a1, implicit-def $ccr
...
--- # ARI
# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# CMP8JI-SAME: 0 0 0 0 1 1 0 0 . 0 0 0 1 0 0 0 1
# CMP8JI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP8JI-SAME: 0 0 0 0 1 1 0 0 . 0 0 0 1 0 0 0 0
# CMP8JI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# CMP32JI-SAME: 0 0 0 0 1 1 0 0 . 1 0 0 1 0 1 1 0
# CMP32JI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# CMP32JI-SAME: 0 0 0 0 1 1 0 0 . 1 0 0 1 0 0 0 1
# CMP32JI-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
name: MxCMP_MI_ARI
body: |
bb.0:
CMP8ji 0, $a1, implicit-def $ccr
CMP8ji -1, $a0, implicit-def $ccr
CMP32ji -1, $a6, implicit-def $ccr
CMP32ji 42, $a1, implicit-def $ccr
...
36 changes: 36 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_RI.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=CMP8DI,CMP32DI

#------------------------------------------------------------------------------
# MxCMP_RI class used for compare operations and operates on data registers and
# immediate data. It uses MxArithImmEncoding encoding class.
# NOTE: CMP is calculated by subtracting LHS(Imm) from RHS(Dn)
#------------------------------------------------------------------------------


# -------------------------------+-------+-----------+-----------
# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# -------------------------------+-------+-----------+-----------
# 0 0 0 0 1 1 0 0 | SIZE | MODE | REG
# -------------------------------+-------+-----------+-----------
# CMP8DI: 0 0 0 0 1 1 0 0 . 0 0 0 0 0 0 0 1
# CMP8DI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# CMP8DI-SAME: 0 0 0 0 1 1 0 0 . 0 0 0 0 0 0 0 0
# CMP8DI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# CMP32DI-SAME: 0 0 0 0 1 1 0 0 . 1 0 0 0 0 1 1 1
# CMP32DI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP32DI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 1 1 0 1
# -------------------------------+-------+-----------+-----------
# CMP32DI-SAME: 0 0 0 0 1 1 0 0 . 1 0 0 0 0 0 0 1
# CMP32DI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CMP32DI-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
name: MxCMP_RI
body: |
bb.0:
CMP8di 0, $bd1, implicit-def $ccr
CMP8di -1, $bd0, implicit-def $ccr
CMP32di 13, $d7, implicit-def $ccr
CMP32di 42, $d1, implicit-def $ccr
125 changes: 125 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_RM.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=CMP8DF,CMP32DF
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=CMP8DP,CMP32DP,CMP8DJ,CMP32DJ

#------------------------------------------------------------------------------
# MxCMP_RM class used for compare operations and operates on memory data and
# register. It uses MxArithEncoding encoding class.
# NOTE: CMP is calculated by subtracting LHS(Mem) from RHS(Reg)
#------------------------------------------------------------------------------

--- # PCI
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# CMP8DK: 1 0 1 1 0 0 0 0 . 0 0 1 1 1 0 1 1
# CMP8DK-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# CMP8DK-SAME: 1 0 1 1 0 0 0 0 . 0 0 1 1 1 0 1 1
# CMP8DK-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# CMP32DK-SAME: 1 0 1 1 0 0 0 0 . 1 0 1 1 1 0 1 1
# CMP32DK-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
#
# NOTE Immediates for pc-rel instructions use relocations and addendum is encoded
# inside the relocation record thus there are 0s instead of the value.
name: MxBiArOp_RFRM_PCI
body: |
bb.0:
CMP8dk $bd0, 0, $d1, implicit-def $ccr
CMP8dk $bd0, -1, $d1, implicit-def $ccr
CMP32dk $d0, 0, $d1, implicit-def $ccr
...
--- # PCD
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# CMP8DQ-SAME: 1 0 1 1 0 0 0 0 . 0 0 1 1 1 0 1 0
# CMP8DQ-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# CMP32DQ-SAME: 1 0 1 1 0 0 0 0 . 1 0 1 1 1 0 1 0
# CMP32DQ-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
#
# NOTE Immediates for pc-rel instructions use relocations and addendum is encoded
# inside the relocation record thus there are 0s instead of the value.
name: MxBiArOp_RFRM_PCD
body: |
bb.0:
CMP8dq $bd0, 0, implicit-def $ccr
CMP32dq $d0, -1, implicit-def $ccr
...
--- # ARII
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# CMP8DF: 1 0 1 1 0 0 0 0 . 0 0 1 1 0 0 0 0
# CMP8DF-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# CMP8DF-SAME: 1 0 1 1 0 0 0 0 . 0 0 1 1 0 0 0 0
# CMP8DF-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1
# ---------------------------------------------------------------
# CMP32DF-SAME: 1 0 1 1 0 0 0 0 . 1 0 1 1 0 0 0 1
# CMP32DF-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# CMP32DF-SAME: 1 0 1 1 0 0 1 0 . 1 0 1 1 0 0 1 0
# CMP32DF-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxCMP_RM_ARII
body: |
bb.0:
CMP8df $bd0, 0, $a0, $d1, implicit-def $ccr
CMP8df $bd0, -1, $a0, $d1, implicit-def $ccr
CMP32df $d0, 0, $a1, $d1, implicit-def $ccr
CMP32df $d1, 0, $a2, $a2, implicit-def $ccr
...
--- # ARID
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# CMP8DP: 1 0 1 1 0 0 0 0 . 0 0 1 0 1 0 0 0
# CMP8DP-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# CMP32DP-SAME: 1 0 1 1 0 0 0 0 . 1 0 1 0 1 0 0 1
# CMP32DP-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
name: MxCMP_RM_ARID
body: |
bb.0:
CMP8dp $bd0, 0, $a0, implicit-def $ccr
CMP32dp $d0, -1, $a1, implicit-def $ccr
...
--- # ARI
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# OPWORD x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# CMP8DJ-SAME: 1 0 1 1 0 0 0 0 . 0 0 0 1 0 0 0 0
# ---------------------------------------------------------------
# CMP32DJ-SAME: 1 0 1 1 0 1 1 0 . 1 0 0 1 0 0 0 1
name: MxCMP_RM_ARI
body: |
bb.0:
CMP8dj $bd0, $a0, implicit-def $ccr
CMP32dj $d3, $a1, implicit-def $ccr
...
27 changes: 27 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxCMP_RR.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=CMP8DD,CMP32DD

#------------------------------------------------------------------------------
# MxCMP_RR class used for compare operations and operates on data registers only.
# It uses MxArithEncoding encoding class and MxOpModeNdEA opmode class.
# NOTE: CMP is calculated by subtracting LHS(EA) from RHS(Dn)
#------------------------------------------------------------------------------


# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# x x x x | REG | OPMODE | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# CMP8DD: 1 0 1 1 0 0 1 0 . 0 0 0 0 0 0 0 0
# CMP8DD-SAME: 1 0 1 1 0 1 0 0 . 0 0 0 0 0 0 1 1
# CMP32DD-SAME: 1 0 1 1 0 0 1 0 . 1 0 0 0 0 0 0 0
# CMP32DD-SAME: 1 0 1 1 0 0 1 0 . 1 0 0 0 0 1 1 1
name: MxCMP_RR
body: |
bb.0:
CMP8dd $bd0, $bd1, implicit-def $ccr
CMP8dd $bd3, $bd2, implicit-def $ccr
CMP32dd $d0, $d1, implicit-def $ccr
CMP32dd $d7, $d1, implicit-def $ccr
48 changes: 48 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxDiMu.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=SDIVD32D16,UDIVD32D16,SMULD32D16,UMULD32D16
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=SDIVD32I16,UDIVD32I16,SMULD32I16,UMULD32I16

#------------------------------------------------------------------------------
# MxDiMu is used for sign/unsigned division/multiply of word size data
#------------------------------------------------------------------------------


# ---------------------------------------------------------------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------------------------------
# x x x x | REG | OPMODE | MODE | REG
# ---------------------------------------------------------------
# SDIVD32D16: 1 0 0 0 0 0 0 1 . 1 1 0 0 0 0 0 1
# ---------------------------------------------------------------
# UDIVD32D16-SAME: 1 0 0 0 0 0 0 0 . 1 1 0 0 0 0 0 1
# ---------------------------------------------------------------
# SDIVD32I16: 1 0 0 0 0 0 0 1 . 1 1 1 1 1 1 0 0
# SDIVD32I16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# UDIVD32I16-SAME: 1 0 0 0 0 0 0 0 . 1 1 1 1 1 1 0 0
# UDIVD32I16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ---------------------------------------------------------------
# SMULD32D16-SAME: 1 1 0 0 0 0 0 1 . 1 1 0 0 0 0 0 1
# ---------------------------------------------------------------
# UMULD32D16-SAME: 1 1 0 0 0 0 0 0 . 1 1 0 0 0 0 0 1
# ---------------------------------------------------------------
# SMULD32I16-SAME: 1 1 0 0 0 0 0 1 . 1 1 1 1 1 1 0 0
# SMULD32I16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# UMULD32I16-SAME: 1 1 0 0 0 0 0 0 . 1 1 1 1 1 1 0 0
# UMULD32I16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ---------------------------------------------------------------
name: MxDiMu
body: |
bb.0:
$d0 = SDIVd32d16 $d0, $wd1, implicit-def $ccr
$d0 = UDIVd32d16 $d0, $wd1, implicit-def $ccr
$d0 = SDIVd32i16 $d0, 0, implicit-def $ccr
$d0 = UDIVd32i16 $d0, -1, implicit-def $ccr
$d0 = SMULd32d16 $d0, $wd1, implicit-def $ccr
$d0 = UMULd32d16 $d0, $wd1, implicit-def $ccr
$d0 = SMULd32i16 $d0, 0, implicit-def $ccr
$d0 = UMULd32i16 $d0, -1, implicit-def $ccr
25 changes: 25 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxExt.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=EXT16,EXT32

#------------------------------------------------------------------------------
# MxExt sign extends data inside a register
#------------------------------------------------------------------------------


# ---------------------------------------------------------------
# F E D C B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------------------------------
# 0 1 0 0 1 0 0 | OPMODE | 0 0 0 | REG
# ---------------------------------------------------------------
# EXT16: 0 1 0 0 1 0 0 0 . 1 0 0 0 0 0 0 0
# EXT16-SAME: 0 1 0 0 1 0 0 0 . 1 0 0 0 0 0 1 1
# EXT32-SAME: 0 1 0 0 1 0 0 0 . 1 1 0 0 0 0 0 0
# EXT32-SAME: 0 1 0 0 1 0 0 0 . 1 1 0 0 0 1 1 1
name: MxEXT
body: |
bb.0:
$wd0 = EXT16 $wd0, implicit-def $ccr
$wd3 = EXT16 $wd3, implicit-def $ccr
$d0 = EXT32 $d0, implicit-def $ccr
$d7 = EXT32 $d7, implicit-def $ccr
39 changes: 39 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Arith/Classes/MxNEG.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=NEG8D,NEG32D,NEGX8D,NEGX32D

#------------------------------------------------------------------------------
# MxNEG is used to negate a number
#------------------------------------------------------------------------------


--- # NEG
# ---------------+---------------+-------+-----------+-----------
# F E D C | B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# ---------------+---------------+-------+-----------------------
# 0 1 0 0 | x x x x | SIZE | MODE | REG
# ---------------+---------------+-------+-----------+-----------
# NEG8D: 0 1 0 0 0 1 0 0 . 0 0 0 0 0 0 0 0
# NEG32D-SAME: 0 1 0 0 0 1 0 0 . 1 0 0 0 0 0 0 0
name: MxNEG
body: |
bb.0:
$bd0 = NEG8d $bd0, implicit-def $ccr
$d0 = NEG32d $d0, implicit-def $ccr
...
--- # NEGX
# ---------------+---------------+-------+-----------+-----------
# F E D C | B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# ---------------+---------------+-------+-----------------------
# 0 1 0 0 | x x x x | SIZE | MODE | REG
# ---------------+---------------+-------+-----------+-----------
# NEGX8D-SAME: 0 1 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# NEGX32D-SAME: 0 1 0 0 0 0 0 0 . 1 0 0 0 0 0 0 0
name: MxNEGX
body: |
bb.0:
$bd0 = NEGX8d $bd0, implicit $ccr, implicit-def $ccr
$d0 = NEGX32d $d0, implicit $ccr, implicit-def $ccr
...
115 changes: 115 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Bits/Classes/MxBTST_MI.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=BTST8KI,BTST8QI,BTST8FI,BTST8PI,BTST8JI

#------------------------------------------------------------------------------
# MxBTST_MI class used for BTST operations, the source is locate in memory and
# the bit number is immediate value. This instruciton can only operate on 8 bits.
#------------------------------------------------------------------------------


--- # PCI
# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------+-----------+-----------
# 0 0 0 0 1 0 0 0 0 0 | MODE | REG
# ---------------------------------------+-----------+-----------
# BTST8KI: 0 0 0 0 1 0 0 0 . 0 0 1 1 1 0 1 1
# BTST8KI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# BTST8KI-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# BTST8KI-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 1 1 0 1 1
# BTST8KI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1
# BTST8KI-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxBTST_MI_PCI
body: |
bb.0:
BTST8ki -1, $d1, 0, implicit-def $ccr
BTST8ki 0, $d0, 1, implicit-def $ccr
...
--- # PCD
# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------+-----------+-----------
# 0 0 0 0 1 0 0 0 0 0 | MODE | REG
# ---------------------------------------+-----------+-----------
# BTST8QI-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 1 1 0 1 0
# BTST8QI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# BTST8QI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# BTST8QI-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 1 1 0 1 0
# BTST8QI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# BTST8QI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
name: MxBTST_MI_PCD
body: |
bb.0:
BTST8qi 0, 0, implicit-def $ccr
BTST8qi -1, -1, implicit-def $ccr
...
--- # ARII
# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------+-----------+-----------
# 0 0 0 0 1 0 0 0 0 0 | MODE | REG
# ---------------------------------------+-----------+-----------
# BTST8FI-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 1 0 0 0 1
# BTST8FI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# BTST8FI-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# BTST8FI-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 1 0 0 0 0
# BTST8FI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# BTST8FI-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxBTST_MI_ARII
body: |
bb.0:
BTST8fi -1, $a1, $a0, 0, implicit-def $ccr
BTST8fi 0, $a0, $a0, -1, implicit-def $ccr
...
--- # ARID
# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------+-----------+-----------
# 0 0 0 0 1 0 0 0 0 0 | MODE | REG
# ---------------------------------------+-----------+-----------
# BTST8PI-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 0 1 0 0 1
# BTST8PI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# BTST8PI-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# BTST8PI-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 0 1 0 0 0
# BTST8PI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
# BTST8PI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
name: MxBTST_MI_ARID
body: |
bb.0:
BTST8pi -1, $a1, 0, implicit-def $ccr
BTST8pi 0, $a0, -1, implicit-def $ccr
...
--- # ARI
# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------+-----------+-----------
# 0 0 0 0 1 0 0 0 0 0 | MODE | REG
# ---------------------------------------+-----------+-----------
# BTST8JI-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 1 0 0 0 1
# BTST8JI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# BTST8JI-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 1 0 0 0 0
# BTST8JI-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1
name: MxBTST_MI_ARI
body: |
bb.0:
BTST8ji $a1, 0, implicit-def $ccr
BTST8ji $a0, -1, implicit-def $ccr
...
104 changes: 104 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Bits/Classes/MxBTST_MR.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=BTST8KD,BTST8QD,BTST8FD,BTST8PD,BTST8JD

#------------------------------------------------------------------------------
# MxBTST_MR class used for BTST operations, the source is locate in memory and
# the bit number is in register. This instruciton can only operate on 8 bits.
#------------------------------------------------------------------------------


--- # PCI
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# 0 0 0 0 | REG | 1 0 0 | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# BTST8KD: 0 0 0 0 0 0 0 1 . 0 0 1 1 1 0 1 1
# BTST8KD-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# BTST8KD-SAME: 0 0 0 0 0 0 1 1 . 0 0 1 1 1 0 1 1
# BTST8KD-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxBTST_MR_PCI
body: |
bb.0:
BTST8kd -1, $d1, $bd0, implicit-def $ccr
BTST8kd 0, $d0, $bd1, implicit-def $ccr
...
--- # PCD
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# 0 0 0 0 | REG | 1 0 0 | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# BTST8QD-SAME: 0 0 0 0 0 0 0 1 . 0 0 1 1 1 0 1 0
# BTST8QD-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------+-----------+-----------
# BTST8QD-SAME: 0 0 0 0 0 0 1 1 . 0 0 1 1 1 0 1 0
# BTST8QD-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
name: MxBTST_MR_PCD
body: |
bb.0:
BTST8qd 0, $bd0, implicit-def $ccr
BTST8qd -1, $bd1, implicit-def $ccr
...
--- # ARII
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# 0 0 0 0 | REG | 1 0 0 | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# BTST8FD-SAME: 0 0 0 0 0 0 0 1 . 0 0 1 1 0 0 0 1
# BTST8FD-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# BTST8FD-SAME: 0 0 0 0 0 0 1 1 . 0 0 1 1 0 0 0 0
# BTST8FD-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxBTST_MR_ARII
body: |
bb.0:
BTST8fd -1, $a1, $a0, $bd0, implicit-def $ccr
BTST8fd 0, $a0, $a0, $bd1, implicit-def $ccr
...
--- # ARID
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# 0 0 0 0 | REG | 1 0 0 | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# BTST8PD-SAME: 0 0 0 0 0 0 0 1 . 0 0 1 0 1 0 0 1
# BTST8PD-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# -------------------------------+-------+-----------+-----------
# BTST8PD-SAME: 0 0 0 0 0 0 1 1 . 0 0 1 0 1 0 0 0
# BTST8PD-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
name: MxBTST_MR_ARID
body: |
bb.0:
BTST8pd -1, $a1, $bd0, implicit-def $ccr
BTST8pd 0, $a0, $bd1, implicit-def $ccr
...
--- # ARI
# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# 0 0 0 0 | REG | 1 0 0 | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# BTST8JD-SAME: 0 0 0 0 0 0 0 1 . 0 0 0 1 0 0 0 1
# BTST8JD-SAME: 0 0 0 0 0 0 1 1 . 0 0 0 1 0 0 0 0
name: MxBTST_MR_ARI
body: |
bb.0:
BTST8jd $a1, $bd0, implicit-def $ccr
BTST8jd $a0, $bd1, implicit-def $ccr
...
25 changes: 25 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Bits/Classes/MxBTST_RI.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=BTST32DI

#------------------------------------------------------------------------------
# MxBTST_RI class used for BTST operations, the source is in a data register and
# the bit number is a immediate. This instruction can only operate on 32 bits
#------------------------------------------------------------------------------


# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------------------+-----------
# 0 0 0 0 1 0 0 0 0 0 | MODE | REG
# ---------------------------------------+-----------+-----------
# BTST32DI: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# BTST32DI: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1
# ---------------------------------------------------------------
# BTST32DI: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 1 1
# BTST32DI: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
name: MxBTST_RI
body: |
bb.0:
BTST32di $d0, 1, implicit-def $ccr
BTST32di $d3, 0, implicit-def $ccr
22 changes: 22 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Bits/Classes/MxBTST_RR.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=BTST32DD

#------------------------------------------------------------------------------
# MxBTST_RR class used for BTST operations, where both the source and bit number
# are in registers. This instruction can only operate on 32 bits
#------------------------------------------------------------------------------


# ---------------+-----------+-----------+-----------+-----------
# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0
# ---------------+-----------+-----------+-----------+-----------
# 0 0 0 0 | REG | 1 0 0 | MODE | REG
# ---------------+-----------+-----------+-----------+-----------
# BTST32DD: 0 0 0 0 0 0 1 1 . 0 0 0 0 0 0 0 0
# BTST32DD: 0 0 0 0 0 0 0 1 . 0 0 0 0 0 0 1 1
name: MxBTST_RR
body: |
bb.0:
BTST32dd $d0, $d1, implicit-def $ccr
BTST32dd $d3, $d0, implicit-def $ccr
49 changes: 49 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBRA.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=BRA8,BRA16

#------------------------------------------------------------------------------
# MxBRA unconditionally branches somewhere
#------------------------------------------------------------------------------

--- # MxBRA8
# -------------------------------+-------------------------------
# F E D C B A 9 8 | 7 6 5 4 3 2 1 0
# -------------------------------+-------------------------------
# 0 1 1 0 0 0 0 0 | 8-BIT DISPLACEMENT
# -------------------------------+-------------------------------
# BRA8: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 1
# BRA8-SAME: 0 1 1 0 0 0 0 0 . 0 0 1 0 1 0 1 0
#
# NOTE MxBRA branches cannot encode 0 displacement, 0 in displacement instructs
# to use additional word. Also it cannot encode -1 since all 1s instruct to use
# two additional words to encode 32bit offset(since M68020).
name: MxBRA8
body: |
bb.0:
BRA8 1, implicit $ccr
BRA8 42, implicit $ccr
...
--- # MxBRA16
# -------------------------------+-------------------------------
# F E D C B A 9 8 | 7 6 5 4 3 2 1 0
# -------------------------------+-------------------------------
# 0 1 1 0 0 0 0 0 | 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# BRA16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# -------------------------------+-------------------------------
# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# BRA16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ---------------------------------------------------------------
# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# BRA16-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
name: MxBRA16
body: |
bb.0:
BRA16 0, implicit $ccr
BRA16 -1, implicit $ccr
BRA16 42, implicit $ccr
...
126 changes: 126 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBcc.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=BCC8,BLS8,BLT8,BEQ8,BMI8,BNE8,BGE8,BCS8,BPL8
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=BPL8,BGT8,BHI8,BVC8,BLE8,BVS8,BCC16,BLS16
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=BLT16,BEQ16,BMI16,BNE16,BGE16,BCS16,BPL16
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=BGT16,BHI16,BVC16,BLE16,BVS16

#------------------------------------------------------------------------------
# MxScc branches if the condition is True
#------------------------------------------------------------------------------

--- # MxBcc8
# ---------------+---------------+-------------------------------
# F E D C | B A 9 8 | 7 6 5 4 3 2 1 0
# ---------------+---------------+-------------------------------
# 0 1 1 0 | CONDITION | 8-BIT DISPLACEMENT
# ---------------+---------------+-------------------------------
# BHI8: 0 1 1 0 0 0 1 0 . 0 0 0 0 0 0 0 1
# BLS8: 0 1 1 0 0 0 1 1 . 0 0 1 0 1 0 1 0
# BCC8-SAME: 0 1 1 0 0 1 0 0 . 0 0 0 0 0 0 0 1
# BCS8-SAME: 0 1 1 0 0 1 0 1 . 0 0 0 0 0 0 0 1
# BNE8-SAME: 0 1 1 0 0 1 1 0 . 0 0 0 0 0 0 0 1
# BEQ8-SAME: 0 1 1 0 0 1 1 1 . 0 0 0 0 0 0 0 1
# BVC8-SAME: 0 1 1 0 1 0 0 0 . 0 0 0 0 0 0 0 1
# BVS8-SAME: 0 1 1 0 1 0 0 1 . 0 0 0 0 0 0 0 1
# BPL8-SAME: 0 1 1 0 1 0 1 0 . 0 0 0 0 0 0 0 1
# BMI8-SAME: 0 1 1 0 1 0 1 1 . 0 0 0 0 0 0 0 1
# BGE8-SAME: 0 1 1 0 1 1 0 0 . 0 0 0 0 0 0 0 1
# BLT8-SAME: 0 1 1 0 1 1 0 1 . 0 0 0 0 0 0 0 1
# BGT8-SAME: 0 1 1 0 1 1 1 0 . 0 0 0 0 0 0 0 1
# BLE8-SAME: 0 1 1 0 1 1 1 1 . 0 0 0 0 0 0 0 1
#
# NOTE MxBCC8 branches cannot encode 0 displacement, 0 in displacement instructs
# to use additional word. Also it cannot encode -1 since all 1s instruct to use
# two additional words to encode 32bit offset(since M68020).
name: MxBcc8
body: |
bb.0:
Bhi8 1, implicit $ccr
Bls8 42, implicit $ccr
Bcc8 1, implicit $ccr
Bcs8 1, implicit $ccr
Bne8 1, implicit $ccr
Beq8 1, implicit $ccr
Bvc8 1, implicit $ccr
Bvs8 1, implicit $ccr
Bpl8 1, implicit $ccr
Bmi8 1, implicit $ccr
Bge8 1, implicit $ccr
Blt8 1, implicit $ccr
Bgt8 1, implicit $ccr
Ble8 1, implicit $ccr
...
--- # MxBcc16
# ---------------+---------------+-------------------------------
# F E D C | B A 9 8 | 7 6 5 4 3 2 1 0
# ---------------+---------------+-------------------------------
# 0 1 1 0 | CONDITION | 0 0 0 0 0 0 0 0
# ---------------+---------------+-------------------------------
# BHI16: 0 1 1 0 0 0 1 0 . 0 0 0 0 0 0 0 0
# BHI16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ---------------------------------------------------------------
# BLS16-SAME: 0 1 1 0 0 0 1 1 . 0 0 0 0 0 0 0 0
# BLS16-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
# ---------------------------------------------------------------
# BCC16-SAME: 0 1 1 0 0 1 0 0 . 0 0 0 0 0 0 0 0
# BCC16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BCS16: 0 1 1 0 0 1 0 1 . 0 0 0 0 0 0 0 0
# BCS16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BNE16-SAME: 0 1 1 0 0 1 1 0 . 0 0 0 0 0 0 0 0
# BNE16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BEQ16-SAME: 0 1 1 0 0 1 1 1 . 0 0 0 0 0 0 0 0
# BGE16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BVC16-SAME: 0 1 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# BVC16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BVS16-SAME: 0 1 1 0 1 0 0 1 . 0 0 0 0 0 0 0 0
# BVS16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BPL16-SAME: 0 1 1 0 1 0 1 0 . 0 0 0 0 0 0 0 0
# BPL16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BMI16-SAME: 0 1 1 0 1 0 1 1 . 0 0 0 0 0 0 0 0
# BMI16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BGE16-SAME: 0 1 1 0 1 1 0 0 . 0 0 0 0 0 0 0 0
# BLE16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BLT16-SAME: 0 1 1 0 1 1 0 1 . 0 0 0 0 0 0 0 0
# BLT16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BGT16-SAME: 0 1 1 0 1 1 1 0 . 0 0 0 0 0 0 0 0
# BGT16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# BLE16-SAME: 0 1 1 0 1 1 1 1 . 0 0 0 0 0 0 0 0
# BLE16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
name: MxBcc16
body: |
bb.0:
Bhi16 -1, implicit $ccr
Bls16 42, implicit $ccr
Bcc16 0, implicit $ccr
Bcs16 0, implicit $ccr
Bne16 0, implicit $ccr
Beq16 0, implicit $ccr
Bvc16 0, implicit $ccr
Bvs16 0, implicit $ccr
Bpl16 0, implicit $ccr
Bmi16 0, implicit $ccr
Bge16 0, implicit $ccr
Blt16 0, implicit $ccr
Bgt16 0, implicit $ccr
Ble16 0, implicit $ccr
...
88 changes: 88 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxCALL.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=CALLK,CALLQ,CALLB,CALLJ

#------------------------------------------------------------------------------
# MxCALL pushes address of the next instruction and jumps to the location
#------------------------------------------------------------------------------

--- # MxCALL_PCI
# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------+-----------+-----------
# 0 1 0 0 1 1 1 0 1 0 | MODE | REG
# ---------------------------------------+-----------+-----------
# CALLK: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 1
# CALLK-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------+-----------+-----------
# CALLK-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 1
# CALLK-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1
# ---------------------------------------+-----------+-----------
# CALLK-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 1
# CALLK-SAME: 1 0 0 0 1 0 0 0 . 0 0 1 0 1 0 1 0
# ---+-----------+---+-------+---+-------------------------------
# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
# ---+-----------+---+-------+---+-------------------------------
name: MxCALL_PCI
body: |
bb.0:
CALLk 0, $a0
CALLk -1, $a0
CALLk 42, $a0
...
--- # MxCALL_PCD
# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------+-----------+-----------
# 0 1 0 0 1 1 1 0 1 0 | MODE | REG
# ---------------------------------------+-----------+-----------
# CALLQ-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 0
# CALLQ-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------+-----------+-----------
# CALLQ-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 0
# CALLQ-SAME: 0 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
name: MxCALL_PCD
body: |
bb.0:
CALLq 0
CALLq 32767
...
--- # MxCALL_ABS
# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------+-----------+-----------
# 0 1 0 0 1 1 1 0 1 0 | MODE | REG
# ---------------------------------------+-----------+-----------
# CALLB-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 0 1
# CALLB-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# CALLB-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
# ---------------------------------------+-----------+-----------
# CALLB-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 0 1
# CALLB-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# CALLB-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
name: MxCALL_ABS
body: |
bb.0:
CALLb 42
CALLb -1
...
--- # MxCALL_ARI
# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------+-----------+-----------
# 0 1 0 0 1 1 1 0 1 0 | MODE | REG
# ---------------------------------------+-----------+-----------
# CALLJ-SAME: 0 1 0 0 1 1 1 0 . 1 0 0 1 0 0 0 0
# CALLJ-SAME: 0 1 0 0 1 1 1 0 . 1 0 0 1 0 0 0 1
# CALLJ-SAME: 0 1 0 0 1 1 1 0 . 1 0 0 1 0 0 1 0
name: MxCALL_ARI
body: |
bb.0:
CALLj $a0
CALLj $a1
CALLj $a2
...
21 changes: 21 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxJMP.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=JMP32J

#------------------------------------------------------------------------------
# MxJMP encodes unconditional jump
#------------------------------------------------------------------------------

--- # MxJMP_ARI
# ---------------------------------------+-----------+-----------
# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
# ---------------------------------------+-----------+-----------
# 0 1 0 0 1 1 1 0 1 1 | MODE | REG
# ---------------------------------------+-----------+-----------
# JMP32J: 0 1 0 0 1 1 1 0 . 1 1 0 1 0 0 0 0
name: MxJMP_ARI
body: |
bb.0:
JMP32j $a0
...
16 changes: 16 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxNOP.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=NOP

#------------------------------------------------------------------------------
# MxNOP
#------------------------------------------------------------------------------

# ---------------------------------------------------------------
# F E D C B A 9 8 7 6 5 4 3 2 1 0
# ---------------------------------------------------------------
# NOP: 0 1 0 0 1 1 1 0 . 0 1 1 1 0 0 0 1
name: MxNOP
body: |
bb.0:
NOP
16 changes: 16 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxRTS.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=RTS

#------------------------------------------------------------------------------
# MxRTS pops return address from the stack and jumps there
#------------------------------------------------------------------------------

# ---------------------------------------------------------------
# F E D C B A 9 8 7 6 5 4 3 2 1 0
# ---------------------------------------------------------------
# RTS: 0 1 0 0 1 1 1 0 . 0 1 1 1 0 1 0 1
name: MxRTS
body: |
bb.0:
RTS
140 changes: 140 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxScc.mir
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# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=SETD8CC,SETD8LS,SETD8LT,SETD8EQ,SETD8MI,SETD8F
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=SETD8NE,SETD8GE,SETD8CS,SETD8PL,SETD8GT,SETD8T
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=SETD8HI,SETD8VC,SETD8LE,SETD8VS,SETP8CC,SETP8LS
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=SETP8LT,SETP8EQ,SETP8MI,SETP8F,SETP8NE,SETP8GE
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=SETP8CS,SETP8PL,SETP8GT,SETP8T,SETP8HI,SETP8VC
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
# RUN: | extract-section .text \
# RUN: | FileCheck %s -check-prefixes=SETP8LE,SETP8VS

#------------------------------------------------------------------------------
# MxScc sets byte filled with 1s or 0s based on cc condition
#------------------------------------------------------------------------------

--- # MxScc_D
# ---------------+---------------+-------+-----------+-----------
# F E D C | B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# ---------------+---------------+-------+-----------+-----------
# 0 1 0 1 | CONDITION | 1 1 | MODE | REG
# ---------------+---------------+-------+-----------+-----------
# SETD8T: 0 1 0 1 0 0 0 0 . 1 1 0 0 0 0 0 0
# SETD8F: 0 1 0 1 0 0 0 1 . 1 1 0 0 0 0 0 1
# SETD8HI: 0 1 0 1 0 0 1 0 . 1 1 0 0 0 0 1 0
# SETD8LS-SAME: 0 1 0 1 0 0 1 1 . 1 1 0 0 0 0 1 1
# SETD8CC: 0 1 0 1 0 1 0 0 . 1 1 0 0 0 1 0 0
# SETD8CS-SAME: 0 1 0 1 0 1 0 1 . 1 1 0 0 0 1 0 1
# SETD8NE-SAME: 0 1 0 1 0 1 1 0 . 1 1 0 0 0 1 1 0
# SETD8EQ-SAME: 0 1 0 1 0 1 1 1 . 1 1 0 0 0 1 1 1
# SETD8VC-SAME: 0 1 0 1 1 0 0 0 . 1 1 0 0 0 0 0 0
# SETD8VS-SAME: 0 1 0 1 1 0 0 1 . 1 1 0 0 0 0 0 0
# SETD8PL-SAME: 0 1 0 1 1 0 1 0 . 1 1 0 0 0 0 0 0
# SETD8MI-SAME: 0 1 0 1 1 0 1 1 . 1 1 0 0 0 0 0 0
# SETD8GE-SAME: 0 1 0 1 1 1 0 0 . 1 1 0 0 0 0 0 0
# SETD8LT-SAME: 0 1 0 1 1 1 0 1 . 1 1 0 0 0 0 0 0
# SETD8GT-SAME: 0 1 0 1 1 1 1 0 . 1 1 0 0 0 0 0 0
# SETD8LE-SAME: 0 1 0 1 1 1 1 1 . 1 1 0 0 0 0 0 0
name: MxScc_D
body: |
bb.0:
$bd0 = SETd8t implicit $ccr
$bd1 = SETd8f implicit $ccr
$bd2 = SETd8hi implicit $ccr
$bd3 = SETd8ls implicit $ccr
$bd4 = SETd8cc implicit $ccr
$bd5 = SETd8cs implicit $ccr
$bd6 = SETd8ne implicit $ccr
$bd7 = SETd8eq implicit $ccr
$bd0 = SETd8vc implicit $ccr
$bd0 = SETd8vs implicit $ccr
$bd0 = SETd8pl implicit $ccr
$bd0 = SETd8mi implicit $ccr
$bd0 = SETd8ge implicit $ccr
$bd0 = SETd8lt implicit $ccr
$bd0 = SETd8gt implicit $ccr
$bd0 = SETd8le implicit $ccr
...
--- # MxScc_ARID
# ---------------+---------------+-------+-----------+-----------
# F E D C | B A 9 8 | 7 6 | 5 4 3 | 2 1 0
# ---------------+---------------+-------+-----------+-----------
# 0 1 0 1 | CONDITION | 1 1 | MODE | REG
# ---------------+---------------+-------+-----------+-----------
# SETP8T: 0 1 0 1 0 0 0 0 . 1 1 1 0 1 0 0 0
# SETP8T-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
# ---------------------------------------------------------------
# SETP8F: 0 1 0 1 0 0 0 1 . 1 1 1 0 1 0 0 1
# SETP8F-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
# ---------------------------------------------------------------
# SETP8HI-SAME: 0 1 0 1 0 0 1 0 . 1 1 1 0 1 0 1 0
# SETP8HI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8LS-SAME: 0 1 0 1 0 0 1 1 . 1 1 1 0 1 0 1 1
# SETP8LS-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8CC-SAME: 0 1 0 1 0 1 0 0 . 1 1 1 0 1 1 0 0
# SETP8CC-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8CS: 0 1 0 1 0 1 0 1 . 1 1 1 0 1 1 0 1
# SETP8CS-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8NE-SAME: 0 1 0 1 0 1 1 0 . 1 1 1 0 1 1 1 0
# SETP8NE-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8EQ-SAME: 0 1 0 1 0 1 1 1 . 1 1 1 0 1 0 0 0
# SETP8EQ-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8VC-SAME: 0 1 0 1 1 0 0 0 . 1 1 1 0 1 0 0 0
# SETP8VC-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8VS: 0 1 0 1 1 0 0 1 . 1 1 1 0 1 0 0 0
# SETP8VS-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8PL-SAME: 0 1 0 1 1 0 1 0 . 1 1 1 0 1 0 0 0
# SETP8PL-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8MI-SAME: 0 1 0 1 1 0 1 1 . 1 1 1 0 1 0 0 0
# SETP8MI-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8GE-SAME: 0 1 0 1 1 1 0 0 . 1 1 1 0 1 0 0 0
# SETP8GE-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8LT: 0 1 0 1 1 1 0 1 . 1 1 1 0 1 0 0 0
# SETP8LT-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8GT-SAME: 0 1 0 1 1 1 1 0 . 1 1 1 0 1 0 0 0
# SETP8GT-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
# ---------------------------------------------------------------
# SETP8LE: 0 1 0 1 1 1 1 1 . 1 1 1 0 1 0 0 0
# SETP8LE-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
name: MxScc_ARID
body: |
bb.0:
SETp8t -1, $a0, implicit $ccr
SETp8f 42, $a1, implicit $ccr
SETp8hi 0, $a2, implicit $ccr
SETp8ls 0, $a3, implicit $ccr
SETp8cc 0, $a4, implicit $ccr
SETp8cs 0, $a5, implicit $ccr
SETp8ne 0, $a6, implicit $ccr
SETp8eq 0, $a0, implicit $ccr
SETp8vc 0, $a0, implicit $ccr
SETp8vs 0, $a0, implicit $ccr
SETp8pl 0, $a0, implicit $ccr
SETp8mi 0, $a0, implicit $ccr
SETp8ge 0, $a0, implicit $ccr
SETp8lt 0, $a0, implicit $ccr
SETp8gt 0, $a0, implicit $ccr
SETp8le 0, $a0, implicit $ccr
...
31 changes: 31 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Control/branch-pc-rel.mir
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@@ -0,0 +1,31 @@
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj \
# RUN: -code-model=small -relocation-model=pic -o - \
# RUN: | extract-section .text -h \
# RUN: | FileCheck %s

#------------------------------------------------------------------------------
# This test checks whether branches have correct offset
#------------------------------------------------------------------------------

--- # TEXT
# 0 CHECK: 6702
# 2 CHECK-SAME: 6008
# 4 CHECK-SAME: d0bc 0000 0000
# A CHECK-SAME: 4e75
# C CHECK-SAME: d0bc 0000 0001
# 12 CHECK-SAME: 4e75
name: TEXT
body: |
bb.0:
successors: %bb.2,%bb.1
Beq8 %bb.1, implicit $ccr
BRA8 %bb.2
bb.1:
$d0 = ADD32ri $d0, 0, implicit-def $ccr
RET 0, $d0
bb.2:
$d0 = ADD32ri $d0, 1, implicit-def $ccr
RET 0, $d0
...
66 changes: 66 additions & 0 deletions llvm/test/CodeGen/M68k/Encoding/Control/call-pc-rel.mir
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@@ -0,0 +1,66 @@
# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj \
# RUN: -code-model=small -relocation-model=pic -o - \
# RUN: | extract-section .text -h \
# RUN: | FileCheck %s

#------------------------------------------------------------------------------
# Tests PC-Relative Calls' offsets. The rest requires relocation and tested
# appropriately elsewhere.
#------------------------------------------------------------------------------

#
# <BACKWARD>
# 00 CHECK: 4e71
# 02 CHECK-SAME: 4e75
#
# <PCI>
# 04 CHECK-SAME: 4ebb 08fa
# 08 CHECK-SAME: 4ebb 080a
#
# <PCD>
# 0c CHECK-SAME: 4eba fff2
# 10 CHECK-SAME: 4eba 0002
#
# <FORWARD>
# 14 CHECK-SAME: 4e71
# 16 CHECK-SAME: 4e75
--- |

define dso_local void @BACKWARD() { entry: ret void }
define dso_local void @PCI() { entry: ret void }
define dso_local void @PCD() { entry: ret void }
define dso_local void @FORWARD() { entry: ret void }

...
--- # BACKWARD
name: BACKWARD
body: |
bb.0:
NOP
RTS
...
--- # PCI
name: PCI
body: |
bb.0:
CALLk @BACKWARD, $d0
CALLk @FORWARD, $d0
...
--- # PCD
name: PCD
body: |
bb.0:
CALLq @BACKWARD
CALLq @FORWARD
...
--- # FORWARD
name: FORWARD
body: |
bb.0:
NOP
RTS
...
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