152 changes: 76 additions & 76 deletions llvm/test/Analysis/CostModel/AArch64/fptoi_sat.ll
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65 changes: 6 additions & 59 deletions llvm/test/CodeGen/AArch64/fcvt_combine.ll
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Expand Up @@ -466,72 +466,19 @@ define <8 x i16> @test_v8f16_sat(<8 x half> %in) {
; CHECK-NO16: // %bb.0:
; CHECK-NO16-NEXT: movi v1.8h, #68, lsl #8
; CHECK-NO16-NEXT: fcvtl v2.4s, v0.4h
; CHECK-NO16-NEXT: mov w8, #32767 // =0x7fff
; CHECK-NO16-NEXT: fcvtl2 v0.4s, v0.8h
; CHECK-NO16-NEXT: mov w11, #-32768 // =0xffff8000
; CHECK-NO16-NEXT: fcvtl v3.4s, v1.4h
; CHECK-NO16-NEXT: fcvtl2 v1.4s, v1.8h
; CHECK-NO16-NEXT: fmul v2.4s, v2.4s, v3.4s
; CHECK-NO16-NEXT: fmul v0.4s, v0.4s, v1.4s
; CHECK-NO16-NEXT: fcvtn v1.4h, v2.4s
; CHECK-NO16-NEXT: fcvtn2 v1.8h, v0.4s
; CHECK-NO16-NEXT: fcvtl2 v0.4s, v1.8h
; CHECK-NO16-NEXT: fcvtl v1.4s, v1.4h
; CHECK-NO16-NEXT: mov s2, v0.s[1]
; CHECK-NO16-NEXT: fcvtzs w10, s0
; CHECK-NO16-NEXT: fcvtzs w15, s1
; CHECK-NO16-NEXT: fcvtzs w9, s2
; CHECK-NO16-NEXT: mov s2, v0.s[2]
; CHECK-NO16-NEXT: mov s0, v0.s[3]
; CHECK-NO16-NEXT: cmp w9, w8
; CHECK-NO16-NEXT: fcvtzs w12, s2
; CHECK-NO16-NEXT: mov s2, v1.s[1]
; CHECK-NO16-NEXT: csel w9, w9, w8, lt
; CHECK-NO16-NEXT: fcvtzs w13, s0
; CHECK-NO16-NEXT: mov s0, v1.s[2]
; CHECK-NO16-NEXT: cmn w9, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: csel w9, w9, w11, gt
; CHECK-NO16-NEXT: cmp w10, w8
; CHECK-NO16-NEXT: csel w10, w10, w8, lt
; CHECK-NO16-NEXT: fcvtzs w14, s2
; CHECK-NO16-NEXT: cmn w10, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: fcvtzs w16, s0
; CHECK-NO16-NEXT: mov s0, v1.s[3]
; CHECK-NO16-NEXT: csel w10, w10, w11, gt
; CHECK-NO16-NEXT: cmp w12, w8
; CHECK-NO16-NEXT: csel w12, w12, w8, lt
; CHECK-NO16-NEXT: fmov s1, w10
; CHECK-NO16-NEXT: cmn w12, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: csel w12, w12, w11, gt
; CHECK-NO16-NEXT: cmp w13, w8
; CHECK-NO16-NEXT: csel w13, w13, w8, lt
; CHECK-NO16-NEXT: mov v1.s[1], w9
; CHECK-NO16-NEXT: fcvtzs w9, s0
; CHECK-NO16-NEXT: cmn w13, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: csel w13, w13, w11, gt
; CHECK-NO16-NEXT: cmp w14, w8
; CHECK-NO16-NEXT: csel w14, w14, w8, lt
; CHECK-NO16-NEXT: cmn w14, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: mov v1.s[2], w12
; CHECK-NO16-NEXT: csel w14, w14, w11, gt
; CHECK-NO16-NEXT: cmp w15, w8
; CHECK-NO16-NEXT: csel w15, w15, w8, lt
; CHECK-NO16-NEXT: cmn w15, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: csel w10, w15, w11, gt
; CHECK-NO16-NEXT: cmp w16, w8
; CHECK-NO16-NEXT: mov v1.s[3], w13
; CHECK-NO16-NEXT: fmov s2, w10
; CHECK-NO16-NEXT: csel w10, w16, w8, lt
; CHECK-NO16-NEXT: cmn w10, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: csel w10, w10, w11, gt
; CHECK-NO16-NEXT: cmp w9, w8
; CHECK-NO16-NEXT: mov v2.s[1], w14
; CHECK-NO16-NEXT: csel w8, w9, w8, lt
; CHECK-NO16-NEXT: cmn w8, #8, lsl #12 // =32768
; CHECK-NO16-NEXT: csel w8, w8, w11, gt
; CHECK-NO16-NEXT: mov v2.s[2], w10
; CHECK-NO16-NEXT: mov v2.s[3], w8
; CHECK-NO16-NEXT: uzp1 v0.8h, v2.8h, v1.8h
; CHECK-NO16-NEXT: fcvtl v0.4s, v1.4h
; CHECK-NO16-NEXT: fcvtl2 v1.4s, v1.8h
; CHECK-NO16-NEXT: fcvtzs v0.4s, v0.4s
; CHECK-NO16-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-NO16-NEXT: sqxtn v0.4h, v0.4s
; CHECK-NO16-NEXT: sqxtn2 v0.8h, v1.4s
; CHECK-NO16-NEXT: ret
;
; CHECK-FP16-LABEL: test_v8f16_sat:
Expand Down
513 changes: 67 additions & 446 deletions llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
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382 changes: 53 additions & 329 deletions llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
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45 changes: 15 additions & 30 deletions llvm/test/Transforms/AggressiveInstCombine/AArch64/fptosisat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -92,16 +92,10 @@ define i32 @f64_i16(double %in) {
}

define i64 @f16_i32(half %in) {
; CHECK-FP-LABEL: @f16_i32(
; CHECK-FP-NEXT: [[CONV:%.*]] = fptosi half [[IN:%.*]] to i64
; CHECK-FP-NEXT: [[MIN:%.*]] = call i64 @llvm.smin.i64(i64 [[CONV]], i64 2147483647)
; CHECK-FP-NEXT: [[MAX:%.*]] = call i64 @llvm.smax.i64(i64 [[MIN]], i64 -2147483648)
; CHECK-FP-NEXT: ret i64 [[MAX]]
;
; CHECK-FP16-LABEL: @f16_i32(
; CHECK-FP16-NEXT: [[TMP1:%.*]] = call i32 @llvm.fptosi.sat.i32.f16(half [[IN:%.*]])
; CHECK-FP16-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
; CHECK-FP16-NEXT: ret i64 [[TMP2]]
; CHECK-LABEL: @f16_i32(
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.fptosi.sat.i32.f16(half [[IN:%.*]])
; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
; CHECK-NEXT: ret i64 [[TMP2]]
;
%conv = fptosi half %in to i64
%min = call i64 @llvm.smin.i64(i64 %conv, i64 2147483647)
Expand Down Expand Up @@ -185,16 +179,10 @@ define <8 x i64> @v8f32_i32(<8 x float> %in) {
}

define <4 x i32> @v4f16_i16(<4 x half> %in) {
; CHECK-FP-LABEL: @v4f16_i16(
; CHECK-FP-NEXT: [[CONV:%.*]] = fptosi <4 x half> [[IN:%.*]] to <4 x i32>
; CHECK-FP-NEXT: [[MIN:%.*]] = call <4 x i32> @llvm.smin.v4i32(<4 x i32> [[CONV]], <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
; CHECK-FP-NEXT: [[MAX:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[MIN]], <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
; CHECK-FP-NEXT: ret <4 x i32> [[MAX]]
;
; CHECK-FP16-LABEL: @v4f16_i16(
; CHECK-FP16-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> [[IN:%.*]])
; CHECK-FP16-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>
; CHECK-FP16-NEXT: ret <4 x i32> [[TMP2]]
; CHECK-LABEL: @v4f16_i16(
; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> [[IN:%.*]])
; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[TMP2]]
;
%conv = fptosi <4 x half> %in to <4 x i32>
%min = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %conv, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
Expand All @@ -203,16 +191,10 @@ define <4 x i32> @v4f16_i16(<4 x half> %in) {
}

define <8 x i32> @v8f16_i16(<8 x half> %in) {
; CHECK-FP-LABEL: @v8f16_i16(
; CHECK-FP-NEXT: [[CONV:%.*]] = fptosi <8 x half> [[IN:%.*]] to <8 x i32>
; CHECK-FP-NEXT: [[MIN:%.*]] = call <8 x i32> @llvm.smin.v8i32(<8 x i32> [[CONV]], <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
; CHECK-FP-NEXT: [[MAX:%.*]] = call <8 x i32> @llvm.smax.v8i32(<8 x i32> [[MIN]], <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
; CHECK-FP-NEXT: ret <8 x i32> [[MAX]]
;
; CHECK-FP16-LABEL: @v8f16_i16(
; CHECK-FP16-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> [[IN:%.*]])
; CHECK-FP16-NEXT: [[TMP2:%.*]] = sext <8 x i16> [[TMP1]] to <8 x i32>
; CHECK-FP16-NEXT: ret <8 x i32> [[TMP2]]
; CHECK-LABEL: @v8f16_i16(
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> [[IN:%.*]])
; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i16> [[TMP1]] to <8 x i32>
; CHECK-NEXT: ret <8 x i32> [[TMP2]]
;
%conv = fptosi <8 x half> %in to <8 x i32>
%min = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
Expand Down Expand Up @@ -292,3 +274,6 @@ declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>)
declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>)
declare <8 x i32> @llvm.smin.v8i32(<8 x i32>, <8 x i32>)
declare <8 x i32> @llvm.smax.v8i32(<8 x i32>, <8 x i32>)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-FP: {{.*}}
; CHECK-FP16: {{.*}}