253 changes: 107 additions & 146 deletions llvm/lib/TableGen/TGParser.cpp
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7 changes: 3 additions & 4 deletions llvm/lib/TableGen/TGParser.h
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Original file line number Diff line number Diff line change
Expand Up @@ -126,10 +126,9 @@ class TGParser {
// iteration space.
typedef std::vector<IterRecord> IterSet;

bool addDefOne(std::unique_ptr<Record> Rec, Init *DefmName,
IterSet &IterVals);
bool addDefForeach(Record *Rec, Init *DefmName, IterSet &IterVals);
bool addDef(std::unique_ptr<Record> Rec, Init *DefmName);
bool addDefOne(std::unique_ptr<Record> Rec, IterSet &IterVals);
bool addDefForeach(Record *Rec, IterSet &IterVals);
bool addDef(std::unique_ptr<Record> Rec);

private: // Parser methods.
bool ParseObjectList(MultiClass *MC = nullptr);
Expand Down
144 changes: 72 additions & 72 deletions llvm/lib/Target/AArch64/AArch64InstrFormats.td
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72 changes: 36 additions & 36 deletions llvm/lib/Target/AMDGPU/BUFInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -52,19 +52,19 @@ class getAddrName<int addrKind> {
"")))));
}

class MUBUFAddr64Table <bit is_addr64, string suffix = ""> {
class MUBUFAddr64Table <bit is_addr64, string Name> {
bit IsAddr64 = is_addr64;
string OpName = NAME # suffix;
string OpName = Name;
}

class MUBUFLdsTable <bit is_lds, string suffix> {
class MUBUFLdsTable <bit is_lds, string Name> {
bit IsLds = is_lds;
string OpName = NAME # suffix;
string OpName = Name;
}

class MTBUFAddr64Table <bit is_addr64, string suffix = ""> {
class MTBUFAddr64Table <bit is_addr64, string Name> {
bit IsAddr64 = is_addr64;
string OpName = NAME # suffix;
string OpName = Name;
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -219,13 +219,13 @@ multiclass MTBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,
[(set load_vt:$vdata,
(ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i8:$dfmt,
i8:$nfmt, i1:$glc, i1:$slc, i1:$tfe)))]>,
MTBUFAddr64Table<0>;
MTBUFAddr64Table<0, NAME>;

def _ADDR64 : MTBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
[(set load_vt:$vdata,
(ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset,
i8:$dfmt, i8:$nfmt, i1:$glc, i1:$slc, i1:$tfe)))]>,
MTBUFAddr64Table<1>;
MTBUFAddr64Table<1, NAME>;

def _OFFEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
def _IDXEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
Expand Down Expand Up @@ -265,13 +265,13 @@ multiclass MTBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
[(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
i16:$offset, i8:$dfmt, i8:$nfmt, i1:$glc,
i1:$slc, i1:$tfe))]>,
MTBUFAddr64Table<0>;
MTBUFAddr64Table<0, NAME>;

def _ADDR64 : MTBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
[(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
i16:$offset, i8:$dfmt, i8:$nfmt, i1:$glc,
i1:$slc, i1:$tfe))]>,
MTBUFAddr64Table<1>;
MTBUFAddr64Table<1, NAME>;

def _OFFEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
def _IDXEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
Expand Down Expand Up @@ -474,15 +474,15 @@ multiclass MUBUF_Pseudo_Loads<string opName, RegisterClass vdataClass,
[],
[(set load_vt:$vdata,
(ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))])>,
MUBUFAddr64Table<0, !if(isLds, "_LDS", "")>;
MUBUFAddr64Table<0, NAME # !if(isLds, "_LDS", "")>;

def _ADDR64 : MUBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
TiedDest, isLds,
!if(isLds,
[],
[(set load_vt:$vdata,
(ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))])>,
MUBUFAddr64Table<1, !if(isLds, "_LDS", "")>;
MUBUFAddr64Table<1, NAME # !if(isLds, "_LDS", "")>;

def _OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, TiedDest, isLds>;
def _IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, TiedDest, isLds>;
Expand Down Expand Up @@ -530,12 +530,12 @@ multiclass MUBUF_Pseudo_Stores<string opName, RegisterClass vdataClass,
def _OFFSET : MUBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass,
[(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>,
MUBUFAddr64Table<0>;
MUBUFAddr64Table<0, NAME>;

def _ADDR64 : MUBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
[(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>,
MUBUFAddr64Table<1>;
MUBUFAddr64Table<1, NAME>;

def _OFFEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
def _IDXEN : MUBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
Expand Down Expand Up @@ -666,9 +666,9 @@ multiclass MUBUF_Pseudo_Atomics <string opName,
SDPatternOperator atomic> {

def _OFFSET : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Offset, vdataClass>,
MUBUFAddr64Table <0>;
MUBUFAddr64Table <0, NAME>;
def _ADDR64 : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.Addr64, vdataClass>,
MUBUFAddr64Table <1>;
MUBUFAddr64Table <1, NAME>;
def _OFFEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
def _IDXEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
def _BOTHEN : MUBUF_AtomicNoRet_Pseudo <opName, BUFAddrKind.BothEn, vdataClass>;
Expand All @@ -677,13 +677,13 @@ multiclass MUBUF_Pseudo_Atomics <string opName,
[(set vdataType:$vdata,
(atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$slc),
vdataType:$vdata_in))]>,
MUBUFAddr64Table <0, "_RTN">;
MUBUFAddr64Table <0, NAME # "_RTN">;

def _ADDR64_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.Addr64, vdataClass,
[(set vdataType:$vdata,
(atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$slc),
vdataType:$vdata_in))]>,
MUBUFAddr64Table <1, "_RTN">;
MUBUFAddr64Table <1, NAME # "_RTN">;

def _OFFEN_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.OffEn, vdataClass>;
def _IDXEN_RTN : MUBUF_AtomicRet_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass>;
Expand Down Expand Up @@ -1663,26 +1663,26 @@ multiclass MUBUF_Real_AllAddr_si<bits<7> op> {
multiclass MUBUF_Real_AllAddr_Lds_si<bits<7> op> {

def _OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
MUBUFLdsTable<0, "_OFFSET_si">;
MUBUFLdsTable<0, NAME # "_OFFSET_si">;
def _ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_ADDR64")>,
MUBUFLdsTable<0, "_ADDR64_si">;
MUBUFLdsTable<0, NAME # "_ADDR64_si">;
def _OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
MUBUFLdsTable<0, "_OFFEN_si">;
MUBUFLdsTable<0, NAME # "_OFFEN_si">;
def _IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
MUBUFLdsTable<0, "_IDXEN_si">;
MUBUFLdsTable<0, NAME # "_IDXEN_si">;
def _BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
MUBUFLdsTable<0, "_BOTHEN_si">;
MUBUFLdsTable<0, NAME # "_BOTHEN_si">;

def _LDS_OFFSET_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>,
MUBUFLdsTable<1, "_OFFSET_si">;
MUBUFLdsTable<1, NAME # "_OFFSET_si">;
def _LDS_ADDR64_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_ADDR64")>,
MUBUFLdsTable<1, "_ADDR64_si">;
MUBUFLdsTable<1, NAME # "_ADDR64_si">;
def _LDS_OFFEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>,
MUBUFLdsTable<1, "_OFFEN_si">;
MUBUFLdsTable<1, NAME # "_OFFEN_si">;
def _LDS_IDXEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>,
MUBUFLdsTable<1, "_IDXEN_si">;
MUBUFLdsTable<1, NAME # "_IDXEN_si">;
def _LDS_BOTHEN_si : MUBUF_Real_si <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>,
MUBUFLdsTable<1, "_BOTHEN_si">;
MUBUFLdsTable<1, NAME # "_BOTHEN_si">;
}

multiclass MUBUF_Real_Atomic_si<bits<7> op> : MUBUF_Real_AllAddr_si<op> {
Expand Down Expand Up @@ -1846,22 +1846,22 @@ multiclass MUBUF_Real_AllAddr_vi<bits<7> op> {
multiclass MUBUF_Real_AllAddr_Lds_vi<bits<7> op> {

def _OFFSET_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFSET")>,
MUBUFLdsTable<0, "_OFFSET_vi">;
MUBUFLdsTable<0, NAME # "_OFFSET_vi">;
def _OFFEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_OFFEN")>,
MUBUFLdsTable<0, "_OFFEN_vi">;
MUBUFLdsTable<0, NAME # "_OFFEN_vi">;
def _IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_IDXEN")>,
MUBUFLdsTable<0, "_IDXEN_vi">;
MUBUFLdsTable<0, NAME # "_IDXEN_vi">;
def _BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_BOTHEN")>,
MUBUFLdsTable<0, "_BOTHEN_vi">;
MUBUFLdsTable<0, NAME # "_BOTHEN_vi">;

def _LDS_OFFSET_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFSET")>,
MUBUFLdsTable<1, "_OFFSET_vi">;
MUBUFLdsTable<1, NAME # "_OFFSET_vi">;
def _LDS_OFFEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_OFFEN")>,
MUBUFLdsTable<1, "_OFFEN_vi">;
MUBUFLdsTable<1, NAME # "_OFFEN_vi">;
def _LDS_IDXEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_IDXEN")>,
MUBUFLdsTable<1, "_IDXEN_vi">;
MUBUFLdsTable<1, NAME # "_IDXEN_vi">;
def _LDS_BOTHEN_vi : MUBUF_Real_vi <op, !cast<MUBUF_Pseudo>(NAME#"_LDS_BOTHEN")>,
MUBUFLdsTable<1, "_BOTHEN_vi">;
MUBUFLdsTable<1, NAME # "_BOTHEN_vi">;
}

class MUBUF_Real_gfx80 <bits<7> op, MUBUF_Pseudo ps> :
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/AMDGPU/MIMGInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -280,15 +280,15 @@ multiclass MIMG_Sampler_Src_Helper_Helper <bits<7> op, string asm,
multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
RegisterClass dst_rc,
int channels, bit wqm> {
defm : MIMG_Sampler_Src_Helper_Helper <op, asm, dst_rc, channels, wqm, 0, "">;
defm "" : MIMG_Sampler_Src_Helper_Helper <op, asm, dst_rc, channels, wqm, 0, "">;

let d16 = 1 in {
let SubtargetPredicate = HasPackedD16VMem in {
defm : MIMG_Sampler_Src_Helper_Helper <op, asm, dst_rc, channels, wqm, 1, "_D16">;
defm "" : MIMG_Sampler_Src_Helper_Helper <op, asm, dst_rc, channels, wqm, 1, "_D16">;
} // End HasPackedD16VMem.

let SubtargetPredicate = HasUnpackedD16VMem, DecoderNamespace = "GFX80_UNPACKED" in {
defm : MIMG_Sampler_Src_Helper_Helper <op, asm, dst_rc, channels, wqm, 1, "_D16_gfx80">;
defm "" : MIMG_Sampler_Src_Helper_Helper <op, asm, dst_rc, channels, wqm, 1, "_D16_gfx80">;
} // End HasUnpackedD16VMem.
} // End d16 = 1.
}
Expand Down Expand Up @@ -348,15 +348,15 @@ multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
}

multiclass MIMG_Gather <bits<7> op, string asm, bit wqm=0> {
defm : MIMG_Gather_Src_Helper<op, asm, VReg_128, wqm, 0, "_V4", "">;
defm "" : MIMG_Gather_Src_Helper<op, asm, VReg_128, wqm, 0, "_V4", "">;

let d16 = 1 in {
let AssemblerPredicate = HasPackedD16VMem in {
defm : MIMG_Gather_Src_Helper<op, asm, VReg_64, wqm, 1, "_V2", "_D16">;
defm "" : MIMG_Gather_Src_Helper<op, asm, VReg_64, wqm, 1, "_V2", "_D16">;
} // End HasPackedD16VMem.

let AssemblerPredicate = HasUnpackedD16VMem, DecoderNamespace = "GFX80_UNPACKED" in {
defm : MIMG_Gather_Src_Helper<op, asm, VReg_128, wqm, 1, "_V4", "_D16_gfx80">;
defm "" : MIMG_Gather_Src_Helper<op, asm, VReg_128, wqm, 1, "_V4", "_D16_gfx80">;
} // End HasUnpackedD16VMem.
} // End d16 = 1.
}
Expand Down
329 changes: 172 additions & 157 deletions llvm/lib/Target/X86/X86InstrAVX512.td
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25 changes: 12 additions & 13 deletions llvm/lib/Target/X86/X86InstrSSE.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2740,7 +2740,7 @@ multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
Operand intmemop, ComplexPattern int_cpat,
Intrinsic Intr, SDNode OpNode, Domain d,
X86FoldableSchedWrite sched,
Predicate target, string Suffix> {
Predicate target> {
let hasSideEffects = 0 in {
def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
!strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
Expand Down Expand Up @@ -2768,7 +2768,7 @@ multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
// These are unary operations, but they are modeled as having 2 source operands
// because the high elements of the destination are unchanged in SSE.
def : Pat<(Intr VR128:$src),
(!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
(!cast<Instruction>(NAME#r_Int) VR128:$src, VR128:$src)>;
}
// We don't want to fold scalar loads into these instructions unless
// optimizing for size. This is because the folded instruction will have a
Expand All @@ -2779,7 +2779,7 @@ multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
// rcpss mem, %xmm0
let Predicates = [target, OptForSize] in {
def : Pat<(Intr int_cpat:$src2),
(!cast<Instruction>(NAME#Suffix##m_Int)
(!cast<Instruction>(NAME#m_Int)
(vt (IMPLICIT_DEF)), addr:$src2)>;
}
}
Expand All @@ -2789,8 +2789,7 @@ multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
X86MemOperand x86memop,
Operand intmemop, ComplexPattern int_cpat,
Intrinsic Intr, SDNode OpNode, Domain d,
X86FoldableSchedWrite sched, Predicate target,
string Suffix> {
X86FoldableSchedWrite sched, Predicate target> {
let hasSideEffects = 0 in {
def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Expand Down Expand Up @@ -2822,18 +2821,18 @@ multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
// TODO: In theory, we could fold the load, and avoid the stall caused by
// the partial register store, either in BreakFalseDeps or with smarter RA.
let Predicates = [target] in {
def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
def : Pat<(OpNode RC:$src), (!cast<Instruction>(NAME#r)
(ScalarVT (IMPLICIT_DEF)), RC:$src)>;
def : Pat<(Intr VR128:$src),
(!cast<Instruction>("V"#NAME#Suffix##r_Int) VR128:$src,
(!cast<Instruction>(NAME#r_Int) VR128:$src,
VR128:$src)>;
}
let Predicates = [target, OptForSize] in {
def : Pat<(Intr int_cpat:$src2),
(!cast<Instruction>("V"#NAME#Suffix##m_Int)
(!cast<Instruction>(NAME#m_Int)
(vt (IMPLICIT_DEF)), addr:$src2)>;
def : Pat<(ScalarVT (OpNode (load addr:$src))),
(!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
(!cast<Instruction>(NAME#m) (ScalarVT (IMPLICIT_DEF)),
addr:$src)>;
}
}
Expand Down Expand Up @@ -2915,11 +2914,11 @@ multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
ssmem, sse_load_f32,
!cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
SSEPackedSingle, sched.Scl, UseSSE1, "SS">, XS;
SSEPackedSingle, sched.Scl, UseSSE1>, XS;
defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
f32mem, ssmem, sse_load_f32,
!cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
SSEPackedSingle, sched.Scl, AVXTarget, "SS">, XS, VEX_4V,
SSEPackedSingle, sched.Scl, AVXTarget>, XS, VEX_4V,
VEX_LIG, VEX_WIG, NotMemoryFoldable;
}

Expand All @@ -2928,11 +2927,11 @@ multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
sdmem, sse_load_f64,
!cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
OpNode, SSEPackedDouble, sched.Scl, UseSSE2, "SD">, XD;
OpNode, SSEPackedDouble, sched.Scl, UseSSE2>, XD;
defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
f64mem, sdmem, sse_load_f64,
!cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
OpNode, SSEPackedDouble, sched.Scl, AVXTarget, "SD">,
OpNode, SSEPackedDouble, sched.Scl, AVXTarget>,
XD, VEX_4V, VEX_LIG, VEX_WIG, NotMemoryFoldable;
}

Expand Down
2 changes: 0 additions & 2 deletions llvm/test/TableGen/Dag.td
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,6 @@ def VAL3 : bar<foo1, somedef1>;
// CHECK-NEXT: dag Dag1 = (somedef1 1);
// CHECK-NEXT: dag Dag2 = (somedef1 2);
// CHECK-NEXT: dag Dag3 = (somedef1 2);
// CHECK-NEXT: NAME = ?
// CHECK-NEXT: }


Expand All @@ -69,7 +68,6 @@ def VAL4 : bar<foo2, somedef2>;
// CHECK-NEXT: dag Dag1 = (somedef1 1);
// CHECK-NEXT: dag Dag2 = (somedef2 2);
// CHECK-NEXT: dag Dag3 = (somedef2 2);
// CHECK-NEXT: NAME = ?
// CHECK-NEXT: }

def VAL5 : bar<foo2, somedef2> {
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/TableGen/MultiClassDefName.td
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Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@ multiclass MC3<string s> {
def ZFizz#s : C<s>;
}

defm : MC3<"Buzz">;
defm "" : MC3<"Buzz">;

// CHECK: def ZFizzBuzz
// CHECK: string name = "Buzz";
Expand Down
2 changes: 0 additions & 2 deletions llvm/test/TableGen/lisp.td
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Original file line number Diff line number Diff line change
Expand Up @@ -5,14 +5,12 @@
// CHECK-NEXT: string element = "Jeffrey Sinclair";
// CHECK-NEXT: list<string> rest = [];
// CHECK-NEXT: int null = 1;
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: def Three {
// CHECK-NEXT: list<string> names = ["Tom", "Dick", "Harry"];
// CHECK-NEXT: string element = "Tom";
// CHECK-NEXT: list<string> rest = ["Dick", "Harry"];
// CHECK-NEXT: int null = 0;
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }

class List<list<string> n> {
Expand Down
83 changes: 50 additions & 33 deletions llvm/test/TableGen/name-resolution-consistency.td
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Original file line number Diff line number Diff line change
@@ -1,57 +1,56 @@
// RUN: llvm-tblgen %s | FileCheck %s
// XFAIL: vg_leak

// This test demonstrates a number of inconsistencies in how NAME is resolved
// and record names are constructed.
//
// The TODO lines describe a suggested consistent behavior that would result
// from:
// (1) Treating NAME as an implicit multiclass template argument and
// (2) always storing the name of (non-anonymous) prototype records in
// multiclasses with at least one explicit reference to NAME.
//
// Unfortunately, several backends (including X86) rely quite heavily on the
// current inconsistent behavior and would have to be fixed.

// CHECK: def B0a {
// CHECK: string e = "B0";
// CHECK: }

// CHECK: def B0ba {
// TODO: expect "B0b" here
// CHECK: string a = "B0";
// CHECK: string a = "B0b";
// CHECK: string b = "B0";
// CHECK: }

// CHECK: def B0bys {
// CHECK: string f = "B0b";
// CHECK: string g = "B0";
// CHECK: }

// CHECK: def B0cza {
// TODO: expect "B0cz" here
// CHECK: string a = "B0";
// CHECK: string a = "B0cz";
// CHECK: string b = "B0";
// CHECK: }

// TODO: expect this to be named 'xB0b'
// CHECK: def B0xb {
// TODO: expect "B0b" here
// CHECK: string c = "b";
// CHECK: string d = "b";
// CHECK: def B0czyt {
// CHECK: string f = "B0cz";
// CHECK: string g = "B0";
// CHECK: }

// TODO: expect this to be named B0bys
// CHECK: def B0ys {
// TODO: expect "B0b" here
// CHECK: string f = "b";
// CHECK: string g = "b";
// CHECK: def C0 {
// CHECK: string a = "C0";
// CHECK: string b = "C0";
// CHECK: string c = "a";
// CHECK: }

// CHECK: def xB0cz {
// CHECK: string c = "B0cz";
// CHECK: string d = "B0cz";
// CHECK: def D0a {
// CHECK: string a = "D0a";
// CHECK: string b = "D0a";
// CHECK: string c = "D0";
// CHECK: }

// TODO: expect this to be named B0czyt
// CHECK: def yt {
// CHECK: string f = "B0cz";
// CHECK: string g = "B0cz";
// CHECK: def D0b {
// CHECK: string a = "D0b";
// CHECK: string b = "D0b";
// CHECK: string c = "a";
// CHECK: }

// CHECK: def xB0b {
// CHECK: string c = "B0b";
// CHECK: string d = "B0";
// CHECK: }

// CHECK: def xB0cz {
// CHECK: string c = "B0cz";
// CHECK: string d = "B0";
// CHECK: }

multiclass A<string p, string q> {
Expand Down Expand Up @@ -82,3 +81,21 @@ multiclass B<string name, string t> {
}

defm B0 : B<"z", "t">;

class Cbase {
string a = NAME;
}

class C<string arg> : Cbase {
string b = NAME;
string c = arg;
}

def C0 : C<"a">;

multiclass D<string arg> {
def a : C<NAME>;
def b : C<arg>;
}

defm D0 : D<"a">;
11 changes: 0 additions & 11 deletions llvm/test/TableGen/subst.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,51 +28,40 @@ def JimmyJohnson : AName<"Jimmy Johnson", Mr>;
// CHECK-NEXT: class AName<string AName:name = ?, Honorific AName:honorific = ?> {
// CHECK-NEXT: string name = !subst("FIRST", "John", !subst("LAST", "Smith", AName:name));
// CHECK-NEXT: Honorific honorific = !subst(TVAR, Mr, AName:honorific);
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: class Honorific<string Honorific:t = ?> {
// CHECK-NEXT: string honorific = Honorific:t;
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: class Name<string Name:n = ?, Honorific Name:t = ?> {
// CHECK-NEXT: string name = Name:n;
// CHECK-NEXT: Honorific honorific = Name:t;
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: ------------- Defs -----------------
// CHECK-NEXT: def JaneSmith {
// CHECK-NEXT: string name = "Jane Smith";
// CHECK-NEXT: Honorific honorific = Ms;
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: def JimmyJohnson {
// CHECK-NEXT: string name = "Jimmy Johnson";
// CHECK-NEXT: Honorific honorific = Mr;
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: def JohnSmith {
// CHECK-NEXT: string name = "John Smith";
// CHECK-NEXT: Honorific honorific = Mr;
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: def JohnSmithJones {
// CHECK-NEXT: string name = "John Smith-Jones";
// CHECK-NEXT: Honorific honorific = Mr;
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: def Mr
// CHECK-NEXT: string honorific = "Mr.";
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: def Mrs {
// CHECK-NEXT: string honorific = "Mrs.";
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: def Ms {
// CHECK-NEXT: string honorific = "Ms.";
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }
// CHECK-NEXT: def TVAR {
// CHECK-NEXT: string honorific = "Bogus";
// CHECK-NEXT: string NAME = ?;
// CHECK-NEXT: }