237 changes: 75 additions & 162 deletions llvm/test/CodeGen/RISCV/float-convert.ll
View file
Original file line number Diff line number Diff line change
@@ -1,23 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s

define i32 @fcvt_w_s(float %a) nounwind {
; RV32IF-LABEL: fcvt_w_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_w_s:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_w_s:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s:
; RV32I: # %bb.0:
Expand All @@ -41,23 +36,14 @@ define i32 @fcvt_w_s(float %a) nounwind {
}

define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV32IF-LABEL: fcvt_w_s_sat:
; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB1_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: .LBB1_2: # %start
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_w_s_sat:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB1_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: .LBB1_2: # %start
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_w_s_sat:
; CHECKIF: # %bb.0: # %start
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB1_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz
; CHECKIF-NEXT: .LBB1_2: # %start
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat:
; RV32I: # %bb.0: # %start
Expand Down Expand Up @@ -159,15 +145,10 @@ start:
declare i32 @llvm.fptosi.sat.i32.f32(float)

define i32 @fcvt_wu_s(float %a) nounwind {
; RV32IF-LABEL: fcvt_wu_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_wu_s:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_wu_s:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s:
; RV32I: # %bb.0:
Expand All @@ -193,25 +174,15 @@ define i32 @fcvt_wu_s(float %a) nounwind {
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
; RV32IF-LABEL: fcvt_wu_s_multiple_use:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.wu.s a1, fa0, rtz
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: beqz a1, .LBB3_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: mv a0, a1
; RV32IF-NEXT: .LBB3_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_wu_s_multiple_use:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.wu.s a1, fa0, rtz
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: beqz a1, .LBB3_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: mv a0, a1
; RV64IF-NEXT: .LBB3_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_wu_s_multiple_use:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.wu.s a1, fa0, rtz
; CHECKIF-NEXT: li a0, 1
; CHECKIF-NEXT: beqz a1, .LBB3_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: mv a0, a1
; CHECKIF-NEXT: .LBB3_2:
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_multiple_use:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -249,23 +220,14 @@ define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
}

define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV32IF-LABEL: fcvt_wu_s_sat:
; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB4_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IF-NEXT: .LBB4_2: # %start
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_wu_s_sat:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB4_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: .LBB4_2: # %start
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_wu_s_sat:
; CHECKIF: # %bb.0: # %start
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB4_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
; CHECKIF-NEXT: .LBB4_2: # %start
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_sat:
; RV32I: # %bb.0: # %start
Expand Down Expand Up @@ -343,17 +305,11 @@ start:
declare i32 @llvm.fptoui.sat.i32.f32(float)

define i32 @fmv_x_w(float %a, float %b) nounwind {
; RV32IF-LABEL: fmv_x_w:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fadd.s ft0, fa0, fa1
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmv_x_w:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fadd.s ft0, fa0, fa1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fmv_x_w:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fadd.s ft0, fa0, fa1
; CHECKIF-NEXT: fmv.x.w a0, ft0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmv_x_w:
; RV32I: # %bb.0:
Expand All @@ -379,15 +335,10 @@ define i32 @fmv_x_w(float %a, float %b) nounwind {
}

define float @fcvt_s_w(i32 %a) nounwind {
; RV32IF-LABEL: fcvt_s_w:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.s.w fa0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_w:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_s_w:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.s.w fa0, a0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w:
; RV32I: # %bb.0:
Expand All @@ -412,17 +363,11 @@ define float @fcvt_s_w(i32 %a) nounwind {
}

define float @fcvt_s_w_load(i32* %p) nounwind {
; RV32IF-LABEL: fcvt_s_w_load:
; RV32IF: # %bb.0:
; RV32IF-NEXT: lw a0, 0(a0)
; RV32IF-NEXT: fcvt.s.w fa0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_w_load:
; RV64IF: # %bb.0:
; RV64IF-NEXT: lw a0, 0(a0)
; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_s_w_load:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: lw a0, 0(a0)
; CHECKIF-NEXT: fcvt.s.w fa0, a0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_load:
; RV32I: # %bb.0:
Expand All @@ -449,15 +394,10 @@ define float @fcvt_s_w_load(i32* %p) nounwind {
}

define float @fcvt_s_wu(i32 %a) nounwind {
; RV32IF-LABEL: fcvt_s_wu:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.s.wu fa0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_wu:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_s_wu:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.s.wu fa0, a0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -519,19 +459,12 @@ define float @fcvt_s_wu_load(i32* %p) nounwind {
}

define float @fmv_w_x(i32 %a, i32 %b) nounwind {
; RV32IF-LABEL: fmv_w_x:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fadd.s fa0, ft0, ft1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmv_w_x:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fadd.s fa0, ft0, ft1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fmv_w_x:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fmv.w.x ft0, a0
; CHECKIF-NEXT: fmv.w.x ft1, a1
; CHECKIF-NEXT: fadd.s fa0, ft0, ft1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmv_w_x:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -1051,15 +984,10 @@ define float @fcvt_s_lu(i64 %a) nounwind {
}

define float @fcvt_s_w_i8(i8 signext %a) nounwind {
; RV32IF-LABEL: fcvt_s_w_i8:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.s.w fa0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_w_i8:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_s_w_i8:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.s.w fa0, a0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_i8:
; RV32I: # %bb.0:
Expand All @@ -1083,15 +1011,10 @@ define float @fcvt_s_w_i8(i8 signext %a) nounwind {
}

define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
; RV32IF-LABEL: fcvt_s_wu_i8:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.s.wu fa0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_wu_i8:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_s_wu_i8:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.s.wu fa0, a0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu_i8:
; RV32I: # %bb.0:
Expand All @@ -1115,15 +1038,10 @@ define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
}

define float @fcvt_s_w_i16(i16 signext %a) nounwind {
; RV32IF-LABEL: fcvt_s_w_i16:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.s.w fa0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_w_i16:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.w fa0, a0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_s_w_i16:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.s.w fa0, a0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_w_i16:
; RV32I: # %bb.0:
Expand All @@ -1147,15 +1065,10 @@ define float @fcvt_s_w_i16(i16 signext %a) nounwind {
}

define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
; RV32IF-LABEL: fcvt_s_wu_i16:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fcvt.s.wu fa0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_s_wu_i16:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fcvt.s.wu fa0, a0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcvt_s_wu_i16:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fcvt.s.wu fa0, a0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcvt_s_wu_i16:
; RV32I: # %bb.0:
Expand Down
578 changes: 184 additions & 394 deletions llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
View file

Large diffs are not rendered by default.

257 changes: 81 additions & 176 deletions llvm/test/CodeGen/RISCV/float-fcmp.ll
View file
Original file line number Diff line number Diff line change
@@ -1,23 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
; RUN: -target-abi=ilp32f | FileCheck -check-prefix=CHECKIF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
; RUN: -target-abi=lp64f | FileCheck -check-prefix=CHECKIF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s

define i32 @fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_false:
; RV32IF: # %bb.0:
; RV32IF-NEXT: li a0, 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_false:
; RV64IF: # %bb.0:
; RV64IF-NEXT: li a0, 0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_false:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: li a0, 0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_false:
; RV32I: # %bb.0:
Expand All @@ -34,15 +29,10 @@ define i32 @fcmp_false(float %a, float %b) nounwind {
}

define i32 @fcmp_oeq(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_oeq:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_oeq:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_oeq:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
Expand All @@ -69,15 +59,10 @@ define i32 @fcmp_oeq(float %a, float %b) nounwind {
}

define i32 @fcmp_ogt(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ogt:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa1, fa0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_ogt:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa1, fa0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_ogt:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: flt.s a0, fa1, fa0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
Expand All @@ -104,15 +89,10 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind {
}

define i32 @fcmp_oge(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_oge:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fle.s a0, fa1, fa0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_oge:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fle.s a0, fa1, fa0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_oge:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fle.s a0, fa1, fa0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -141,15 +121,10 @@ define i32 @fcmp_oge(float %a, float %b) nounwind {
}

define i32 @fcmp_olt(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_olt:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_olt:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa0, fa1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_olt:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: flt.s a0, fa0, fa1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
Expand All @@ -176,15 +151,10 @@ define i32 @fcmp_olt(float %a, float %b) nounwind {
}

define i32 @fcmp_ole(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ole:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fle.s a0, fa0, fa1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_ole:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fle.s a0, fa0, fa1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_ole:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fle.s a0, fa0, fa1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
Expand All @@ -211,19 +181,12 @@ define i32 @fcmp_ole(float %a, float %b) nounwind {
}

define i32 @fcmp_one(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_one:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa0, fa1
; RV32IF-NEXT: flt.s a1, fa1, fa0
; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_one:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa0, fa1
; RV64IF-NEXT: flt.s a1, fa1, fa0
; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_one:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: flt.s a0, fa0, fa1
; CHECKIF-NEXT: flt.s a1, fa1, fa0
; CHECKIF-NEXT: or a0, a1, a0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -276,19 +239,12 @@ define i32 @fcmp_one(float %a, float %b) nounwind {
}

define i32 @fcmp_ord(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ord:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa1, fa1
; RV32IF-NEXT: feq.s a1, fa0, fa0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_ord:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa1, fa1
; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_ord:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa1, fa1
; CHECKIF-NEXT: feq.s a1, fa0, fa0
; CHECKIF-NEXT: and a0, a1, a0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
Expand All @@ -315,21 +271,13 @@ define i32 @fcmp_ord(float %a, float %b) nounwind {
}

define i32 @fcmp_ueq(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ueq:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa0, fa1
; RV32IF-NEXT: flt.s a1, fa1, fa0
; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_ueq:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa0, fa1
; RV64IF-NEXT: flt.s a1, fa1, fa0
; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_ueq:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: flt.s a0, fa0, fa1
; CHECKIF-NEXT: flt.s a1, fa1, fa0
; CHECKIF-NEXT: or a0, a1, a0
; CHECKIF-NEXT: xori a0, a0, 1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -382,17 +330,11 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind {
}

define i32 @fcmp_ugt(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ugt:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fle.s a0, fa0, fa1
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_ugt:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fle.s a0, fa0, fa1
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_ugt:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fle.s a0, fa0, fa1
; CHECKIF-NEXT: xori a0, a0, 1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
Expand All @@ -419,17 +361,11 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind {
}

define i32 @fcmp_uge(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_uge:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa0, fa1
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_uge:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa0, fa1
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_uge:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: flt.s a0, fa0, fa1
; CHECKIF-NEXT: xori a0, a0, 1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -458,17 +394,11 @@ define i32 @fcmp_uge(float %a, float %b) nounwind {
}

define i32 @fcmp_ult(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ult:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fle.s a0, fa1, fa0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_ult:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fle.s a0, fa1, fa0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_ult:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fle.s a0, fa1, fa0
; CHECKIF-NEXT: xori a0, a0, 1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
Expand All @@ -495,17 +425,11 @@ define i32 @fcmp_ult(float %a, float %b) nounwind {
}

define i32 @fcmp_ule(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ule:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flt.s a0, fa1, fa0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_ule:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flt.s a0, fa1, fa0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_ule:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: flt.s a0, fa1, fa0
; CHECKIF-NEXT: xori a0, a0, 1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
Expand All @@ -532,17 +456,11 @@ define i32 @fcmp_ule(float %a, float %b) nounwind {
}

define i32 @fcmp_une(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_une:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa1
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_une:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa1
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_une:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa1
; CHECKIF-NEXT: xori a0, a0, 1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
Expand All @@ -569,21 +487,13 @@ define i32 @fcmp_une(float %a, float %b) nounwind {
}

define i32 @fcmp_uno(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_uno:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa1, fa1
; RV32IF-NEXT: feq.s a1, fa0, fa0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_uno:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa1, fa1
; RV64IF-NEXT: feq.s a1, fa0, fa0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_uno:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa1, fa1
; CHECKIF-NEXT: feq.s a1, fa0, fa0
; CHECKIF-NEXT: and a0, a1, a0
; CHECKIF-NEXT: xori a0, a0, 1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
Expand All @@ -610,15 +520,10 @@ define i32 @fcmp_uno(float %a, float %b) nounwind {
}

define i32 @fcmp_true(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_true:
; RV32IF: # %bb.0:
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_true:
; RV64IF: # %bb.0:
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fcmp_true:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: li a0, 1
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fcmp_true:
; RV32I: # %bb.0:
Expand Down
39 changes: 13 additions & 26 deletions llvm/test/CodeGen/RISCV/float-imm.ll
View file
Original file line number Diff line number Diff line change
@@ -1,39 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
; RUN: -target-abi=ilp32f | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
; RUN: -target-abi=lp64f | FileCheck %s

; TODO: constant pool shouldn't be necessary for RV64IF.
define float @float_imm() nounwind {
; RV32IF-LABEL: float_imm:
; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a0, %hi(.LCPI0_0)
; RV32IF-NEXT: flw fa0, %lo(.LCPI0_0)(a0)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: float_imm:
; RV64IF: # %bb.0:
; RV64IF-NEXT: lui a0, %hi(.LCPI0_0)
; RV64IF-NEXT: flw fa0, %lo(.LCPI0_0)(a0)
; RV64IF-NEXT: ret
; CHECK-LABEL: float_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flw fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: ret
ret float 3.14159274101257324218750
}

define float @float_imm_op(float %a) nounwind {
; RV32IF-LABEL: float_imm_op:
; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
; RV32IF-NEXT: fadd.s fa0, fa0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: float_imm_op:
; RV64IF: # %bb.0:
; RV64IF-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
; RV64IF-NEXT: fadd.s fa0, fa0, ft0
; RV64IF-NEXT: ret
; CHECK-LABEL: float_imm_op:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
%1 = fadd float %a, 1.0
ret float %1
}
43 changes: 14 additions & 29 deletions llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \
; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=ilp32f \
; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: | FileCheck -check-prefixes=CHECKIF,RV32IF %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \
; RUN: -verify-machineinstrs -disable-strictnode-mutation -target-abi=lp64f \
; RUN: | FileCheck -check-prefix=RV64IF %s
; RUN: | FileCheck -check-prefixes=CHECKIF,RV64IF %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
; RUN: -verify-machineinstrs -disable-strictnode-mutation \
; RUN: | FileCheck -check-prefix=RV32I %s
Expand All @@ -15,15 +15,10 @@
declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)

define float @sqrt_f32(float %a) nounwind strictfp {
; RV32IF-LABEL: sqrt_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fsqrt.s fa0, fa0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: sqrt_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fsqrt.s fa0, fa0
; RV64IF-NEXT: ret
; CHECKIF-LABEL: sqrt_f32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fsqrt.s fa0, fa0
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: sqrt_f32:
; RV32I: # %bb.0:
Expand Down Expand Up @@ -512,15 +507,10 @@ define float @log2_f32(float %a) nounwind strictfp {
declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)

define float @fma_f32(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fma_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fma_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fma_f32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fma_f32:
; RV32I: # %bb.0:
Expand All @@ -546,15 +536,10 @@ define float @fma_f32(float %a, float %b, float %c) nounwind strictfp {
declare float @llvm.experimental.constrained.fmuladd.f32(float, float, float, metadata, metadata)

define float @fmuladd_f32(float %a, float %b, float %c) nounwind strictfp {
; RV32IF-LABEL: fmuladd_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmuladd_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fmuladd_f32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fmadd.s fa0, fa0, fa1, fa2
; CHECKIF-NEXT: ret
;
; RV32I-LABEL: fmuladd_f32:
; RV32I: # %bb.0:
Expand Down
33 changes: 11 additions & 22 deletions llvm/test/CodeGen/RISCV/float-isnan.ll
View file
Original file line number Diff line number Diff line change
@@ -1,35 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32IF %s
; RUN: < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64IF %s
; RUN: < %s | FileCheck %s

define zeroext i1 @float_is_nan(float %a) nounwind {
; RV32IF-LABEL: float_is_nan:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: float_is_nan:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: ret
; CHECK-LABEL: float_is_nan:
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa0
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp uno float %a, 0.000000e+00
ret i1 %1
}

define zeroext i1 @float_not_nan(float %a) nounwind {
; RV32IF-LABEL: float_not_nan:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: float_not_nan:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: ret
; CHECK-LABEL: float_not_nan:
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa0
; CHECK-NEXT: ret
%1 = fcmp ord float %a, 0.000000e+00
ret i1 %1
}
73 changes: 24 additions & 49 deletions llvm/test/CodeGen/RISCV/float-mem.ll
View file
Original file line number Diff line number Diff line change
@@ -1,23 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s

define dso_local float @flw(float *%a) nounwind {
; RV32IF-LABEL: flw:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flw ft0, 0(a0)
; RV32IF-NEXT: flw ft1, 12(a0)
; RV32IF-NEXT: fadd.s fa0, ft0, ft1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: flw:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flw ft0, 0(a0)
; RV64IF-NEXT: flw ft1, 12(a0)
; RV64IF-NEXT: fadd.s fa0, ft0, ft1
; RV64IF-NEXT: ret
; CHECKIF-LABEL: flw:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: flw ft0, 0(a0)
; CHECKIF-NEXT: flw ft1, 12(a0)
; CHECKIF-NEXT: fadd.s fa0, ft0, ft1
; CHECKIF-NEXT: ret
%1 = load float, float* %a
%2 = getelementptr float, float* %a, i32 3
%3 = load float, float* %2
Expand All @@ -30,19 +23,12 @@ define dso_local float @flw(float *%a) nounwind {
define dso_local void @fsw(float *%a, float %b, float %c) nounwind {
; Use %b and %c in an FP op to ensure floating point registers are used, even
; for the soft float ABI
; RV32IF-LABEL: fsw:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fadd.s ft0, fa0, fa1
; RV32IF-NEXT: fsw ft0, 0(a0)
; RV32IF-NEXT: fsw ft0, 32(a0)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fsw:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fadd.s ft0, fa0, fa1
; RV64IF-NEXT: fsw ft0, 0(a0)
; RV64IF-NEXT: fsw ft0, 32(a0)
; RV64IF-NEXT: ret
; CHECKIF-LABEL: fsw:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fadd.s ft0, fa0, fa1
; CHECKIF-NEXT: fsw ft0, 0(a0)
; CHECKIF-NEXT: fsw ft0, 32(a0)
; CHECKIF-NEXT: ret
%1 = fadd float %b, %c
store float %1, float* %a
%2 = getelementptr float, float* %a, i32 8
Expand All @@ -56,27 +42,16 @@ define dso_local void @fsw(float *%a, float %b, float %c) nounwind {
define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
; Use %a and %b in an FP op to ensure floating point registers are used, even
; for the soft float ABI
; RV32IF-LABEL: flw_fsw_global:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fadd.s fa0, fa0, fa1
; RV32IF-NEXT: lui a0, %hi(G)
; RV32IF-NEXT: flw ft0, %lo(G)(a0)
; RV32IF-NEXT: addi a1, a0, %lo(G)
; RV32IF-NEXT: fsw fa0, %lo(G)(a0)
; RV32IF-NEXT: flw ft0, 36(a1)
; RV32IF-NEXT: fsw fa0, 36(a1)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: flw_fsw_global:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fadd.s fa0, fa0, fa1
; RV64IF-NEXT: lui a0, %hi(G)
; RV64IF-NEXT: flw ft0, %lo(G)(a0)
; RV64IF-NEXT: addi a1, a0, %lo(G)
; RV64IF-NEXT: fsw fa0, %lo(G)(a0)
; RV64IF-NEXT: flw ft0, 36(a1)
; RV64IF-NEXT: fsw fa0, 36(a1)
; RV64IF-NEXT: ret
; CHECKIF-LABEL: flw_fsw_global:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: fadd.s fa0, fa0, fa1
; CHECKIF-NEXT: lui a0, %hi(G)
; CHECKIF-NEXT: flw ft0, %lo(G)(a0)
; CHECKIF-NEXT: addi a1, a0, %lo(G)
; CHECKIF-NEXT: fsw fa0, %lo(G)(a0)
; CHECKIF-NEXT: flw ft0, 36(a1)
; CHECKIF-NEXT: fsw fa0, 36(a1)
; CHECKIF-NEXT: ret
%1 = fadd float %a, %b
%2 = load volatile float, float* @G
store float %1, float* @G
Expand Down
254 changes: 82 additions & 172 deletions llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
View file
Original file line number Diff line number Diff line change
@@ -1,27 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RV32IF %s
; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIF,RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
; RUN: -target-abi=lp64f | FileCheck -check-prefix=RV64IF %s
; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIF,RV64IF %s

define signext i32 @test_floor_si32(float %x) {
; RV32IF-LABEL: test_floor_si32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB0_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn
; RV32IF-NEXT: .LBB0_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_floor_si32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB0_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn
; RV64IF-NEXT: .LBB0_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: test_floor_si32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB0_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.w.s a0, fa0, rdn
; CHECKIF-NEXT: .LBB0_2:
; CHECKIF-NEXT: ret
%a = call float @llvm.floor.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %b
Expand Down Expand Up @@ -98,23 +89,14 @@ define i64 @test_floor_si64(float %x) nounwind {
}

define signext i32 @test_floor_ui32(float %x) {
; RV32IF-LABEL: test_floor_ui32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB2_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn
; RV32IF-NEXT: .LBB2_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_floor_ui32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB2_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rdn
; RV64IF-NEXT: .LBB2_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: test_floor_ui32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB2_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rdn
; CHECKIF-NEXT: .LBB2_2:
; CHECKIF-NEXT: ret
%a = call float @llvm.floor.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %b
Expand Down Expand Up @@ -178,23 +160,14 @@ define i64 @test_floor_ui64(float %x) nounwind {
}

define signext i32 @test_ceil_si32(float %x) {
; RV32IF-LABEL: test_ceil_si32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB4_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rup
; RV32IF-NEXT: .LBB4_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_ceil_si32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB4_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rup
; RV64IF-NEXT: .LBB4_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: test_ceil_si32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB4_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.w.s a0, fa0, rup
; CHECKIF-NEXT: .LBB4_2:
; CHECKIF-NEXT: ret
%a = call float @llvm.ceil.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %b
Expand Down Expand Up @@ -271,23 +244,14 @@ define i64 @test_ceil_si64(float %x) nounwind {
}

define signext i32 @test_ceil_ui32(float %x) {
; RV32IF-LABEL: test_ceil_ui32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB6_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup
; RV32IF-NEXT: .LBB6_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_ceil_ui32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB6_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rup
; RV64IF-NEXT: .LBB6_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: test_ceil_ui32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB6_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rup
; CHECKIF-NEXT: .LBB6_2:
; CHECKIF-NEXT: ret
%a = call float @llvm.ceil.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %b
Expand Down Expand Up @@ -351,23 +315,14 @@ define i64 @test_ceil_ui64(float %x) nounwind {
}

define signext i32 @test_trunc_si32(float %x) {
; RV32IF-LABEL: test_trunc_si32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB8_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV32IF-NEXT: .LBB8_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_trunc_si32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB8_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
; RV64IF-NEXT: .LBB8_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: test_trunc_si32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB8_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.w.s a0, fa0, rtz
; CHECKIF-NEXT: .LBB8_2:
; CHECKIF-NEXT: ret
%a = call float @llvm.trunc.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %b
Expand Down Expand Up @@ -444,23 +399,14 @@ define i64 @test_trunc_si64(float %x) nounwind {
}

define signext i32 @test_trunc_ui32(float %x) {
; RV32IF-LABEL: test_trunc_ui32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB10_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV32IF-NEXT: .LBB10_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_trunc_ui32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB10_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
; RV64IF-NEXT: .LBB10_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: test_trunc_ui32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB10_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rtz
; CHECKIF-NEXT: .LBB10_2:
; CHECKIF-NEXT: ret
%a = call float @llvm.trunc.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %b
Expand Down Expand Up @@ -524,23 +470,14 @@ define i64 @test_trunc_ui64(float %x) nounwind {
}

define signext i32 @test_round_si32(float %x) {
; RV32IF-LABEL: test_round_si32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB12_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
; RV32IF-NEXT: .LBB12_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_round_si32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB12_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm
; RV64IF-NEXT: .LBB12_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: test_round_si32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB12_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.w.s a0, fa0, rmm
; CHECKIF-NEXT: .LBB12_2:
; CHECKIF-NEXT: ret
%a = call float @llvm.round.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %b
Expand Down Expand Up @@ -617,23 +554,14 @@ define i64 @test_round_si64(float %x) nounwind {
}

define signext i32 @test_round_ui32(float %x) {
; RV32IF-LABEL: test_round_ui32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB14_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rmm
; RV32IF-NEXT: .LBB14_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_round_ui32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB14_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rmm
; RV64IF-NEXT: .LBB14_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: test_round_ui32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB14_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rmm
; CHECKIF-NEXT: .LBB14_2:
; CHECKIF-NEXT: ret
%a = call float @llvm.round.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %b
Expand Down Expand Up @@ -697,23 +625,14 @@ define i64 @test_round_ui64(float %x) nounwind {
}

define signext i32 @test_roundeven_si32(float %x) {
; RV32IF-LABEL: test_roundeven_si32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB16_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rne
; RV32IF-NEXT: .LBB16_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_roundeven_si32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB16_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rne
; RV64IF-NEXT: .LBB16_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: test_roundeven_si32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB16_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.w.s a0, fa0, rne
; CHECKIF-NEXT: .LBB16_2:
; CHECKIF-NEXT: ret
%a = call float @llvm.roundeven.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
ret i32 %b
Expand Down Expand Up @@ -790,23 +709,14 @@ define i64 @test_roundeven_si64(float %x) nounwind {
}

define signext i32 @test_roundeven_ui32(float %x) {
; RV32IF-LABEL: test_roundeven_ui32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
; RV32IF-NEXT: beqz a0, .LBB18_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rne
; RV32IF-NEXT: .LBB18_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_roundeven_ui32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
; RV64IF-NEXT: beqz a0, .LBB18_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rne
; RV64IF-NEXT: .LBB18_2:
; RV64IF-NEXT: ret
; CHECKIF-LABEL: test_roundeven_ui32:
; CHECKIF: # %bb.0:
; CHECKIF-NEXT: feq.s a0, fa0, fa0
; CHECKIF-NEXT: beqz a0, .LBB18_2
; CHECKIF-NEXT: # %bb.1:
; CHECKIF-NEXT: fcvt.wu.s a0, fa0, rne
; CHECKIF-NEXT: .LBB18_2:
; CHECKIF-NEXT: ret
%a = call float @llvm.roundeven.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
ret i32 %b
Expand Down
426 changes: 137 additions & 289 deletions llvm/test/CodeGen/RISCV/float-select-fcmp.ll
View file

Large diffs are not rendered by default.

185 changes: 58 additions & 127 deletions llvm/test/CodeGen/RISCV/half-arith-strict.ll
View file
Original file line number Diff line number Diff line change
@@ -1,84 +1,57 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: -disable-strictnode-mutation -target-abi ilp32f < %s \
; RUN: | FileCheck -check-prefix=RV32IZFH %s
; RUN: -disable-strictnode-mutation -target-abi ilp32f < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -disable-strictnode-mutation -target-abi lp64f < %s \
; RUN: | FileCheck -check-prefix=RV64IZFH %s
; RUN: -disable-strictnode-mutation -target-abi lp64f < %s | FileCheck %s

; FIXME: We can't test without Zfh because soft promote legalization isn't
; implemented in SelectionDAG for STRICT nodes.

define half @fadd_h(half %a, half %b) nounwind strictfp {
; RV32IZFH-LABEL: fadd_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fadd_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fadd_h:
; CHECK: # %bb.0:
; CHECK-NEXT: fadd.h fa0, fa0, fa1
; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.fadd.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
declare half @llvm.experimental.constrained.fadd.f16(half, half, metadata, metadata)

define half @fsub_h(half %a, half %b) nounwind strictfp {
; RV32IZFH-LABEL: fsub_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fsub.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fsub_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fsub.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fsub_h:
; CHECK: # %bb.0:
; CHECK-NEXT: fsub.h fa0, fa0, fa1
; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.fsub.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
declare half @llvm.experimental.constrained.fsub.f16(half, half, metadata, metadata)

define half @fmul_h(half %a, half %b) nounwind strictfp {
; RV32IZFH-LABEL: fmul_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmul.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fmul_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmul.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fmul_h:
; CHECK: # %bb.0:
; CHECK-NEXT: fmul.h fa0, fa0, fa1
; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.fmul.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
declare half @llvm.experimental.constrained.fmul.f16(half, half, metadata, metadata)

define half @fdiv_h(half %a, half %b) nounwind strictfp {
; RV32IZFH-LABEL: fdiv_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fdiv.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fdiv_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fdiv.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fdiv_h:
; CHECK: # %bb.0:
; CHECK-NEXT: fdiv.h fa0, fa0, fa1
; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.fdiv.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
declare half @llvm.experimental.constrained.fdiv.f16(half, half, metadata, metadata)

define half @fsqrt_h(half %a) nounwind strictfp {
; RV32IZFH-LABEL: fsqrt_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fsqrt.h fa0, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fsqrt_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fsqrt.h fa0, fa0
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fsqrt_h:
; CHECK: # %bb.0:
; CHECK-NEXT: fsqrt.h fa0, fa0
; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
Expand All @@ -99,56 +72,36 @@ declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
;declare half @llvm.experimental.constrained.maxnum.f16(half, half, metadata) strictfp

define half @fmadd_h(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fmadd_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fmadd_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fmadd_h:
; CHECK: # %bb.0:
; CHECK-NEXT: fmadd.h fa0, fa0, fa1, fa2
; CHECK-NEXT: ret
%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}
declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) strictfp

define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fmsub_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fmsub_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fmsub_h:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.h.x ft0, zero
; CHECK-NEXT: fadd.h ft0, fa2, ft0
; CHECK-NEXT: fmsub.h fa0, fa0, fa1, ft0
; CHECK-NEXT: ret
%c_ = fadd half 0.0, %c ; avoid negation using xor
%negc = fneg half %c_
%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}

define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmadd_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero
; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmadd_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero
; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fnmadd_h:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.h.x ft0, zero
; CHECK-NEXT: fadd.h ft1, fa0, ft0
; CHECK-NEXT: fadd.h ft0, fa2, ft0
; CHECK-NEXT: fnmadd.h fa0, ft1, fa1, ft0
; CHECK-NEXT: ret
%a_ = fadd half 0.0, %a
%c_ = fadd half 0.0, %c
%nega = fneg half %a_
Expand All @@ -158,21 +111,13 @@ define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
}

define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmadd_h_2:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero
; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmadd_h_2:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero
; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fnmadd_h_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.h.x ft0, zero
; CHECK-NEXT: fadd.h ft1, fa1, ft0
; CHECK-NEXT: fadd.h ft0, fa2, ft0
; CHECK-NEXT: fnmadd.h fa0, ft1, fa0, ft0
; CHECK-NEXT: ret
%b_ = fadd half 0.0, %b
%c_ = fadd half 0.0, %c
%negb = fneg half %b_
Expand All @@ -182,39 +127,25 @@ define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
}

define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmsub_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero
; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0
; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmsub_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero
; RV64IZFH-NEXT: fadd.h ft0, fa0, ft0
; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fnmsub_h:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.h.x ft0, zero
; CHECK-NEXT: fadd.h ft0, fa0, ft0
; CHECK-NEXT: fnmsub.h fa0, ft0, fa1, fa2
; CHECK-NEXT: ret
%a_ = fadd half 0.0, %a
%nega = fneg half %a_
%1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
ret half %1
}

define half @fnmsub_h_2(half %a, half %b, half %c) nounwind strictfp {
; RV32IZFH-LABEL: fnmsub_h_2:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero
; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmsub_h_2:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x ft0, zero
; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
; RV64IZFH-NEXT: ret
; CHECK-LABEL: fnmsub_h_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.h.x ft0, zero
; CHECK-NEXT: fadd.h ft0, fa1, ft0
; CHECK-NEXT: fnmsub.h fa0, ft0, fa0, fa2
; CHECK-NEXT: ret
%b_ = fadd half 0.0, %b
%negb = fneg half %b_
%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
Expand Down
355 changes: 112 additions & 243 deletions llvm/test/CodeGen/RISCV/half-arith.ll
View file

Large diffs are not rendered by default.

152 changes: 48 additions & 104 deletions llvm/test/CodeGen/RISCV/half-convert-strict.ll
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f -disable-strictnode-mutation < %s \
; RUN: | FileCheck -check-prefix=RV32IZFH %s
; RUN: | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f -disable-strictnode-mutation < %s \
; RUN: | FileCheck -check-prefix=RV64IZFH %s
; RUN: | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32d -disable-strictnode-mutation < %s \
; RUN: | FileCheck -check-prefix=RV32IDZFH %s
Expand Down Expand Up @@ -67,15 +67,10 @@ define i16 @fcvt_ui_h(half %a) nounwind strictfp {
declare i16 @llvm.experimental.constrained.fptoui.i16.f16(half, metadata)

define i32 @fcvt_w_h(half %a) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_w_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_w_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_w_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_h:
; RV32IDZFH: # %bb.0:
Expand All @@ -92,15 +87,10 @@ define i32 @fcvt_w_h(half %a) nounwind strictfp {
declare i32 @llvm.experimental.constrained.fptosi.i32.f16(half, metadata)

define i32 @fcvt_wu_h(half %a) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_wu_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_wu_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_wu_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h:
; RV32IDZFH: # %bb.0:
Expand All @@ -120,25 +110,15 @@ declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
; inserted on RV64.
; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.
define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) {
; RV32IZFH-LABEL: fcvt_wu_h_multiple_use:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
; RV32IZFH-NEXT: li a0, 1
; RV32IZFH-NEXT: beqz a1, .LBB4_2
; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: mv a0, a1
; RV32IZFH-NEXT: .LBB4_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_wu_h_multiple_use:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
; RV64IZFH-NEXT: li a0, 1
; RV64IZFH-NEXT: beqz a1, .LBB4_2
; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: mv a0, a1
; RV64IZFH-NEXT: .LBB4_2:
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.wu.h a1, fa0, rtz
; CHECKIZFH-NEXT: li a0, 1
; CHECKIZFH-NEXT: beqz a1, .LBB4_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: mv a0, a1
; CHECKIZFH-NEXT: .LBB4_2:
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -265,15 +245,10 @@ define half @fcvt_h_si(i16 %a) nounwind strictfp {
declare half @llvm.experimental.constrained.sitofp.f16.i16(i16, metadata, metadata)

define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_h_si_signext:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_si_signext:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_si_signext:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_si_signext:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -322,15 +297,10 @@ define half @fcvt_h_ui(i16 %a) nounwind strictfp {
declare half @llvm.experimental.constrained.uitofp.f16.i16(i16, metadata, metadata)

define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_h_ui_zeroext:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
; RV32IDZFH: # %bb.0:
Expand All @@ -346,15 +316,10 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
}

define half @fcvt_h_w(i32 %a) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_h_w:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_w:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_w:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w:
; RV32IDZFH: # %bb.0:
Expand All @@ -371,17 +336,11 @@ define half @fcvt_h_w(i32 %a) nounwind strictfp {
declare half @llvm.experimental.constrained.sitofp.f16.i32(i32, metadata, metadata)

define half @fcvt_h_w_load(i32* %p) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_h_w_load:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: lw a0, 0(a0)
; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_w_load:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lw a0, 0(a0)
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_w_load:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: lw a0, 0(a0)
; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w_load:
; RV32IDZFH: # %bb.0:
Expand All @@ -400,15 +359,10 @@ define half @fcvt_h_w_load(i32* %p) nounwind strictfp {
}

define half @fcvt_h_wu(i32 %a) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_h_wu:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_wu:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_wu:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_wu:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -520,15 +474,10 @@ define half @fcvt_h_lu(i64 %a) nounwind strictfp {
declare half @llvm.experimental.constrained.uitofp.f16.i64(i64, metadata, metadata)

define half @fcvt_h_s(float %a) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_h_s:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_s:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_s:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.h.s fa0, fa0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_s:
; RV32IDZFH: # %bb.0:
Expand All @@ -545,15 +494,10 @@ define half @fcvt_h_s(float %a) nounwind strictfp {
declare half @llvm.experimental.constrained.fptrunc.f16.f32(float, metadata, metadata)

define float @fcvt_s_h(half %a) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_s_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_s_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_s_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.s.h fa0, fa0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_s_h:
; RV32IDZFH: # %bb.0:
Expand Down
228 changes: 72 additions & 156 deletions llvm/test/CodeGen/RISCV/half-convert.ll
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs \
Expand Down Expand Up @@ -405,15 +405,10 @@ start:
declare i16 @llvm.fptoui.sat.i16.f16(half)

define i32 @fcvt_w_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_w_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_w_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_w_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_h:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -453,23 +448,14 @@ define i32 @fcvt_w_h(half %a) nounwind {
}

define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_w_h_sat:
; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
; RV32IZFH-NEXT: beqz a0, .LBB5_2
; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IZFH-NEXT: .LBB5_2: # %start
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_w_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
; RV64IZFH-NEXT: beqz a0, .LBB5_2
; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV64IZFH-NEXT: .LBB5_2: # %start
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_w_h_sat:
; CHECKIZFH: # %bb.0: # %start
; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
; CHECKIZFH-NEXT: beqz a0, .LBB5_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
; CHECKIZFH-NEXT: .LBB5_2: # %start
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_h_sat:
; RV32IDZFH: # %bb.0: # %start
Expand Down Expand Up @@ -595,15 +581,10 @@ start:
declare i32 @llvm.fptosi.sat.i32.f16(half)

define i32 @fcvt_wu_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_wu_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_wu_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_wu_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -645,25 +626,15 @@ define i32 @fcvt_wu_h(half %a) nounwind {
; Test where the fptoui has multiple uses, one of which causes a sext to be
; inserted on RV64.
define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) nounwind {
; RV32IZFH-LABEL: fcvt_wu_h_multiple_use:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
; RV32IZFH-NEXT: li a0, 1
; RV32IZFH-NEXT: beqz a1, .LBB7_2
; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: mv a0, a1
; RV32IZFH-NEXT: .LBB7_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_wu_h_multiple_use:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.wu.h a1, fa0, rtz
; RV64IZFH-NEXT: li a0, 1
; RV64IZFH-NEXT: beqz a1, .LBB7_2
; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: mv a0, a1
; RV64IZFH-NEXT: .LBB7_2:
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.wu.h a1, fa0, rtz
; CHECKIZFH-NEXT: li a0, 1
; CHECKIZFH-NEXT: beqz a1, .LBB7_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: mv a0, a1
; CHECKIZFH-NEXT: .LBB7_2:
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -727,23 +698,14 @@ define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) nounwind {
}

define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_wu_h_sat:
; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
; RV32IZFH-NEXT: beqz a0, .LBB8_2
; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV32IZFH-NEXT: .LBB8_2: # %start
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_wu_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
; RV64IZFH-NEXT: beqz a0, .LBB8_2
; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; RV64IZFH-NEXT: .LBB8_2: # %start
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_wu_h_sat:
; CHECKIZFH: # %bb.0: # %start
; CHECKIZFH-NEXT: feq.h a0, fa0, fa0
; CHECKIZFH-NEXT: beqz a0, .LBB8_2
; CHECKIZFH-NEXT: # %bb.1:
; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
; CHECKIZFH-NEXT: .LBB8_2: # %start
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h_sat:
; RV32IDZFH: # %bb.0: # %start
Expand Down Expand Up @@ -1493,15 +1455,10 @@ define half @fcvt_h_si(i16 %a) nounwind {
}

define half @fcvt_h_si_signext(i16 signext %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_si_signext:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_si_signext:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_si_signext:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_si_signext:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1593,15 +1550,10 @@ define half @fcvt_h_ui(i16 %a) nounwind {
}

define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_ui_zeroext:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_ui_zeroext:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1637,15 +1589,10 @@ define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
}

define half @fcvt_h_w(i32 %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_w:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_w:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_w:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1682,17 +1629,11 @@ define half @fcvt_h_w(i32 %a) nounwind {
}

define half @fcvt_h_w_load(i32* %p) nounwind {
; RV32IZFH-LABEL: fcvt_h_w_load:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: lw a0, 0(a0)
; RV32IZFH-NEXT: fcvt.h.w fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_w_load:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lw a0, 0(a0)
; RV64IZFH-NEXT: fcvt.h.w fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_w_load:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: lw a0, 0(a0)
; CHECKIZFH-NEXT: fcvt.h.w fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_w_load:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1733,15 +1674,10 @@ define half @fcvt_h_w_load(i32* %p) nounwind {
}

define half @fcvt_h_wu(i32 %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_wu:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.h.wu fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_wu:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_wu:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.h.wu fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_wu:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1933,15 +1869,10 @@ define half @fcvt_h_lu(i64 %a) nounwind {
}

define half @fcvt_h_s(float %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_s:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_h_s:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_h_s:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.h.s fa0, fa0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_s:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1975,15 +1906,10 @@ define half @fcvt_h_s(float %a) nounwind {
}

define float @fcvt_s_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_s_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_s_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fcvt_s_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fcvt.s.h fa0, fa0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_s_h:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -2131,15 +2057,10 @@ define double @fcvt_d_h(half %a) nounwind {
}

define half @bitcast_h_i16(i16 %a) nounwind {
; RV32IZFH-LABEL: bitcast_h_i16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x fa0, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: bitcast_h_i16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.h.x fa0, a0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: bitcast_h_i16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmv.h.x fa0, a0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: bitcast_h_i16:
; RV32IDZFH: # %bb.0:
Expand All @@ -2163,15 +2084,10 @@ define half @bitcast_h_i16(i16 %a) nounwind {
}

define i16 @bitcast_i16_h(half %a) nounwind {
; RV32IZFH-LABEL: bitcast_i16_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.x.h a0, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: bitcast_i16_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmv.x.h a0, fa0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: bitcast_i16_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmv.x.h a0, fa0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: bitcast_i16_h:
; RV32IDZFH: # %bb.0:
Expand Down
580 changes: 184 additions & 396 deletions llvm/test/CodeGen/RISCV/half-fcmp-strict.ll
View file

Large diffs are not rendered by default.

257 changes: 81 additions & 176 deletions llvm/test/CodeGen/RISCV/half-fcmp.ll
View file
Original file line number Diff line number Diff line change
@@ -1,23 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: < %s | FileCheck -check-prefix=RV64I %s

define i32 @fcmp_false(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_false:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: li a0, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_false:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: li a0, 0
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_false:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: li a0, 0
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_false:
; RV32I: # %bb.0:
Expand All @@ -34,15 +29,10 @@ define i32 @fcmp_false(half %a, half %b) nounwind {
}

define i32 @fcmp_oeq(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_oeq:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_oeq:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_oeq:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: feq.h a0, fa0, fa1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
Expand All @@ -63,15 +53,10 @@ define i32 @fcmp_oeq(half %a, half %b) nounwind {
}

define i32 @fcmp_ogt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ogt:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa1, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_ogt:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_ogt:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: flt.h a0, fa1, fa0
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
Expand All @@ -92,15 +77,10 @@ define i32 @fcmp_ogt(half %a, half %b) nounwind {
}

define i32 @fcmp_oge(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_oge:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fle.h a0, fa1, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_oge:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_oge:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: fle.h a0, fa1, fa0
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
Expand All @@ -121,15 +101,10 @@ define i32 @fcmp_oge(half %a, half %b) nounwind {
}

define i32 @fcmp_olt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_olt:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_olt:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_olt:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
Expand All @@ -150,15 +125,10 @@ define i32 @fcmp_olt(half %a, half %b) nounwind {
}

define i32 @fcmp_ole(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ole:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fle.h a0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_ole:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_ole:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: fle.h a0, fa0, fa1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
Expand All @@ -179,19 +149,12 @@ define i32 @fcmp_ole(half %a, half %b) nounwind {
}

define i32 @fcmp_one(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_one:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: flt.h a1, fa1, fa0
; RV32IZFH-NEXT: or a0, a1, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_one:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_one:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
;CHECKIZFH-NEXT: flt.h a1, fa1, fa0
;CHECKIZFH-NEXT: or a0, a1, a0
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
Expand All @@ -216,19 +179,12 @@ define i32 @fcmp_one(half %a, half %b) nounwind {
}

define i32 @fcmp_ord(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ord:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa1, fa1
; RV32IZFH-NEXT: feq.h a1, fa0, fa0
; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_ord:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa1, fa1
; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_ord:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: feq.h a0, fa1, fa1
;CHECKIZFH-NEXT: feq.h a1, fa0, fa0
;CHECKIZFH-NEXT: and a0, a1, a0
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
Expand All @@ -253,21 +209,13 @@ define i32 @fcmp_ord(half %a, half %b) nounwind {
}

define i32 @fcmp_ueq(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ueq:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: flt.h a1, fa1, fa0
; RV32IZFH-NEXT: or a0, a1, a0
; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_ueq:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_ueq:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
;CHECKIZFH-NEXT: flt.h a1, fa1, fa0
;CHECKIZFH-NEXT: or a0, a1, a0
;CHECKIZFH-NEXT: xori a0, a0, 1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
Expand All @@ -294,17 +242,11 @@ define i32 @fcmp_ueq(half %a, half %b) nounwind {
}

define i32 @fcmp_ugt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ugt:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fle.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_ugt:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_ugt:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: fle.h a0, fa0, fa1
;CHECKIZFH-NEXT: xori a0, a0, 1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
Expand All @@ -327,17 +269,11 @@ define i32 @fcmp_ugt(half %a, half %b) nounwind {
}

define i32 @fcmp_uge(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_uge:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_uge:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_uge:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
;CHECKIZFH-NEXT: xori a0, a0, 1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
Expand All @@ -360,17 +296,11 @@ define i32 @fcmp_uge(half %a, half %b) nounwind {
}

define i32 @fcmp_ult(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ult:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fle.h a0, fa1, fa0
; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_ult:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_ult:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: fle.h a0, fa1, fa0
;CHECKIZFH-NEXT: xori a0, a0, 1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
Expand All @@ -393,17 +323,11 @@ define i32 @fcmp_ult(half %a, half %b) nounwind {
}

define i32 @fcmp_ule(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ule:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flt.h a0, fa1, fa0
; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_ule:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_ule:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: flt.h a0, fa1, fa0
;CHECKIZFH-NEXT: xori a0, a0, 1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
Expand All @@ -426,17 +350,11 @@ define i32 @fcmp_ule(half %a, half %b) nounwind {
}

define i32 @fcmp_une(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_une:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_une:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_une:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: feq.h a0, fa0, fa1
;CHECKIZFH-NEXT: xori a0, a0, 1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
Expand All @@ -459,21 +377,13 @@ define i32 @fcmp_une(half %a, half %b) nounwind {
}

define i32 @fcmp_uno(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_uno:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa1, fa1
; RV32IZFH-NEXT: feq.h a1, fa0, fa0
; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_uno:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa1, fa1
; RV64IZFH-NEXT: feq.h a1, fa0, fa0
; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_uno:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: feq.h a0, fa1, fa1
;CHECKIZFH-NEXT: feq.h a1, fa0, fa0
;CHECKIZFH-NEXT: and a0, a1, a0
;CHECKIZFH-NEXT: xori a0, a0, 1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
Expand All @@ -500,15 +410,10 @@ define i32 @fcmp_uno(half %a, half %b) nounwind {
}

define i32 @fcmp_true(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_true:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: li a0, 1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_true:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: li a0, 1
; RV64IZFH-NEXT: ret
;CHECKIZFH-LABEL: fcmp_true:
;CHECKIZFH: # %bb.0:
;CHECKIZFH-NEXT: li a0, 1
;CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_true:
; RV32I: # %bb.0:
Expand Down
39 changes: 13 additions & 26 deletions llvm/test/CodeGen/RISCV/half-imm.ll
View file
Original file line number Diff line number Diff line change
@@ -1,39 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: -target-abi ilp32f < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
; RUN: -target-abi lp64f < %s | FileCheck %s

; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
define half @half_imm() nounwind {
; RV32IZFH-LABEL: half_imm:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI0_0)
; RV32IZFH-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: half_imm:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI0_0)
; RV64IZFH-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; RV64IZFH-NEXT: ret
; CHECK-LABEL: half_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: ret
ret half 3.0
}

define half @half_imm_op(half %a) nounwind {
; RV32IZFH-LABEL: half_imm_op:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
; RV32IZFH-NEXT: fadd.h fa0, fa0, ft0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: half_imm_op:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
; RV64IZFH-NEXT: fadd.h fa0, fa0, ft0
; RV64IZFH-NEXT: ret
; CHECK-LABEL: half_imm_op:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
%1 = fadd half %a, 1.0
ret half %1
}
95 changes: 30 additions & 65 deletions llvm/test/CodeGen/RISCV/half-intrinsics.ll
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
; RUN: -verify-machineinstrs -target-abi ilp32f | \
; RUN: FileCheck -check-prefix=RV32IZFH %s
; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
; RUN: -verify-machineinstrs -target-abi lp64f | \
; RUN: FileCheck -check-prefix=RV64IZFH %s
; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
; RUN: FileCheck -check-prefix=RV32IDZFH %s
Expand All @@ -21,15 +21,10 @@
declare half @llvm.sqrt.f16(half)

define half @sqrt_f16(half %a) nounwind {
; RV32IZFH-LABEL: sqrt_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fsqrt.h fa0, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: sqrt_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fsqrt.h fa0, fa0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: sqrt_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fsqrt.h fa0, fa0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: sqrt_f16:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -954,15 +949,10 @@ define half @log2_f16(half %a) nounwind {
declare half @llvm.fma.f16(half, half, half)

define half @fma_f16(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fma_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fma_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fma_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fma_f16:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1046,15 +1036,10 @@ define half @fma_f16(half %a, half %b, half %c) nounwind {
declare half @llvm.fmuladd.f16(half, half, half)

define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fmuladd_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fmuladd_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fmuladd_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fmuladd_f16:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1148,15 +1133,10 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
declare half @llvm.fabs.f16(half)

define half @fabs_f16(half %a) nounwind {
; RV32IZFH-LABEL: fabs_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fabs.h fa0, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fabs_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fabs.h fa0, fa0
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fabs_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fabs.h fa0, fa0
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fabs_f16:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1186,15 +1166,10 @@ define half @fabs_f16(half %a) nounwind {
declare half @llvm.minnum.f16(half, half)

define half @minnum_f16(half %a, half %b) nounwind {
; RV32IZFH-LABEL: minnum_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmin.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: minnum_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmin.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: minnum_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: minnum_f16:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1264,15 +1239,10 @@ define half @minnum_f16(half %a, half %b) nounwind {
declare half @llvm.maxnum.f16(half, half)

define half @maxnum_f16(half %a, half %b) nounwind {
; RV32IZFH-LABEL: maxnum_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmax.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: maxnum_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmax.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: maxnum_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: maxnum_f16:
; RV32IDZFH: # %bb.0:
Expand Down Expand Up @@ -1359,15 +1329,10 @@ define half @maxnum_f16(half %a, half %b) nounwind {
declare half @llvm.copysign.f16(half, half)

define half @copysign_f16(half %a, half %b) nounwind {
; RV32IZFH-LABEL: copysign_f16:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: copysign_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fsgnj.h fa0, fa0, fa1
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: copysign_f16:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fsgnj.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
; RV32IDZFH-LABEL: copysign_f16:
; RV32IDZFH: # %bb.0:
Expand Down
33 changes: 11 additions & 22 deletions llvm/test/CodeGen/RISCV/half-isnan.ll
View file
Original file line number Diff line number Diff line change
@@ -1,35 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: -target-abi ilp32f < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
; RUN: -target-abi lp64f < %s | FileCheck %s

define zeroext i1 @half_is_nan(half %a) nounwind {
; RV32IZFH-LABEL: half_is_nan:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: half_is_nan:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: ret
; CHECK-LABEL: half_is_nan:
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa0
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%1 = fcmp uno half %a, 0.000000e+00
ret i1 %1
}

define zeroext i1 @half_not_nan(half %a) nounwind {
; RV32IZFH-LABEL: half_not_nan:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: half_not_nan:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
; RV64IZFH-NEXT: ret
; CHECK-LABEL: half_not_nan:
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa0
; CHECK-NEXT: ret
%1 = fcmp ord half %a, 0.000000e+00
ret i1 %1
}
73 changes: 24 additions & 49 deletions llvm/test/CodeGen/RISCV/half-mem.ll
View file
Original file line number Diff line number Diff line change
@@ -1,23 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s

define half @flh(half *%a) nounwind {
; RV32IZFH-LABEL: flh:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: flh ft0, 0(a0)
; RV32IZFH-NEXT: flh ft1, 6(a0)
; RV32IZFH-NEXT: fadd.h fa0, ft0, ft1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: flh:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: flh ft0, 0(a0)
; RV64IZFH-NEXT: flh ft1, 6(a0)
; RV64IZFH-NEXT: fadd.h fa0, ft0, ft1
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: flh:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: flh ft0, 0(a0)
; CHECKIZFH-NEXT: flh ft1, 6(a0)
; CHECKIZFH-NEXT: fadd.h fa0, ft0, ft1
; CHECKIZFH-NEXT: ret
%1 = load half, half* %a
%2 = getelementptr half, half* %a, i32 3
%3 = load half, half* %2
Expand All @@ -30,19 +23,12 @@ define half @flh(half *%a) nounwind {
define dso_local void @fsh(half *%a, half %b, half %c) nounwind {
; Use %b and %c in an FP op to ensure half precision floating point registers
; are used, even for the soft half ABI
; RV32IZFH-LABEL: fsh:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
; RV32IZFH-NEXT: fsh ft0, 0(a0)
; RV32IZFH-NEXT: fsh ft0, 16(a0)
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fsh:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
; RV64IZFH-NEXT: fsh ft0, 0(a0)
; RV64IZFH-NEXT: fsh ft0, 16(a0)
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: fsh:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fadd.h ft0, fa0, fa1
; CHECKIZFH-NEXT: fsh ft0, 0(a0)
; CHECKIZFH-NEXT: fsh ft0, 16(a0)
; CHECKIZFH-NEXT: ret
%1 = fadd half %b, %c
store half %1, half* %a
%2 = getelementptr half, half* %a, i32 8
Expand All @@ -56,27 +42,16 @@ define dso_local void @fsh(half *%a, half %b, half %c) nounwind {
define half @flh_fsh_global(half %a, half %b) nounwind {
; Use %a and %b in an FP op to ensure half precision floating point registers
; are used, even for the soft half ABI
; RV32IZFH-LABEL: flh_fsh_global:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV32IZFH-NEXT: lui a0, %hi(G)
; RV32IZFH-NEXT: flh ft0, %lo(G)(a0)
; RV32IZFH-NEXT: addi a1, a0, %lo(G)
; RV32IZFH-NEXT: fsh fa0, %lo(G)(a0)
; RV32IZFH-NEXT: flh ft0, 18(a1)
; RV32IZFH-NEXT: fsh fa0, 18(a1)
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: flh_fsh_global:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
; RV64IZFH-NEXT: lui a0, %hi(G)
; RV64IZFH-NEXT: flh ft0, %lo(G)(a0)
; RV64IZFH-NEXT: addi a1, a0, %lo(G)
; RV64IZFH-NEXT: fsh fa0, %lo(G)(a0)
; RV64IZFH-NEXT: flh ft0, 18(a1)
; RV64IZFH-NEXT: fsh fa0, 18(a1)
; RV64IZFH-NEXT: ret
; CHECKIZFH-LABEL: flh_fsh_global:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fadd.h fa0, fa0, fa1
; CHECKIZFH-NEXT: lui a0, %hi(G)
; CHECKIZFH-NEXT: flh ft0, %lo(G)(a0)
; CHECKIZFH-NEXT: addi a1, a0, %lo(G)
; CHECKIZFH-NEXT: fsh fa0, %lo(G)(a0)
; CHECKIZFH-NEXT: flh ft0, 18(a1)
; CHECKIZFH-NEXT: fsh fa0, 18(a1)
; CHECKIZFH-NEXT: ret
%1 = fadd half %a, %b
%2 = load volatile half, half* @G
store half %1, half* @G
Expand Down
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