68 changes: 34 additions & 34 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -233,10 +233,10 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_v(<8 x float> inreg %v
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: v_mov_b32_e32 v16, s7
; MOVREL-NEXT: v_mov_b32_e32 v15, s6
; MOVREL-NEXT: v_mov_b32_e32 v14, s5
; MOVREL-NEXT: v_mov_b32_e32 v12, s3
; MOVREL-NEXT: v_mov_b32_e32 v13, s4
; MOVREL-NEXT: v_mov_b32_e32 v15, s6
; MOVREL-NEXT: v_mov_b32_e32 v12, s3
; MOVREL-NEXT: v_mov_b32_e32 v11, s2
; MOVREL-NEXT: v_mov_b32_e32 v10, s1
; MOVREL-NEXT: v_mov_b32_e32 v9, s0
Expand Down Expand Up @@ -400,10 +400,10 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_v(<8 x float> inreg %v
; MOVREL-NEXT: s_mov_b32 s4, s6
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: v_mov_b32_e32 v17, s7
; MOVREL-NEXT: v_mov_b32_e32 v16, s6
; MOVREL-NEXT: v_mov_b32_e32 v15, s5
; MOVREL-NEXT: v_mov_b32_e32 v13, s3
; MOVREL-NEXT: v_mov_b32_e32 v14, s4
; MOVREL-NEXT: v_mov_b32_e32 v16, s6
; MOVREL-NEXT: v_mov_b32_e32 v13, s3
; MOVREL-NEXT: v_mov_b32_e32 v12, s2
; MOVREL-NEXT: v_mov_b32_e32 v11, s1
; MOVREL-NEXT: v_mov_b32_e32 v10, s0
Expand Down Expand Up @@ -800,10 +800,10 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; MOVREL-NEXT: s_mov_b32 s18, 0
; MOVREL-NEXT: s_mov_b32 s19, 0x40200000
; MOVREL-NEXT: s_mov_b32 s17, 0x401c0000
; MOVREL-NEXT: s_mov_b32 s15, 0x40180000
; MOVREL-NEXT: s_mov_b32 s13, 0x40140000
; MOVREL-NEXT: s_mov_b32 s16, s18
; MOVREL-NEXT: s_mov_b32 s15, 0x40180000
; MOVREL-NEXT: s_mov_b32 s14, s18
; MOVREL-NEXT: s_mov_b32 s13, 0x40140000
; MOVREL-NEXT: s_mov_b32 s12, s18
; MOVREL-NEXT: s_mov_b64 s[10:11], 4.0
; MOVREL-NEXT: s_mov_b32 s9, 0x40080000
Expand Down Expand Up @@ -834,8 +834,8 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: s_lshl_b32 m0, s5, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s5, v2
; MOVREL-NEXT: s_lshl_b32 m0, s5, 1
; MOVREL-NEXT: v_mov_b32_e32 v7, v23
; MOVREL-NEXT: v_mov_b32_e32 v8, v24
; MOVREL-NEXT: v_mov_b32_e32 v9, v25
Expand Down Expand Up @@ -966,10 +966,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do
; MOVREL-NEXT: s_mov_b32 s12, s14
; MOVREL-NEXT: s_mov_b32 s14, s16
; MOVREL-NEXT: v_mov_b32_e32 v32, s15
; MOVREL-NEXT: v_mov_b32_e32 v31, s14
; MOVREL-NEXT: v_mov_b32_e32 v30, s13
; MOVREL-NEXT: v_mov_b32_e32 v28, s11
; MOVREL-NEXT: v_mov_b32_e32 v29, s12
; MOVREL-NEXT: v_mov_b32_e32 v31, s14
; MOVREL-NEXT: v_mov_b32_e32 v28, s11
; MOVREL-NEXT: v_mov_b32_e32 v27, s10
; MOVREL-NEXT: v_mov_b32_e32 v26, s9
; MOVREL-NEXT: v_mov_b32_e32 v25, s8
Expand All @@ -989,8 +989,8 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do
; MOVREL-NEXT: v_mov_b32_e32 v2, v18
; MOVREL-NEXT: v_mov_b32_e32 v3, v19
; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v0
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: v_mov_b32_e32 v7, v23
Expand Down Expand Up @@ -1095,8 +1095,8 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_s(<8 x double> inreg %vec, do
; MOVREL-NEXT: v_mov_b32_e32 v17, s15
; MOVREL-NEXT: v_mov_b32_e32 v2, s0
; MOVREL-NEXT: s_lshl_b32 m0, s18, 1
; MOVREL-NEXT: v_mov_b32_e32 v15, s13
; MOVREL-NEXT: v_mov_b32_e32 v16, s14
; MOVREL-NEXT: v_mov_b32_e32 v15, s13
; MOVREL-NEXT: v_mov_b32_e32 v14, s12
; MOVREL-NEXT: v_mov_b32_e32 v13, s11
; MOVREL-NEXT: v_mov_b32_e32 v12, s10
Expand Down Expand Up @@ -1260,10 +1260,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
; MOVREL-NEXT: s_mov_b32 s12, s14
; MOVREL-NEXT: s_mov_b32 s14, s16
; MOVREL-NEXT: v_mov_b32_e32 v34, s15
; MOVREL-NEXT: v_mov_b32_e32 v33, s14
; MOVREL-NEXT: v_mov_b32_e32 v32, s13
; MOVREL-NEXT: v_mov_b32_e32 v30, s11
; MOVREL-NEXT: v_mov_b32_e32 v31, s12
; MOVREL-NEXT: v_mov_b32_e32 v33, s14
; MOVREL-NEXT: v_mov_b32_e32 v30, s11
; MOVREL-NEXT: v_mov_b32_e32 v29, s10
; MOVREL-NEXT: v_mov_b32_e32 v28, s9
; MOVREL-NEXT: v_mov_b32_e32 v27, s8
Expand All @@ -1283,8 +1283,8 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v7, v23
; MOVREL-NEXT: v_mov_b32_e32 v8, v24
; MOVREL-NEXT: v_mov_b32_e32 v9, v25
Expand Down Expand Up @@ -1373,8 +1373,8 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_v(<8 x double> %vec, double i
; MOVREL-NEXT: v_mov_b32_e32 v17, v0
; MOVREL-NEXT: v_mov_b32_e32 v31, v14
; MOVREL-NEXT: v_mov_b32_e32 v30, v13
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v16
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v29, v12
; MOVREL-NEXT: v_mov_b32_e32 v28, v11
; MOVREL-NEXT: v_mov_b32_e32 v27, v10
Expand Down Expand Up @@ -1501,8 +1501,8 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v(<8 x double> %vec, double %
; MOVREL-NEXT: v_mov_b32_e32 v19, v0
; MOVREL-NEXT: v_mov_b32_e32 v33, v14
; MOVREL-NEXT: v_mov_b32_e32 v32, v13
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v31, v12
; MOVREL-NEXT: v_mov_b32_e32 v30, v11
; MOVREL-NEXT: v_mov_b32_e32 v29, v10
Expand Down Expand Up @@ -1557,8 +1557,8 @@ define amdgpu_ps <3 x i32> @dyn_insertelement_v3i32_s_s_s(<3 x i32> inreg %vec,
; MOVREL-NEXT: s_mov_b32 m0, s6
; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: s_movreld_b32 s0, s5
; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <3 x i32> %vec, i32 %val, i32 %idx
Expand Down Expand Up @@ -2135,10 +2135,10 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, do
; MOVREL-NEXT: v_mov_b32_e32 v32, v13
; MOVREL-NEXT: s_add_i32 s2, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v18
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: v_mov_b32_e32 v31, v12
; MOVREL-NEXT: v_mov_b32_e32 v30, v11
; MOVREL-NEXT: v_mov_b32_e32 v29, v10
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: v_mov_b32_e32 v28, v9
; MOVREL-NEXT: v_mov_b32_e32 v27, v8
; MOVREL-NEXT: v_mov_b32_e32 v26, v7
Expand Down Expand Up @@ -2696,10 +2696,10 @@ define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_v_s(<16 x i32> inreg %ve
; MOVREL-NEXT: s_mov_b32 s12, s14
; MOVREL-NEXT: s_mov_b32 s14, s16
; MOVREL-NEXT: v_mov_b32_e32 v16, s15
; MOVREL-NEXT: s_mov_b32 m0, s18
; MOVREL-NEXT: v_mov_b32_e32 v1, s0
; MOVREL-NEXT: v_mov_b32_e32 v14, s13
; MOVREL-NEXT: s_mov_b32 m0, s18
; MOVREL-NEXT: v_mov_b32_e32 v15, s14
; MOVREL-NEXT: v_mov_b32_e32 v14, s13
; MOVREL-NEXT: v_mov_b32_e32 v13, s12
; MOVREL-NEXT: v_mov_b32_e32 v12, s11
; MOVREL-NEXT: v_mov_b32_e32 v11, s10
Expand Down Expand Up @@ -2927,8 +2927,8 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32f32_s_v_s(<32 x float> inreg
; MOVREL-NEXT: s_mov_b32 s28, s30
; MOVREL-NEXT: s_mov_b32 s29, s31
; MOVREL-NEXT: s_mov_b32 s31, s33
; MOVREL-NEXT: s_mov_b32 s30, s32
; MOVREL-NEXT: v_mov_b32_e32 v32, v0
; MOVREL-NEXT: s_mov_b32 s30, s32
; MOVREL-NEXT: v_mov_b32_e32 v0, s0
; MOVREL-NEXT: s_mov_b32 m0, s34
; MOVREL-NEXT: v_mov_b32_e32 v1, s1
Expand Down Expand Up @@ -3113,8 +3113,8 @@ define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_v_s(<16 x i64> inreg %ve
; MOVREL-NEXT: v_mov_b32_e32 v33, s31
; MOVREL-NEXT: v_mov_b32_e32 v2, s0
; MOVREL-NEXT: s_lshl_b32 m0, s34, 1
; MOVREL-NEXT: v_mov_b32_e32 v31, s29
; MOVREL-NEXT: v_mov_b32_e32 v32, s30
; MOVREL-NEXT: v_mov_b32_e32 v31, s29
; MOVREL-NEXT: v_mov_b32_e32 v30, s28
; MOVREL-NEXT: v_mov_b32_e32 v29, s27
; MOVREL-NEXT: v_mov_b32_e32 v28, s26
Expand Down Expand Up @@ -3327,8 +3327,8 @@ define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_v_s(<16 x double> inr
; MOVREL-NEXT: v_mov_b32_e32 v33, s31
; MOVREL-NEXT: v_mov_b32_e32 v2, s0
; MOVREL-NEXT: s_lshl_b32 m0, s34, 1
; MOVREL-NEXT: v_mov_b32_e32 v31, s29
; MOVREL-NEXT: v_mov_b32_e32 v32, s30
; MOVREL-NEXT: v_mov_b32_e32 v31, s29
; MOVREL-NEXT: v_mov_b32_e32 v30, s28
; MOVREL-NEXT: v_mov_b32_e32 v29, s27
; MOVREL-NEXT: v_mov_b32_e32 v28, s26
Expand Down Expand Up @@ -3567,10 +3567,10 @@ define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_v(<7 x float> inreg %v
; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s6, s8
; MOVREL-NEXT: v_mov_b32_e32 v17, s7
; MOVREL-NEXT: v_mov_b32_e32 v13, s3
; MOVREL-NEXT: v_mov_b32_e32 v14, s4
; MOVREL-NEXT: v_mov_b32_e32 v15, s5
; MOVREL-NEXT: v_mov_b32_e32 v16, s6
; MOVREL-NEXT: v_mov_b32_e32 v15, s5
; MOVREL-NEXT: v_mov_b32_e32 v14, s4
; MOVREL-NEXT: v_mov_b32_e32 v13, s3
; MOVREL-NEXT: v_mov_b32_e32 v12, s2
; MOVREL-NEXT: v_mov_b32_e32 v11, s1
; MOVREL-NEXT: v_mov_b32_e32 v10, s0
Expand Down Expand Up @@ -3949,9 +3949,9 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; MOVREL-NEXT: s_mov_b32 s13, s15
; MOVREL-NEXT: v_mov_b32_e32 v34, s15
; MOVREL-NEXT: v_mov_b32_e32 v33, s14
; MOVREL-NEXT: v_mov_b32_e32 v30, s11
; MOVREL-NEXT: v_mov_b32_e32 v31, s12
; MOVREL-NEXT: v_mov_b32_e32 v32, s13
; MOVREL-NEXT: v_mov_b32_e32 v31, s12
; MOVREL-NEXT: v_mov_b32_e32 v30, s11
; MOVREL-NEXT: v_mov_b32_e32 v29, s10
; MOVREL-NEXT: v_mov_b32_e32 v28, s9
; MOVREL-NEXT: v_mov_b32_e32 v27, s8
Expand All @@ -3971,8 +3971,8 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v7, v23
; MOVREL-NEXT: v_mov_b32_e32 v8, v24
; MOVREL-NEXT: v_mov_b32_e32 v9, v25
Expand Down Expand Up @@ -4039,8 +4039,8 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_s(<7 x double> %vec,
;
; MOVREL-LABEL: dyn_insertelement_v7f64_v_v_s:
; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: v_mov_b32_e32 v16, v15
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, v14
; MOVREL-NEXT: v_movreld_b32_e32 v1, v16
Expand Down Expand Up @@ -4125,8 +4125,8 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_v(<7 x double> %vec,
; MOVREL-NEXT: v_mov_b32_e32 v17, v0
; MOVREL-NEXT: v_mov_b32_e32 v31, v14
; MOVREL-NEXT: v_mov_b32_e32 v30, v13
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v16
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v29, v12
; MOVREL-NEXT: v_mov_b32_e32 v28, v11
; MOVREL-NEXT: v_mov_b32_e32 v27, v10
Expand Down Expand Up @@ -4408,8 +4408,8 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
; MOVREL-NEXT: v_mov_b32_e32 v4, v20
; MOVREL-NEXT: v_mov_b32_e32 v5, v21
; MOVREL-NEXT: v_mov_b32_e32 v6, v22
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v2
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_mov_b32_e32 v7, v23
; MOVREL-NEXT: v_mov_b32_e32 v8, v24
; MOVREL-NEXT: v_mov_b32_e32 v9, v25
Expand Down Expand Up @@ -4468,8 +4468,8 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_s(<5 x double> %vec,
;
; MOVREL-LABEL: dyn_insertelement_v5f64_v_v_s:
; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: v_mov_b32_e32 v16, v11
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: ; implicit-def: $vcc_hi
; MOVREL-NEXT: v_movreld_b32_e32 v0, v10
; MOVREL-NEXT: v_movreld_b32_e32 v1, v16
Expand Down Expand Up @@ -4558,8 +4558,8 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec,
; MOVREL-NEXT: v_mov_b32_e32 v15, v2
; MOVREL-NEXT: v_mov_b32_e32 v14, v1
; MOVREL-NEXT: v_mov_b32_e32 v13, v0
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, s1, v12
; MOVREL-NEXT: s_lshl_b32 m0, s1, 1
; MOVREL-NEXT: v_movreld_b32_e32 v13, v10
; MOVREL-NEXT: v_movreld_b32_e32 v14, v11
; MOVREL-NEXT: s_and_saveexec_b32 vcc_lo, vcc_lo
Expand Down
34 changes: 17 additions & 17 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -118,8 +118,8 @@ define amdgpu_ps float @s_div_fmas_f32(float inreg %a, float inreg %b, float inr
; GFX10_W32-NEXT: s_cmp_eq_u32 s3, 0
; GFX10_W32-NEXT: v_mov_b32_e32 v0, s1
; GFX10_W32-NEXT: v_mov_b32_e32 v1, s2
; GFX10_W32-NEXT: ; implicit-def: $vcc_hi
; GFX10_W32-NEXT: s_cselect_b32 s3, 1, 0
; GFX10_W32-NEXT: ; implicit-def: $vcc_hi
; GFX10_W32-NEXT: s_and_b32 s3, 1, s3
; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; GFX10_W32-NEXT: v_div_fmas_f32 v0, s0, v0, v1
Expand All @@ -129,8 +129,8 @@ define amdgpu_ps float @s_div_fmas_f32(float inreg %a, float inreg %b, float inr
; GFX10_W64: ; %bb.0:
; GFX10_W64-NEXT: s_cmp_eq_u32 s3, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s1
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s2
; GFX10_W64-NEXT: s_cselect_b32 s3, 1, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s2
; GFX10_W64-NEXT: s_and_b32 s3, 1, s3
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3
; GFX10_W64-NEXT: v_div_fmas_f32 v0, s0, v0, v1
Expand Down Expand Up @@ -197,12 +197,12 @@ define amdgpu_ps double @s_div_fmas_f64(double inreg %a, double inreg %b, double
; GFX10_W64: ; %bb.0:
; GFX10_W64-NEXT: s_cmp_eq_u32 s6, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2
; GFX10_W64-NEXT: v_mov_b32_e32 v2, s4
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s5
; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v2, s4
; GFX10_W64-NEXT: s_and_b32 s6, 1, s6
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s5
; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], s[0:1], v[0:1], v[2:3]
; GFX10_W64-NEXT: v_readfirstlane_b32 s0, v0
; GFX10_W64-NEXT: v_readfirstlane_b32 s1, v1
Expand Down Expand Up @@ -284,8 +284,8 @@ define amdgpu_kernel void @test_div_fmas_f32(float addrspace(1)* %out, [8 x i32]
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_and_b32 s2, 1, s2
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s3
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s4
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s4
; GFX10_W64-NEXT: v_div_fmas_f32 v2, s5, v0, v1
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s0
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s1
Expand Down Expand Up @@ -593,9 +593,9 @@ define amdgpu_kernel void @test_div_fmas_f64(double addrspace(1)* %out, double %
; GFX10_W64-NEXT: s_and_b32 s8, 1, s8
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s4
; GFX10_W64-NEXT: v_mov_b32_e32 v2, s6
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s8
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s5
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s7
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s8
; GFX10_W64-NEXT: v_div_fmas_f64 v[0:1], s[2:3], v[0:1], v[2:3]
; GFX10_W64-NEXT: v_mov_b32_e32 v3, s1
; GFX10_W64-NEXT: v_mov_b32_e32 v2, s0
Expand Down Expand Up @@ -672,8 +672,8 @@ define amdgpu_kernel void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %ou
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_cmp_eq_u32 s7, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v0, s5
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s6
; GFX10_W64-NEXT: s_cselect_b32 s2, 1, 0
; GFX10_W64-NEXT: v_mov_b32_e32 v1, s6
; GFX10_W64-NEXT: s_and_b32 s2, 1, s2
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2
; GFX10_W64-NEXT: v_div_fmas_f32 v2, s4, v0, v1
Expand Down Expand Up @@ -912,11 +912,11 @@ define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace
; GFX10_W32-NEXT: v_add_co_u32_e64 v1, vcc_lo, v3, v1
; GFX10_W32-NEXT: s_cselect_b32 s2, 1, 0
; GFX10_W32-NEXT: v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
; GFX10_W32-NEXT: v_add_co_u32_e64 v3, vcc_lo, v1, 8
; GFX10_W32-NEXT: s_and_b32 s2, 1, s2
; GFX10_W32-NEXT: v_add_co_u32_e64 v3, vcc_lo, v1, 8
; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s2, 0, s2
; GFX10_W32-NEXT: v_add_co_ci_u32_e32 v4, vcc_lo, 0, v2, vcc_lo
; GFX10_W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s2, 0, s2
; GFX10_W32-NEXT: s_clause 0x2
; GFX10_W32-NEXT: global_load_dword v1, v[1:2], off
; GFX10_W32-NEXT: global_load_dword v2, v[3:4], off offset:-4
Expand Down Expand Up @@ -944,11 +944,11 @@ define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace
; GFX10_W64-NEXT: v_add_co_u32_e64 v1, vcc, v3, v1
; GFX10_W64-NEXT: s_cselect_b32 s2, 1, 0
; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v2, vcc, v4, v2, vcc
; GFX10_W64-NEXT: v_add_co_u32_e64 v3, vcc, v1, 8
; GFX10_W64-NEXT: s_and_b32 s2, 1, s2
; GFX10_W64-NEXT: v_add_co_u32_e64 v3, vcc, v1, 8
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2
; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v4, vcc, 0, v2, vcc
; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2
; GFX10_W64-NEXT: s_clause 0x2
; GFX10_W64-NEXT: global_load_dword v1, v[1:2], off
; GFX10_W64-NEXT: global_load_dword v2, v[3:4], off offset:-4
Expand Down Expand Up @@ -1093,7 +1093,7 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out
; GFX10_W64: ; %bb.0: ; %entry
; GFX10_W64-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x4c
; GFX10_W64-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX10_W64-NEXT: s_mov_b32 s4, 0
; GFX10_W64-NEXT: s_mov_b32 s6, 0
; GFX10_W64-NEXT: v_lshlrev_b64 v[1:2], 2, v[0:1]
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: v_mov_b32_e32 v4, s3
Expand All @@ -1103,19 +1103,19 @@ define amdgpu_kernel void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out
; GFX10_W64-NEXT: v_add_co_ci_u32_e32 v2, vcc, v4, v2, vcc
; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX10_W64-NEXT: global_load_dwordx3 v[1:3], v[1:2], off
; GFX10_W64-NEXT: s_and_saveexec_b64 s[6:7], vcc
; GFX10_W64-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GFX10_W64-NEXT: s_cbranch_execz BB13_2
; GFX10_W64-NEXT: ; %bb.1: ; %bb
; GFX10_W64-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0
; GFX10_W64-NEXT: s_cselect_b32 s4, 1, 0
; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0
; GFX10_W64-NEXT: BB13_2: ; %exit
; GFX10_W64-NEXT: v_nop
; GFX10_W64-NEXT: s_or_b64 exec, exec, s[6:7]
; GFX10_W64-NEXT: s_and_b32 s0, 1, s4
; GFX10_W64-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX10_W64-NEXT: s_and_b32 s0, 1, s6
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_add_u32 s0, s2, 8
Expand Down
80 changes: 40 additions & 40 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -482,11 +482,11 @@ define amdgpu_ps float @atomic_add_i32_2d(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -519,19 +519,19 @@ define amdgpu_ps float @atomic_add_i32_3d(<8 x i32> inreg %rsrc, i32 %data, i16
;
; GFX10-LABEL: atomic_add_i32_3d:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -564,19 +564,19 @@ define amdgpu_ps float @atomic_add_i32_cube(<8 x i32> inreg %rsrc, i32 %data, i1
;
; GFX10-LABEL: atomic_add_i32_cube:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -612,11 +612,11 @@ define amdgpu_ps float @atomic_add_i32_1darray(<8 x i32> inreg %rsrc, i32 %data,
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -649,19 +649,19 @@ define amdgpu_ps float @atomic_add_i32_2darray(<8 x i32> inreg %rsrc, i32 %data,
;
; GFX10-LABEL: atomic_add_i32_2darray:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -694,19 +694,19 @@ define amdgpu_ps float @atomic_add_i32_2dmsaa(<8 x i32> inreg %rsrc, i32 %data,
;
; GFX10-LABEL: atomic_add_i32_2dmsaa:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v3, v4, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -745,13 +745,13 @@ define amdgpu_ps float @atomic_add_i32_2darraymsaa(<8 x i32> inreg %rsrc, i32 %d
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: v_and_or_b32 v1, v1, v5, v2
; GFX10-NEXT: v_and_or_b32 v2, v3, v5, v4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v1, v1, v5, v2
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v3, v5, v4
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -1277,11 +1277,11 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2d(<8 x i32> inreg %rsrc, i64 %data
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -1314,19 +1314,19 @@ define amdgpu_ps <2 x float> @atomic_add_i64_3d(<8 x i32> inreg %rsrc, i64 %data
;
; GFX10-LABEL: atomic_add_i64_3d:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -1359,19 +1359,19 @@ define amdgpu_ps <2 x float> @atomic_add_i64_cube(<8 x i32> inreg %rsrc, i64 %da
;
; GFX10-LABEL: atomic_add_i64_cube:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -1407,11 +1407,11 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1darray(<8 x i32> inreg %rsrc, i64
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -1444,19 +1444,19 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darray(<8 x i32> inreg %rsrc, i64
;
; GFX10-LABEL: atomic_add_i64_2darray:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -1489,19 +1489,19 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2dmsaa(<8 x i32> inreg %rsrc, i64 %
;
; GFX10-LABEL: atomic_add_i64_2dmsaa:
; GFX10: ; %bb.0: ; %main_body
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v5, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v2, v2, v5, v3
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v3, v4, v5, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -1540,13 +1540,13 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darraymsaa(<8 x i32> inreg %rsrc,
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: v_and_or_b32 v2, v2, v6, v3
; GFX10-NEXT: v_and_or_b32 v3, v4, v6, v5
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v2, v2, v6, v3
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v3, v4, v6, v5
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -588,23 +588,23 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
;
; GFX10NSA-LABEL: gather4_l_2d:
; GFX10NSA: ; %bb.0: ; %main_body
; GFX10NSA-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10NSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10NSA-NEXT: s_mov_b32 s0, s2
; GFX10NSA-NEXT: s_mov_b32 s2, s4
; GFX10NSA-NEXT: s_mov_b32 s4, s6
; GFX10NSA-NEXT: s_mov_b32 s6, s8
; GFX10NSA-NEXT: s_mov_b32 s8, s10
; GFX10NSA-NEXT: s_mov_b32 s10, s12
; GFX10NSA-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10NSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10NSA-NEXT: s_lshl_b32 s12, s0, 16
; GFX10NSA-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10NSA-NEXT: v_and_or_b32 v1, v2, v3, s12
; GFX10NSA-NEXT: s_mov_b32 s1, s3
; GFX10NSA-NEXT: s_mov_b32 s3, s5
; GFX10NSA-NEXT: s_mov_b32 s5, s7
; GFX10NSA-NEXT: s_mov_b32 s7, s9
; GFX10NSA-NEXT: s_mov_b32 s9, s11
; GFX10NSA-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10NSA-NEXT: s_mov_b32 s11, s13
; GFX10NSA-NEXT: v_and_or_b32 v1, v2, v3, s12
; GFX10NSA-NEXT: ; implicit-def: $vcc_hi
; GFX10NSA-NEXT: image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -640,23 +640,23 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in
;
; GFX10NSA-LABEL: gather4_c_l_2d:
; GFX10NSA: ; %bb.0: ; %main_body
; GFX10NSA-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10NSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10NSA-NEXT: s_mov_b32 s0, s2
; GFX10NSA-NEXT: s_mov_b32 s2, s4
; GFX10NSA-NEXT: s_mov_b32 s4, s6
; GFX10NSA-NEXT: s_mov_b32 s6, s8
; GFX10NSA-NEXT: s_mov_b32 s8, s10
; GFX10NSA-NEXT: s_mov_b32 s10, s12
; GFX10NSA-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX10NSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX10NSA-NEXT: s_lshl_b32 s12, s0, 16
; GFX10NSA-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10NSA-NEXT: v_and_or_b32 v2, v3, v4, s12
; GFX10NSA-NEXT: s_mov_b32 s1, s3
; GFX10NSA-NEXT: s_mov_b32 s3, s5
; GFX10NSA-NEXT: s_mov_b32 s5, s7
; GFX10NSA-NEXT: s_mov_b32 s7, s9
; GFX10NSA-NEXT: s_mov_b32 s9, s11
; GFX10NSA-NEXT: v_and_or_b32 v1, v1, v4, v2
; GFX10NSA-NEXT: s_mov_b32 s11, s13
; GFX10NSA-NEXT: v_and_or_b32 v2, v3, v4, s12
; GFX10NSA-NEXT: ; implicit-def: $vcc_hi
; GFX10NSA-NEXT: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -695,6 +695,7 @@ define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10NSA-NEXT: s_mov_b32 s1, s3
; GFX10NSA-NEXT: s_mov_b32 s2, s4
; GFX10NSA-NEXT: s_mov_b32 s3, s5
; GFX10NSA-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10NSA-NEXT: s_mov_b32 s4, s6
; GFX10NSA-NEXT: s_mov_b32 s5, s7
; GFX10NSA-NEXT: s_mov_b32 s6, s8
Expand All @@ -703,7 +704,6 @@ define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10NSA-NEXT: s_mov_b32 s9, s11
; GFX10NSA-NEXT: s_mov_b32 s10, s12
; GFX10NSA-NEXT: s_mov_b32 s11, s13
; GFX10NSA-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10NSA-NEXT: ; implicit-def: $vcc_hi
; GFX10NSA-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -742,6 +742,7 @@ define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10NSA-NEXT: s_mov_b32 s1, s3
; GFX10NSA-NEXT: s_mov_b32 s2, s4
; GFX10NSA-NEXT: s_mov_b32 s3, s5
; GFX10NSA-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10NSA-NEXT: s_mov_b32 s4, s6
; GFX10NSA-NEXT: s_mov_b32 s5, s7
; GFX10NSA-NEXT: s_mov_b32 s6, s8
Expand All @@ -750,7 +751,6 @@ define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10NSA-NEXT: s_mov_b32 s9, s11
; GFX10NSA-NEXT: s_mov_b32 s10, s12
; GFX10NSA-NEXT: s_mov_b32 s11, s13
; GFX10NSA-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10NSA-NEXT: ; implicit-def: $vcc_hi
; GFX10NSA-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16
; GFX10NSA-NEXT: s_waitcnt vmcnt(0)
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,9 @@ define amdgpu_ps <4 x float> @load_2d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, i32
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
Expand Down Expand Up @@ -113,9 +113,9 @@ define amdgpu_ps <4 x float> @load_2d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc,
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe lwe
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe lwe
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,13 +30,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw(<8 x i32> inreg %rsrc,
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -77,17 +77,17 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
Expand Down Expand Up @@ -131,17 +131,17 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v4, v1
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v4, v3
; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,9 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
Expand Down Expand Up @@ -113,9 +113,9 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe lwe
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe lwe
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,19 +24,19 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw(<8 x i32> inreg %rsrc, i16 %s,
;
; GFX10-LABEL: load_3d_v4f32_xyzw:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -71,23 +71,23 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, i32
;
; GFX10-LABEL: load_3d_v4f32_xyzw_tfe:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
Expand Down Expand Up @@ -125,23 +125,23 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc,
;
; GFX10-LABEL: load_3d_v4f32_xyzw_tfe_lwe:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_mov_b32 s0, s2
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: v_mov_b32_e32 v3, 0xffff
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: s_lshl_b32 s8, s0, 16
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: v_and_or_b32 v0, v0, v3, v1
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_and_or_b32 v1, v2, v3, s8
; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,9 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, i32
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
Expand Down Expand Up @@ -113,9 +113,9 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc,
; GFX10-NEXT: s_mov_b32 s6, s8
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: v_mov_b32_e32 v5, s10
; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe lwe
; GFX10-NEXT: v_mov_b32_e32 v6, s11
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[0:4], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe lwe
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[5:6], v4, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.a16.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,7 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
Expand All @@ -81,7 +82,6 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -123,12 +123,12 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_lshl_b32 s12, s0, 16
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -167,6 +167,7 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
Expand All @@ -175,7 +176,6 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -217,12 +217,12 @@ define amdgpu_ps <4 x float> @sample_l_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_lshl_b32 s12, s0, 16
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, s12
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -261,6 +261,7 @@ define amdgpu_ps <4 x float> @sample_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
Expand All @@ -269,7 +270,6 @@ define amdgpu_ps <4 x float> @sample_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -311,12 +311,12 @@ define amdgpu_ps <4 x float> @sample_c_l_o_1d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_lshl_b32 s12, s0, 16
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, s12
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s7, s9
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, s12
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -355,6 +355,7 @@ define amdgpu_ps <4 x float> @sample_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
Expand All @@ -363,7 +364,6 @@ define amdgpu_ps <4 x float> @sample_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> i
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -402,6 +402,7 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
Expand All @@ -410,7 +411,6 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v0, v0, 0xffff, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -449,6 +449,7 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
Expand All @@ -457,7 +458,6 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -496,6 +496,7 @@ define amdgpu_ps <4 x float> @gather4_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
Expand All @@ -504,7 +505,6 @@ define amdgpu_ps <4 x float> @gather4_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> in
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v1, v1, 0xffff, v2
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_gather4_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down Expand Up @@ -543,6 +543,7 @@ define amdgpu_ps <4 x float> @gather4_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_mov_b32 s2, s4
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: s_mov_b32 s4, s6
; GFX10-NEXT: s_mov_b32 s5, s7
; GFX10-NEXT: s_mov_b32 s6, s8
Expand All @@ -551,7 +552,6 @@ define amdgpu_ps <4 x float> @gather4_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32>
; GFX10-NEXT: s_mov_b32 s9, s11
; GFX10-NEXT: s_mov_b32 s10, s12
; GFX10-NEXT: s_mov_b32 s11, s13
; GFX10-NEXT: v_and_or_b32 v2, v2, 0xffff, v3
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_gather4_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
; GFX10-NEXT: s_waitcnt vmcnt(0)
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -593,9 +593,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_0()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 0)
call void asm sideeffect "", ""()
Expand All @@ -614,9 +614,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_1()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 1)
call void asm sideeffect "", ""()
Expand All @@ -635,9 +635,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_2()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x2
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 2)
call void asm sideeffect "", ""()
Expand All @@ -656,9 +656,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_4()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x4
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 4)
call void asm sideeffect "", ""()
Expand All @@ -677,9 +677,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_8()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 8)
call void asm sideeffect "", ""()
Expand All @@ -698,9 +698,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_16()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 1
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 1
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 16)
call void asm sideeffect "", ""()
Expand All @@ -719,9 +719,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_32()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 2
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 2
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 32)
call void asm sideeffect "", ""()
Expand All @@ -740,9 +740,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_64()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 4
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 4
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 64)
call void asm sideeffect "", ""()
Expand All @@ -761,9 +761,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_128(
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 8
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 8
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 128)
call void asm sideeffect "", ""()
Expand All @@ -782,9 +782,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_15()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0xf
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 15)
call void asm sideeffect "", ""()
Expand All @@ -803,9 +803,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_255(
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0xf
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 15
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 15
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 255)
call void asm sideeffect "", ""()
Expand All @@ -825,9 +825,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_597(
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x5
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 5
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 5
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 597)
call void asm sideeffect "", ""()
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,8 +69,8 @@ define i32 @v_sdot4_cast_v4i8(<4 x i8> %a, <4 x i8> %b, i32 %c) {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: s_movk_i32 s5, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v1
; GFX10-NEXT: v_and_b32_e32 v1, s5, v2
; GFX10-NEXT: v_and_b32_e32 v2, s5, v3
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,8 +69,8 @@ define i32 @v_udot4_cast_v4i8(<4 x i8> %a, <4 x i8> %b, i32 %c) {
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8
; GFX10-NEXT: s_movk_i32 s5, 0xff
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_and_or_b32 v0, v0, s5, v1
; GFX10-NEXT: v_and_b32_e32 v1, s5, v2
; GFX10-NEXT: v_and_b32_e32 v2, s5, v3
Expand Down
152 changes: 76 additions & 76 deletions llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
View file

Large diffs are not rendered by default.

10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AMDGPU/cc-update.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,9 +47,9 @@ define amdgpu_kernel void @test_kern_stack() local_unnamed_addr #0 {
; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: ; implicit-def: $vcc_hi
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX1010-NEXT: s_endpgm
Expand Down Expand Up @@ -146,9 +146,9 @@ define amdgpu_kernel void @test_kern_stack_and_call() local_unnamed_addr #0 {
; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_getpc_b64 s[4:5]
; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+4
Expand Down Expand Up @@ -213,9 +213,9 @@ define amdgpu_kernel void @test_force_fp_kern_stack() local_unnamed_addr #2 {
; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: ; implicit-def: $vcc_hi
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX1010-NEXT: s_endpgm
Expand Down Expand Up @@ -318,9 +318,9 @@ define amdgpu_kernel void @test_force_fp_kern_stack_and_call() local_unnamed_add
; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_getpc_b64 s[4:5]
; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+4
Expand Down Expand Up @@ -382,8 +382,8 @@ define amdgpu_kernel void @test_sgpr_offset_kernel() #1 {
; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: s_mov_b32 s6, 0x20000
; GFX1010-NEXT: ; implicit-def: $vcc_hi
; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8
; GFX1010-NEXT: ; implicit-def: $vcc_hi
; GFX1010-NEXT: s_waitcnt vmcnt(0)
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX1010-NEXT: v_nop
Expand Down
332 changes: 166 additions & 166 deletions llvm/test/CodeGen/AMDGPU/idot2.ll
View file

Large diffs are not rendered by default.

74 changes: 37 additions & 37 deletions llvm/test/CodeGen/AMDGPU/idot4s.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -643,30 +643,30 @@ define amdgpu_kernel void @idot4_multiuse_mul1(<4 x i8> addrspace(1)* %src1,
; GFX10-DL-LABEL: idot4_multiuse_mul1:
; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_sext_i32_i8 s5, s2
; GFX10-DL-NEXT: s_sext_i32_i8 s6, s3
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_sext_i32_i8 s2, s0
; GFX10-DL-NEXT: s_sext_i32_i8 s3, s1
; GFX10-DL-NEXT: s_bfe_i32 s6, s0, 0x80008
; GFX10-DL-NEXT: s_bfe_i32 s7, s1, 0x80008
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s6, s7, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x80010
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x80010
; GFX10-DL-NEXT: s_ashr_i32 s0, s0, 24
; GFX10-DL-NEXT: s_ashr_i32 s1, s1, 24
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s2, s3, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s0, s1, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x80008
; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x80008
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s5, s6, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s4, s7, v0
; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x80010
; GFX10-DL-NEXT: s_bfe_i32 s7, s3, 0x80010
; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 24
; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 24
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s5, s6, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s4, s7, v0
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm
<4 x i8> addrspace(1)* %src2,
Expand Down Expand Up @@ -853,14 +853,14 @@ define amdgpu_kernel void @idot4_acc32_vecMul(<4 x i8> addrspace(1)* %src1,
; GFX10-DL-NEXT: v_lshrrev_b16_e64 v0, 8, s2
; GFX10-DL-NEXT: v_lshrrev_b16_e64 v1, 8, s3
; GFX10-DL-NEXT: v_mov_b32_e32 v2, s4
; GFX10-DL-NEXT: s_sext_i32_i8 s5, s2
; GFX10-DL-NEXT: s_sext_i32_i8 s6, s3
; GFX10-DL-NEXT: s_sext_i32_i8 s4, s2
; GFX10-DL-NEXT: s_sext_i32_i8 s5, s3
; GFX10-DL-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-DL-NEXT: v_bfe_i32 v1, v1, 0, 8
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2
; GFX10-DL-NEXT: s_bfe_i32 s4, s2, 0x80010
; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 24
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s5, s6, v2
; GFX10-DL-NEXT: s_bfe_i32 s5, s3, 0x80010
; GFX10-DL-NEXT: s_ashr_i32 s2, s2, 24
; GFX10-DL-NEXT: s_ashr_i32 s3, s3, 24
; GFX10-DL-NEXT: v_mad_i32_i24 v0, v0, v1, v2
; GFX10-DL-NEXT: v_mad_i32_i24 v0, s4, s5, v0
Expand Down Expand Up @@ -1052,25 +1052,25 @@ define amdgpu_kernel void @idot4_acc16_vecMul(<4 x i8> addrspace(1)* %src1,
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_bfe_i32 s4, s0, 0x80000
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x80000
; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v4, 8, s0
; GFX10-DL-NEXT: s_lshr_b32 s5, s1, 16
; GFX10-DL-NEXT: s_bfe_i32 s0, s0, 0x80000
; GFX10-DL-NEXT: s_bfe_i32 s3, s1, 0x80000
; GFX10-DL-NEXT: v_and_b32_e32 v7, s0, v3
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v5, 8, s1
; GFX10-DL-NEXT: v_and_b32_e32 v6, s3, v3
; GFX10-DL-NEXT: v_and_b32_e32 v7, s4, v3
; GFX10-DL-NEXT: s_bfe_i32 s0, s2, 0x80000
; GFX10-DL-NEXT: s_bfe_i32 s1, s5, 0x80000
; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6
; GFX10-DL-NEXT: s_lshr_b32 s0, s1, 16
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v8, 8, s2
; GFX10-DL-NEXT: v_lshl_or_b32 v4, v4, 16, v7
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v6, 8, s2
; GFX10-DL-NEXT: v_and_b32_e32 v8, s1, v3
; GFX10-DL-NEXT: v_and_b32_e32 v3, s0, v3
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v7, 8, s5
; GFX10-DL-NEXT: s_bfe_i32 s1, s2, 0x80000
; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6
; GFX10-DL-NEXT: s_bfe_i32 s2, s0, 0x80000
; GFX10-DL-NEXT: v_ashrrev_i16_e64 v6, 8, s0
; GFX10-DL-NEXT: v_and_b32_e32 v7, s2, v3
; GFX10-DL-NEXT: v_and_b32_e32 v3, s1, v3
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5
; GFX10-DL-NEXT: v_lshl_or_b32 v3, v6, 16, v3
; GFX10-DL-NEXT: v_lshl_or_b32 v5, v7, 16, v8
; GFX10-DL-NEXT: v_lshl_or_b32 v5, v6, 16, v7
; GFX10-DL-NEXT: v_lshl_or_b32 v3, v8, 16, v3
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v3, v3, v5
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v4, v2
Expand Down
150 changes: 75 additions & 75 deletions llvm/test/CodeGen/AMDGPU/idot4u.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -623,11 +623,11 @@ define amdgpu_kernel void @udot2_8(<4 x i8> addrspace(1)* %src1,
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s3, s2, s1
; GFX10-DL-NEXT: s_and_b32 s1, s0, s1
; GFX10-DL-NEXT: s_bfe_u32 s2, s2, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s0, s0, 0x80008
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s2, v2
; GFX10-DL-NEXT: s_bfe_u32 s1, s2, 0x80008
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2
; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm
<4 x i8> addrspace(1)* %src2,
Expand Down Expand Up @@ -946,6 +946,7 @@ define amdgpu_kernel void @udot4_CommutationAccrossMADs(<4 x i8> addrspace(1)* %
; GFX10-DL-LABEL: udot4_CommutationAccrossMADs:
; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-DL-NEXT: s_movk_i32 s4, 0xff
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2
Expand All @@ -955,20 +956,19 @@ define amdgpu_kernel void @udot4_CommutationAccrossMADs(<4 x i8> addrspace(1)* %
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_movk_i32 s2, 0xff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x80008
; GFX10-DL-NEXT: s_and_b32 s5, s0, s2
; GFX10-DL-NEXT: s_and_b32 s2, s1, s2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80008
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s3, s0, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s4, s1, 0x80010
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v2
; GFX10-DL-NEXT: s_and_b32 s2, s0, s4
; GFX10-DL-NEXT: s_and_b32 s3, s1, s4
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s5, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s3, s2, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s1, s0, v2
; GFX10-DL-NEXT: global_store_byte v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm
Expand Down Expand Up @@ -1140,31 +1140,31 @@ define amdgpu_kernel void @udot4_multiuse_mul1(<4 x i8> addrspace(1)* %src1,
; GFX10-DL-LABEL: udot4_multiuse_mul1:
; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX10-DL-NEXT: s_movk_i32 s5, 0xff
; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_movk_i32 s2, 0xff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_and_b32 s6, s2, s5
; GFX10-DL-NEXT: s_and_b32 s5, s3, s5
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_and_b32 s3, s0, s2
; GFX10-DL-NEXT: s_and_b32 s2, s1, s2
; GFX10-DL-NEXT: s_bfe_u32 s6, s0, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s7, s1, 0x80008
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s7, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s3, s2, v0
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80008
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s4, s7, v0
; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24
; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s5, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s4, s7, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm
<4 x i8> addrspace(1)* %src2,
Expand Down Expand Up @@ -1348,32 +1348,32 @@ define amdgpu_kernel void @udot4_multiuse_add1(<4 x i8> addrspace(1)* %src1,
; GFX10-DL-LABEL: udot4_multiuse_add1:
; GFX10-DL: ; %bb.0: ; %entry
; GFX10-DL-NEXT: s_clause 0x1
; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34
; GFX10-DL-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-DL-NEXT: s_movk_i32 s7, 0xff
; GFX10-DL-NEXT: ; implicit-def: $vcc_hi
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX10-DL-NEXT: s_movk_i32 s5, 0xff
; GFX10-DL-NEXT: s_load_dword s6, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-DL-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_bfe_u32 s6, s2, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80008
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: s_and_b32 s8, s2, s5
; GFX10-DL-NEXT: s_and_b32 s5, s3, s5
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s6, s7, v0
; GFX10-DL-NEXT: s_bfe_u32 s6, s2, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s7, s3, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24
; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s8, s5, v0
; GFX10-DL-NEXT: v_add_nc_u32_e32 v0, s4, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s6, s7, v1
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s6
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80008
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s2, s3, v0
; GFX10-DL-NEXT: s_and_b32 s2, s0, s7
; GFX10-DL-NEXT: s_and_b32 s3, s1, s7
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s2, s3, v0
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s2, s3, v1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v0, s6, v0
; GFX10-DL-NEXT: v_mad_u32_u24 v1, s0, s1, v1
; GFX10-DL-NEXT: v_add_nc_u32_e32 v2, v1, v0
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s4
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s5
; GFX10-DL-NEXT: global_store_dword v[0:1], v2, off
; GFX10-DL-NEXT: s_endpgm
<4 x i8> addrspace(1)* %src2,
Expand Down Expand Up @@ -1560,15 +1560,15 @@ define amdgpu_kernel void @notdot4_mixedtypes(<4 x i8> addrspace(1)* %src1,
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80008
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80008
; GFX10-DL-NEXT: s_sext_i32_i8 s4, s0
; GFX10-DL-NEXT: s_sext_i32_i8 s5, s1
; GFX10-DL-NEXT: s_waitcnt vmcnt(0)
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_sext_i32_i8 s2, s0
; GFX10-DL-NEXT: s_sext_i32_i8 s3, s1
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s2, s3, v2
; GFX10-DL-NEXT: s_bfe_u32 s2, s0, 0x80010
; GFX10-DL-NEXT: s_bfe_u32 s3, s1, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX10-DL-NEXT: v_mad_i32_i24 v2, s4, s5, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s2, s3, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s0, s1, v2
; GFX10-DL-NEXT: global_store_short v[0:1], v2, off
Expand Down Expand Up @@ -1754,20 +1754,20 @@ define amdgpu_kernel void @udot4_acc32_vecMul(<4 x i8> addrspace(1)* %src1,
; GFX10-DL-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-DL-NEXT: s_load_dword s3, s[6:7], 0x0
; GFX10-DL-NEXT: s_load_dword s4, s[0:1], 0x0
; GFX10-DL-NEXT: s_movk_i32 s5, 0xff
; GFX10-DL-NEXT: s_mov_b32 s6, 0xffff
; GFX10-DL-NEXT: s_movk_i32 s6, 0xff
; GFX10-DL-NEXT: s_mov_b32 s5, 0xffff
; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-DL-NEXT: v_mov_b32_e32 v0, s2
; GFX10-DL-NEXT: v_mov_b32_e32 v1, s3
; GFX10-DL-NEXT: s_and_b32 s7, s2, s5
; GFX10-DL-NEXT: v_mov_b32_e32 v2, s4
; GFX10-DL-NEXT: s_and_b32 s5, s3, s5
; GFX10-DL-NEXT: v_and_b32_sdwa v0, s6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-DL-NEXT: v_and_b32_sdwa v1, s6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-DL-NEXT: s_and_b32 s4, s2, s6
; GFX10-DL-NEXT: s_and_b32 s6, s3, s6
; GFX10-DL-NEXT: v_and_b32_sdwa v0, s5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-DL-NEXT: v_and_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s4, s6, v2
; GFX10-DL-NEXT: s_bfe_u32 s4, s2, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v2, s7, s5, v2
; GFX10-DL-NEXT: s_bfe_u32 s5, s3, 0x80010
; GFX10-DL-NEXT: s_lshr_b32 s2, s2, 24
; GFX10-DL-NEXT: s_lshr_b32 s3, s3, 24
; GFX10-DL-NEXT: v_mad_u32_u24 v0, v0, v1, v2
; GFX10-DL-NEXT: v_mad_u32_u24 v0, s4, s5, v0
Expand Down Expand Up @@ -1956,14 +1956,14 @@ define amdgpu_kernel void @udot4_acc16_vecMul(<4 x i8> addrspace(1)* %src1,
; GFX10-DL-NEXT: v_and_b32_sdwa v7, v3, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-DL-NEXT: v_lshrrev_b16_e64 v5, 8, s1
; GFX10-DL-NEXT: v_and_b32_sdwa v6, v3, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 16
; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 16
; GFX10-DL-NEXT: s_lshr_b32 s2, s1, 16
; GFX10-DL-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-DL-NEXT: v_lshl_or_b32 v4, v4, 16, v7
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 24
; GFX10-DL-NEXT: v_and_b32_sdwa v6, v3, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-DL-NEXT: v_and_b32_sdwa v3, v3, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-DL-NEXT: v_lshl_or_b32 v5, v5, 16, v6
; GFX10-DL-NEXT: v_and_b32_sdwa v6, v3, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-DL-NEXT: v_and_b32_sdwa v3, v3, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 24
; GFX10-DL-NEXT: v_pk_mul_lo_u16 v4, v4, v5
; GFX10-DL-NEXT: v_lshl_or_b32 v5, s1, 16, v6
; GFX10-DL-NEXT: v_lshl_or_b32 v3, s0, 16, v3
Expand Down Expand Up @@ -2176,15 +2176,15 @@ define amdgpu_kernel void @udot4_acc8_vecMul(<4 x i8> addrspace(1)* %src1,
; GFX10-DL-NEXT: v_lshrrev_b16_e64 v4, 8, s1
; GFX10-DL-NEXT: s_lshr_b32 s2, s0, 24
; GFX10-DL-NEXT: s_lshr_b32 s3, s1, 24
; GFX10-DL-NEXT: s_lshr_b32 s4, s0, 16
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s2, s3
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v3, v3, v4
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v4, s0, s1
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s2, s3
; GFX10-DL-NEXT: s_lshr_b32 s0, s1, 16
; GFX10-DL-NEXT: s_lshr_b32 s0, s0, 16
; GFX10-DL-NEXT: s_lshr_b32 s1, s1, 16
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v3, 8, v3
; GFX10-DL-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_lshlrev_b16_e64 v4, 8, v5
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s4, s0
; GFX10-DL-NEXT: v_mul_lo_u16_e64 v5, s0, s1
; GFX10-DL-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX10-DL-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX10-DL-NEXT: v_or_b32_e32 v4, v3, v4
Expand Down
190 changes: 95 additions & 95 deletions llvm/test/CodeGen/AMDGPU/idot8s.ll
View file

Large diffs are not rendered by default.

270 changes: 135 additions & 135 deletions llvm/test/CodeGen/AMDGPU/idot8u.ll
View file

Large diffs are not rendered by default.

12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,8 +34,8 @@ define amdgpu_ps void @load_1d_f16_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_short v[0:1], v1, off
; GFX10-NEXT: global_store_dword v[0:1], v2, off
Expand Down Expand Up @@ -97,8 +97,8 @@ define amdgpu_ps void @load_1d_f16_tfe_dmask1(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_short v[0:1], v1, off
; GFX10-NEXT: global_store_dword v[0:1], v2, off
Expand Down Expand Up @@ -160,8 +160,8 @@ define amdgpu_ps void @load_1d_v2f16_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: global_store_dword v[0:1], v2, off
Expand Down Expand Up @@ -223,8 +223,8 @@ define amdgpu_ps void @load_1d_v2f16_tfe_dmask1(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: global_store_dword v[0:1], v2, off
Expand Down Expand Up @@ -286,8 +286,8 @@ define amdgpu_ps void @load_1d_v2f16_tfe_dmask3(<8 x i32> inreg %rsrc, i32 %s) {
; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: global_store_dword v[0:1], v2, off
Expand Down Expand Up @@ -363,8 +363,8 @@ define amdgpu_ps void @load_1d_v4f16_tfe_dmask15(<8 x i32> inreg %rsrc, i32 %s)
; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[1:2], off
; GFX10-NEXT: global_store_dword v[0:1], v3, off
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -593,9 +593,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_0()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 0)
call void asm sideeffect "", ""()
Expand All @@ -614,9 +614,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_1()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x1
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 1)
call void asm sideeffect "", ""()
Expand All @@ -635,9 +635,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_2()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x2
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 2)
call void asm sideeffect "", ""()
Expand All @@ -656,9 +656,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_4()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x4
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 4)
call void asm sideeffect "", ""()
Expand All @@ -677,9 +677,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_8()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x8
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 8)
call void asm sideeffect "", ""()
Expand All @@ -698,9 +698,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_16()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 1
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 1
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 16)
call void asm sideeffect "", ""()
Expand All @@ -719,9 +719,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_32()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 2
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 2
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 32)
call void asm sideeffect "", ""()
Expand All @@ -740,9 +740,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_64()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 4
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 4
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 64)
call void asm sideeffect "", ""()
Expand All @@ -761,9 +761,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_128(
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x0
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 8
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 8
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 128)
call void asm sideeffect "", ""()
Expand All @@ -782,9 +782,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_15()
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0xf
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 0
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 15)
call void asm sideeffect "", ""()
Expand All @@ -803,9 +803,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_255(
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0xf
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 15
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 15
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 255)
call void asm sideeffect "", ""()
Expand All @@ -825,9 +825,9 @@ define amdgpu_kernel void @test_setreg_full_both_round_mode_and_denorm_mode_597(
; GFX10: ; %bb.0:
; GFX10-NEXT: s_round_mode 0x5
; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: s_denorm_mode 5
; GFX10-NEXT: ;;#ASMSTART
; GFX10-NEXT: ;;#ASMEND
; GFX10-NEXT: s_denorm_mode 5
; GFX10-NEXT: s_endpgm
call void @llvm.amdgcn.s.setreg(i32 14337, i32 597)
call void asm sideeffect "", ""()
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -101,8 +101,8 @@ define hidden amdgpu_kernel void @clmem_read(i8 addrspace(1)* %buffer) {
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
; GFX10: global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,8 +25,8 @@ body: |
; GCN: $vcc_hi = IMPLICIT_DEF
; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store 4, addrspace 3)
; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
; GCN: $m0 = S_MOV_B32 0
; GCN: $vgpr0 = COPY [[S_LOAD_DWORD_IMM]]
; GCN: $m0 = S_MOV_B32 0
; GCN: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
; GCN: DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
; GCN: S_WAITCNT 0
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@
define amdgpu_kernel void @kernel_background_evaluate(float addrspace(5)* %kg, <4 x i32> addrspace(1)* %input, <4 x float> addrspace(1)* %output, i32 %i) {
; GCN-LABEL: kernel_background_evaluate:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dword s6, s[0:1], 0x24
; GCN-NEXT: s_load_dword s0, s[0:1], 0x24
; GCN-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
; GCN-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
; GCN-NEXT: s_mov_b32 s38, -1
Expand All @@ -26,16 +26,16 @@ define amdgpu_kernel void @kernel_background_evaluate(float addrspace(5)* %kg, <
; GCN-NEXT: v_mov_b32_e32 v2, 0x4000
; GCN-NEXT: v_mov_b32_e32 v3, 0
; GCN-NEXT: v_mov_b32_e32 v4, 0x400000
; GCN-NEXT: s_mov_b64 s[0:1], s[36:37]
; GCN-NEXT: s_mov_b64 s[2:3], s[38:39]
; GCN-NEXT: s_mov_b32 s32, 0xc0000
; GCN-NEXT: v_add_nc_u32_e64 v40, 4, 0x4000
; GCN-NEXT: ; implicit-def: $vcc_hi
; GCN-NEXT: s_getpc_b64 s[4:5]
; GCN-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4
; GCN-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+4
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, s6
; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: s_mov_b64 s[0:1], s[36:37]
; GCN-NEXT: s_mov_b64 s[2:3], s[38:39]
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -136,10 +136,10 @@ define <4 x float> @call_preserved_vgpr_tuple8(<8 x i32> %rsrc, <4 x i32> %samp,
; GFX10-NEXT: s_add_u32 s4, s4, extern_func@gotpcrel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, extern_func@gotpcrel32@hi+4
; GFX10-NEXT: v_mov_b32_e32 v40, v16
; GFX10-NEXT: v_mov_b32_e32 v41, v15
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-NEXT: image_gather4_c_b_cl v[0:3], v[12:19], s[36:43], s[44:47] dmask:0x1
; GFX10-NEXT: v_mov_b32_e32 v41, v15
; GFX10-NEXT: v_mov_b32_e32 v42, v14
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-NEXT: v_mov_b32_e32 v43, v13
; GFX10-NEXT: v_mov_b32_e32 v44, v12
; GFX10-NEXT: ; implicit-def: $vcc_hi
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/wave32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -235,9 +235,9 @@ bb13:
; GFX1064: s_or_b64 [[MASK0:s\[[0-9:]+\]]], [[MASK0]], vcc
; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo
; GFX1064: s_andn2_b64 [[MASK1:s\[[0-9:]+\]]], [[MASK1]], exec
; GCN: global_store_dword
; GFX1032: s_and_b32 [[MASK0]], [[MASK0]], exec_lo
; GFX1064: s_and_b64 [[MASK0]], [[MASK0]], exec
; GCN: global_store_dword
; GFX1032: s_or_b32 [[MASK1]], [[MASK1]], [[MASK0]]
; GFX1064: s_or_b64 [[MASK1]], [[MASK1]], [[MASK0]]
; GCN: BB{{.*}}: ; %Flow
Expand Down