286 changes: 26 additions & 260 deletions llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,22 +17,9 @@ define <vscale x 1 x i8> @vsrl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv1i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%vc = lshr <vscale x 1 x i8> %va, %splat
ret <vscale x 1 x i8> %vc
}

define <vscale x 1 x i8> @vsrl_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv1i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
%head = insertelement <vscale x 1 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
%vc = lshr <vscale x 1 x i8> %va, %splat
ret <vscale x 1 x i8> %vc
Expand All @@ -54,22 +41,9 @@ define <vscale x 2 x i8> @vsrl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv2i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%vc = lshr <vscale x 2 x i8> %va, %splat
ret <vscale x 2 x i8> %vc
}

define <vscale x 2 x i8> @vsrl_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv2i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
%head = insertelement <vscale x 2 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
%vc = lshr <vscale x 2 x i8> %va, %splat
ret <vscale x 2 x i8> %vc
Expand All @@ -91,22 +65,9 @@ define <vscale x 4 x i8> @vsrl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv4i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%vc = lshr <vscale x 4 x i8> %va, %splat
ret <vscale x 4 x i8> %vc
}

define <vscale x 4 x i8> @vsrl_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv4i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
%head = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%vc = lshr <vscale x 4 x i8> %va, %splat
ret <vscale x 4 x i8> %vc
Expand All @@ -128,22 +89,9 @@ define <vscale x 8 x i8> @vsrl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv8i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i8> %vc
}

define <vscale x 8 x i8> @vsrl_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv8i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
%head = insertelement <vscale x 8 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i8> %vc
Expand All @@ -165,22 +113,9 @@ define <vscale x 16 x i8> @vsrl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv16i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%vc = lshr <vscale x 16 x i8> %va, %splat
ret <vscale x 16 x i8> %vc
}

define <vscale x 16 x i8> @vsrl_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv16i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
%head = insertelement <vscale x 16 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
%vc = lshr <vscale x 16 x i8> %va, %splat
ret <vscale x 16 x i8> %vc
Expand All @@ -202,22 +137,9 @@ define <vscale x 32 x i8> @vsrl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv32i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%vc = lshr <vscale x 32 x i8> %va, %splat
ret <vscale x 32 x i8> %vc
}

define <vscale x 32 x i8> @vsrl_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv32i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
%head = insertelement <vscale x 32 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
%vc = lshr <vscale x 32 x i8> %va, %splat
ret <vscale x 32 x i8> %vc
Expand All @@ -239,22 +161,9 @@ define <vscale x 64 x i8> @vsrl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv64i8_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%vc = lshr <vscale x 64 x i8> %va, %splat
ret <vscale x 64 x i8> %vc
}

define <vscale x 64 x i8> @vsrl_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
; CHECK-LABEL: vsrl_vx_nxv64i8_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
%head = insertelement <vscale x 64 x i8> undef, i8 6, i32 0
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
%vc = lshr <vscale x 64 x i8> %va, %splat
ret <vscale x 64 x i8> %vc
Expand All @@ -276,22 +185,9 @@ define <vscale x 1 x i16> @vsrl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv1i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%vc = lshr <vscale x 1 x i16> %va, %splat
ret <vscale x 1 x i16> %vc
}

define <vscale x 1 x i16> @vsrl_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv1i16_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
%head = insertelement <vscale x 1 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
%vc = lshr <vscale x 1 x i16> %va, %splat
ret <vscale x 1 x i16> %vc
Expand All @@ -313,22 +209,9 @@ define <vscale x 2 x i16> @vsrl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv2i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%vc = lshr <vscale x 2 x i16> %va, %splat
ret <vscale x 2 x i16> %vc
}

define <vscale x 2 x i16> @vsrl_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv2i16_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
%head = insertelement <vscale x 2 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
%vc = lshr <vscale x 2 x i16> %va, %splat
ret <vscale x 2 x i16> %vc
Expand All @@ -350,22 +233,9 @@ define <vscale x 4 x i16> @vsrl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv4i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%vc = lshr <vscale x 4 x i16> %va, %splat
ret <vscale x 4 x i16> %vc
}

define <vscale x 4 x i16> @vsrl_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv4i16_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
%head = insertelement <vscale x 4 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
%vc = lshr <vscale x 4 x i16> %va, %splat
ret <vscale x 4 x i16> %vc
Expand All @@ -387,22 +257,9 @@ define <vscale x 8 x i16> @vsrl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv8i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i16> %vc
}

define <vscale x 8 x i16> @vsrl_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv8i16_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
%head = insertelement <vscale x 8 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i16> %vc
Expand All @@ -424,22 +281,9 @@ define <vscale x 16 x i16> @vsrl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv16i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%vc = lshr <vscale x 16 x i16> %va, %splat
ret <vscale x 16 x i16> %vc
}

define <vscale x 16 x i16> @vsrl_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv16i16_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
%head = insertelement <vscale x 16 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
%vc = lshr <vscale x 16 x i16> %va, %splat
ret <vscale x 16 x i16> %vc
Expand All @@ -461,22 +305,9 @@ define <vscale x 32 x i16> @vsrl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv32i16_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vsrl.vi v16, v16, 31
; CHECK-NEXT: vsrl.vi v16, v16, 6
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%vc = lshr <vscale x 32 x i16> %va, %splat
ret <vscale x 32 x i16> %vc
}

define <vscale x 32 x i16> @vsrl_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
; CHECK-LABEL: vsrl_vx_nxv32i16_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
%head = insertelement <vscale x 32 x i16> undef, i16 6, i32 0
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
%vc = lshr <vscale x 32 x i16> %va, %splat
ret <vscale x 32 x i16> %vc
Expand Down Expand Up @@ -506,19 +337,6 @@ define <vscale x 1 x i32> @vsrl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
ret <vscale x 1 x i32> %vc
}

define <vscale x 1 x i32> @vsrl_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vsrl_vx_nxv1i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vc = lshr <vscale x 1 x i32> %va, %splat
ret <vscale x 1 x i32> %vc
}

define <vscale x 2 x i32> @vsrl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vsrl_vx_nxv2i32:
; CHECK: # %bb.0:
Expand All @@ -543,19 +361,6 @@ define <vscale x 2 x i32> @vsrl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
ret <vscale x 2 x i32> %vc
}

define <vscale x 2 x i32> @vsrl_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vsrl_vx_nxv2i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vc = lshr <vscale x 2 x i32> %va, %splat
ret <vscale x 2 x i32> %vc
}

define <vscale x 4 x i32> @vsrl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vsrl_vx_nxv4i32:
; CHECK: # %bb.0:
Expand All @@ -580,19 +385,6 @@ define <vscale x 4 x i32> @vsrl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
ret <vscale x 4 x i32> %vc
}

define <vscale x 4 x i32> @vsrl_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vsrl_vx_nxv4i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vc = lshr <vscale x 4 x i32> %va, %splat
ret <vscale x 4 x i32> %vc
}

define <vscale x 8 x i32> @vsrl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vsrl_vx_nxv8i32:
; CHECK: # %bb.0:
Expand All @@ -617,19 +409,6 @@ define <vscale x 8 x i32> @vsrl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
ret <vscale x 8 x i32> %vc
}

define <vscale x 8 x i32> @vsrl_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vsrl_vx_nxv8i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = lshr <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i32> %vc
}

define <vscale x 16 x i32> @vsrl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
; CHECK-LABEL: vsrl_vx_nxv16i32:
; CHECK: # %bb.0:
Expand All @@ -654,19 +433,6 @@ define <vscale x 16 x i32> @vsrl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
ret <vscale x 16 x i32> %vc
}

define <vscale x 16 x i32> @vsrl_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
; CHECK-LABEL: vsrl_vx_nxv16i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu
; CHECK-NEXT: vsrl.vx v16, v16, a0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
%vc = lshr <vscale x 16 x i32> %va, %splat
ret <vscale x 16 x i32> %vc
}

define <vscale x 1 x i64> @vsrl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vsrl_vx_nxv1i64:
; CHECK: # %bb.0:
Expand Down