304 changes: 152 additions & 152 deletions llvm/test/CodeGen/RISCV/fpclamptosat.ll
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10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/legalize-fneg.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -56,16 +56,16 @@ entry:
define void @test3(ptr %a, ptr %b) nounwind {
; RV32-LABEL: test3:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 4(a1)
; RV32-NEXT: lw a3, 12(a1)
; RV32-NEXT: lw a2, 12(a1)
; RV32-NEXT: lw a3, 4(a1)
; RV32-NEXT: lw a4, 8(a1)
; RV32-NEXT: lw a1, 0(a1)
; RV32-NEXT: lui a5, 524288
; RV32-NEXT: xor a3, a3, a5
; RV32-NEXT: xor a2, a2, a5
; RV32-NEXT: sw a4, 8(a0)
; RV32-NEXT: sw a1, 0(a0)
; RV32-NEXT: sw a2, 4(a0)
; RV32-NEXT: sw a3, 12(a0)
; RV32-NEXT: sw a3, 4(a0)
; RV32-NEXT: sw a2, 12(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: test3:
Expand Down
34 changes: 17 additions & 17 deletions llvm/test/CodeGen/RISCV/llvm.exp10.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -222,32 +222,32 @@ define <3 x half> @exp10_v3f16(<3 x half> %x) {
; RV64IFD-NEXT: .cfi_offset s1, -24
; RV64IFD-NEXT: .cfi_offset s2, -32
; RV64IFD-NEXT: .cfi_offset fs0, -40
; RV64IFD-NEXT: lhu s1, 16(a1)
; RV64IFD-NEXT: lhu s2, 0(a1)
; RV64IFD-NEXT: lhu a1, 8(a1)
; RV64IFD-NEXT: lhu s1, 0(a1)
; RV64IFD-NEXT: lhu a2, 8(a1)
; RV64IFD-NEXT: lhu s2, 16(a1)
; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: fmv.w.x fa0, a1
; RV64IFD-NEXT: fmv.w.x fa0, a2
; RV64IFD-NEXT: call __extendhfsf2
; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.s fs0, fa0
; RV64IFD-NEXT: fmv.w.x fa0, s2
; RV64IFD-NEXT: fmv.w.x fa0, s1
; RV64IFD-NEXT: call __extendhfsf2
; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.x.w a0, fs0
; RV64IFD-NEXT: slli s2, a0, 16
; RV64IFD-NEXT: slli s1, a0, 16
; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: slli a0, a0, 48
; RV64IFD-NEXT: srli a0, a0, 48
; RV64IFD-NEXT: or s2, a0, s2
; RV64IFD-NEXT: fmv.w.x fa0, s1
; RV64IFD-NEXT: or s1, a0, s1
; RV64IFD-NEXT: fmv.w.x fa0, s2
; RV64IFD-NEXT: call __extendhfsf2
; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.x.w a0, fa0
; RV64IFD-NEXT: sh a0, 4(s0)
; RV64IFD-NEXT: sw s2, 0(s0)
; RV64IFD-NEXT: sw s1, 0(s0)
; RV64IFD-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -349,27 +349,27 @@ define <4 x half> @exp10_v4f16(<4 x half> %x) {
; RV64IFD-NEXT: .cfi_offset fs0, -48
; RV64IFD-NEXT: .cfi_offset fs1, -56
; RV64IFD-NEXT: .cfi_offset fs2, -64
; RV64IFD-NEXT: lhu s1, 24(a1)
; RV64IFD-NEXT: lhu s2, 0(a1)
; RV64IFD-NEXT: lhu s3, 8(a1)
; RV64IFD-NEXT: lhu a1, 16(a1)
; RV64IFD-NEXT: lhu s1, 0(a1)
; RV64IFD-NEXT: lhu s2, 8(a1)
; RV64IFD-NEXT: lhu a2, 16(a1)
; RV64IFD-NEXT: lhu s3, 24(a1)
; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: fmv.w.x fa0, a1
; RV64IFD-NEXT: fmv.w.x fa0, a2
; RV64IFD-NEXT: call __extendhfsf2
; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.s fs0, fa0
; RV64IFD-NEXT: fmv.w.x fa0, s3
; RV64IFD-NEXT: fmv.w.x fa0, s2
; RV64IFD-NEXT: call __extendhfsf2
; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.s fs1, fa0
; RV64IFD-NEXT: fmv.w.x fa0, s2
; RV64IFD-NEXT: fmv.w.x fa0, s1
; RV64IFD-NEXT: call __extendhfsf2
; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: call __truncsfhf2
; RV64IFD-NEXT: fmv.s fs2, fa0
; RV64IFD-NEXT: fmv.w.x fa0, s1
; RV64IFD-NEXT: fmv.w.x fa0, s3
; RV64IFD-NEXT: call __extendhfsf2
; RV64IFD-NEXT: call exp10f
; RV64IFD-NEXT: fmv.x.w s1, fs2
Expand Down
112 changes: 56 additions & 56 deletions llvm/test/CodeGen/RISCV/llvm.frexp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -738,33 +738,33 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi
; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s0, 12(a1)
; RV32I-NEXT: lw s1, 8(a1)
; RV32I-NEXT: lw s2, 4(a1)
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw s0, 4(a1)
; RV32I-NEXT: lw s1, 8(a1)
; RV32I-NEXT: lw s2, 12(a1)
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call frexpf
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a1, sp, 12
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call frexpf
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, sp, 16
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call frexpf
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, sp, 20
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call frexpf
; RV32I-NEXT: lw a1, 8(sp)
; RV32I-NEXT: lw a2, 12(sp)
; RV32I-NEXT: lw a3, 16(sp)
; RV32I-NEXT: lw a4, 20(sp)
; RV32I-NEXT: sw a0, 12(s3)
; RV32I-NEXT: sw s1, 8(s3)
; RV32I-NEXT: sw s2, 4(s3)
; RV32I-NEXT: sw s0, 4(s3)
; RV32I-NEXT: sw s4, 0(s3)
; RV32I-NEXT: sw a4, 28(s3)
; RV32I-NEXT: sw a3, 24(s3)
Expand All @@ -788,33 +788,33 @@ define { <4 x float>, <4 x i32> } @test_frexp_v4f32_v4i32(<4 x float> %a) nounwi
; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw s0, 24(a1)
; RV64I-NEXT: lw s1, 16(a1)
; RV64I-NEXT: lw s2, 8(a1)
; RV64I-NEXT: lw a2, 0(a1)
; RV64I-NEXT: lw s0, 8(a1)
; RV64I-NEXT: lw s1, 16(a1)
; RV64I-NEXT: lw s2, 24(a1)
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call frexpf
; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call frexpf
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, sp, 8
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call frexpf
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call frexpf
; RV64I-NEXT: lw a1, 0(sp)
; RV64I-NEXT: lw a2, 4(sp)
; RV64I-NEXT: lw a3, 8(sp)
; RV64I-NEXT: lw a4, 12(sp)
; RV64I-NEXT: sw a0, 12(s3)
; RV64I-NEXT: sw s1, 8(s3)
; RV64I-NEXT: sw s2, 4(s3)
; RV64I-NEXT: sw s0, 4(s3)
; RV64I-NEXT: sw s4, 0(s3)
; RV64I-NEXT: sw a4, 28(s3)
; RV64I-NEXT: sw a3, 24(s3)
Expand Down Expand Up @@ -1006,29 +1006,29 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi
; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s0, 12(a1)
; RV32I-NEXT: lw s1, 8(a1)
; RV32I-NEXT: lw s2, 4(a1)
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw s0, 4(a1)
; RV32I-NEXT: lw s1, 8(a1)
; RV32I-NEXT: lw s2, 12(a1)
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call frexpf
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a1, sp, 12
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call frexpf
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: addi a1, sp, 16
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call frexpf
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: addi a1, sp, 20
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call frexpf
; RV32I-NEXT: sw a0, 12(s3)
; RV32I-NEXT: sw s1, 8(s3)
; RV32I-NEXT: sw s2, 4(s3)
; RV32I-NEXT: sw s0, 4(s3)
; RV32I-NEXT: sw s4, 0(s3)
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
Expand All @@ -1048,29 +1048,29 @@ define <4 x float> @test_frexp_v4f32_v4i32_only_use_fract(<4 x float> %a) nounwi
; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw s0, 24(a1)
; RV64I-NEXT: lw s1, 16(a1)
; RV64I-NEXT: lw s2, 8(a1)
; RV64I-NEXT: lw a2, 0(a1)
; RV64I-NEXT: lw s0, 8(a1)
; RV64I-NEXT: lw s1, 16(a1)
; RV64I-NEXT: lw s2, 24(a1)
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call frexpf
; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call frexpf
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: addi a1, sp, 8
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call frexpf
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call frexpf
; RV64I-NEXT: sw a0, 12(s3)
; RV64I-NEXT: sw s1, 8(s3)
; RV64I-NEXT: sw s2, 4(s3)
; RV64I-NEXT: sw s0, 4(s3)
; RV64I-NEXT: sw s4, 0(s3)
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -1254,22 +1254,22 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind {
; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: lw s0, 12(a1)
; RV32I-NEXT: lw s1, 8(a1)
; RV32I-NEXT: lw s2, 4(a1)
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw s0, 4(a1)
; RV32I-NEXT: lw s1, 8(a1)
; RV32I-NEXT: lw s2, 12(a1)
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: addi a1, sp, 12
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: call frexpf
; RV32I-NEXT: addi a1, sp, 16
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call frexpf
; RV32I-NEXT: addi a1, sp, 20
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call frexpf
; RV32I-NEXT: addi a1, sp, 24
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call frexpf
; RV32I-NEXT: lw a0, 24(sp)
; RV32I-NEXT: lw a1, 20(sp)
Expand All @@ -1295,22 +1295,22 @@ define <4 x i32> @test_frexp_v4f32_v4i32_only_use_exp(<4 x float> %a) nounwind {
; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: lw s0, 24(a1)
; RV64I-NEXT: lw s1, 16(a1)
; RV64I-NEXT: lw s2, 8(a1)
; RV64I-NEXT: lw a2, 0(a1)
; RV64I-NEXT: lw s0, 8(a1)
; RV64I-NEXT: lw s1, 16(a1)
; RV64I-NEXT: lw s2, 24(a1)
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: addi a1, sp, 8
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: call frexpf
; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call frexpf
; RV64I-NEXT: addi a1, sp, 16
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call frexpf
; RV64I-NEXT: addi a1, sp, 20
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call frexpf
; RV64I-NEXT: lw a0, 20(sp)
; RV64I-NEXT: lw a1, 16(sp)
Expand Down Expand Up @@ -1584,16 +1584,16 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind {
; RV32IFD-NEXT: addi a2, sp, 36
; RV32IFD-NEXT: sw a3, 0(sp)
; RV32IFD-NEXT: call frexpl
; RV32IFD-NEXT: lw a0, 36(sp)
; RV32IFD-NEXT: lw a0, 24(sp)
; RV32IFD-NEXT: lw a1, 28(sp)
; RV32IFD-NEXT: lw a2, 24(sp)
; RV32IFD-NEXT: lw a2, 16(sp)
; RV32IFD-NEXT: lw a3, 20(sp)
; RV32IFD-NEXT: lw a4, 16(sp)
; RV32IFD-NEXT: lw a4, 36(sp)
; RV32IFD-NEXT: sw a1, 12(s0)
; RV32IFD-NEXT: sw a2, 8(s0)
; RV32IFD-NEXT: sw a0, 8(s0)
; RV32IFD-NEXT: sw a3, 4(s0)
; RV32IFD-NEXT: sw a4, 0(s0)
; RV32IFD-NEXT: sw a0, 16(s0)
; RV32IFD-NEXT: sw a2, 0(s0)
; RV32IFD-NEXT: sw a4, 16(s0)
; RV32IFD-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 48
Expand Down Expand Up @@ -1637,16 +1637,16 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind {
; RV32IZFINXZDINX-NEXT: addi a2, sp, 36
; RV32IZFINXZDINX-NEXT: sw a3, 0(sp)
; RV32IZFINXZDINX-NEXT: call frexpl
; RV32IZFINXZDINX-NEXT: lw a0, 36(sp)
; RV32IZFINXZDINX-NEXT: lw a0, 24(sp)
; RV32IZFINXZDINX-NEXT: lw a1, 28(sp)
; RV32IZFINXZDINX-NEXT: lw a2, 24(sp)
; RV32IZFINXZDINX-NEXT: lw a2, 16(sp)
; RV32IZFINXZDINX-NEXT: lw a3, 20(sp)
; RV32IZFINXZDINX-NEXT: lw a4, 16(sp)
; RV32IZFINXZDINX-NEXT: lw a4, 36(sp)
; RV32IZFINXZDINX-NEXT: sw a1, 12(s0)
; RV32IZFINXZDINX-NEXT: sw a2, 8(s0)
; RV32IZFINXZDINX-NEXT: sw a0, 8(s0)
; RV32IZFINXZDINX-NEXT: sw a3, 4(s0)
; RV32IZFINXZDINX-NEXT: sw a4, 0(s0)
; RV32IZFINXZDINX-NEXT: sw a0, 16(s0)
; RV32IZFINXZDINX-NEXT: sw a2, 0(s0)
; RV32IZFINXZDINX-NEXT: sw a4, 16(s0)
; RV32IZFINXZDINX-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 48
Expand Down Expand Up @@ -1690,16 +1690,16 @@ define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind {
; RV32I-NEXT: addi a2, sp, 36
; RV32I-NEXT: sw a3, 0(sp)
; RV32I-NEXT: call frexpl
; RV32I-NEXT: lw a0, 36(sp)
; RV32I-NEXT: lw a0, 24(sp)
; RV32I-NEXT: lw a1, 28(sp)
; RV32I-NEXT: lw a2, 24(sp)
; RV32I-NEXT: lw a2, 16(sp)
; RV32I-NEXT: lw a3, 20(sp)
; RV32I-NEXT: lw a4, 16(sp)
; RV32I-NEXT: lw a4, 36(sp)
; RV32I-NEXT: sw a1, 12(s0)
; RV32I-NEXT: sw a2, 8(s0)
; RV32I-NEXT: sw a0, 8(s0)
; RV32I-NEXT: sw a3, 4(s0)
; RV32I-NEXT: sw a4, 0(s0)
; RV32I-NEXT: sw a0, 16(s0)
; RV32I-NEXT: sw a2, 0(s0)
; RV32I-NEXT: sw a4, 16(s0)
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/memcpy.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,46 +25,46 @@ define i32 @t0() {
; RV32: # %bb.0: # %entry
; RV32-NEXT: lui a0, %hi(src)
; RV32-NEXT: lw a1, %lo(src)(a0)
; RV32-NEXT: lui a2, %hi(dst)
; RV32-NEXT: sw a1, %lo(dst)(a2)
; RV32-NEXT: addi a0, a0, %lo(src)
; RV32-NEXT: lbu a1, 10(a0)
; RV32-NEXT: lw a2, 4(a0)
; RV32-NEXT: lh a3, 8(a0)
; RV32-NEXT: lw a0, 4(a0)
; RV32-NEXT: addi a2, a2, %lo(dst)
; RV32-NEXT: sb a1, 10(a2)
; RV32-NEXT: sh a3, 8(a2)
; RV32-NEXT: sw a0, 4(a2)
; RV32-NEXT: lbu a0, 10(a0)
; RV32-NEXT: lui a4, %hi(dst)
; RV32-NEXT: sw a1, %lo(dst)(a4)
; RV32-NEXT: addi a1, a4, %lo(dst)
; RV32-NEXT: sb a0, 10(a1)
; RV32-NEXT: sh a3, 8(a1)
; RV32-NEXT: sw a2, 4(a1)
; RV32-NEXT: li a0, 0
; RV32-NEXT: ret
;
; RV64-LABEL: t0:
; RV64: # %bb.0: # %entry
; RV64-NEXT: lui a0, %hi(src)
; RV64-NEXT: ld a1, %lo(src)(a0)
; RV64-NEXT: lui a2, %hi(dst)
; RV64-NEXT: addi a0, a0, %lo(src)
; RV64-NEXT: lbu a3, 10(a0)
; RV64-NEXT: lh a0, 8(a0)
; RV64-NEXT: sd a1, %lo(dst)(a2)
; RV64-NEXT: addi a1, a2, %lo(dst)
; RV64-NEXT: sb a3, 10(a1)
; RV64-NEXT: sh a0, 8(a1)
; RV64-NEXT: lh a2, 8(a0)
; RV64-NEXT: lbu a0, 10(a0)
; RV64-NEXT: lui a3, %hi(dst)
; RV64-NEXT: sd a1, %lo(dst)(a3)
; RV64-NEXT: addi a1, a3, %lo(dst)
; RV64-NEXT: sb a0, 10(a1)
; RV64-NEXT: sh a2, 8(a1)
; RV64-NEXT: li a0, 0
; RV64-NEXT: ret
;
; RV32-FAST-LABEL: t0:
; RV32-FAST: # %bb.0: # %entry
; RV32-FAST-NEXT: lui a0, %hi(src)
; RV32-FAST-NEXT: lw a1, %lo(src)(a0)
; RV32-FAST-NEXT: lui a2, %hi(dst)
; RV32-FAST-NEXT: addi a0, a0, %lo(src)
; RV32-FAST-NEXT: lw a3, 7(a0)
; RV32-FAST-NEXT: lw a0, 4(a0)
; RV32-FAST-NEXT: sw a1, %lo(dst)(a2)
; RV32-FAST-NEXT: addi a1, a2, %lo(dst)
; RV32-FAST-NEXT: sw a3, 7(a1)
; RV32-FAST-NEXT: sw a0, 4(a1)
; RV32-FAST-NEXT: lw a2, 4(a0)
; RV32-FAST-NEXT: lw a0, 7(a0)
; RV32-FAST-NEXT: lui a3, %hi(dst)
; RV32-FAST-NEXT: sw a1, %lo(dst)(a3)
; RV32-FAST-NEXT: addi a1, a3, %lo(dst)
; RV32-FAST-NEXT: sw a0, 7(a1)
; RV32-FAST-NEXT: sw a2, 4(a1)
; RV32-FAST-NEXT: li a0, 0
; RV32-FAST-NEXT: ret
;
Expand Down Expand Up @@ -166,16 +166,16 @@ define void @t2(ptr nocapture %C) nounwind {
; RV64-FAST-NEXT: lui a1, %hi(.L.str2)
; RV64-FAST-NEXT: ld a2, %lo(.L.str2)(a1)
; RV64-FAST-NEXT: sd a2, 0(a0)
; RV64-FAST-NEXT: lui a2, 1156
; RV64-FAST-NEXT: addi a2, a2, 332
; RV64-FAST-NEXT: addi a1, a1, %lo(.L.str2)
; RV64-FAST-NEXT: ld a3, 24(a1)
; RV64-FAST-NEXT: ld a4, 16(a1)
; RV64-FAST-NEXT: ld a1, 8(a1)
; RV64-FAST-NEXT: sw a2, 32(a0)
; RV64-FAST-NEXT: sd a3, 24(a0)
; RV64-FAST-NEXT: sd a4, 16(a0)
; RV64-FAST-NEXT: sd a1, 8(a0)
; RV64-FAST-NEXT: ld a2, 8(a1)
; RV64-FAST-NEXT: ld a3, 16(a1)
; RV64-FAST-NEXT: ld a1, 24(a1)
; RV64-FAST-NEXT: lui a4, 1156
; RV64-FAST-NEXT: addi a4, a4, 332
; RV64-FAST-NEXT: sw a4, 32(a0)
; RV64-FAST-NEXT: sd a1, 24(a0)
; RV64-FAST-NEXT: sd a3, 16(a0)
; RV64-FAST-NEXT: sd a2, 8(a0)
; RV64-FAST-NEXT: ret
entry:
tail call void @llvm.memcpy.p0.p0.i64(ptr %C, ptr @.str2, i64 36, i1 false)
Expand Down
10 changes: 6 additions & 4 deletions llvm/test/CodeGen/RISCV/misched-load-clustering.ll
View file
Original file line number Diff line number Diff line change
@@ -1,12 +1,14 @@
; REQUIRES: asserts
; RUN: llc -mtriple=riscv32 -verify-misched -debug-only=machine-scheduler -o - 2>&1 < %s \
; RUN: llc -mtriple=riscv32 -verify-misched -riscv-misched-load-clustering=false \
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
; RUN: | FileCheck -check-prefix=NOCLUSTER %s
; RUN: llc -mtriple=riscv64 -verify-misched -debug-only=machine-scheduler -o - 2>&1 < %s \
; RUN: llc -mtriple=riscv64 -verify-misched -riscv-misched-load-clustering=false \
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
; RUN: | FileCheck -check-prefix=NOCLUSTER %s
; RUN: llc -mtriple=riscv32 -riscv-misched-load-clustering -verify-misched \
; RUN: llc -mtriple=riscv32 -verify-misched \
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
; RUN: | FileCheck -check-prefix=LDCLUSTER %s
; RUN: llc -mtriple=riscv64 -riscv-misched-load-clustering -verify-misched \
; RUN: llc -mtriple=riscv64 -verify-misched \
; RUN: -debug-only=machine-scheduler -o - 2>&1 < %s \
; RUN: | FileCheck -check-prefix=LDCLUSTER %s

Expand Down
134 changes: 67 additions & 67 deletions llvm/test/CodeGen/RISCV/mul.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1351,48 +1351,48 @@ define i128 @muli128_m3840(i128 %a) nounwind {
; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw a2, 12(a1)
; RV32IM-NEXT: lw a3, 8(a1)
; RV32IM-NEXT: lw a4, 0(a1)
; RV32IM-NEXT: lw a1, 4(a1)
; RV32IM-NEXT: lw a2, 0(a1)
; RV32IM-NEXT: lw a3, 4(a1)
; RV32IM-NEXT: lw a4, 8(a1)
; RV32IM-NEXT: lw a1, 12(a1)
; RV32IM-NEXT: li a5, -15
; RV32IM-NEXT: slli a5, a5, 8
; RV32IM-NEXT: mulhu a6, a4, a5
; RV32IM-NEXT: mul a7, a1, a5
; RV32IM-NEXT: mulhu a6, a2, a5
; RV32IM-NEXT: mul a7, a3, a5
; RV32IM-NEXT: add a6, a7, a6
; RV32IM-NEXT: sltu a7, a6, a7
; RV32IM-NEXT: mulhu t0, a1, a5
; RV32IM-NEXT: mulhu t0, a3, a5
; RV32IM-NEXT: add a7, t0, a7
; RV32IM-NEXT: sub a6, a6, a4
; RV32IM-NEXT: neg t0, a4
; RV32IM-NEXT: sub a6, a6, a2
; RV32IM-NEXT: neg t0, a2
; RV32IM-NEXT: sltu t1, a6, t0
; RV32IM-NEXT: li t2, -1
; RV32IM-NEXT: mulhu t3, a4, t2
; RV32IM-NEXT: mulhu t3, a2, t2
; RV32IM-NEXT: add t1, t3, t1
; RV32IM-NEXT: add t1, a7, t1
; RV32IM-NEXT: sub t4, t1, a1
; RV32IM-NEXT: mul t5, a3, a5
; RV32IM-NEXT: sub t5, t5, a4
; RV32IM-NEXT: sub t4, t1, a3
; RV32IM-NEXT: mul t5, a4, a5
; RV32IM-NEXT: sub t5, t5, a2
; RV32IM-NEXT: add t6, t4, t5
; RV32IM-NEXT: sltu s0, t6, t4
; RV32IM-NEXT: neg s1, a1
; RV32IM-NEXT: neg s1, a3
; RV32IM-NEXT: sltu t4, t4, s1
; RV32IM-NEXT: sltu a7, t1, a7
; RV32IM-NEXT: mulhu t1, a1, t2
; RV32IM-NEXT: mulhu t1, a3, t2
; RV32IM-NEXT: add a7, t1, a7
; RV32IM-NEXT: add a7, a7, t4
; RV32IM-NEXT: sltu t0, t5, t0
; RV32IM-NEXT: mul a2, a2, a5
; RV32IM-NEXT: mulhu t1, a3, a5
; RV32IM-NEXT: sub a3, t1, a3
; RV32IM-NEXT: add a2, a3, a2
; RV32IM-NEXT: mul a1, a1, a5
; RV32IM-NEXT: mulhu t1, a4, a5
; RV32IM-NEXT: sub a4, t1, a4
; RV32IM-NEXT: add a1, a4, a1
; RV32IM-NEXT: sub a1, t3, a1
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: add a3, a2, a3
; RV32IM-NEXT: sub a3, t3, a3
; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: add a1, a1, t0
; RV32IM-NEXT: add a1, a7, a1
; RV32IM-NEXT: add a1, a1, s0
; RV32IM-NEXT: mul a2, a4, a5
; RV32IM-NEXT: mul a2, a2, a5
; RV32IM-NEXT: sw a2, 0(a0)
; RV32IM-NEXT: sw a6, 4(a0)
; RV32IM-NEXT: sw t6, 8(a0)
Expand Down Expand Up @@ -1436,92 +1436,92 @@ define i128 @muli128_m63(i128 %a) nounwind {
; RV32I-LABEL: muli128_m63:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a1)
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: lw a6, 8(a1)
; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: slli a3, a2, 6
; RV32I-NEXT: sltu a5, a2, a3
; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: slli a1, a2, 6
; RV32I-NEXT: sltu a4, a2, a1
; RV32I-NEXT: srli a7, a2, 26
; RV32I-NEXT: slli t0, a1, 6
; RV32I-NEXT: slli t0, a3, 6
; RV32I-NEXT: or a7, t0, a7
; RV32I-NEXT: mv t0, a5
; RV32I-NEXT: beq a1, a7, .LBB37_2
; RV32I-NEXT: mv t0, a4
; RV32I-NEXT: beq a3, a7, .LBB37_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu t0, a1, a7
; RV32I-NEXT: sltu t0, a3, a7
; RV32I-NEXT: .LBB37_2:
; RV32I-NEXT: srli t1, a1, 26
; RV32I-NEXT: srli t1, a3, 26
; RV32I-NEXT: slli t2, a6, 6
; RV32I-NEXT: or t1, t2, t1
; RV32I-NEXT: sub t2, a6, t1
; RV32I-NEXT: sltu t3, t2, t0
; RV32I-NEXT: sltu t1, a6, t1
; RV32I-NEXT: srli a6, a6, 26
; RV32I-NEXT: slli t4, a4, 6
; RV32I-NEXT: slli t4, a5, 6
; RV32I-NEXT: or a6, t4, a6
; RV32I-NEXT: sub a4, a4, a6
; RV32I-NEXT: sub a4, a4, t1
; RV32I-NEXT: sub a4, a4, t3
; RV32I-NEXT: sub a5, a5, a6
; RV32I-NEXT: sub a5, a5, t1
; RV32I-NEXT: sub a5, a5, t3
; RV32I-NEXT: sub a6, t2, t0
; RV32I-NEXT: sub a1, a1, a7
; RV32I-NEXT: sub a1, a1, a5
; RV32I-NEXT: sub a2, a2, a3
; RV32I-NEXT: sub a3, a3, a7
; RV32I-NEXT: sub a3, a3, a4
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: sw a1, 4(a0)
; RV32I-NEXT: sw a3, 4(a0)
; RV32I-NEXT: sw a6, 8(a0)
; RV32I-NEXT: sw a4, 12(a0)
; RV32I-NEXT: sw a5, 12(a0)
; RV32I-NEXT: ret
;
; RV32IM-LABEL: muli128_m63:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi sp, sp, -16
; RV32IM-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; RV32IM-NEXT: lw a2, 12(a1)
; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a4, 4(a1)
; RV32IM-NEXT: lw a1, 8(a1)
; RV32IM-NEXT: lw a2, 0(a1)
; RV32IM-NEXT: lw a3, 4(a1)
; RV32IM-NEXT: lw a4, 8(a1)
; RV32IM-NEXT: lw a1, 12(a1)
; RV32IM-NEXT: li a5, -63
; RV32IM-NEXT: mulhu a6, a3, a5
; RV32IM-NEXT: slli a7, a4, 6
; RV32IM-NEXT: sub a7, a4, a7
; RV32IM-NEXT: mulhu a6, a2, a5
; RV32IM-NEXT: slli a7, a3, 6
; RV32IM-NEXT: sub a7, a3, a7
; RV32IM-NEXT: add a6, a7, a6
; RV32IM-NEXT: sltu a7, a6, a7
; RV32IM-NEXT: mulhu t0, a4, a5
; RV32IM-NEXT: mulhu t0, a3, a5
; RV32IM-NEXT: add a7, t0, a7
; RV32IM-NEXT: sub a6, a6, a3
; RV32IM-NEXT: neg t0, a3
; RV32IM-NEXT: sub a6, a6, a2
; RV32IM-NEXT: neg t0, a2
; RV32IM-NEXT: sltu t1, a6, t0
; RV32IM-NEXT: li t2, -1
; RV32IM-NEXT: mulhu t3, a3, t2
; RV32IM-NEXT: mulhu t3, a2, t2
; RV32IM-NEXT: add t1, t3, t1
; RV32IM-NEXT: add t1, a7, t1
; RV32IM-NEXT: sub t4, t1, a4
; RV32IM-NEXT: slli t5, a1, 6
; RV32IM-NEXT: sub t6, a1, a3
; RV32IM-NEXT: sub t4, t1, a3
; RV32IM-NEXT: slli t5, a4, 6
; RV32IM-NEXT: sub t6, a4, a2
; RV32IM-NEXT: sub t5, t6, t5
; RV32IM-NEXT: add t6, t4, t5
; RV32IM-NEXT: sltu s0, t6, t4
; RV32IM-NEXT: neg s1, a4
; RV32IM-NEXT: neg s1, a3
; RV32IM-NEXT: sltu t4, t4, s1
; RV32IM-NEXT: sltu a7, t1, a7
; RV32IM-NEXT: mulhu t1, a4, t2
; RV32IM-NEXT: mulhu t1, a3, t2
; RV32IM-NEXT: add a7, t1, a7
; RV32IM-NEXT: add a7, a7, t4
; RV32IM-NEXT: sltu t0, t5, t0
; RV32IM-NEXT: slli t1, a2, 6
; RV32IM-NEXT: sub a2, a2, t1
; RV32IM-NEXT: mulhu a5, a1, a5
; RV32IM-NEXT: sub a5, a5, a1
; RV32IM-NEXT: add a2, a5, a2
; RV32IM-NEXT: add a4, a3, a4
; RV32IM-NEXT: sub a1, t3, a4
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: slli t1, a1, 6
; RV32IM-NEXT: sub a1, a1, t1
; RV32IM-NEXT: mulhu a5, a4, a5
; RV32IM-NEXT: sub a5, a5, a4
; RV32IM-NEXT: add a1, a5, a1
; RV32IM-NEXT: add a3, a2, a3
; RV32IM-NEXT: sub a3, t3, a3
; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: add a1, a1, t0
; RV32IM-NEXT: add a1, a7, a1
; RV32IM-NEXT: add a1, a1, s0
; RV32IM-NEXT: slli a2, a3, 6
; RV32IM-NEXT: sub a3, a3, a2
; RV32IM-NEXT: sw a3, 0(a0)
; RV32IM-NEXT: slli a3, a2, 6
; RV32IM-NEXT: sub a2, a2, a3
; RV32IM-NEXT: sw a2, 0(a0)
; RV32IM-NEXT: sw a6, 4(a0)
; RV32IM-NEXT: sw t6, 8(a0)
; RV32IM-NEXT: sw a1, 12(a0)
Expand Down
1,200 changes: 600 additions & 600 deletions llvm/test/CodeGen/RISCV/nontemporal.ll
View file

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1241,8 +1241,8 @@ define i64 @foo2(ptr %p) {
define void @PR41129(ptr %p64) {
; RV32-LABEL: PR41129:
; RV32: # %bb.0: # %entry
; RV32-NEXT: lw a2, 4(a0)
; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a2, 4(a0)
; RV32-NEXT: or a3, a1, a2
; RV32-NEXT: beqz a3, .LBB37_2
; RV32-NEXT: # %bb.1: # %false
Expand Down
816 changes: 408 additions & 408 deletions llvm/test/CodeGen/RISCV/push-pop-popret.ll
View file

Large diffs are not rendered by default.

72 changes: 36 additions & 36 deletions llvm/test/CodeGen/RISCV/reduction-formation.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,24 +8,24 @@
define i32 @reduce_sum_4xi32(<4 x i32> %v) {
; RV32-LABEL: reduce_sum_4xi32:
; RV32: # %bb.0:
; RV32-NEXT: lw a1, 12(a0)
; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a2, 4(a0)
; RV32-NEXT: lw a3, 0(a0)
; RV32-NEXT: lw a0, 8(a0)
; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: add a0, a2, a0
; RV32-NEXT: lw a3, 8(a0)
; RV32-NEXT: lw a0, 12(a0)
; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: add a0, a3, a0
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: reduce_sum_4xi32:
; RV64: # %bb.0:
; RV64-NEXT: lw a1, 24(a0)
; RV64-NEXT: lw a1, 0(a0)
; RV64-NEXT: lw a2, 8(a0)
; RV64-NEXT: lw a3, 0(a0)
; RV64-NEXT: lw a0, 16(a0)
; RV64-NEXT: add a2, a3, a2
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: addw a0, a2, a0
; RV64-NEXT: lw a3, 16(a0)
; RV64-NEXT: lw a0, 24(a0)
; RV64-NEXT: add a1, a1, a2
; RV64-NEXT: add a0, a3, a0
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ret
%e0 = extractelement <4 x i32> %v, i32 0
%e1 = extractelement <4 x i32> %v, i32 1
Expand All @@ -40,24 +40,24 @@ define i32 @reduce_sum_4xi32(<4 x i32> %v) {
define i32 @reduce_xor_4xi32(<4 x i32> %v) {
; RV32-LABEL: reduce_xor_4xi32:
; RV32: # %bb.0:
; RV32-NEXT: lw a1, 12(a0)
; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a2, 4(a0)
; RV32-NEXT: lw a3, 0(a0)
; RV32-NEXT: lw a0, 8(a0)
; RV32-NEXT: xor a2, a3, a2
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: xor a0, a2, a0
; RV32-NEXT: lw a3, 8(a0)
; RV32-NEXT: lw a0, 12(a0)
; RV32-NEXT: xor a1, a1, a2
; RV32-NEXT: xor a0, a3, a0
; RV32-NEXT: xor a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: reduce_xor_4xi32:
; RV64: # %bb.0:
; RV64-NEXT: ld a1, 24(a0)
; RV64-NEXT: ld a1, 0(a0)
; RV64-NEXT: ld a2, 8(a0)
; RV64-NEXT: ld a3, 0(a0)
; RV64-NEXT: ld a0, 16(a0)
; RV64-NEXT: xor a2, a3, a2
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: xor a0, a2, a0
; RV64-NEXT: ld a3, 16(a0)
; RV64-NEXT: ld a0, 24(a0)
; RV64-NEXT: xor a1, a1, a2
; RV64-NEXT: xor a0, a3, a0
; RV64-NEXT: xor a0, a1, a0
; RV64-NEXT: ret
%e0 = extractelement <4 x i32> %v, i32 0
%e1 = extractelement <4 x i32> %v, i32 1
Expand All @@ -72,24 +72,24 @@ define i32 @reduce_xor_4xi32(<4 x i32> %v) {
define i32 @reduce_or_4xi32(<4 x i32> %v) {
; RV32-LABEL: reduce_or_4xi32:
; RV32: # %bb.0:
; RV32-NEXT: lw a1, 12(a0)
; RV32-NEXT: lw a1, 0(a0)
; RV32-NEXT: lw a2, 4(a0)
; RV32-NEXT: lw a3, 0(a0)
; RV32-NEXT: lw a0, 8(a0)
; RV32-NEXT: or a2, a3, a2
; RV32-NEXT: or a0, a0, a1
; RV32-NEXT: or a0, a2, a0
; RV32-NEXT: lw a3, 8(a0)
; RV32-NEXT: lw a0, 12(a0)
; RV32-NEXT: or a1, a1, a2
; RV32-NEXT: or a0, a3, a0
; RV32-NEXT: or a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: reduce_or_4xi32:
; RV64: # %bb.0:
; RV64-NEXT: ld a1, 24(a0)
; RV64-NEXT: ld a1, 0(a0)
; RV64-NEXT: ld a2, 8(a0)
; RV64-NEXT: ld a3, 0(a0)
; RV64-NEXT: ld a0, 16(a0)
; RV64-NEXT: or a2, a3, a2
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: or a0, a2, a0
; RV64-NEXT: ld a3, 16(a0)
; RV64-NEXT: ld a0, 24(a0)
; RV64-NEXT: or a1, a1, a2
; RV64-NEXT: or a0, a3, a0
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: ret
%e0 = extractelement <4 x i32> %v, i32 0
%e1 = extractelement <4 x i32> %v, i32 1
Expand Down
144 changes: 72 additions & 72 deletions llvm/test/CodeGen/RISCV/rv32zbb.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -683,9 +683,9 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind {
; RV32I-LABEL: ctpop_v2i64:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: lw a4, 0(a1)
; RV32I-NEXT: lw a2, 8(a1)
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: srli a5, a3, 1
; RV32I-NEXT: lui a6, 349525
; RV32I-NEXT: addi a6, a6, 1365
Expand All @@ -707,37 +707,37 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind {
; RV32I-NEXT: slli t0, a3, 16
; RV32I-NEXT: add a3, a3, t0
; RV32I-NEXT: srli a3, a3, 24
; RV32I-NEXT: srli t0, a1, 1
; RV32I-NEXT: srli t0, a4, 1
; RV32I-NEXT: and t0, t0, a6
; RV32I-NEXT: sub a1, a1, t0
; RV32I-NEXT: and t0, a1, a5
; RV32I-NEXT: sub a4, a4, t0
; RV32I-NEXT: and t0, a4, a5
; RV32I-NEXT: srli a4, a4, 2
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: add a4, t0, a4
; RV32I-NEXT: srli t0, a4, 4
; RV32I-NEXT: add a4, a4, t0
; RV32I-NEXT: and a4, a4, a7
; RV32I-NEXT: slli t0, a4, 8
; RV32I-NEXT: add a4, a4, t0
; RV32I-NEXT: slli t0, a4, 16
; RV32I-NEXT: add a4, a4, t0
; RV32I-NEXT: srli a4, a4, 24
; RV32I-NEXT: add a3, a4, a3
; RV32I-NEXT: srli a4, a1, 1
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: sub a1, a1, a4
; RV32I-NEXT: and a4, a1, a5
; RV32I-NEXT: srli a1, a1, 2
; RV32I-NEXT: and a1, a1, a5
; RV32I-NEXT: add a1, t0, a1
; RV32I-NEXT: srli t0, a1, 4
; RV32I-NEXT: add a1, a1, t0
; RV32I-NEXT: add a1, a4, a1
; RV32I-NEXT: srli a4, a1, 4
; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: and a1, a1, a7
; RV32I-NEXT: slli t0, a1, 8
; RV32I-NEXT: add a1, a1, t0
; RV32I-NEXT: slli t0, a1, 16
; RV32I-NEXT: add a1, a1, t0
; RV32I-NEXT: slli a4, a1, 8
; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: slli a4, a1, 16
; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: srli a1, a1, 24
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: srli a3, a4, 1
; RV32I-NEXT: and a3, a3, a6
; RV32I-NEXT: sub a4, a4, a3
; RV32I-NEXT: and a3, a4, a5
; RV32I-NEXT: srli a4, a4, 2
; RV32I-NEXT: and a4, a4, a5
; RV32I-NEXT: add a3, a3, a4
; RV32I-NEXT: srli a4, a3, 4
; RV32I-NEXT: add a3, a3, a4
; RV32I-NEXT: and a3, a3, a7
; RV32I-NEXT: slli a4, a3, 8
; RV32I-NEXT: add a3, a3, a4
; RV32I-NEXT: slli a4, a3, 16
; RV32I-NEXT: add a3, a3, a4
; RV32I-NEXT: srli a3, a3, 24
; RV32I-NEXT: srli a4, a2, 1
; RV32I-NEXT: and a4, a4, a6
; RV32I-NEXT: sub a2, a2, a4
Expand All @@ -753,11 +753,11 @@ define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind {
; RV32I-NEXT: slli a4, a2, 16
; RV32I-NEXT: add a2, a2, a4
; RV32I-NEXT: srli a2, a2, 24
; RV32I-NEXT: add a2, a2, a3
; RV32I-NEXT: add a1, a2, a1
; RV32I-NEXT: sw zero, 12(a0)
; RV32I-NEXT: sw zero, 4(a0)
; RV32I-NEXT: sw a2, 8(a0)
; RV32I-NEXT: sw a1, 0(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a3, 0(a0)
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: ctpop_v2i64:
Expand Down Expand Up @@ -785,21 +785,21 @@ define <2 x i1> @ctpop_v2i64_ult_two(<2 x i64> %a) nounwind {
; RV32I-LABEL: ctpop_v2i64_ult_two:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: lw a2, 12(a0)
; RV32I-NEXT: lw a2, 4(a0)
; RV32I-NEXT: lw a3, 8(a0)
; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: addi a4, a1, -1
; RV32I-NEXT: and a4, a1, a4
; RV32I-NEXT: lw a4, 12(a0)
; RV32I-NEXT: addi a0, a1, -1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: sub a1, a0, a1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: addi a1, a3, -1
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: sub a3, a2, a3
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: sub a2, a4, a2
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: ret
Expand Down Expand Up @@ -828,21 +828,21 @@ define <2 x i1> @ctpop_v2i64_ugt_one(<2 x i64> %a) nounwind {
; RV32I-LABEL: ctpop_v2i64_ugt_one:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a1, 0(a0)
; RV32I-NEXT: lw a2, 12(a0)
; RV32I-NEXT: lw a2, 4(a0)
; RV32I-NEXT: lw a3, 8(a0)
; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: addi a4, a1, -1
; RV32I-NEXT: and a4, a1, a4
; RV32I-NEXT: lw a4, 12(a0)
; RV32I-NEXT: addi a0, a1, -1
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: seqz a1, a1
; RV32I-NEXT: sub a1, a0, a1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: or a0, a4, a0
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: addi a1, a3, -1
; RV32I-NEXT: and a1, a3, a1
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: sub a3, a2, a3
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: seqz a2, a3
; RV32I-NEXT: sub a2, a4, a2
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: ret
Expand Down Expand Up @@ -873,15 +873,15 @@ define <2 x i1> @ctpop_v2i64_eq_one(<2 x i64> %a) nounwind {
; RV32I-LABEL: ctpop_v2i64_eq_one:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lw a2, 12(a0)
; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: beqz a0, .LBB22_3
; RV32I-NEXT: lw a0, 0(a0)
; RV32I-NEXT: lw a3, 4(a1)
; RV32I-NEXT: lw a2, 12(a1)
; RV32I-NEXT: beqz a3, .LBB22_3
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: sub a3, a0, a3
; RV32I-NEXT: xor a0, a0, a3
; RV32I-NEXT: sltu a0, a3, a0
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: sub a0, a3, a0
; RV32I-NEXT: xor a3, a3, a0
; RV32I-NEXT: sltu a0, a0, a3
; RV32I-NEXT: lw a1, 8(a1)
; RV32I-NEXT: bnez a2, .LBB22_4
; RV32I-NEXT: .LBB22_2:
Expand All @@ -890,9 +890,9 @@ define <2 x i1> @ctpop_v2i64_eq_one(<2 x i64> %a) nounwind {
; RV32I-NEXT: sltu a1, a2, a1
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB22_3:
; RV32I-NEXT: addi a0, a3, -1
; RV32I-NEXT: xor a3, a3, a0
; RV32I-NEXT: sltu a0, a0, a3
; RV32I-NEXT: addi a3, a0, -1
; RV32I-NEXT: xor a0, a0, a3
; RV32I-NEXT: sltu a0, a3, a0
; RV32I-NEXT: lw a1, 8(a1)
; RV32I-NEXT: beqz a2, .LBB22_2
; RV32I-NEXT: .LBB22_4:
Expand Down Expand Up @@ -927,20 +927,20 @@ define <2 x i1> @ctpop_v2i64_eq_one(<2 x i64> %a) nounwind {
define <2 x i1> @ctpop_v2i64_ne_one(<2 x i64> %a) nounwind {
; RV32I-LABEL: ctpop_v2i64_ne_one:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 0(a0)
; RV32I-NEXT: lw a3, 4(a0)
; RV32I-NEXT: lw a1, 12(a0)
; RV32I-NEXT: lw a2, 4(a0)
; RV32I-NEXT: lw a3, 0(a0)
; RV32I-NEXT: beqz a2, .LBB23_2
; RV32I-NEXT: beqz a3, .LBB23_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: seqz a3, a3
; RV32I-NEXT: sub a3, a2, a3
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: sltu a2, a3, a2
; RV32I-NEXT: j .LBB23_3
; RV32I-NEXT: .LBB23_2:
; RV32I-NEXT: addi a2, a3, -1
; RV32I-NEXT: seqz a2, a2
; RV32I-NEXT: sub a2, a3, a2
; RV32I-NEXT: xor a3, a3, a2
; RV32I-NEXT: sltu a2, a2, a3
; RV32I-NEXT: j .LBB23_3
; RV32I-NEXT: .LBB23_2:
; RV32I-NEXT: addi a3, a2, -1
; RV32I-NEXT: xor a2, a2, a3
; RV32I-NEXT: sltu a2, a3, a2
; RV32I-NEXT: .LBB23_3:
; RV32I-NEXT: lw a3, 8(a0)
; RV32I-NEXT: xori a0, a2, 1
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -177,12 +177,12 @@ define i8 @test13(ptr %0, i64 %1) {
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: subw a2, a2, a1
; RV64I-NEXT: add a2, a0, a2
; RV64I-NEXT: lbu a2, 0(a2)
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: subw a3, a3, a1
; RV64I-NEXT: add a0, a0, a3
; RV64I-NEXT: lbu a1, 0(a2)
; RV64I-NEXT: lbu a0, 0(a0)
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
%3 = mul i64 %1, -4294967296
%4 = add i64 %3, 4294967296 ; 1 << 32
Expand Down
64 changes: 32 additions & 32 deletions llvm/test/CodeGen/RISCV/rvv/expand-no-v.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,49 +8,49 @@ declare i32 @llvm.vp.reduce.add.v4i32(i32, <4 x i32>, <4 x i1>, i32)
define i32 @vpreduce_add_v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) {
; RV32-LABEL: vpreduce_add_v4i32:
; RV32: # %bb.0:
; RV32-NEXT: lw a4, 4(a1)
; RV32-NEXT: lw a5, 12(a1)
; RV32-NEXT: lw a4, 0(a1)
; RV32-NEXT: lw a5, 4(a1)
; RV32-NEXT: lw a6, 8(a1)
; RV32-NEXT: lw a1, 0(a1)
; RV32-NEXT: lw a1, 12(a1)
; RV32-NEXT: lw a7, 0(a2)
; RV32-NEXT: lw t0, 8(a2)
; RV32-NEXT: lw t1, 12(a2)
; RV32-NEXT: lw a2, 4(a2)
; RV32-NEXT: lw t0, 4(a2)
; RV32-NEXT: lw t1, 8(a2)
; RV32-NEXT: lw a2, 12(a2)
; RV32-NEXT: snez t2, a3
; RV32-NEXT: sltiu t3, a3, 3
; RV32-NEXT: xori t3, t3, 1
; RV32-NEXT: sltiu t4, a3, 4
; RV32-NEXT: xori t4, t4, 1
; RV32-NEXT: sltiu a3, a3, 2
; RV32-NEXT: xori a3, a3, 1
; RV32-NEXT: and a2, a3, a2
; RV32-NEXT: and a3, t4, t1
; RV32-NEXT: and t0, t3, t0
; RV32-NEXT: and a3, a3, t0
; RV32-NEXT: and a2, t4, a2
; RV32-NEXT: and t0, t3, t1
; RV32-NEXT: and a7, t2, a7
; RV32-NEXT: neg a7, a7
; RV32-NEXT: and a1, a7, a1
; RV32-NEXT: and a4, a7, a4
; RV32-NEXT: neg a7, t0
; RV32-NEXT: and a6, a7, a6
; RV32-NEXT: neg a3, a3
; RV32-NEXT: and a3, a3, a5
; RV32-NEXT: neg a2, a2
; RV32-NEXT: and a2, a2, a4
; RV32-NEXT: add a2, a2, a3
; RV32-NEXT: add a1, a1, a6
; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: and a1, a2, a1
; RV32-NEXT: neg a2, a3
; RV32-NEXT: and a2, a2, a5
; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: add a4, a4, a6
; RV32-NEXT: add a1, a4, a1
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: ret
;
; RV64-LABEL: vpreduce_add_v4i32:
; RV64: # %bb.0:
; RV64-NEXT: lw a4, 8(a1)
; RV64-NEXT: lw a5, 24(a1)
; RV64-NEXT: lw a4, 0(a1)
; RV64-NEXT: lw a5, 8(a1)
; RV64-NEXT: lw a6, 16(a1)
; RV64-NEXT: lw a1, 0(a1)
; RV64-NEXT: lw a1, 24(a1)
; RV64-NEXT: ld a7, 0(a2)
; RV64-NEXT: ld t0, 16(a2)
; RV64-NEXT: ld t1, 24(a2)
; RV64-NEXT: ld a2, 8(a2)
; RV64-NEXT: ld t0, 8(a2)
; RV64-NEXT: ld t1, 16(a2)
; RV64-NEXT: ld a2, 24(a2)
; RV64-NEXT: sext.w a3, a3
; RV64-NEXT: snez t2, a3
; RV64-NEXT: sltiu t3, a3, 3
Expand All @@ -59,21 +59,21 @@ define i32 @vpreduce_add_v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl) {
; RV64-NEXT: xori t4, t4, 1
; RV64-NEXT: sltiu a3, a3, 2
; RV64-NEXT: xori a3, a3, 1
; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: and a3, t4, t1
; RV64-NEXT: and t0, t3, t0
; RV64-NEXT: and a3, a3, t0
; RV64-NEXT: and a2, t4, a2
; RV64-NEXT: and t0, t3, t1
; RV64-NEXT: and a7, t2, a7
; RV64-NEXT: negw a7, a7
; RV64-NEXT: and a1, a7, a1
; RV64-NEXT: and a4, a7, a4
; RV64-NEXT: negw a7, t0
; RV64-NEXT: and a6, a7, a6
; RV64-NEXT: negw a3, a3
; RV64-NEXT: and a3, a3, a5
; RV64-NEXT: negw a2, a2
; RV64-NEXT: and a2, a2, a4
; RV64-NEXT: add a2, a2, a3
; RV64-NEXT: add a1, a1, a6
; RV64-NEXT: add a1, a1, a2
; RV64-NEXT: and a1, a2, a1
; RV64-NEXT: negw a2, a3
; RV64-NEXT: and a2, a2, a5
; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a4, a4, a6
; RV64-NEXT: add a1, a4, a1
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.add.v4i32(i32 %s, <4 x i32> %v, <4 x i1> %m, i32 %evl)
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vector-i8-index-cornercase.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -121,13 +121,13 @@ define <512 x i8> @two_source(<512 x i8> %a, <512 x i8> %b) {
; CHECK-NEXT: lbu a3, 985(sp)
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
; CHECK-NEXT: vslideup.vx v8, v24, a2
; CHECK-NEXT: lbu a1, 1012(sp)
; CHECK-NEXT: vmv.s.x v24, a3
; CHECK-NEXT: li a1, 478
; CHECK-NEXT: li a2, 477
; CHECK-NEXT: lbu a3, 1012(sp)
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
; CHECK-NEXT: vslideup.vx v8, v24, a2
; CHECK-NEXT: vmv.s.x v24, a3
; CHECK-NEXT: li a2, 478
; CHECK-NEXT: li a3, 477
; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma
; CHECK-NEXT: vslideup.vx v8, v24, a3
; CHECK-NEXT: vmv.s.x v24, a1
; CHECK-NEXT: li a1, 501
; CHECK-NEXT: li a2, 500
; CHECK-NEXT: vsetvli zero, a1, e8, m8, tu, ma
Expand Down
50 changes: 25 additions & 25 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,38 +26,38 @@ define void @add_v4i32(ptr %x, ptr %y) {
define void @add_v2i64(ptr %x, ptr %y) {
; RV32-LABEL: add_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: lw a2, 8(a0)
; RV32-NEXT: lw a3, 12(a0)
; RV32-NEXT: lw a2, 0(a1)
; RV32-NEXT: lw a3, 4(a1)
; RV32-NEXT: lw a4, 0(a0)
; RV32-NEXT: lw a5, 4(a0)
; RV32-NEXT: lw a6, 4(a1)
; RV32-NEXT: lw a7, 0(a1)
; RV32-NEXT: lw a6, 8(a0)
; RV32-NEXT: lw a7, 12(a0)
; RV32-NEXT: lw t0, 8(a1)
; RV32-NEXT: lw a1, 12(a1)
; RV32-NEXT: add a5, a5, a6
; RV32-NEXT: add a7, a4, a7
; RV32-NEXT: sltu a4, a7, a4
; RV32-NEXT: add a4, a5, a4
; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: add t0, a2, t0
; RV32-NEXT: sltu a2, t0, a2
; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: add a3, a5, a3
; RV32-NEXT: add a2, a4, a2
; RV32-NEXT: sltu a4, a2, a4
; RV32-NEXT: add a3, a3, a4
; RV32-NEXT: add a1, a7, a1
; RV32-NEXT: add t0, a6, t0
; RV32-NEXT: sltu a4, t0, a6
; RV32-NEXT: add a1, a1, a4
; RV32-NEXT: sw t0, 8(a0)
; RV32-NEXT: sw a7, 0(a0)
; RV32-NEXT: sw a2, 0(a0)
; RV32-NEXT: sw a1, 12(a0)
; RV32-NEXT: sw a4, 4(a0)
; RV32-NEXT: sw a3, 4(a0)
; RV32-NEXT: ret
;
; RV64-LABEL: add_v2i64:
; RV64: # %bb.0:
; RV64-NEXT: ld a2, 8(a0)
; RV64-NEXT: ld a3, 0(a0)
; RV64-NEXT: ld a2, 0(a0)
; RV64-NEXT: ld a3, 8(a0)
; RV64-NEXT: ld a4, 0(a1)
; RV64-NEXT: ld a1, 8(a1)
; RV64-NEXT: add a3, a3, a4
; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a2, a2, a4
; RV64-NEXT: add a1, a3, a1
; RV64-NEXT: sd a1, 8(a0)
; RV64-NEXT: sd a3, 0(a0)
; RV64-NEXT: sd a2, 0(a0)
; RV64-NEXT: ret
%a = load <2 x i64>, ptr %x
%b = load <2 x i64>, ptr %y
Expand Down Expand Up @@ -134,14 +134,14 @@ define void @fadd_v4f32(ptr %x, ptr %y) {
define void @fadd_v2f64(ptr %x, ptr %y) {
; CHECK-LABEL: fadd_v2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: fld fa5, 8(a0)
; CHECK-NEXT: fld fa4, 0(a0)
; CHECK-NEXT: fld fa5, 0(a0)
; CHECK-NEXT: fld fa4, 8(a0)
; CHECK-NEXT: fld fa3, 0(a1)
; CHECK-NEXT: fld fa2, 8(a1)
; CHECK-NEXT: fadd.d fa4, fa4, fa3
; CHECK-NEXT: fadd.d fa5, fa5, fa2
; CHECK-NEXT: fsd fa5, 8(a0)
; CHECK-NEXT: fsd fa4, 0(a0)
; CHECK-NEXT: fadd.d fa5, fa5, fa3
; CHECK-NEXT: fadd.d fa4, fa4, fa2
; CHECK-NEXT: fsd fa4, 8(a0)
; CHECK-NEXT: fsd fa5, 0(a0)
; CHECK-NEXT: ret
%a = load <2 x double>, ptr %x
%b = load <2 x double>, ptr %y
Expand Down
942 changes: 471 additions & 471 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
View file

Large diffs are not rendered by default.

36 changes: 18 additions & 18 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access-zve32x.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,25 +7,25 @@
define <4 x i1> @load_large_vector(ptr %p) {
; ZVE32X-LABEL: load_large_vector:
; ZVE32X: # %bb.0:
; ZVE32X-NEXT: ld a1, 80(a0)
; ZVE32X-NEXT: ld a2, 72(a0)
; ZVE32X-NEXT: ld a3, 56(a0)
; ZVE32X-NEXT: ld a1, 0(a0)
; ZVE32X-NEXT: ld a2, 8(a0)
; ZVE32X-NEXT: ld a3, 24(a0)
; ZVE32X-NEXT: ld a4, 32(a0)
; ZVE32X-NEXT: ld a5, 24(a0)
; ZVE32X-NEXT: ld a6, 48(a0)
; ZVE32X-NEXT: ld a7, 8(a0)
; ZVE32X-NEXT: ld a0, 0(a0)
; ZVE32X-NEXT: xor a4, a5, a4
; ZVE32X-NEXT: snez a4, a4
; ZVE32X-NEXT: ld a5, 48(a0)
; ZVE32X-NEXT: ld a6, 56(a0)
; ZVE32X-NEXT: ld a7, 72(a0)
; ZVE32X-NEXT: ld a0, 80(a0)
; ZVE32X-NEXT: xor a3, a3, a4
; ZVE32X-NEXT: snez a3, a3
; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; ZVE32X-NEXT: vmv.s.x v8, a4
; ZVE32X-NEXT: vmv.s.x v8, a3
; ZVE32X-NEXT: vand.vi v8, v8, 1
; ZVE32X-NEXT: vmsne.vi v0, v8, 0
; ZVE32X-NEXT: vmv.s.x v9, zero
; ZVE32X-NEXT: vmerge.vim v8, v9, 1, v0
; ZVE32X-NEXT: xor a0, a0, a7
; ZVE32X-NEXT: snez a0, a0
; ZVE32X-NEXT: vmv.s.x v10, a0
; ZVE32X-NEXT: xor a1, a1, a2
; ZVE32X-NEXT: snez a1, a1
; ZVE32X-NEXT: vmv.s.x v10, a1
; ZVE32X-NEXT: vand.vi v10, v10, 1
; ZVE32X-NEXT: vmsne.vi v0, v10, 0
; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
Expand All @@ -35,9 +35,9 @@ define <4 x i1> @load_large_vector(ptr %p) {
; ZVE32X-NEXT: vslideup.vi v11, v8, 1
; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVE32X-NEXT: vmsne.vi v0, v11, 0
; ZVE32X-NEXT: xor a0, a6, a3
; ZVE32X-NEXT: snez a0, a0
; ZVE32X-NEXT: vmv.s.x v8, a0
; ZVE32X-NEXT: xor a1, a5, a6
; ZVE32X-NEXT: snez a1, a1
; ZVE32X-NEXT: vmv.s.x v8, a1
; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; ZVE32X-NEXT: vand.vi v8, v8, 1
; ZVE32X-NEXT: vmsne.vi v8, v8, 0
Expand All @@ -50,8 +50,8 @@ define <4 x i1> @load_large_vector(ptr %p) {
; ZVE32X-NEXT: vslideup.vi v11, v8, 2
; ZVE32X-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; ZVE32X-NEXT: vmsne.vi v0, v11, 0
; ZVE32X-NEXT: xor a1, a2, a1
; ZVE32X-NEXT: snez a0, a1
; ZVE32X-NEXT: xor a0, a7, a0
; ZVE32X-NEXT: snez a0, a0
; ZVE32X-NEXT: vmv.s.x v8, a0
; ZVE32X-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; ZVE32X-NEXT: vand.vi v8, v8, 1
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-lrint.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -777,24 +777,24 @@ define <8 x iXLen> @lrint_v8f64(<8 x double> %x) {
; RV32-NEXT: vfmv.f.s fa5, v10
; RV32-NEXT: fcvt.w.d a2, fa5
; RV32-NEXT: vslidedown.vi v8, v8, 3
; RV32-NEXT: vfmv.f.s fa5, v8
; RV32-NEXT: fcvt.w.d a3, fa5
; RV32-NEXT: fld fa5, 32(sp)
; RV32-NEXT: vfmv.f.s fa4, v8
; RV32-NEXT: fld fa3, 40(sp)
; RV32-NEXT: fcvt.w.d a3, fa4
; RV32-NEXT: fld fa4, 40(sp)
; RV32-NEXT: fld fa3, 48(sp)
; RV32-NEXT: fld fa2, 56(sp)
; RV32-NEXT: fcvt.w.d a4, fa5
; RV32-NEXT: fcvt.w.d a5, fa4
; RV32-NEXT: fcvt.w.d a6, fa3
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v8, a1
; RV32-NEXT: fcvt.w.d a1, fa3
; RV32-NEXT: fld fa5, 48(sp)
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: vslide1down.vx v8, v8, a3
; RV32-NEXT: fcvt.w.d a0, fa5
; RV32-NEXT: fld fa5, 56(sp)
; RV32-NEXT: vslide1down.vx v8, v8, a4
; RV32-NEXT: vslide1down.vx v8, v8, a1
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: fcvt.w.d a0, fa5
; RV32-NEXT: vslide1down.vx v8, v8, a5
; RV32-NEXT: vslide1down.vx v8, v8, a6
; RV32-NEXT: fcvt.w.d a0, fa2
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: addi sp, s0, -128
; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -827,24 +827,24 @@ define <8 x iXLen> @lrint_v8f64(<8 x double> %x) {
; RV64-i32-NEXT: vfmv.f.s fa5, v10
; RV64-i32-NEXT: fcvt.l.d a2, fa5
; RV64-i32-NEXT: vslidedown.vi v8, v8, 3
; RV64-i32-NEXT: vfmv.f.s fa5, v8
; RV64-i32-NEXT: fcvt.l.d a3, fa5
; RV64-i32-NEXT: fld fa5, 32(sp)
; RV64-i32-NEXT: vfmv.f.s fa4, v8
; RV64-i32-NEXT: fld fa3, 40(sp)
; RV64-i32-NEXT: fcvt.l.d a3, fa4
; RV64-i32-NEXT: fld fa4, 40(sp)
; RV64-i32-NEXT: fld fa3, 48(sp)
; RV64-i32-NEXT: fld fa2, 56(sp)
; RV64-i32-NEXT: fcvt.l.d a4, fa5
; RV64-i32-NEXT: fcvt.l.d a5, fa4
; RV64-i32-NEXT: fcvt.l.d a6, fa3
; RV64-i32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV64-i32-NEXT: vmv.v.x v8, a1
; RV64-i32-NEXT: fcvt.l.d a1, fa3
; RV64-i32-NEXT: fld fa5, 48(sp)
; RV64-i32-NEXT: vslide1down.vx v8, v8, a0
; RV64-i32-NEXT: vslide1down.vx v8, v8, a2
; RV64-i32-NEXT: vslide1down.vx v8, v8, a3
; RV64-i32-NEXT: fcvt.l.d a0, fa5
; RV64-i32-NEXT: fld fa5, 56(sp)
; RV64-i32-NEXT: vslide1down.vx v8, v8, a4
; RV64-i32-NEXT: vslide1down.vx v8, v8, a1
; RV64-i32-NEXT: vslide1down.vx v8, v8, a0
; RV64-i32-NEXT: fcvt.l.d a0, fa5
; RV64-i32-NEXT: vslide1down.vx v8, v8, a5
; RV64-i32-NEXT: vslide1down.vx v8, v8, a6
; RV64-i32-NEXT: fcvt.l.d a0, fa2
; RV64-i32-NEXT: vslide1down.vx v8, v8, a0
; RV64-i32-NEXT: addi sp, s0, -128
; RV64-i32-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
Expand Down
1,692 changes: 846 additions & 846 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
View file

Large diffs are not rendered by default.

1,598 changes: 799 additions & 799 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
View file

Large diffs are not rendered by default.

16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -736,18 +736,18 @@ define void @scatter_of_pointers(ptr noalias nocapture %arg, ptr noalias nocaptu
; ZVE32F-NEXT: li a5, 40
; ZVE32F-NEXT: .LBB13_1: # %bb2
; ZVE32F-NEXT: # =>This Inner Loop Header: Depth=1
; ZVE32F-NEXT: ld a6, 8(a1)
; ZVE32F-NEXT: ld a7, 0(a1)
; ZVE32F-NEXT: ld t0, 24(a1)
; ZVE32F-NEXT: ld t1, 16(a1)
; ZVE32F-NEXT: ld a6, 0(a1)
; ZVE32F-NEXT: ld a7, 8(a1)
; ZVE32F-NEXT: ld t0, 16(a1)
; ZVE32F-NEXT: ld t1, 24(a1)
; ZVE32F-NEXT: mul t2, a4, a5
; ZVE32F-NEXT: add t2, a0, t2
; ZVE32F-NEXT: mul t3, a2, a5
; ZVE32F-NEXT: add t3, a0, t3
; ZVE32F-NEXT: sd a7, 0(t3)
; ZVE32F-NEXT: sd a6, 0(t2)
; ZVE32F-NEXT: sd t1, 80(t3)
; ZVE32F-NEXT: sd t0, 80(t2)
; ZVE32F-NEXT: sd a6, 0(t3)
; ZVE32F-NEXT: sd a7, 0(t2)
; ZVE32F-NEXT: sd t0, 80(t3)
; ZVE32F-NEXT: sd t1, 80(t2)
; ZVE32F-NEXT: addi a2, a2, 4
; ZVE32F-NEXT: addi a1, a1, 32
; ZVE32F-NEXT: addi a4, a4, 4
Expand Down
272 changes: 136 additions & 136 deletions llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
View file

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/scmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -87,10 +87,10 @@ define i8 @scmp.8.128(i128 %x, i128 %y) nounwind {
; RV32I-LABEL: scmp.8.128:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 4(a1)
; RV32I-NEXT: lw a3, 4(a0)
; RV32I-NEXT: lw a4, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: lw a6, 12(a0)
; RV32I-NEXT: lw a3, 4(a0)
; RV32I-NEXT: lw a7, 8(a0)
; RV32I-NEXT: beq a6, a5, .LBB4_2
; RV32I-NEXT: # %bb.1:
Expand Down
110 changes: 55 additions & 55 deletions llvm/test/CodeGen/RISCV/shifts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -171,21 +171,21 @@ define i128 @lshr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: add a1, a3, a1
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: srl a3, a3, a2
; RV32I-NEXT: slli a5, a4, 1
; RV32I-NEXT: andi a6, a2, 31
; RV32I-NEXT: xori a6, a6, 31
; RV32I-NEXT: lw a7, 8(a1)
; RV32I-NEXT: sll a5, a5, a6
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: slli a6, a4, 1
; RV32I-NEXT: andi a7, a2, 31
; RV32I-NEXT: xori a7, a7, 31
; RV32I-NEXT: sll a6, a6, a7
; RV32I-NEXT: or a3, a3, a6
; RV32I-NEXT: srl a4, a4, a2
; RV32I-NEXT: slli a5, a7, 1
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: sll a5, a5, a6
; RV32I-NEXT: or a4, a4, a5
; RV32I-NEXT: srl a5, a7, a2
; RV32I-NEXT: slli a7, a1, 1
; RV32I-NEXT: sll a6, a7, a6
; RV32I-NEXT: slli a6, a5, 1
; RV32I-NEXT: sll a6, a6, a7
; RV32I-NEXT: or a4, a4, a6
; RV32I-NEXT: srl a5, a5, a2
; RV32I-NEXT: slli a6, a1, 1
; RV32I-NEXT: sll a6, a6, a7
; RV32I-NEXT: or a5, a5, a6
; RV32I-NEXT: srl a1, a1, a2
; RV32I-NEXT: sw a1, 12(a0)
Expand Down Expand Up @@ -221,41 +221,41 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-LABEL: ashr128:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a4, 12(a1)
; RV32I-NEXT: lw a5, 0(a1)
; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw a3, 12(a1)
; RV32I-NEXT: lw a4, 8(a1)
; RV32I-NEXT: lw a5, 4(a1)
; RV32I-NEXT: lw a1, 0(a1)
; RV32I-NEXT: sw a3, 12(sp)
; RV32I-NEXT: sw a4, 8(sp)
; RV32I-NEXT: sw a5, 4(sp)
; RV32I-NEXT: sw a1, 0(sp)
; RV32I-NEXT: srai a3, a3, 31
; RV32I-NEXT: sw a3, 28(sp)
; RV32I-NEXT: sw a3, 24(sp)
; RV32I-NEXT: sw a3, 20(sp)
; RV32I-NEXT: sw a3, 16(sp)
; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: sw a3, 8(sp)
; RV32I-NEXT: sw a1, 4(sp)
; RV32I-NEXT: sw a5, 0(sp)
; RV32I-NEXT: srai a4, a4, 31
; RV32I-NEXT: sw a4, 28(sp)
; RV32I-NEXT: sw a4, 24(sp)
; RV32I-NEXT: sw a4, 20(sp)
; RV32I-NEXT: sw a4, 16(sp)
; RV32I-NEXT: srli a1, a2, 3
; RV32I-NEXT: andi a1, a1, 12
; RV32I-NEXT: mv a3, sp
; RV32I-NEXT: add a1, a3, a1
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: lw a4, 4(a1)
; RV32I-NEXT: lw a5, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: srl a3, a3, a2
; RV32I-NEXT: slli a5, a4, 1
; RV32I-NEXT: andi a6, a2, 31
; RV32I-NEXT: xori a6, a6, 31
; RV32I-NEXT: lw a7, 8(a1)
; RV32I-NEXT: sll a5, a5, a6
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: slli a6, a4, 1
; RV32I-NEXT: andi a7, a2, 31
; RV32I-NEXT: xori a7, a7, 31
; RV32I-NEXT: sll a6, a6, a7
; RV32I-NEXT: or a3, a3, a6
; RV32I-NEXT: srl a4, a4, a2
; RV32I-NEXT: slli a5, a7, 1
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: sll a5, a5, a6
; RV32I-NEXT: or a4, a4, a5
; RV32I-NEXT: srl a5, a7, a2
; RV32I-NEXT: slli a7, a1, 1
; RV32I-NEXT: sll a6, a7, a6
; RV32I-NEXT: slli a6, a5, 1
; RV32I-NEXT: sll a6, a6, a7
; RV32I-NEXT: or a4, a4, a6
; RV32I-NEXT: srl a5, a5, a2
; RV32I-NEXT: slli a6, a1, 1
; RV32I-NEXT: sll a6, a6, a7
; RV32I-NEXT: or a5, a5, a6
; RV32I-NEXT: sra a1, a1, a2
; RV32I-NEXT: sw a1, 12(a0)
Expand Down Expand Up @@ -310,27 +310,27 @@ define i128 @shl128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sub a3, a3, a1
; RV32I-NEXT: lw a1, 4(a3)
; RV32I-NEXT: lw a4, 0(a3)
; RV32I-NEXT: sll a5, a1, a2
; RV32I-NEXT: srli a6, a4, 1
; RV32I-NEXT: andi a7, a2, 31
; RV32I-NEXT: lw t0, 8(a3)
; RV32I-NEXT: xori a7, a7, 31
; RV32I-NEXT: srl a6, a6, a7
; RV32I-NEXT: or a5, a5, a6
; RV32I-NEXT: sll a6, t0, a2
; RV32I-NEXT: lw a5, 8(a3)
; RV32I-NEXT: lw a3, 12(a3)
; RV32I-NEXT: sll a6, a1, a2
; RV32I-NEXT: srli a7, a4, 1
; RV32I-NEXT: andi t0, a2, 31
; RV32I-NEXT: xori t0, t0, 31
; RV32I-NEXT: srl a7, a7, t0
; RV32I-NEXT: or a6, a6, a7
; RV32I-NEXT: sll a7, a5, a2
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: srl a1, a1, a7
; RV32I-NEXT: or a1, a6, a1
; RV32I-NEXT: srl a1, a1, t0
; RV32I-NEXT: or a1, a7, a1
; RV32I-NEXT: sll a3, a3, a2
; RV32I-NEXT: srli a6, t0, 1
; RV32I-NEXT: srl a6, a6, a7
; RV32I-NEXT: or a3, a3, a6
; RV32I-NEXT: srli a5, a5, 1
; RV32I-NEXT: srl a5, a5, t0
; RV32I-NEXT: or a3, a3, a5
; RV32I-NEXT: sll a2, a4, a2
; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: sw a3, 12(a0)
; RV32I-NEXT: sw a1, 8(a0)
; RV32I-NEXT: sw a5, 4(a0)
; RV32I-NEXT: sw a6, 4(a0)
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -394,10 +394,10 @@ define i64 @fshr64_minsize(i64 %a, i64 %b) minsize nounwind {
define i128 @fshr128_minsize(i128 %a, i128 %b) minsize nounwind {
; RV32I-LABEL: fshr128_minsize:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw t2, 0(a1)
; RV32I-NEXT: lw a2, 0(a2)
; RV32I-NEXT: lw t2, 0(a1)
; RV32I-NEXT: lw a7, 4(a1)
; RV32I-NEXT: lw a3, 8(a1)
; RV32I-NEXT: lw a1, 12(a1)
; RV32I-NEXT: andi t1, a2, 64
; RV32I-NEXT: mv t0, a7
Expand Down
136 changes: 68 additions & 68 deletions llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -308,22 +308,22 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV32-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32-NEXT: mv s0, a0
; RV32-NEXT: lbu a0, 12(a0)
; RV32-NEXT: lw a1, 8(s0)
; RV32-NEXT: slli a2, a0, 30
; RV32-NEXT: lw a3, 4(s0)
; RV32-NEXT: srli s1, a1, 2
; RV32-NEXT: or s1, s1, a2
; RV32-NEXT: slli a2, a1, 31
; RV32-NEXT: srli a4, a3, 1
; RV32-NEXT: or s2, a4, a2
; RV32-NEXT: srli a0, a0, 2
; RV32-NEXT: slli a0, a0, 31
; RV32-NEXT: srai s3, a0, 31
; RV32-NEXT: srli a1, a1, 1
; RV32-NEXT: lbu a1, 12(a0)
; RV32-NEXT: lw a2, 8(a0)
; RV32-NEXT: lw a3, 4(a0)
; RV32-NEXT: lw a0, 0(a0)
; RV32-NEXT: slli a4, a1, 30
; RV32-NEXT: srli s1, a2, 2
; RV32-NEXT: or s1, s1, a4
; RV32-NEXT: slli a4, a2, 31
; RV32-NEXT: srli a5, a3, 1
; RV32-NEXT: or s2, a5, a4
; RV32-NEXT: srli a1, a1, 2
; RV32-NEXT: slli a1, a1, 31
; RV32-NEXT: lw a0, 0(s0)
; RV32-NEXT: srai s4, a1, 31
; RV32-NEXT: srai s3, a1, 31
; RV32-NEXT: srli a2, a2, 1
; RV32-NEXT: slli a2, a2, 31
; RV32-NEXT: srai s4, a2, 31
; RV32-NEXT: slli a1, a3, 31
; RV32-NEXT: srai a1, a1, 31
; RV32-NEXT: li a2, 6
Expand Down Expand Up @@ -389,8 +389,8 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV64-NEXT: mv s0, a0
; RV64-NEXT: lbu a0, 12(a0)
; RV64-NEXT: lwu a1, 8(s0)
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: ld a2, 0(s0)
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: or a0, a1, a0
; RV64-NEXT: slli a0, a0, 29
; RV64-NEXT: srai s1, a0, 31
Expand Down Expand Up @@ -460,22 +460,22 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV32M-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32M-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32M-NEXT: mv s0, a0
; RV32M-NEXT: lbu a0, 12(a0)
; RV32M-NEXT: lw a1, 8(s0)
; RV32M-NEXT: slli a2, a0, 30
; RV32M-NEXT: lw a3, 4(s0)
; RV32M-NEXT: srli s1, a1, 2
; RV32M-NEXT: or s1, s1, a2
; RV32M-NEXT: slli a2, a1, 31
; RV32M-NEXT: srli a4, a3, 1
; RV32M-NEXT: or s2, a4, a2
; RV32M-NEXT: srli a0, a0, 2
; RV32M-NEXT: slli a0, a0, 31
; RV32M-NEXT: srai s3, a0, 31
; RV32M-NEXT: srli a1, a1, 1
; RV32M-NEXT: lbu a1, 12(a0)
; RV32M-NEXT: lw a2, 8(a0)
; RV32M-NEXT: lw a3, 4(a0)
; RV32M-NEXT: lw a0, 0(a0)
; RV32M-NEXT: slli a4, a1, 30
; RV32M-NEXT: srli s1, a2, 2
; RV32M-NEXT: or s1, s1, a4
; RV32M-NEXT: slli a4, a2, 31
; RV32M-NEXT: srli a5, a3, 1
; RV32M-NEXT: or s2, a5, a4
; RV32M-NEXT: srli a1, a1, 2
; RV32M-NEXT: slli a1, a1, 31
; RV32M-NEXT: lw a0, 0(s0)
; RV32M-NEXT: srai s4, a1, 31
; RV32M-NEXT: srai s3, a1, 31
; RV32M-NEXT: srli a2, a2, 1
; RV32M-NEXT: slli a2, a2, 31
; RV32M-NEXT: srai s4, a2, 31
; RV32M-NEXT: slli a1, a3, 31
; RV32M-NEXT: srai a1, a1, 31
; RV32M-NEXT: li a2, 6
Expand Down Expand Up @@ -534,34 +534,34 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV64M: # %bb.0:
; RV64M-NEXT: ld a1, 0(a0)
; RV64M-NEXT: lwu a2, 8(a0)
; RV64M-NEXT: srli a3, a1, 2
; RV64M-NEXT: lbu a4, 12(a0)
; RV64M-NEXT: lbu a3, 12(a0)
; RV64M-NEXT: srli a4, a1, 2
; RV64M-NEXT: slli a5, a2, 62
; RV64M-NEXT: or a3, a5, a3
; RV64M-NEXT: srai a3, a3, 31
; RV64M-NEXT: slli a4, a4, 32
; RV64M-NEXT: or a2, a2, a4
; RV64M-NEXT: or a4, a5, a4
; RV64M-NEXT: srai a4, a4, 31
; RV64M-NEXT: slli a3, a3, 32
; RV64M-NEXT: or a2, a2, a3
; RV64M-NEXT: slli a2, a2, 29
; RV64M-NEXT: lui a4, %hi(.LCPI3_0)
; RV64M-NEXT: ld a4, %lo(.LCPI3_0)(a4)
; RV64M-NEXT: lui a3, %hi(.LCPI3_0)
; RV64M-NEXT: ld a3, %lo(.LCPI3_0)(a3)
; RV64M-NEXT: srai a2, a2, 31
; RV64M-NEXT: slli a1, a1, 31
; RV64M-NEXT: srai a1, a1, 31
; RV64M-NEXT: mulh a4, a2, a4
; RV64M-NEXT: srli a5, a4, 63
; RV64M-NEXT: srai a4, a4, 1
; RV64M-NEXT: add a4, a4, a5
; RV64M-NEXT: mulh a3, a2, a3
; RV64M-NEXT: srli a5, a3, 63
; RV64M-NEXT: srai a3, a3, 1
; RV64M-NEXT: add a3, a3, a5
; RV64M-NEXT: lui a5, %hi(.LCPI3_1)
; RV64M-NEXT: ld a5, %lo(.LCPI3_1)(a5)
; RV64M-NEXT: add a2, a2, a4
; RV64M-NEXT: slli a4, a4, 2
; RV64M-NEXT: add a2, a2, a4
; RV64M-NEXT: mulh a4, a3, a5
; RV64M-NEXT: srli a5, a4, 63
; RV64M-NEXT: srai a4, a4, 1
; RV64M-NEXT: add a4, a4, a5
; RV64M-NEXT: slli a5, a4, 3
; RV64M-NEXT: add a3, a3, a4
; RV64M-NEXT: add a2, a2, a3
; RV64M-NEXT: slli a3, a3, 2
; RV64M-NEXT: add a2, a2, a3
; RV64M-NEXT: mulh a3, a4, a5
; RV64M-NEXT: srli a5, a3, 63
; RV64M-NEXT: srai a3, a3, 1
; RV64M-NEXT: add a3, a3, a5
; RV64M-NEXT: slli a5, a3, 3
; RV64M-NEXT: add a3, a4, a3
; RV64M-NEXT: sub a3, a3, a5
; RV64M-NEXT: addi a3, a3, -1
; RV64M-NEXT: seqz a3, a3
Expand Down Expand Up @@ -610,22 +610,22 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV32MV-NEXT: slli a1, a1, 1
; RV32MV-NEXT: sub sp, sp, a1
; RV32MV-NEXT: mv s0, a0
; RV32MV-NEXT: lbu a0, 12(a0)
; RV32MV-NEXT: lw a1, 8(s0)
; RV32MV-NEXT: slli a2, a0, 30
; RV32MV-NEXT: lw a3, 4(s0)
; RV32MV-NEXT: srli s1, a1, 2
; RV32MV-NEXT: or s1, s1, a2
; RV32MV-NEXT: slli a2, a1, 31
; RV32MV-NEXT: srli a4, a3, 1
; RV32MV-NEXT: or s2, a4, a2
; RV32MV-NEXT: srli a0, a0, 2
; RV32MV-NEXT: slli a0, a0, 31
; RV32MV-NEXT: srai s3, a0, 31
; RV32MV-NEXT: srli a1, a1, 1
; RV32MV-NEXT: lbu a1, 12(a0)
; RV32MV-NEXT: lw a2, 8(a0)
; RV32MV-NEXT: lw a3, 4(a0)
; RV32MV-NEXT: lw a0, 0(a0)
; RV32MV-NEXT: slli a4, a1, 30
; RV32MV-NEXT: srli s1, a2, 2
; RV32MV-NEXT: or s1, s1, a4
; RV32MV-NEXT: slli a4, a2, 31
; RV32MV-NEXT: srli a5, a3, 1
; RV32MV-NEXT: or s2, a5, a4
; RV32MV-NEXT: srli a1, a1, 2
; RV32MV-NEXT: slli a1, a1, 31
; RV32MV-NEXT: srai s4, a1, 31
; RV32MV-NEXT: lw a0, 0(s0)
; RV32MV-NEXT: srai s3, a1, 31
; RV32MV-NEXT: srli a2, a2, 1
; RV32MV-NEXT: slli a2, a2, 31
; RV32MV-NEXT: srai s4, a2, 31
; RV32MV-NEXT: slli a1, a3, 31
; RV32MV-NEXT: srai a1, a1, 31
; RV32MV-NEXT: li a2, 1
Expand Down Expand Up @@ -728,8 +728,8 @@ define void @test_srem_vec(ptr %X) nounwind {
; RV64MV: # %bb.0:
; RV64MV-NEXT: lbu a1, 12(a0)
; RV64MV-NEXT: lwu a2, 8(a0)
; RV64MV-NEXT: slli a1, a1, 32
; RV64MV-NEXT: ld a3, 0(a0)
; RV64MV-NEXT: slli a1, a1, 32
; RV64MV-NEXT: or a1, a2, a1
; RV64MV-NEXT: slli a1, a1, 29
; RV64MV-NEXT: srai a1, a1, 31
Expand Down
638 changes: 320 additions & 318 deletions llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
View file

Large diffs are not rendered by default.

32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/stack-store-check.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -143,15 +143,15 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: addi a2, sp, 392
; CHECK-NEXT: sw a3, 392(sp)
; CHECK-NEXT: call __subtf3
; CHECK-NEXT: lw a0, 424(sp)
; CHECK-NEXT: lw a0, 432(sp)
; CHECK-NEXT: lw a1, 436(sp)
; CHECK-NEXT: lw a2, 432(sp)
; CHECK-NEXT: lw a2, 424(sp)
; CHECK-NEXT: lw a3, 428(sp)
; CHECK-NEXT: lui a4, %hi(X)
; CHECK-NEXT: sw a1, %lo(X+12)(a4)
; CHECK-NEXT: sw a2, %lo(X+8)(a4)
; CHECK-NEXT: sw a0, %lo(X+8)(a4)
; CHECK-NEXT: sw a3, %lo(X+4)(a4)
; CHECK-NEXT: sw a0, %lo(X)(a4)
; CHECK-NEXT: sw a2, %lo(X)(a4)
; CHECK-NEXT: lw s8, 4(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw s8, 212(sp)
; CHECK-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -190,15 +190,15 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: addi a2, sp, 344
; CHECK-NEXT: sw s9, 360(sp)
; CHECK-NEXT: call __multf3
; CHECK-NEXT: lw a0, 376(sp)
; CHECK-NEXT: lw a0, 384(sp)
; CHECK-NEXT: lw a1, 388(sp)
; CHECK-NEXT: lw a2, 384(sp)
; CHECK-NEXT: lw a2, 376(sp)
; CHECK-NEXT: lw a3, 380(sp)
; CHECK-NEXT: lui a4, %hi(S)
; CHECK-NEXT: sw a1, %lo(S+12)(a4)
; CHECK-NEXT: sw a2, %lo(S+8)(a4)
; CHECK-NEXT: sw a0, %lo(S+8)(a4)
; CHECK-NEXT: sw a3, %lo(S+4)(a4)
; CHECK-NEXT: sw a0, %lo(S)(a4)
; CHECK-NEXT: sw a2, %lo(S)(a4)
; CHECK-NEXT: lw a0, 48(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a0, 260(sp)
; CHECK-NEXT: sw s10, 256(sp)
Expand All @@ -216,15 +216,15 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: lw a3, 44(sp) # 4-byte Folded Reload
; CHECK-NEXT: sw a3, 264(sp)
; CHECK-NEXT: call __subtf3
; CHECK-NEXT: lw a0, 280(sp)
; CHECK-NEXT: lw a0, 288(sp)
; CHECK-NEXT: lw a1, 292(sp)
; CHECK-NEXT: lw a2, 288(sp)
; CHECK-NEXT: lw a2, 280(sp)
; CHECK-NEXT: lw a3, 284(sp)
; CHECK-NEXT: lui a4, %hi(T)
; CHECK-NEXT: sw a1, %lo(T+12)(a4)
; CHECK-NEXT: sw a2, %lo(T+8)(a4)
; CHECK-NEXT: sw a0, %lo(T+8)(a4)
; CHECK-NEXT: sw a3, %lo(T+4)(a4)
; CHECK-NEXT: sw a0, %lo(T)(a4)
; CHECK-NEXT: sw a2, %lo(T)(a4)
; CHECK-NEXT: sw zero, 164(sp)
; CHECK-NEXT: sw zero, 160(sp)
; CHECK-NEXT: sw zero, 156(sp)
Expand All @@ -238,15 +238,15 @@ define void @main() local_unnamed_addr nounwind {
; CHECK-NEXT: addi a2, sp, 152
; CHECK-NEXT: sw s1, 168(sp)
; CHECK-NEXT: call __addtf3
; CHECK-NEXT: lw a0, 184(sp)
; CHECK-NEXT: lw a0, 192(sp)
; CHECK-NEXT: lw a1, 196(sp)
; CHECK-NEXT: lw a2, 192(sp)
; CHECK-NEXT: lw a2, 184(sp)
; CHECK-NEXT: lw a3, 188(sp)
; CHECK-NEXT: lui a4, %hi(Y)
; CHECK-NEXT: sw a1, %lo(Y+12)(a4)
; CHECK-NEXT: sw a2, %lo(Y+8)(a4)
; CHECK-NEXT: sw a0, %lo(Y+8)(a4)
; CHECK-NEXT: sw a3, %lo(Y+4)(a4)
; CHECK-NEXT: sw a0, %lo(Y)(a4)
; CHECK-NEXT: sw a2, %lo(Y)(a4)
; CHECK-NEXT: sw zero, 116(sp)
; CHECK-NEXT: sw zero, 112(sp)
; CHECK-NEXT: sw zero, 108(sp)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/ucmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -87,10 +87,10 @@ define i8 @ucmp.8.128(i128 %x, i128 %y) nounwind {
; RV32I-LABEL: ucmp.8.128:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a2, 4(a1)
; RV32I-NEXT: lw a3, 4(a0)
; RV32I-NEXT: lw a4, 8(a1)
; RV32I-NEXT: lw a5, 12(a1)
; RV32I-NEXT: lw a6, 12(a0)
; RV32I-NEXT: lw a3, 4(a0)
; RV32I-NEXT: lw a7, 8(a0)
; RV32I-NEXT: beq a6, a5, .LBB4_2
; RV32I-NEXT: # %bb.1:
Expand Down
96 changes: 48 additions & 48 deletions llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,47 +10,47 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {
; RISCV32-NEXT: sw s2, 20(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s3, 16(sp) # 4-byte Folded Spill
; RISCV32-NEXT: sw s4, 12(sp) # 4-byte Folded Spill
; RISCV32-NEXT: lw a3, 12(a1)
; RISCV32-NEXT: lw a7, 12(a2)
; RISCV32-NEXT: lw a6, 8(a1)
; RISCV32-NEXT: lw a4, 0(a2)
; RISCV32-NEXT: lw a5, 0(a1)
; RISCV32-NEXT: lw a3, 0(a1)
; RISCV32-NEXT: lw t2, 4(a1)
; RISCV32-NEXT: lw t0, 8(a2)
; RISCV32-NEXT: lw a2, 4(a2)
; RISCV32-NEXT: mulhu a1, a5, a4
; RISCV32-NEXT: mul t1, t2, a4
; RISCV32-NEXT: add a1, t1, a1
; RISCV32-NEXT: sltu t1, a1, t1
; RISCV32-NEXT: mulhu t3, t2, a4
; RISCV32-NEXT: lw a4, 8(a1)
; RISCV32-NEXT: lw a5, 12(a1)
; RISCV32-NEXT: lw a1, 0(a2)
; RISCV32-NEXT: lw t0, 4(a2)
; RISCV32-NEXT: lw a6, 8(a2)
; RISCV32-NEXT: lw a7, 12(a2)
; RISCV32-NEXT: mulhu a2, a3, a1
; RISCV32-NEXT: mul t1, t2, a1
; RISCV32-NEXT: add a2, t1, a2
; RISCV32-NEXT: sltu t1, a2, t1
; RISCV32-NEXT: mulhu t3, t2, a1
; RISCV32-NEXT: add t4, t3, t1
; RISCV32-NEXT: mul t1, a5, a2
; RISCV32-NEXT: add a1, t1, a1
; RISCV32-NEXT: sltu t1, a1, t1
; RISCV32-NEXT: mulhu t3, a5, a2
; RISCV32-NEXT: mul t1, a3, t0
; RISCV32-NEXT: add a2, t1, a2
; RISCV32-NEXT: sltu t1, a2, t1
; RISCV32-NEXT: mulhu t3, a3, t0
; RISCV32-NEXT: add t1, t3, t1
; RISCV32-NEXT: add t5, t4, t1
; RISCV32-NEXT: mul t6, t2, a2
; RISCV32-NEXT: mul t6, t2, t0
; RISCV32-NEXT: add s0, t6, t5
; RISCV32-NEXT: mul t1, t0, a5
; RISCV32-NEXT: mul s3, a6, a4
; RISCV32-NEXT: mul t1, a6, a3
; RISCV32-NEXT: mul s3, a4, a1
; RISCV32-NEXT: add s4, s3, t1
; RISCV32-NEXT: add t1, s0, s4
; RISCV32-NEXT: sltu t3, t1, s0
; RISCV32-NEXT: sltu s0, s0, t6
; RISCV32-NEXT: sltu t4, t5, t4
; RISCV32-NEXT: mulhu t5, t2, a2
; RISCV32-NEXT: mulhu t5, t2, t0
; RISCV32-NEXT: add t4, t5, t4
; RISCV32-NEXT: add s0, t4, s0
; RISCV32-NEXT: mul t4, t2, t0
; RISCV32-NEXT: mul t5, a7, a5
; RISCV32-NEXT: mul t4, t2, a6
; RISCV32-NEXT: mul t5, a7, a3
; RISCV32-NEXT: add t4, t5, t4
; RISCV32-NEXT: mulhu s1, t0, a5
; RISCV32-NEXT: mulhu s1, a6, a3
; RISCV32-NEXT: add s2, s1, t4
; RISCV32-NEXT: mul t4, a2, a6
; RISCV32-NEXT: mul t5, a3, a4
; RISCV32-NEXT: mul t4, t0, a4
; RISCV32-NEXT: mul t5, a5, a1
; RISCV32-NEXT: add t4, t5, t4
; RISCV32-NEXT: mulhu t5, a6, a4
; RISCV32-NEXT: mulhu t5, a4, a1
; RISCV32-NEXT: add t6, t5, t4
; RISCV32-NEXT: add t4, t6, s2
; RISCV32-NEXT: sltu s3, s4, s3
Expand All @@ -65,39 +65,39 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) #0 {
; RISCV32-NEXT: snez s1, t2
; RISCV32-NEXT: snez s2, a7
; RISCV32-NEXT: and s1, s2, s1
; RISCV32-NEXT: mulhu s2, a7, a5
; RISCV32-NEXT: mulhu s2, a7, a3
; RISCV32-NEXT: snez s2, s2
; RISCV32-NEXT: or s1, s1, s2
; RISCV32-NEXT: mulhu t2, t2, t0
; RISCV32-NEXT: mulhu t2, t2, a6
; RISCV32-NEXT: snez t2, t2
; RISCV32-NEXT: or t2, s1, t2
; RISCV32-NEXT: or t2, t2, s0
; RISCV32-NEXT: sltu t5, t6, t5
; RISCV32-NEXT: snez t6, a2
; RISCV32-NEXT: snez s0, a3
; RISCV32-NEXT: snez t6, t0
; RISCV32-NEXT: snez s0, a5
; RISCV32-NEXT: and t6, s0, t6
; RISCV32-NEXT: mulhu s0, a3, a4
; RISCV32-NEXT: mulhu s0, a5, a1
; RISCV32-NEXT: snez s0, s0
; RISCV32-NEXT: or t6, t6, s0
; RISCV32-NEXT: mulhu a2, a2, a6
; RISCV32-NEXT: snez a2, a2
; RISCV32-NEXT: or a2, t6, a2
; RISCV32-NEXT: or a2, a2, t5
; RISCV32-NEXT: or a7, t0, a7
; RISCV32-NEXT: snez a7, a7
; RISCV32-NEXT: or a3, a6, a3
; RISCV32-NEXT: snez a3, a3
; RISCV32-NEXT: and a3, a3, a7
; RISCV32-NEXT: or a2, a3, a2
; RISCV32-NEXT: or a2, a2, t2
; RISCV32-NEXT: or a2, a2, t3
; RISCV32-NEXT: mul a3, a5, a4
; RISCV32-NEXT: andi a2, a2, 1
; RISCV32-NEXT: sw a3, 0(a0)
; RISCV32-NEXT: sw a1, 4(a0)
; RISCV32-NEXT: mulhu t0, t0, a4
; RISCV32-NEXT: snez t0, t0
; RISCV32-NEXT: or t0, t6, t0
; RISCV32-NEXT: or t0, t0, t5
; RISCV32-NEXT: or a6, a6, a7
; RISCV32-NEXT: snez a6, a6
; RISCV32-NEXT: or a4, a4, a5
; RISCV32-NEXT: snez a4, a4
; RISCV32-NEXT: and a4, a4, a6
; RISCV32-NEXT: or a4, a4, t0
; RISCV32-NEXT: or a4, a4, t2
; RISCV32-NEXT: or a4, a4, t3
; RISCV32-NEXT: mul a1, a3, a1
; RISCV32-NEXT: andi a4, a4, 1
; RISCV32-NEXT: sw a1, 0(a0)
; RISCV32-NEXT: sw a2, 4(a0)
; RISCV32-NEXT: sw t1, 8(a0)
; RISCV32-NEXT: sw t4, 12(a0)
; RISCV32-NEXT: sb a2, 16(a0)
; RISCV32-NEXT: sb a4, 16(a0)
; RISCV32-NEXT: lw s0, 28(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s1, 24(sp) # 4-byte Folded Reload
; RISCV32-NEXT: lw s2, 20(sp) # 4-byte Folded Reload
Expand Down
72 changes: 36 additions & 36 deletions llvm/test/CodeGen/RISCV/unaligned-load-store.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -54,19 +54,19 @@ define i24 @load_i24(ptr %p) {
;
; RV32IZBKB-LABEL: load_i24:
; RV32IZBKB: # %bb.0:
; RV32IZBKB-NEXT: lbu a1, 1(a0)
; RV32IZBKB-NEXT: lbu a2, 0(a0)
; RV32IZBKB-NEXT: lbu a1, 0(a0)
; RV32IZBKB-NEXT: lbu a2, 1(a0)
; RV32IZBKB-NEXT: lbu a0, 2(a0)
; RV32IZBKB-NEXT: packh a1, a2, a1
; RV32IZBKB-NEXT: packh a1, a1, a2
; RV32IZBKB-NEXT: pack a0, a1, a0
; RV32IZBKB-NEXT: ret
;
; RV64IZBKB-LABEL: load_i24:
; RV64IZBKB: # %bb.0:
; RV64IZBKB-NEXT: lbu a1, 1(a0)
; RV64IZBKB-NEXT: lbu a2, 0(a0)
; RV64IZBKB-NEXT: lbu a1, 0(a0)
; RV64IZBKB-NEXT: lbu a2, 1(a0)
; RV64IZBKB-NEXT: lbu a0, 2(a0)
; RV64IZBKB-NEXT: packh a1, a2, a1
; RV64IZBKB-NEXT: packh a1, a1, a2
; RV64IZBKB-NEXT: slli a0, a0, 16
; RV64IZBKB-NEXT: or a0, a1, a0
; RV64IZBKB-NEXT: ret
Expand Down Expand Up @@ -99,11 +99,11 @@ define i32 @load_i32(ptr %p) {
;
; SLOWZBKB-LABEL: load_i32:
; SLOWZBKB: # %bb.0:
; SLOWZBKB-NEXT: lbu a1, 1(a0)
; SLOWZBKB-NEXT: lbu a2, 0(a0)
; SLOWZBKB-NEXT: lbu a1, 0(a0)
; SLOWZBKB-NEXT: lbu a2, 1(a0)
; SLOWZBKB-NEXT: lbu a3, 2(a0)
; SLOWZBKB-NEXT: lbu a0, 3(a0)
; SLOWZBKB-NEXT: packh a1, a2, a1
; SLOWZBKB-NEXT: packh a1, a1, a2
; SLOWZBKB-NEXT: slli a3, a3, 16
; SLOWZBKB-NEXT: slli a0, a0, 24
; SLOWZBKB-NEXT: or a0, a0, a3
Expand All @@ -130,17 +130,17 @@ define i64 @load_i64(ptr %p) {
; RV32I-NEXT: slli a3, a3, 16
; RV32I-NEXT: slli a4, a4, 24
; RV32I-NEXT: or a2, a4, a3
; RV32I-NEXT: or a2, a2, a1
; RV32I-NEXT: lbu a1, 5(a0)
; RV32I-NEXT: lbu a3, 4(a0)
; RV32I-NEXT: lbu a4, 6(a0)
; RV32I-NEXT: lbu a4, 5(a0)
; RV32I-NEXT: or a2, a2, a1
; RV32I-NEXT: lbu a1, 6(a0)
; RV32I-NEXT: lbu a0, 7(a0)
; RV32I-NEXT: slli a1, a1, 8
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: slli a4, a4, 16
; RV32I-NEXT: slli a4, a4, 8
; RV32I-NEXT: or a3, a4, a3
; RV32I-NEXT: slli a1, a1, 16
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: or a1, a0, a3
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
Expand All @@ -155,37 +155,37 @@ define i64 @load_i64(ptr %p) {
; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: slli a4, a4, 24
; RV64I-NEXT: or a3, a4, a3
; RV64I-NEXT: lbu a2, 4(a0)
; RV64I-NEXT: lbu a4, 5(a0)
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: lbu a2, 5(a0)
; RV64I-NEXT: lbu a3, 4(a0)
; RV64I-NEXT: lbu a4, 6(a0)
; RV64I-NEXT: lbu a3, 6(a0)
; RV64I-NEXT: lbu a0, 7(a0)
; RV64I-NEXT: slli a2, a2, 8
; RV64I-NEXT: or a2, a2, a3
; RV64I-NEXT: slli a4, a4, 16
; RV64I-NEXT: slli a4, a4, 8
; RV64I-NEXT: or a2, a4, a2
; RV64I-NEXT: slli a3, a3, 16
; RV64I-NEXT: slli a0, a0, 24
; RV64I-NEXT: or a0, a0, a4
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
; RV32IZBKB-LABEL: load_i64:
; RV32IZBKB: # %bb.0:
; RV32IZBKB-NEXT: lbu a1, 1(a0)
; RV32IZBKB-NEXT: lbu a2, 0(a0)
; RV32IZBKB-NEXT: lbu a1, 0(a0)
; RV32IZBKB-NEXT: lbu a2, 1(a0)
; RV32IZBKB-NEXT: lbu a3, 2(a0)
; RV32IZBKB-NEXT: lbu a4, 3(a0)
; RV32IZBKB-NEXT: packh a1, a2, a1
; RV32IZBKB-NEXT: packh a1, a1, a2
; RV32IZBKB-NEXT: slli a3, a3, 16
; RV32IZBKB-NEXT: slli a4, a4, 24
; RV32IZBKB-NEXT: or a3, a4, a3
; RV32IZBKB-NEXT: lbu a2, 5(a0)
; RV32IZBKB-NEXT: lbu a4, 4(a0)
; RV32IZBKB-NEXT: lbu a2, 4(a0)
; RV32IZBKB-NEXT: lbu a4, 5(a0)
; RV32IZBKB-NEXT: lbu a5, 6(a0)
; RV32IZBKB-NEXT: lbu a6, 7(a0)
; RV32IZBKB-NEXT: or a0, a3, a1
; RV32IZBKB-NEXT: packh a1, a4, a2
; RV32IZBKB-NEXT: packh a1, a2, a4
; RV32IZBKB-NEXT: slli a5, a5, 16
; RV32IZBKB-NEXT: slli a6, a6, 24
; RV32IZBKB-NEXT: or a2, a6, a5
Expand All @@ -194,20 +194,20 @@ define i64 @load_i64(ptr %p) {
;
; RV64IZBKB-LABEL: load_i64:
; RV64IZBKB: # %bb.0:
; RV64IZBKB-NEXT: lbu a1, 5(a0)
; RV64IZBKB-NEXT: lbu a2, 4(a0)
; RV64IZBKB-NEXT: lbu a1, 4(a0)
; RV64IZBKB-NEXT: lbu a2, 5(a0)
; RV64IZBKB-NEXT: lbu a3, 6(a0)
; RV64IZBKB-NEXT: lbu a4, 7(a0)
; RV64IZBKB-NEXT: packh a1, a2, a1
; RV64IZBKB-NEXT: packh a1, a1, a2
; RV64IZBKB-NEXT: slli a3, a3, 16
; RV64IZBKB-NEXT: slli a4, a4, 24
; RV64IZBKB-NEXT: or a3, a4, a3
; RV64IZBKB-NEXT: lbu a2, 1(a0)
; RV64IZBKB-NEXT: lbu a4, 0(a0)
; RV64IZBKB-NEXT: lbu a2, 0(a0)
; RV64IZBKB-NEXT: lbu a4, 1(a0)
; RV64IZBKB-NEXT: lbu a5, 2(a0)
; RV64IZBKB-NEXT: lbu a0, 3(a0)
; RV64IZBKB-NEXT: or a1, a3, a1
; RV64IZBKB-NEXT: packh a2, a4, a2
; RV64IZBKB-NEXT: packh a2, a2, a4
; RV64IZBKB-NEXT: slli a5, a5, 16
; RV64IZBKB-NEXT: slli a0, a0, 24
; RV64IZBKB-NEXT: or a0, a0, a5
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -522,10 +522,10 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV32MV-LABEL: test_urem_vec:
; RV32MV: # %bb.0:
; RV32MV-NEXT: lw a1, 0(a0)
; RV32MV-NEXT: andi a2, a1, 2047
; RV32MV-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32MV-NEXT: vmv.v.x v8, a2
; RV32MV-NEXT: lbu a2, 4(a0)
; RV32MV-NEXT: andi a3, a1, 2047
; RV32MV-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32MV-NEXT: vmv.v.x v8, a3
; RV32MV-NEXT: slli a3, a1, 10
; RV32MV-NEXT: srli a3, a3, 21
; RV32MV-NEXT: vslide1down.vx v8, v8, a3
Expand Down
442 changes: 222 additions & 220 deletions llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
View file

Large diffs are not rendered by default.

50 changes: 25 additions & 25 deletions llvm/test/CodeGen/RISCV/vararg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -822,11 +822,11 @@ define i64 @va2(ptr %fmt, ...) nounwind {
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 20
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 27
; ILP32-ILP32F-FPELIM-NEXT: andi a0, a0, -8
; ILP32-ILP32F-FPELIM-NEXT: addi a1, sp, 35
; ILP32-ILP32F-FPELIM-NEXT: sw a1, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a1, 4(a0)
; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-FPELIM-NEXT: andi a1, a0, -8
; ILP32-ILP32F-FPELIM-NEXT: addi a0, sp, 35
; ILP32-ILP32F-FPELIM-NEXT: sw a0, 12(sp)
; ILP32-ILP32F-FPELIM-NEXT: lw a0, 0(a1)
; ILP32-ILP32F-FPELIM-NEXT: lw a1, 4(a1)
; ILP32-ILP32F-FPELIM-NEXT: addi sp, sp, 48
; ILP32-ILP32F-FPELIM-NEXT: ret
;
Expand All @@ -846,11 +846,11 @@ define i64 @va2(ptr %fmt, ...) nounwind {
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 4
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 11
; ILP32-ILP32F-WITHFP-NEXT: andi a0, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: addi a1, s0, 19
; ILP32-ILP32F-WITHFP-NEXT: sw a1, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a1, 4(a0)
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a0)
; ILP32-ILP32F-WITHFP-NEXT: andi a1, a0, -8
; ILP32-ILP32F-WITHFP-NEXT: addi a0, s0, 19
; ILP32-ILP32F-WITHFP-NEXT: sw a0, -12(s0)
; ILP32-ILP32F-WITHFP-NEXT: lw a0, 0(a1)
; ILP32-ILP32F-WITHFP-NEXT: lw a1, 4(a1)
; ILP32-ILP32F-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; ILP32-ILP32F-WITHFP-NEXT: addi sp, sp, 48
Expand All @@ -869,11 +869,11 @@ define i64 @va2(ptr %fmt, ...) nounwind {
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 20
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 27
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a0, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a1, sp, 35
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a1, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 4(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a0)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: andi a1, a0, -8
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi a0, sp, 35
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: sw a0, 12(sp)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a0, 0(a1)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: lw a1, 4(a1)
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: addi sp, sp, 48
; RV32D-ILP32-ILP32F-ILP32D-FPELIM-NEXT: ret
;
Expand All @@ -888,11 +888,11 @@ define i64 @va2(ptr %fmt, ...) nounwind {
; ILP32E-FPELIM-NEXT: addi a0, sp, 8
; ILP32E-FPELIM-NEXT: sw a0, 0(sp)
; ILP32E-FPELIM-NEXT: addi a0, sp, 15
; ILP32E-FPELIM-NEXT: andi a0, a0, -8
; ILP32E-FPELIM-NEXT: addi a1, sp, 23
; ILP32E-FPELIM-NEXT: sw a1, 0(sp)
; ILP32E-FPELIM-NEXT: lw a1, 4(a0)
; ILP32E-FPELIM-NEXT: lw a0, 0(a0)
; ILP32E-FPELIM-NEXT: andi a1, a0, -8
; ILP32E-FPELIM-NEXT: addi a0, sp, 23
; ILP32E-FPELIM-NEXT: sw a0, 0(sp)
; ILP32E-FPELIM-NEXT: lw a0, 0(a1)
; ILP32E-FPELIM-NEXT: lw a1, 4(a1)
; ILP32E-FPELIM-NEXT: addi sp, sp, 28
; ILP32E-FPELIM-NEXT: ret
;
Expand All @@ -910,11 +910,11 @@ define i64 @va2(ptr %fmt, ...) nounwind {
; ILP32E-WITHFP-NEXT: addi a0, s0, 4
; ILP32E-WITHFP-NEXT: sw a0, -12(s0)
; ILP32E-WITHFP-NEXT: addi a0, s0, 11
; ILP32E-WITHFP-NEXT: andi a0, a0, -8
; ILP32E-WITHFP-NEXT: addi a1, s0, 19
; ILP32E-WITHFP-NEXT: sw a1, -12(s0)
; ILP32E-WITHFP-NEXT: lw a1, 4(a0)
; ILP32E-WITHFP-NEXT: lw a0, 0(a0)
; ILP32E-WITHFP-NEXT: andi a1, a0, -8
; ILP32E-WITHFP-NEXT: addi a0, s0, 19
; ILP32E-WITHFP-NEXT: sw a0, -12(s0)
; ILP32E-WITHFP-NEXT: lw a0, 0(a1)
; ILP32E-WITHFP-NEXT: lw a1, 4(a1)
; ILP32E-WITHFP-NEXT: lw ra, 8(sp) # 4-byte Folded Reload
; ILP32E-WITHFP-NEXT: lw s0, 4(sp) # 4-byte Folded Reload
; ILP32E-WITHFP-NEXT: addi sp, sp, 36
Expand Down
4,424 changes: 2,212 additions & 2,212 deletions llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll
View file

Large diffs are not rendered by default.

2,118 changes: 1,059 additions & 1,059 deletions llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll
View file

Large diffs are not rendered by default.

14 changes: 7 additions & 7 deletions llvm/test/CodeGen/RISCV/xtheadmempair.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,14 +57,14 @@ define i64 @lwud(ptr %a) {
define i64 @ldd(ptr %a) {
; RV32XTHEADMEMPAIR-LABEL: ldd:
; RV32XTHEADMEMPAIR: # %bb.0:
; RV32XTHEADMEMPAIR-NEXT: lw a1, 32(a0)
; RV32XTHEADMEMPAIR-NEXT: lw a2, 36(a0)
; RV32XTHEADMEMPAIR-NEXT: lw a3, 44(a0)
; RV32XTHEADMEMPAIR-NEXT: lw a1, 44(a0)
; RV32XTHEADMEMPAIR-NEXT: lw a2, 32(a0)
; RV32XTHEADMEMPAIR-NEXT: lw a3, 36(a0)
; RV32XTHEADMEMPAIR-NEXT: lw a0, 40(a0)
; RV32XTHEADMEMPAIR-NEXT: add a2, a2, a3
; RV32XTHEADMEMPAIR-NEXT: add a0, a1, a0
; RV32XTHEADMEMPAIR-NEXT: sltu a1, a0, a1
; RV32XTHEADMEMPAIR-NEXT: add a1, a2, a1
; RV32XTHEADMEMPAIR-NEXT: add a1, a3, a1
; RV32XTHEADMEMPAIR-NEXT: add a0, a2, a0
; RV32XTHEADMEMPAIR-NEXT: sltu a2, a0, a2
; RV32XTHEADMEMPAIR-NEXT: add a1, a1, a2
; RV32XTHEADMEMPAIR-NEXT: ret
;
; RV64XTHEADMEMPAIR-LABEL: ldd:
Expand Down