4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/preserve.ll
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,7 @@ define void @masked_gather_v8i8(ptr %a, ptr %b) #0 {
; VBITS_GE_256-NEXT: zip2 v1.8b, v0.8b, v0.8b
; VBITS_GE_256-NEXT: zip1 v0.8b, v0.8b, v0.8b
; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x1, x8, lsl #3]
; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]
; VBITS_GE_256-NEXT: shl v1.4h, v1.4h, #8
; VBITS_GE_256-NEXT: shl v0.4h, v0.4h, #8
; VBITS_GE_256-NEXT: sshr v1.4h, v1.4h, #8
Expand All @@ -75,10 +76,9 @@ define void @masked_gather_v8i8(ptr %a, ptr %b) #0 {
; VBITS_GE_256-NEXT: sunpklo z1.d, z1.s
; VBITS_GE_256-NEXT: sunpklo z0.d, z0.s
; VBITS_GE_256-NEXT: cmpne p1.d, p0/z, z1.d, #0
; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1]
; VBITS_GE_256-NEXT: cmpne p0.d, p0/z, z0.d, #0
; VBITS_GE_256-NEXT: ld1b { z0.d }, p1/z, [z2.d]
; VBITS_GE_256-NEXT: ld1b { z1.d }, p0/z, [z1.d]
; VBITS_GE_256-NEXT: ld1b { z1.d }, p0/z, [z3.d]
; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s
; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s
; VBITS_GE_256-NEXT: uzp1 z0.h, z0.h, z0.h
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ body: |
; CHECK-LABEL: name: bic_i16_zero
; CHECK: liveins: $p0, $z0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit killed $p0, implicit $z0 {
; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit killed $p0, implicit $z0 {
; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_H $p0, $z0
; CHECK-NEXT: $z0 = LSL_ZPmI_H killed renamable $p0, internal $z0, 0
; CHECK-NEXT: $z0 = BIC_ZPmZ_H killed renamable $p0, internal killed $z0, internal killed renamable $z0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ body: |
; CHECK-LABEL: name: fmul_float_zero
; CHECK: liveins: $p0, $z0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit $p0, implicit $z0 {
; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit $p0, implicit $z0 {
; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0
; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0
; CHECK-NEXT: $z0 = FMUL_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ body: |
; CHECK-LABEL: name: fsub_s_zero
; CHECK: liveins: $p0, $z0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $z0_hi, implicit $p0, implicit $z0 {
; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit $p0, implicit $z0 {
; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0
; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0
; CHECK-NEXT: $z0 = FSUBR_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -14,22 +14,22 @@ define <8 x i8> @concat_v8i8(<4 x i8> %op1, <4 x i8> %op2) {
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
; CHECK-NEXT: mov z2.h, z1.h[3]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
; CHECK-NEXT: mov z2.h, z1.h[3]
; CHECK-NEXT: mov z3.h, z1.h[2]
; CHECK-NEXT: mov z1.h, z1.h[1]
; CHECK-NEXT: mov z4.h, z0.h[3]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [sp, #12]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strb w8, [sp, #8]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov z2.h, z0.h[2]
; CHECK-NEXT: mov z0.h, z0.h[1]
; CHECK-NEXT: strb w9, [sp, #8]
; CHECK-NEXT: fmov w9, s3
; CHECK-NEXT: strb w8, [sp, #15]
; CHECK-NEXT: fmov w8, s3
; CHECK-NEXT: strb w8, [sp, #14]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: strb w9, [sp, #14]
; CHECK-NEXT: strb w8, [sp, #13]
; CHECK-NEXT: fmov w8, s4
; CHECK-NEXT: strb w8, [sp, #11]
Expand Down
166 changes: 82 additions & 84 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -215,49 +215,48 @@ define void @fcvtzu_v16f16_v16i64(ptr %a, ptr %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #128
; CHECK-NEXT: .cfi_def_cfa_offset 128
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldp q0, q4, [x0]
; CHECK-NEXT: mov z1.h, z0.h[1]
; CHECK-NEXT: mov z2.h, z0.h[3]
; CHECK-NEXT: fcvtzu x8, h0
; CHECK-NEXT: mov z3.h, z0.h[2]
; CHECK-NEXT: fcvtzu x8, h0
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: mov z5.h, z4.h[3]
; CHECK-NEXT: fcvtzu x10, h4
; CHECK-NEXT: fcvtzu x9, h1
; CHECK-NEXT: fcvtzu x10, h2
; CHECK-NEXT: ldr q1, [x0, #16]
; CHECK-NEXT: fcvtzu x11, h3
; CHECK-NEXT: mov z2.h, z0.h[1]
; CHECK-NEXT: fcvtzu x11, h2
; CHECK-NEXT: fcvtzu x12, h3
; CHECK-NEXT: mov z1.h, z0.h[1]
; CHECK-NEXT: mov z3.h, z0.h[3]
; CHECK-NEXT: fcvtzu x12, h1
; CHECK-NEXT: stp x8, x9, [sp, #32]
; CHECK-NEXT: fcvtzu x8, h0
; CHECK-NEXT: fcvtzu x13, h0
; CHECK-NEXT: mov z0.h, z0.h[2]
; CHECK-NEXT: fcvtzu x9, h2
; CHECK-NEXT: stp x11, x10, [sp, #48]
; CHECK-NEXT: fcvtzu x10, h3
; CHECK-NEXT: mov z2.h, z1.h[1]
; CHECK-NEXT: mov z3.h, z1.h[3]
; CHECK-NEXT: fcvtzu x11, h0
; CHECK-NEXT: mov z0.h, z1.h[2]
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: stp x8, x9, [sp]
; CHECK-NEXT: fcvtzu x8, h2
; CHECK-NEXT: mov z2.h, z4.h[1]
; CHECK-NEXT: stp x8, x9, [sp, #32]
; CHECK-NEXT: fcvtzu x8, h1
; CHECK-NEXT: fcvtzu x9, h3
; CHECK-NEXT: mov z2.h, z1.h[1]
; CHECK-NEXT: stp x11, x10, [sp, #16]
; CHECK-NEXT: fcvtzu x10, h0
; CHECK-NEXT: mov z0.h, z1.h[3]
; CHECK-NEXT: fcvtzu x11, h1
; CHECK-NEXT: mov z1.h, z1.h[2]
; CHECK-NEXT: stp x12, x8, [sp, #96]
; CHECK-NEXT: stp x12, x11, [sp, #48]
; CHECK-NEXT: fcvtzu x11, h0
; CHECK-NEXT: mov z1.h, z4.h[2]
; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8
; CHECK-NEXT: fcvtzu x12, h2
; CHECK-NEXT: fcvtzu x8, h0
; CHECK-NEXT: ldp q3, q4, [sp]
; CHECK-NEXT: stp x10, x9, [sp, #112]
; CHECK-NEXT: stp x13, x8, [sp]
; CHECK-NEXT: fcvtzu x8, h5
; CHECK-NEXT: stp x11, x9, [sp, #16]
; CHECK-NEXT: fcvtzu x9, h1
; CHECK-NEXT: mov z0.h, z4.h[1]
; CHECK-NEXT: mov z1.h, z4.h[3]
; CHECK-NEXT: mov z2.h, z4.h[2]
; CHECK-NEXT: fcvtzu x11, h4
; CHECK-NEXT: stp x10, x12, [sp, #96]
; CHECK-NEXT: ldp q3, q4, [sp]
; CHECK-NEXT: fcvtzu x10, h0
; CHECK-NEXT: fcvtzu x12, h1
; CHECK-NEXT: stp x9, x8, [sp, #112]
; CHECK-NEXT: fcvtzu x8, h2
; CHECK-NEXT: ldp q0, q1, [sp, #32]
; CHECK-NEXT: stp x11, x12, [sp, #64]
; CHECK-NEXT: ldp q6, q7, [sp, #96]
; CHECK-NEXT: stp x9, x8, [sp, #80]
; CHECK-NEXT: stp x11, x10, [sp, #64]
; CHECK-NEXT: stp x8, x12, [sp, #80]
; CHECK-NEXT: ldp q5, q2, [sp, #64]
; CHECK-NEXT: stp q0, q1, [x1]
; CHECK-NEXT: stp q3, q4, [x1, #32]
Expand Down Expand Up @@ -498,13 +497,13 @@ define <4 x i16> @fcvtzu_v4f64_v4i16(ptr %a) {
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: mov z2.s, z0.s[1]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: mov z0.s, z1.s[1]
; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: strh w8, [sp, #12]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: strh w8, [sp, #8]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: strh w9, [sp, #8]
; CHECK-NEXT: strh w8, [sp, #14]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strh w8, [sp, #10]
Expand Down Expand Up @@ -571,33 +570,33 @@ define void @fcvtzu_v16f64_v16i16(ptr %a, ptr %b) {
; CHECK-NEXT: ldp q4, q5, [x0, #80]
; CHECK-NEXT: ldr q7, [x0, #64]
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s
; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov z16.s, z1.s[1]
; CHECK-NEXT: mov z1.s, z0.s[1]
; CHECK-NEXT: strh w8, [sp, #12]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov z0.s, z2.s[1]
; CHECK-NEXT: strh w8, [sp, #8]
; CHECK-NEXT: strh w8, [sp, #12]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov z2.s, z3.s[1]
; CHECK-NEXT: strh w8, [sp, #4]
; CHECK-NEXT: fmov w8, s3
; CHECK-NEXT: strh w9, [sp, #8]
; CHECK-NEXT: fmov w9, s3
; CHECK-NEXT: movprfx z3, z7
; CHECK-NEXT: fcvtzs z3.d, p0/m, z7.d
; CHECK-NEXT: strh w8, [sp]
; CHECK-NEXT: strh w8, [sp, #4]
; CHECK-NEXT: fmov w8, s16
; CHECK-NEXT: strh w9, [sp]
; CHECK-NEXT: strh w8, [sp, #14]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: uzp1 z1.s, z4.s, z4.s
Expand Down Expand Up @@ -966,49 +965,48 @@ define void @fcvtzs_v16f16_v16i64(ptr %a, ptr %b) {
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #128
; CHECK-NEXT: .cfi_def_cfa_offset 128
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldp q0, q4, [x0]
; CHECK-NEXT: mov z1.h, z0.h[1]
; CHECK-NEXT: mov z2.h, z0.h[3]
; CHECK-NEXT: fcvtzs x8, h0
; CHECK-NEXT: mov z3.h, z0.h[2]
; CHECK-NEXT: fcvtzs x8, h0
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: mov z5.h, z4.h[3]
; CHECK-NEXT: fcvtzs x10, h4
; CHECK-NEXT: fcvtzs x9, h1
; CHECK-NEXT: fcvtzs x10, h2
; CHECK-NEXT: ldr q1, [x0, #16]
; CHECK-NEXT: fcvtzs x11, h3
; CHECK-NEXT: mov z2.h, z0.h[1]
; CHECK-NEXT: fcvtzs x11, h2
; CHECK-NEXT: fcvtzs x12, h3
; CHECK-NEXT: mov z1.h, z0.h[1]
; CHECK-NEXT: mov z3.h, z0.h[3]
; CHECK-NEXT: fcvtzs x12, h1
; CHECK-NEXT: stp x8, x9, [sp, #32]
; CHECK-NEXT: fcvtzs x8, h0
; CHECK-NEXT: fcvtzs x13, h0
; CHECK-NEXT: mov z0.h, z0.h[2]
; CHECK-NEXT: fcvtzs x9, h2
; CHECK-NEXT: stp x11, x10, [sp, #48]
; CHECK-NEXT: fcvtzs x10, h3
; CHECK-NEXT: mov z2.h, z1.h[1]
; CHECK-NEXT: mov z3.h, z1.h[3]
; CHECK-NEXT: fcvtzs x11, h0
; CHECK-NEXT: mov z0.h, z1.h[2]
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: stp x8, x9, [sp]
; CHECK-NEXT: fcvtzs x8, h2
; CHECK-NEXT: mov z2.h, z4.h[1]
; CHECK-NEXT: stp x8, x9, [sp, #32]
; CHECK-NEXT: fcvtzs x8, h1
; CHECK-NEXT: fcvtzs x9, h3
; CHECK-NEXT: mov z2.h, z1.h[1]
; CHECK-NEXT: stp x11, x10, [sp, #16]
; CHECK-NEXT: fcvtzs x10, h0
; CHECK-NEXT: mov z0.h, z1.h[3]
; CHECK-NEXT: fcvtzs x11, h1
; CHECK-NEXT: mov z1.h, z1.h[2]
; CHECK-NEXT: stp x12, x8, [sp, #96]
; CHECK-NEXT: stp x12, x11, [sp, #48]
; CHECK-NEXT: fcvtzs x11, h0
; CHECK-NEXT: mov z1.h, z4.h[2]
; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8
; CHECK-NEXT: fcvtzs x12, h2
; CHECK-NEXT: fcvtzs x8, h0
; CHECK-NEXT: ldp q3, q4, [sp]
; CHECK-NEXT: stp x10, x9, [sp, #112]
; CHECK-NEXT: stp x13, x8, [sp]
; CHECK-NEXT: fcvtzs x8, h5
; CHECK-NEXT: stp x11, x9, [sp, #16]
; CHECK-NEXT: fcvtzs x9, h1
; CHECK-NEXT: mov z0.h, z4.h[1]
; CHECK-NEXT: mov z1.h, z4.h[3]
; CHECK-NEXT: mov z2.h, z4.h[2]
; CHECK-NEXT: fcvtzs x11, h4
; CHECK-NEXT: stp x10, x12, [sp, #96]
; CHECK-NEXT: ldp q3, q4, [sp]
; CHECK-NEXT: fcvtzs x10, h0
; CHECK-NEXT: fcvtzs x12, h1
; CHECK-NEXT: stp x9, x8, [sp, #112]
; CHECK-NEXT: fcvtzs x8, h2
; CHECK-NEXT: ldp q0, q1, [sp, #32]
; CHECK-NEXT: stp x11, x12, [sp, #64]
; CHECK-NEXT: ldp q6, q7, [sp, #96]
; CHECK-NEXT: stp x9, x8, [sp, #80]
; CHECK-NEXT: stp x11, x10, [sp, #64]
; CHECK-NEXT: stp x8, x12, [sp, #80]
; CHECK-NEXT: ldp q5, q2, [sp, #64]
; CHECK-NEXT: stp q0, q1, [x1]
; CHECK-NEXT: stp q3, q4, [x1, #32]
Expand Down Expand Up @@ -1251,13 +1249,13 @@ define <4 x i16> @fcvtzs_v4f64_v4i16(ptr %a) {
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: mov z2.s, z0.s[1]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: mov z0.s, z1.s[1]
; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: strh w8, [sp, #12]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: strh w8, [sp, #8]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: strh w9, [sp, #8]
; CHECK-NEXT: strh w8, [sp, #14]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strh w8, [sp, #10]
Expand Down Expand Up @@ -1324,33 +1322,33 @@ define void @fcvtzs_v16f64_v16i16(ptr %a, ptr %b) {
; CHECK-NEXT: ldp q4, q5, [x0, #80]
; CHECK-NEXT: ldr q7, [x0, #64]
; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d
; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT: fcvtzs z3.d, p0/m, z3.d
; CHECK-NEXT: fcvtzs z6.d, p0/m, z6.d
; CHECK-NEXT: fcvtzs z5.d, p0/m, z5.d
; CHECK-NEXT: fcvtzs z4.d, p0/m, z4.d
; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s
; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s
; CHECK-NEXT: uzp1 z3.s, z3.s, z3.s
; CHECK-NEXT: uzp1 z6.s, z6.s, z6.s
; CHECK-NEXT: uzp1 z5.s, z5.s, z5.s
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov z16.s, z1.s[1]
; CHECK-NEXT: mov z1.s, z0.s[1]
; CHECK-NEXT: strh w8, [sp, #12]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: mov z0.s, z2.s[1]
; CHECK-NEXT: strh w8, [sp, #8]
; CHECK-NEXT: strh w8, [sp, #12]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: mov z2.s, z3.s[1]
; CHECK-NEXT: strh w8, [sp, #4]
; CHECK-NEXT: fmov w8, s3
; CHECK-NEXT: strh w9, [sp, #8]
; CHECK-NEXT: fmov w9, s3
; CHECK-NEXT: movprfx z3, z7
; CHECK-NEXT: fcvtzs z3.d, p0/m, z7.d
; CHECK-NEXT: strh w8, [sp]
; CHECK-NEXT: strh w8, [sp, #4]
; CHECK-NEXT: fmov w8, s16
; CHECK-NEXT: strh w9, [sp]
; CHECK-NEXT: strh w8, [sp, #14]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: uzp1 z1.s, z4.s, z4.s
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -89,22 +89,22 @@ define void @alloc_v32i8(ptr %st_ptr) nounwind {
; CHECK-NEXT: ldp q0, q3, [sp, #16]
; CHECK-NEXT: mov z1.b, z0.b[14]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: mov z2.b, z0.b[12]
; CHECK-NEXT: mov z4.b, z0.b[10]
; CHECK-NEXT: mov z2.b, z0.b[12]
; CHECK-NEXT: mov z5.b, z0.b[8]
; CHECK-NEXT: strb w8, [sp]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov z1.b, z0.b[6]
; CHECK-NEXT: strb w8, [sp, #7]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: mov z2.b, z0.b[4]
; CHECK-NEXT: mov z0.b, z0.b[2]
; CHECK-NEXT: strb w8, [sp, #6]
; CHECK-NEXT: strb w8, [sp, #7]
; CHECK-NEXT: fmov w8, s4
; CHECK-NEXT: strb w9, [sp, #6]
; CHECK-NEXT: fmov w9, s5
; CHECK-NEXT: strb w8, [sp, #5]
; CHECK-NEXT: fmov w8, s5
; CHECK-NEXT: strb w8, [sp, #4]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: strb w9, [sp, #4]
; CHECK-NEXT: strb w8, [sp, #3]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: strb w8, [sp, #2]
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10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -259,16 +259,16 @@ define <8 x float> @masked_load_v8f32(ptr %src, <8 x i1> %mask) {
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: mov z1.b, z0.b[6]
; CHECK-NEXT: strh w8, [sp, #6]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: mov z2.b, z0.b[5]
; CHECK-NEXT: mov z0.b, z0.b[4]
; CHECK-NEXT: strh w8, [sp, #4]
; CHECK-NEXT: strh w8, [sp, #6]
; CHECK-NEXT: fmov w8, s3
; CHECK-NEXT: strh w9, [sp, #4]
; CHECK-NEXT: fmov w9, s4
; CHECK-NEXT: strh w8, [sp, #2]
; CHECK-NEXT: fmov w8, s4
; CHECK-NEXT: strh w8, [sp, #14]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: strh w9, [sp, #14]
; CHECK-NEXT: strh w8, [sp, #12]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: strh w8, [sp, #10]
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -241,27 +241,27 @@ define void @masked_store_v8f32(ptr %dst, <8 x i1> %mask) {
; CHECK-NEXT: mov z4.b, z0.b[4]
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: strh w8, [sp, #14]
; CHECK-NEXT: fmov w8, s2
; CHECK-NEXT: fmov w9, s2
; CHECK-NEXT: mov z2.s, #0 // =0x0
; CHECK-NEXT: strh w8, [sp, #12]
; CHECK-NEXT: strh w8, [sp, #14]
; CHECK-NEXT: fmov w8, s3
; CHECK-NEXT: mov z3.b, z0.b[2]
; CHECK-NEXT: strh w8, [sp, #10]
; CHECK-NEXT: fmov w8, s4
; CHECK-NEXT: strh w9, [sp, #12]
; CHECK-NEXT: fmov w9, s4
; CHECK-NEXT: mov z4.b, z0.b[1]
; CHECK-NEXT: strh w8, [sp, #8]
; CHECK-NEXT: strh w8, [sp, #10]
; CHECK-NEXT: mov x8, #4 // =0x4
; CHECK-NEXT: strh w9, [sp, #8]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: ldr d1, [sp, #8]
; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: lsl z1.s, z1.s, #31
; CHECK-NEXT: asr z1.s, z1.s, #31
; CHECK-NEXT: cmpne p1.s, p0/z, z1.s, #0
; CHECK-NEXT: mov z1.b, z0.b[3]
; CHECK-NEXT: st1w { z2.s }, p1, [x0, x8, lsl #2]
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: strh w8, [sp]
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: strh w9, [sp]
; CHECK-NEXT: strh w8, [sp, #6]
; CHECK-NEXT: fmov w8, s3
; CHECK-NEXT: strh w8, [sp, #4]
Expand Down
206 changes: 103 additions & 103 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
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