323 changes: 281 additions & 42 deletions llvm/lib/CodeGen/MIRParser/MIParser.cpp
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38 changes: 30 additions & 8 deletions llvm/lib/CodeGen/MIRParser/MIParser.h
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Original file line number Diff line number Diff line change
Expand Up @@ -36,9 +36,36 @@ struct PerFunctionMIParsingState {
DenseMap<unsigned, unsigned> JumpTableSlots;
};

bool parseMachineInstr(MachineInstr *&MI, SourceMgr &SM, MachineFunction &MF,
StringRef Src, const PerFunctionMIParsingState &PFS,
const SlotMapping &IRSlots, SMDiagnostic &Error);
/// Parse the machine basic block definitions, and skip the machine
/// instructions.
///
/// This function runs the first parsing pass on the machine function's body.
/// It parses only the machine basic block definitions and creates the machine
/// basic blocks in the given machine function.
///
/// The machine instructions aren't parsed during the first pass because all
/// the machine basic blocks aren't defined yet - this makes it impossible to
/// resolve the machine basic block references.
///
/// Return true if an error occurred.
bool parseMachineBasicBlockDefinitions(MachineFunction &MF, StringRef Src,
PerFunctionMIParsingState &PFS,
const SlotMapping &IRSlots,
SMDiagnostic &Error);

/// Parse the machine instructions.
///
/// This function runs the second parsing pass on the machine function's body.
/// It skips the machine basic block definitions and parses only the machine
/// instructions and basic block attributes like liveins and successors.
///
/// The second parsing pass assumes that the first parsing pass already ran
/// on the given source string.
///
/// Return true if an error occurred.
bool parseMachineInstructions(MachineFunction &MF, StringRef Src,
const PerFunctionMIParsingState &PFS,
const SlotMapping &IRSlots, SMDiagnostic &Error);

bool parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM,
MachineFunction &MF, StringRef Src,
Expand All @@ -57,11 +84,6 @@ bool parseVirtualRegisterReference(unsigned &Reg, SourceMgr &SM,
const SlotMapping &IRSlots,
SMDiagnostic &Error);

bool parseIRBlockReference(const BasicBlock *&BB, SourceMgr &SM,
MachineFunction &MF, StringRef Src,
const PerFunctionMIParsingState &PFS,
const SlotMapping &IRSlots, SMDiagnostic &Error);

} // end namespace llvm

#endif
103 changes: 14 additions & 89 deletions llvm/lib/CodeGen/MIRParser/MIRParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -96,13 +96,6 @@ class MIRParserImpl {
/// Return true if error occurred.
bool initializeMachineFunction(MachineFunction &MF);

/// Initialize the machine basic block using it's YAML representation.
///
/// Return true if an error occurred.
bool initializeMachineBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
const yaml::MachineBasicBlock &YamlMBB,
const PerFunctionMIParsingState &PFS);

bool initializeRegisterInfo(MachineFunction &MF,
const yaml::MachineFunction &YamlMF,
PerFunctionMIParsingState &PFS);
Expand Down Expand Up @@ -294,36 +287,15 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
return true;
}

const auto &F = *MF.getFunction();
for (const auto &YamlMBB : YamlMF.BasicBlocks) {
const BasicBlock *BB = nullptr;
const yaml::StringValue &Name = YamlMBB.Name;
const yaml::StringValue &IRBlock = YamlMBB.IRBlock;
if (!Name.Value.empty()) {
BB = dyn_cast_or_null<BasicBlock>(
F.getValueSymbolTable().lookup(Name.Value));
if (!BB)
return error(Name.SourceRange.Start,
Twine("basic block '") + Name.Value +
"' is not defined in the function '" + MF.getName() +
"'");
}
if (!IRBlock.Value.empty()) {
// TODO: Report an error when both name and ir block are specified.
SMDiagnostic Error;
if (parseIRBlockReference(BB, SM, MF, IRBlock.Value, PFS, IRSlots, Error))
return error(Error, IRBlock.SourceRange);
}
auto *MBB = MF.CreateMachineBasicBlock(BB);
MF.insert(MF.end(), MBB);
bool WasInserted =
PFS.MBBSlots.insert(std::make_pair(YamlMBB.ID, MBB)).second;
if (!WasInserted)
return error(Twine("redefinition of machine basic block with id #") +
Twine(YamlMBB.ID));
SMDiagnostic Error;
if (parseMachineBasicBlockDefinitions(MF, YamlMF.Body.Value.Value, PFS,
IRSlots, Error)) {
reportDiagnostic(
diagFromBlockStringDiag(Error, YamlMF.Body.Value.SourceRange));
return true;
}

if (YamlMF.BasicBlocks.empty())
if (MF.empty())
return error(Twine("machine function '") + Twine(MF.getName()) +
"' requires at least one machine basic block in its body");
// Initialize the frame information after creating all the MBBs so that the
Expand All @@ -335,13 +307,13 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
if (!YamlMF.JumpTableInfo.Entries.empty() &&
initializeJumpTableInfo(MF, YamlMF.JumpTableInfo, PFS))
return true;
// Initialize the machine basic blocks after creating them all so that the
// machine instructions parser can resolve the MBB references.
unsigned I = 0;
for (const auto &YamlMBB : YamlMF.BasicBlocks) {
if (initializeMachineBasicBlock(MF, *MF.getBlockNumbered(I++), YamlMBB,
PFS))
return true;
// Parse the machine instructions after creating all of the MBBs so that the
// parser can resolve the MBB references.
if (parseMachineInstructions(MF, YamlMF.Body.Value.Value, PFS, IRSlots,
Error)) {
reportDiagnostic(
diagFromBlockStringDiag(Error, YamlMF.Body.Value.SourceRange));
return true;
}
inferRegisterInfo(MF, YamlMF);
// FIXME: This is a temporary workaround until the reserved registers can be
Expand All @@ -351,53 +323,6 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
return false;
}

bool MIRParserImpl::initializeMachineBasicBlock(
MachineFunction &MF, MachineBasicBlock &MBB,
const yaml::MachineBasicBlock &YamlMBB,
const PerFunctionMIParsingState &PFS) {
MBB.setAlignment(YamlMBB.Alignment);
if (YamlMBB.AddressTaken)
MBB.setHasAddressTaken();
MBB.setIsLandingPad(YamlMBB.IsLandingPad);
SMDiagnostic Error;
// Parse the successors.
const auto &Weights = YamlMBB.SuccessorWeights;
bool HasWeights = !Weights.empty();
if (HasWeights && Weights.size() != YamlMBB.Successors.size()) {
bool IsFew = Weights.size() < YamlMBB.Successors.size();
return error(IsFew ? Weights.back().SourceRange.End
: Weights[YamlMBB.Successors.size()].SourceRange.Start,
Twine("too ") + (IsFew ? "few" : "many") +
" successor weights, expected " +
Twine(YamlMBB.Successors.size()) + ", have " +
Twine(Weights.size()));
}
size_t SuccessorIndex = 0;
for (const auto &MBBSource : YamlMBB.Successors) {
MachineBasicBlock *SuccMBB = nullptr;
if (parseMBBReference(SuccMBB, MBBSource, MF, PFS))
return true;
// TODO: Report an error when adding the same successor more than once.
MBB.addSuccessor(SuccMBB, HasWeights ? Weights[SuccessorIndex++].Value : 0);
}
// Parse the liveins.
for (const auto &LiveInSource : YamlMBB.LiveIns) {
unsigned Reg = 0;
if (parseNamedRegisterReference(Reg, SM, MF, LiveInSource.Value, PFS,
IRSlots, Error))
return error(Error, LiveInSource.SourceRange);
MBB.addLiveIn(Reg);
}
// Parse the instructions.
for (const auto &MISource : YamlMBB.Instructions) {
MachineInstr *MI = nullptr;
if (parseMachineInstr(MI, SM, MF, MISource.Value, PFS, IRSlots, Error))
return error(Error, MISource.SourceRange);
MBB.insert(MBB.end(), MI);
}
return false;
}

bool MIRParserImpl::initializeRegisterInfo(MachineFunction &MF,
const yaml::MachineFunction &YamlMF,
PerFunctionMIParsingState &PFS) {
Expand Down
122 changes: 73 additions & 49 deletions llvm/lib/CodeGen/MIRPrinter.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -83,8 +83,6 @@ class MIRPrinter {
const MachineConstantPool &ConstantPool);
void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
const MachineJumpTableInfo &JTI);
void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
const MachineBasicBlock &MBB);
void convertStackObjects(yaml::MachineFunction &MF,
const MachineFrameInfo &MFI,
const TargetRegisterInfo *TRI);
Expand All @@ -93,10 +91,6 @@ class MIRPrinter {
void initRegisterMaskIds(const MachineFunction &MF);
};

} // end namespace llvm

namespace {

/// This class prints out the machine instructions using the MIR serialization
/// format.
class MIPrinter {
Expand All @@ -112,6 +106,8 @@ class MIPrinter {
: OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
StackObjectOperandMapping(StackObjectOperandMapping) {}

void print(const MachineBasicBlock &MBB);

void print(const MachineInstr &MI);
void printMBBReference(const MachineBasicBlock &MBB);
void printIRBlockReference(const BasicBlock &BB);
Expand All @@ -125,7 +121,7 @@ class MIPrinter {
void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
};

} // end anonymous namespace
} // end namespace llvm

namespace llvm {
namespace yaml {
Expand Down Expand Up @@ -181,11 +177,16 @@ void MIRPrinter::print(const MachineFunction &MF) {
convert(YamlMF, *ConstantPool);
if (const auto *JumpTableInfo = MF.getJumpTableInfo())
convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
raw_string_ostream StrOS(YamlMF.Body.Value.Value);
bool IsNewlineNeeded = false;
for (const auto &MBB : MF) {
yaml::MachineBasicBlock YamlMBB;
convert(MST, YamlMBB, MBB);
YamlMF.BasicBlocks.push_back(YamlMBB);
if (IsNewlineNeeded)
StrOS << "\n";
MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
.print(MBB);
IsNewlineNeeded = true;
}
StrOS.flush();
yaml::Output Out(OS);
Out << YamlMF;
}
Expand Down Expand Up @@ -364,64 +365,87 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
}
}

void MIRPrinter::convert(ModuleSlotTracker &MST,
yaml::MachineBasicBlock &YamlMBB,
const MachineBasicBlock &MBB) {
void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
const auto *TRI = MF.getSubtarget().getRegisterInfo();
unsigned I = 0;
for (const uint32_t *Mask : TRI->getRegMasks())
RegisterMaskIds.insert(std::make_pair(Mask, I++));
}

void MIPrinter::print(const MachineBasicBlock &MBB) {
assert(MBB.getNumber() >= 0 && "Invalid MBB number");
YamlMBB.ID = (unsigned)MBB.getNumber();
OS << "bb." << MBB.getNumber();
bool HasAttributes = false;
if (const auto *BB = MBB.getBasicBlock()) {
if (BB->hasName()) {
YamlMBB.Name.Value = BB->getName();
OS << "." << BB->getName();
} else {
HasAttributes = true;
OS << " (";
int Slot = MST.getLocalSlot(BB);
if (Slot == -1)
YamlMBB.IRBlock.Value = "<badref>";
OS << "<ir-block badref>";
else
YamlMBB.IRBlock.Value = (Twine("%ir-block.") + Twine(Slot)).str();
OS << (Twine("%ir-block.") + Twine(Slot)).str();
}
}
YamlMBB.Alignment = MBB.getAlignment();
YamlMBB.AddressTaken = MBB.hasAddressTaken();
YamlMBB.IsLandingPad = MBB.isLandingPad();
for (const auto *SuccMBB : MBB.successors()) {
std::string Str;
raw_string_ostream StrOS(Str);
MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
.printMBBReference(*SuccMBB);
YamlMBB.Successors.push_back(StrOS.str());
if (MBB.hasAddressTaken()) {
OS << (HasAttributes ? ", " : " (");
OS << "address-taken";
HasAttributes = true;
}
if (MBB.hasSuccessorWeights()) {
for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I)
YamlMBB.SuccessorWeights.push_back(
yaml::UnsignedValue(MBB.getSuccWeight(I)));
if (MBB.isLandingPad()) {
OS << (HasAttributes ? ", " : " (");
OS << "landing-pad";
HasAttributes = true;
}
if (MBB.getAlignment()) {
OS << (HasAttributes ? ", " : " (");
OS << "align " << MBB.getAlignment();
HasAttributes = true;
}
if (HasAttributes)
OS << ")";
OS << ":\n";

bool HasLineAttributes = false;
// Print the successors
if (!MBB.succ_empty()) {
OS.indent(2) << "successors: ";
for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
if (I != MBB.succ_begin())
OS << ", ";
printMBBReference(**I);
if (MBB.hasSuccessorWeights())
OS << '(' << MBB.getSuccWeight(I) << ')';
}
OS << "\n";
HasLineAttributes = true;
}

// Print the live in registers.
const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
assert(TRI && "Expected target register info");
for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
std::string Str;
raw_string_ostream StrOS(Str);
printReg(*I, StrOS, TRI);
YamlMBB.LiveIns.push_back(StrOS.str());
if (!MBB.livein_empty()) {
OS.indent(2) << "liveins: ";
for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
if (I != MBB.livein_begin())
OS << ", ";
printReg(*I, OS, TRI);
}
OS << "\n";
HasLineAttributes = true;
}
// Print the machine instructions.
YamlMBB.Instructions.reserve(MBB.size());
std::string Str;

if (HasLineAttributes)
OS << "\n";
for (const auto &MI : MBB) {
raw_string_ostream StrOS(Str);
MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping).print(MI);
YamlMBB.Instructions.push_back(StrOS.str());
Str.clear();
OS.indent(2);
print(MI);
OS << "\n";
}
}

void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
const auto *TRI = MF.getSubtarget().getRegisterInfo();
unsigned I = 0;
for (const uint32_t *Mask : TRI->getRegMasks())
RegisterMaskIds.insert(std::make_pair(Mask, I++));
}

void MIPrinter::print(const MachineInstr &MI) {
const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
const auto *TRI = SubTarget.getRegisterInfo();
Expand Down
27 changes: 13 additions & 14 deletions llvm/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,18 +15,17 @@
...
---
name: trivial_fp_func
body:
- id: 0
name: entry
liveins: [ '%lr', '%fp', '%lr', '%fp' ]
instructions:
- '%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2'
- '%fp = frame-setup ADDXri %sp, 0, 0'
# CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16
- 'frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16'
- 'frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8'
- 'frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16'
- 'BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp'
- '%sp, %fp, %lr = LDPXpost %sp, 2'
- RET_ReallyLR
body: |
bb.0.entry:
liveins: %lr, %fp, %lr, %fp
%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2
%fp = frame-setup ADDXri %sp, 0, 0
; CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16
frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16
frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8
frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16
BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
%sp, %fp, %lr = LDPXpost %sp, 2
RET_ReallyLR
...
21 changes: 10 additions & 11 deletions llvm/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,15 +15,14 @@
...
---
name: trivial_fp_func
body:
- id: 0
name: entry
liveins: [ '%lr', '%fp', '%lr', '%fp' ]
instructions:
- '%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2'
- '%fp = frame-setup ADDXri %sp, 0, 0'
- 'BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp'
# CHECK: %sp, %fp, %lr = LDPXpost %sp, 2
- '%sp, %fp, %lr = LDPXpost %sp, 2'
- RET_ReallyLR
body: |
bb.0.entry:
liveins: %lr, %fp, %lr, %fp
%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2
%fp = frame-setup ADDXri %sp, 0, 0
BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
; CHECK: %sp, %fp, %lr = LDPXpost %sp, 2
%sp, %fp, %lr = LDPXpost %sp, 2
RET_ReallyLR
...
47 changes: 23 additions & 24 deletions llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,28 +38,27 @@ liveins:
- { reg: '%sgpr0_sgpr1' }
frameInfo:
maxAlignment: 8
body:
- id: 0
name: entry
liveins: [ '%sgpr0_sgpr1' ]
instructions:
- '%sgpr2_sgpr3 = S_GETPC_B64'
# CHECK: [[@LINE+1]]:50: expected the name of the target index
- '%sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc'
- '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
- '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
- '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
- '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
- '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
- '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
- '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
- '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
- '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
- '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
- '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
- '%sgpr7 = S_MOV_B32 61440'
- '%sgpr6 = S_MOV_B32 -1'
- '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
- 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
- S_ENDPGM
body: |
bb.0.entry:
liveins: %sgpr0_sgpr1
%sgpr2_sgpr3 = S_GETPC_B64
; CHECK: [[@LINE+1]]:45: expected the name of the target index
%sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc
%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
%sgpr7 = S_MOV_B32 61440
%sgpr6 = S_MOV_B32 -1
%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
S_ENDPGM
...
47 changes: 23 additions & 24 deletions llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,28 +38,27 @@ liveins:
- { reg: '%sgpr0_sgpr1' }
frameInfo:
maxAlignment: 8
body:
- id: 0
name: entry
liveins: [ '%sgpr0_sgpr1' ]
instructions:
- '%sgpr2_sgpr3 = S_GETPC_B64'
# CHECK: [[@LINE+1]]:50: use of undefined target index 'constdata-start'
- '%sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc'
- '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
- '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
- '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
- '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
- '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
- '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
- '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
- '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
- '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
- '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
- '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
- '%sgpr7 = S_MOV_B32 61440'
- '%sgpr6 = S_MOV_B32 -1'
- '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
- 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
- S_ENDPGM
body: |
bb.0.entry:
liveins: %sgpr0_sgpr1
%sgpr2_sgpr3 = S_GETPC_B64
; CHECK: [[@LINE+1]]:45: use of undefined target index 'constdata-start'
%sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc
%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
%sgpr7 = S_MOV_B32 61440
%sgpr6 = S_MOV_B32 -1
%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
S_ENDPGM
...
94 changes: 46 additions & 48 deletions llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,30 +47,29 @@ liveins:
- { reg: '%sgpr0_sgpr1' }
frameInfo:
maxAlignment: 8
body:
- id: 0
name: entry
liveins: [ '%sgpr0_sgpr1' ]
instructions:
- '%sgpr2_sgpr3 = S_GETPC_B64'
# CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
- '%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc'
- '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
- '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
- '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
- '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
- '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
- '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
- '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
- '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
- '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
- '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
- '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
- '%sgpr7 = S_MOV_B32 61440'
- '%sgpr6 = S_MOV_B32 -1'
- '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
- 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
- S_ENDPGM
body: |
bb.0.entry:
liveins: %sgpr0_sgpr1
%sgpr2_sgpr3 = S_GETPC_B64
; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
%sgpr7 = S_MOV_B32 61440
%sgpr6 = S_MOV_B32 -1
%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
S_ENDPGM
...
---
name: float2
Expand All @@ -79,28 +78,27 @@ liveins:
- { reg: '%sgpr0_sgpr1' }
frameInfo:
maxAlignment: 8
body:
- id: 0
name: entry
liveins: [ '%sgpr0_sgpr1' ]
instructions:
- '%sgpr2_sgpr3 = S_GETPC_B64'
# CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
- '%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc'
- '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
- '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
- '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
- '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
- '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
- '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
- '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
- '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
- '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
- '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
- '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
- '%sgpr7 = S_MOV_B32 61440'
- '%sgpr6 = S_MOV_B32 -1'
- '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
- 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
- S_ENDPGM
body: |
bb.0.entry:
liveins: %sgpr0_sgpr1
%sgpr2_sgpr3 = S_GETPC_B64
; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
%sgpr7 = S_MOV_B32 61440
%sgpr6 = S_MOV_B32 -1
%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
S_ENDPGM
...
50 changes: 25 additions & 25 deletions llvm/test/CodeGen/MIR/Generic/basic-blocks.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,37 +13,37 @@
ret i32 0
}

define i32 @test() {
start:
ret i32 0
}

...
---
# CHECK: name: foo
# CHECK-LABEL: name: foo
# CHECK: body:
# CHECK-NEXT: - id: 0
# CHECK-NEXT: name: entry
# CHECK-NEXT: alignment: 0
# CHECK-NEXT: isLandingPad: false
# CHECK-NEXT: addressTaken: false
# CHECK-NEXT: bb.0.entry:
name: foo
body:
- id: 0
name: entry
body: |
bb.0.entry:
...
---
# CHECK: name: bar
# CHECK-LABEL: name: bar
# CHECK: body:
# CHECK-NEXT: - id: 0
# CHECK-NEXT: name: start
# CHECK-NEXT: alignment: 4
# CHECK-NEXT: isLandingPad: false
# CHECK-NEXT: addressTaken: false
# CHECK-NEXT: - id: 1
# CHECK-NEXT: alignment: 0
# CHECK-NEXT: isLandingPad: false
# CHECK-NEXT: addressTaken: true
# CHECK-NEXT: bb.0.start (align 4):
# CHECK: bb.1 (address-taken):
name: bar
body:
- id: 0
name: start
alignment: 4
- id: 1
addressTaken: true
body: |
bb.0.start (align 4):
bb.1 (address-taken):
...
---
# CHECK-LABEL: name: test
# CHECK: body:
# CHECK-NEXT: bb.0.start (address-taken, align 4):
# CHECK: bb.1 (address-taken, align 4):
name: test
body: |
bb.0.start (align 4, address-taken):
bb.1 (address-taken, align 4):
...
8 changes: 4 additions & 4 deletions ...machine-basic-block-expected-ir-block.mir → ...eric/expected-colon-after-basic-block.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,14 +3,14 @@
--- |

define i32 @foo() {
entry:
ret i32 0
}

...
---
name: foo
body:
- id: 0
# CHECK: [[@LINE+1]]:19: expected an IR block reference
ir-block: '0'
body: |
; CHECK: [[@LINE+1]]:13: expected ':'
bb.0.entry
...
29 changes: 0 additions & 29 deletions llvm/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir
View file

This file was deleted.

17 changes: 8 additions & 9 deletions llvm/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,13 +17,12 @@
...
---
name: foo
body:
- id: 0
name: entry
# CHECK: [[@LINE+1]]:35: expected a machine basic block reference
successors: [ '%bb.1.less', '2' ]
- id: 1
name: less
- id: 2
name: exit
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:29: expected a machine basic block reference
successors: %bb.1.less, 2
bb.1.less:
bb.2.exit:
...
10 changes: 4 additions & 6 deletions llvm/test/CodeGen/MIR/Generic/frame-info.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,9 +44,8 @@ tracksRegLiveness: true
# CHECK: body
frameInfo:
maxAlignment: 4
body:
- id: 0
name: entry
body: |
bb.0.entry:
...
---
name: test2
Expand Down Expand Up @@ -84,8 +83,7 @@ frameInfo:
hasOpaqueSPAdjustment: true
hasVAStart: true
hasMustTailInVarArgFunc: true
body:
- id: 0
name: entry
body: |
bb.0.entry:
...

29 changes: 14 additions & 15 deletions llvm/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,19 +36,18 @@ jumpTable:
entries:
- id: 0
blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
body:
- id: 0
name: entry
- id: 1
name: entry
- id: 2
name: def
- id: 3
name: lbl1
- id: 4
name: lbl2
- id: 5
name: lbl3
- id: 6
name: lbl4
body: |
bb.0.entry:
bb.1.entry:
bb.2.def:
bb.3.lbl1:
bb.4.lbl2:
bb.5.lbl3:
bb.6.lbl4:
...
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/MIR/Generic/llvmIR.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,6 @@
...
---
name: foo
body:
- id: 0
body: |
bb.0:
...
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/MIR/Generic/llvmIRMissing.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,6 @@
---
# CHECK: name: foo
name: foo
body:
- id: 0
body: |
bb.0:
...
8 changes: 3 additions & 5 deletions llvm/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,7 @@
...
---
name: foo
body:
# CHECK: id: 0
# CHECK: ir-block: '%ir-block.0'
- id: 0
ir-block: '%ir-block.0'
body: |
; CHECK: bb.0 (%ir-block.0):
bb.0 (%ir-block.0):
...
9 changes: 5 additions & 4 deletions llvm/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,9 @@
...
---
name: foo
body:
# CHECK: redefinition of machine basic block with id #0
- id: 0
- id: 0
body: |
; CHECK: [[@LINE+3]]:3: redefinition of machine basic block with id #0
bb.0:
bb.0:
...
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,7 @@
...
---
name: foo
body:
- id: 0
# CHECK: [[@LINE+1]]:19: use of undefined IR block '%ir-block.10'
ir-block: '%ir-block.10'
body: |
; CHECK: [[@LINE+1]]:9: use of undefined IR block '%ir-block.10'
bb.0 (%ir-block.10):
...
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,7 @@
...
---
name: foo
body:
# CHECK: [[@LINE+2]]:18: basic block 'entrie' is not defined in the function 'foo'
- id: 0
name: entrie
body: |
; CHECK: [[@LINE+1]]:3: basic block 'entrie' is not defined in the function 'foo'
bb.0.entrie:
...
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/MIR/Generic/machine-function-missing-function.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,12 +12,12 @@
...
---
name: foo
body:
- id: 0
body: |
bb.0:
...
---
# CHECK: function 'faa' isn't defined in the provided LLVM IR
name: faa
body:
- id: 0
body: |
bb.0:
...
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/MIR/Generic/machine-function-missing-name.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,11 +16,11 @@
---
# CHECK: [[@LINE+1]]:1: missing required key 'name'
nme: foo
body:
- id: 0
body: |
bb.0:
...
---
name: bar
body:
- id: 0
body: |
bb.0:
...
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/MIR/Generic/machine-function.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,8 @@
# CHECK-NEXT: hasInlineAsm: false
# CHECK: ...
name: foo
body:
- id: 0
body: |
bb.0:
...
---
# CHECK: name: bar
Expand All @@ -37,8 +37,8 @@ body:
# CHECK-NEXT: hasInlineAsm: false
# CHECK: ...
name: bar
body:
- id: 0
body: |
bb.0:
...
---
# CHECK: name: func
Expand All @@ -48,8 +48,8 @@ body:
# CHECK: ...
name: func
alignment: 8
body:
- id: 0
body: |
bb.0:
...
---
# CHECK: name: func2
Expand All @@ -61,6 +61,6 @@ name: func2
alignment: 16
exposesReturnsTwice: true
hasInlineAsm: true
body:
- id: 0
body: |
bb.0:
...
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/MIR/Generic/register-info.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@
# CHECK-NEXT: tracksSubRegLiveness: false
# CHECK: ...
name: foo
body:
- id: 0
body: |
bb.0:
...
---
# CHECK: name: bar
Expand All @@ -35,6 +35,6 @@ name: bar
isSSA: false
tracksRegLiveness: true
tracksSubRegLiveness: true
body:
- id: 0
body: |
bb.0:
...
16 changes: 7 additions & 9 deletions llvm/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,11 @@ name: test
registers:
- { id: 0, class: float32regs }
- { id: 1, class: float32regs }
body:
- id: 0
name: entry
instructions:
- '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
# CHECK: [[@LINE+1]]:38: expected a floating point literal
- '%1 = FADD_rnf32ri %0, float 3'
- 'StoreRetvalF32 %1, 0'
- Return
body: |
bb.0.entry:
%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
; CHECK: [[@LINE+1]]:33: expected a floating point literal
%1 = FADD_rnf32ri %0, float 3
StoreRetvalF32 %1, 0
Return
...
60 changes: 28 additions & 32 deletions llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,22 +38,20 @@ registers:
- { id: 5, class: float32regs }
- { id: 6, class: float32regs }
- { id: 7, class: float32regs }
body:
- id: 0
name: entry
instructions:
- '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
- '%1 = CVT_f64_f32 %0, 0'
- '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1'
# CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00
- '%3 = FADD_rnf64ri %1, double 3.250000e+00'
- '%4 = CVT_f32_f64 %3, 5'
- '%5 = CVT_f32_s32 %2, 5'
# CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00
- '%6 = FADD_rnf32ri %5, float 6.250000e+00'
- '%7 = FMUL_rnf32rr %6, %4'
- 'StoreRetvalF32 %7, 0'
- Return
body: |
bb.0.entry:
%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
%1 = CVT_f64_f32 %0, 0
%2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1
; CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00
%3 = FADD_rnf64ri %1, double 3.250000e+00
%4 = CVT_f32_f64 %3, 5
%5 = CVT_f32_s32 %2, 5
; CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00
%6 = FADD_rnf32ri %5, float 6.250000e+00
%7 = FMUL_rnf32rr %6, %4
StoreRetvalF32 %7, 0
Return
...
---
name: test2
Expand All @@ -66,20 +64,18 @@ registers:
- { id: 5, class: float32regs }
- { id: 6, class: float32regs }
- { id: 7, class: float32regs }
body:
- id: 0
name: entry
instructions:
- '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0'
- '%1 = CVT_f64_f32 %0, 0'
- '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1'
# CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
- '%3 = FADD_rnf64ri %1, double 0x7FF8000000000000'
- '%4 = CVT_f32_f64 %3, 5'
- '%5 = CVT_f32_s32 %2, 5'
# CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
- '%6 = FADD_rnf32ri %5, float 0x7FF8000000000000'
- '%7 = FMUL_rnf32rr %6, %4'
- 'StoreRetvalF32 %7, 0'
- Return
body: |
bb.0.entry:
%0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0
%1 = CVT_f64_f32 %0, 0
%2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1
; CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
%3 = FADD_rnf64ri %1, double 0x7FF8000000000000
%4 = CVT_f32_f64 %3, 5
%5 = CVT_f32_s32 %2, 5
; CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
%6 = FADD_rnf32ri %5, float 0x7FF8000000000000
%7 = FMUL_rnf32rr %6, %4
StoreRetvalF32 %7, 0
Return
...
16 changes: 7 additions & 9 deletions llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,11 @@ name: test
registers:
- { id: 0, class: float32regs }
- { id: 1, class: float32regs }
body:
- id: 0
name: entry
instructions:
- '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
# CHECK: [[@LINE+1]]:38: floating point constant does not have type 'float'
- '%1 = FADD_rnf32ri %0, float 0xH3C00'
- 'StoreRetvalF32 %1, 0'
- Return
body: |
bb.0.entry:
%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
; CHECK: [[@LINE+1]]:33: floating point constant does not have type 'float'
%1 = FADD_rnf32ri %0, float 0xH3C00
StoreRetvalF32 %1, 0
Return
...
57 changes: 47 additions & 10 deletions llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,17 +9,54 @@
ret i32 %c
}

define i32 @test2(i32 %a, i32 %b) {
body:
%c = add i32 %a, %b
ret i32 %c
}

define i32 @test3() {
body:
ret i32 0
}

...
---
name: test
body:
# CHECK: name: body
# CHECK: liveins: [ '%edi', '%esi' ]
# CHECK-NEXT: instructions:
- id: 0
name: body
liveins: [ '%edi', '%esi' ]
instructions:
- '%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _'
- 'RETQ %eax'
body: |
; CHECK-LABEL: bb.0.body:
; CHECK-NEXT: liveins: %edi, %esi
bb.0.body:
liveins: %edi, %esi
%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _
RETQ %eax
...
---
name: test2
body: |
; CHECK-LABEL: name: test2
; Verify that we can have multiple lists of liveins that will be merged into
; one.
; CHECK: bb.0.body:
; CHECK-NEXT: liveins: %edi, %esi
bb.0.body:
liveins: %edi
liveins: %esi
%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _
RETQ %eax
...
---
name: test3
body: |
; Verify that we can have an empty list of liveins.
; CHECK-LABEL: name: test3
; CHECK: bb.0.body:
; CHECK-NEXT: %eax = MOV32r0 implicit-def dead %eflags
bb.0.body:
liveins:
%eax = MOV32r0 implicit-def dead %eflags
RETQ killed %eax
...
41 changes: 41 additions & 0 deletions llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s

--- |

define i32 @foo(i32 %a) {
entry:
%0 = icmp sle i32 %a, 10
br i1 %0, label %less, label %exit

less: ; preds = %entry
ret i32 0

exit: ; preds = %entry
ret i32 %a
}

...
---
name: foo
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
body: |
bb.0.entry:
successors: %bb.1.less, %bb.2.exit
liveins: %edi 44
CMP32ri8 %edi, 10, implicit-def %eflags
JG_1 %bb.2.exit, implicit killed %eflags
; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line
less bb.1:
%eax = MOV32r0 implicit-def dead %eflags
RETQ killed %eax
bb.2.exit:
liveins: %edi
%eax = COPY killed %edi
RETQ killed %eax
...
114 changes: 49 additions & 65 deletions llvm/test/CodeGen/MIR/X86/block-address-operands.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -54,84 +54,68 @@
...
---
name: test
body:
- id: 0
name: entry
successors: [ '%bb.1.block' ]
instructions:
# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
- '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _'
- 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
- 'JMP64m %rip, 1, _, @addr, _'
- id: 1
name: block
addressTaken: true
instructions:
- RETQ
body: |
bb.0.entry:
successors: %bb.1.block
; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _
bb.1.block (address-taken):
RETQ
...
---
name: test2
tracksRegLiveness: true
body:
- id: 0
name: entry
successors: [ '%bb.1' ]
instructions:
# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
- '%rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _'
- 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
- 'JMP64m %rip, 1, _, @addr, _'
- id: 1
addressTaken: true
instructions:
- RETQ
body: |
bb.0.entry:
successors: %bb.1
; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
%rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _
bb.1 (address-taken):
RETQ
...
---
name: slot_in_other_function
tracksRegLiveness: true
body:
- id: 0
name: entry
liveins: [ '%rdi' ]
instructions:
# CHECK: name: slot_in_other_function
# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
- '%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _'
- 'MOV64mr killed %rdi, 1, _, 0, _, killed %rax'
- RETQ
body: |
bb.0.entry:
liveins: %rdi
; CHECK-LABEL: name: slot_in_other_function
; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
MOV64mr killed %rdi, 1, _, 0, _, killed %rax
RETQ
...
---
name: test3
tracksRegLiveness: true
body:
- id: 0
name: entry
successors: [ '%bb.1' ]
instructions:
# CHECK: name: test3
# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
- '%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _'
- 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
- 'JMP64m %rip, 1, _, @addr, _'
- id: 1
addressTaken: true
instructions:
- RETQ
body: |
bb.0.entry:
successors: %bb.1
; CHECK-LABEL: name: test3
; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _
bb.1 (address-taken):
RETQ
...
---
name: test4
body:
- id: 0
name: entry
successors: [ '%bb.1.block' ]
instructions:
# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
- '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _'
- 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
- 'JMP64m %rip, 1, _, @addr, _'
- id: 1
name: block
addressTaken: true
instructions:
- RETQ
body: |
bb.0.entry:
successors: %bb.1.block
; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _
bb.1.block (address-taken):
RETQ
...
81 changes: 39 additions & 42 deletions llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,13 +34,12 @@
---
name: compute
tracksRegLiveness: true
body:
- id: 0
name: body
liveins: [ '%edi' ]
instructions:
- '%eax = COPY killed %edi'
- 'RETQ killed %eax'
body: |
bb.0.body:
liveins: %edi
%eax = COPY killed %edi
RETQ killed %eax
...
---
name: func
Expand All @@ -60,39 +59,37 @@ fixedStack:
stack:
- { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
- { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi' }
body:
- id: 0
name: entry
successors: [ '%bb.1.check' ]
liveins: [ '%edi', '%rbx' ]
instructions:
- 'frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
- '%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags'
- '%ebx = COPY %edi'
- 'MOV32mr %rsp, 1, _, 12, _, %ebx'
- id: 1
name: check
successors: [ '%bb.2.loop', '%bb.3.exit' ]
liveins: [ '%ebx' ]
instructions:
- 'CMP32ri8 %ebx, 10, implicit-def %eflags'
- 'JG_1 %bb.3.exit, implicit killed %eflags'
- 'JMP_1 %bb.2.loop'
- id: 2
name: loop
successors: [ '%bb.1.check' ]
liveins: [ '%ebx' ]
instructions:
- '%edi = MOV32rm %rsp, 1, _, 12, _'
- 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
- '%eax = DEC32r killed %eax, implicit-def dead %eflags'
- 'MOV32mr %rsp, 1, _, 12, _, killed %eax'
- 'JMP_1 %bb.1.check'
- id: 3
name: exit
instructions:
- '%eax = MOV32r0 implicit-def dead %eflags'
- '%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags'
- '%rbx = POP64r implicit-def %rsp, implicit %rsp'
- 'RETQ %eax'
body: |
bb.0.entry:
successors: %bb.1.check
liveins: %edi, %rbx
frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
%ebx = COPY %edi
MOV32mr %rsp, 1, _, 12, _, %ebx
bb.1.check:
successors: %bb.2.loop, %bb.3.exit
liveins: %ebx
CMP32ri8 %ebx, 10, implicit-def %eflags
JG_1 %bb.3.exit, implicit killed %eflags
JMP_1 %bb.2.loop
bb.2.loop:
successors: %bb.1.check
liveins: %ebx
%edi = MOV32rm %rsp, 1, _, 12, _
CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
%eax = DEC32r killed %eax, implicit-def dead %eflags
MOV32mr %rsp, 1, _, 12, _, killed %eax
JMP_1 %bb.1.check
bb.3.exit:
%eax = MOV32r0 implicit-def dead %eflags
%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
%rbx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax
...
16 changes: 7 additions & 9 deletions llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,14 +18,12 @@ frameInfo:
stackSize: 4040
stack:
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
body:
- id: 0
name: entry
instructions:
- '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'
# CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048
- 'CFI_INSTRUCTION .cfi_def_cfa_offset 4048'
- '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'
- 'RETQ'
body: |
bb.0.entry:
%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
; CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048
CFI_INSTRUCTION .cfi_def_cfa_offset 4048
%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
RETQ
...

21 changes: 10 additions & 11 deletions llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,15 +19,14 @@ frameInfo:
stackSize: 8
fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
body:
- id: 0
name: entry
liveins: [ '%rbp' ]
instructions:
- 'PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp'
- 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
- 'CFI_INSTRUCTION .cfi_offset %rbp, -16'
- '%rbp = MOV64rr %rsp'
# CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp
- 'CFI_INSTRUCTION .cfi_def_cfa_register %rbp'
body: |
bb.0.entry:
liveins: %rbp
PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
CFI_INSTRUCTION .cfi_def_cfa_offset 16
CFI_INSTRUCTION .cfi_offset %rbp, -16
%rbp = MOV64rr %rsp
; CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp
CFI_INSTRUCTION .cfi_def_cfa_register %rbp
...
35 changes: 17 additions & 18 deletions llvm/test/CodeGen/MIR/X86/cfi-offset.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,23 +26,22 @@ frameInfo:
hasCalls: true
fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
body:
- id: 0
name: entry
liveins: [ '%ecx', '%edi', '%edx', '%esi', '%rbx' ]
instructions:
- 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
- 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
# CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16
- 'CFI_INSTRUCTION .cfi_offset %rbx, -16'
- '%ebx = COPY %edi, implicit-def %rbx'
- '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'
- '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'
- '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'
- '%edi = COPY %ebx'
- 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
- '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'
- '%rbx = POP64r implicit-def %rsp, implicit %rsp'
- 'RETQ %eax'
body: |
bb.0.entry:
liveins: %ecx, %edi, %edx, %esi, %rbx
PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
CFI_INSTRUCTION .cfi_def_cfa_offset 16
; CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16
CFI_INSTRUCTION .cfi_offset %rbx, -16
%ebx = COPY %edi, implicit-def %rbx
%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
%edi = COPY %ebx
CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
%rbx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax
...

10 changes: 4 additions & 6 deletions llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,11 +17,9 @@ constants:
# CHECK: [[@LINE+1]]:18: redefinition of constant pool item '%const.0'
- id: 0
value: 'double 3.250000e+00'
body:
- id: 0
name: entry
instructions:
- '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
- 'RETQ %xmm0'
body: |
bb.0.entry:
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
RETQ %xmm0
...

76 changes: 34 additions & 42 deletions llvm/test/CodeGen/MIR/X86/constant-pool.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -57,17 +57,15 @@ constants:
- id: 1
value: 'float 6.250000e+00'
alignment: 4
body:
- id: 0
name: entry
instructions:
# CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
# CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
- '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
- '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'
- '%xmm1 = CVTSS2SDrr killed %xmm1'
- '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
- 'RETQ %xmm0'
body: |
bb.0.entry:
; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
%xmm1 = CVTSS2SDrr killed %xmm1
%xmm0 = MULSDrr killed %xmm0, killed %xmm1
RETQ %xmm0
...
---
# Verify that alignment can be inferred:
Expand All @@ -85,15 +83,13 @@ constants:
value: 'double 3.250000e+00'
- id: 1
value: 'float 6.250000e+00'
body:
- id: 0
name: entry
instructions:
- '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
- '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'
- '%xmm1 = CVTSS2SDrr killed %xmm1'
- '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
- 'RETQ %xmm0'
body: |
bb.0.entry:
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
%xmm1 = CVTSS2SDrr killed %xmm1
%xmm0 = MULSDrr killed %xmm0, killed %xmm1
RETQ %xmm0
...
---
# Verify that the non-standard alignments are respected:
Expand All @@ -113,17 +109,15 @@ constants:
- id: 1
value: 'float 6.250000e+00'
alignment: 1
body:
- id: 0
name: entry
instructions:
# CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
# CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
- '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
- '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'
- '%xmm1 = CVTSS2SDrr killed %xmm1'
- '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
- 'RETQ %xmm0'
body: |
bb.0.entry:
; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
%xmm1 = CVTSS2SDrr killed %xmm1
%xmm0 = MULSDrr killed %xmm0, killed %xmm1
RETQ %xmm0
...
---
# CHECK: name: test4
Expand All @@ -133,15 +127,13 @@ constants:
value: 'double 3.250000e+00'
- id: 1
value: 'float 6.250000e+00'
body:
- id: 0
name: entry
instructions:
# CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
# CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
- '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _'
- '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _'
- '%xmm1 = CVTSS2SDrr killed %xmm1'
- '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
- 'RETQ %xmm0'
body: |
bb.0.entry:
; CHECK: %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
%xmm1 = CVTSS2SDrr killed %xmm1
%xmm0 = MULSDrr killed %xmm0, killed %xmm1
RETQ %xmm0
...
10 changes: 4 additions & 6 deletions llvm/test/CodeGen/MIR/X86/constant-value-error.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,11 +17,9 @@ constants:
- id: 0
# CHECK: [[@LINE+1]]:19: expected type
value: 'dub 3.250000e+00'
body:
- id: 0
name: entry
instructions:
- '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
- 'RETQ %xmm0'
body: |
bb.0.entry:
%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
RETQ %xmm0
...

14 changes: 6 additions & 8 deletions llvm/test/CodeGen/MIR/X86/dead-register-flag.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,12 +15,10 @@
...
---
name: foo
body:
# CHECK: name: body
- id: 0
name: body
instructions:
# CHECK: - '%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags'
- '%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags'
- 'RETQ %eax'
body: |
; CHECK: bb.0.body:
bb.0.body:
; CHECK: %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
RETQ %eax
...
18 changes: 8 additions & 10 deletions llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,14 +16,12 @@ name: volatile_inc
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
body:
- id: 0
name: entry
liveins: [ '%rdi' ]
instructions:
# CHECK: [[@LINE+1]]:55: duplicate 'volatile' memory operand flag
- '%eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)'
- '%eax = INC32r killed %eax, implicit-def dead %eflags'
- 'MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)'
- 'RETQ %eax'
body: |
bb.0.entry:
liveins: %rdi
; CHECK: [[@LINE+1]]:50: duplicate 'volatile' memory operand flag
%eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)
%eax = INC32r killed %eax, implicit-def dead %eflags
MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
RETQ %eax
...
33 changes: 15 additions & 18 deletions llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,22 +17,19 @@
...
---
name: foo
body:
- id: 0
name: entry
successors: [ '%bb.1.less', '%bb.2.exit' ]
instructions:
- 'CMP32ri8 %edi, 10, implicit-def %eflags'
# CHECK: [[@LINE+1]]:36: duplicate 'implicit' register flag
- 'JG_1 %bb.2.exit, implicit implicit %eflags'
- id: 1
name: less
instructions:
- '%eax = MOV32r0 implicit-def %eflags'
- 'RETQ %eax'
- id: 2
name: exit
instructions:
- '%eax = COPY %edi'
- 'RETQ %eax'
body: |
bb.0.entry:
successors: %bb.1.less, %bb.2.exit
CMP32ri8 %edi, 10, implicit-def %eflags
; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag
JG_1 %bb.2.exit, implicit implicit %eflags
bb.1.less:
%eax = MOV32r0 implicit-def %eflags
RETQ %eax
bb.2.exit:
%eax = COPY %edi
RETQ %eax
...
29 changes: 14 additions & 15 deletions llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,19 +28,18 @@ frameInfo:
stackSize: 8
adjustsStack: true
hasCalls: true
body:
- id: 0
name: entry
liveins: [ '%edi', '%esi' ]
instructions:
- 'frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp'
- CFI_INSTRUCTION .cfi_def_cfa_offset 16
- '%ecx = COPY %edi'
- '%ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags'
# CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
- 'INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di'
- '%edi = COPY killed %ecx'
- 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
- '%rax = POP64r implicit-def %rsp, implicit %rsp'
- RETQ
body: |
bb.0.entry:
liveins: %edi, %esi
frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
CFI_INSTRUCTION .cfi_def_cfa_offset 16
%ecx = COPY %edi
%ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags
; CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
%edi = COPY killed %ecx
CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
%rax = POP64r implicit-def %rsp, implicit %rsp
RETQ
...
24 changes: 11 additions & 13 deletions llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,17 +16,15 @@ name: memory_alignment
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
body:
- id: 0
name: entry
liveins: [ '%rdi' ]
instructions:
# CHECK: [[@LINE+1]]:70: expected 'align'
- '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)'
- '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
- '%xmm2 = FsFLD0SS'
- '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
- 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
- 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
- RETQ
body: |
bb.0.entry:
liveins: %rdi
; CHECK: [[@LINE+1]]:65: expected 'align'
%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)
%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
%xmm2 = FsFLD0SS
%xmm1 = MOVSSrr killed %xmm1, killed %xmm2
MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
RETQ
...
24 changes: 11 additions & 13 deletions llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,17 +16,15 @@ name: memory_alignment
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
body:
- id: 0
name: entry
liveins: [ '%rdi' ]
instructions:
# CHECK: [[@LINE+1]]:75: expected an integer literal after 'align'
- '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)'
- '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
- '%xmm2 = FsFLD0SS'
- '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
- 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
- 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
- RETQ
body: |
bb.0.entry:
liveins: %rdi
; CHECK: [[@LINE+1]]:70: expected an integer literal after 'align'
%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)
%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
%xmm2 = FsFLD0SS
%xmm1 = MOVSSrr killed %xmm1, killed %xmm2
MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
RETQ
...
40 changes: 40 additions & 0 deletions llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s

--- |

define i32 @foo(i32 %a) {
entry:
%0 = icmp sle i32 %a, 10
br i1 %0, label %less, label %exit

less: ; preds = %entry
ret i32 0

exit: ; preds = %entry
ret i32 %a
}

...
---
name: foo
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
body: |
; CHECK: [[@LINE+1]]:3: expected a basic block definition before instructions
successors: %bb.1.less, %bb.2.exit
liveins: %edi 44
CMP32ri8 %edi, 10, implicit-def %eflags
JG_1 %bb.2.exit, implicit killed %eflags
bb.1.less:
%eax = MOV32r0 implicit-def dead %eflags
RETQ killed %eax
bb.2.exit:
liveins: %edi
%eax = COPY killed %edi
RETQ killed %eax
...
24 changes: 10 additions & 14 deletions llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,18 +17,14 @@
...
---
name: test
body:
- id: 0
name: entry
successors: [ '%bb.1.block' ]
instructions:
# CHECK: [[@LINE+1]]:56: expected an IR block reference
- '%rax = LEA64r %rip, 1, _, blockaddress(@test, _), _'
- 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
- 'JMP64m %rip, 1, _, @addr, _'
- id: 1
name: block
addressTaken: true
instructions:
- RETQ
body: |
bb.0.entry:
successors: %bb.1.block
; CHECK: [[@LINE+1]]:51: expected an IR block reference
%rax = LEA64r %rip, 1, _, blockaddress(@test, _), _
MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _
bb.1.block (address-taken):
RETQ
...
32 changes: 15 additions & 17 deletions llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,21 +24,19 @@ frameInfo:
hasCalls: true
fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
body:
- id: 0
name: entry
instructions:
- 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
- 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
# CHECK: [[@LINE+1]]:43: expected ','
- 'CFI_INSTRUCTION .cfi_offset %rbx -16'
- '%ebx = COPY %edi, implicit-def %rbx'
- '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'
- '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'
- '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'
- '%edi = COPY %ebx'
- 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
- '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'
- '%rbx = POP64r implicit-def %rsp, implicit %rsp'
- 'RETQ %eax'
body: |
bb.0.entry:
PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
CFI_INSTRUCTION .cfi_def_cfa_offset 16
; CHECK: [[@LINE+1]]:38: expected ','
CFI_INSTRUCTION .cfi_offset %rbx -16
%ebx = COPY %edi, implicit-def %rbx
%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
%edi = COPY %ebx
CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
%rbx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax
...
14 changes: 6 additions & 8 deletions llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,12 +16,10 @@ name: test
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
body:
- id: 0
name: entry2
liveins: [ '%rdi' ]
instructions:
# CHECK: [[@LINE+1]]:92: expected ',' before the next machine memory operand
- 'INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a)'
- RETQ
body: |
bb.0.entry2:
liveins: %rdi
; CHECK: [[@LINE+1]]:87: expected ',' before the next machine memory operand
INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a)
RETQ
...
28 changes: 12 additions & 16 deletions llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,20 +19,16 @@
...
---
name: foo
body:
- id: 0
name: entry
instructions:
- '%eax = MOV32rm %rdi, 1, _, 0, _'
- 'CMP32ri8 %eax, 10, implicit-def %eflags'
# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags'
- 'JG_1 %bb.2.exit, implicit %eax'
- id: 1
name: less
instructions:
- '%eax = MOV32r0 implicit-def %eflags'
- id: 2
name: exit
instructions:
- 'RETQ %eax'
body: |
bb.0.entry:
%eax = MOV32rm %rdi, 1, _, 0, _
CMP32ri8 %eax, 10, implicit-def %eflags
; CHECK: [[@LINE+1]]:22: expected an implicit register operand 'implicit %eflags'
JG_1 %bb.2.exit, implicit %eax
bb.1.less:
%eax = MOV32r0 implicit-def %eflags
bb.2.exit:
RETQ %eax
...
28 changes: 12 additions & 16 deletions llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,20 +19,16 @@
...
---
name: foo
body:
- id: 0
name: entry
instructions:
- '%eax = MOV32rm %rdi, 1, _, 0, _'
- 'CMP32ri8 %eax, 10, implicit-def %eflags'
# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags'
- 'JG_1 %bb.2.exit, implicit-def %eflags'
- id: 1
name: less
instructions:
- '%eax = MOV32r0 implicit-def %eflags'
- id: 2
name: exit
instructions:
- 'RETQ %eax'
body: |
bb.0.entry:
%eax = MOV32rm %rdi, 1, _, 0, _
CMP32ri8 %eax, 10, implicit-def %eflags
; CHECK: [[@LINE+1]]:22: expected an implicit register operand 'implicit %eflags'
JG_1 %bb.2.exit, implicit-def %eflags
bb.1.less:
%eax = MOV32r0 implicit-def %eflags
bb.2.exit:
RETQ %eax
...
14 changes: 6 additions & 8 deletions llvm/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,11 @@ name: test
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
body:
- id: 0
name: entry
liveins: [ '%rdi' ]
instructions:
# CHECK: [[@LINE+1]]:60: expected 'from'
- '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 %ir.a)'
- 'RETQ %eax'
body: |
bb.0.entry:
liveins: %rdi
; CHECK: [[@LINE+1]]:55: expected 'from'
%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 %ir.a)
RETQ %eax
...

24 changes: 10 additions & 14 deletions llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,18 +17,14 @@
...
---
name: test
body:
- id: 0
name: entry
successors: [ '%bb.1.block' ]
instructions:
# CHECK: [[@LINE+1]]:49: expected an IR function reference
- '%rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _'
- 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
- 'JMP64m %rip, 1, _, @addr, _'
- id: 1
name: block
addressTaken: true
instructions:
- RETQ
body: |
bb.0.entry:
successors: %bb.1.block
; CHECK: [[@LINE+1]]:44: expected an IR function reference
%rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _
MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _
bb.1.block (address-taken):
RETQ
...
24 changes: 10 additions & 14 deletions llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,18 +17,14 @@
...
---
name: test
body:
- id: 0
name: entry
successors: [ '%bb.1.block' ]
instructions:
# CHECK: [[@LINE+1]]:49: expected a global value
- '%rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _'
- 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
- 'JMP64m %rip, 1, _, @addr, _'
- id: 1
name: block
addressTaken: true
instructions:
- RETQ
body: |
bb.0.entry:
successors: %bb.1.block
; CHECK: [[@LINE+1]]:44: expected a global value
%rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _
MOV64mr %rip, 1, _, @addr, _, killed %rax
JMP64m %rip, 1, _, @addr, _

bb.1.block (address-taken):
RETQ
...
16 changes: 7 additions & 9 deletions llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,11 @@
...
---
name: inc
body:
- id: 0
name: entry
instructions:
# CHECK: [[@LINE+1]]:42: expected an integer literal after '+'
- '%rax = MOV64rm %rip, 1, _, @G + , _'
- '%eax = MOV32rm %rax, 1, _, 0, _'
- '%eax = INC32r %eax, implicit-def %eflags'
- 'RETQ %eax'
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:37: expected an integer literal after '+'
%rax = MOV64rm %rip, 1, _, @G + , _
%eax = MOV32rm %rax, 1, _, 0, _
%eax = INC32r %eax, implicit-def %eflags
RETQ %eax
...
38 changes: 38 additions & 0 deletions llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s

--- |

define i32 @foo(i32 %a) {
entry:
%0 = icmp sle i32 %a, 10
br i1 %0, label %less, label %exit

less:
ret i32 0

exit:
ret i32 %a
}

...
---
name: foo
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:29: expected an integer literal after '('
successors: %bb.1.less (_), %bb.2.exit(32)
liveins: %edi

CMP32ri8 %edi, 10, implicit-def %eflags
JG_1 %bb.2.exit, implicit killed %eflags

bb.1.less:
%eax = MOV32r0 implicit-def dead %eflags
RETQ killed %eax

bb.2.exit:
liveins: %edi

%eax = COPY killed %edi
RETQ killed %eax
...
14 changes: 6 additions & 8 deletions llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,12 +14,10 @@ name: test
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
body:
- id: 0
name: entry
liveins: [ '%rdi' ]
instructions:
# CHECK: [[@LINE+1]]:53: expected 'load' or 'store' memory operation
- '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a)'
- 'RETQ %eax'
body: |
bb.0.entry:
liveins: %rdi
; CHECK: [[@LINE+1]]:48: expected 'load' or 'store' memory operation
%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a)
RETQ %eax
...
12 changes: 5 additions & 7 deletions llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,12 +10,10 @@
...
---
name: foo
body:
- id: 0
name: entry
instructions:
# CHECK: [[@LINE+1]]:24: expected a machine operand
- '%eax = XOR32rr ='
- 'RETQ %eax'
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:20: expected a machine operand
%eax = XOR32rr =
RETQ %eax
...

18 changes: 8 additions & 10 deletions llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,14 +48,12 @@ frameInfo:
maxAlignment: 4
stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 }
body:
- id: 0
name: entry
instructions:
- '%0 = COPY %edi'
# CHECK: [[@LINE+1]]:51: expected a metadata node after 'debug-location'
- 'DBG_VALUE _, 0, !12, !13, debug-location 14'
- 'MOV32mr %stack.x.addr, 1, _, 0, _, %0'
- '%eax = COPY %0'
- 'RETQ %eax'
body: |
bb.0.entry:
%0 = COPY %edi
; CHECK: [[@LINE+1]]:46: expected a metadata node after 'debug-location'
DBG_VALUE _, 0, !12, !13, debug-location 14
MOV32mr %stack.x.addr, 1, _, 0, _, %0
%eax = COPY %0
RETQ %eax
...
18 changes: 8 additions & 10 deletions llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,14 +48,12 @@ frameInfo:
maxAlignment: 4
stack:
- { id: 0, name: x.addr, size: 4, alignment: 4 }
body:
- id: 0
name: entry
instructions:
- '%0 = COPY %edi'
# CHECK: [[@LINE+1]]:33: expected metadata id after '!'
- 'DBG_VALUE _, 0, !12, ! _'
- 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'
- '%eax = COPY %0'
- 'RETQ %eax'
body: |
bb.0.entry:
%0 = COPY %edi
; CHECK: [[@LINE+1]]:28: expected metadata id after '!'
DBG_VALUE _, 0, !12, ! _
MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
%eax = COPY %0
RETQ %eax
...
19 changes: 9 additions & 10 deletions llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,14 +17,13 @@ registers:
# CHECK: [[@LINE+1]]:48: expected a named register
- { id: 1, class: gr32, preferred-register: '%0' }
- { id: 2, class: gr32, preferred-register: '%edi' }
body:
- id: 0
name: body
liveins: [ '%edi', '%esi' ]
instructions:
- '%1 = COPY %esi'
- '%2 = COPY %edi'
- '%2 = IMUL32rr %2, %1, implicit-def dead %eflags'
- '%eax = COPY %2'
- 'RETQ killed %eax'
body: |
bb.0.body:
liveins: %edi, %esi

%1 = COPY %esi
%2 = COPY %edi
%2 = IMUL32rr %2, %1, implicit-def dead %eflags
%eax = COPY %2
RETQ killed %eax
...
81 changes: 39 additions & 42 deletions llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,13 +32,12 @@
---
name: compute
tracksRegLiveness: true
body:
- id: 0
name: body
liveins: [ '%edi' ]
instructions:
- '%eax = COPY killed %edi'
- 'RETQ killed %eax'
body: |
bb.0.body:
liveins: %edi

%eax = COPY killed %edi
RETQ killed %eax
...
---
name: func
Expand All @@ -53,39 +52,37 @@ fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%0' }
stack:
- { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
body:
- id: 0
name: entry
successors: [ '%bb.1.check' ]
liveins: [ '%edi', '%rbx' ]
instructions:
- 'frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
- '%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags'
- '%ebx = COPY %edi'
- 'MOV32mr %rsp, 1, _, 12, _, %ebx'
- id: 1
name: check
successors: [ '%bb.2.loop', '%bb.3.exit' ]
liveins: [ '%ebx' ]
instructions:
- 'CMP32ri8 %ebx, 10, implicit-def %eflags'
- 'JG_1 %bb.3.exit, implicit killed %eflags'
- 'JMP_1 %bb.2.loop'
- id: 2
name: loop
successors: [ '%bb.1.check' ]
liveins: [ '%ebx' ]
instructions:
- '%edi = MOV32rm %rsp, 1, _, 12, _'
- 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
- '%eax = DEC32r killed %eax, implicit-def dead %eflags'
- 'MOV32mr %rsp, 1, _, 12, _, killed %eax'
- 'JMP_1 %bb.1.check'
- id: 3
name: exit
instructions:
- '%eax = MOV32r0 implicit-def dead %eflags'
- '%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags'
- '%rbx = POP64r implicit-def %rsp, implicit %rsp'
- 'RETQ %eax'
body: |
bb.0.entry:
successors: %bb.1.check
liveins: %edi, %rbx

frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
%ebx = COPY %edi
MOV32mr %rsp, 1, _, 12, _, %ebx

bb.1.check:
successors: %bb.2.loop, %bb.3.exit
liveins: %ebx

CMP32ri8 %ebx, 10, implicit-def %eflags
JG_1 %bb.3.exit, implicit killed %eflags
JMP_1 %bb.2.loop

bb.2.loop:
successors: %bb.1.check
liveins: %ebx

%edi = MOV32rm %rsp, 1, _, 12, _
CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
%eax = DEC32r killed %eax, implicit-def dead %eflags
MOV32mr %rsp, 1, _, 12, _, killed %eax
JMP_1 %bb.1.check

bb.3.exit:
%eax = MOV32r0 implicit-def dead %eflags
%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
%rbx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax
...
15 changes: 7 additions & 8 deletions llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,12 +17,11 @@ registers:
liveins:
# CHECK: [[@LINE+1]]:13: expected a named register
- { reg: '%0' }
body:
- id: 0
name: body
liveins: [ '%edi' ]
instructions:
- '%0 = COPY %edi'
- '%eax = COPY %0'
- 'RETQ %eax'
body: |
bb.0.body:
liveins: %edi

%0 = COPY %edi
%eax = COPY %0
RETQ %eax
...
15 changes: 7 additions & 8 deletions llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -10,12 +10,11 @@
...
---
name: test
body:
- id: 0
name: body
# CHECK: [[@LINE+1]]:21: expected a named register
liveins: [ '%0' ]
instructions:
- '%eax = COPY %edi'
- 'RETQ %eax'
body: |
bb.0.body:
; CHECK: [[@LINE+1]]:14: expected a named register
liveins: %0

%eax = COPY %edi
RETQ %eax
...
41 changes: 41 additions & 0 deletions llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s

--- |

define i32 @foo(i32 %a) {
entry:
%0 = icmp sle i32 %a, 10
br i1 %0, label %less, label %exit

less: ; preds = %entry
ret i32 0

exit: ; preds = %entry
ret i32 %a
}

...
---
name: foo
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
body: |
bb.0.entry:
successors: %bb.1.less, %bb.2.exit
; CHECK: [[@LINE+1]]:19: expected line break at the end of a list
liveins: %edi 44

CMP32ri8 %edi, 10, implicit-def %eflags
JG_1 %bb.2.exit, implicit killed %eflags

bb.1.less:
%eax = MOV32r0 implicit-def dead %eflags
RETQ killed %eax

bb.2.exit:
liveins: %edi

%eax = COPY killed %edi
RETQ killed %eax
...
28 changes: 12 additions & 16 deletions llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,20 +18,16 @@
...
---
name: foo
body:
- id: 0
name: entry
instructions:
- '%eax = MOV32rm %rdi, 1, _, 0, _'
- 'CMP32ri8 %eax, 10, implicit-def %eflags'
# CHECK: [[@LINE+1]]:18: expected a number after '%bb.'
- 'JG_1 %bb.nah, implicit %eflags'
- id: 1
name: yes
instructions:
- '%eax = MOV32r0 implicit-def %eflags'
- id: 2
name: nah
instructions:
- 'RETQ %eax'
body: |
bb.0.entry:
%eax = MOV32rm %rdi, 1, _, 0, _
CMP32ri8 %eax, 10, implicit-def %eflags
; CHECK: [[@LINE+1]]:14: expected a number after '%bb.'
JG_1 %bb.nah, implicit %eflags

bb.1.true:
%eax = MOV32r0 implicit-def %eflags

bb.2.nah:
RETQ %eax
...
16 changes: 7 additions & 9 deletions llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,14 +16,12 @@ frameInfo:
stackSize: 4040
stack:
- { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
body:
- id: 0
name: entry
instructions:
- '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'
# CHECK: [[@LINE+1]]:46: expected a cfi offset
- 'CFI_INSTRUCTION .cfi_def_cfa_offset _'
- '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'
- 'RETQ'
body: |
bb.0.entry:
%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
; CHECK: [[@LINE+1]]:41: expected a cfi offset
CFI_INSTRUCTION .cfi_def_cfa_offset _
%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
RETQ
...

14 changes: 6 additions & 8 deletions llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,11 @@ name: test
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
body:
- id: 0
name: entry
liveins: [ '%rdi' ]
instructions:
# CHECK: [[@LINE+1]]:65: expected a pointer IR value
- '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b)'
- 'RETQ %eax'
body: |
bb.0.entry:
liveins: %rdi
; CHECK: [[@LINE+1]]:60: expected a pointer IR value
%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b)
RETQ %eax
...

24 changes: 11 additions & 13 deletions llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,17 +16,15 @@ name: memory_alignment
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
body:
- id: 0
name: entry
liveins: [ '%rdi' ]
instructions:
# CHECK: [[@LINE+1]]:76: expected an integer literal after 'align'
- '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)'
- '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
- '%xmm2 = FsFLD0SS'
- '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
- 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
- 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
- RETQ
body: |
bb.0.entry:
liveins: %rdi
; CHECK: [[@LINE+1]]:71: expected an integer literal after 'align'
%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)
%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
%xmm2 = FsFLD0SS
%xmm1 = MOVSSrr killed %xmm1, killed %xmm2
MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
RETQ
...
32 changes: 15 additions & 17 deletions llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,21 +24,19 @@ frameInfo:
hasCalls: true
fixedStack:
- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
body:
- id: 0
name: entry
instructions:
- 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
- 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
# CHECK: [[@LINE+1]]:38: expected a cfi register
- 'CFI_INSTRUCTION .cfi_offset %0, -16'
- '%ebx = COPY %edi, implicit-def %rbx'
- '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'
- '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'
- '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'
- '%edi = COPY %ebx'
- 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
- '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'
- '%rbx = POP64r implicit-def %rsp, implicit %rsp'
- 'RETQ %eax'
body: |
bb.0.entry:
PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
CFI_INSTRUCTION .cfi_def_cfa_offset 16
; CHECK: [[@LINE+1]]:33: expected a cfi register
CFI_INSTRUCTION .cfi_offset %0, -16
%ebx = COPY %edi, implicit-def %rbx
%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
%edi = COPY %ebx
CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
%rbx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax
...
12 changes: 5 additions & 7 deletions llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,11 +12,9 @@
...
---
name: foo
body:
- id: 0
name: entry
instructions:
# CHECK: [[@LINE+1]]:37: expected a register after register flags
- '%eax = MOV32r0 implicit-def 2'
- 'RETQ %eax'
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:33: expected a register after register flags
%eax = MOV32r0 implicit-def 2
RETQ %eax
...
14 changes: 6 additions & 8 deletions llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,11 @@ name: test
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
body:
- id: 0
name: entry
liveins: [ '%rdi' ]
instructions:
# CHECK: [[@LINE+1]]:58: expected the size integer literal after memory operation
- '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a)'
- 'RETQ %eax'
body: |
bb.0.entry:
liveins: %rdi
; CHECK: [[@LINE+1]]:53: expected the size integer literal after memory operation
%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a)
RETQ %eax
...

18 changes: 8 additions & 10 deletions llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,14 +16,12 @@ registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr8 }
- { id: 2, class: gr8 }
body:
- name: entry
id: 0
instructions:
- '%0 = COPY %edi'
# CHECK: [[@LINE+1]]:25: expected a subregister index after ':'
- '%1 = COPY %0 : 42'
- '%2 = AND8ri %1, 1, implicit-def %eflags'
- '%al = COPY %2'
- 'RETQ %al'
body: |
bb.0.entry:
%0 = COPY %edi
; CHECK: [[@LINE+1]]:20: expected a subregister index after ':'
%1 = COPY %0 : 42
%2 = AND8ri %1, 1, implicit-def %eflags
%al = COPY %2
RETQ %al
...
16 changes: 7 additions & 9 deletions llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,11 @@
...
---
name: inc
body:
- id: 0
name: entry
instructions:
# CHECK: [[@LINE+1]]:51: expected the name of the target flag
- '%rax = MOV64rm %rip, 1, _, target-flags( ) @G, _'
- '%eax = MOV32rm killed %rax, 1, _, 0, _'
- '%eax = INC32r killed %eax, implicit-def dead %eflags'
- 'RETQ %eax'
body: |
bb.0.entry:
; CHECK: [[@LINE+1]]:46: expected the name of the target flag
%rax = MOV64rm %rip, 1, _, target-flags( ) @G, _
%eax = MOV32rm killed %rax, 1, _, 0, _
%eax = INC32r killed %eax, implicit-def dead %eflags
RETQ %eax
...
14 changes: 6 additions & 8 deletions llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,13 +14,11 @@ name: test
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
body:
- id: 0
name: entry
liveins: [ '%rdi' ]
instructions:
# CHECK: [[@LINE+1]]:65: expected an IR value reference
- '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a)'
- 'RETQ %eax'
body: |
bb.0.entry:
liveins: %rdi
; CHECK: [[@LINE+1]]:60: expected an IR value reference
%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a)
RETQ %eax
...

15 changes: 7 additions & 8 deletions llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,12 +17,11 @@ registers:
liveins:
# CHECK: [[@LINE+1]]:34: expected a virtual register
- { reg: '%edi', virtual-reg: '%edi' }
body:
- id: 0
name: body
liveins: [ '%edi' ]
instructions:
- '%0 = COPY %edi'
- '%eax = COPY %0'
- 'RETQ %eax'
body: |
bb.0.body:
liveins: %edi

%0 = COPY %edi
%eax = COPY %0
RETQ %eax
...
66 changes: 32 additions & 34 deletions llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,38 +29,36 @@
---
name: test
tracksRegLiveness: true
body:
- id: 0
name: entry
successors: [ '%bb.1.entry', '%bb.2.entry' ]
liveins: [ '%edi' ]
instructions:
- '%rsp = SUB64ri32 %rsp, 520, implicit-def %eflags'
- '%rcx = LOAD_STACK_GUARD'
- 'MOV64mr %rsp, 1, _, 512, _, %rcx'
- '%rax = MOVSX64rr32 %edi'
- '%eax = MOV32rm %rsp, 4, %rax, 0, _'
- 'CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags'
- 'JNE_1 %bb.2.entry, implicit %eflags'
- id: 1
name: entry
liveins: [ '%eax' ]
instructions:
- '%rsp = ADD64ri32 %rsp, 520, implicit-def %eflags'
- 'RETQ %eax'
- id: 2
name: entry
instructions:
# CHECK: CALL64pcrel32 $__stack_chk_fail,
# CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail.09-_,
# CHECK-NEXT: CALL64pcrel32 $"__stack_chk_fail$",
# CHECK-NEXT: CALL64pcrel32 $"$Quoted \09 External symbol \11 ",
# CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail + 2,
# CHECK-NEXT: CALL64pcrel32 $" check stack - 20" - 20,
- 'CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp'
- 'CALL64pcrel32 $__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp'
- 'CALL64pcrel32 $__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp'
- 'CALL64pcrel32 $"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp'
- 'CALL64pcrel32 $__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp'
- 'CALL64pcrel32 $" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp'
body: |
bb.0.entry:
successors: %bb.1.entry, %bb.2.entry
liveins: %edi

%rsp = SUB64ri32 %rsp, 520, implicit-def %eflags
%rcx = LOAD_STACK_GUARD
MOV64mr %rsp, 1, _, 512, _, %rcx
%rax = MOVSX64rr32 %edi
%eax = MOV32rm %rsp, 4, %rax, 0, _
CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags
JNE_1 %bb.2.entry, implicit %eflags

bb.1.entry:
liveins: %eax

%rsp = ADD64ri32 %rsp, 520, implicit-def %eflags
RETQ %eax

bb.2.entry:
; CHECK: CALL64pcrel32 $__stack_chk_fail,
; CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail.09-_,
; CHECK-NEXT: CALL64pcrel32 $"__stack_chk_fail$",
; CHECK-NEXT: CALL64pcrel32 $"$Quoted \09 External symbol \11 ",
; CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail + 2,
; CHECK-NEXT: CALL64pcrel32 $" check stack - 20" - 20,
CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp
CALL64pcrel32 $__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp
CALL64pcrel32 $__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp
CALL64pcrel32 $"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp
CALL64pcrel32 $__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp
CALL64pcrel32 $" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp
...
22 changes: 10 additions & 12 deletions llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,16 +26,14 @@ fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true }
stack:
- { id: 0, name: b, offset: -8, size: 4, alignment: 4 }
body:
- id: 0
name: entry
instructions:
- 'frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp'
- CFI_INSTRUCTION .cfi_def_cfa_offset 8
# CHECK: name: test
# CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
- '%eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)'
- 'MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)'
- '%edx = POP32r implicit-def %esp, implicit %esp'
- 'RETL %eax'
body: |
bb.0.entry:
frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp
CFI_INSTRUCTION .cfi_def_cfa_offset 8
; CHECK: name: test
; CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
%eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)
%edx = POP32r implicit-def %esp, implicit %esp
RETL %eax
...
12 changes: 5 additions & 7 deletions llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,11 +20,9 @@ fixedStack:
- { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
# CHECK: [[@LINE+1]]:11: redefinition of fixed stack object '%fixed-stack.0'
- { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
body:
- id: 0
name: entry
instructions:
- '%eax = MOV32rm %esp, 1, _, 4, _'
- '%eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags'
- 'RETL %eax'
body: |
bb.0.entry:
%eax = MOV32rm %esp, 1, _, 4, _
%eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags
RETL %eax
...
12 changes: 5 additions & 7 deletions llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,11 +25,9 @@ fixedStack:
- { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
stack:
- { id: 0, offset: -8, size: 4, alignment: 4 }
body:
- id: 0
name: entry
instructions:
- '%eax = MOV32rm %esp, 1, _, 8, _'
- 'MOV32mr %esp, 1, _, 0, _, %eax'
- 'RETL %eax'
body: |
bb.0.entry:
%eax = MOV32rm %esp, 1, _, 8, _
MOV32mr %esp, 1, _, 0, _, %eax
RETL %eax
...
59 changes: 30 additions & 29 deletions llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,33 +40,34 @@ frameInfo:
restorePoint: '%bb.2.true'
stack:
- { id: 0, name: tmp, offset: 0, size: 4, alignment: 4 }
body:
- id: 0
successors: [ '%bb.2.true', '%bb.1' ]
liveins: [ '%edi', '%esi' ]
instructions:
- '%eax = COPY %edi'
- 'CMP32rr %eax, killed %esi, implicit-def %eflags'
- 'JL_1 %bb.2.true, implicit killed %eflags'
- id: 1
successors: [ '%bb.3.false' ]
liveins: [ '%eax' ]
instructions:
- 'JMP_1 %bb.3.false'
- id: 2
name: 'true'
successors: [ '%bb.3.false' ]
liveins: [ '%eax' ]
instructions:
- 'MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax'
- 'ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp'
- '%rsi = LEA64r %stack.0.tmp, 1, _, 0, _'
- '%edi = MOV32r0 implicit-def dead %eflags'
- 'CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax'
- 'ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp'
- id: 3
name: 'false'
liveins: [ '%eax' ]
instructions:
- 'RETQ %eax'
body: |
bb.0:
successors: %bb.2.true, %bb.1
liveins: %edi, %esi

%eax = COPY %edi
CMP32rr %eax, killed %esi, implicit-def %eflags
JL_1 %bb.2.true, implicit killed %eflags

bb.1:
successors: %bb.3.false
liveins: %eax

JMP_1 %bb.3.false

bb.2.true:
successors: %bb.3.false
liveins: %eax

MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax
ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp
%rsi = LEA64r %stack.0.tmp, 1, _, 0, _
%edi = MOV32r0 implicit-def dead %eflags
CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax
ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp

bb.3.false:
liveins: %eax

RETQ %eax
...
26 changes: 11 additions & 15 deletions llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,22 +18,18 @@
...
---
name: compute
body:
- name: body
id: 0
instructions:
- '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'
- 'RETQ %eax'
body: |
bb.0.body:
%eax = IMUL32rri8 %edi, 11, implicit-def %eflags
RETQ %eax
...
---
name: foo
body:
- name: entry
id: 0
instructions:
# CHECK: frame-setup PUSH64r %rax
- 'frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp'
- 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
- '%rdx = POP64r implicit-def %rsp, implicit %rsp'
- 'RETQ %eax'
body: |
bb.0.entry:
; CHECK: frame-setup PUSH64r %rax
frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp
CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
%rdx = POP64r implicit-def %rsp, implicit %rsp
RETQ %eax
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19 changes: 9 additions & 10 deletions llvm/test/CodeGen/MIR/X86/function-liveins.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,14 +25,13 @@ registers:
liveins:
- { reg: '%edi', virtual-reg: '%0' }
- { reg: '%esi', virtual-reg: '%1' }
body:
- id: 0
name: body
liveins: [ '%edi', '%esi' ]
instructions:
- '%1 = COPY %esi'
- '%0 = COPY %edi'
- '%2 = ADD32rr %0, %1, implicit-def dead %eflags'
- '%eax = COPY %2'
- 'RETQ %eax'
body: |
bb.0.body:
liveins: %edi, %esi

%1 = COPY %esi
%0 = COPY %edi
%2 = ADD32rr %0, %1, implicit-def dead %eflags
%eax = COPY %2
RETQ %eax
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