48 changes: 0 additions & 48 deletions llvm/test/CodeGen/RISCV/select-or.ll
View file
Original file line number Diff line number Diff line change
@@ -1,12 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IBT %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IBT %s

;; There are a few different ways to lower (select (or A, B), X, Y). This test
;; ensures that we do so with as few branches as possible.
Expand All @@ -22,12 +18,6 @@ define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: ret
;
; RV32IBT-LABEL: select_of_or:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: or a0, a0, a1
; RV32IBT-NEXT: cmov a0, a0, a2, a3
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: select_of_or:
; RV64I: # %bb.0:
; RV64I-NEXT: or a1, a0, a1
Expand All @@ -37,12 +27,6 @@ define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i
; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret
;
; RV64IBT-LABEL: select_of_or:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: or a0, a0, a1
; RV64IBT-NEXT: cmov a0, a0, a2, a3
; RV64IBT-NEXT: ret
%1 = or i1 %a, %b
%2 = select i1 %1, i32 %c, i32 %d
ret i32 %2
Expand All @@ -68,22 +52,6 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IBT-LABEL: if_of_or:
; RV32IBT: # %bb.0:
; RV32IBT-NEXT: addi sp, sp, -16
; RV32IBT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IBT-NEXT: or a0, a0, a1
; RV32IBT-NEXT: beqz a0, .LBB1_2
; RV32IBT-NEXT: # %bb.1: # %if.then
; RV32IBT-NEXT: call either@plt
; RV32IBT-NEXT: j .LBB1_3
; RV32IBT-NEXT: .LBB1_2: # %if.else
; RV32IBT-NEXT: call neither@plt
; RV32IBT-NEXT: .LBB1_3: # %if.end
; RV32IBT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IBT-NEXT: addi sp, sp, 16
; RV32IBT-NEXT: ret
;
; RV64I-LABEL: if_of_or:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
Expand All @@ -99,22 +67,6 @@ define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IBT-LABEL: if_of_or:
; RV64IBT: # %bb.0:
; RV64IBT-NEXT: addi sp, sp, -16
; RV64IBT-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IBT-NEXT: or a0, a0, a1
; RV64IBT-NEXT: beqz a0, .LBB1_2
; RV64IBT-NEXT: # %bb.1: # %if.then
; RV64IBT-NEXT: call either@plt
; RV64IBT-NEXT: j .LBB1_3
; RV64IBT-NEXT: .LBB1_2: # %if.else
; RV64IBT-NEXT: call neither@plt
; RV64IBT-NEXT: .LBB1_3: # %if.end
; RV64IBT-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IBT-NEXT: addi sp, sp, 16
; RV64IBT-NEXT: ret
%1 = or i1 %a, %b
br i1 %1, label %if.then, label %if.else

Expand Down
142 changes: 49 additions & 93 deletions llvm/test/CodeGen/RISCV/ssub_sat.ll
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32NoZbt,RV32I
; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64NoZbt,RV64I
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV32NoZbt,RV32IZbb
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV64NoZbt,RV64IZbb
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32,RV32I
; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64,RV64I
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV32,RV32IZbb
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV64,RV64IZbb

declare i4 @llvm.ssub.sat.i4(i4, i4)
declare i8 @llvm.ssub.sat.i8(i8, i8)
Expand All @@ -13,19 +11,19 @@ declare i32 @llvm.ssub.sat.i32(i32, i32)
declare i64 @llvm.ssub.sat.i64(i64, i64)

define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
; RV32NoZbt-LABEL: func:
; RV32NoZbt: # %bb.0:
; RV32NoZbt-NEXT: mv a2, a0
; RV32NoZbt-NEXT: sgtz a3, a1
; RV32NoZbt-NEXT: sub a0, a0, a1
; RV32NoZbt-NEXT: slt a1, a0, a2
; RV32NoZbt-NEXT: beq a3, a1, .LBB0_2
; RV32NoZbt-NEXT: # %bb.1:
; RV32NoZbt-NEXT: srai a0, a0, 31
; RV32NoZbt-NEXT: lui a1, 524288
; RV32NoZbt-NEXT: xor a0, a0, a1
; RV32NoZbt-NEXT: .LBB0_2:
; RV32NoZbt-NEXT: ret
; RV32-LABEL: func:
; RV32: # %bb.0:
; RV32-NEXT: mv a2, a0
; RV32-NEXT: sgtz a3, a1
; RV32-NEXT: sub a0, a0, a1
; RV32-NEXT: slt a1, a0, a2
; RV32-NEXT: beq a3, a1, .LBB0_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: srai a0, a0, 31
; RV32-NEXT: lui a1, 524288
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: .LBB0_2:
; RV32-NEXT: ret
;
; RV64I-LABEL: func:
; RV64I: # %bb.0:
Expand All @@ -52,86 +50,44 @@ define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
; RV64IZbb-NEXT: min a0, a0, a2
; RV64IZbb-NEXT: max a0, a0, a1
; RV64IZbb-NEXT: ret
;
; RV32IZbbZbt-LABEL: func:
; RV32IZbbZbt: # %bb.0:
; RV32IZbbZbt-NEXT: sgtz a2, a1
; RV32IZbbZbt-NEXT: sub a1, a0, a1
; RV32IZbbZbt-NEXT: slt a0, a1, a0
; RV32IZbbZbt-NEXT: xor a0, a2, a0
; RV32IZbbZbt-NEXT: srai a2, a1, 31
; RV32IZbbZbt-NEXT: lui a3, 524288
; RV32IZbbZbt-NEXT: xor a2, a2, a3
; RV32IZbbZbt-NEXT: cmov a0, a0, a2, a1
; RV32IZbbZbt-NEXT: ret
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
ret i32 %tmp;
}

define i64 @func2(i64 %x, i64 %y) nounwind {
; RV32NoZbt-LABEL: func2:
; RV32NoZbt: # %bb.0:
; RV32NoZbt-NEXT: mv a4, a1
; RV32NoZbt-NEXT: sltu a1, a0, a2
; RV32NoZbt-NEXT: sub a5, a4, a3
; RV32NoZbt-NEXT: sub a1, a5, a1
; RV32NoZbt-NEXT: xor a5, a4, a1
; RV32NoZbt-NEXT: xor a3, a4, a3
; RV32NoZbt-NEXT: and a3, a3, a5
; RV32NoZbt-NEXT: bltz a3, .LBB1_2
; RV32NoZbt-NEXT: # %bb.1:
; RV32NoZbt-NEXT: sub a0, a0, a2
; RV32NoZbt-NEXT: ret
; RV32NoZbt-NEXT: .LBB1_2:
; RV32NoZbt-NEXT: srai a0, a1, 31
; RV32NoZbt-NEXT: lui a1, 524288
; RV32NoZbt-NEXT: xor a1, a0, a1
; RV32NoZbt-NEXT: ret
;
; RV64NoZbt-LABEL: func2:
; RV64NoZbt: # %bb.0:
; RV64NoZbt-NEXT: mv a2, a0
; RV64NoZbt-NEXT: sgtz a3, a1
; RV64NoZbt-NEXT: sub a0, a0, a1
; RV64NoZbt-NEXT: slt a1, a0, a2
; RV64NoZbt-NEXT: beq a3, a1, .LBB1_2
; RV64NoZbt-NEXT: # %bb.1:
; RV64NoZbt-NEXT: srai a0, a0, 63
; RV64NoZbt-NEXT: li a1, -1
; RV64NoZbt-NEXT: slli a1, a1, 63
; RV64NoZbt-NEXT: xor a0, a0, a1
; RV64NoZbt-NEXT: .LBB1_2:
; RV64NoZbt-NEXT: ret
;
; RV32IZbbZbt-LABEL: func2:
; RV32IZbbZbt: # %bb.0:
; RV32IZbbZbt-NEXT: sltu a4, a0, a2
; RV32IZbbZbt-NEXT: sub a5, a1, a3
; RV32IZbbZbt-NEXT: sub a4, a5, a4
; RV32IZbbZbt-NEXT: srai a5, a4, 31
; RV32IZbbZbt-NEXT: lui a6, 524288
; RV32IZbbZbt-NEXT: xor a6, a5, a6
; RV32IZbbZbt-NEXT: xor a7, a1, a4
; RV32IZbbZbt-NEXT: xor a1, a1, a3
; RV32IZbbZbt-NEXT: and a1, a1, a7
; RV32IZbbZbt-NEXT: slti a3, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a3, a6, a4
; RV32IZbbZbt-NEXT: sub a0, a0, a2
; RV32IZbbZbt-NEXT: cmov a0, a3, a5, a0
; RV32IZbbZbt-NEXT: ret
; RV32-LABEL: func2:
; RV32: # %bb.0:
; RV32-NEXT: mv a4, a1
; RV32-NEXT: sltu a1, a0, a2
; RV32-NEXT: sub a5, a4, a3
; RV32-NEXT: sub a1, a5, a1
; RV32-NEXT: xor a5, a4, a1
; RV32-NEXT: xor a3, a4, a3
; RV32-NEXT: and a3, a3, a5
; RV32-NEXT: bltz a3, .LBB1_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: sub a0, a0, a2
; RV32-NEXT: ret
; RV32-NEXT: .LBB1_2:
; RV32-NEXT: srai a0, a1, 31
; RV32-NEXT: lui a1, 524288
; RV32-NEXT: xor a1, a0, a1
; RV32-NEXT: ret
;
; RV64IZbbZbt-LABEL: func2:
; RV64IZbbZbt: # %bb.0:
; RV64IZbbZbt-NEXT: sgtz a2, a1
; RV64IZbbZbt-NEXT: sub a1, a0, a1
; RV64IZbbZbt-NEXT: slt a0, a1, a0
; RV64IZbbZbt-NEXT: xor a0, a2, a0
; RV64IZbbZbt-NEXT: srai a2, a1, 63
; RV64IZbbZbt-NEXT: li a3, -1
; RV64IZbbZbt-NEXT: slli a3, a3, 63
; RV64IZbbZbt-NEXT: xor a2, a2, a3
; RV64IZbbZbt-NEXT: cmov a0, a0, a2, a1
; RV64IZbbZbt-NEXT: ret
; RV64-LABEL: func2:
; RV64: # %bb.0:
; RV64-NEXT: mv a2, a0
; RV64-NEXT: sgtz a3, a1
; RV64-NEXT: sub a0, a0, a1
; RV64-NEXT: slt a1, a0, a2
; RV64-NEXT: beq a3, a1, .LBB1_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: li a1, -1
; RV64-NEXT: slli a1, a1, 63
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: .LBB1_2:
; RV64-NEXT: ret
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
ret i64 %tmp;
}
Expand Down
145 changes: 50 additions & 95 deletions llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32NoZbt,RV32I
; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64NoZbt,RV64I
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV32NoZbt,RV32IZbb
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV64NoZbt,RV64IZbb
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV32IZbb,RV32IZbbZbt
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb,+experimental-zbt | FileCheck %s --check-prefixes=RV64IZbb,RV64IZbbZbt
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32,RV32I
; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64,RV64I
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV32,RV32IZbb
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb | FileCheck %s --check-prefixes=RV64,RV64IZbb

declare i4 @llvm.ssub.sat.i4(i4, i4)
declare i8 @llvm.ssub.sat.i8(i8, i8)
Expand All @@ -13,20 +11,20 @@ declare i32 @llvm.ssub.sat.i32(i32, i32)
declare i64 @llvm.ssub.sat.i64(i64, i64)

define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
; RV32NoZbt-LABEL: func32:
; RV32NoZbt: # %bb.0:
; RV32NoZbt-NEXT: mv a3, a0
; RV32NoZbt-NEXT: mul a0, a1, a2
; RV32NoZbt-NEXT: sgtz a1, a0
; RV32NoZbt-NEXT: sub a0, a3, a0
; RV32NoZbt-NEXT: slt a2, a0, a3
; RV32NoZbt-NEXT: beq a1, a2, .LBB0_2
; RV32NoZbt-NEXT: # %bb.1:
; RV32NoZbt-NEXT: srai a0, a0, 31
; RV32NoZbt-NEXT: lui a1, 524288
; RV32NoZbt-NEXT: xor a0, a0, a1
; RV32NoZbt-NEXT: .LBB0_2:
; RV32NoZbt-NEXT: ret
; RV32-LABEL: func32:
; RV32: # %bb.0:
; RV32-NEXT: mv a3, a0
; RV32-NEXT: mul a0, a1, a2
; RV32-NEXT: sgtz a1, a0
; RV32-NEXT: sub a0, a3, a0
; RV32-NEXT: slt a2, a0, a3
; RV32-NEXT: beq a1, a2, .LBB0_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: srai a0, a0, 31
; RV32-NEXT: lui a1, 524288
; RV32-NEXT: xor a0, a0, a1
; RV32-NEXT: .LBB0_2:
; RV32-NEXT: ret
;
; RV64I-LABEL: func32:
; RV64I: # %bb.0:
Expand Down Expand Up @@ -57,88 +55,45 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
; RV64IZbb-NEXT: min a0, a0, a2
; RV64IZbb-NEXT: max a0, a0, a1
; RV64IZbb-NEXT: ret
;
; RV32IZbbZbt-LABEL: func32:
; RV32IZbbZbt: # %bb.0:
; RV32IZbbZbt-NEXT: mul a1, a1, a2
; RV32IZbbZbt-NEXT: sgtz a2, a1
; RV32IZbbZbt-NEXT: sub a1, a0, a1
; RV32IZbbZbt-NEXT: slt a0, a1, a0
; RV32IZbbZbt-NEXT: xor a0, a2, a0
; RV32IZbbZbt-NEXT: srai a2, a1, 31
; RV32IZbbZbt-NEXT: lui a3, 524288
; RV32IZbbZbt-NEXT: xor a2, a2, a3
; RV32IZbbZbt-NEXT: cmov a0, a0, a2, a1
; RV32IZbbZbt-NEXT: ret
%a = mul i32 %y, %z
%tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
ret i32 %tmp
}

define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; RV32NoZbt-LABEL: func64:
; RV32NoZbt: # %bb.0:
; RV32NoZbt-NEXT: mv a2, a1
; RV32NoZbt-NEXT: sltu a1, a0, a4
; RV32NoZbt-NEXT: sub a3, a2, a5
; RV32NoZbt-NEXT: sub a1, a3, a1
; RV32NoZbt-NEXT: xor a3, a2, a1
; RV32NoZbt-NEXT: xor a2, a2, a5
; RV32NoZbt-NEXT: and a2, a2, a3
; RV32NoZbt-NEXT: bltz a2, .LBB1_2
; RV32NoZbt-NEXT: # %bb.1:
; RV32NoZbt-NEXT: sub a0, a0, a4
; RV32NoZbt-NEXT: ret
; RV32NoZbt-NEXT: .LBB1_2:
; RV32NoZbt-NEXT: srai a0, a1, 31
; RV32NoZbt-NEXT: lui a1, 524288
; RV32NoZbt-NEXT: xor a1, a0, a1
; RV32NoZbt-NEXT: ret
;
; RV64NoZbt-LABEL: func64:
; RV64NoZbt: # %bb.0:
; RV64NoZbt-NEXT: mv a1, a0
; RV64NoZbt-NEXT: sgtz a3, a2
; RV64NoZbt-NEXT: sub a0, a0, a2
; RV64NoZbt-NEXT: slt a1, a0, a1
; RV64NoZbt-NEXT: beq a3, a1, .LBB1_2
; RV64NoZbt-NEXT: # %bb.1:
; RV64NoZbt-NEXT: srai a0, a0, 63
; RV64NoZbt-NEXT: li a1, -1
; RV64NoZbt-NEXT: slli a1, a1, 63
; RV64NoZbt-NEXT: xor a0, a0, a1
; RV64NoZbt-NEXT: .LBB1_2:
; RV64NoZbt-NEXT: ret
;
; RV32IZbbZbt-LABEL: func64:
; RV32IZbbZbt: # %bb.0:
; RV32IZbbZbt-NEXT: sltu a2, a0, a4
; RV32IZbbZbt-NEXT: sub a3, a1, a5
; RV32IZbbZbt-NEXT: sub a2, a3, a2
; RV32IZbbZbt-NEXT: srai a3, a2, 31
; RV32IZbbZbt-NEXT: lui a6, 524288
; RV32IZbbZbt-NEXT: xor a6, a3, a6
; RV32IZbbZbt-NEXT: xor a7, a1, a2
; RV32IZbbZbt-NEXT: xor a1, a1, a5
; RV32IZbbZbt-NEXT: and a1, a1, a7
; RV32IZbbZbt-NEXT: slti a5, a1, 0
; RV32IZbbZbt-NEXT: cmov a1, a5, a6, a2
; RV32IZbbZbt-NEXT: sub a0, a0, a4
; RV32IZbbZbt-NEXT: cmov a0, a5, a3, a0
; RV32IZbbZbt-NEXT: ret
; RV32-LABEL: func64:
; RV32: # %bb.0:
; RV32-NEXT: mv a2, a1
; RV32-NEXT: sltu a1, a0, a4
; RV32-NEXT: sub a3, a2, a5
; RV32-NEXT: sub a1, a3, a1
; RV32-NEXT: xor a3, a2, a1
; RV32-NEXT: xor a2, a2, a5
; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: bltz a2, .LBB1_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: sub a0, a0, a4
; RV32-NEXT: ret
; RV32-NEXT: .LBB1_2:
; RV32-NEXT: srai a0, a1, 31
; RV32-NEXT: lui a1, 524288
; RV32-NEXT: xor a1, a0, a1
; RV32-NEXT: ret
;
; RV64IZbbZbt-LABEL: func64:
; RV64IZbbZbt: # %bb.0:
; RV64IZbbZbt-NEXT: sgtz a1, a2
; RV64IZbbZbt-NEXT: sub a2, a0, a2
; RV64IZbbZbt-NEXT: slt a0, a2, a0
; RV64IZbbZbt-NEXT: xor a0, a1, a0
; RV64IZbbZbt-NEXT: srai a1, a2, 63
; RV64IZbbZbt-NEXT: li a3, -1
; RV64IZbbZbt-NEXT: slli a3, a3, 63
; RV64IZbbZbt-NEXT: xor a1, a1, a3
; RV64IZbbZbt-NEXT: cmov a0, a0, a1, a2
; RV64IZbbZbt-NEXT: ret
; RV64-LABEL: func64:
; RV64: # %bb.0:
; RV64-NEXT: mv a1, a0
; RV64-NEXT: sgtz a3, a2
; RV64-NEXT: sub a0, a0, a2
; RV64-NEXT: slt a1, a0, a1
; RV64-NEXT: beq a3, a1, .LBB1_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: li a1, -1
; RV64-NEXT: slli a1, a1, 63
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: .LBB1_2:
; RV64-NEXT: ret
%a = mul i64 %y, %z
%tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
ret i64 %tmp
Expand Down
18 changes: 0 additions & 18 deletions llvm/test/MC/RISCV/rv32zbt-invalid.s
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22 changes: 0 additions & 22 deletions llvm/test/MC/RISCV/rv32zbt-valid.s
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