266 changes: 140 additions & 126 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
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254 changes: 136 additions & 118 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
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178 changes: 94 additions & 84 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -11,24 +11,26 @@ body: |
; GFX6-LABEL: name: narrow_shl_s32_by_2_from_zext_s16
; GFX6: liveins: $vgpr0
; GFX6: %argument:_(s32) = COPY $vgpr0
; GFX6: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX6: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX6: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX6: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX6: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX6: %shl:_(s32) = G_ZEXT [[SHL]](s16)
; GFX6: $vgpr0 = COPY %shl(s32)
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: %argument:_(s32) = COPY $vgpr0
; GFX6-NEXT: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX6-NEXT: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX6-NEXT: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX6-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX6-NEXT: %shl:_(s32) = G_ZEXT [[SHL]](s16)
; GFX6-NEXT: $vgpr0 = COPY %shl(s32)
; GFX9-LABEL: name: narrow_shl_s32_by_2_from_zext_s16
; GFX9: liveins: $vgpr0
; GFX9: %argument:_(s32) = COPY $vgpr0
; GFX9: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX9: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX9: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX9: %shl:_(s32) = G_ZEXT [[SHL]](s16)
; GFX9: $vgpr0 = COPY %shl(s32)
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: %argument:_(s32) = COPY $vgpr0
; GFX9-NEXT: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX9-NEXT: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX9-NEXT: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX9-NEXT: %shl:_(s32) = G_ZEXT [[SHL]](s16)
; GFX9-NEXT: $vgpr0 = COPY %shl(s32)
%argument:_(s32) = COPY $vgpr0
%narrow:_(s16) = G_TRUNC %argument
%masklow14:_(s16) = G_CONSTANT i16 16383
Expand All @@ -48,24 +50,26 @@ body: |
; GFX6-LABEL: name: narrow_shl_s64_by_2_from_zext_s16
; GFX6: liveins: $vgpr0
; GFX6: %argument:_(s32) = COPY $vgpr0
; GFX6: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX6: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX6: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX6: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX6: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX6: %shl:_(s64) = G_ZEXT [[SHL]](s16)
; GFX6: $vgpr0_vgpr1 = COPY %shl(s64)
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: %argument:_(s32) = COPY $vgpr0
; GFX6-NEXT: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX6-NEXT: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX6-NEXT: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX6-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX6-NEXT: %shl:_(s64) = G_ZEXT [[SHL]](s16)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY %shl(s64)
; GFX9-LABEL: name: narrow_shl_s64_by_2_from_zext_s16
; GFX9: liveins: $vgpr0
; GFX9: %argument:_(s32) = COPY $vgpr0
; GFX9: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX9: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX9: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX9: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX9: %shl:_(s64) = G_ZEXT [[SHL]](s16)
; GFX9: $vgpr0_vgpr1 = COPY %shl(s64)
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: %argument:_(s32) = COPY $vgpr0
; GFX9-NEXT: %narrow:_(s16) = G_TRUNC %argument(s32)
; GFX9-NEXT: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX9-NEXT: %masked:_(s16) = G_AND %narrow, %masklow14
; GFX9-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s16) = G_SHL %masked, [[C]](s16)
; GFX9-NEXT: %shl:_(s64) = G_ZEXT [[SHL]](s16)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY %shl(s64)
%argument:_(s32) = COPY $vgpr0
%narrow:_(s16) = G_TRUNC %argument
%masklow14:_(s16) = G_CONSTANT i16 16383
Expand All @@ -85,24 +89,26 @@ body: |
; GFX6-LABEL: name: narrow_shl_s16_by_2_from_zext_s8
; GFX6: liveins: $vgpr0
; GFX6: %argument:_(s32) = COPY $vgpr0
; GFX6: %narrow:_(s8) = G_TRUNC %argument(s32)
; GFX6: %masklow6:_(s8) = G_CONSTANT i8 63
; GFX6: %masked:_(s8) = G_AND %narrow, %masklow6
; GFX6: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; GFX6: [[SHL:%[0-9]+]]:_(s8) = G_SHL %masked, [[C]](s8)
; GFX6: %result:_(s32) = G_ZEXT [[SHL]](s8)
; GFX6: $vgpr0 = COPY %result(s32)
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: %argument:_(s32) = COPY $vgpr0
; GFX6-NEXT: %narrow:_(s8) = G_TRUNC %argument(s32)
; GFX6-NEXT: %masklow6:_(s8) = G_CONSTANT i8 63
; GFX6-NEXT: %masked:_(s8) = G_AND %narrow, %masklow6
; GFX6-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; GFX6-NEXT: [[SHL:%[0-9]+]]:_(s8) = G_SHL %masked, [[C]](s8)
; GFX6-NEXT: %result:_(s32) = G_ZEXT [[SHL]](s8)
; GFX6-NEXT: $vgpr0 = COPY %result(s32)
; GFX9-LABEL: name: narrow_shl_s16_by_2_from_zext_s8
; GFX9: liveins: $vgpr0
; GFX9: %argument:_(s32) = COPY $vgpr0
; GFX9: %narrow:_(s8) = G_TRUNC %argument(s32)
; GFX9: %masklow6:_(s8) = G_CONSTANT i8 63
; GFX9: %masked:_(s8) = G_AND %narrow, %masklow6
; GFX9: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; GFX9: [[SHL:%[0-9]+]]:_(s8) = G_SHL %masked, [[C]](s8)
; GFX9: %result:_(s32) = G_ZEXT [[SHL]](s8)
; GFX9: $vgpr0 = COPY %result(s32)
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: %argument:_(s32) = COPY $vgpr0
; GFX9-NEXT: %narrow:_(s8) = G_TRUNC %argument(s32)
; GFX9-NEXT: %masklow6:_(s8) = G_CONSTANT i8 63
; GFX9-NEXT: %masked:_(s8) = G_AND %narrow, %masklow6
; GFX9-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; GFX9-NEXT: [[SHL:%[0-9]+]]:_(s8) = G_SHL %masked, [[C]](s8)
; GFX9-NEXT: %result:_(s32) = G_ZEXT [[SHL]](s8)
; GFX9-NEXT: $vgpr0 = COPY %result(s32)
%argument:_(s32) = COPY $vgpr0
%narrow:_(s8) = G_TRUNC %argument
%masklow6:_(s8) = G_CONSTANT i8 63
Expand All @@ -123,26 +129,28 @@ body: |
; GFX6-LABEL: name: narrow_shl_v2s32_by_2_from_zext_v2s16
; GFX6: liveins: $vgpr0
; GFX6: %narrow:_(<2 x s16>) = COPY $vgpr0
; GFX6: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX6: %masklow14vec:_(<2 x s16>) = G_BUILD_VECTOR %masklow14(s16), %masklow14(s16)
; GFX6: %masked:_(<2 x s16>) = G_AND %narrow, %masklow14vec
; GFX6: %extend:_(<2 x s32>) = G_ZEXT %masked(<2 x s16>)
; GFX6: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX6: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX6: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: %narrow:_(<2 x s16>) = COPY $vgpr0
; GFX6-NEXT: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX6-NEXT: %masklow14vec:_(<2 x s16>) = G_BUILD_VECTOR %masklow14(s16), %masklow14(s16)
; GFX6-NEXT: %masked:_(<2 x s16>) = G_AND %narrow, %masklow14vec
; GFX6-NEXT: %extend:_(<2 x s32>) = G_ZEXT %masked(<2 x s16>)
; GFX6-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX6-NEXT: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX6-NEXT: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX6-NEXT: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
; GFX9-LABEL: name: narrow_shl_v2s32_by_2_from_zext_v2s16
; GFX9: liveins: $vgpr0
; GFX9: %narrow:_(<2 x s16>) = COPY $vgpr0
; GFX9: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX9: %masklow14vec:_(<2 x s16>) = G_BUILD_VECTOR %masklow14(s16), %masklow14(s16)
; GFX9: %masked:_(<2 x s16>) = G_AND %narrow, %masklow14vec
; GFX9: %extend:_(<2 x s32>) = G_ZEXT %masked(<2 x s16>)
; GFX9: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX9: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX9: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: %narrow:_(<2 x s16>) = COPY $vgpr0
; GFX9-NEXT: %masklow14:_(s16) = G_CONSTANT i16 16383
; GFX9-NEXT: %masklow14vec:_(<2 x s16>) = G_BUILD_VECTOR %masklow14(s16), %masklow14(s16)
; GFX9-NEXT: %masked:_(<2 x s16>) = G_AND %narrow, %masklow14vec
; GFX9-NEXT: %extend:_(<2 x s32>) = G_ZEXT %masked(<2 x s16>)
; GFX9-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX9-NEXT: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX9-NEXT: %shl:_(<2 x s32>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1 = COPY %shl(<2 x s32>)
%narrow:_(<2 x s16>) = COPY $vgpr0
%masklow14:_(s16) = G_CONSTANT i16 16383
%masklow14vec:_(<2 x s16>) = G_BUILD_VECTOR %masklow14, %masklow14
Expand All @@ -163,26 +171,28 @@ body: |
; GFX6-LABEL: name: narrow_shl_v2s64_by_2_from_anyext_v2s32
; GFX6: liveins: $vgpr0_vgpr1
; GFX6: %narrow:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX6: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX6: %masklow30vec:_(<2 x s32>) = G_BUILD_VECTOR %masklow30(s32), %masklow30(s32)
; GFX6: %masked:_(<2 x s32>) = G_AND %narrow, %masklow30vec
; GFX6: %extend:_(<2 x s64>) = G_ANYEXT %masked(<2 x s32>)
; GFX6: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX6: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX6: %shl:_(<2 x s64>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX6: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %shl(<2 x s64>)
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: %narrow:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX6-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX6-NEXT: %masklow30vec:_(<2 x s32>) = G_BUILD_VECTOR %masklow30(s32), %masklow30(s32)
; GFX6-NEXT: %masked:_(<2 x s32>) = G_AND %narrow, %masklow30vec
; GFX6-NEXT: %extend:_(<2 x s64>) = G_ANYEXT %masked(<2 x s32>)
; GFX6-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX6-NEXT: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX6-NEXT: %shl:_(<2 x s64>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX6-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %shl(<2 x s64>)
; GFX9-LABEL: name: narrow_shl_v2s64_by_2_from_anyext_v2s32
; GFX9: liveins: $vgpr0_vgpr1
; GFX9: %narrow:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX9: %masklow30vec:_(<2 x s32>) = G_BUILD_VECTOR %masklow30(s32), %masklow30(s32)
; GFX9: %masked:_(<2 x s32>) = G_AND %narrow, %masklow30vec
; GFX9: %extend:_(<2 x s64>) = G_ANYEXT %masked(<2 x s32>)
; GFX9: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX9: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX9: %shl:_(<2 x s64>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %shl(<2 x s64>)
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: %narrow:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GFX9-NEXT: %masklow30:_(s32) = G_CONSTANT i32 1073741823
; GFX9-NEXT: %masklow30vec:_(<2 x s32>) = G_BUILD_VECTOR %masklow30(s32), %masklow30(s32)
; GFX9-NEXT: %masked:_(<2 x s32>) = G_AND %narrow, %masklow30vec
; GFX9-NEXT: %extend:_(<2 x s64>) = G_ANYEXT %masked(<2 x s32>)
; GFX9-NEXT: %shiftamt:_(s32) = G_CONSTANT i32 2
; GFX9-NEXT: %shiftamtvec:_(<2 x s32>) = G_BUILD_VECTOR %shiftamt(s32), %shiftamt(s32)
; GFX9-NEXT: %shl:_(<2 x s64>) = G_SHL %extend, %shiftamtvec(<2 x s32>)
; GFX9-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %shl(<2 x s64>)
%narrow:_(<2 x s32>) = COPY $vgpr0_vgpr1
%masklow30:_(s32) = G_CONSTANT i32 1073741823
%masklow30vec:_(<2 x s32>) = G_BUILD_VECTOR %masklow30, %masklow30
Expand Down
108 changes: 59 additions & 49 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -11,11 +11,12 @@ body: |
; CHECK-LABEL: name: narrow_shl_s64_32_s64amt
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[TRUNC]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[TRUNC]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_CONSTANT i64 32
%2:_(s64) = G_SHL %0, %1
Expand All @@ -31,11 +32,12 @@ body: |
; CHECK-LABEL: name: narrow_shl_s64_32
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[TRUNC]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C]](s32), [[TRUNC]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 32
%2:_(s64) = G_SHL %0, %1
Expand All @@ -51,13 +53,14 @@ body: |
; CHECK-LABEL: name: narrow_shl_s64_33
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[SHL]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[SHL]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 33
%2:_(s64) = G_SHL %0, %1
Expand All @@ -73,10 +76,11 @@ body: |
; CHECK-LABEL: name: narrow_shl_s64_31
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](s64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 31
%2:_(s64) = G_SHL %0, %1
Expand All @@ -92,13 +96,14 @@ body: |
; CHECK-LABEL: name: narrow_shl_s64_63
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[SHL]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C1]](s32), [[SHL]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 63
%2:_(s64) = G_SHL %0, %1
Expand All @@ -114,10 +119,11 @@ body: |
; CHECK-LABEL: name: narrow_shl_s64_64
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](s64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 64
%2:_(s64) = G_SHL %0, %1
Expand All @@ -133,10 +139,11 @@ body: |
; CHECK-LABEL: name: narrow_shl_s64_65
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](s64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 65
%2:_(s64) = G_SHL %0, %1
Expand All @@ -152,10 +159,11 @@ body: |
; CHECK-LABEL: name: narrow_shl_s32_16
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; CHECK: $vgpr0 = COPY [[SHL]](s32)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[SHL]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 16
%2:_(s32) = G_SHL %0, %1
Expand All @@ -171,10 +179,11 @@ body: |
; CHECK-LABEL: name: narrow_shl_s32_17
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; CHECK: $vgpr0 = COPY [[SHL]](s32)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[SHL]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 17
%2:_(s32) = G_SHL %0, %1
Expand All @@ -190,11 +199,12 @@ body: |
; CHECK-LABEL: name: narrow_shl_v2s32_17
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s32>)
; CHECK: $vgpr0_vgpr1 = COPY [[SHL]](<2 x s32>)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<2 x s32>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s32>)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SHL]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 17
%2:_(<2 x s32>) = G_BUILD_VECTOR %1, %1
Expand Down
33 changes: 18 additions & 15 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shl.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,11 +11,12 @@ body: |
; CHECK-LABEL: name: trunc_s32_shl_s64_5
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
; CHECK: $vgpr0 = COPY [[SHL]](s32)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32)
; CHECK-NEXT: $vgpr0 = COPY [[SHL]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 1
%2:_(s64) = G_SHL %0:_, %1
Expand All @@ -33,11 +34,12 @@ body: |
; CHECK-LABEL: name: trunc_s16_shl_s32_5
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; CHECK-NEXT: S_ENDPGM 0, implicit [[TRUNC]](s16)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 1
%2:_(s32) = G_SHL %0:_, %1
Expand All @@ -56,11 +58,12 @@ body: |
; CHECK-LABEL: name: trunc_s16_shl_s64_5
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s64)
; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s16)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s32)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s64)
; CHECK-NEXT: S_ENDPGM 0, implicit [[TRUNC]](s16)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CONSTANT i32 1
%2:_(s64) = G_SHL %0:_, %1
Expand Down
112 changes: 60 additions & 52 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-zext-trunc.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,10 +10,11 @@ body: |
; GCN-LABEL: name: zext_trunc_s32_s16_s32
; GCN: liveins: $vgpr0
; GCN: %var:_(s32) = COPY $vgpr0
; GCN: %c3FFF:_(s32) = G_CONSTANT i32 16383
; GCN: %low_bits:_(s32) = G_AND %var, %c3FFF
; GCN: $vgpr0 = COPY %low_bits(s32)
; GCN-NEXT: {{ $}}
; GCN-NEXT: %var:_(s32) = COPY $vgpr0
; GCN-NEXT: %c3FFF:_(s32) = G_CONSTANT i32 16383
; GCN-NEXT: %low_bits:_(s32) = G_AND %var, %c3FFF
; GCN-NEXT: $vgpr0 = COPY %low_bits(s32)
%var:_(s32) = COPY $vgpr0
%c3FFF:_(s32) = G_CONSTANT i32 16383
%low_bits:_(s32) = G_AND %var, %c3FFF
Expand All @@ -31,12 +32,13 @@ body: |
; GCN-LABEL: name: zext_trunc_s32_s16_s32_unknown_high_bits
; GCN: liveins: $vgpr0
; GCN: %var:_(s32) = COPY $vgpr0
; GCN: %cFFFFF:_(s32) = G_CONSTANT i32 1048575
; GCN: %low_bits:_(s32) = G_AND %var, %cFFFFF
; GCN: %trunc:_(s16) = G_TRUNC %low_bits(s32)
; GCN: %zext:_(s32) = G_ZEXT %trunc(s16)
; GCN: $vgpr0 = COPY %zext(s32)
; GCN-NEXT: {{ $}}
; GCN-NEXT: %var:_(s32) = COPY $vgpr0
; GCN-NEXT: %cFFFFF:_(s32) = G_CONSTANT i32 1048575
; GCN-NEXT: %low_bits:_(s32) = G_AND %var, %cFFFFF
; GCN-NEXT: %trunc:_(s16) = G_TRUNC %low_bits(s32)
; GCN-NEXT: %zext:_(s32) = G_ZEXT %trunc(s16)
; GCN-NEXT: $vgpr0 = COPY %zext(s32)
%var:_(s32) = COPY $vgpr0
%cFFFFF:_(s32) = G_CONSTANT i32 1048575
%low_bits:_(s32) = G_AND %var, %cFFFFF
Expand All @@ -54,12 +56,13 @@ body: |
; GCN-LABEL: name: zext_trunc_s64_s16_s32
; GCN: liveins: $vgpr0_vgpr1
; GCN: %var:_(s64) = COPY $vgpr0_vgpr1
; GCN: %c3FFF:_(s64) = G_CONSTANT i64 16383
; GCN: %low_bits:_(s64) = G_AND %var, %c3FFF
; GCN: %trunc:_(s16) = G_TRUNC %low_bits(s64)
; GCN: %zext:_(s32) = G_ZEXT %trunc(s16)
; GCN: $vgpr0 = COPY %zext(s32)
; GCN-NEXT: {{ $}}
; GCN-NEXT: %var:_(s64) = COPY $vgpr0_vgpr1
; GCN-NEXT: %c3FFF:_(s64) = G_CONSTANT i64 16383
; GCN-NEXT: %low_bits:_(s64) = G_AND %var, %c3FFF
; GCN-NEXT: %trunc:_(s16) = G_TRUNC %low_bits(s64)
; GCN-NEXT: %zext:_(s32) = G_ZEXT %trunc(s16)
; GCN-NEXT: $vgpr0 = COPY %zext(s32)
%var:_(s64) = COPY $vgpr0_vgpr1
%c3FFF:_(s64) = G_CONSTANT i64 16383
%low_bits:_(s64) = G_AND %var, %c3FFF
Expand All @@ -77,12 +80,13 @@ body: |
; GCN-LABEL: name: zext_trunc_s32_s16_s64
; GCN: liveins: $vgpr0
; GCN: %var:_(s32) = COPY $vgpr0
; GCN: %c3FFF:_(s32) = G_CONSTANT i32 16383
; GCN: %low_bits:_(s32) = G_AND %var, %c3FFF
; GCN: %trunc:_(s16) = G_TRUNC %low_bits(s32)
; GCN: %zext:_(s64) = G_ZEXT %trunc(s16)
; GCN: $vgpr0_vgpr1 = COPY %zext(s64)
; GCN-NEXT: {{ $}}
; GCN-NEXT: %var:_(s32) = COPY $vgpr0
; GCN-NEXT: %c3FFF:_(s32) = G_CONSTANT i32 16383
; GCN-NEXT: %low_bits:_(s32) = G_AND %var, %c3FFF
; GCN-NEXT: %trunc:_(s16) = G_TRUNC %low_bits(s32)
; GCN-NEXT: %zext:_(s64) = G_ZEXT %trunc(s16)
; GCN-NEXT: $vgpr0_vgpr1 = COPY %zext(s64)
%var:_(s32) = COPY $vgpr0
%c3FFF:_(s32) = G_CONSTANT i32 16383
%low_bits:_(s32) = G_AND %var, %c3FFF
Expand All @@ -100,12 +104,13 @@ body: |
; GCN-LABEL: name: zext_trunc_v2s32_v2s16_v2s32
; GCN: liveins: $vgpr0_vgpr1
; GCN: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GCN: %c3FFF:_(s32) = G_CONSTANT i32 16383
; GCN: %c7FFF:_(s32) = G_CONSTANT i32 32767
; GCN: %c:_(<2 x s32>) = G_BUILD_VECTOR %c3FFF(s32), %c7FFF(s32)
; GCN: %low_bits:_(<2 x s32>) = G_AND %var, %c
; GCN: $vgpr0_vgpr1 = COPY %low_bits(<2 x s32>)
; GCN-NEXT: {{ $}}
; GCN-NEXT: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GCN-NEXT: %c3FFF:_(s32) = G_CONSTANT i32 16383
; GCN-NEXT: %c7FFF:_(s32) = G_CONSTANT i32 32767
; GCN-NEXT: %c:_(<2 x s32>) = G_BUILD_VECTOR %c3FFF(s32), %c7FFF(s32)
; GCN-NEXT: %low_bits:_(<2 x s32>) = G_AND %var, %c
; GCN-NEXT: $vgpr0_vgpr1 = COPY %low_bits(<2 x s32>)
%var:_(<2 x s32>) = COPY $vgpr0_vgpr1
%c3FFF:_(s32) = G_CONSTANT i32 16383
%c7FFF:_(s32) = G_CONSTANT i32 32767
Expand All @@ -125,14 +130,15 @@ body: |
; GCN-LABEL: name: zext_trunc_v2s32_v2s16_v2s32_unknown_high_bits
; GCN: liveins: $vgpr0_vgpr1
; GCN: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GCN: %cFFFFF:_(s32) = G_CONSTANT i32 1048575
; GCN: %c7FFF:_(s32) = G_CONSTANT i32 32767
; GCN: %c:_(<2 x s32>) = G_BUILD_VECTOR %cFFFFF(s32), %c7FFF(s32)
; GCN: %low_bits:_(<2 x s32>) = G_AND %var, %c
; GCN: %trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s32>)
; GCN: %zext:_(<2 x s32>) = G_ZEXT %trunc(<2 x s16>)
; GCN: $vgpr0_vgpr1 = COPY %zext(<2 x s32>)
; GCN-NEXT: {{ $}}
; GCN-NEXT: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GCN-NEXT: %cFFFFF:_(s32) = G_CONSTANT i32 1048575
; GCN-NEXT: %c7FFF:_(s32) = G_CONSTANT i32 32767
; GCN-NEXT: %c:_(<2 x s32>) = G_BUILD_VECTOR %cFFFFF(s32), %c7FFF(s32)
; GCN-NEXT: %low_bits:_(<2 x s32>) = G_AND %var, %c
; GCN-NEXT: %trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s32>)
; GCN-NEXT: %zext:_(<2 x s32>) = G_ZEXT %trunc(<2 x s16>)
; GCN-NEXT: $vgpr0_vgpr1 = COPY %zext(<2 x s32>)
%var:_(<2 x s32>) = COPY $vgpr0_vgpr1
%cFFFFF:_(s32) = G_CONSTANT i32 1048575
%c7FFF:_(s32) = G_CONSTANT i32 32767
Expand All @@ -152,14 +158,15 @@ body: |
; GCN-LABEL: name: zext_trunc_v2s64_v2s16_v2s32
; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; GCN: %var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GCN: %c3FFF:_(s64) = G_CONSTANT i64 16383
; GCN: %c7FFF:_(s64) = G_CONSTANT i64 32767
; GCN: %c:_(<2 x s64>) = G_BUILD_VECTOR %c3FFF(s64), %c7FFF(s64)
; GCN: %low_bits:_(<2 x s64>) = G_AND %var, %c
; GCN: %trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s64>)
; GCN: %zext:_(<2 x s32>) = G_ZEXT %trunc(<2 x s16>)
; GCN: $vgpr0_vgpr1 = COPY %zext(<2 x s32>)
; GCN-NEXT: {{ $}}
; GCN-NEXT: %var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; GCN-NEXT: %c3FFF:_(s64) = G_CONSTANT i64 16383
; GCN-NEXT: %c7FFF:_(s64) = G_CONSTANT i64 32767
; GCN-NEXT: %c:_(<2 x s64>) = G_BUILD_VECTOR %c3FFF(s64), %c7FFF(s64)
; GCN-NEXT: %low_bits:_(<2 x s64>) = G_AND %var, %c
; GCN-NEXT: %trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s64>)
; GCN-NEXT: %zext:_(<2 x s32>) = G_ZEXT %trunc(<2 x s16>)
; GCN-NEXT: $vgpr0_vgpr1 = COPY %zext(<2 x s32>)
%var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%c3FFF:_(s64) = G_CONSTANT i64 16383
%c7FFF:_(s64) = G_CONSTANT i64 32767
Expand All @@ -179,14 +186,15 @@ body: |
; GCN-LABEL: name: zext_trunc_v2s32_v2s16_v2s64
; GCN: liveins: $vgpr0_vgpr1
; GCN: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GCN: %c3FFF:_(s32) = G_CONSTANT i32 16383
; GCN: %c7FFF:_(s32) = G_CONSTANT i32 32767
; GCN: %c:_(<2 x s32>) = G_BUILD_VECTOR %c3FFF(s32), %c7FFF(s32)
; GCN: %low_bits:_(<2 x s32>) = G_AND %var, %c
; GCN: %trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s32>)
; GCN: %zext:_(<2 x s64>) = G_ZEXT %trunc(<2 x s16>)
; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %zext(<2 x s64>)
; GCN-NEXT: {{ $}}
; GCN-NEXT: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
; GCN-NEXT: %c3FFF:_(s32) = G_CONSTANT i32 16383
; GCN-NEXT: %c7FFF:_(s32) = G_CONSTANT i32 32767
; GCN-NEXT: %c:_(<2 x s32>) = G_BUILD_VECTOR %c3FFF(s32), %c7FFF(s32)
; GCN-NEXT: %low_bits:_(<2 x s32>) = G_AND %var, %c
; GCN-NEXT: %trunc:_(<2 x s16>) = G_TRUNC %low_bits(<2 x s32>)
; GCN-NEXT: %zext:_(<2 x s64>) = G_ZEXT %trunc(<2 x s16>)
; GCN-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %zext(<2 x s64>)
%var:_(<2 x s32>) = COPY $vgpr0_vgpr1
%c3FFF:_(s32) = G_CONSTANT i32 16383
%c7FFF:_(s32) = G_CONSTANT i32 32767
Expand Down
84 changes: 42 additions & 42 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,89 +16,89 @@
define i32 addrspace(4)* @external_constant_got() {
; GCN-LABEL: name: external_constant_got
; GCN: bb.1 (%ir-block.0):
; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant + 4, target-flags(amdgpu-gotprel32-hi) @external_constant + 12, implicit-def $scc
; GCN: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p4) from got, addrspace 4)
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p4)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: SI_RETURN implicit $vgpr0, implicit $vgpr1
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant + 4, target-flags(amdgpu-gotprel32-hi) @external_constant + 12, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p4) from got, addrspace 4)
; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p4)
; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)
; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GCN-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(4)* @external_constant
}

define i32 addrspace(1)* @external_global_got() {
; GCN-LABEL: name: external_global_got
; GCN: bb.1 (%ir-block.0):
; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_global + 4, target-flags(amdgpu-gotprel32-hi) @external_global + 12, implicit-def $scc
; GCN: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p1) from got, addrspace 4)
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: SI_RETURN implicit $vgpr0, implicit $vgpr1
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_global + 4, target-flags(amdgpu-gotprel32-hi) @external_global + 12, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p1) from got, addrspace 4)
; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p1)
; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)
; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GCN-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(1)* @external_global
}

define i32 addrspace(999)* @external_other_got() {
; GCN-LABEL: name: external_other_got
; GCN: bb.1 (%ir-block.0):
; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_other + 4, target-flags(amdgpu-gotprel32-hi) @external_other + 12, implicit-def $scc
; GCN: [[LOAD:%[0-9]+]]:_(p999) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p999) from got, addrspace 4)
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p999)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: SI_RETURN implicit $vgpr0, implicit $vgpr1
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_other + 4, target-flags(amdgpu-gotprel32-hi) @external_other + 12, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(p999) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p999) from got, addrspace 4)
; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](p999)
; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)
; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GCN-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(999)* @external_other
}

define i32 addrspace(4)* @internal_constant_pcrel() {
; GCN-LABEL: name: internal_constant_pcrel
; GCN: bb.1 (%ir-block.0):
; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant + 4, target-flags(amdgpu-rel32-hi) @internal_constant + 12, implicit-def $scc
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p4)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: SI_RETURN implicit $vgpr0, implicit $vgpr1
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant + 4, target-flags(amdgpu-rel32-hi) @internal_constant + 12, implicit-def $scc
; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p4)
; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)
; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GCN-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(4)* @internal_constant
}

define i32 addrspace(1)* @internal_global_pcrel() {
; GCN-LABEL: name: internal_global_pcrel
; GCN: bb.1 (%ir-block.0):
; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p1) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_global + 4, target-flags(amdgpu-rel32-hi) @internal_global + 12, implicit-def $scc
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p1)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: SI_RETURN implicit $vgpr0, implicit $vgpr1
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p1) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_global + 4, target-flags(amdgpu-rel32-hi) @internal_global + 12, implicit-def $scc
; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p1)
; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)
; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GCN-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(1)* @internal_global
}

define i32 addrspace(999)* @internal_other_pcrel() {
; GCN-LABEL: name: internal_other_pcrel
; GCN: bb.1 (%ir-block.0):
; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p999) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_other + 4, target-flags(amdgpu-rel32-hi) @internal_other + 12, implicit-def $scc
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p999)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: SI_RETURN implicit $vgpr0, implicit $vgpr1
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p999) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_other + 4, target-flags(amdgpu-rel32-hi) @internal_other + 12, implicit-def $scc
; GCN-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[SI_PC_ADD_REL_OFFSET]](p999)
; GCN-NEXT: $vgpr0 = COPY [[UV]](s32)
; GCN-NEXT: $vgpr1 = COPY [[UV1]](s32)
; GCN-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
ret i32 addrspace(999)* @internal_other
}

define i32 addrspace(6)* @external_constant32_got() {
; GCN-LABEL: name: external_constant32_got
; GCN: bb.1 (%ir-block.0):
; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32 + 4, target-flags(amdgpu-gotprel32-hi) @external_constant32 + 12, implicit-def $scc
; GCN: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p4) from got, addrspace 4)
; GCN: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[LOAD]](p4), 0
; GCN: $vgpr0 = COPY [[EXTRACT]](p6)
; GCN: SI_RETURN implicit $vgpr0
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32 + 4, target-flags(amdgpu-gotprel32-hi) @external_constant32 + 12, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p4) from got, addrspace 4)
; GCN-NEXT: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[LOAD]](p4), 0
; GCN-NEXT: $vgpr0 = COPY [[EXTRACT]](p6)
; GCN-NEXT: SI_RETURN implicit $vgpr0
ret i32 addrspace(6)* @external_constant32
}

define i32 addrspace(6)* @internal_constant32_pcrel() {
; GCN-LABEL: name: internal_constant32_pcrel
; GCN: bb.1 (%ir-block.0):
; GCN: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32 + 4, target-flags(amdgpu-rel32-hi) @internal_constant32 + 12, implicit-def $scc
; GCN: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0
; GCN: $vgpr0 = COPY [[EXTRACT]](p6)
; GCN: SI_RETURN implicit $vgpr0
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32 + 4, target-flags(amdgpu-rel32-hi) @internal_constant32 + 12, implicit-def $scc
; GCN-NEXT: [[EXTRACT:%[0-9]+]]:_(p6) = G_EXTRACT [[SI_PC_ADD_REL_OFFSET]](p4), 0
; GCN-NEXT: $vgpr0 = COPY [[EXTRACT]](p6)
; GCN-NEXT: SI_RETURN implicit $vgpr0
ret i32 addrspace(6)* @internal_constant32
}
50 changes: 28 additions & 22 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,14 +16,16 @@ body: |
; GFX6-LABEL: name: smax_neg_abs_pattern_s32_ss
; GFX6: liveins: $sgpr0
; GFX6: %src0:sreg_32 = COPY $sgpr0
; GFX6: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX6: S_ENDPGM 0, implicit %smax
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: %src0:sreg_32 = COPY $sgpr0
; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX6-NEXT: S_ENDPGM 0, implicit %smax
; GFX9-LABEL: name: smax_neg_abs_pattern_s32_ss
; GFX9: liveins: $sgpr0
; GFX9: %src0:sreg_32 = COPY $sgpr0
; GFX9: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX9: S_ENDPGM 0, implicit %smax
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: %src0:sreg_32 = COPY $sgpr0
; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX9-NEXT: S_ENDPGM 0, implicit %smax
%src0:sgpr(s32) = COPY $sgpr0
%zero:sgpr(s32) = G_CONSTANT i32 0
%ineg:sgpr(s32) = G_SUB %zero, %src0
Expand All @@ -43,14 +45,16 @@ body: |
; GFX6-LABEL: name: smax_neg_abs_pattern_s32_ss_commute
; GFX6: liveins: $sgpr0
; GFX6: %src0:sreg_32 = COPY $sgpr0
; GFX6: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX6: S_ENDPGM 0, implicit %smax
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: %src0:sreg_32 = COPY $sgpr0
; GFX6-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX6-NEXT: S_ENDPGM 0, implicit %smax
; GFX9-LABEL: name: smax_neg_abs_pattern_s32_ss_commute
; GFX9: liveins: $sgpr0
; GFX9: %src0:sreg_32 = COPY $sgpr0
; GFX9: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX9: S_ENDPGM 0, implicit %smax
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: %src0:sreg_32 = COPY $sgpr0
; GFX9-NEXT: %smax:sreg_32 = S_ABS_I32 %src0, implicit-def $scc
; GFX9-NEXT: S_ENDPGM 0, implicit %smax
%src0:sgpr(s32) = COPY $sgpr0
%zero:sgpr(s32) = G_CONSTANT i32 0
%ineg:sgpr(s32) = G_SUB %zero, %src0
Expand All @@ -70,18 +74,20 @@ body: |
; GFX6-LABEL: name: smax_neg_abs_pattern_s32_vv
; GFX6: liveins: $vgpr0
; GFX6: %src0:vgpr_32 = COPY $vgpr0
; GFX6: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX6: %ineg:vgpr_32, dead %4:sreg_64_xexec = V_SUB_CO_U32_e64 %zero, %src0, 0, implicit $exec
; GFX6: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
; GFX6: S_ENDPGM 0, implicit %smax
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: %src0:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX6-NEXT: %ineg:vgpr_32, dead %4:sreg_64_xexec = V_SUB_CO_U32_e64 %zero, %src0, 0, implicit $exec
; GFX6-NEXT: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %smax
; GFX9-LABEL: name: smax_neg_abs_pattern_s32_vv
; GFX9: liveins: $vgpr0
; GFX9: %src0:vgpr_32 = COPY $vgpr0
; GFX9: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX9: %ineg:vgpr_32 = V_SUB_U32_e64 %zero, %src0, 0, implicit $exec
; GFX9: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
; GFX9: S_ENDPGM 0, implicit %smax
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: %src0:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: %zero:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; GFX9-NEXT: %ineg:vgpr_32 = V_SUB_U32_e64 %zero, %src0, 0, implicit $exec
; GFX9-NEXT: %smax:vgpr_32 = V_MAX_I32_e64 %src0, %ineg, implicit $exec
; GFX9-NEXT: S_ENDPGM 0, implicit %smax
%src0:vgpr(s32) = COPY $vgpr0
%zero:vgpr(s32) = G_CONSTANT i32 0
%ineg:vgpr(s32) = G_SUB %zero, %src0
Expand Down
100 changes: 56 additions & 44 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,23 +16,27 @@ body: |
; GFX6-LABEL: name: add_s32
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_ADD_I32_]], %7, 0, implicit $exec
; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_CO_U32_e64 %8, [[COPY2]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit %7, implicit %8, implicit %9
; GFX6: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX6-NEXT: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
; GFX6-NEXT: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_CO_U32_e64 [[S_ADD_I32_]], %7, 0, implicit $exec
; GFX6-NEXT: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_CO_U32_e64 %8, [[COPY2]], 0, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit %7, implicit %8, implicit %9
; GFX9-LABEL: name: add_s32
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_I32_]], [[V_ADD_U32_e64_]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_2]]
; GFX9: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_I32_]], 0, implicit $exec
; GFX9-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_I32_]], [[V_ADD_U32_e64_]], 0, implicit $exec
; GFX9-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec
; GFX9-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]], implicit [[V_ADD_U32_e64_]], implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_2]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:vgpr(s32) = COPY $vgpr0
Expand Down Expand Up @@ -68,14 +72,16 @@ body: |
; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
; GFX6: liveins: $sgpr0
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
; GFX6: S_ENDPGM 0, implicit [[S_SUB_I32_]]
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
; GFX6-NEXT: S_ENDPGM 0, implicit [[S_SUB_I32_]]
; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_s
; GFX9: liveins: $sgpr0
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
; GFX9: S_ENDPGM 0, implicit [[S_SUB_I32_]]
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9-NEXT: [[S_SUB_I32_:%[0-9]+]]:sreg_32 = S_SUB_I32 [[COPY]], 64, implicit-def $scc
; GFX9-NEXT: S_ENDPGM 0, implicit [[S_SUB_I32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 -64
%2:sgpr(s32) = G_ADD %0, %1
Expand All @@ -95,14 +101,16 @@ body: |
; GFX6-LABEL: name: add_neg_inline_const_64_to_sub_s32_v
; GFX6: liveins: $vgpr0
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: %2:vgpr_32, dead %3:sreg_64 = V_SUB_CO_U32_e64 [[COPY]], 64, 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit %2
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: %2:vgpr_32, dead %3:sreg_64 = V_SUB_CO_U32_e64 [[COPY]], 64, 0, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %2
; GFX9-LABEL: name: add_neg_inline_const_64_to_sub_s32_v
; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY]], 64, 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_SUB_U32_e64_]]
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[V_SUB_U32_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U32_e64 [[COPY]], 64, 0, implicit $exec
; GFX9-NEXT: S_ENDPGM 0, implicit [[V_SUB_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 -64
%2:vgpr(s32) = G_ADD %0, %1
Expand All @@ -122,16 +130,18 @@ body: |
; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_s
; GFX6: liveins: $sgpr0
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; GFX6: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GFX6: S_ENDPGM 0, implicit [[S_ADD_I32_]]
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; GFX6-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GFX6-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]]
; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_s
; GFX9: liveins: $sgpr0
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_]]
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
; GFX9-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
; GFX9-NEXT: S_ENDPGM 0, implicit [[S_ADD_I32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = G_CONSTANT i32 16
%2:sgpr(s32) = G_ADD %0, %1
Expand All @@ -151,16 +161,18 @@ body: |
; GFX6-LABEL: name: add_neg_inline_const_16_to_sub_s32_v
; GFX6: liveins: $vgpr0
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
; GFX6: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit %2
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
; GFX6-NEXT: %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %2
; GFX9-LABEL: name: add_neg_inline_const_16_to_sub_s32_v
; GFX9: liveins: $vgpr0
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
; GFX9-NEXT: {{ $}}
; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 16, implicit $exec
; GFX9-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX9-NEXT: S_ENDPGM 0, implicit [[V_ADD_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_CONSTANT i32 16
%2:vgpr(s32) = G_ADD %0, %1
Expand Down
32 changes: 18 additions & 14 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,10 +18,11 @@ body: |
; GFX6-LABEL: name: add_s16
; GFX6: liveins: $vgpr0, $vgpr1
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
; GFX10-LABEL: name: add_s16
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
Expand Down Expand Up @@ -50,10 +51,11 @@ body: |
; GFX6-LABEL: name: add_s16_zext_to_s32
; GFX6: liveins: $vgpr0, $vgpr1
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: [[V_ADD_U16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U16_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_ADD_U16_e64_]]
; GFX10-LABEL: name: add_s16_zext_to_s32
; GFX10: liveins: $vgpr0, $vgpr1
; GFX10-NEXT: {{ $}}
Expand Down Expand Up @@ -84,9 +86,10 @@ body: |
; GFX6-LABEL: name: add_s16_neg_inline_const_64
; GFX6: liveins: $vgpr0
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
; GFX10-LABEL: name: add_s16_neg_inline_const_64
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
Expand All @@ -113,9 +116,10 @@ body: |
; GFX6-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
; GFX6: liveins: $vgpr0
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
; GFX6: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[V_SUB_U16_e64_:%[0-9]+]]:vgpr_32 = V_SUB_U16_e64 [[COPY]], 64, 0, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit [[V_SUB_U16_e64_]]
; GFX10-LABEL: name: add_s16_neg_inline_const_64_zext_to_s32
; GFX10: liveins: $vgpr0
; GFX10-NEXT: {{ $}}
Expand Down
108 changes: 60 additions & 48 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,16 +13,18 @@ body: |
liveins: $sgpr0, $vgpr0
; WAVE64-LABEL: name: class_s32_vcc_sv
; WAVE64: liveins: $sgpr0, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-LABEL: name: class_s32_vcc_sv
; WAVE32: liveins: $sgpr0, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
Expand All @@ -40,16 +42,18 @@ body: |
liveins: $sgpr0, $vgpr0
; WAVE64-LABEL: name: class_s32_vcc_vs
; WAVE64: liveins: $sgpr0, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-LABEL: name: class_s32_vcc_vs
; WAVE32: liveins: $sgpr0, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
Expand All @@ -67,16 +71,18 @@ body: |
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: class_s32_vcc_vv
; WAVE64: liveins: $vgpr0, $vgpr1
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE64-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-LABEL: name: class_s32_vcc_vv
; WAVE32: liveins: $vgpr0, $vgpr1
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; WAVE32-NEXT: [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
Expand All @@ -94,16 +100,18 @@ body: |
liveins: $sgpr0_sgpr1, $vgpr0
; WAVE64-LABEL: name: class_s64_vcc_sv
; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-LABEL: name: class_s64_vcc_sv
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s32) = COPY $vgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
Expand All @@ -122,16 +130,18 @@ body: |
; WAVE64-LABEL: name: class_s64_vcc_vs
; WAVE64: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-LABEL: name: class_s64_vcc_vs
; WAVE32: liveins: $sgpr0_sgpr1, $vgpr0
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:sgpr(s32) = COPY $sgpr0
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
Expand All @@ -150,16 +160,18 @@ body: |
; WAVE64-LABEL: name: class_s64_vcc_vv
; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; WAVE64: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE64-NEXT: {{ $}}
; WAVE64-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; WAVE64-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-LABEL: name: class_s64_vcc_vv
; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; WAVE32: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
; WAVE32-NEXT: {{ $}}
; WAVE32-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; WAVE32-NEXT: [[V_CMP_CLASS_F64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F64_e64 0, [[COPY]], [[COPY1]], implicit $exec
; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F64_e64_]]
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s32) = COPY $vgpr2
%2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0, %1
Expand Down
14 changes: 8 additions & 6 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,10 @@ body: |
; CHECK-LABEL: name: cos_s32_vs
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: %1:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit %1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0
S_ENDPGM 0, implicit %1
Expand All @@ -34,9 +35,10 @@ body: |
; CHECK-LABEL: name: cos_s32_vv
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: %1:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit %1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0
S_ENDPGM 0, implicit %1
Expand Down
27 changes: 15 additions & 12 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,11 @@ body: |
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: cvt_pk_i16_vsv
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
Expand All @@ -35,10 +36,11 @@ body: |
; GCN-LABEL: name: cvt_pk_i16_vvs
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
Expand All @@ -56,10 +58,11 @@ body: |
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: cvt_pk_i16_vvv
; GCN: liveins: $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_CVT_PK_I16_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_I16_I32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PK_I16_I32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.i16), %0, %1
Expand Down
27 changes: 15 additions & 12 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,11 @@ body: |
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: cvt_pk_u16_vsv
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
Expand All @@ -35,10 +36,11 @@ body: |
; GCN-LABEL: name: cvt_pk_u16_vvs
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
Expand All @@ -56,10 +58,11 @@ body: |
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: cvt_pk_u16_vvv
; GCN: liveins: $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_CVT_PK_U16_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PK_U16_U32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PK_U16_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pk.u16), %0, %1
Expand Down
27 changes: 15 additions & 12 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,11 @@ body: |
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: cvt_pknorm_i16_vsv
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CVT_PKNORM_I16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_I16_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_CVT_PKNORM_I16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PKNORM_I16_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.i16), %0, %1
Expand All @@ -35,10 +36,11 @@ body: |
; GCN-LABEL: name: cvt_pknorm_i16_vvs
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_CVT_PKNORM_I16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_I16_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[V_CVT_PKNORM_I16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PKNORM_I16_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.i16), %0, %1
Expand All @@ -56,10 +58,11 @@ body: |
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: cvt_pknorm_i16_vvv
; GCN: liveins: $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_CVT_PKNORM_I16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_I16_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_CVT_PKNORM_I16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_I16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PKNORM_I16_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.i16), %0, %1
Expand Down
27 changes: 15 additions & 12 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,11 @@ body: |
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: cvt_pknorm_u16_vsv
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_CVT_PKNORM_U16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_U16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_U16_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_CVT_PKNORM_U16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_U16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PKNORM_U16_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.u16), %0, %1
Expand All @@ -35,10 +36,11 @@ body: |
; GCN-LABEL: name: cvt_pknorm_u16_vvs
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_CVT_PKNORM_U16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_U16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_U16_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[V_CVT_PKNORM_U16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_U16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PKNORM_U16_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.u16), %0, %1
Expand All @@ -56,10 +58,11 @@ body: |
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: cvt_pknorm_u16_vvv
; GCN: liveins: $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_CVT_PKNORM_U16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_U16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_CVT_PKNORM_U16_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_CVT_PKNORM_U16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKNORM_U16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_CVT_PKNORM_U16_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pknorm.u16), %0, %1
Expand Down
27 changes: 15 additions & 12 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,10 +13,11 @@ body: |
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: cvt_pkrtz_vsv
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit %2
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit %2
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
Expand All @@ -35,10 +36,11 @@ body: |
; GCN-LABEL: name: cvt_pkrtz_vvs
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit %2
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
Expand All @@ -56,10 +58,11 @@ body: |
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: cvt_pkrtz_vvv
; GCN: liveins: $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit %2
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: %2:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
Expand Down
14 changes: 8 additions & 6 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,10 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: ds_swizzle_0
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 0, 0, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 0, 0, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.swizzle), %0, 0
S_ENDPGM 0, implicit %1
Expand All @@ -36,9 +37,10 @@ body: |
liveins: $vgpr0
; CHECK-LABEL: name: ds_swizzle_65535
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 65535, 0, implicit $exec
; CHECK: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 65535, 0, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.swizzle), %0, 65535
S_ENDPGM 0, implicit %1
Expand Down
97 changes: 53 additions & 44 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,11 +16,12 @@ body: |
; GCN-LABEL: name: fmad_ftz_s32_vvvv
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
Expand All @@ -40,11 +41,12 @@ body: |
; GCN-LABEL: name: fmad_ftz_s32_vsvv
; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1
Expand All @@ -64,11 +66,12 @@ body: |
; GCN-LABEL: name: fmad_ftz_s32_vvsv
; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s32) = COPY $vgpr1
Expand All @@ -88,12 +91,13 @@ body: |
; GCN-LABEL: name: fmad_ftz_s32_vvvs
; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:sgpr(s32) = COPY $sgpr0
Expand All @@ -115,10 +119,11 @@ body: |
; GCN-LABEL: name: fmad_ftz_s32_vssv
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %0, %1
Expand All @@ -137,11 +142,12 @@ body: |
; GCN-LABEL: name: fmad_ftz_s32_vsvs
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %0
Expand All @@ -160,11 +166,12 @@ body: |
; GCN-LABEL: name: fmad_ftz_s32_vvss
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %1, %0, %0
Expand All @@ -183,10 +190,11 @@ body: |
; GCN-LABEL: name: fmad_ftz_s32_vsss
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GCN-NEXT: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %0, %0
S_ENDPGM 0, implicit %1
Expand Down Expand Up @@ -223,11 +231,12 @@ body: |
; GCN-LABEL: name: fmad_ftz_s32_vvv_fneg_v
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN: [[V_MAD_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F32_e64 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MAD_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN-NEXT: [[V_MAD_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAD_F32_e64 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MAD_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
Expand Down
78 changes: 43 additions & 35 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,11 +13,12 @@ body: |
; GCN-LABEL: name: fmed3_s32_vvvv
; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
Expand All @@ -37,11 +38,12 @@ body: |
; GCN-LABEL: name: fmed3_s32_vsvv
; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = COPY $vgpr1
Expand All @@ -61,11 +63,12 @@ body: |
; GCN-LABEL: name: fmed3_s32_vvsv
; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s32) = COPY $vgpr1
Expand All @@ -85,11 +88,12 @@ body: |
; GCN-LABEL: name: fmed3_s32_vvvs
; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:sgpr(s32) = COPY $sgpr0
Expand All @@ -111,10 +115,11 @@ body: |
; GCN-LABEL: name: fmed3_s32_vssv
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %1
Expand All @@ -133,10 +138,11 @@ body: |
; GCN-LABEL: name: fmed3_s32_vsvs
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %0
Expand All @@ -155,10 +161,11 @@ body: |
; GCN-LABEL: name: fmed3_s32_vvss
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %1, %0, %0
Expand All @@ -177,9 +184,10 @@ body: |
; GCN-LABEL: name: fmed3_s32_vsss
; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN-NEXT: [[V_MED3_F32_e64_:%[0-9]+]]:vgpr_32 = V_MED3_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: S_ENDPGM 0, implicit [[V_MED3_F32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %0
S_ENDPGM 0, implicit %1
Expand Down
28 changes: 16 additions & 12 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,10 @@ body: |
; CHECK-LABEL: name: fract_s32_vs
; CHECK: liveins: $sgpr0
; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK: %1:vgpr_32 = nofpexcept V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit %1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit %1
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
S_ENDPGM 0, implicit %1
Expand All @@ -34,9 +35,10 @@ body: |
; CHECK-LABEL: name: fract_s32_vv
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: %1:vgpr_32 = nofpexcept V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit %1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: %1:vgpr_32 = nofpexcept V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit %1
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
S_ENDPGM 0, implicit %1
Expand All @@ -54,9 +56,10 @@ body: |
; CHECK-LABEL: name: fract_s64_vs
; CHECK: liveins: $sgpr0_sgpr1
; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK: %1:vreg_64 = nofpexcept V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit %1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
; CHECK-NEXT: %1:vreg_64 = nofpexcept V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit %1
%0:sgpr(s64) = COPY $sgpr0_sgpr1
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
S_ENDPGM 0, implicit %1
Expand All @@ -74,9 +77,10 @@ body: |
; CHECK-LABEL: name: fract_s64_vv
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK: %1:vreg_64 = nofpexcept V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK: S_ENDPGM 0, implicit %1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; CHECK-NEXT: %1:vreg_64 = nofpexcept V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit %1
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
S_ENDPGM 0, implicit %1
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,10 @@ body: |
; HSAPAL-LABEL: name: groupstaticsize_v
; HSAPAL: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
; HSAPAL: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; HSAPAL-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MESA-LABEL: name: groupstaticsize_v
; MESA: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @llvm.amdgcn.groupstaticsize, implicit $exec
; MESA: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
; MESA-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
%0:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
S_ENDPGM 0, implicit %0
...
Expand All @@ -37,10 +37,10 @@ body: |
; HSAPAL-LABEL: name: groupstaticsize_s
; HSAPAL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
; HSAPAL: S_ENDPGM 0, implicit [[S_MOV_B32_]]
; HSAPAL-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
; MESA-LABEL: name: groupstaticsize_s
; MESA: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @llvm.amdgcn.groupstaticsize
; MESA: S_ENDPGM 0, implicit [[S_MOV_B32_]]
; MESA-NEXT: S_ENDPGM 0, implicit [[S_MOV_B32_]]
%0:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
S_ENDPGM 0, implicit %0
...
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