72 changes: 36 additions & 36 deletions clang/test/CodeGen/X86/avx512vlvbmi2-builtins.c
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6 changes: 3 additions & 3 deletions clang/test/CodeGen/X86/mmx-builtins.c
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Expand Up @@ -86,7 +86,7 @@ __m64 test_mm_and_si64(__m64 a, __m64 b) {

__m64 test_mm_andnot_si64(__m64 a, __m64 b) {
// CHECK-LABEL: test_mm_andnot_si64
// CHECK: [[TMP:%.*]] = xor <1 x i64> {{%.*}}, <i64 -1>
// CHECK: [[TMP:%.*]] = xor <1 x i64> {{%.*}}, splat (i64 -1)
// CHECK: and <1 x i64> [[TMP]], {{%.*}}
return _mm_andnot_si64(a, b);
}
Expand Down Expand Up @@ -333,8 +333,8 @@ int test_mm_movemask_pi8(__m64 a) {

__m64 test_mm_mul_su32(__m64 a, __m64 b) {
// CHECK-LABEL: test_mm_mul_su32
// CHECK: and <2 x i64> {{%.*}}, <i64 4294967295, i64 4294967295>
// CHECK: and <2 x i64> {{%.*}}, <i64 4294967295, i64 4294967295>
// CHECK: and <2 x i64> {{%.*}}, splat (i64 4294967295)
// CHECK: and <2 x i64> {{%.*}}, splat (i64 4294967295)
// CHECK: mul <2 x i64> %{{.*}}, %{{.*}}
return _mm_mul_su32(a, b);
}
Expand Down
2 changes: 1 addition & 1 deletion clang/test/CodeGen/X86/sse-builtins.c
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Expand Up @@ -35,7 +35,7 @@ TEST_CONSTEXPR(match_m128(_mm_and_ps((__m128){-4.0f, -5.0f, +6.0f, +7.0f}, (__m1

__m128 test_mm_andnot_ps(__m128 A, __m128 B) {
// CHECK-LABEL: test_mm_andnot_ps
// CHECK: xor <4 x i32> %{{.*}}, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: xor <4 x i32> %{{.*}}, splat (i32 -1)
// CHECK: and <4 x i32>
return _mm_andnot_ps(A, B);
}
Expand Down
8 changes: 4 additions & 4 deletions clang/test/CodeGen/X86/sse2-builtins.c
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Expand Up @@ -99,15 +99,15 @@ __m128i test_mm_and_si128(__m128i A, __m128i B) {

__m128d test_mm_andnot_pd(__m128d A, __m128d B) {
// CHECK-LABEL: test_mm_andnot_pd
// CHECK: xor <2 x i64> %{{.*}}, <i64 -1, i64 -1>
// CHECK: xor <2 x i64> %{{.*}}, splat (i64 -1)
// CHECK: and <2 x i64>
return _mm_andnot_pd(A, B);
}
TEST_CONSTEXPR(match_m128d(_mm_andnot_pd((__m128d){+1.0, -3.0}, (__m128d){+0.0, -0.0}), +0.0, -0.0));

__m128i test_mm_andnot_si128(__m128i A, __m128i B) {
// CHECK-LABEL: test_mm_andnot_si128
// CHECK: xor <2 x i64> %{{.*}}, <i64 -1, i64 -1>
// CHECK: xor <2 x i64> %{{.*}}, splat (i64 -1)
// CHECK: and <2 x i64>
return _mm_andnot_si128(A, B);
}
Expand Down Expand Up @@ -906,8 +906,8 @@ int test_mm_movemask_pd(__m128d A) {

__m128i test_mm_mul_epu32(__m128i A, __m128i B) {
// CHECK-LABEL: test_mm_mul_epu32
// CHECK: and <2 x i64> %{{.*}}, <i64 4294967295, i64 4294967295>
// CHECK: and <2 x i64> %{{.*}}, <i64 4294967295, i64 4294967295>
// CHECK: and <2 x i64> %{{.*}}, splat (i64 4294967295)
// CHECK: and <2 x i64> %{{.*}}, splat (i64 4294967295)
// CHECK: mul <2 x i64> %{{.*}}, %{{.*}}
return _mm_mul_epu32(A, B);
}
Expand Down
8 changes: 4 additions & 4 deletions clang/test/CodeGen/X86/sse41-builtins.c
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Expand Up @@ -312,10 +312,10 @@ __m128i test_mm_mpsadbw_epu8(__m128i x, __m128i y) {

__m128i test_mm_mul_epi32(__m128i x, __m128i y) {
// CHECK-LABEL: test_mm_mul_epi32
// CHECK: shl <2 x i64> %{{.*}}, <i64 32, i64 32>
// CHECK: ashr <2 x i64> %{{.*}}, <i64 32, i64 32>
// CHECK: shl <2 x i64> %{{.*}}, <i64 32, i64 32>
// CHECK: ashr <2 x i64> %{{.*}}, <i64 32, i64 32>
// CHECK: shl <2 x i64> %{{.*}}, splat (i64 32)
// CHECK: ashr <2 x i64> %{{.*}}, splat (i64 32)
// CHECK: shl <2 x i64> %{{.*}}, splat (i64 32)
// CHECK: ashr <2 x i64> %{{.*}}, splat (i64 32)
// CHECK: mul <2 x i64> %{{.*}}, %{{.*}}
return _mm_mul_epi32(x, y);
}
Expand Down
16 changes: 8 additions & 8 deletions clang/test/CodeGen/X86/xop-builtins-cmp.c
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Expand Up @@ -408,48 +408,48 @@ __m128i test_mm_comfalse_epi64(__m128i a, __m128i b) {

__m128i test_mm_comtrue_epu8(__m128i a, __m128i b) {
// CHECK-LABEL: test_mm_comtrue_epu8
// CHECK: ret <2 x i64> <i64 -1, i64 -1>
// CHECK: ret <2 x i64> splat (i64 -1)
return _mm_comtrue_epu8(a, b);
}

__m128i test_mm_comtrue_epu16(__m128i a, __m128i b) {
// CHECK-LABEL: test_mm_comtrue_epu16
// CHECK: ret <2 x i64> <i64 -1, i64 -1>
// CHECK: ret <2 x i64> splat (i64 -1)
return _mm_comtrue_epu16(a, b);
}

__m128i test_mm_comtrue_epu32(__m128i a, __m128i b) {
// CHECK-LABEL: test_mm_comtrue_epu32
// CHECK: ret <2 x i64> <i64 -1, i64 -1>
// CHECK: ret <2 x i64> splat (i64 -1)
return _mm_comtrue_epu32(a, b);
}

__m128i test_mm_comtrue_epu64(__m128i a, __m128i b) {
// CHECK-LABEL: test_mm_comtrue_epu64
// CHECK: ret <2 x i64> <i64 -1, i64 -1>
// CHECK: ret <2 x i64> splat (i64 -1)
return _mm_comtrue_epu64(a, b);
}

__m128i test_mm_comtrue_epi8(__m128i a, __m128i b) {
// CHECK-LABEL: test_mm_comtrue_epi8
// CHECK: ret <2 x i64> <i64 -1, i64 -1>
// CHECK: ret <2 x i64> splat (i64 -1)
return _mm_comtrue_epi8(a, b);
}

__m128i test_mm_comtrue_epi16(__m128i a, __m128i b) {
// CHECK-LABEL: test_mm_comtrue_epi16
// CHECK: ret <2 x i64> <i64 -1, i64 -1>
// CHECK: ret <2 x i64> splat (i64 -1)
return _mm_comtrue_epi16(a, b);
}

__m128i test_mm_comtrue_epi32(__m128i a, __m128i b) {
// CHECK-LABEL: test_mm_comtrue_epi32
// CHECK: ret <2 x i64> <i64 -1, i64 -1>
// CHECK: ret <2 x i64> splat (i64 -1)
return _mm_comtrue_epi32(a, b);
}

__m128i test_mm_comtrue_epi64(__m128i a, __m128i b) {
// CHECK-LABEL: test_mm_comtrue_epi64
// CHECK: ret <2 x i64> <i64 -1, i64 -1>
// CHECK: ret <2 x i64> splat (i64 -1)
return _mm_comtrue_epi64(a, b);
}
12 changes: 6 additions & 6 deletions clang/test/CodeGen/X86/xop-builtins.c
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Expand Up @@ -173,7 +173,7 @@ __m128i test_mm_hsubq_epi32(__m128i a) {
__m128i test_mm_cmov_si128(__m128i a, __m128i b, __m128i c) {
// CHECK-LABEL: test_mm_cmov_si128
// CHECK: [[AND:%.*]] = and <2 x i64> %{{.*}}, %{{.*}}
// CHECK: [[NEG:%.*]] = xor <2 x i64> %{{.*}}, <i64 -1, i64 -1>
// CHECK: [[NEG:%.*]] = xor <2 x i64> %{{.*}}, splat (i64 -1)
// CHECK-NEXT: [[ANDN:%.*]] = and <2 x i64> %{{.*}}, [[NEG]]
// CHECK-NEXT: %{{.*}} = or <2 x i64> [[AND]], [[ANDN]]
return _mm_cmov_si128(a, b, c);
Expand All @@ -182,7 +182,7 @@ __m128i test_mm_cmov_si128(__m128i a, __m128i b, __m128i c) {
__m256i test_mm256_cmov_si256(__m256i a, __m256i b, __m256i c) {
// CHECK-LABEL: test_mm256_cmov_si256
// CHECK: [[AND:%.*]] = and <4 x i64> %{{.*}}, %{{.*}}
// CHECK: [[NEG:%.*]] = xor <4 x i64> %{{.*}}, <i64 -1, i64 -1, i64 -1, i64 -1>
// CHECK: [[NEG:%.*]] = xor <4 x i64> %{{.*}}, splat (i64 -1)
// CHECK-NEXT: [[ANDN:%.*]] = and <4 x i64> %{{.*}}, [[NEG]]
// CHECK-NEXT: %{{.*}} = or <4 x i64> [[AND]], [[ANDN]]
return _mm256_cmov_si256(a, b, c);
Expand Down Expand Up @@ -220,25 +220,25 @@ __m128i test_mm_rot_epi64(__m128i a, __m128i b) {

__m128i test_mm_roti_epi8(__m128i a) {
// CHECK-LABEL: test_mm_roti_epi8
// CHECK: call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
// CHECK: call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}, <16 x i8> splat (i8 1))
return _mm_roti_epi8(a, 1);
}

__m128i test_mm_roti_epi16(__m128i a) {
// CHECK-LABEL: test_mm_roti_epi16
// CHECK: call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> <i16 50, i16 50, i16 50, i16 50, i16 50, i16 50, i16 50, i16 50>)
// CHECK: call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> splat (i16 50))
return _mm_roti_epi16(a, 50);
}

__m128i test_mm_roti_epi32(__m128i a) {
// CHECK-LABEL: test_mm_roti_epi32
// CHECK: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 226, i32 226, i32 226, i32 226>)
// CHECK: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> splat (i32 226))
return _mm_roti_epi32(a, -30);
}

__m128i test_mm_roti_epi64(__m128i a) {
// CHECK-LABEL: test_mm_roti_epi64
// CHECK: call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> <i64 100, i64 100>)
// CHECK: call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i64> splat (i64 100))
return _mm_roti_epi64(a, 100);
}

Expand Down
64 changes: 32 additions & 32 deletions clang/test/CodeGen/aarch64-neon-3v.c
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Expand Up @@ -341,255 +341,255 @@ uint64x2_t test_veorq_u64(uint64x2_t a, uint64x2_t b) {
}

// CHECK-LABEL: define{{.*}} <8 x i8> @test_vbic_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, splat (i8 -1)
// CHECK: [[AND_I:%.*]] = and <8 x i8> %a, [[NEG_I]]
// CHECK: ret <8 x i8> [[AND_I]]
int8x8_t test_vbic_s8(int8x8_t a, int8x8_t b) {
return vbic_s8(a, b);
}

// CHECK-LABEL: define{{.*}} <16 x i8> @test_vbicq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, splat (i8 -1)
// CHECK: [[AND_I:%.*]] = and <16 x i8> %a, [[NEG_I]]
// CHECK: ret <16 x i8> [[AND_I]]
int8x16_t test_vbicq_s8(int8x16_t a, int8x16_t b) {
return vbicq_s8(a, b);
}

// CHECK-LABEL: define{{.*}} <4 x i16> @test_vbic_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, splat (i16 -1)
// CHECK: [[AND_I:%.*]] = and <4 x i16> %a, [[NEG_I]]
// CHECK: ret <4 x i16> [[AND_I]]
int16x4_t test_vbic_s16(int16x4_t a, int16x4_t b) {
return vbic_s16(a, b);
}

// CHECK-LABEL: define{{.*}} <8 x i16> @test_vbicq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, splat (i16 -1)
// CHECK: [[AND_I:%.*]] = and <8 x i16> %a, [[NEG_I]]
// CHECK: ret <8 x i16> [[AND_I]]
int16x8_t test_vbicq_s16(int16x8_t a, int16x8_t b) {
return vbicq_s16(a, b);
}

// CHECK-LABEL: define{{.*}} <2 x i32> @test_vbic_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, <i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, splat (i32 -1)
// CHECK: [[AND_I:%.*]] = and <2 x i32> %a, [[NEG_I]]
// CHECK: ret <2 x i32> [[AND_I]]
int32x2_t test_vbic_s32(int32x2_t a, int32x2_t b) {
return vbic_s32(a, b);
}

// CHECK-LABEL: define{{.*}} <4 x i32> @test_vbicq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, splat (i32 -1)
// CHECK: [[AND_I:%.*]] = and <4 x i32> %a, [[NEG_I]]
// CHECK: ret <4 x i32> [[AND_I]]
int32x4_t test_vbicq_s32(int32x4_t a, int32x4_t b) {
return vbicq_s32(a, b);
}

// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbic_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, <i64 -1>
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, splat (i64 -1)
// CHECK: [[AND_I:%.*]] = and <1 x i64> %a, [[NEG_I]]
// CHECK: ret <1 x i64> [[AND_I]]
int64x1_t test_vbic_s64(int64x1_t a, int64x1_t b) {
return vbic_s64(a, b);
}

// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbicq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, <i64 -1, i64 -1>
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, splat (i64 -1)
// CHECK: [[AND_I:%.*]] = and <2 x i64> %a, [[NEG_I]]
// CHECK: ret <2 x i64> [[AND_I]]
int64x2_t test_vbicq_s64(int64x2_t a, int64x2_t b) {
return vbicq_s64(a, b);
}

// CHECK-LABEL: define{{.*}} <8 x i8> @test_vbic_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, splat (i8 -1)
// CHECK: [[AND_I:%.*]] = and <8 x i8> %a, [[NEG_I]]
// CHECK: ret <8 x i8> [[AND_I]]
uint8x8_t test_vbic_u8(uint8x8_t a, uint8x8_t b) {
return vbic_u8(a, b);
}

// CHECK-LABEL: define{{.*}} <16 x i8> @test_vbicq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, splat (i8 -1)
// CHECK: [[AND_I:%.*]] = and <16 x i8> %a, [[NEG_I]]
// CHECK: ret <16 x i8> [[AND_I]]
uint8x16_t test_vbicq_u8(uint8x16_t a, uint8x16_t b) {
return vbicq_u8(a, b);
}

// CHECK-LABEL: define{{.*}} <4 x i16> @test_vbic_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, splat (i16 -1)
// CHECK: [[AND_I:%.*]] = and <4 x i16> %a, [[NEG_I]]
// CHECK: ret <4 x i16> [[AND_I]]
uint16x4_t test_vbic_u16(uint16x4_t a, uint16x4_t b) {
return vbic_u16(a, b);
}

// CHECK-LABEL: define{{.*}} <8 x i16> @test_vbicq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, splat (i16 -1)
// CHECK: [[AND_I:%.*]] = and <8 x i16> %a, [[NEG_I]]
// CHECK: ret <8 x i16> [[AND_I]]
uint16x8_t test_vbicq_u16(uint16x8_t a, uint16x8_t b) {
return vbicq_u16(a, b);
}

// CHECK-LABEL: define{{.*}} <2 x i32> @test_vbic_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, <i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, splat (i32 -1)
// CHECK: [[AND_I:%.*]] = and <2 x i32> %a, [[NEG_I]]
// CHECK: ret <2 x i32> [[AND_I]]
uint32x2_t test_vbic_u32(uint32x2_t a, uint32x2_t b) {
return vbic_u32(a, b);
}

// CHECK-LABEL: define{{.*}} <4 x i32> @test_vbicq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, splat (i32 -1)
// CHECK: [[AND_I:%.*]] = and <4 x i32> %a, [[NEG_I]]
// CHECK: ret <4 x i32> [[AND_I]]
uint32x4_t test_vbicq_u32(uint32x4_t a, uint32x4_t b) {
return vbicq_u32(a, b);
}

// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbic_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, <i64 -1>
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, splat (i64 -1)
// CHECK: [[AND_I:%.*]] = and <1 x i64> %a, [[NEG_I]]
// CHECK: ret <1 x i64> [[AND_I]]
uint64x1_t test_vbic_u64(uint64x1_t a, uint64x1_t b) {
return vbic_u64(a, b);
}

// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbicq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, <i64 -1, i64 -1>
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, splat (i64 -1)
// CHECK: [[AND_I:%.*]] = and <2 x i64> %a, [[NEG_I]]
// CHECK: ret <2 x i64> [[AND_I]]
uint64x2_t test_vbicq_u64(uint64x2_t a, uint64x2_t b) {
return vbicq_u64(a, b);
}

// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorn_s8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, splat (i8 -1)
// CHECK: [[OR_I:%.*]] = or <8 x i8> %a, [[NEG_I]]
// CHECK: ret <8 x i8> [[OR_I]]
int8x8_t test_vorn_s8(int8x8_t a, int8x8_t b) {
return vorn_s8(a, b);
}

// CHECK-LABEL: define{{.*}} <16 x i8> @test_vornq_s8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, splat (i8 -1)
// CHECK: [[OR_I:%.*]] = or <16 x i8> %a, [[NEG_I]]
// CHECK: ret <16 x i8> [[OR_I]]
int8x16_t test_vornq_s8(int8x16_t a, int8x16_t b) {
return vornq_s8(a, b);
}

// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorn_s16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, splat (i16 -1)
// CHECK: [[OR_I:%.*]] = or <4 x i16> %a, [[NEG_I]]
// CHECK: ret <4 x i16> [[OR_I]]
int16x4_t test_vorn_s16(int16x4_t a, int16x4_t b) {
return vorn_s16(a, b);
}

// CHECK-LABEL: define{{.*}} <8 x i16> @test_vornq_s16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, splat (i16 -1)
// CHECK: [[OR_I:%.*]] = or <8 x i16> %a, [[NEG_I]]
// CHECK: ret <8 x i16> [[OR_I]]
int16x8_t test_vornq_s16(int16x8_t a, int16x8_t b) {
return vornq_s16(a, b);
}

// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorn_s32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, <i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, splat (i32 -1)
// CHECK: [[OR_I:%.*]] = or <2 x i32> %a, [[NEG_I]]
// CHECK: ret <2 x i32> [[OR_I]]
int32x2_t test_vorn_s32(int32x2_t a, int32x2_t b) {
return vorn_s32(a, b);
}

// CHECK-LABEL: define{{.*}} <4 x i32> @test_vornq_s32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, splat (i32 -1)
// CHECK: [[OR_I:%.*]] = or <4 x i32> %a, [[NEG_I]]
// CHECK: ret <4 x i32> [[OR_I]]
int32x4_t test_vornq_s32(int32x4_t a, int32x4_t b) {
return vornq_s32(a, b);
}

// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorn_s64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, <i64 -1>
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, splat (i64 -1)
// CHECK: [[OR_I:%.*]] = or <1 x i64> %a, [[NEG_I]]
// CHECK: ret <1 x i64> [[OR_I]]
int64x1_t test_vorn_s64(int64x1_t a, int64x1_t b) {
return vorn_s64(a, b);
}

// CHECK-LABEL: define{{.*}} <2 x i64> @test_vornq_s64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, <i64 -1, i64 -1>
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, splat (i64 -1)
// CHECK: [[OR_I:%.*]] = or <2 x i64> %a, [[NEG_I]]
// CHECK: ret <2 x i64> [[OR_I]]
int64x2_t test_vornq_s64(int64x2_t a, int64x2_t b) {
return vornq_s64(a, b);
}

// CHECK-LABEL: define{{.*}} <8 x i8> @test_vorn_u8(<8 x i8> noundef %a, <8 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %b, splat (i8 -1)
// CHECK: [[OR_I:%.*]] = or <8 x i8> %a, [[NEG_I]]
// CHECK: ret <8 x i8> [[OR_I]]
uint8x8_t test_vorn_u8(uint8x8_t a, uint8x8_t b) {
return vorn_u8(a, b);
}

// CHECK-LABEL: define{{.*}} <16 x i8> @test_vornq_u8(<16 x i8> noundef %a, <16 x i8> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %b, splat (i8 -1)
// CHECK: [[OR_I:%.*]] = or <16 x i8> %a, [[NEG_I]]
// CHECK: ret <16 x i8> [[OR_I]]
uint8x16_t test_vornq_u8(uint8x16_t a, uint8x16_t b) {
return vornq_u8(a, b);
}

// CHECK-LABEL: define{{.*}} <4 x i16> @test_vorn_u16(<4 x i16> noundef %a, <4 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %b, splat (i16 -1)
// CHECK: [[OR_I:%.*]] = or <4 x i16> %a, [[NEG_I]]
// CHECK: ret <4 x i16> [[OR_I]]
uint16x4_t test_vorn_u16(uint16x4_t a, uint16x4_t b) {
return vorn_u16(a, b);
}

// CHECK-LABEL: define{{.*}} <8 x i16> @test_vornq_u16(<8 x i16> noundef %a, <8 x i16> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %b, splat (i16 -1)
// CHECK: [[OR_I:%.*]] = or <8 x i16> %a, [[NEG_I]]
// CHECK: ret <8 x i16> [[OR_I]]
uint16x8_t test_vornq_u16(uint16x8_t a, uint16x8_t b) {
return vornq_u16(a, b);
}

// CHECK-LABEL: define{{.*}} <2 x i32> @test_vorn_u32(<2 x i32> noundef %a, <2 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, <i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %b, splat (i32 -1)
// CHECK: [[OR_I:%.*]] = or <2 x i32> %a, [[NEG_I]]
// CHECK: ret <2 x i32> [[OR_I]]
uint32x2_t test_vorn_u32(uint32x2_t a, uint32x2_t b) {
return vorn_u32(a, b);
}

// CHECK-LABEL: define{{.*}} <4 x i32> @test_vornq_u32(<4 x i32> noundef %a, <4 x i32> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %b, splat (i32 -1)
// CHECK: [[OR_I:%.*]] = or <4 x i32> %a, [[NEG_I]]
// CHECK: ret <4 x i32> [[OR_I]]
uint32x4_t test_vornq_u32(uint32x4_t a, uint32x4_t b) {
return vornq_u32(a, b);
}

// CHECK-LABEL: define{{.*}} <1 x i64> @test_vorn_u64(<1 x i64> noundef %a, <1 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, <i64 -1>
// CHECK: [[NEG_I:%.*]] = xor <1 x i64> %b, splat (i64 -1)
// CHECK: [[OR_I:%.*]] = or <1 x i64> %a, [[NEG_I]]
// CHECK: ret <1 x i64> [[OR_I]]
uint64x1_t test_vorn_u64(uint64x1_t a, uint64x1_t b) {
return vorn_u64(a, b);
}

// CHECK-LABEL: define{{.*}} <2 x i64> @test_vornq_u64(<2 x i64> noundef %a, <2 x i64> noundef %b) #0 {
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, <i64 -1, i64 -1>
// CHECK: [[NEG_I:%.*]] = xor <2 x i64> %b, splat (i64 -1)
// CHECK: [[OR_I:%.*]] = or <2 x i64> %a, [[NEG_I]]
// CHECK: ret <2 x i64> [[OR_I]]
uint64x2_t test_vornq_u64(uint64x2_t a, uint64x2_t b) {
Expand Down
324 changes: 162 additions & 162 deletions clang/test/CodeGen/aarch64-neon-intrinsics.c
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Large diffs are not rendered by default.

52 changes: 26 additions & 26 deletions clang/test/CodeGen/aarch64-neon-misc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1668,98 +1668,98 @@ poly8x16_t test_vcntq_p8(poly8x16_t a) {
}

// CHECK-LABEL: @test_vmvn_s8(
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %a, splat (i8 -1)
// CHECK: ret <8 x i8> [[NEG_I]]
int8x8_t test_vmvn_s8(int8x8_t a) {
return vmvn_s8(a);
}

// CHECK-LABEL: @test_vmvnq_s8(
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %a, splat (i8 -1)
// CHECK: ret <16 x i8> [[NEG_I]]
int8x16_t test_vmvnq_s8(int8x16_t a) {
return vmvnq_s8(a);
}

// CHECK-LABEL: @test_vmvn_s16(
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %a, splat (i16 -1)
// CHECK: ret <4 x i16> [[NEG_I]]
int16x4_t test_vmvn_s16(int16x4_t a) {
return vmvn_s16(a);
}

// CHECK-LABEL: @test_vmvnq_s16(
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %a, splat (i16 -1)
// CHECK: ret <8 x i16> [[NEG_I]]
int16x8_t test_vmvnq_s16(int16x8_t a) {
return vmvnq_s16(a);
}

// CHECK-LABEL: @test_vmvn_s32(
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %a, <i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %a, splat (i32 -1)
// CHECK: ret <2 x i32> [[NEG_I]]
int32x2_t test_vmvn_s32(int32x2_t a) {
return vmvn_s32(a);
}

// CHECK-LABEL: @test_vmvnq_s32(
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %a, splat (i32 -1)
// CHECK: ret <4 x i32> [[NEG_I]]
int32x4_t test_vmvnq_s32(int32x4_t a) {
return vmvnq_s32(a);
}

// CHECK-LABEL: @test_vmvn_u8(
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %a, splat (i8 -1)
// CHECK: ret <8 x i8> [[NEG_I]]
uint8x8_t test_vmvn_u8(uint8x8_t a) {
return vmvn_u8(a);
}

// CHECK-LABEL: @test_vmvnq_u8(
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %a, splat (i8 -1)
// CHECK: ret <16 x i8> [[NEG_I]]
uint8x16_t test_vmvnq_u8(uint8x16_t a) {
return vmvnq_u8(a);
}

// CHECK-LABEL: @test_vmvn_u16(
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i16> %a, splat (i16 -1)
// CHECK: ret <4 x i16> [[NEG_I]]
uint16x4_t test_vmvn_u16(uint16x4_t a) {
return vmvn_u16(a);
}

// CHECK-LABEL: @test_vmvnq_u16(
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i16> %a, splat (i16 -1)
// CHECK: ret <8 x i16> [[NEG_I]]
uint16x8_t test_vmvnq_u16(uint16x8_t a) {
return vmvnq_u16(a);
}

// CHECK-LABEL: @test_vmvn_u32(
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %a, <i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <2 x i32> %a, splat (i32 -1)
// CHECK: ret <2 x i32> [[NEG_I]]
uint32x2_t test_vmvn_u32(uint32x2_t a) {
return vmvn_u32(a);
}

// CHECK-LABEL: @test_vmvnq_u32(
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK: [[NEG_I:%.*]] = xor <4 x i32> %a, splat (i32 -1)
// CHECK: ret <4 x i32> [[NEG_I]]
uint32x4_t test_vmvnq_u32(uint32x4_t a) {
return vmvnq_u32(a);
}

// CHECK-LABEL: @test_vmvn_p8(
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <8 x i8> %a, splat (i8 -1)
// CHECK: ret <8 x i8> [[NEG_I]]
poly8x8_t test_vmvn_p8(poly8x8_t a) {
return vmvn_p8(a);
}

// CHECK-LABEL: @test_vmvnq_p8(
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: [[NEG_I:%.*]] = xor <16 x i8> %a, splat (i8 -1)
// CHECK: ret <16 x i8> [[NEG_I]]
poly8x16_t test_vmvnq_p8(poly8x16_t a) {
return vmvnq_p8(a);
Expand Down Expand Up @@ -2076,7 +2076,7 @@ uint32x4_t test_vqmovn_high_u64(uint32x2_t a, uint64x2_t b) {

// CHECK-LABEL: @test_vshll_n_s8(
// CHECK: [[TMP0:%.*]] = sext <8 x i8> %a to <8 x i16>
// CHECK: [[VSHLL_N:%.*]] = shl <8 x i16> [[TMP0]], <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
// CHECK: [[VSHLL_N:%.*]] = shl <8 x i16> [[TMP0]], splat (i16 8)
// CHECK: ret <8 x i16> [[VSHLL_N]]
int16x8_t test_vshll_n_s8(int8x8_t a) {
return vshll_n_s8(a, 8);
Expand All @@ -2086,7 +2086,7 @@ int16x8_t test_vshll_n_s8(int8x8_t a) {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
// CHECK: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>
// CHECK: [[VSHLL_N:%.*]] = shl <4 x i32> [[TMP2]], <i32 16, i32 16, i32 16, i32 16>
// CHECK: [[VSHLL_N:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 16)
// CHECK: ret <4 x i32> [[VSHLL_N]]
int32x4_t test_vshll_n_s16(int16x4_t a) {
return vshll_n_s16(a, 16);
Expand All @@ -2096,15 +2096,15 @@ int32x4_t test_vshll_n_s16(int16x4_t a) {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
// CHECK: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
// CHECK: [[VSHLL_N:%.*]] = shl <2 x i64> [[TMP2]], <i64 32, i64 32>
// CHECK: [[VSHLL_N:%.*]] = shl <2 x i64> [[TMP2]], splat (i64 32)
// CHECK: ret <2 x i64> [[VSHLL_N]]
int64x2_t test_vshll_n_s32(int32x2_t a) {
return vshll_n_s32(a, 32);
}

// CHECK-LABEL: @test_vshll_n_u8(
// CHECK: [[TMP0:%.*]] = zext <8 x i8> %a to <8 x i16>
// CHECK: [[VSHLL_N:%.*]] = shl <8 x i16> [[TMP0]], <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
// CHECK: [[VSHLL_N:%.*]] = shl <8 x i16> [[TMP0]], splat (i16 8)
// CHECK: ret <8 x i16> [[VSHLL_N]]
uint16x8_t test_vshll_n_u8(uint8x8_t a) {
return vshll_n_u8(a, 8);
Expand All @@ -2114,7 +2114,7 @@ uint16x8_t test_vshll_n_u8(uint8x8_t a) {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
// CHECK: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
// CHECK: [[VSHLL_N:%.*]] = shl <4 x i32> [[TMP2]], <i32 16, i32 16, i32 16, i32 16>
// CHECK: [[VSHLL_N:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 16)
// CHECK: ret <4 x i32> [[VSHLL_N]]
uint32x4_t test_vshll_n_u16(uint16x4_t a) {
return vshll_n_u16(a, 16);
Expand All @@ -2124,7 +2124,7 @@ uint32x4_t test_vshll_n_u16(uint16x4_t a) {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
// CHECK: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
// CHECK: [[VSHLL_N:%.*]] = shl <2 x i64> [[TMP2]], <i64 32, i64 32>
// CHECK: [[VSHLL_N:%.*]] = shl <2 x i64> [[TMP2]], splat (i64 32)
// CHECK: ret <2 x i64> [[VSHLL_N]]
uint64x2_t test_vshll_n_u32(uint32x2_t a) {
return vshll_n_u32(a, 32);
Expand All @@ -2133,7 +2133,7 @@ uint64x2_t test_vshll_n_u32(uint32x2_t a) {
// CHECK-LABEL: @test_vshll_high_n_s8(
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: [[TMP0:%.*]] = sext <8 x i8> [[SHUFFLE_I]] to <8 x i16>
// CHECK: [[VSHLL_N:%.*]] = shl <8 x i16> [[TMP0]], <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
// CHECK: [[VSHLL_N:%.*]] = shl <8 x i16> [[TMP0]], splat (i16 8)
// CHECK: ret <8 x i16> [[VSHLL_N]]
int16x8_t test_vshll_high_n_s8(int8x16_t a) {
return vshll_high_n_s8(a, 8);
Expand All @@ -2144,7 +2144,7 @@ int16x8_t test_vshll_high_n_s8(int8x16_t a) {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
// CHECK: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>
// CHECK: [[VSHLL_N:%.*]] = shl <4 x i32> [[TMP2]], <i32 16, i32 16, i32 16, i32 16>
// CHECK: [[VSHLL_N:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 16)
// CHECK: ret <4 x i32> [[VSHLL_N]]
int32x4_t test_vshll_high_n_s16(int16x8_t a) {
return vshll_high_n_s16(a, 16);
Expand All @@ -2155,7 +2155,7 @@ int32x4_t test_vshll_high_n_s16(int16x8_t a) {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
// CHECK: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>
// CHECK: [[VSHLL_N:%.*]] = shl <2 x i64> [[TMP2]], <i64 32, i64 32>
// CHECK: [[VSHLL_N:%.*]] = shl <2 x i64> [[TMP2]], splat (i64 32)
// CHECK: ret <2 x i64> [[VSHLL_N]]
int64x2_t test_vshll_high_n_s32(int32x4_t a) {
return vshll_high_n_s32(a, 32);
Expand All @@ -2164,7 +2164,7 @@ int64x2_t test_vshll_high_n_s32(int32x4_t a) {
// CHECK-LABEL: @test_vshll_high_n_u8(
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %a, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK: [[TMP0:%.*]] = zext <8 x i8> [[SHUFFLE_I]] to <8 x i16>
// CHECK: [[VSHLL_N:%.*]] = shl <8 x i16> [[TMP0]], <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
// CHECK: [[VSHLL_N:%.*]] = shl <8 x i16> [[TMP0]], splat (i16 8)
// CHECK: ret <8 x i16> [[VSHLL_N]]
uint16x8_t test_vshll_high_n_u8(uint8x16_t a) {
return vshll_high_n_u8(a, 8);
Expand All @@ -2175,7 +2175,7 @@ uint16x8_t test_vshll_high_n_u8(uint8x16_t a) {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
// CHECK: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
// CHECK: [[VSHLL_N:%.*]] = shl <4 x i32> [[TMP2]], <i32 16, i32 16, i32 16, i32 16>
// CHECK: [[VSHLL_N:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 16)
// CHECK: ret <4 x i32> [[VSHLL_N]]
uint32x4_t test_vshll_high_n_u16(uint16x8_t a) {
return vshll_high_n_u16(a, 16);
Expand All @@ -2186,7 +2186,7 @@ uint32x4_t test_vshll_high_n_u16(uint16x8_t a) {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
// CHECK: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
// CHECK: [[VSHLL_N:%.*]] = shl <2 x i64> [[TMP2]], <i64 32, i64 32>
// CHECK: [[VSHLL_N:%.*]] = shl <2 x i64> [[TMP2]], splat (i64 32)
// CHECK: ret <2 x i64> [[VSHLL_N]]
uint64x2_t test_vshll_high_n_u32(uint32x4_t a) {
return vshll_high_n_u32(a, 32);
Expand Down
8 changes: 4 additions & 4 deletions clang/test/CodeGen/aarch64-neon-shifts.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,13 @@

uint8x8_t test_shift_vshr(uint8x8_t a) {
// CHECK-LABEL: test_shift_vshr
// CHECK: %{{.*}} = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
// CHECK: %{{.*}} = lshr <8 x i8> %a, splat (i8 5)
return vshr_n_u8(a, 5);
}

int8x8_t test_shift_vshr_smax(int8x8_t a) {
// CHECK-LABEL: test_shift_vshr_smax
// CHECK: %{{.*}} = ashr <8 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
// CHECK: %{{.*}} = ashr <8 x i8> %a, splat (i8 7)
return vshr_n_s8(a, 8);
}

Expand All @@ -25,14 +25,14 @@ uint8x8_t test_shift_vshr_umax(uint8x8_t a) {

uint8x8_t test_shift_vsra(uint8x8_t a, uint8x8_t b) {
// CHECK-LABEL: test_shift_vsra
// CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
// CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, splat (i8 5)
// CHECK: %{{.*}} = add <8 x i8> %a, %[[SHR]]
return vsra_n_u8(a, b, 5);
}

int8x8_t test_shift_vsra_smax(int8x8_t a, int8x8_t b) {
// CHECK-LABEL: test_shift_vsra_smax
// CHECK: %[[SHR:.*]] = ashr <8 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
// CHECK: %[[SHR:.*]] = ashr <8 x i8> %b, splat (i8 7)
// CHECK: %{{.*}} = add <8 x i8> %a, %[[SHR]]
return vsra_n_s8(a, b, 8);
}
Expand Down
24 changes: 12 additions & 12 deletions clang/test/CodeGen/aarch64-neon-tbl.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -245,10 +245,10 @@ int8x16_t test_vqtbl4q_s8(int8x16x4_t a, int8x16_t b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[VTBL1_I:%.*]] = shufflevector <8 x i8> [[B]], <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> [[C]])
// CHECK-NEXT: [[TMP0:%.*]] = icmp uge <8 x i8> [[C]], <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
// CHECK-NEXT: [[TMP0:%.*]] = icmp uge <8 x i8> [[C]], splat (i8 8)
// CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i1> [[TMP0]] to <8 x i8>
// CHECK-NEXT: [[TMP2:%.*]] = and <8 x i8> [[TMP1]], [[A]]
// CHECK-NEXT: [[TMP3:%.*]] = xor <8 x i8> [[TMP1]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP3:%.*]] = xor <8 x i8> [[TMP1]], splat (i8 -1)
// CHECK-NEXT: [[TMP4:%.*]] = and <8 x i8> [[TMP3]], [[VTBL11_I]]
// CHECK-NEXT: [[VTBX_I:%.*]] = or <8 x i8> [[TMP2]], [[TMP4]]
// CHECK-NEXT: ret <8 x i8> [[VTBX_I]]
Expand Down Expand Up @@ -296,10 +296,10 @@ int8x8_t test_vtbx2_s8(int8x8_t a, int8x8x2_t b, int8x8_t c) {
// CHECK-NEXT: [[VTBL2_I:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP2]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[VTBL25_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[VTBL26_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> [[VTBL2_I]], <16 x i8> [[VTBL25_I]], <8 x i8> [[C]])
// CHECK-NEXT: [[TMP4:%.*]] = icmp uge <8 x i8> [[C]], <i8 24, i8 24, i8 24, i8 24, i8 24, i8 24, i8 24, i8 24>
// CHECK-NEXT: [[TMP4:%.*]] = icmp uge <8 x i8> [[C]], splat (i8 24)
// CHECK-NEXT: [[TMP5:%.*]] = sext <8 x i1> [[TMP4]] to <8 x i8>
// CHECK-NEXT: [[TMP6:%.*]] = and <8 x i8> [[TMP5]], [[A]]
// CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i8> [[TMP5]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i8> [[TMP5]], splat (i8 -1)
// CHECK-NEXT: [[TMP8:%.*]] = and <8 x i8> [[TMP7]], [[VTBL26_I]]
// CHECK-NEXT: [[VTBX_I:%.*]] = or <8 x i8> [[TMP6]], [[TMP8]]
// CHECK-NEXT: ret <8 x i8> [[VTBX_I]]
Expand Down Expand Up @@ -725,10 +725,10 @@ uint8x16_t test_vqtbl4q_u8(uint8x16x4_t a, uint8x16_t b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[VTBL1_I:%.*]] = shufflevector <8 x i8> [[B]], <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> [[C]])
// CHECK-NEXT: [[TMP0:%.*]] = icmp uge <8 x i8> [[C]], <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
// CHECK-NEXT: [[TMP0:%.*]] = icmp uge <8 x i8> [[C]], splat (i8 8)
// CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i1> [[TMP0]] to <8 x i8>
// CHECK-NEXT: [[TMP2:%.*]] = and <8 x i8> [[TMP1]], [[A]]
// CHECK-NEXT: [[TMP3:%.*]] = xor <8 x i8> [[TMP1]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP3:%.*]] = xor <8 x i8> [[TMP1]], splat (i8 -1)
// CHECK-NEXT: [[TMP4:%.*]] = and <8 x i8> [[TMP3]], [[VTBL11_I]]
// CHECK-NEXT: [[VTBX_I:%.*]] = or <8 x i8> [[TMP2]], [[TMP4]]
// CHECK-NEXT: ret <8 x i8> [[VTBX_I]]
Expand Down Expand Up @@ -776,10 +776,10 @@ uint8x8_t test_vtbx2_u8(uint8x8_t a, uint8x8x2_t b, uint8x8_t c) {
// CHECK-NEXT: [[VTBL2_I:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP2]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[VTBL25_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[VTBL26_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> [[VTBL2_I]], <16 x i8> [[VTBL25_I]], <8 x i8> [[C]])
// CHECK-NEXT: [[TMP4:%.*]] = icmp uge <8 x i8> [[C]], <i8 24, i8 24, i8 24, i8 24, i8 24, i8 24, i8 24, i8 24>
// CHECK-NEXT: [[TMP4:%.*]] = icmp uge <8 x i8> [[C]], splat (i8 24)
// CHECK-NEXT: [[TMP5:%.*]] = sext <8 x i1> [[TMP4]] to <8 x i8>
// CHECK-NEXT: [[TMP6:%.*]] = and <8 x i8> [[TMP5]], [[A]]
// CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i8> [[TMP5]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i8> [[TMP5]], splat (i8 -1)
// CHECK-NEXT: [[TMP8:%.*]] = and <8 x i8> [[TMP7]], [[VTBL26_I]]
// CHECK-NEXT: [[VTBX_I:%.*]] = or <8 x i8> [[TMP6]], [[TMP8]]
// CHECK-NEXT: ret <8 x i8> [[VTBX_I]]
Expand Down Expand Up @@ -1205,10 +1205,10 @@ poly8x16_t test_vqtbl4q_p8(poly8x16x4_t a, uint8x16_t b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[VTBL1_I:%.*]] = shufflevector <8 x i8> [[B]], <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[VTBL11_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VTBL1_I]], <8 x i8> [[C]])
// CHECK-NEXT: [[TMP0:%.*]] = icmp uge <8 x i8> [[C]], <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>
// CHECK-NEXT: [[TMP0:%.*]] = icmp uge <8 x i8> [[C]], splat (i8 8)
// CHECK-NEXT: [[TMP1:%.*]] = sext <8 x i1> [[TMP0]] to <8 x i8>
// CHECK-NEXT: [[TMP2:%.*]] = and <8 x i8> [[TMP1]], [[A]]
// CHECK-NEXT: [[TMP3:%.*]] = xor <8 x i8> [[TMP1]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP3:%.*]] = xor <8 x i8> [[TMP1]], splat (i8 -1)
// CHECK-NEXT: [[TMP4:%.*]] = and <8 x i8> [[TMP3]], [[VTBL11_I]]
// CHECK-NEXT: [[VTBX_I:%.*]] = or <8 x i8> [[TMP2]], [[TMP4]]
// CHECK-NEXT: ret <8 x i8> [[VTBX_I]]
Expand Down Expand Up @@ -1256,10 +1256,10 @@ poly8x8_t test_vtbx2_p8(poly8x8_t a, poly8x8x2_t b, uint8x8_t c) {
// CHECK-NEXT: [[VTBL2_I:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> [[TMP2]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[VTBL25_I:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[VTBL26_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x i8> [[VTBL2_I]], <16 x i8> [[VTBL25_I]], <8 x i8> [[C]])
// CHECK-NEXT: [[TMP4:%.*]] = icmp uge <8 x i8> [[C]], <i8 24, i8 24, i8 24, i8 24, i8 24, i8 24, i8 24, i8 24>
// CHECK-NEXT: [[TMP4:%.*]] = icmp uge <8 x i8> [[C]], splat (i8 24)
// CHECK-NEXT: [[TMP5:%.*]] = sext <8 x i1> [[TMP4]] to <8 x i8>
// CHECK-NEXT: [[TMP6:%.*]] = and <8 x i8> [[TMP5]], [[A]]
// CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i8> [[TMP5]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i8> [[TMP5]], splat (i8 -1)
// CHECK-NEXT: [[TMP8:%.*]] = and <8 x i8> [[TMP7]], [[VTBL26_I]]
// CHECK-NEXT: [[VTBX_I:%.*]] = or <8 x i8> [[TMP6]], [[TMP8]]
// CHECK-NEXT: ret <8 x i8> [[VTBX_I]]
Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGen/aarch64-poly64.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@ uint64x2_t test_vtstq_p64(poly64x2_t a, poly64x2_t b) {

// CHECK-LABEL: define{{.*}} <1 x i64> @test_vbsl_p64(<1 x i64> noundef %a, <1 x i64> noundef %b, <1 x i64> noundef %c) #0 {
// CHECK: [[VBSL3_I:%.*]] = and <1 x i64> %a, %b
// CHECK: [[TMP3:%.*]] = xor <1 x i64> %a, <i64 -1>
// CHECK: [[TMP3:%.*]] = xor <1 x i64> %a, splat (i64 -1)
// CHECK: [[VBSL4_I:%.*]] = and <1 x i64> [[TMP3]], %c
// CHECK: [[VBSL5_I:%.*]] = or <1 x i64> [[VBSL3_I]], [[VBSL4_I]]
// CHECK: ret <1 x i64> [[VBSL5_I]]
Expand All @@ -52,7 +52,7 @@ poly64x1_t test_vbsl_p64(poly64x1_t a, poly64x1_t b, poly64x1_t c) {

// CHECK-LABEL: define{{.*}} <2 x i64> @test_vbslq_p64(<2 x i64> noundef %a, <2 x i64> noundef %b, <2 x i64> noundef %c) #0 {
// CHECK: [[VBSL3_I:%.*]] = and <2 x i64> %a, %b
// CHECK: [[TMP3:%.*]] = xor <2 x i64> %a, <i64 -1, i64 -1>
// CHECK: [[TMP3:%.*]] = xor <2 x i64> %a, splat (i64 -1)
// CHECK: [[VBSL4_I:%.*]] = and <2 x i64> [[TMP3]], %c
// CHECK: [[VBSL5_I:%.*]] = or <2 x i64> [[VBSL3_I]], [[VBSL4_I]]
// CHECK: ret <2 x i64> [[VBSL5_I]]
Expand Down
18 changes: 9 additions & 9 deletions clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -370,7 +370,7 @@ fixed_uint64_t xor_u64(fixed_uint64_t a, fixed_uint64_t b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_COERCE:%.*]] = bitcast <vscale x 16 x i1> [[TMP0:%.*]] to <vscale x 2 x i8>
// CHECK-NEXT: [[A:%.*]] = call <8 x i8> @llvm.vector.extract.v8i8.nxv2i8(<vscale x 2 x i8> [[A_COERCE]], i64 0)
// CHECK-NEXT: [[NOT:%.*]] = xor <8 x i8> [[A]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[NOT:%.*]] = xor <8 x i8> [[A]], splat (i8 -1)
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i8> @llvm.vector.insert.nxv2i8.v8i8(<vscale x 2 x i8> undef, <8 x i8> [[NOT]], i64 0)
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i8> [[CAST_SCALABLE]] to <vscale x 16 x i1>
// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
Expand All @@ -382,7 +382,7 @@ fixed_bool_t neg_bool(fixed_bool_t a) {
// CHECK-LABEL: @neg_i8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NOT:%.*]] = xor <64 x i8> [[A]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[NOT:%.*]] = xor <64 x i8> [[A]], splat (i8 -1)
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[NOT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CAST_SCALABLE]]
//
Expand All @@ -393,7 +393,7 @@ fixed_int8_t neg_i8(fixed_int8_t a) {
// CHECK-LABEL: @neg_i16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NOT:%.*]] = xor <32 x i16> [[A]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[NOT:%.*]] = xor <32 x i16> [[A]], splat (i16 -1)
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[NOT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CAST_SCALABLE]]
//
Expand All @@ -404,7 +404,7 @@ fixed_int16_t neg_i16(fixed_int16_t a) {
// CHECK-LABEL: @neg_i32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NOT:%.*]] = xor <16 x i32> [[A]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[NOT:%.*]] = xor <16 x i32> [[A]], splat (i32 -1)
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[NOT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CAST_SCALABLE]]
//
Expand All @@ -415,7 +415,7 @@ fixed_int32_t neg_i32(fixed_int32_t a) {
// CHECK-LABEL: @neg_i64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NOT:%.*]] = xor <8 x i64> [[A]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
// CHECK-NEXT: [[NOT:%.*]] = xor <8 x i64> [[A]], splat (i64 -1)
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[NOT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CAST_SCALABLE]]
//
Expand All @@ -426,7 +426,7 @@ fixed_int64_t neg_i64(fixed_int64_t a) {
// CHECK-LABEL: @neg_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <64 x i8> @llvm.vector.extract.v64i8.nxv16i8(<vscale x 16 x i8> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NOT:%.*]] = xor <64 x i8> [[A]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[NOT:%.*]] = xor <64 x i8> [[A]], splat (i8 -1)
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 16 x i8> @llvm.vector.insert.nxv16i8.v64i8(<vscale x 16 x i8> undef, <64 x i8> [[NOT]], i64 0)
// CHECK-NEXT: ret <vscale x 16 x i8> [[CAST_SCALABLE]]
//
Expand All @@ -437,7 +437,7 @@ fixed_uint8_t neg_u8(fixed_uint8_t a) {
// CHECK-LABEL: @neg_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <32 x i16> @llvm.vector.extract.v32i16.nxv8i16(<vscale x 8 x i16> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NOT:%.*]] = xor <32 x i16> [[A]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[NOT:%.*]] = xor <32 x i16> [[A]], splat (i16 -1)
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v32i16(<vscale x 8 x i16> undef, <32 x i16> [[NOT]], i64 0)
// CHECK-NEXT: ret <vscale x 8 x i16> [[CAST_SCALABLE]]
//
Expand All @@ -448,7 +448,7 @@ fixed_uint16_t neg_u16(fixed_uint16_t a) {
// CHECK-LABEL: @neg_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NOT:%.*]] = xor <16 x i32> [[A]], <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[NOT:%.*]] = xor <16 x i32> [[A]], splat (i32 -1)
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[NOT]], i64 0)
// CHECK-NEXT: ret <vscale x 4 x i32> [[CAST_SCALABLE]]
//
Expand All @@ -459,7 +459,7 @@ fixed_uint32_t neg_u32(fixed_uint32_t a) {
// CHECK-LABEL: @neg_u64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A:%.*]] = call <8 x i64> @llvm.vector.extract.v8i64.nxv2i64(<vscale x 2 x i64> [[A_COERCE:%.*]], i64 0)
// CHECK-NEXT: [[NOT:%.*]] = xor <8 x i64> [[A]], <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
// CHECK-NEXT: [[NOT:%.*]] = xor <8 x i64> [[A]], splat (i64 -1)
// CHECK-NEXT: [[CAST_SCALABLE:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v8i64(<vscale x 2 x i64> undef, <8 x i64> [[NOT]], i64 0)
// CHECK-NEXT: ret <vscale x 2 x i64> [[CAST_SCALABLE]]
//
Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics-generic.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@
// CHECK-NEXT: [[VBSL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16>
// CHECK-NEXT: [[VBSL2_I:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16>
// CHECK-NEXT: [[VBSL3_I:%.*]] = and <4 x i16> [[A]], [[VBSL1_I]]
// CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i16> [[A]], <i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i16> [[A]], splat (i16 -1)
// CHECK-NEXT: [[VBSL4_I:%.*]] = and <4 x i16> [[TMP3]], [[VBSL2_I]]
// CHECK-NEXT: [[VBSL5_I:%.*]] = or <4 x i16> [[VBSL3_I]], [[VBSL4_I]]
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[VBSL5_I]] to <4 x half>
Expand All @@ -40,7 +40,7 @@ float16x4_t test_vbsl_f16(uint16x4_t a, float16x4_t b, float16x4_t c) {
// CHECK-NEXT: [[VBSL1_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16>
// CHECK-NEXT: [[VBSL2_I:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16>
// CHECK-NEXT: [[VBSL3_I:%.*]] = and <8 x i16> [[A]], [[VBSL1_I]]
// CHECK-NEXT: [[TMP3:%.*]] = xor <8 x i16> [[A]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[TMP3:%.*]] = xor <8 x i16> [[A]], splat (i16 -1)
// CHECK-NEXT: [[VBSL4_I:%.*]] = and <8 x i16> [[TMP3]], [[VBSL2_I]]
// CHECK-NEXT: [[VBSL5_I:%.*]] = or <8 x i16> [[VBSL3_I]], [[VBSL4_I]]
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[VBSL5_I]] to <8 x half>
Expand Down
18 changes: 9 additions & 9 deletions clang/test/CodeGen/arm-bf16-convert-intrinsics.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@
// CHECK-A64-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[__REINT_836_I]], align 8
// CHECK-A64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
// CHECK-A64-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP0]] to <4 x i32>
// CHECK-A64-NEXT: [[VSHLL_N_I:%.*]] = shl <4 x i32> [[TMP2]], <i32 16, i32 16, i32 16, i32 16>
// CHECK-A64-NEXT: [[VSHLL_N_I:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 16)
// CHECK-A64-NEXT: store <4 x i32> [[VSHLL_N_I]], ptr [[__REINT1_836_I]], align 16
// CHECK-A64-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[__REINT1_836_I]], align 16
// CHECK-A64-NEXT: ret <4 x float> [[TMP3]]
Expand All @@ -43,7 +43,7 @@
// CHECK-A32-HARDFP-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[__REINT_836_I]], align 8
// CHECK-A32-HARDFP-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
// CHECK-A32-HARDFP-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP0]] to <4 x i32>
// CHECK-A32-HARDFP-NEXT: [[VSHLL_N_I:%.*]] = shl <4 x i32> [[TMP2]], <i32 16, i32 16, i32 16, i32 16>
// CHECK-A32-HARDFP-NEXT: [[VSHLL_N_I:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 16)
// CHECK-A32-HARDFP-NEXT: store <4 x i32> [[VSHLL_N_I]], ptr [[__REINT1_836_I]], align 8
// CHECK-A32-HARDFP-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[__REINT1_836_I]], align 8
// CHECK-A32-HARDFP-NEXT: ret <4 x float> [[TMP3]]
Expand All @@ -65,7 +65,7 @@
// CHECK-A32-SOFTFP-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[__REINT_836_I]], align 8
// CHECK-A32-SOFTFP-NEXT: [[TMP2:%.*]] = bitcast <4 x i16> [[TMP1]] to <8 x i8>
// CHECK-A32-SOFTFP-NEXT: [[TMP3:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>
// CHECK-A32-SOFTFP-NEXT: [[VSHLL_N_I:%.*]] = shl <4 x i32> [[TMP3]], <i32 16, i32 16, i32 16, i32 16>
// CHECK-A32-SOFTFP-NEXT: [[VSHLL_N_I:%.*]] = shl <4 x i32> [[TMP3]], splat (i32 16)
// CHECK-A32-SOFTFP-NEXT: store <4 x i32> [[VSHLL_N_I]], ptr [[__REINT1_836_I]], align 8
// CHECK-A32-SOFTFP-NEXT: [[TMP4:%.*]] = load <4 x float>, ptr [[__REINT1_836_I]], align 8
// CHECK-A32-SOFTFP-NEXT: ret <4 x float> [[TMP4]]
Expand All @@ -83,7 +83,7 @@ float32x4_t test_vcvt_f32_bf16(bfloat16x4_t a) {
// CHECK-A64-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[__REINT_836_I_I]], align 8
// CHECK-A64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
// CHECK-A64-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP0]] to <4 x i32>
// CHECK-A64-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP2]], <i32 16, i32 16, i32 16, i32 16>
// CHECK-A64-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 16)
// CHECK-A64-NEXT: store <4 x i32> [[VSHLL_N_I_I]], ptr [[__REINT1_836_I_I]], align 16
// CHECK-A64-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[__REINT1_836_I_I]], align 16
// CHECK-A64-NEXT: ret <4 x float> [[TMP3]]
Expand All @@ -97,7 +97,7 @@ float32x4_t test_vcvt_f32_bf16(bfloat16x4_t a) {
// CHECK-A32-HARDFP-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[__REINT_836_I_I]], align 8
// CHECK-A32-HARDFP-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
// CHECK-A32-HARDFP-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP0]] to <4 x i32>
// CHECK-A32-HARDFP-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP2]], <i32 16, i32 16, i32 16, i32 16>
// CHECK-A32-HARDFP-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 16)
// CHECK-A32-HARDFP-NEXT: store <4 x i32> [[VSHLL_N_I_I]], ptr [[__REINT1_836_I_I]], align 8
// CHECK-A32-HARDFP-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[__REINT1_836_I_I]], align 8
// CHECK-A32-HARDFP-NEXT: ret <4 x float> [[TMP3]]
Expand Down Expand Up @@ -138,7 +138,7 @@ float32x4_t test_vcvt_f32_bf16(bfloat16x4_t a) {
// CHECK-A32-SOFTFP-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr [[__REINT_836_I_I]], align 8
// CHECK-A32-SOFTFP-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP5]] to <8 x i8>
// CHECK-A32-SOFTFP-NEXT: [[TMP7:%.*]] = sext <4 x i16> [[TMP5]] to <4 x i32>
// CHECK-A32-SOFTFP-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP7]], <i32 16, i32 16, i32 16, i32 16>
// CHECK-A32-SOFTFP-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP7]], splat (i32 16)
// CHECK-A32-SOFTFP-NEXT: store <4 x i32> [[VSHLL_N_I_I]], ptr [[__REINT1_836_I_I]], align 8
// CHECK-A32-SOFTFP-NEXT: [[TMP8:%.*]] = load <4 x float>, ptr [[__REINT1_836_I_I]], align 8
// CHECK-A32-SOFTFP-NEXT: ret <4 x float> [[TMP8]]
Expand All @@ -156,7 +156,7 @@ float32x4_t test_vcvtq_low_f32_bf16(bfloat16x8_t a) {
// CHECK-A64-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[__REINT_836_I_I]], align 8
// CHECK-A64-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
// CHECK-A64-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP0]] to <4 x i32>
// CHECK-A64-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP2]], <i32 16, i32 16, i32 16, i32 16>
// CHECK-A64-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 16)
// CHECK-A64-NEXT: store <4 x i32> [[VSHLL_N_I_I]], ptr [[__REINT1_836_I_I]], align 16
// CHECK-A64-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[__REINT1_836_I_I]], align 16
// CHECK-A64-NEXT: ret <4 x float> [[TMP3]]
Expand All @@ -170,7 +170,7 @@ float32x4_t test_vcvtq_low_f32_bf16(bfloat16x8_t a) {
// CHECK-A32-HARDFP-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr [[__REINT_836_I_I]], align 8
// CHECK-A32-HARDFP-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
// CHECK-A32-HARDFP-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP0]] to <4 x i32>
// CHECK-A32-HARDFP-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP2]], <i32 16, i32 16, i32 16, i32 16>
// CHECK-A32-HARDFP-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 16)
// CHECK-A32-HARDFP-NEXT: store <4 x i32> [[VSHLL_N_I_I]], ptr [[__REINT1_836_I_I]], align 8
// CHECK-A32-HARDFP-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[__REINT1_836_I_I]], align 8
// CHECK-A32-HARDFP-NEXT: ret <4 x float> [[TMP3]]
Expand Down Expand Up @@ -211,7 +211,7 @@ float32x4_t test_vcvtq_low_f32_bf16(bfloat16x8_t a) {
// CHECK-A32-SOFTFP-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr [[__REINT_836_I_I]], align 8
// CHECK-A32-SOFTFP-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[TMP5]] to <8 x i8>
// CHECK-A32-SOFTFP-NEXT: [[TMP7:%.*]] = sext <4 x i16> [[TMP5]] to <4 x i32>
// CHECK-A32-SOFTFP-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP7]], <i32 16, i32 16, i32 16, i32 16>
// CHECK-A32-SOFTFP-NEXT: [[VSHLL_N_I_I:%.*]] = shl <4 x i32> [[TMP7]], splat (i32 16)
// CHECK-A32-SOFTFP-NEXT: store <4 x i32> [[VSHLL_N_I_I]], ptr [[__REINT1_836_I_I]], align 8
// CHECK-A32-SOFTFP-NEXT: [[TMP8:%.*]] = load <4 x float>, ptr [[__REINT1_836_I_I]], align 8
// CHECK-A32-SOFTFP-NEXT: ret <4 x float> [[TMP8]]
Expand Down
36 changes: 18 additions & 18 deletions clang/test/CodeGen/arm-mve-intrinsics/absneg.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,7 @@ int32x4_t test_vabsq_s32(int32x4_t a)

// CHECK-LABEL: @test_vmvnq_s8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[A:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[A:%.*]], splat (i8 -1)
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
int8x16_t test_vmvnq_s8(int8x16_t a)
Expand All @@ -98,7 +98,7 @@ int8x16_t test_vmvnq_s8(int8x16_t a)

// CHECK-LABEL: @test_vmvnq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[A:%.*]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[A:%.*]], splat (i16 -1)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vmvnq_s16(int16x8_t a)
Expand All @@ -112,7 +112,7 @@ int16x8_t test_vmvnq_s16(int16x8_t a)

// CHECK-LABEL: @test_vmvnq_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[A:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[A:%.*]], splat (i32 -1)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
int32x4_t test_vmvnq_s32(int32x4_t a)
Expand All @@ -126,7 +126,7 @@ int32x4_t test_vmvnq_s32(int32x4_t a)

// CHECK-LABEL: @test_vmvnq_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[A:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[A:%.*]], splat (i8 -1)
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
uint8x16_t test_vmvnq_u8(uint8x16_t a)
Expand All @@ -140,7 +140,7 @@ uint8x16_t test_vmvnq_u8(uint8x16_t a)

// CHECK-LABEL: @test_vmvnq_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[A:%.*]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[A:%.*]], splat (i16 -1)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
uint16x8_t test_vmvnq_u16(uint16x8_t a)
Expand All @@ -154,7 +154,7 @@ uint16x8_t test_vmvnq_u16(uint16x8_t a)

// CHECK-LABEL: @test_vmvnq_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[A:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[A:%.*]], splat (i32 -1)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
uint32x4_t test_vmvnq_u32(uint32x4_t a)
Expand Down Expand Up @@ -431,9 +431,9 @@ int32x4_t test_vnegq_s32(int32x4_t a)
// CHECK-LABEL: @test_vqabsq_s8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = icmp sgt <16 x i8> [[A:%.*]], zeroinitializer
// CHECK-NEXT: [[TMP1:%.*]] = icmp eq <16 x i8> [[A]], <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
// CHECK-NEXT: [[TMP1:%.*]] = icmp eq <16 x i8> [[A]], splat (i8 -128)
// CHECK-NEXT: [[TMP2:%.*]] = sub <16 x i8> zeroinitializer, [[A]]
// CHECK-NEXT: [[TMP3:%.*]] = select <16 x i1> [[TMP1]], <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>, <16 x i8> [[TMP2]]
// CHECK-NEXT: [[TMP3:%.*]] = select <16 x i1> [[TMP1]], <16 x i8> splat (i8 127), <16 x i8> [[TMP2]]
// CHECK-NEXT: [[TMP4:%.*]] = select <16 x i1> [[TMP0]], <16 x i8> [[A]], <16 x i8> [[TMP3]]
// CHECK-NEXT: ret <16 x i8> [[TMP4]]
//
Expand All @@ -449,9 +449,9 @@ int8x16_t test_vqabsq_s8(int8x16_t a)
// CHECK-LABEL: @test_vqabsq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = icmp sgt <8 x i16> [[A:%.*]], zeroinitializer
// CHECK-NEXT: [[TMP1:%.*]] = icmp eq <8 x i16> [[A]], <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
// CHECK-NEXT: [[TMP1:%.*]] = icmp eq <8 x i16> [[A]], splat (i16 -32768)
// CHECK-NEXT: [[TMP2:%.*]] = sub <8 x i16> zeroinitializer, [[A]]
// CHECK-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>, <8 x i16> [[TMP2]]
// CHECK-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> splat (i16 32767), <8 x i16> [[TMP2]]
// CHECK-NEXT: [[TMP4:%.*]] = select <8 x i1> [[TMP0]], <8 x i16> [[A]], <8 x i16> [[TMP3]]
// CHECK-NEXT: ret <8 x i16> [[TMP4]]
//
Expand All @@ -467,9 +467,9 @@ int16x8_t test_vqabsq_s16(int16x8_t a)
// CHECK-LABEL: @test_vqabsq_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = icmp sgt <4 x i32> [[A:%.*]], zeroinitializer
// CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[A]], <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
// CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[A]], splat (i32 -2147483648)
// CHECK-NEXT: [[TMP2:%.*]] = sub <4 x i32> zeroinitializer, [[A]]
// CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> [[TMP2]]
// CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> splat (i32 2147483647), <4 x i32> [[TMP2]]
// CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> [[A]], <4 x i32> [[TMP3]]
// CHECK-NEXT: ret <4 x i32> [[TMP4]]
//
Expand All @@ -484,9 +484,9 @@ int32x4_t test_vqabsq_s32(int32x4_t a)

// CHECK-LABEL: @test_vqnegq_s8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = icmp eq <16 x i8> [[A:%.*]], <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
// CHECK-NEXT: [[TMP0:%.*]] = icmp eq <16 x i8> [[A:%.*]], splat (i8 -128)
// CHECK-NEXT: [[TMP1:%.*]] = sub <16 x i8> zeroinitializer, [[A]]
// CHECK-NEXT: [[TMP2:%.*]] = select <16 x i1> [[TMP0]], <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>, <16 x i8> [[TMP1]]
// CHECK-NEXT: [[TMP2:%.*]] = select <16 x i1> [[TMP0]], <16 x i8> splat (i8 127), <16 x i8> [[TMP1]]
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
int8x16_t test_vqnegq_s8(int8x16_t a)
Expand All @@ -500,9 +500,9 @@ int8x16_t test_vqnegq_s8(int8x16_t a)

// CHECK-LABEL: @test_vqnegq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = icmp eq <8 x i16> [[A:%.*]], <i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768, i16 -32768>
// CHECK-NEXT: [[TMP0:%.*]] = icmp eq <8 x i16> [[A:%.*]], splat (i16 -32768)
// CHECK-NEXT: [[TMP1:%.*]] = sub <8 x i16> zeroinitializer, [[A]]
// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP0]], <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>, <8 x i16> [[TMP1]]
// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP0]], <8 x i16> splat (i16 32767), <8 x i16> [[TMP1]]
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vqnegq_s16(int16x8_t a)
Expand All @@ -516,9 +516,9 @@ int16x8_t test_vqnegq_s16(int16x8_t a)

// CHECK-LABEL: @test_vqnegq_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = icmp eq <4 x i32> [[A:%.*]], <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648>
// CHECK-NEXT: [[TMP0:%.*]] = icmp eq <4 x i32> [[A:%.*]], splat (i32 -2147483648)
// CHECK-NEXT: [[TMP1:%.*]] = sub <4 x i32> zeroinitializer, [[A]]
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>, <4 x i32> [[TMP1]]
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP0]], <4 x i32> splat (i32 2147483647), <4 x i32> [[TMP1]]
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vqnegq_s32(int32x4_t a)
Expand Down
56 changes: 28 additions & 28 deletions clang/test/CodeGen/arm-mve-intrinsics/bitwise-imm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@

// CHECK-LABEL: @test_vbicq_n_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = and <8 x i16> [[A:%.*]], <i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007>
// CHECK-NEXT: [[TMP0:%.*]] = and <8 x i16> [[A:%.*]], splat (i16 11007)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vbicq_n_s16(int16x8_t a)
Expand All @@ -22,7 +22,7 @@ int16x8_t test_vbicq_n_s16(int16x8_t a)

// CHECK-LABEL: @test_vbicq_n_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], <i32 -252, i32 -252, i32 -252, i32 -252>
// CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], splat (i32 -252)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
int32x4_t test_vbicq_n_s32(int32x4_t a)
Expand All @@ -36,7 +36,7 @@ int32x4_t test_vbicq_n_s32(int32x4_t a)

// CHECK-LABEL: @test_vbicq_n_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = and <8 x i16> [[A:%.*]], <i16 -243, i16 -243, i16 -243, i16 -243, i16 -243, i16 -243, i16 -243, i16 -243>
// CHECK-NEXT: [[TMP0:%.*]] = and <8 x i16> [[A:%.*]], splat (i16 -243)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
uint16x8_t test_vbicq_n_u16(uint16x8_t a)
Expand All @@ -50,7 +50,7 @@ uint16x8_t test_vbicq_n_u16(uint16x8_t a)

// CHECK-LABEL: @test_vbicq_n_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], <i32 -8193, i32 -8193, i32 -8193, i32 -8193>
// CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], splat (i32 -8193)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
uint32x4_t test_vbicq_n_u32(uint32x4_t a)
Expand All @@ -64,7 +64,7 @@ uint32x4_t test_vbicq_n_u32(uint32x4_t a)

// CHECK-LABEL: @test_vorrq_n_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = or <8 x i16> [[A:%.*]], <i16 195, i16 195, i16 195, i16 195, i16 195, i16 195, i16 195, i16 195>
// CHECK-NEXT: [[TMP0:%.*]] = or <8 x i16> [[A:%.*]], splat (i16 195)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vorrq_n_s16(int16x8_t a)
Expand All @@ -78,7 +78,7 @@ int16x8_t test_vorrq_n_s16(int16x8_t a)

// CHECK-LABEL: @test_vorrq_n_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], <i32 65536, i32 65536, i32 65536, i32 65536>
// CHECK-NEXT: [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], splat (i32 65536)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
int32x4_t test_vorrq_n_s32(int32x4_t a)
Expand All @@ -92,7 +92,7 @@ int32x4_t test_vorrq_n_s32(int32x4_t a)

// CHECK-LABEL: @test_vorrq_n_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = or <8 x i16> [[A:%.*]], <i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096>
// CHECK-NEXT: [[TMP0:%.*]] = or <8 x i16> [[A:%.*]], splat (i16 -4096)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
uint16x8_t test_vorrq_n_u16(uint16x8_t a)
Expand All @@ -106,7 +106,7 @@ uint16x8_t test_vorrq_n_u16(uint16x8_t a)

// CHECK-LABEL: @test_vorrq_n_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], <i32 8978432, i32 8978432, i32 8978432, i32 8978432>
// CHECK-NEXT: [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], splat (i32 8978432)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
uint32x4_t test_vorrq_n_u32(uint32x4_t a)
Expand All @@ -120,7 +120,7 @@ uint32x4_t test_vorrq_n_u32(uint32x4_t a)

// CHECK-LABEL: @test_vmvnq_n_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret <8 x i16> <i16 27391, i16 27391, i16 27391, i16 27391, i16 27391, i16 27391, i16 27391, i16 27391>
// CHECK-NEXT: ret <8 x i16> splat (i16 27391)
//
int16x8_t test_vmvnq_n_s16()
{
Expand All @@ -129,7 +129,7 @@ int16x8_t test_vmvnq_n_s16()

// CHECK-LABEL: @test_vmvnq_n_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret <4 x i32> <i32 -5570561, i32 -5570561, i32 -5570561, i32 -5570561>
// CHECK-NEXT: ret <4 x i32> splat (i32 -5570561)
//
int32x4_t test_vmvnq_n_s32()
{
Expand All @@ -138,7 +138,7 @@ int32x4_t test_vmvnq_n_s32()

// CHECK-LABEL: @test_vmvnq_n_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret <8 x i16> <i16 -18689, i16 -18689, i16 -18689, i16 -18689, i16 -18689, i16 -18689, i16 -18689, i16 -18689>
// CHECK-NEXT: ret <8 x i16> splat (i16 -18689)
//
uint16x8_t test_vmvnq_n_u16()
{
Expand All @@ -147,7 +147,7 @@ uint16x8_t test_vmvnq_n_u16()

// CHECK-LABEL: @test_vmvnq_n_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: ret <4 x i32> <i32 1023410175, i32 1023410175, i32 1023410175, i32 1023410175>
// CHECK-NEXT: ret <4 x i32> splat (i32 1023410175)
//
uint32x4_t test_vmvnq_n_u32()
{
Expand All @@ -158,7 +158,7 @@ uint32x4_t test_vmvnq_n_u32()
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = and <8 x i16> [[A:%.*]], <i16 -11265, i16 -11265, i16 -11265, i16 -11265, i16 -11265, i16 -11265, i16 -11265, i16 -11265>
// CHECK-NEXT: [[TMP2:%.*]] = and <8 x i16> [[A:%.*]], splat (i16 -11265)
// CHECK-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> [[TMP2]], <8 x i16> [[A]]
// CHECK-NEXT: ret <8 x i16> [[TMP3]]
//
Expand All @@ -175,7 +175,7 @@ int16x8_t test_vbicq_m_n_s16(int16x8_t a, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[A:%.*]], <i32 -13893633, i32 -13893633, i32 -13893633, i32 -13893633>
// CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[A:%.*]], splat (i32 -13893633)
// CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[A]]
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
//
Expand All @@ -192,7 +192,7 @@ int32x4_t test_vbicq_m_n_s32(int32x4_t a, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = and <8 x i16> [[A:%.*]], <i16 -37, i16 -37, i16 -37, i16 -37, i16 -37, i16 -37, i16 -37, i16 -37>
// CHECK-NEXT: [[TMP2:%.*]] = and <8 x i16> [[A:%.*]], splat (i16 -37)
// CHECK-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> [[TMP2]], <8 x i16> [[A]]
// CHECK-NEXT: ret <8 x i16> [[TMP3]]
//
Expand All @@ -209,7 +209,7 @@ uint16x8_t test_vbicq_m_n_u16(uint16x8_t a, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[A:%.*]], <i32 -1644167169, i32 -1644167169, i32 -1644167169, i32 -1644167169>
// CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[A:%.*]], splat (i32 -1644167169)
// CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[A]]
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
//
Expand All @@ -226,7 +226,7 @@ uint32x4_t test_vbicq_m_n_u32(uint32x4_t a, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = or <8 x i16> [[A:%.*]], <i16 13568, i16 13568, i16 13568, i16 13568, i16 13568, i16 13568, i16 13568, i16 13568>
// CHECK-NEXT: [[TMP2:%.*]] = or <8 x i16> [[A:%.*]], splat (i16 13568)
// CHECK-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> [[TMP2]], <8 x i16> [[A]]
// CHECK-NEXT: ret <8 x i16> [[TMP3]]
//
Expand All @@ -243,7 +243,7 @@ int16x8_t test_vorrq_m_n_s16(int16x8_t a, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[A:%.*]], <i32 654311424, i32 654311424, i32 654311424, i32 654311424>
// CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[A:%.*]], splat (i32 654311424)
// CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[A]]
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
//
Expand All @@ -260,7 +260,7 @@ int32x4_t test_vorrq_m_n_s32(int32x4_t a, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = or <8 x i16> [[A:%.*]], <i16 175, i16 175, i16 175, i16 175, i16 175, i16 175, i16 175, i16 175>
// CHECK-NEXT: [[TMP2:%.*]] = or <8 x i16> [[A:%.*]], splat (i16 175)
// CHECK-NEXT: [[TMP3:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> [[TMP2]], <8 x i16> [[A]]
// CHECK-NEXT: ret <8 x i16> [[TMP3]]
//
Expand All @@ -277,7 +277,7 @@ uint16x8_t test_vorrq_m_n_u16(uint16x8_t a, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[A:%.*]], <i32 89, i32 89, i32 89, i32 89>
// CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[A:%.*]], splat (i32 89)
// CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> [[A]]
// CHECK-NEXT: ret <4 x i32> [[TMP3]]
//
Expand All @@ -294,7 +294,7 @@ uint32x4_t test_vorrq_m_n_u32(uint32x4_t a, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> <i16 -3841, i16 -3841, i16 -3841, i16 -3841, i16 -3841, i16 -3841, i16 -3841, i16 -3841>, <8 x i16> [[INACTIVE:%.*]]
// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> splat (i16 -3841), <8 x i16> [[INACTIVE:%.*]]
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vmvnq_m_n_s16(int16x8_t inactive, mve_pred16_t p)
Expand All @@ -310,7 +310,7 @@ int16x8_t test_vmvnq_m_n_s16(int16x8_t inactive, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -18945, i32 -18945, i32 -18945, i32 -18945>, <4 x i32> [[INACTIVE:%.*]]
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> splat (i32 -18945), <4 x i32> [[INACTIVE:%.*]]
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vmvnq_m_n_s32(int32x4_t inactive, mve_pred16_t p)
Expand All @@ -326,7 +326,7 @@ int32x4_t test_vmvnq_m_n_s32(int32x4_t inactive, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> <i16 23295, i16 23295, i16 23295, i16 23295, i16 23295, i16 23295, i16 23295, i16 23295>, <8 x i16> [[INACTIVE:%.*]]
// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> splat (i16 23295), <8 x i16> [[INACTIVE:%.*]]
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vmvnq_m_n_u16(uint16x8_t inactive, mve_pred16_t p)
Expand All @@ -342,7 +342,7 @@ uint16x8_t test_vmvnq_m_n_u16(uint16x8_t inactive, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -63489, i32 -63489, i32 -63489, i32 -63489>, <4 x i32> [[INACTIVE:%.*]]
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> splat (i32 -63489), <4 x i32> [[INACTIVE:%.*]]
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vmvnq_m_n_u32(uint32x4_t inactive, mve_pred16_t p)
Expand All @@ -358,7 +358,7 @@ uint32x4_t test_vmvnq_m_n_u32(uint32x4_t inactive, mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> <i16 767, i16 767, i16 767, i16 767, i16 767, i16 767, i16 767, i16 767>, <8 x i16> undef
// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> splat (i16 767), <8 x i16> undef
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vmvnq_x_n_s16(mve_pred16_t p)
Expand All @@ -370,7 +370,7 @@ int16x8_t test_vmvnq_x_n_s16(mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -12189697, i32 -12189697, i32 -12189697, i32 -12189697>, <4 x i32> undef
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> splat (i32 -12189697), <4 x i32> undef
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vmvnq_x_n_s32(mve_pred16_t p)
Expand All @@ -382,7 +382,7 @@ int32x4_t test_vmvnq_x_n_s32(mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> <i16 -21505, i16 -21505, i16 -21505, i16 -21505, i16 -21505, i16 -21505, i16 -21505, i16 -21505>, <8 x i16> undef
// CHECK-NEXT: [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> splat (i16 -21505), <8 x i16> undef
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vmvnq_x_n_u16(mve_pred16_t p)
Expand All @@ -394,7 +394,7 @@ uint16x8_t test_vmvnq_x_n_u16(mve_pred16_t p)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -4865, i32 -4865, i32 -4865, i32 -4865>, <4 x i32> undef
// CHECK-NEXT: [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> splat (i32 -4865), <4 x i32> undef
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vmvnq_x_n_u32(mve_pred16_t p)
Expand Down
8 changes: 4 additions & 4 deletions clang/test/CodeGen/arm-mve-intrinsics/cplusplus.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@

// CHECK-LABEL: @_Z16test_vbicq_n_s1617__simd128_int16_t(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = and <8 x i16> [[A:%.*]], <i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007>
// CHECK-NEXT: [[TMP0:%.*]] = and <8 x i16> [[A:%.*]], splat (i16 11007)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vbicq_n_s16(int16x8_t a)
Expand All @@ -22,7 +22,7 @@ int16x8_t test_vbicq_n_s16(int16x8_t a)

// CHECK-LABEL: @_Z16test_vbicq_n_u3218__simd128_uint32_t(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], <i32 -8193, i32 -8193, i32 -8193, i32 -8193>
// CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], splat (i32 -8193)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
uint32x4_t test_vbicq_n_u32(uint32x4_t a)
Expand All @@ -36,7 +36,7 @@ uint32x4_t test_vbicq_n_u32(uint32x4_t a)

// CHECK-LABEL: @_Z16test_vorrq_n_s3217__simd128_int32_t(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], <i32 65536, i32 65536, i32 65536, i32 65536>
// CHECK-NEXT: [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], splat (i32 65536)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
int32x4_t test_vorrq_n_s32(int32x4_t a)
Expand All @@ -50,7 +50,7 @@ int32x4_t test_vorrq_n_s32(int32x4_t a)

// CHECK-LABEL: @_Z16test_vorrq_n_u1618__simd128_uint16_t(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = or <8 x i16> [[A:%.*]], <i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096>
// CHECK-NEXT: [[TMP0:%.*]] = or <8 x i16> [[A:%.*]], splat (i16 -4096)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
uint16x8_t test_vorrq_n_u16(uint16x8_t a)
Expand Down
8 changes: 4 additions & 4 deletions clang/test/CodeGen/arm-mve-intrinsics/vbicq.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@

// CHECK-LABEL: @test_vbicq_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[B:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[B:%.*]], splat (i8 -1)
// CHECK-NEXT: [[TMP1:%.*]] = and <16 x i8> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <16 x i8> [[TMP1]]
//
Expand All @@ -23,7 +23,7 @@ uint8x16_t test_vbicq_u8(uint8x16_t a, uint8x16_t b)

// CHECK-LABEL: @test_vbicq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[B:%.*]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[B:%.*]], splat (i16 -1)
// CHECK-NEXT: [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <8 x i16> [[TMP1]]
//
Expand All @@ -38,7 +38,7 @@ int16x8_t test_vbicq_s16(int16x8_t a, int16x8_t b)

// CHECK-LABEL: @test_vbicq_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[B:%.*]], splat (i32 -1)
// CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <4 x i32> [[TMP1]]
//
Expand All @@ -55,7 +55,7 @@ uint32x4_t test_vbicq_u32(uint32x4_t a, uint32x4_t b)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i32> [[TMP1]], <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i32> [[TMP1]], splat (i32 -1)
// CHECK-NEXT: [[TMP3:%.*]] = and <4 x i32> [[TMP0]], [[TMP2]]
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[TMP4]]
Expand Down
30 changes: 15 additions & 15 deletions clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@

// CHECK-LABEL: @test_vshlq_n_s8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = shl <16 x i8> [[A:%.*]], <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
// CHECK-NEXT: [[TMP0:%.*]] = shl <16 x i8> [[A:%.*]], splat (i8 5)
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
int8x16_t test_vshlq_n_s8(int8x16_t a)
Expand All @@ -22,7 +22,7 @@ int8x16_t test_vshlq_n_s8(int8x16_t a)

// CHECK-LABEL: @test_vshlq_n_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = shl <8 x i16> [[A:%.*]], <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
// CHECK-NEXT: [[TMP0:%.*]] = shl <8 x i16> [[A:%.*]], splat (i16 5)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vshlq_n_s16(int16x8_t a)
Expand All @@ -36,7 +36,7 @@ int16x8_t test_vshlq_n_s16(int16x8_t a)

// CHECK-LABEL: @test_vshlq_n_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = shl <4 x i32> [[A:%.*]], <i32 18, i32 18, i32 18, i32 18>
// CHECK-NEXT: [[TMP0:%.*]] = shl <4 x i32> [[A:%.*]], splat (i32 18)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
int32x4_t test_vshlq_n_s32(int32x4_t a)
Expand Down Expand Up @@ -92,7 +92,7 @@ int32x4_t test_vshlq_n_s32_trivial(int32x4_t a)

// CHECK-LABEL: @test_vshlq_n_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = shl <16 x i8> [[A:%.*]], <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
// CHECK-NEXT: [[TMP0:%.*]] = shl <16 x i8> [[A:%.*]], splat (i8 3)
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
uint8x16_t test_vshlq_n_u8(uint8x16_t a)
Expand All @@ -106,7 +106,7 @@ uint8x16_t test_vshlq_n_u8(uint8x16_t a)

// CHECK-LABEL: @test_vshlq_n_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = shl <8 x i16> [[A:%.*]], <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
// CHECK-NEXT: [[TMP0:%.*]] = shl <8 x i16> [[A:%.*]], splat (i16 11)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
uint16x8_t test_vshlq_n_u16(uint16x8_t a)
Expand All @@ -120,7 +120,7 @@ uint16x8_t test_vshlq_n_u16(uint16x8_t a)

// CHECK-LABEL: @test_vshlq_n_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = shl <4 x i32> [[A:%.*]], <i32 7, i32 7, i32 7, i32 7>
// CHECK-NEXT: [[TMP0:%.*]] = shl <4 x i32> [[A:%.*]], splat (i32 7)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
uint32x4_t test_vshlq_n_u32(uint32x4_t a)
Expand Down Expand Up @@ -176,7 +176,7 @@ uint32x4_t test_vshlq_n_u32_trivial(uint32x4_t a)

// CHECK-LABEL: @test_vshrq_n_s8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = ashr <16 x i8> [[A:%.*]], <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
// CHECK-NEXT: [[TMP0:%.*]] = ashr <16 x i8> [[A:%.*]], splat (i8 4)
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
int8x16_t test_vshrq_n_s8(int8x16_t a)
Expand All @@ -190,7 +190,7 @@ int8x16_t test_vshrq_n_s8(int8x16_t a)

// CHECK-LABEL: @test_vshrq_n_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = ashr <8 x i16> [[A:%.*]], <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
// CHECK-NEXT: [[TMP0:%.*]] = ashr <8 x i16> [[A:%.*]], splat (i16 10)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vshrq_n_s16(int16x8_t a)
Expand All @@ -204,7 +204,7 @@ int16x8_t test_vshrq_n_s16(int16x8_t a)

// CHECK-LABEL: @test_vshrq_n_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = ashr <4 x i32> [[A:%.*]], <i32 19, i32 19, i32 19, i32 19>
// CHECK-NEXT: [[TMP0:%.*]] = ashr <4 x i32> [[A:%.*]], splat (i32 19)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
int32x4_t test_vshrq_n_s32(int32x4_t a)
Expand All @@ -218,7 +218,7 @@ int32x4_t test_vshrq_n_s32(int32x4_t a)

// CHECK-LABEL: @test_vshrq_n_s8_trivial(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = ashr <16 x i8> [[A:%.*]], <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
// CHECK-NEXT: [[TMP0:%.*]] = ashr <16 x i8> [[A:%.*]], splat (i8 7)
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
int8x16_t test_vshrq_n_s8_trivial(int8x16_t a)
Expand All @@ -232,7 +232,7 @@ int8x16_t test_vshrq_n_s8_trivial(int8x16_t a)

// CHECK-LABEL: @test_vshrq_n_s16_trivial(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = ashr <8 x i16> [[A:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
// CHECK-NEXT: [[TMP0:%.*]] = ashr <8 x i16> [[A:%.*]], splat (i16 15)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vshrq_n_s16_trivial(int16x8_t a)
Expand All @@ -246,7 +246,7 @@ int16x8_t test_vshrq_n_s16_trivial(int16x8_t a)

// CHECK-LABEL: @test_vshrq_n_s32_trivial(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = ashr <4 x i32> [[A:%.*]], <i32 31, i32 31, i32 31, i32 31>
// CHECK-NEXT: [[TMP0:%.*]] = ashr <4 x i32> [[A:%.*]], splat (i32 31)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
int32x4_t test_vshrq_n_s32_trivial(int32x4_t a)
Expand All @@ -260,7 +260,7 @@ int32x4_t test_vshrq_n_s32_trivial(int32x4_t a)

// CHECK-LABEL: @test_vshrq_n_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = lshr <16 x i8> [[A:%.*]], <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
// CHECK-NEXT: [[TMP0:%.*]] = lshr <16 x i8> [[A:%.*]], splat (i8 1)
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
uint8x16_t test_vshrq_n_u8(uint8x16_t a)
Expand All @@ -274,7 +274,7 @@ uint8x16_t test_vshrq_n_u8(uint8x16_t a)

// CHECK-LABEL: @test_vshrq_n_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = lshr <8 x i16> [[A:%.*]], <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
// CHECK-NEXT: [[TMP0:%.*]] = lshr <8 x i16> [[A:%.*]], splat (i16 10)
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
uint16x8_t test_vshrq_n_u16(uint16x8_t a)
Expand All @@ -288,7 +288,7 @@ uint16x8_t test_vshrq_n_u16(uint16x8_t a)

// CHECK-LABEL: @test_vshrq_n_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = lshr <4 x i32> [[A:%.*]], <i32 10, i32 10, i32 10, i32 10>
// CHECK-NEXT: [[TMP0:%.*]] = lshr <4 x i32> [[A:%.*]], splat (i32 10)
// CHECK-NEXT: ret <4 x i32> [[TMP0]]
//
uint32x4_t test_vshrq_n_u32(uint32x4_t a)
Expand Down
8 changes: 4 additions & 4 deletions clang/test/CodeGen/arm-mve-intrinsics/vornq.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@

// CHECK-LABEL: @test_vornq_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[B:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[B:%.*]], splat (i8 -1)
// CHECK-NEXT: [[TMP1:%.*]] = or <16 x i8> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <16 x i8> [[TMP1]]
//
Expand All @@ -23,7 +23,7 @@ uint8x16_t test_vornq_u8(uint8x16_t a, uint8x16_t b)

// CHECK-LABEL: @test_vornq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[B:%.*]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[B:%.*]], splat (i16 -1)
// CHECK-NEXT: [[TMP1:%.*]] = or <8 x i16> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <8 x i16> [[TMP1]]
//
Expand All @@ -38,7 +38,7 @@ int16x8_t test_vornq_s16(int16x8_t a, int16x8_t b)

// CHECK-LABEL: @test_vornq_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[B:%.*]], splat (i32 -1)
// CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <4 x i32> [[TMP1]]
//
Expand All @@ -55,7 +55,7 @@ uint32x4_t test_vornq_u32(uint32x4_t a, uint32x4_t b)
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i32> [[TMP1]], <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i32> [[TMP1]], splat (i32 -1)
// CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP0]], [[TMP2]]
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[TMP4]]
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8 changes: 4 additions & 4 deletions clang/test/CodeGen/arm-neon-shifts.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,13 +9,13 @@

uint8x8_t test_shift_vshr(uint8x8_t a) {
// CHECK-LABEL: test_shift_vshr
// CHECK: %{{.*}} = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
// CHECK: %{{.*}} = lshr <8 x i8> %a, splat (i8 5)
return vshr_n_u8(a, 5);
}

int8x8_t test_shift_vshr_smax(int8x8_t a) {
// CHECK-LABEL: test_shift_vshr_smax
// CHECK: %{{.*}} = ashr <8 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
// CHECK: %{{.*}} = ashr <8 x i8> %a, splat (i8 7)
return vshr_n_s8(a, 8);
}

Expand All @@ -27,14 +27,14 @@ uint8x8_t test_shift_vshr_umax(uint8x8_t a) {

uint8x8_t test_shift_vsra(uint8x8_t a, uint8x8_t b) {
// CHECK-LABEL: test_shift_vsra
// CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
// CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, splat (i8 5)
// CHECK: %{{.*}} = add <8 x i8> %a, %[[SHR]]
return vsra_n_u8(a, b, 5);
}

int8x8_t test_shift_vsra_smax(int8x8_t a, int8x8_t b) {
// CHECK-LABEL: test_shift_vsra_smax
// CHECK: %[[SHR:.*]] = ashr <8 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
// CHECK: %[[SHR:.*]] = ashr <8 x i8> %b, splat (i8 7)
// CHECK: %{{.*}} = add <8 x i8> %a, %[[SHR]]
return vsra_n_s8(a, b, 8);
}
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