38 changes: 17 additions & 21 deletions llvm/test/CodeGen/PowerPC/testComparesieqss.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesieqss.c'

@glob = local_unnamed_addr global i16 0, align 2
@glob = dso_local local_unnamed_addr global i16 0, align 2

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss(i16 signext %a, i16 signext %b) {
define dso_local signext i32 @test_ieqss(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -37,7 +37,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
define dso_local signext i32 @test_ieqss_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand Down Expand Up @@ -67,7 +67,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss_z(i16 signext %a) {
define dso_local signext i32 @test_ieqss_z(i16 signext %a) {
; CHECK-LABEL: test_ieqss_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -91,7 +91,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ieqss_sext_z(i16 signext %a) {
define dso_local signext i32 @test_ieqss_sext_z(i16 signext %a) {
; CHECK-LABEL: test_ieqss_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -118,7 +118,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
define dso_local void @test_ieqss_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -129,12 +129,11 @@ define void @test_ieqss_store(i16 signext %a, i16 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_store:
Expand All @@ -153,7 +152,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
define dso_local void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_ieqss_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -165,13 +164,12 @@ define void @test_ieqss_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_store:
Expand All @@ -191,7 +189,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ieqss_z_store(i16 signext %a) {
define dso_local void @test_ieqss_z_store(i16 signext %a) {
; CHECK-LABEL: test_ieqss_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -201,11 +199,10 @@ define void @test_ieqss_z_store(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_z_store:
Expand All @@ -223,7 +220,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ieqss_sext_z_store(i16 signext %a) {
define dso_local void @test_ieqss_sext_z_store(i16 signext %a) {
; CHECK-LABEL: test_ieqss_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -234,12 +231,11 @@ define void @test_ieqss_sext_z_store(i16 signext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ieqss_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ieqss_sext_z_store:
Expand Down
38 changes: 17 additions & 21 deletions llvm/test/CodeGen/PowerPC/testComparesiequc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequc.c'

@glob = local_unnamed_addr global i8 0, align 1
@glob = dso_local local_unnamed_addr global i8 0, align 1

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) {
define dso_local signext i32 @test_iequc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -37,7 +37,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
define dso_local signext i32 @test_iequc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand Down Expand Up @@ -67,7 +67,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc_z(i8 zeroext %a) {
define dso_local signext i32 @test_iequc_z(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -91,7 +91,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequc_sext_z(i8 zeroext %a) {
define dso_local signext i32 @test_iequc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -118,7 +118,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
define dso_local void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -129,12 +129,11 @@ define void @test_iequc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_store:
Expand All @@ -153,7 +152,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
define dso_local void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_iequc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -165,13 +164,12 @@ define void @test_iequc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_sext_store:
Expand All @@ -191,7 +189,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequc_z_store(i8 zeroext %a) {
define dso_local void @test_iequc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -201,11 +199,10 @@ define void @test_iequc_z_store(i8 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_z_store:
Expand All @@ -223,7 +220,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequc_sext_z_store(i8 zeroext %a) {
define dso_local void @test_iequc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_iequc_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -234,12 +231,11 @@ define void @test_iequc_sext_z_store(i8 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequc_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: stb r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequc_sext_z_store:
Expand Down
38 changes: 17 additions & 21 deletions llvm/test/CodeGen/PowerPC/testComparesiequi.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequi.c'

@glob = local_unnamed_addr global i32 0, align 4
@glob = dso_local local_unnamed_addr global i32 0, align 4

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) {
define dso_local signext i32 @test_iequi(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -37,7 +37,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
define dso_local signext i32 @test_iequi_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand Down Expand Up @@ -67,7 +67,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi_z(i32 zeroext %a) {
define dso_local signext i32 @test_iequi_z(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -91,7 +91,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequi_sext_z(i32 zeroext %a) {
define dso_local signext i32 @test_iequi_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -118,7 +118,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
define dso_local void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -129,12 +129,11 @@ define void @test_iequi_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_store:
Expand All @@ -153,7 +152,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
define dso_local void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_iequi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -165,13 +164,12 @@ define void @test_iequi_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_sext_store:
Expand All @@ -191,7 +189,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequi_z_store(i32 zeroext %a) {
define dso_local void @test_iequi_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -201,11 +199,10 @@ define void @test_iequi_z_store(i32 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_z_store:
Expand All @@ -223,7 +220,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequi_sext_z_store(i32 zeroext %a) {
define dso_local void @test_iequi_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_iequi_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -234,12 +231,11 @@ define void @test_iequi_sext_z_store(i32 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequi_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: stw r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequi_sext_z_store:
Expand Down
38 changes: 17 additions & 21 deletions llvm/test/CodeGen/PowerPC/testComparesiequll.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequll.c'

@glob = local_unnamed_addr global i64 0, align 8
@glob = dso_local local_unnamed_addr global i64 0, align 8

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll(i64 %a, i64 %b) {
define dso_local signext i32 @test_iequll(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -37,7 +37,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll_sext(i64 %a, i64 %b) {
define dso_local signext i32 @test_iequll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -64,7 +64,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll_z(i64 %a) {
define dso_local signext i32 @test_iequll_z(i64 %a) {
; CHECK-LABEL: test_iequll_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3
Expand All @@ -88,7 +88,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequll_sext_z(i64 %a) {
define dso_local signext i32 @test_iequll_sext_z(i64 %a) {
; CHECK-LABEL: test_iequll_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r3, r3, -1
Expand All @@ -112,7 +112,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequll_store(i64 %a, i64 %b) {
define dso_local void @test_iequll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -123,12 +123,11 @@ define void @test_iequll_store(i64 %a, i64 %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: std r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_store:
Expand All @@ -147,7 +146,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequll_sext_store(i64 %a, i64 %b) {
define dso_local void @test_iequll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_iequll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -158,12 +157,11 @@ define void @test_iequll_sext_store(i64 %a, i64 %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: std r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_sext_store:
Expand All @@ -182,7 +180,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequll_z_store(i64 %a) {
define dso_local void @test_iequll_z_store(i64 %a) {
; CHECK-LABEL: test_iequll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3
Expand All @@ -192,11 +190,10 @@ define void @test_iequll_z_store(i64 %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzd r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 58, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: std r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_z_store:
Expand All @@ -214,7 +211,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequll_sext_z_store(i64 %a) {
define dso_local void @test_iequll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_iequll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r3, r3, -1
Expand All @@ -224,11 +221,10 @@ define void @test_iequll_sext_z_store(i64 %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addic r3, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: subfe r3, r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: std r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequll_sext_z_store:
Expand Down
38 changes: 17 additions & 21 deletions llvm/test/CodeGen/PowerPC/testComparesiequs.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,10 +7,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; ModuleID = 'ComparisonTestCases/testComparesiequs.c'

@glob = local_unnamed_addr global i16 0, align 2
@glob = dso_local local_unnamed_addr global i16 0, align 2

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
define dso_local signext i32 @test_iequs(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -37,7 +37,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
define dso_local signext i32 @test_iequs_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand Down Expand Up @@ -67,7 +67,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs_z(i16 zeroext %a) {
define dso_local signext i32 @test_iequs_z(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -91,7 +91,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iequs_sext_z(i16 zeroext %a) {
define dso_local signext i32 @test_iequs_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -118,7 +118,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
define dso_local void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -129,12 +129,11 @@ define void @test_iequs_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_store:
Expand All @@ -153,7 +152,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
define dso_local void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_iequs_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor r3, r3, r4
Expand All @@ -165,13 +164,12 @@ define void @test_iequs_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: xor r3, r3, r4
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_sext_store:
Expand All @@ -191,7 +189,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequs_z_store(i16 zeroext %a) {
define dso_local void @test_iequs_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -201,11 +199,10 @@ define void @test_iequs_z_store(i16 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_z_store:
Expand All @@ -223,7 +220,7 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iequs_sext_z_store(i16 zeroext %a) {
define dso_local void @test_iequs_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_iequs_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -234,12 +231,11 @@ define void @test_iequs_sext_z_store(i16 zeroext %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iequs_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: cntlzw r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: srwi r3, r3, 5
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iequs_sext_z_store:
Expand Down
20 changes: 9 additions & 11 deletions llvm/test/CodeGen/PowerPC/testComparesigesc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i8 0, align 1
@glob = dso_local local_unnamed_addr global i8 0, align 1

define signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
define dso_local signext i32 @test_igesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -33,7 +33,7 @@ entry:
ret i32 %conv2
}

define signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
define dso_local signext i32 @test_igesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -59,7 +59,7 @@ entry:
ret i32 %sub
}

define void @test_igesc_store(i8 signext %a, i8 signext %b) {
define dso_local void @test_igesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -70,12 +70,11 @@ define void @test_igesc_store(i8 signext %a, i8 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesc_store:
Expand All @@ -93,7 +92,7 @@ entry:
ret void
}

define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
define dso_local void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_igesc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -104,12 +103,11 @@ define void @test_igesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesc_sext_store:
Expand Down
20 changes: 9 additions & 11 deletions llvm/test/CodeGen/PowerPC/testComparesigesi.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i32 0, align 4
@glob = dso_local local_unnamed_addr global i32 0, align 4

define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
define dso_local signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -33,7 +33,7 @@ entry:
ret i32 %conv
}

define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
define dso_local signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -59,7 +59,7 @@ entry:
ret i32 %sub
}

define void @test_igesi_store(i32 signext %a, i32 signext %b) {
define dso_local void @test_igesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -70,12 +70,11 @@ define void @test_igesi_store(i32 signext %a, i32 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesi_store:
Expand All @@ -93,7 +92,7 @@ entry:
ret void
}

define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
define dso_local void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_igesi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -104,12 +103,11 @@ define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesi_sext_store:
Expand Down
38 changes: 17 additions & 21 deletions llvm/test/CodeGen/PowerPC/testComparesigesll.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i64 0, align 8
@glob = dso_local local_unnamed_addr global i64 0, align 8

define signext i32 @test_igesll(i64 %a, i64 %b) {
define dso_local signext i32 @test_igesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
Expand Down Expand Up @@ -36,7 +36,7 @@ entry:
ret i32 %conv
}

define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
define dso_local signext i32 @test_igesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63
Expand Down Expand Up @@ -68,7 +68,7 @@ entry:
ret i32 %sub
}

define signext i32 @test_igesll_z(i64 %a) {
define dso_local signext i32 @test_igesll_z(i64 %a) {
; CHECK-LABEL: test_igesll_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: not r3, r3
Expand All @@ -91,7 +91,7 @@ entry:
ret i32 %conv
}

define signext i32 @test_igesll_sext_z(i64 %a) {
define dso_local signext i32 @test_igesll_sext_z(i64 %a) {
; CHECK-LABEL: test_igesll_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r3, r3, 63
Expand All @@ -114,7 +114,7 @@ entry:
ret i32 %sub
}

define void @test_igesll_store(i64 %a, i64 %b) {
define dso_local void @test_igesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
Expand All @@ -126,13 +126,12 @@ define void @test_igesll_store(i64 %a, i64 %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: std r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_store:
Expand All @@ -151,7 +150,7 @@ entry:
ret void
}

define void @test_igesll_sext_store(i64 %a, i64 %b) {
define dso_local void @test_igesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r3, 63
Expand All @@ -165,13 +164,12 @@ define void @test_igesll_sext_store(i64 %a, i64 %b) {
; CHECK-BE-LABEL: test_igesll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: std r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_sext_store:
Expand All @@ -191,7 +189,7 @@ entry:
ret void
}

define void @test_igesll_z_store(i64 %a) {
define dso_local void @test_igesll_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: not r3, r3
Expand All @@ -201,11 +199,10 @@ define void @test_igesll_z_store(i64 %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: std r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_z_store:
Expand All @@ -222,7 +219,7 @@ entry:
ret void
}

define void @test_igesll_sext_z_store(i64 %a) {
define dso_local void @test_igesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_igesll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: not r3, r3
Expand All @@ -232,11 +229,10 @@ define void @test_igesll_sext_z_store(i64 %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: not r3, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: std r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igesll_sext_z_store:
Expand Down
20 changes: 9 additions & 11 deletions llvm/test/CodeGen/PowerPC/testComparesigess.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i16 0, align 2
@glob = dso_local local_unnamed_addr global i16 0, align 2

define signext i32 @test_igess(i16 signext %a, i16 signext %b) {
define dso_local signext i32 @test_igess(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -33,7 +33,7 @@ entry:
ret i32 %conv2
}

define signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
define dso_local signext i32 @test_igess_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -59,7 +59,7 @@ entry:
ret i32 %sub
}

define void @test_igess_store(i16 signext %a, i16 signext %b) {
define dso_local void @test_igess_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -70,12 +70,11 @@ define void @test_igess_store(i16 signext %a, i16 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igess_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igess_store:
Expand All @@ -93,7 +92,7 @@ entry:
ret void
}

define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
define dso_local void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_igess_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -104,12 +103,11 @@ define void @test_igess_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igess_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r3, r4
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_igess_sext_store:
Expand Down
110 changes: 37 additions & 73 deletions llvm/test/CodeGen/PowerPC/testComparesigeuc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE

@glob = local_unnamed_addr global i8 0, align 1
@glob = dso_local local_unnamed_addr global i8 0, align 1

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
define dso_local signext i32 @test_igeuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igeuc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -25,7 +25,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
define dso_local signext i32 @test_igeuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igeuc_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -40,7 +40,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc_z(i8 zeroext %a) {
define dso_local signext i32 @test_igeuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_igeuc_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 1
Expand All @@ -52,7 +52,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeuc_sext_z(i8 zeroext %a) {
define dso_local signext i32 @test_igeuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_igeuc_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, -1
Expand All @@ -64,25 +64,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_igeuc_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_igeuc_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_igeuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igeuc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = zext i1 %cmp to i8
Expand All @@ -92,25 +82,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_igeuc_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_igeuc_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_igeuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_igeuc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, %b
%conv3 = sext i1 %cmp to i8
Expand All @@ -125,21 +105,13 @@ entry:
}

; Function Attrs : norecurse nounwind
define void @test_igeuc_z_store(i8 zeroext %a) {
; BE-LABEL: test_igeuc_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r3, r2, .LC0@toc@ha
; BE-NEXT: li r4, 1
; BE-NEXT: ld r3, .LC0@toc@l(r3)
; BE-NEXT: stb r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_igeuc_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r3, r2, glob@toc@ha
; LE-NEXT: li r4, 1
; LE-NEXT: stb r4, glob@toc@l(r3)
; LE-NEXT: blr
define dso_local void @test_igeuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_igeuc_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, glob@toc@ha
; CHECK-NEXT: li r4, 1
; CHECK-NEXT: stb r4, glob@toc@l(r3)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, 0
%conv3 = zext i1 %cmp to i8
Expand All @@ -148,21 +120,13 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeuc_sext_z_store(i8 zeroext %a) {
; BE-LABEL: test_igeuc_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r3, r2, .LC0@toc@ha
; BE-NEXT: li r4, -1
; BE-NEXT: ld r3, .LC0@toc@l(r3)
; BE-NEXT: stb r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_igeuc_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r3, r2, glob@toc@ha
; LE-NEXT: li r4, -1
; LE-NEXT: stb r4, glob@toc@l(r3)
; LE-NEXT: blr
define dso_local void @test_igeuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_igeuc_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, glob@toc@ha
; CHECK-NEXT: li r4, -1
; CHECK-NEXT: stb r4, glob@toc@l(r3)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i8 %a, 0
%conv3 = sext i1 %cmp to i8
Expand Down
110 changes: 37 additions & 73 deletions llvm/test/CodeGen/PowerPC/testComparesigeui.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE

@glob = local_unnamed_addr global i32 0, align 4
@glob = dso_local local_unnamed_addr global i32 0, align 4

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
define dso_local signext i32 @test_igeui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igeui:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -25,7 +25,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) {
define dso_local signext i32 @test_igeui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igeui_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -39,7 +39,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui_z(i32 zeroext %a) {
define dso_local signext i32 @test_igeui_z(i32 zeroext %a) {
; CHECK-LABEL: test_igeui_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 1
Expand All @@ -51,7 +51,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeui_sext_z(i32 zeroext %a) {
define dso_local signext i32 @test_igeui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_igeui_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, -1
Expand All @@ -63,25 +63,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_igeui_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_igeui_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_igeui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igeui_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
Expand All @@ -91,25 +81,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_igeui_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_igeui_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_igeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_igeui_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, %b
%sub = sext i1 %cmp to i32
Expand All @@ -118,21 +98,13 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeui_z_store(i32 zeroext %a) {
; BE-LABEL: test_igeui_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r3, r2, .LC0@toc@ha
; BE-NEXT: li r4, 1
; BE-NEXT: ld r3, .LC0@toc@l(r3)
; BE-NEXT: stw r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_igeui_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r3, r2, glob@toc@ha
; LE-NEXT: li r4, 1
; LE-NEXT: stw r4, glob@toc@l(r3)
; LE-NEXT: blr
define dso_local void @test_igeui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_igeui_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, glob@toc@ha
; CHECK-NEXT: li r4, 1
; CHECK-NEXT: stw r4, glob@toc@l(r3)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = zext i1 %cmp to i32
Expand All @@ -141,21 +113,13 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeui_sext_z_store(i32 zeroext %a) {
; BE-LABEL: test_igeui_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r3, r2, .LC0@toc@ha
; BE-NEXT: li r4, -1
; BE-NEXT: ld r3, .LC0@toc@l(r3)
; BE-NEXT: stw r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_igeui_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r3, r2, glob@toc@ha
; LE-NEXT: li r4, -1
; LE-NEXT: stw r4, glob@toc@l(r3)
; LE-NEXT: blr
define dso_local void @test_igeui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_igeui_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, glob@toc@ha
; CHECK-NEXT: li r4, -1
; CHECK-NEXT: stw r4, glob@toc@l(r3)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i32 %a, 0
%conv1 = sext i1 %cmp to i32
Expand Down
110 changes: 37 additions & 73 deletions llvm/test/CodeGen/PowerPC/testComparesigeull.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE

@glob = local_unnamed_addr global i64 0, align 8
@glob = dso_local local_unnamed_addr global i64 0, align 8

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull(i64 %a, i64 %b) {
define dso_local signext i32 @test_igeull(i64 %a, i64 %b) {
; CHECK-LABEL: test_igeull:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subc r3, r3, r4
Expand All @@ -25,7 +25,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
define dso_local signext i32 @test_igeull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igeull_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subc r3, r3, r4
Expand All @@ -39,7 +39,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull_z(i64 %a) {
define dso_local signext i32 @test_igeull_z(i64 %a) {
; CHECK-LABEL: test_igeull_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 1
Expand All @@ -51,7 +51,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull_sext_z(i64 %a) {
define dso_local signext i32 @test_igeull_sext_z(i64 %a) {
; CHECK-LABEL: test_igeull_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, -1
Expand All @@ -63,25 +63,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeull_store(i64 %a, i64 %b) {
; BE-LABEL: test_igeull_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: addi r4, r4, 1
; BE-NEXT: std r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_igeull_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: addi r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_igeull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igeull_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64
Expand All @@ -90,25 +80,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeull_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_igeull_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: not r4, r4
; BE-NEXT: std r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_igeull_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: not r3, r3
; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_igeull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igeull_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64
Expand All @@ -117,21 +97,13 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeull_z_store(i64 %a) {
; BE-LABEL: test_igeull_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r3, r2, .LC0@toc@ha
; BE-NEXT: li r4, 1
; BE-NEXT: ld r3, .LC0@toc@l(r3)
; BE-NEXT: std r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_igeull_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r3, r2, glob@toc@ha
; LE-NEXT: li r4, 1
; LE-NEXT: std r4, glob@toc@l(r3)
; LE-NEXT: blr
define dso_local void @test_igeull_z_store(i64 %a) {
; CHECK-LABEL: test_igeull_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, glob@toc@ha
; CHECK-NEXT: li r4, 1
; CHECK-NEXT: std r4, glob@toc@l(r3)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = zext i1 %cmp to i64
Expand All @@ -140,21 +112,13 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeull_sext_z_store(i64 %a) {
; BE-LABEL: test_igeull_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r3, r2, .LC0@toc@ha
; BE-NEXT: li r4, -1
; BE-NEXT: ld r3, .LC0@toc@l(r3)
; BE-NEXT: std r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_igeull_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r3, r2, glob@toc@ha
; LE-NEXT: li r4, -1
; LE-NEXT: std r4, glob@toc@l(r3)
; LE-NEXT: blr
define dso_local void @test_igeull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_igeull_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, glob@toc@ha
; CHECK-NEXT: li r4, -1
; CHECK-NEXT: std r4, glob@toc@l(r3)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i64 %a, 0
%conv1 = sext i1 %cmp to i64
Expand Down
110 changes: 37 additions & 73 deletions llvm/test/CodeGen/PowerPC/testComparesigeus.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE

@glob = local_unnamed_addr global i16 0, align 2
@glob = dso_local local_unnamed_addr global i16 0, align 2

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
define dso_local signext i32 @test_igeus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igeus:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -25,7 +25,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) {
define dso_local signext i32 @test_igeus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igeus_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -39,7 +39,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus_z(i16 zeroext %a) {
define dso_local signext i32 @test_igeus_z(i16 zeroext %a) {
; CHECK-LABEL: test_igeus_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 1
Expand All @@ -51,7 +51,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeus_sext_z(i16 zeroext %a) {
define dso_local signext i32 @test_igeus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_igeus_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: li r3, 1
Expand All @@ -63,25 +63,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_igeus_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_igeus_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_igeus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igeus_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = zext i1 %cmp to i16
Expand All @@ -91,25 +81,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_igeus_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: addi r3, r3, -1
; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_igeus_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: addi r3, r3, -1
; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_igeus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_igeus_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, %b
%conv3 = sext i1 %cmp to i16
Expand All @@ -118,21 +98,13 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeus_z_store(i16 zeroext %a) {
; BE-LABEL: test_igeus_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r3, r2, .LC0@toc@ha
; BE-NEXT: li r4, 1
; BE-NEXT: ld r3, .LC0@toc@l(r3)
; BE-NEXT: sth r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_igeus_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r3, r2, glob@toc@ha
; LE-NEXT: li r4, 1
; LE-NEXT: sth r4, glob@toc@l(r3)
; LE-NEXT: blr
define dso_local void @test_igeus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_igeus_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, glob@toc@ha
; CHECK-NEXT: li r4, 1
; CHECK-NEXT: sth r4, glob@toc@l(r3)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, 0
%conv3 = zext i1 %cmp to i16
Expand All @@ -141,21 +113,13 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_igeus_sext_z_store(i16 zeroext %a) {
; BE-LABEL: test_igeus_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r3, r2, .LC0@toc@ha
; BE-NEXT: li r4, -1
; BE-NEXT: ld r3, .LC0@toc@l(r3)
; BE-NEXT: sth r4, 0(r3)
; BE-NEXT: blr
;
; LE-LABEL: test_igeus_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r3, r2, glob@toc@ha
; LE-NEXT: li r4, -1
; LE-NEXT: sth r4, glob@toc@l(r3)
; LE-NEXT: blr
define dso_local void @test_igeus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_igeus_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r3, r2, glob@toc@ha
; CHECK-NEXT: li r4, -1
; CHECK-NEXT: sth r4, glob@toc@l(r3)
; CHECK-NEXT: blr
entry:
%cmp = icmp uge i16 %a, 0
%conv3 = sext i1 %cmp to i16
Expand Down
20 changes: 9 additions & 11 deletions llvm/test/CodeGen/PowerPC/testComparesilesc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i8 0, align 1
@glob = dso_local local_unnamed_addr global i8 0, align 1

define signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
define dso_local signext i32 @test_ilesc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -33,7 +33,7 @@ entry:
ret i32 %conv2
}

define signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
define dso_local signext i32 @test_ilesc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -59,7 +59,7 @@ entry:
ret i32 %sub
}

define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
define dso_local void @test_ilesc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -70,12 +70,11 @@ define void @test_ilesc_store(i8 signext %a, i8 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesc_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesc_store:
Expand All @@ -93,7 +92,7 @@ entry:
ret void
}

define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
define dso_local void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_ilesc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -104,12 +103,11 @@ define void @test_ilesc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesc_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stb r3, 0(r4)
; CHECK-BE-NEXT: stb r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesc_sext_store:
Expand Down
20 changes: 9 additions & 11 deletions llvm/test/CodeGen/PowerPC/testComparesilesi.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i32 0, align 4
@glob = dso_local local_unnamed_addr global i32 0, align 4

define signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
define dso_local signext i32 @test_ilesi(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -33,7 +33,7 @@ entry:
ret i32 %conv
}

define signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
define dso_local signext i32 @test_ilesi_sext(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -59,7 +59,7 @@ entry:
ret i32 %sub
}

define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
define dso_local void @test_ilesi_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -70,12 +70,11 @@ define void @test_ilesi_store(i32 signext %a, i32 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesi_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesi_store:
Expand All @@ -93,7 +92,7 @@ entry:
ret void
}

define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
define dso_local void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-LABEL: test_ilesi_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -104,12 +103,11 @@ define void @test_ilesi_sext_store(i32 signext %a, i32 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesi_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: stw r3, 0(r4)
; CHECK-BE-NEXT: stw r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesi_sext_store:
Expand Down
38 changes: 17 additions & 21 deletions llvm/test/CodeGen/PowerPC/testComparesilesll.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i64 0, align 8
@glob = dso_local local_unnamed_addr global i64 0, align 8

define signext i32 @test_ilesll(i64 %a, i64 %b) {
define dso_local signext i32 @test_ilesll(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
Expand Down Expand Up @@ -36,7 +36,7 @@ entry:
ret i32 %conv
}

define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
define dso_local signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63
Expand Down Expand Up @@ -68,7 +68,7 @@ entry:
ret i32 %sub
}

define signext i32 @test_ilesll_z(i64 %a) {
define dso_local signext i32 @test_ilesll_z(i64 %a) {
; CHECK-LABEL: test_ilesll_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -1
Expand All @@ -94,7 +94,7 @@ entry:
ret i32 %conv
}

define signext i32 @test_ilesll_sext_z(i64 %a) {
define dso_local signext i32 @test_ilesll_sext_z(i64 %a) {
; CHECK-LABEL: test_ilesll_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r4, r3, -1
Expand All @@ -120,7 +120,7 @@ entry:
ret i32 %sub
}

define void @test_ilesll_store(i64 %a, i64 %b) {
define dso_local void @test_ilesll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
Expand All @@ -132,13 +132,12 @@ define void @test_ilesll_store(i64 %a, i64 %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: std r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_store:
Expand All @@ -157,7 +156,7 @@ entry:
ret void
}

define void @test_ilesll_sext_store(i64 %a, i64 %b) {
define dso_local void @test_ilesll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63
Expand All @@ -171,13 +170,12 @@ define void @test_ilesll_sext_store(i64 %a, i64 %b) {
; CHECK-BE-LABEL: test_ilesll_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: std r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_sext_store:
Expand All @@ -197,7 +195,7 @@ entry:
ret void
}

define void @test_ilesll_z_store(i64 %a) {
define dso_local void @test_ilesll_z_store(i64 %a) {
; CHECK-LABEL: test_ilesll_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r5, r3, -1
Expand All @@ -208,12 +206,11 @@ define void @test_ilesll_z_store(i64 %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addi r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: or r3, r5, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: std r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_z_store:
Expand All @@ -231,7 +228,7 @@ entry:
ret void
}

define void @test_ilesll_sext_z_store(i64 %a) {
define dso_local void @test_ilesll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ilesll_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi r5, r3, -1
Expand All @@ -242,12 +239,11 @@ define void @test_ilesll_sext_z_store(i64 %a) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_sext_z_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-BE-NEXT: addi r5, r3, -1
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-BE-NEXT: addis r4, r2, glob@toc@ha
; CHECK-BE-NEXT: or r3, r5, r3
; CHECK-BE-NEXT: sradi r3, r3, 63
; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: std r3, glob@toc@l(r4)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_ilesll_sext_z_store:
Expand Down
20 changes: 9 additions & 11 deletions llvm/test/CodeGen/PowerPC/testComparesiless.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,9 @@
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i16 0, align 2
@glob = dso_local local_unnamed_addr global i16 0, align 2

define signext i32 @test_iless(i16 signext %a, i16 signext %b) {
define dso_local signext i32 @test_iless(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -33,7 +33,7 @@ entry:
ret i32 %conv2
}

define signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
define dso_local signext i32 @test_iless_sext(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -59,7 +59,7 @@ entry:
ret i32 %sub
}

define void @test_iless_store(i16 signext %a, i16 signext %b) {
define dso_local void @test_iless_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -70,12 +70,11 @@ define void @test_iless_store(i16 signext %a, i16 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iless_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: xori r3, r3, 1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iless_store:
Expand All @@ -93,7 +92,7 @@ entry:
ret void
}

define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
define dso_local void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-LABEL: test_iless_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -104,12 +103,11 @@ define void @test_iless_sext_store(i16 signext %a, i16 signext %b) {
; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_iless_sext_store:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sub r3, r4, r3
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: addi r3, r3, -1
; CHECK-BE-NEXT: sth r3, 0(r4)
; CHECK-BE-NEXT: sth r3, glob@toc@l(r5)
; CHECK-BE-NEXT: blr
;
; CHECK-LE-LABEL: test_iless_sext_store:
Expand Down
119 changes: 40 additions & 79 deletions llvm/test/CodeGen/PowerPC/testComparesileuc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE

@glob = local_unnamed_addr global i8 0, align 1
@glob = dso_local local_unnamed_addr global i8 0, align 1

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
define dso_local signext i32 @test_ileuc(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ileuc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -25,7 +25,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
define dso_local signext i32 @test_ileuc_sext(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ileuc_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -39,7 +39,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc_z(i8 zeroext %a) {
define dso_local signext i32 @test_ileuc_z(i8 zeroext %a) {
; CHECK-LABEL: test_ileuc_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -52,7 +52,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
define dso_local signext i32 @test_ileuc_sext_z(i8 zeroext %a) {
; CHECK-LABEL: test_ileuc_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -66,25 +66,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_ileuc_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileuc_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_ileuc_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ileuc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = zext i1 %cmp to i8
Expand All @@ -93,25 +83,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; BE-LABEL: test_ileuc_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileuc_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_ileuc_sext_store(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test_ileuc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i8 %a, %b
%conv3 = sext i1 %cmp to i8
Expand All @@ -120,23 +100,14 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileuc_z_store(i8 zeroext %a) {
; BE-LABEL: test_ileuc_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: cntlzw r3, r3
; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: srwi r3, r3, 5
; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileuc_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: cntlzw r3, r3
; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: srwi r3, r3, 5
; LE-NEXT: stb r3, glob@toc@l(r4)
; LE-NEXT: blr
define dso_local void @test_ileuc_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ileuc_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = zext i1 %cmp to i8
Expand All @@ -145,25 +116,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileuc_sext_z_store(i8 zeroext %a) {
; BE-LABEL: test_ileuc_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: cntlzw r3, r3
; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: srwi r3, r3, 5
; BE-NEXT: neg r3, r3
; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileuc_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: cntlzw r3, r3
; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: srwi r3, r3, 5
; LE-NEXT: neg r3, r3
; LE-NEXT: stb r3, glob@toc@l(r4)
; LE-NEXT: blr
define dso_local void @test_ileuc_sext_z_store(i8 zeroext %a) {
; CHECK-LABEL: test_ileuc_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i8 %a, 0
%conv2 = sext i1 %cmp to i8
Expand Down
119 changes: 40 additions & 79 deletions llvm/test/CodeGen/PowerPC/testComparesileui.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE

@glob = local_unnamed_addr global i32 0, align 4
@glob = dso_local local_unnamed_addr global i32 0, align 4

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
define dso_local signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ileui:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -25,7 +25,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
define dso_local signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ileui_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -39,7 +39,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui_z(i32 zeroext %a) {
define dso_local signext i32 @test_ileui_z(i32 zeroext %a) {
; CHECK-LABEL: test_ileui_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -52,7 +52,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileui_sext_z(i32 zeroext %a) {
define dso_local signext i32 @test_ileui_sext_z(i32 zeroext %a) {
; CHECK-LABEL: test_ileui_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -66,25 +66,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_ileui_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileui_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ileui_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%sub = zext i1 %cmp to i32
Expand All @@ -93,25 +83,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; BE-LABEL: test_ileui_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: addi r3, r3, -1
; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileui_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: addi r3, r3, -1
; LE-NEXT: stw r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: test_ileui_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: stw r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i32 %a, %b
%sub = sext i1 %cmp to i32
Expand All @@ -120,23 +100,14 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileui_z_store(i32 zeroext %a) {
; BE-LABEL: test_ileui_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: cntlzw r3, r3
; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: srwi r3, r3, 5
; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileui_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: cntlzw r3, r3
; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: srwi r3, r3, 5
; LE-NEXT: stw r3, glob@toc@l(r4)
; LE-NEXT: blr
define dso_local void @test_ileui_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ileui_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = zext i1 %cmp to i32
Expand All @@ -145,25 +116,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileui_sext_z_store(i32 zeroext %a) {
; BE-LABEL: test_ileui_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: cntlzw r3, r3
; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: srwi r3, r3, 5
; BE-NEXT: neg r3, r3
; BE-NEXT: stw r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileui_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: cntlzw r3, r3
; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: srwi r3, r3, 5
; LE-NEXT: neg r3, r3
; LE-NEXT: stw r3, glob@toc@l(r4)
; LE-NEXT: blr
define dso_local void @test_ileui_sext_z_store(i32 zeroext %a) {
; CHECK-LABEL: test_ileui_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: stw r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i32 %a, 0
%sub = sext i1 %cmp to i32
Expand Down
116 changes: 39 additions & 77 deletions llvm/test/CodeGen/PowerPC/testComparesileull.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE

@glob = local_unnamed_addr global i64 0, align 8
@glob = dso_local local_unnamed_addr global i64 0, align 8

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull(i64 %a, i64 %b) {
define dso_local signext i32 @test_ileull(i64 %a, i64 %b) {
; CHECK-LABEL: test_ileull:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subc r4, r4, r3
Expand All @@ -25,7 +25,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
define dso_local signext i32 @test_ileull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ileull_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subc r4, r4, r3
Expand All @@ -39,7 +39,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_z(i64 %a) {
define dso_local signext i32 @test_ileull_z(i64 %a) {
; CHECK-LABEL: test_ileull_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3
Expand All @@ -52,7 +52,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_sext_z(i64 %a) {
define dso_local signext i32 @test_ileull_sext_z(i64 %a) {
; CHECK-LABEL: test_ileull_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r3, r3, -1
Expand All @@ -65,25 +65,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileull_store(i64 %a, i64 %b) {
; BE-LABEL: test_ileull_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: addi r3, r3, 1
; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileull_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: addi r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_ileull_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ileull_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = zext i1 %cmp to i64
Expand All @@ -92,25 +82,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileull_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_ileull_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: not r3, r3
; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileull_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: not r3, r3
; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_ileull_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_ileull_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, %b
%conv1 = sext i1 %cmp to i64
Expand All @@ -119,23 +99,14 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileull_z_store(i64 %a) {
; BE-LABEL: test_ileull_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: cntlzd r3, r3
; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: rldicl r3, r3, 58, 63
; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileull_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: cntlzd r3, r3
; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 58, 63
; LE-NEXT: std r3, glob@toc@l(r4)
; LE-NEXT: blr
define dso_local void @test_ileull_z_store(i64 %a) {
; CHECK-LABEL: test_ileull_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = zext i1 %cmp to i64
Expand All @@ -144,23 +115,14 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileull_sext_z_store(i64 %a) {
; BE-LABEL: test_ileull_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: addic r3, r3, -1
; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileull_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addic r3, r3, -1
; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: std r3, glob@toc@l(r4)
; LE-NEXT: blr
define dso_local void @test_ileull_sext_z_store(i64 %a) {
; CHECK-LABEL: test_ileull_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i64 %a, 0
%conv1 = sext i1 %cmp to i64
Expand Down
119 changes: 40 additions & 79 deletions llvm/test/CodeGen/PowerPC/testComparesileus.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE

@glob = local_unnamed_addr global i16 0, align 2
@glob = dso_local local_unnamed_addr global i16 0, align 2

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
define dso_local signext i32 @test_ileus(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ileus:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -25,7 +25,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) {
define dso_local signext i32 @test_ileus_sext(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ileus_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
Expand All @@ -39,7 +39,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus_z(i16 zeroext %a) {
define dso_local signext i32 @test_ileus_z(i16 zeroext %a) {
; CHECK-LABEL: test_ileus_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -52,7 +52,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileus_sext_z(i16 zeroext %a) {
define dso_local signext i32 @test_ileus_sext_z(i16 zeroext %a) {
; CHECK-LABEL: test_ileus_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
Expand All @@ -66,25 +66,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_ileus_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: not r3, r3
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileus_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: not r3, r3
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_ileus_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ileus_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: not r3, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = zext i1 %cmp to i16
Expand All @@ -93,25 +83,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; BE-LABEL: test_ileus_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: addi r3, r3, -1
; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileus_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: addi r3, r3, -1
; LE-NEXT: sth r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_ileus_sext_store(i16 zeroext %a, i16 zeroext %b) {
; CHECK-LABEL: test_ileus_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: addi r3, r3, -1
; CHECK-NEXT: sth r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, %b
%conv3 = sext i1 %cmp to i16
Expand All @@ -120,23 +100,14 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileus_z_store(i16 zeroext %a) {
; BE-LABEL: test_ileus_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: cntlzw r3, r3
; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: srwi r3, r3, 5
; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileus_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: cntlzw r3, r3
; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: srwi r3, r3, 5
; LE-NEXT: sth r3, glob@toc@l(r4)
; LE-NEXT: blr
define dso_local void @test_ileus_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ileus_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = zext i1 %cmp to i16
Expand All @@ -145,25 +116,15 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_ileus_sext_z_store(i16 zeroext %a) {
; BE-LABEL: test_ileus_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: cntlzw r3, r3
; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: srwi r3, r3, 5
; BE-NEXT: neg r3, r3
; BE-NEXT: sth r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_ileus_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: cntlzw r3, r3
; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: srwi r3, r3, 5
; LE-NEXT: neg r3, r3
; LE-NEXT: sth r3, glob@toc@l(r4)
; LE-NEXT: blr
define dso_local void @test_ileus_sext_z_store(i16 zeroext %a) {
; CHECK-LABEL: test_ileus_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cntlzw r3, r3
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 5
; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: sth r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp ule i16 %a, 0
%conv2 = sext i1 %cmp to i16
Expand Down
80 changes: 27 additions & 53 deletions llvm/test/CodeGen/PowerPC/testComparesiltsc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,10 +8,10 @@
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE

@glob = local_unnamed_addr global i8 0, align 1
@glob = dso_local local_unnamed_addr global i8 0, align 1

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
define dso_local signext i32 @test_iltsc(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -24,7 +24,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
define dso_local signext i32 @test_iltsc_sext(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc_sext:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
Expand All @@ -37,7 +37,7 @@ entry:
}

; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsc_sext_z(i8 signext %a) {
define dso_local signext i32 @test_iltsc_sext_z(i8 signext %a) {
; CHECK-LABEL: test_iltsc_sext_z:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: srawi r3, r3, 31
Expand All @@ -49,23 +49,14 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iltsc_store(i8 signext %a, i8 signext %b) {
; BE-LABEL: test_iltsc_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r5, .LC0@toc@l(r5)
; BE-NEXT: rldicl r3, r3, 1, 63
; BE-NEXT: stb r3, 0(r5)
; BE-NEXT: blr
;
; LE-LABEL: test_iltsc_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: rldicl r3, r3, 1, 63
; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_iltsc_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = zext i1 %cmp to i8
Expand All @@ -74,23 +65,14 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
; BE-LABEL: test_iltsc_sext_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: sub r3, r3, r4
; BE-NEXT: ld r5, .LC0@toc@l(r5)
; BE-NEXT: sradi r3, r3, 63
; BE-NEXT: stb r3, 0(r5)
; BE-NEXT: blr
;
; LE-LABEL: test_iltsc_sext_store:
; LE: # %bb.0: # %entry
; LE-NEXT: sub r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: sradi r3, r3, 63
; LE-NEXT: stb r3, glob@toc@l(r5)
; LE-NEXT: blr
define dso_local void @test_iltsc_sext_store(i8 signext %a, i8 signext %b) {
; CHECK-LABEL: test_iltsc_sext_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: addis r5, r2, glob@toc@ha
; CHECK-NEXT: sradi r3, r3, 63
; CHECK-NEXT: stb r3, glob@toc@l(r5)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, %b
%conv3 = sext i1 %cmp to i8
Expand All @@ -99,21 +81,13 @@ entry:
}

; Function Attrs: norecurse nounwind
define void @test_iltsc_sext_z_store(i8 signext %a) {
; BE-LABEL: test_iltsc_sext_z_store:
; BE: # %bb.0: # %entry
; BE-NEXT: addis r4, r2, .LC0@toc@ha
; BE-NEXT: srwi r3, r3, 7
; BE-NEXT: ld r4, .LC0@toc@l(r4)
; BE-NEXT: stb r3, 0(r4)
; BE-NEXT: blr
;
; LE-LABEL: test_iltsc_sext_z_store:
; LE: # %bb.0: # %entry
; LE-NEXT: addis r4, r2, glob@toc@ha
; LE-NEXT: srwi r3, r3, 7
; LE-NEXT: stb r3, glob@toc@l(r4)
; LE-NEXT: blr
define dso_local void @test_iltsc_sext_z_store(i8 signext %a) {
; CHECK-LABEL: test_iltsc_sext_z_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addis r4, r2, glob@toc@ha
; CHECK-NEXT: srwi r3, r3, 7
; CHECK-NEXT: stb r3, glob@toc@l(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp slt i8 %a, 0
%conv2 = sext i1 %cmp to i8
Expand Down
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