204 changes: 102 additions & 102 deletions llvm/test/CodeGen/RISCV/double-br-fcmp.ll
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/double-calling-conv.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ define double @caller_double_inreg() nounwind {
; RV32IFD-LABEL: caller_double_inreg:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a0, 262236
; RV32IFD-NEXT: addi a1, a0, 655
; RV32IFD-NEXT: lui a0, 377487
Expand All @@ -42,7 +42,7 @@ define double @caller_double_inreg() nounwind {
; RV32IFD-NEXT: addi a3, a2, 655
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: call callee_double_inreg
; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
%1 = call double @callee_double_inreg(double 2.720000e+00, double 3.720000e+00)
Expand Down Expand Up @@ -74,7 +74,7 @@ define double @caller_double_split_reg_stack() nounwind {
; RV32IFD-LABEL: caller_double_split_reg_stack:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a0, 262510
; RV32IFD-NEXT: addi a2, a0, 327
; RV32IFD-NEXT: lui a0, 262446
Expand All @@ -89,7 +89,7 @@ define double @caller_double_split_reg_stack() nounwind {
; RV32IFD-NEXT: mv a4, zero
; RV32IFD-NEXT: mv a7, a5
; RV32IFD-NEXT: call callee_double_split_reg_stack
; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
%1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72)
Expand All @@ -116,7 +116,7 @@ define double @caller_double_stack() nounwind {
; RV32IFD-LABEL: caller_double_stack:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a0, 262510
; RV32IFD-NEXT: addi a0, a0, 327
; RV32IFD-NEXT: sw a0, 4(sp)
Expand All @@ -136,7 +136,7 @@ define double @caller_double_stack() nounwind {
; RV32IFD-NEXT: mv a5, zero
; RV32IFD-NEXT: mv a7, zero
; RV32IFD-NEXT: call callee_double_stack
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
%1 = call double @callee_double_stack(i64 1, i64 2, i64 3, i64 4, double 5.72, double 6.72)
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -136,9 +136,9 @@ define i64 @fcvt_l_d(double %a) nounwind {
; RV32IFD-LABEL: fcvt_l_d:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
Expand All @@ -155,9 +155,9 @@ define i64 @fcvt_lu_d(double %a) nounwind {
; RV32IFD-LABEL: fcvt_lu_d:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
Expand Down Expand Up @@ -203,9 +203,9 @@ define double @fcvt_d_l(i64 %a) nounwind {
; RV32IFD-LABEL: fcvt_d_l:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: call __floatdidf
; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __floatdidf@plt
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
Expand All @@ -222,9 +222,9 @@ define double @fcvt_d_lu(i64 %a) nounwind {
; RV32IFD-LABEL: fcvt_d_lu:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: call __floatundidf
; RV32IFD-NEXT: lw ra, 12(sp)
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: call __floatundidf@plt
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/double-frem.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,9 @@ define double @frem_f64(double %a, double %b) nounwind {
; RV32ID-LABEL: frem_f64:
; RV32ID: # %bb.0:
; RV32ID-NEXT: addi sp, sp, -16
; RV32ID-NEXT: sw ra, 12(sp)
; RV32ID-NEXT: call fmod
; RV32ID-NEXT: lw ra, 12(sp)
; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32ID-NEXT: call fmod@plt
; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32ID-NEXT: addi sp, sp, 16
; RV32ID-NEXT: ret
%1 = frem double %a, %b
Expand Down
216 changes: 108 additions & 108 deletions llvm/test/CodeGen/RISCV/double-intrinsics.ll
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32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/double-mem.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -158,36 +158,36 @@ define double @fld_stack(double %a) nounwind {
; RV32IFD-LABEL: fld_stack:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: addi a0, sp, 16
; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: call notdead@plt
; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fld_stack:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp)
; RV64IFD-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fsd ft0, 8(sp)
; RV64IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: addi a0, sp, 16
; RV64IFD-NEXT: call notdead
; RV64IFD-NEXT: call notdead@plt
; RV64IFD-NEXT: fld ft0, 16(sp)
; RV64IFD-NEXT: fld ft1, 8(sp)
; RV64IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld ra, 24(sp)
; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret
%1 = alloca double, align 8
Expand All @@ -202,7 +202,7 @@ define void @fsd_stack(double %a, double %b) nounwind {
; RV32IFD-LABEL: fsd_stack:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
Expand All @@ -212,22 +212,22 @@ define void @fsd_stack(double %a, double %b) nounwind {
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: addi a0, sp, 16
; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: call notdead@plt
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fsd_stack:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fsd ft0, 0(sp)
; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call notdead
; RV64IFD-NEXT: ld ra, 8(sp)
; RV64IFD-NEXT: call notdead@plt
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
%1 = fadd double %a, %b ; force store from FPR64
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/double-previous-failure.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ define i32 @main() nounwind {
; RV32IFD-LABEL: main:
; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a1, 262144
; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: call test
Expand All @@ -34,10 +34,10 @@ define i32 @main() nounwind {
; RV32IFD-NEXT: and a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB1_2
; RV32IFD-NEXT: # %bb.1: # %if.then
; RV32IFD-NEXT: call abort
; RV32IFD-NEXT: call abort@plt
; RV32IFD-NEXT: .LBB1_2: # %if.end
; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: call exit
; RV32IFD-NEXT: call exit@plt
entry:
%call = call double @test(double 2.000000e+00)
%cmp = fcmp olt double %call, 2.400000e-01
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ define double @func(double %d, i32 %n) nounwind {
; RV32IFD-LABEL: func:
; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp)
Expand All @@ -18,40 +18,40 @@ define double @func(double %d, i32 %n) nounwind {
; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call func
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) # 8-byte Folded Reload
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: .LBB0_2: # %return
; RV32IFD-NEXT: fsd ft0, 16(sp)
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: func:
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: slli a2, a1, 32
; RV64IFD-NEXT: srli a2, a2, 32
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: beqz a2, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, 0(sp)
; RV64IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call func
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fld ft1, 0(sp)
; RV64IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: .LBB0_2: # %return
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld ra, 8(sp)
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
entry:
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/RISCV/exception-pointer-register.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -17,9 +17,9 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: .cfi_def_cfa_offset 16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
Expand All @@ -28,18 +28,18 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
; RV32I-NEXT: # %bb.1: # %bb2
; RV32I-NEXT: .Ltmp0:
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call bar
; RV32I-NEXT: call bar@plt
; RV32I-NEXT: .Ltmp1:
; RV32I-NEXT: j .LBB0_3
; RV32I-NEXT: .LBB0_2: # %bb1
; RV32I-NEXT: .Ltmp2:
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call foo
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .Ltmp3:
; RV32I-NEXT: .LBB0_3: # %end2
; RV32I-NEXT: lw s1, 4(sp)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_4: # %lpad
Expand All @@ -48,15 +48,15 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call callee
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call _Unwind_Resume
; RV32I-NEXT: call _Unwind_Resume@plt
;
; RV64I-LABEL: caller:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: .cfi_def_cfa_offset 32
; RV64I-NEXT: sd ra, 24(sp)
; RV64I-NEXT: sd s0, 16(sp)
; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
Expand All @@ -65,18 +65,18 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
; RV64I-NEXT: # %bb.1: # %bb2
; RV64I-NEXT: .Ltmp0:
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call bar
; RV64I-NEXT: call bar@plt
; RV64I-NEXT: .Ltmp1:
; RV64I-NEXT: j .LBB0_3
; RV64I-NEXT: .LBB0_2: # %bb1
; RV64I-NEXT: .Ltmp2:
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call foo
; RV64I-NEXT: call foo@plt
; RV64I-NEXT: .Ltmp3:
; RV64I-NEXT: .LBB0_3: # %end2
; RV64I-NEXT: ld s1, 8(sp)
; RV64I-NEXT: ld s0, 16(sp)
; RV64I-NEXT: ld ra, 24(sp)
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_4: # %lpad
Expand All @@ -85,7 +85,7 @@ define void @caller(i1* %p) personality i8* bitcast (i32 (...)* @__gxx_personali
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call callee
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call _Unwind_Resume
; RV64I-NEXT: call _Unwind_Resume@plt
entry:
%0 = icmp eq i1* %p, null
br i1 %0, label %bb1, label %bb2
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/fastcc-float.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ define float @caller(<32 x float> %A) nounwind {
; CHECK-LABEL: caller:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -64
; CHECK-NEXT: sw ra, 60(sp)
; CHECK-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; CHECK-NEXT: flw fa0, 0(a0)
; CHECK-NEXT: flw fa1, 4(a0)
; CHECK-NEXT: flw fa2, 8(a0)
Expand Down Expand Up @@ -63,7 +63,7 @@ define float @caller(<32 x float> %A) nounwind {
; CHECK-NEXT: fsw fs1, 4(sp)
; CHECK-NEXT: fsw fs0, 0(sp)
; CHECK-NEXT: call callee
; CHECK-NEXT: lw ra, 60(sp)
; CHECK-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret
%C = call fastcc float @callee(<32 x float> %A)
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/fastcc-int.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@ define i32 @caller(<16 x i32> %A) nounwind {
; RV32-LABEL: caller:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -32
; RV32-NEXT: sw ra, 28(sp)
; RV32-NEXT: sw s0, 24(sp)
; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32-NEXT: lw t0, 0(a0)
; RV32-NEXT: lw a1, 4(a0)
; RV32-NEXT: lw a2, 8(a0)
Expand All @@ -45,16 +45,16 @@ define i32 @caller(<16 x i32> %A) nounwind {
; RV32-NEXT: sw t1, 0(sp)
; RV32-NEXT: mv a0, t0
; RV32-NEXT: call callee
; RV32-NEXT: lw s0, 24(sp)
; RV32-NEXT: lw ra, 28(sp)
; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret
;
; RV64-LABEL: caller:
; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -48
; RV64-NEXT: sd ra, 40(sp)
; RV64-NEXT: sd s0, 32(sp)
; RV64-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64-NEXT: ld t0, 0(a0)
; RV64-NEXT: ld a1, 8(a0)
; RV64-NEXT: ld a2, 16(a0)
Expand All @@ -76,8 +76,8 @@ define i32 @caller(<16 x i32> %A) nounwind {
; RV64-NEXT: sd t1, 0(sp)
; RV64-NEXT: mv a0, t0
; RV64-NEXT: call callee
; RV64-NEXT: ld s0, 32(sp)
; RV64-NEXT: ld ra, 40(sp)
; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 48
; RV64-NEXT: ret
%C = call fastcc i32 @callee(<16 x i32> %A)
Expand Down
84 changes: 42 additions & 42 deletions llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -66,22 +66,22 @@ define double @bitcast_double_and(double %a1, double %a2) nounwind {
; RV32F-LABEL: bitcast_double_and:
; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw ra, 12(sp)
; RV32F-NEXT: sw s0, 8(sp)
; RV32F-NEXT: sw s1, 4(sp)
; RV32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32F-NEXT: mv s0, a1
; RV32F-NEXT: mv s1, a0
; RV32F-NEXT: call __adddf3
; RV32F-NEXT: call __adddf3@plt
; RV32F-NEXT: mv a2, a0
; RV32F-NEXT: lui a0, 524288
; RV32F-NEXT: addi a0, a0, -1
; RV32F-NEXT: and a3, a1, a0
; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __adddf3
; RV32F-NEXT: lw s1, 4(sp)
; RV32F-NEXT: lw s0, 8(sp)
; RV32F-NEXT: lw ra, 12(sp)
; RV32F-NEXT: call __adddf3@plt
; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
Expand All @@ -106,18 +106,18 @@ define double @bitcast_double_and(double %a1, double %a2) nounwind {
; RV64F-LABEL: bitcast_double_and:
; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp)
; RV64F-NEXT: sd s0, 0(sp)
; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __adddf3
; RV64F-NEXT: call __adddf3@plt
; RV64F-NEXT: addi a1, zero, -1
; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: addi a1, a1, -1
; RV64F-NEXT: and a1, a0, a1
; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __adddf3
; RV64F-NEXT: ld s0, 0(sp)
; RV64F-NEXT: ld ra, 8(sp)
; RV64F-NEXT: call __adddf3@plt
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret
;
Expand Down Expand Up @@ -191,21 +191,21 @@ define double @bitcast_double_xor(double %a1, double %a2) nounwind {
; RV32F-LABEL: bitcast_double_xor:
; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw ra, 12(sp)
; RV32F-NEXT: sw s0, 8(sp)
; RV32F-NEXT: sw s1, 4(sp)
; RV32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32F-NEXT: mv s0, a1
; RV32F-NEXT: mv s1, a0
; RV32F-NEXT: call __muldf3
; RV32F-NEXT: call __muldf3@plt
; RV32F-NEXT: mv a2, a0
; RV32F-NEXT: lui a0, 524288
; RV32F-NEXT: xor a3, a1, a0
; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __muldf3
; RV32F-NEXT: lw s1, 4(sp)
; RV32F-NEXT: lw s0, 8(sp)
; RV32F-NEXT: lw ra, 12(sp)
; RV32F-NEXT: call __muldf3@plt
; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
Expand All @@ -230,17 +230,17 @@ define double @bitcast_double_xor(double %a1, double %a2) nounwind {
; RV64F-LABEL: bitcast_double_xor:
; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp)
; RV64F-NEXT: sd s0, 0(sp)
; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __muldf3
; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: addi a1, zero, -1
; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: xor a1, a0, a1
; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __muldf3
; RV64F-NEXT: ld s0, 0(sp)
; RV64F-NEXT: ld ra, 8(sp)
; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret
;
Expand Down Expand Up @@ -317,21 +317,21 @@ define double @bitcast_double_or(double %a1, double %a2) nounwind {
; RV32F-LABEL: bitcast_double_or:
; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16
; RV32F-NEXT: sw ra, 12(sp)
; RV32F-NEXT: sw s0, 8(sp)
; RV32F-NEXT: sw s1, 4(sp)
; RV32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32F-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32F-NEXT: mv s0, a1
; RV32F-NEXT: mv s1, a0
; RV32F-NEXT: call __muldf3
; RV32F-NEXT: call __muldf3@plt
; RV32F-NEXT: mv a2, a0
; RV32F-NEXT: lui a0, 524288
; RV32F-NEXT: or a3, a1, a0
; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __muldf3
; RV32F-NEXT: lw s1, 4(sp)
; RV32F-NEXT: lw s0, 8(sp)
; RV32F-NEXT: lw ra, 12(sp)
; RV32F-NEXT: call __muldf3@plt
; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
Expand All @@ -357,17 +357,17 @@ define double @bitcast_double_or(double %a1, double %a2) nounwind {
; RV64F-LABEL: bitcast_double_or:
; RV64F: # %bb.0:
; RV64F-NEXT: addi sp, sp, -16
; RV64F-NEXT: sd ra, 8(sp)
; RV64F-NEXT: sd s0, 0(sp)
; RV64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64F-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64F-NEXT: mv s0, a0
; RV64F-NEXT: call __muldf3
; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: addi a1, zero, -1
; RV64F-NEXT: slli a1, a1, 63
; RV64F-NEXT: or a1, a0, a1
; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __muldf3
; RV64F-NEXT: ld s0, 0(sp)
; RV64F-NEXT: ld ra, 8(sp)
; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret
;
Expand Down
238 changes: 119 additions & 119 deletions llvm/test/CodeGen/RISCV/float-br-fcmp.ll
View file

Large diffs are not rendered by default.

24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/float-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -121,9 +121,9 @@ define i64 @fcvt_l_s(float %a) nounwind {
; RV32IF-LABEL: fcvt_l_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: call __fixsfdi
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call __fixsfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
Expand All @@ -140,9 +140,9 @@ define i64 @fcvt_lu_s(float %a) nounwind {
; RV32IF-LABEL: fcvt_lu_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: call __fixunssfdi
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call __fixunssfdi@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
Expand All @@ -159,9 +159,9 @@ define float @fcvt_s_l(i64 %a) nounwind {
; RV32IF-LABEL: fcvt_s_l:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: call __floatdisf
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call __floatdisf@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
Expand All @@ -178,9 +178,9 @@ define float @fcvt_s_lu(i64 %a) nounwind {
; RV32IF-LABEL: fcvt_s_lu:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: call __floatundisf
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call __floatundisf@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/float-frem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,9 @@ define float @frem_f32(float %a, float %b) nounwind {
; RV32IF-LABEL: frem_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: call fmodf
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: call fmodf@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
%1 = frem float %a, %b
Expand Down
212 changes: 106 additions & 106 deletions llvm/test/CodeGen/RISCV/float-intrinsics.ll
View file

Large diffs are not rendered by default.

32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/float-mem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -134,32 +134,32 @@ define float @flw_stack(float %a) nounwind {
; RV32IF-LABEL: flw_stack:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fsw ft0, 4(sp)
; RV32IF-NEXT: fsw ft0, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: addi a0, sp, 8
; RV32IF-NEXT: call notdead
; RV32IF-NEXT: call notdead@plt
; RV32IF-NEXT: flw ft0, 8(sp)
; RV32IF-NEXT: flw ft1, 4(sp)
; RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: flw_stack:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fsw ft0, 0(sp)
; RV64IF-NEXT: fsw ft0, 0(sp) # 4-byte Folded Spill
; RV64IF-NEXT: addi a0, sp, 4
; RV64IF-NEXT: call notdead
; RV64IF-NEXT: call notdead@plt
; RV64IF-NEXT: flw ft0, 4(sp)
; RV64IF-NEXT: flw ft1, 0(sp)
; RV64IF-NEXT: flw ft1, 0(sp) # 4-byte Folded Reload
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
%1 = alloca float, align 4
Expand All @@ -174,28 +174,28 @@ define void @fsw_stack(float %a, float %b) nounwind {
; RV32IF-LABEL: fsw_stack:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fsw ft0, 8(sp)
; RV32IF-NEXT: addi a0, sp, 8
; RV32IF-NEXT: call notdead
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: call notdead@plt
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fsw_stack:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fsw ft0, 4(sp)
; RV64IF-NEXT: addi a0, sp, 4
; RV64IF-NEXT: call notdead
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: call notdead@plt
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
%1 = fadd float %a, %b ; force store from FPR32
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/RISCV/fp128.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ define i32 @test_load_and_cmp() nounwind {
; RV32I-LABEL: test_load_and_cmp:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a6, %lo(x)(a0)
; RV32I-NEXT: lw a7, %lo(x+4)(a0)
Expand All @@ -33,9 +33,9 @@ define i32 @test_load_and_cmp() nounwind {
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: sw a6, 24(sp)
; RV32I-NEXT: call __netf2
; RV32I-NEXT: call __netf2@plt
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw ra, 44(sp)
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
%1 = load fp128, fp128* @x, align 16
Expand All @@ -49,7 +49,7 @@ define i32 @test_add_and_fptosi() nounwind {
; RV32I-LABEL: test_add_and_fptosi:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw ra, 76(sp)
; RV32I-NEXT: sw ra, 76(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, %hi(x)
; RV32I-NEXT: lw a6, %lo(x)(a0)
; RV32I-NEXT: lw a7, %lo(x+4)(a0)
Expand All @@ -71,7 +71,7 @@ define i32 @test_add_and_fptosi() nounwind {
; RV32I-NEXT: addi a1, sp, 40
; RV32I-NEXT: addi a2, sp, 24
; RV32I-NEXT: sw a6, 40(sp)
; RV32I-NEXT: call __addtf3
; RV32I-NEXT: call __addtf3@plt
; RV32I-NEXT: lw a1, 56(sp)
; RV32I-NEXT: lw a0, 60(sp)
; RV32I-NEXT: lw a2, 64(sp)
Expand All @@ -81,8 +81,8 @@ define i32 @test_add_and_fptosi() nounwind {
; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: addi a0, sp, 8
; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: call __fixtfsi
; RV32I-NEXT: lw ra, 76(sp)
; RV32I-NEXT: call __fixtfsi@plt
; RV32I-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 80
; RV32I-NEXT: ret
%1 = load fp128, fp128* @x, align 16
Expand Down
76 changes: 38 additions & 38 deletions llvm/test/CodeGen/RISCV/fp16-promote.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,10 @@ define float @test_fpextend_float(half* %p) nounwind {
; CHECK-LABEL: test_fpextend_float:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp)
; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: lhu a0, 0(a0)
; CHECK-NEXT: call __gnu_h2f_ieee
; CHECK-NEXT: lw ra, 12(sp)
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%a = load half, half* %p
Expand All @@ -31,11 +31,11 @@ define double @test_fpextend_double(half* %p) nounwind {
; CHECK-LABEL: test_fpextend_double:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp)
; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: lhu a0, 0(a0)
; CHECK-NEXT: call __gnu_h2f_ieee
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fcvt.d.s fa0, fa0
; CHECK-NEXT: lw ra, 12(sp)
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%a = load half, half* %p
Expand All @@ -47,13 +47,13 @@ define void @test_fptrunc_float(float %f, half* %p) nounwind {
; CHECK-LABEL: test_fptrunc_float:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp)
; CHECK-NEXT: sw s0, 8(sp)
; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: call __gnu_f2h_ieee
; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: lw s0, 8(sp)
; CHECK-NEXT: lw ra, 12(sp)
; CHECK-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%a = fptrunc float %f to half
Expand All @@ -65,13 +65,13 @@ define void @test_fptrunc_double(double %d, half* %p) nounwind {
; CHECK-LABEL: test_fptrunc_double:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp)
; CHECK-NEXT: sw s0, 8(sp)
; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: call __truncdfhf2
; CHECK-NEXT: call __truncdfhf2@plt
; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: lw s0, 8(sp)
; CHECK-NEXT: lw ra, 12(sp)
; CHECK-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%a = fptrunc double %d to half
Expand All @@ -83,24 +83,24 @@ define void @test_fadd(half* %p, half* %q) nounwind {
; CHECK-LABEL: test_fadd:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sw ra, 28(sp)
; CHECK-NEXT: sw s0, 24(sp)
; CHECK-NEXT: sw s1, 20(sp)
; CHECK-NEXT: fsd fs0, 8(sp)
; CHECK-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; CHECK-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: mv s0, a1
; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: lhu a0, 0(a0)
; CHECK-NEXT: call __gnu_h2f_ieee
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.s fs0, fa0
; CHECK-NEXT: lhu a0, 0(s0)
; CHECK-NEXT: call __gnu_h2f_ieee
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fadd.s fa0, fs0, fa0
; CHECK-NEXT: call __gnu_f2h_ieee
; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: sh a0, 0(s1)
; CHECK-NEXT: fld fs0, 8(sp)
; CHECK-NEXT: lw s1, 20(sp)
; CHECK-NEXT: lw s0, 24(sp)
; CHECK-NEXT: lw ra, 28(sp)
; CHECK-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%a = load half, half* %p
Expand All @@ -114,24 +114,24 @@ define void @test_fmul(half* %p, half* %q) nounwind {
; CHECK-LABEL: test_fmul:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: sw ra, 28(sp)
; CHECK-NEXT: sw s0, 24(sp)
; CHECK-NEXT: sw s1, 20(sp)
; CHECK-NEXT: fsd fs0, 8(sp)
; CHECK-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; CHECK-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; CHECK-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: mv s0, a1
; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: lhu a0, 0(a0)
; CHECK-NEXT: call __gnu_h2f_ieee
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmv.s fs0, fa0
; CHECK-NEXT: lhu a0, 0(s0)
; CHECK-NEXT: call __gnu_h2f_ieee
; CHECK-NEXT: call __gnu_h2f_ieee@plt
; CHECK-NEXT: fmul.s fa0, fs0, fa0
; CHECK-NEXT: call __gnu_f2h_ieee
; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: sh a0, 0(s1)
; CHECK-NEXT: fld fs0, 8(sp)
; CHECK-NEXT: lw s1, 20(sp)
; CHECK-NEXT: lw s0, 24(sp)
; CHECK-NEXT: lw ra, 28(sp)
; CHECK-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%a = load half, half* %p
Expand Down
108 changes: 54 additions & 54 deletions llvm/test/CodeGen/RISCV/frame-info.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,29 +19,29 @@ define void @trivial() {
; RV32-WITHFP: # %bb.0:
; RV32-WITHFP-NEXT: addi sp, sp, -16
; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV32-WITHFP-NEXT: sw ra, 12(sp)
; RV32-WITHFP-NEXT: sw s0, 8(sp)
; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: .cfi_offset ra, -4
; RV32-WITHFP-NEXT: .cfi_offset s0, -8
; RV32-WITHFP-NEXT: addi s0, sp, 16
; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV32-WITHFP-NEXT: lw s0, 8(sp)
; RV32-WITHFP-NEXT: lw ra, 12(sp)
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: ret
;
; RV64-WITHFP-LABEL: trivial:
; RV64-WITHFP: # %bb.0:
; RV64-WITHFP-NEXT: addi sp, sp, -16
; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV64-WITHFP-NEXT: sd ra, 8(sp)
; RV64-WITHFP-NEXT: sd s0, 0(sp)
; RV64-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: .cfi_offset ra, -8
; RV64-WITHFP-NEXT: .cfi_offset s0, -16
; RV64-WITHFP-NEXT: addi s0, sp, 16
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV64-WITHFP-NEXT: ld s0, 0(sp)
; RV64-WITHFP-NEXT: ld ra, 8(sp)
; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: ret
ret void
Expand All @@ -52,8 +52,8 @@ define void @stack_alloc(i32 signext %size) {
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw ra, 12(sp)
; RV32-NEXT: sw s0, 8(sp)
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: .cfi_offset s0, -8
; RV32-NEXT: addi s0, sp, 16
Expand All @@ -62,19 +62,19 @@ define void @stack_alloc(i32 signext %size) {
; RV32-NEXT: andi a0, a0, -16
; RV32-NEXT: sub a0, sp, a0
; RV32-NEXT: mv sp, a0
; RV32-NEXT: call callee_with_args
; RV32-NEXT: call callee_with_args@plt
; RV32-NEXT: addi sp, s0, -16
; RV32-NEXT: lw s0, 8(sp)
; RV32-NEXT: lw ra, 12(sp)
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: stack_alloc:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp)
; RV64-NEXT: sd s0, 0(sp)
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: .cfi_offset s0, -16
; RV64-NEXT: addi s0, sp, 16
Expand All @@ -88,19 +88,19 @@ define void @stack_alloc(i32 signext %size) {
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: sub a0, sp, a0
; RV64-NEXT: mv sp, a0
; RV64-NEXT: call callee_with_args
; RV64-NEXT: call callee_with_args@plt
; RV64-NEXT: addi sp, s0, -16
; RV64-NEXT: ld s0, 0(sp)
; RV64-NEXT: ld ra, 8(sp)
; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret
;
; RV32-WITHFP-LABEL: stack_alloc:
; RV32-WITHFP: # %bb.0: # %entry
; RV32-WITHFP-NEXT: addi sp, sp, -16
; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV32-WITHFP-NEXT: sw ra, 12(sp)
; RV32-WITHFP-NEXT: sw s0, 8(sp)
; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: .cfi_offset ra, -4
; RV32-WITHFP-NEXT: .cfi_offset s0, -8
; RV32-WITHFP-NEXT: addi s0, sp, 16
Expand All @@ -109,19 +109,19 @@ define void @stack_alloc(i32 signext %size) {
; RV32-WITHFP-NEXT: andi a0, a0, -16
; RV32-WITHFP-NEXT: sub a0, sp, a0
; RV32-WITHFP-NEXT: mv sp, a0
; RV32-WITHFP-NEXT: call callee_with_args
; RV32-WITHFP-NEXT: call callee_with_args@plt
; RV32-WITHFP-NEXT: addi sp, s0, -16
; RV32-WITHFP-NEXT: lw s0, 8(sp)
; RV32-WITHFP-NEXT: lw ra, 12(sp)
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: ret
;
; RV64-WITHFP-LABEL: stack_alloc:
; RV64-WITHFP: # %bb.0: # %entry
; RV64-WITHFP-NEXT: addi sp, sp, -16
; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV64-WITHFP-NEXT: sd ra, 8(sp)
; RV64-WITHFP-NEXT: sd s0, 0(sp)
; RV64-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: .cfi_offset ra, -8
; RV64-WITHFP-NEXT: .cfi_offset s0, -16
; RV64-WITHFP-NEXT: addi s0, sp, 16
Expand All @@ -135,10 +135,10 @@ define void @stack_alloc(i32 signext %size) {
; RV64-WITHFP-NEXT: and a0, a0, a1
; RV64-WITHFP-NEXT: sub a0, sp, a0
; RV64-WITHFP-NEXT: mv sp, a0
; RV64-WITHFP-NEXT: call callee_with_args
; RV64-WITHFP-NEXT: call callee_with_args@plt
; RV64-WITHFP-NEXT: addi sp, s0, -16
; RV64-WITHFP-NEXT: ld s0, 0(sp)
; RV64-WITHFP-NEXT: ld ra, 8(sp)
; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: ret
entry:
Expand All @@ -152,83 +152,83 @@ define void @branch_and_tail_call(i1 %a) {
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw ra, 12(sp)
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: andi a0, a0, 1
; RV32-NEXT: beqz a0, .LBB2_2
; RV32-NEXT: # %bb.1: # %blue_pill
; RV32-NEXT: lw ra, 12(sp)
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: tail callee1
; RV32-NEXT: tail callee1@plt
; RV32-NEXT: .LBB2_2: # %red_pill
; RV32-NEXT: call callee2
; RV32-NEXT: lw ra, 12(sp)
; RV32-NEXT: call callee2@plt
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: branch_and_tail_call:
; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp)
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: andi a0, a0, 1
; RV64-NEXT: beqz a0, .LBB2_2
; RV64-NEXT: # %bb.1: # %blue_pill
; RV64-NEXT: ld ra, 8(sp)
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: tail callee1
; RV64-NEXT: tail callee1@plt
; RV64-NEXT: .LBB2_2: # %red_pill
; RV64-NEXT: call callee2
; RV64-NEXT: ld ra, 8(sp)
; RV64-NEXT: call callee2@plt
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret
;
; RV32-WITHFP-LABEL: branch_and_tail_call:
; RV32-WITHFP: # %bb.0:
; RV32-WITHFP-NEXT: addi sp, sp, -16
; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV32-WITHFP-NEXT: sw ra, 12(sp)
; RV32-WITHFP-NEXT: sw s0, 8(sp)
; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: .cfi_offset ra, -4
; RV32-WITHFP-NEXT: .cfi_offset s0, -8
; RV32-WITHFP-NEXT: addi s0, sp, 16
; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV32-WITHFP-NEXT: andi a0, a0, 1
; RV32-WITHFP-NEXT: beqz a0, .LBB2_2
; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill
; RV32-WITHFP-NEXT: lw s0, 8(sp)
; RV32-WITHFP-NEXT: lw ra, 12(sp)
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: tail callee1
; RV32-WITHFP-NEXT: tail callee1@plt
; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill
; RV32-WITHFP-NEXT: call callee2
; RV32-WITHFP-NEXT: lw s0, 8(sp)
; RV32-WITHFP-NEXT: lw ra, 12(sp)
; RV32-WITHFP-NEXT: call callee2@plt
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: ret
;
; RV64-WITHFP-LABEL: branch_and_tail_call:
; RV64-WITHFP: # %bb.0:
; RV64-WITHFP-NEXT: addi sp, sp, -16
; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16
; RV64-WITHFP-NEXT: sd ra, 8(sp)
; RV64-WITHFP-NEXT: sd s0, 0(sp)
; RV64-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64-WITHFP-NEXT: .cfi_offset ra, -8
; RV64-WITHFP-NEXT: .cfi_offset s0, -16
; RV64-WITHFP-NEXT: addi s0, sp, 16
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV64-WITHFP-NEXT: andi a0, a0, 1
; RV64-WITHFP-NEXT: beqz a0, .LBB2_2
; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill
; RV64-WITHFP-NEXT: ld s0, 0(sp)
; RV64-WITHFP-NEXT: ld ra, 8(sp)
; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: tail callee1
; RV64-WITHFP-NEXT: tail callee1@plt
; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill
; RV64-WITHFP-NEXT: call callee2
; RV64-WITHFP-NEXT: ld s0, 0(sp)
; RV64-WITHFP-NEXT: ld ra, 8(sp)
; RV64-WITHFP-NEXT: call callee2@plt
; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: ret
br i1 %a, label %blue_pill, label %red_pill
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/frame.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,35 +10,35 @@ define i32 @test() nounwind {
; RV32I-FPELIM-LABEL: test:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp)
; RV32I-FPELIM-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: sw zero, 24(sp)
; RV32I-FPELIM-NEXT: sw zero, 20(sp)
; RV32I-FPELIM-NEXT: sw zero, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 12(sp)
; RV32I-FPELIM-NEXT: sw zero, 8(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 12
; RV32I-FPELIM-NEXT: call test1
; RV32I-FPELIM-NEXT: call test1@plt
; RV32I-FPELIM-NEXT: mv a0, zero
; RV32I-FPELIM-NEXT: lw ra, 28(sp)
; RV32I-FPELIM-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: test:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -32
; RV32I-WITHFP-NEXT: sw ra, 28(sp)
; RV32I-WITHFP-NEXT: sw s0, 24(sp)
; RV32I-WITHFP-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: sw zero, -24(s0)
; RV32I-WITHFP-NEXT: sw zero, -28(s0)
; RV32I-WITHFP-NEXT: sw zero, -32(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, -28
; RV32I-WITHFP-NEXT: call test1
; RV32I-WITHFP-NEXT: call test1@plt
; RV32I-WITHFP-NEXT: mv a0, zero
; RV32I-WITHFP-NEXT: lw s0, 24(sp)
; RV32I-WITHFP-NEXT: lw ra, 28(sp)
; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret
%key = alloca %struct.key_t, align 4
Expand Down
68 changes: 34 additions & 34 deletions llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,24 +12,24 @@ define i8* @test_frameaddress_0() nounwind {
; RV32I-LABEL: test_frameaddress_0:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_frameaddress_0:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sd s0, 0(sp)
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 16
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: ld s0, 0(sp)
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call i8* @llvm.frameaddress(i32 0)
Expand All @@ -40,26 +40,26 @@ define i8* @test_frameaddress_2() nounwind {
; RV32I-LABEL: test_frameaddress_2:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a0, -8(s0)
; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_frameaddress_2:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sd s0, 0(sp)
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 16
; RV64I-NEXT: ld a0, -16(s0)
; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld s0, 0(sp)
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call i8* @llvm.frameaddress(i32 2)
Expand All @@ -70,32 +70,32 @@ define i8* @test_frameaddress_3_alloca() nounwind {
; RV32I-LABEL: test_frameaddress_3_alloca:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -112
; RV32I-NEXT: sw ra, 108(sp)
; RV32I-NEXT: sw s0, 104(sp)
; RV32I-NEXT: sw ra, 108(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 104(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 112
; RV32I-NEXT: addi a0, s0, -108
; RV32I-NEXT: call notdead
; RV32I-NEXT: call notdead@plt
; RV32I-NEXT: lw a0, -8(s0)
; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw s0, 104(sp)
; RV32I-NEXT: lw ra, 108(sp)
; RV32I-NEXT: lw s0, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 108(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 112
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_frameaddress_3_alloca:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -128
; RV64I-NEXT: sd ra, 120(sp)
; RV64I-NEXT: sd s0, 112(sp)
; RV64I-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 128
; RV64I-NEXT: addi a0, s0, -116
; RV64I-NEXT: call notdead
; RV64I-NEXT: call notdead@plt
; RV64I-NEXT: ld a0, -16(s0)
; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld s0, 112(sp)
; RV64I-NEXT: ld ra, 120(sp)
; RV64I-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 128
; RV64I-NEXT: ret
%1 = alloca [100 x i8]
Expand Down Expand Up @@ -123,28 +123,28 @@ define i8* @test_returnaddress_2() nounwind {
; RV32I-LABEL: test_returnaddress_2:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a0, -8(s0)
; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw a0, -4(a0)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_returnaddress_2:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sd s0, 0(sp)
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 16
; RV64I-NEXT: ld a0, -16(s0)
; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld a0, -8(a0)
; RV64I-NEXT: ld s0, 0(sp)
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call i8* @llvm.returnaddress(i32 2)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/ghccc-rv32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ define ghccc void @foo() nounwind {
; CHECK-NEXT: lw s2, %lo(sp)(a0)
; CHECK-NEXT: lui a0, %hi(base)
; CHECK-NEXT: lw s1, %lo(base)(a0)
; CHECK-NEXT: tail bar
; CHECK-NEXT: tail bar@plt
entry:
%0 = load double, double* @d6
%1 = load double, double* @d5
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/ghccc-rv64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ define ghccc void @foo() nounwind {
; CHECK-NEXT: ld s2, %lo(sp)(a0)
; CHECK-NEXT: lui a0, %hi(base)
; CHECK-NEXT: ld s1, %lo(base)(a0)
; CHECK-NEXT: tail bar
; CHECK-NEXT: tail bar@plt
entry:
%0 = load double, double* @d6
%1 = load double, double* @d5
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -82,13 +82,13 @@ define half @fcopysign_fneg(half %a, half %b) nounwind {
; RV32I-LABEL: fcopysign_fneg:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: call __gnu_h2f_ieee
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: not a1, s0
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: addi a2, a2, -1
Expand All @@ -97,9 +97,9 @@ define half @fcopysign_fneg(half %a, half %b) nounwind {
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a1, a1, 16
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: call __gnu_f2h_ieee
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -111,13 +111,13 @@ define half @fcopysign_fneg(half %a, half %b) nounwind {
; RV64I-LABEL: fcopysign_fneg:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sd s0, 0(sp)
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: call __gnu_h2f_ieee
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: not a1, s0
; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: addiw a2, a2, -1
Expand All @@ -129,9 +129,9 @@ define half @fcopysign_fneg(half %a, half %b) nounwind {
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a1, a1, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: call __gnu_f2h_ieee
; RV64I-NEXT: ld s0, 0(sp)
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand Down
204 changes: 102 additions & 102 deletions llvm/test/CodeGen/RISCV/half-br-fcmp.ll
View file

Large diffs are not rendered by default.

72 changes: 36 additions & 36 deletions llvm/test/CodeGen/RISCV/half-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -108,18 +108,18 @@ define i64 @fcvt_l_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_l_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp)
; RV32IZFH-NEXT: call __fixhfdi
; RV32IZFH-NEXT: lw ra, 12(sp)
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call __fixhfdi@plt
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_l_h:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp)
; RV32IDZFH-NEXT: call __fixhfdi
; RV32IDZFH-NEXT: lw ra, 12(sp)
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: call __fixhfdi@plt
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
Expand All @@ -140,18 +140,18 @@ define i64 @fcvt_lu_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_lu_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp)
; RV32IZFH-NEXT: call __fixunshfdi
; RV32IZFH-NEXT: lw ra, 12(sp)
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call __fixunshfdi@plt
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_lu_h:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp)
; RV32IDZFH-NEXT: call __fixunshfdi
; RV32IDZFH-NEXT: lw ra, 12(sp)
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: call __fixunshfdi@plt
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
Expand Down Expand Up @@ -288,18 +288,18 @@ define half @fcvt_h_l(i64 %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_l:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp)
; RV32IZFH-NEXT: call __floatdihf
; RV32IZFH-NEXT: lw ra, 12(sp)
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call __floatdihf@plt
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_l:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp)
; RV32IDZFH-NEXT: call __floatdihf
; RV32IDZFH-NEXT: lw ra, 12(sp)
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: call __floatdihf@plt
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
Expand All @@ -320,18 +320,18 @@ define half @fcvt_h_lu(i64 %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_lu:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp)
; RV32IZFH-NEXT: call __floatundihf
; RV32IZFH-NEXT: lw ra, 12(sp)
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call __floatundihf@plt
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_h_lu:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: addi sp, sp, -16
; RV32IDZFH-NEXT: sw ra, 12(sp)
; RV32IDZFH-NEXT: call __floatundihf
; RV32IDZFH-NEXT: lw ra, 12(sp)
; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IDZFH-NEXT: call __floatundihf@plt
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
;
Expand Down Expand Up @@ -400,9 +400,9 @@ define half @fcvt_h_d(double %a) nounwind {
; RV32IZFH-LABEL: fcvt_h_d:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp)
; RV32IZFH-NEXT: call __truncdfhf2
; RV32IZFH-NEXT: lw ra, 12(sp)
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: call __truncdfhf2@plt
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
Expand All @@ -414,9 +414,9 @@ define half @fcvt_h_d(double %a) nounwind {
; RV64IZFH-LABEL: fcvt_h_d:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp)
; RV64IZFH-NEXT: call __truncdfhf2
; RV64IZFH-NEXT: ld ra, 8(sp)
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: call __truncdfhf2@plt
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
Expand All @@ -432,10 +432,10 @@ define double @fcvt_d_h(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_d_h:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp)
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
; RV32IZFH-NEXT: call __extendsfdf2
; RV32IZFH-NEXT: lw ra, 12(sp)
; RV32IZFH-NEXT: call __extendsfdf2@plt
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
Expand All @@ -447,10 +447,10 @@ define double @fcvt_d_h(half %a) nounwind {
; RV64IZFH-LABEL: fcvt_d_h:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp)
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: call __extendsfdf2
; RV64IZFH-NEXT: ld ra, 8(sp)
; RV64IZFH-NEXT: call __extendsfdf2@plt
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/half-mem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -118,30 +118,30 @@ define half @flh_stack(half %a) nounwind {
; RV32IZFH-LABEL: flh_stack:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp)
; RV32IZFH-NEXT: fsw fs0, 8(sp)
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fmv.h fs0, fa0
; RV32IZFH-NEXT: addi a0, sp, 4
; RV32IZFH-NEXT: call notdead
; RV32IZFH-NEXT: call notdead@plt
; RV32IZFH-NEXT: flh ft0, 4(sp)
; RV32IZFH-NEXT: fadd.h fa0, ft0, fs0
; RV32IZFH-NEXT: flw fs0, 8(sp)
; RV32IZFH-NEXT: lw ra, 12(sp)
; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: flh_stack:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp)
; RV64IZFH-NEXT: fsw fs0, 4(sp)
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
; RV64IZFH-NEXT: fmv.h fs0, fa0
; RV64IZFH-NEXT: mv a0, sp
; RV64IZFH-NEXT: call notdead
; RV64IZFH-NEXT: call notdead@plt
; RV64IZFH-NEXT: flh ft0, 0(sp)
; RV64IZFH-NEXT: fadd.h fa0, ft0, fs0
; RV64IZFH-NEXT: flw fs0, 4(sp)
; RV64IZFH-NEXT: ld ra, 8(sp)
; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
%1 = alloca half, align 4
Expand All @@ -156,24 +156,24 @@ define void @fsh_stack(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fsh_stack:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp)
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
; RV32IZFH-NEXT: fsh ft0, 8(sp)
; RV32IZFH-NEXT: addi a0, sp, 8
; RV32IZFH-NEXT: call notdead
; RV32IZFH-NEXT: lw ra, 12(sp)
; RV32IZFH-NEXT: call notdead@plt
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fsh_stack:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp)
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
; RV64IZFH-NEXT: fsh ft0, 4(sp)
; RV64IZFH-NEXT: addi a0, sp, 4
; RV64IZFH-NEXT: call notdead
; RV64IZFH-NEXT: ld ra, 8(sp)
; RV64IZFH-NEXT: call notdead@plt
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b ; force store from FPR16
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -128,18 +128,18 @@ define dso_local i32 @load_half() nounwind {
; CHECK-LABEL: load_half:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw ra, 12(sp)
; CHECK-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-NEXT: lui a0, %hi(foo+8)
; CHECK-NEXT: lhu a0, %lo(foo+8)(a0)
; CHECK-NEXT: addi a1, zero, 140
; CHECK-NEXT: bne a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: lw ra, 12(sp)
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB7_2: # %if.then
; CHECK-NEXT: call abort
; CHECK-NEXT: call abort@plt
entry:
%0 = load i16, i16* getelementptr inbounds ([6 x i16], [6 x i16]* @foo, i32 0, i32 4), align 2
%cmp = icmp eq i16 %0, 140
Expand Down
248 changes: 124 additions & 124 deletions llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
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Large diffs are not rendered by default.

192 changes: 96 additions & 96 deletions llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll
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Large diffs are not rendered by default.

192 changes: 96 additions & 96 deletions llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll
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Large diffs are not rendered by default.

42 changes: 21 additions & 21 deletions llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,50 +14,50 @@ define dso_local void @handler() nounwind {
; CHECK-RV32-LABEL: handler:
; CHECK-RV32: # %bb.0: # %entry
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: sw ra, 12(sp)
; CHECK-RV32-NEXT: sw s0, 8(sp)
; CHECK-RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-NEXT: lui a0, 2
; CHECK-RV32-NEXT: addi a0, a0, 4
; CHECK-RV32-NEXT: call read
; CHECK-RV32-NEXT: call read@plt
; CHECK-RV32-NEXT: mv s0, a0
; CHECK-RV32-NEXT: call callee
; CHECK-RV32-NEXT: call callee@plt
; CHECK-RV32-NEXT: mv a0, s0
; CHECK-RV32-NEXT: lw s0, 8(sp)
; CHECK-RV32-NEXT: lw ra, 12(sp)
; CHECK-RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: tail write
; CHECK-RV32-NEXT: tail write@plt
;
; CHECK-RV32-F-LABEL: handler:
; CHECK-RV32-F: # %bb.0: # %entry
; CHECK-RV32-F-NEXT: addi sp, sp, -16
; CHECK-RV32-F-NEXT: sw ra, 12(sp)
; CHECK-RV32-F-NEXT: sw s0, 8(sp)
; CHECK-RV32-F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-F-NEXT: lui a0, 2
; CHECK-RV32-F-NEXT: addi a0, a0, 4
; CHECK-RV32-F-NEXT: call read
; CHECK-RV32-F-NEXT: call read@plt
; CHECK-RV32-F-NEXT: mv s0, a0
; CHECK-RV32-F-NEXT: call callee
; CHECK-RV32-F-NEXT: call callee@plt
; CHECK-RV32-F-NEXT: mv a0, s0
; CHECK-RV32-F-NEXT: lw s0, 8(sp)
; CHECK-RV32-F-NEXT: lw ra, 12(sp)
; CHECK-RV32-F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: addi sp, sp, 16
; CHECK-RV32-F-NEXT: tail write
; CHECK-RV32-F-NEXT: tail write@plt
;
; CHECK-RV32-FD-LABEL: handler:
; CHECK-RV32-FD: # %bb.0: # %entry
; CHECK-RV32-FD-NEXT: addi sp, sp, -16
; CHECK-RV32-FD-NEXT: sw ra, 12(sp)
; CHECK-RV32-FD-NEXT: sw s0, 8(sp)
; CHECK-RV32-FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK-RV32-FD-NEXT: lui a0, 2
; CHECK-RV32-FD-NEXT: addi a0, a0, 4
; CHECK-RV32-FD-NEXT: call read
; CHECK-RV32-FD-NEXT: call read@plt
; CHECK-RV32-FD-NEXT: mv s0, a0
; CHECK-RV32-FD-NEXT: call callee
; CHECK-RV32-FD-NEXT: call callee@plt
; CHECK-RV32-FD-NEXT: mv a0, s0
; CHECK-RV32-FD-NEXT: lw s0, 8(sp)
; CHECK-RV32-FD-NEXT: lw ra, 12(sp)
; CHECK-RV32-FD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: addi sp, sp, 16
; CHECK-RV32-FD-NEXT: tail write
; CHECK-RV32-FD-NEXT: tail write@plt
entry:
%call = tail call i32 @read(i32 8196)
tail call void bitcast (void (...)* @callee to void ()*)()
Expand Down
832 changes: 416 additions & 416 deletions llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
View file

Large diffs are not rendered by default.

1,840 changes: 920 additions & 920 deletions llvm/test/CodeGen/RISCV/interrupt-attr.ll
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Large diffs are not rendered by default.

32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/large-stack.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@ define void @test() {
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -2032
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
; RV32I-WITHFP-NEXT: sw ra, 2028(sp)
; RV32I-WITHFP-NEXT: sw s0, 2024(sp)
; RV32I-WITHFP-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: .cfi_offset ra, -4
; RV32I-WITHFP-NEXT: .cfi_offset s0, -8
; RV32I-WITHFP-NEXT: addi s0, sp, 2032
Expand All @@ -34,8 +34,8 @@ define void @test() {
; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, -352
; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: lw s0, 2024(sp)
; RV32I-WITHFP-NEXT: lw ra, 2028(sp)
; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
; RV32I-WITHFP-NEXT: ret
%tmp = alloca [ 305419896 x i8 ] , align 4
Expand All @@ -50,8 +50,8 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -2032
; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032
; RV32I-FPELIM-NEXT: sw s0, 2028(sp)
; RV32I-FPELIM-NEXT: sw s1, 2024(sp)
; RV32I-FPELIM-NEXT: sw s0, 2028(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: sw s1, 2024(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: .cfi_offset s0, -4
; RV32I-FPELIM-NEXT: .cfi_offset s1, -8
; RV32I-FPELIM-NEXT: lui a1, 97
Expand All @@ -74,19 +74,19 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-FPELIM-NEXT: lui a0, 97
; RV32I-FPELIM-NEXT: addi a0, a0, 672
; RV32I-FPELIM-NEXT: add sp, sp, a0
; RV32I-FPELIM-NEXT: lw s1, 2024(sp)
; RV32I-FPELIM-NEXT: lw s0, 2028(sp)
; RV32I-FPELIM-NEXT: lw s1, 2024(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: lw s0, 2028(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 2032
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -2032
; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
; RV32I-WITHFP-NEXT: sw ra, 2028(sp)
; RV32I-WITHFP-NEXT: sw s0, 2024(sp)
; RV32I-WITHFP-NEXT: sw s1, 2020(sp)
; RV32I-WITHFP-NEXT: sw s2, 2016(sp)
; RV32I-WITHFP-NEXT: sw ra, 2028(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 2024(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s1, 2020(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s2, 2016(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: .cfi_offset ra, -4
; RV32I-WITHFP-NEXT: .cfi_offset s0, -8
; RV32I-WITHFP-NEXT: .cfi_offset s1, -12
Expand Down Expand Up @@ -115,10 +115,10 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-WITHFP-NEXT: lui a0, 97
; RV32I-WITHFP-NEXT: addi a0, a0, 688
; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: lw s2, 2016(sp)
; RV32I-WITHFP-NEXT: lw s1, 2020(sp)
; RV32I-WITHFP-NEXT: lw s0, 2024(sp)
; RV32I-WITHFP-NEXT: lw ra, 2028(sp)
; RV32I-WITHFP-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
; RV32I-WITHFP-NEXT: ret
%data = alloca [ 100000 x i32 ] , align 4
Expand Down
60 changes: 30 additions & 30 deletions llvm/test/CodeGen/RISCV/mul.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,10 @@ define signext i32 @square(i32 %a) nounwind {
; RV32I-LABEL: square:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -27,11 +27,11 @@ define signext i32 @square(i32 %a) nounwind {
; RV64I-LABEL: square:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand All @@ -47,9 +47,9 @@ define signext i32 @mul(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: mul:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -61,10 +61,10 @@ define signext i32 @mul(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: mul:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand Down Expand Up @@ -132,9 +132,9 @@ define i64 @mul64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: mul64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: call __muldi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -151,9 +151,9 @@ define i64 @mul64(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: mul64:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand Down Expand Up @@ -207,13 +207,13 @@ define i32 @mulhs(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: mulhs:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: srai a1, a0, 31
; RV32I-NEXT: srai a3, a2, 31
; RV32I-NEXT: call __muldi3
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -225,12 +225,12 @@ define i32 @mulhs(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: mulhs:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand All @@ -253,13 +253,13 @@ define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV32I-LABEL: mulhu:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: call __muldi3
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -271,10 +271,10 @@ define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64I-LABEL: mulhu:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/rem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,9 +12,9 @@ define i32 @urem(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: urem:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: call __umodsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -26,13 +26,13 @@ define i32 @urem(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: urem:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: call __umoddi3
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand All @@ -48,9 +48,9 @@ define i32 @srem(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: srem:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: call __modsi3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -62,11 +62,11 @@ define i32 @srem(i32 %a, i32 %b) nounwind {
; RV64I-LABEL: srem:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: sext.w a1, a1
; RV64I-NEXT: call __moddi3
; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand Down
60 changes: 30 additions & 30 deletions llvm/test/CodeGen/RISCV/remat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,19 +24,19 @@ define i32 @test() nounwind {
; RV32I-LABEL: test:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -64
; RV32I-NEXT: sw ra, 60(sp)
; RV32I-NEXT: sw s0, 56(sp)
; RV32I-NEXT: sw s1, 52(sp)
; RV32I-NEXT: sw s2, 48(sp)
; RV32I-NEXT: sw s3, 44(sp)
; RV32I-NEXT: sw s4, 40(sp)
; RV32I-NEXT: sw s5, 36(sp)
; RV32I-NEXT: sw s6, 32(sp)
; RV32I-NEXT: sw s7, 28(sp)
; RV32I-NEXT: sw s8, 24(sp)
; RV32I-NEXT: sw s9, 20(sp)
; RV32I-NEXT: sw s10, 16(sp)
; RV32I-NEXT: sw s11, 12(sp)
; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 48(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 44(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 40(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 36(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 32(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s7, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s8, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s9, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s10, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui s6, %hi(a)
; RV32I-NEXT: lw a0, %lo(a)(s6)
; RV32I-NEXT: beqz a0, .LBB0_11
Expand Down Expand Up @@ -70,7 +70,7 @@ define i32 @test() nounwind {
; RV32I-NEXT: lw a3, %lo(d)(s1)
; RV32I-NEXT: lw a4, %lo(e)(s0)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_5: # %if.end
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(k)(s3)
Expand All @@ -83,7 +83,7 @@ define i32 @test() nounwind {
; RV32I-NEXT: lw a3, %lo(e)(s0)
; RV32I-NEXT: lw a4, %lo(f)(s7)
; RV32I-NEXT: addi a5, zero, 64
; RV32I-NEXT: call foo
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_7: # %if.end5
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(j)(s4)
Expand All @@ -96,7 +96,7 @@ define i32 @test() nounwind {
; RV32I-NEXT: lw a3, %lo(f)(s7)
; RV32I-NEXT: lw a4, %lo(g)(s8)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_9: # %if.end9
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
; RV32I-NEXT: lw a0, %lo(i)(s5)
Expand All @@ -109,23 +109,23 @@ define i32 @test() nounwind {
; RV32I-NEXT: lw a3, %lo(g)(s8)
; RV32I-NEXT: lw a4, %lo(h)(s9)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: call foo
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: j .LBB0_2
; RV32I-NEXT: .LBB0_11: # %for.end
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: lw s11, 12(sp)
; RV32I-NEXT: lw s10, 16(sp)
; RV32I-NEXT: lw s9, 20(sp)
; RV32I-NEXT: lw s8, 24(sp)
; RV32I-NEXT: lw s7, 28(sp)
; RV32I-NEXT: lw s6, 32(sp)
; RV32I-NEXT: lw s5, 36(sp)
; RV32I-NEXT: lw s4, 40(sp)
; RV32I-NEXT: lw s3, 44(sp)
; RV32I-NEXT: lw s2, 48(sp)
; RV32I-NEXT: lw s1, 52(sp)
; RV32I-NEXT: lw s0, 56(sp)
; RV32I-NEXT: lw ra, 60(sp)
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
entry:
Expand Down
122 changes: 61 additions & 61 deletions llvm/test/CodeGen/RISCV/rv32Zbb.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -318,7 +318,7 @@ define i32 @ctlz_i32(i32 %a) nounwind {
; RV32I-LABEL: ctlz_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a0, .LBB8_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: srli a1, a0, 1
Expand Down Expand Up @@ -350,13 +350,13 @@ define i32 @ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB8_3
; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB8_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -379,14 +379,14 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-LABEL: ctlz_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: sw s6, 0(sp)
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: srli a0, a1, 1
Expand Down Expand Up @@ -419,7 +419,7 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s0, a1, 257
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: srli a0, s4, 1
; RV32I-NEXT: or a0, s4, a0
Expand All @@ -443,7 +443,7 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s3, .LBB9_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
Expand All @@ -453,14 +453,14 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB9_3:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s6, 0(sp)
; RV32I-NEXT: lw s5, 4(sp)
; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -499,7 +499,7 @@ define i32 @cttz_i32(i32 %a) nounwind {
; RV32I-LABEL: cttz_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: beqz a0, .LBB10_2
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: addi a1, a0, -1
Expand All @@ -523,13 +523,13 @@ define i32 @cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: j .LBB10_3
; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: .LBB10_3: # %cond.end
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -552,14 +552,14 @@ define i64 @cttz_i64(i64 %a) nounwind {
; RV32I-LABEL: cttz_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: sw s6, 0(sp)
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s3, a1
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: addi a0, a0, -1
Expand All @@ -584,7 +584,7 @@ define i64 @cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1
; RV32I-NEXT: not a1, s3
Expand All @@ -600,7 +600,7 @@ define i64 @cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: bnez s4, .LBB11_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
Expand All @@ -610,14 +610,14 @@ define i64 @cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s6, 0(sp)
; RV32I-NEXT: lw s5, 4(sp)
; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -656,7 +656,7 @@ define i32 @ctpop_i32(i32 %a) nounwind {
; RV32I-LABEL: ctpop_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
Expand All @@ -675,9 +675,9 @@ define i32 @ctpop_i32(i32 %a) nounwind {
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -700,13 +700,13 @@ define i64 @ctpop_i64(i64 %a) nounwind {
; RV32I-LABEL: ctpop_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
; RV32I-NEXT: sw s0, 24(sp)
; RV32I-NEXT: sw s1, 20(sp)
; RV32I-NEXT: sw s2, 16(sp)
; RV32I-NEXT: sw s3, 12(sp)
; RV32I-NEXT: sw s4, 8(sp)
; RV32I-NEXT: sw s5, 4(sp)
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: srli a0, a1, 1
; RV32I-NEXT: lui a2, 349525
Expand All @@ -727,7 +727,7 @@ define i64 @ctpop_i64(i64 %a) nounwind {
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli s5, a0, 24
; RV32I-NEXT: srli a0, s2, 1
; RV32I-NEXT: and a0, a0, s3
Expand All @@ -740,17 +740,17 @@ define i64 @ctpop_i64(i64 %a) nounwind {
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: add a0, a0, s5
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: lw s5, 4(sp)
; RV32I-NEXT: lw s4, 8(sp)
; RV32I-NEXT: lw s3, 12(sp)
; RV32I-NEXT: lw s2, 16(sp)
; RV32I-NEXT: lw s1, 20(sp)
; RV32I-NEXT: lw s0, 24(sp)
; RV32I-NEXT: lw ra, 28(sp)
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down
52 changes: 26 additions & 26 deletions llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,28 +15,28 @@ define float @float_test(float %a, float %b) nounwind {
; RV32IF-LABEL: float_test:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s0, 8(sp)
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: mv s0, a1
; RV32IF-NEXT: call __addsf3
; RV32IF-NEXT: call __addsf3@plt
; RV32IF-NEXT: mv a1, s0
; RV32IF-NEXT: call __divsf3
; RV32IF-NEXT: lw s0, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: call __divsf3@plt
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: float_test:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: sd s0, 0(sp)
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64IF-NEXT: mv s0, a1
; RV64IF-NEXT: call __addsf3
; RV64IF-NEXT: call __addsf3@plt
; RV64IF-NEXT: mv a1, s0
; RV64IF-NEXT: call __divsf3
; RV64IF-NEXT: ld s0, 0(sp)
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: call __divsf3@plt
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
%1 = fadd float %a, %b
Expand All @@ -48,32 +48,32 @@ define double @double_test(double %a, double %b) nounwind {
; RV32IF-LABEL: double_test:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s0, 8(sp)
; RV32IF-NEXT: sw s1, 4(sp)
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32IF-NEXT: mv s0, a3
; RV32IF-NEXT: mv s1, a2
; RV32IF-NEXT: call __adddf3
; RV32IF-NEXT: call __adddf3@plt
; RV32IF-NEXT: mv a2, s1
; RV32IF-NEXT: mv a3, s0
; RV32IF-NEXT: call __divdf3
; RV32IF-NEXT: lw s1, 4(sp)
; RV32IF-NEXT: lw s0, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: call __divdf3@plt
; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: double_test:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: sd s0, 0(sp)
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64IF-NEXT: mv s0, a1
; RV64IF-NEXT: call __adddf3
; RV64IF-NEXT: call __adddf3@plt
; RV64IF-NEXT: mv a1, s0
; RV64IF-NEXT: call __divdf3
; RV64IF-NEXT: ld s0, 0(sp)
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: call __divdf3@plt
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
%1 = fadd double %a, %b
Expand Down
52 changes: 26 additions & 26 deletions llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,58 +13,58 @@ define half @half_test(half %a, half %b) nounwind {
; RV32I-LABEL: half_test:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: sw s2, 0(sp)
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s0, a1, -1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: call __gnu_h2f_ieee
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s2, s0
; RV32I-NEXT: call __gnu_h2f_ieee
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __addsf3
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __divsf3
; RV32I-NEXT: call __gnu_f2h_ieee
; RV32I-NEXT: lw s2, 0(sp)
; RV32I-NEXT: lw s1, 4(sp)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: call __divsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: half_test:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp)
; RV64I-NEXT: sd s0, 16(sp)
; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: sd s2, 0(sp)
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s2, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s0, a1, -1
; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: call __gnu_h2f_ieee
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s2, s0
; RV64I-NEXT: call __gnu_h2f_ieee
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __addsf3
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __divsf3
; RV64I-NEXT: call __gnu_f2h_ieee
; RV64I-NEXT: ld s2, 0(sp)
; RV64I-NEXT: ld s1, 8(sp)
; RV64I-NEXT: ld s0, 16(sp)
; RV64I-NEXT: ld ra, 24(sp)
; RV64I-NEXT: call __divsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%1 = fadd half %a, %b
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/rv64-large-stack.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,20 +8,20 @@ define void @foo() nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -2032
; CHECK-NEXT: sd ra, 2024(sp)
; CHECK-NEXT: sd ra, 2024(sp) # 8-byte Folded Spill
; CHECK-NEXT: lui a0, 95
; CHECK-NEXT: addiw a0, a0, 1505
; CHECK-NEXT: slli a0, a0, 13
; CHECK-NEXT: addi a0, a0, -2000
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: call baz
; CHECK-NEXT: call baz@plt
; CHECK-NEXT: lui a0, 95
; CHECK-NEXT: addiw a0, a0, 1505
; CHECK-NEXT: slli a0, a0, 13
; CHECK-NEXT: addi a0, a0, -2000
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ld ra, 2024(sp)
; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 2032
; CHECK-NEXT: ret
entry:
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