[GlobalISel] Value to vreg during IR to MachineInstr translation for aggregate type

[qcolombet]

Bugzilla Link	26161
Resolution	FIXED
Resolved on	May 18, 2018 06:34
Version	trunk
OS	All
Blocks	#34708 #34709 #34707
CC	@aemerson,@adibiagio,@bcardosolopes,@hfinkel

Extended Description

The design to handle aggregate types during IR translation in GlobalISel will need to be revisited to at least acknowledge that we choose the right approach.

At first, this is not critical that we don’t support aggregate types, thus a simple mapping one Value* to one Vreg is perfectly fine.

When we would add the support for such types, we have basically two options:

1. Replicate SDAG solution, i.e., more or less map one Value* to a list of Vregs (one Vreg per component).
2. Keep the mapping simple, i.e., one Value* to one (big) Vreg.

The pros and cons are discussed in the following thread:
http://lists.llvm.org/pipermail/llvm-dev/2016-January/094049.html

Although #​2 seems preferable, we don’t have any actual experience on how well we would be to optimize this representation.

[qcolombet]

assigned to @aemerson

[aemerson]

We now split aggregates into multiple Regs as of r332449.

[aemerson]

mentioned in issue #34707

[ostannard]

mentioned in issue #34707

[aemerson]

mentioned in issue #34709

[ostannard]

mentioned in issue #34708