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likely arm64 miscompile #55201
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@llvm/issue-subscribers-backend-aarch64 |
bad asm from the default backend _f:
ror w8, w0, #27
orr w0, w8, #0x20
ret good asm from global isel: _f:
orr w8, w0, #0x1
ubfx w9, w0, #27, #1
orr w0, w9, w8, lsl #5
ret
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Seems to be something in the rotate matching. x86 picks a funnel shift instead. |
This patch fixes it diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 71618eb2bd7c..ac9670746c53 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7482,7 +7482,7 @@ SDValue DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
// TODO: Support pre-legalization funnel-shift by constant.
bool IsRotate = LHSShift.getOperand(0) == RHSShift.getOperand(0);
- if (!IsRotate && !(HasFSHL || HasFSHR)) {
+ if (!IsRotate && !(HasFSHL || HasFSHR)) {
if (TLI.isTypeLegal(VT) && LHS.hasOneUse() && RHS.hasOneUse() &&
ISD::matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum) &&
!LHSMask && !RHSMask) {
// Look for a disguised rotate by constant. We might be able to do better. The block of code behind that |
Candidate patch https://reviews.llvm.org/D124711 |
Fixed by 6affe87 |
ok this has been llvm-reduced but it's still a bit complex, sorry!
we believe that
f(0xf0000000) -> 32
and that is what we get when using global isel, and also when compiling this code for x64.on the other hand, the default arm64 backend from top of tree gives
f(0xf0000000) -> 62
we don't think there's any UB going on here, seems like a straight-up miscompile
cc @ornata @nunoplopes @ryan-berger @nbushehri @aqjune @Hatsunespica
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