or+and miscompile with global isel on arm64

[regehr]

we're seeing a miscompile of this using top of tree with global isel:

define i32 @f3(i32 %0) {
  %2 = or i32 %0, 65536
  %3 = and i32 1520220788, %2
  ret i32 %3
}

the output is:

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 12, 0
	.globl	_f3                             ; -- Begin function f3
	.p2align	2
_f3:                                    ; @f3
	.cfi_startproc
; %bb.0:
	orr	w8, w0, #0x10000
	and	w0, w0, w8
	ret
	.cfi_endproc
                                        ; -- End function
.subsections_via_symbols

here's a driver showing the issue, and that the default codegen gives the right answer:

Johns-MacBook-Pro:~ regehr$ cat foo.c
#include <stdio.h>

unsigned f3(unsigned);

int main(void) {
  printf("%u\n", f3(1));
  return 0;
}

Johns-MacBook-Pro:~ regehr$ ~/llvm-project/for-alive/bin/llc foo.ll -global-isel 
Johns-MacBook-Pro:~ regehr$ clang foo.c foo.s && ./a.out
1
Johns-MacBook-Pro:~ regehr$ ~/llvm-project/for-alive/bin/llc foo.ll
Johns-MacBook-Pro:~ regehr$ clang foo.c foo.s && ./a.out
0
Johns-MacBook-Pro:~ regehr$ 

cc @ornata @nunoplopes @ryan-berger @nbushehri @zhengyang92 @aqjune @Hatsunespica

[llvmbot]

@llvm/issue-subscribers-backend-aarch64

[jroelofs]

Sounds like: b046eb1

[jroelofs]

Yep, this needs to choose the operand more carefully:

   MatchInfo = [=, &MI](MachineIRBuilder &B) {
     Observer.changingInstr(MI);
     MI.getOperand(1).setReg(Src);
     Observer.changedInstr(MI);
   };
   return true;

b046eb1#diff-8c5f6b76b226d2087ec6bd0a7c643fba246650ab64f0b9ef7b4f4bda3fd7f70eR4034-R4039

https://llvm.godbolt.org/z/fxh463vMW

[jroelofs]

https://reviews.llvm.org/D125472