-
Notifications
You must be signed in to change notification settings - Fork 11.8k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
miscompile by arm64 backend #55342
Labels
Comments
@llvm/issue-subscribers-backend-aarch64 |
@sparker-arm looks like the TypePromotion pass. |
I think PromoteTree shouldn't sext the first operand for SafeWrap instructions. Something like this diff --git a/llvm/lib/CodeGen/TypePromotion.cpp b/llvm/lib/CodeGen/TypePromotion.cpp
index 48454a5047dd..0caf763c7ff0 100644
--- a/llvm/lib/CodeGen/TypePromotion.cpp
+++ b/llvm/lib/CodeGen/TypePromotion.cpp
@@ -484,7 +484,7 @@ void IRPromoter::PromoteTree() {
continue;
if (auto *Const = dyn_cast<ConstantInt>(Op)) {
- Constant *NewConst = SafeWrap.contains(I)
+ Constant *NewConst = (SafeWrap.contains(I) && i == 1)
? ConstantExpr::getSExt(Const, ExtTy)
: ConstantExpr::getZExt(Const, ExtTy);
I->setOperand(i, NewConst); |
That sounds good to me, I don't think the pass handles non-canonical IR very well at the moment. I can put together a patch, if you don't have one already. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
this function should return 1:
however, the arm64 backend (in LLVM 14 and also top of tree) has it returning 0:
cc @ornata @nunoplopes @ryan-berger @nbushehri @zhengyang92 @aqjune @Hatsunespica
The text was updated successfully, but these errors were encountered: