-
Notifications
You must be signed in to change notification settings - Fork 12.2k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
miscompile from arm64 backend with (icmp ult (sub -6, -8) 3) #55490
Comments
@llvm/issue-subscribers-backend-aarch64 |
Is this the same as #55342? |
well it sure looks related but no, this one is still wrong using an LLVM that has your patch to that one |
if y'all prefer, we can sit on these ones that are highly non-canonical, but I feel like it's hard to prove that there aren't canonical triggers for this issue |
Looks like a bug in the same code as 55342. When the safewrap instruction is a subtract, instead of sign extending the constant, we need to negate it, sign extend it, then negate it again, I think. I think the sign extend by itself is only correct for add. |
Candidate patch https://reviews.llvm.org/D125653 |
ok here's a trigger for this issue that, while not being canonical, at least doesn't contain a trivial fold opportunity define i1 @f(i4 %0) {
%2 = sub i4 %0, 6
%3 = icmp ult i4 -5, %2
ret i1 %3
} |
Fixed by 8d3894f |
here's a function that needs to return true:
however, since the 14 release the arm64 backend got a regression causing it to return false:
cc @ornata @nunoplopes @ryan-berger @nbushehri @zhengyang92 @aqjune @Hatsunespica
The text was updated successfully, but these errors were encountered: