[AMDGPU][Disassembler] `getInlineImmVal16` can't tell BF16 and FP16 apart when it comes to inline literal

[shiltian]

Based on the spec, 242 is the encoding for inline literal 1.0. However, when getInlineImmVal16 sees 242, it doesn't know whether the operand is BF16 or FP16. Currently it returns 1.0 in FP16 format. As a consequence, the encoded instruction and operand are not correct. See llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt for the test case.

[llvmbot]

@llvm/issue-subscribers-backend-amdgpu

Author: Shilei Tian (shiltian)

Based on the spec, `242` is the encoding for inline literal `1.0`. However, when `getInlineImmVal16` sees `242`, it doesn't know whether the operand is BF16 or FP16. Currently it returns `1.0` in FP16 format. As a consequence, the encoded instruction and operand are not correct.