diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp index 0024e84c5ede8..cbc8579e85a34 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp @@ -147,12 +147,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) .lower(); getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR}) - .legalFor({{s32, s32}, {sXLen, sXLen}}) + .legalFor({{sXLen, sXLen}}) + .customFor(ST.is64Bit(), {{s32, s32}}) .widenScalarToNextPow2(0) - .clampScalar(1, s32, sXLen) - .clampScalar(0, s32, sXLen) - .minScalarSameAs(1, 0) - .maxScalarSameAs(1, 0); + .clampScalar(1, sXLen, sXLen) + .clampScalar(0, sXLen, sXLen); auto &ExtActions = getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}) @@ -1166,6 +1165,12 @@ static unsigned getRISCVWOpcode(unsigned Opcode) { switch (Opcode) { default: llvm_unreachable("Unexpected opcode"); + case TargetOpcode::G_ASHR: + return RISCV::G_SRAW; + case TargetOpcode::G_LSHR: + return RISCV::G_SRLW; + case TargetOpcode::G_SHL: + return RISCV::G_SLLW; case TargetOpcode::G_SDIV: return RISCV::G_DIVW; case TargetOpcode::G_UDIV: @@ -1223,6 +1228,34 @@ bool RISCVLegalizerInfo::legalizeCustom( return Helper.lower(MI, 0, /* Unused hint type */ LLT()) == LegalizerHelper::Legalized; } + case TargetOpcode::G_ASHR: + case TargetOpcode::G_LSHR: + case TargetOpcode::G_SHL: { + if (getIConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI)) { + // We don't need a custom node for shift by constant. Just widen the + // source and the shift amount. + unsigned ExtOpc = TargetOpcode::G_ANYEXT; + if (MI.getOpcode() == TargetOpcode::G_ASHR) + ExtOpc = TargetOpcode::G_SEXT; + else if (MI.getOpcode() == TargetOpcode::G_LSHR) + ExtOpc = TargetOpcode::G_ZEXT; + + Helper.Observer.changingInstr(MI); + Helper.widenScalarSrc(MI, sXLen, 1, ExtOpc); + Helper.widenScalarSrc(MI, sXLen, 2, TargetOpcode::G_ZEXT); + Helper.widenScalarDst(MI, sXLen); + Helper.Observer.changedInstr(MI); + return true; + } + + Helper.Observer.changingInstr(MI); + Helper.widenScalarSrc(MI, sXLen, 1, TargetOpcode::G_ANYEXT); + Helper.widenScalarSrc(MI, sXLen, 2, TargetOpcode::G_ANYEXT); + Helper.widenScalarDst(MI, sXLen); + MI.setDesc(MIRBuilder.getTII().get(getRISCVWOpcode(MI.getOpcode()))); + Helper.Observer.changedInstr(MI); + return true; + } case TargetOpcode::G_SDIV: case TargetOpcode::G_UDIV: case TargetOpcode::G_UREM: diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td index 3f5bbabf859e5..87ae01156f084 100644 --- a/llvm/lib/Target/RISCV/RISCVGISel.td +++ b/llvm/lib/Target/RISCV/RISCVGISel.td @@ -169,6 +169,12 @@ def : LdPat; def : StPat; } +let Predicates = [IsRV64] in { +// FIXME: Temporary until i32->i64 zext is no longer legal. +def : Pat <(srl (zext GPR:$rs1), uimm5:$shamt), + (SRLIW GPR:$rs1, uimm5:$shamt)>; +} + //===----------------------------------------------------------------------===// // RV64 i32 patterns not used by SelectionDAG //===----------------------------------------------------------------------===// @@ -195,17 +201,6 @@ def : Pat<(anyext GPR:$src), (COPY GPR:$src)>; def : Pat<(sext GPR:$src), (ADDIW GPR:$src, 0)>; def : Pat<(trunc GPR:$src), (COPY GPR:$src)>; -def : PatGprGpr; -def : PatGprGpr; -def : PatGprGpr; - -def : Pat<(i32 (shl GPR:$rs1, uimm5i32:$imm)), - (SLLIW GPR:$rs1, (i64 (as_i64imm $imm)))>; -def : Pat<(i32 (srl GPR:$rs1, uimm5i32:$imm)), - (SRLIW GPR:$rs1, (i64 (as_i64imm $imm)))>; -def : Pat<(i32 (sra GPR:$rs1, uimm5i32:$imm)), - (SRAIW GPR:$rs1, (i64 (as_i64imm $imm)))>; - // Use sext if the sign bit of the input is 0. def : Pat<(zext_is_sext GPR:$src), (ADDIW GPR:$src, 0)>; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrGISel.td b/llvm/lib/Target/RISCV/RISCVInstrGISel.td index bf2f8663cfa15..ac5f4f0ca6cc5 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrGISel.td +++ b/llvm/lib/Target/RISCV/RISCVInstrGISel.td @@ -17,6 +17,30 @@ class RISCVGenericInstruction : GenericInstruction { let Namespace = "RISCV"; } +// Pseudo equivalent to a RISCVISD::SRAW. +def G_SRAW : RISCVGenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1, type0:$src2); + let hasSideEffects = false; +} +def : GINodeEquiv; + +// Pseudo equivalent to a RISCVISD::SRLW. +def G_SRLW : RISCVGenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1, type0:$src2); + let hasSideEffects = false; +} +def : GINodeEquiv; + +// Pseudo equivalent to a RISCVISD::SLLW. +def G_SLLW : RISCVGenericInstruction { + let OutOperandList = (outs type0:$dst); + let InOperandList = (ins type0:$src1, type0:$src2); + let hasSideEffects = false; +} +def : GINodeEquiv; + // Pseudo equivalent to a RISCVISD::DIVW. def G_DIVW : RISCVGenericInstruction { let OutOperandList = (outs type0:$dst); diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll index e6b009287ae76..38cdd6a2cdcdc 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll @@ -171,7 +171,7 @@ define i32 @slli_i32(i32 %a) { ; ; RV64IM-LABEL: slli_i32: ; RV64IM: # %bb.0: # %entry -; RV64IM-NEXT: slliw a0, a0, 11 +; RV64IM-NEXT: slli a0, a0, 11 ; RV64IM-NEXT: ret entry: %0 = shl i32 %a, 11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll index 72d8a6173152f..10bbc82b3d40b 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/bitmanip.ll @@ -2,7 +2,6 @@ ; RUN: llc -mtriple=riscv32 -global-isel -global-isel-abort=1 < %s 2>&1 | FileCheck %s --check-prefixes=RV32 ; RUN: llc -mtriple=riscv64 -global-isel -global-isel-abort=1 < %s 2>&1 | FileCheck %s --check-prefixes=RV64 -; FIXME: andi a0, a0, 1 is unneeded define i2 @bitreverse_i2(i2 %x) { ; RV32-LABEL: bitreverse_i2: ; RV32: # %bb.0: @@ -18,15 +17,13 @@ define i2 @bitreverse_i2(i2 %x) { ; RV64-NEXT: slli a1, a0, 1 ; RV64-NEXT: andi a1, a1, 2 ; RV64-NEXT: andi a0, a0, 3 -; RV64-NEXT: srliw a0, a0, 1 -; RV64-NEXT: andi a0, a0, 1 +; RV64-NEXT: srli a0, a0, 1 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: ret %rev = call i2 @llvm.bitreverse.i2(i2 %x) ret i2 %rev } -; FIXME: andi a0, a0, 1 is unneeded define i3 @bitreverse_i3(i3 %x) { ; RV32-LABEL: bitreverse_i3: ; RV32: # %bb.0: @@ -46,15 +43,13 @@ define i3 @bitreverse_i3(i3 %x) { ; RV64-NEXT: andi a0, a0, 7 ; RV64-NEXT: andi a2, a0, 2 ; RV64-NEXT: or a1, a1, a2 -; RV64-NEXT: srliw a0, a0, 2 -; RV64-NEXT: andi a0, a0, 1 +; RV64-NEXT: srli a0, a0, 2 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: ret %rev = call i3 @llvm.bitreverse.i3(i3 %x) ret i3 %rev } -; FIXME: andi a0, a0, 1 is unneeded define i4 @bitreverse_i4(i4 %x) { ; RV32-LABEL: bitreverse_i4: ; RV32: # %bb.0: @@ -79,18 +74,16 @@ define i4 @bitreverse_i4(i4 %x) { ; RV64-NEXT: andi a2, a2, 4 ; RV64-NEXT: or a1, a1, a2 ; RV64-NEXT: andi a0, a0, 15 -; RV64-NEXT: srliw a2, a0, 1 +; RV64-NEXT: srli a2, a0, 1 ; RV64-NEXT: andi a2, a2, 2 ; RV64-NEXT: or a1, a1, a2 -; RV64-NEXT: srliw a0, a0, 3 -; RV64-NEXT: andi a0, a0, 1 +; RV64-NEXT: srli a0, a0, 3 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: ret %rev = call i4 @llvm.bitreverse.i4(i4 %x) ret i4 %rev } -; FIXME: andi a0, a0, 1 is unneeded define i7 @bitreverse_i7(i7 %x) { ; RV32-LABEL: bitreverse_i7: ; RV32: # %bb.0: @@ -122,20 +115,20 @@ define i7 @bitreverse_i7(i7 %x) { ; RV64-NEXT: slli a2, a0, 4 ; RV64-NEXT: andi a2, a2, 32 ; RV64-NEXT: or a1, a1, a2 -; RV64-NEXT: slli a2, a0, 2 -; RV64-NEXT: andi a2, a2, 16 +; RV64-NEXT: li a2, 2 +; RV64-NEXT: slli a3, a0, 2 +; RV64-NEXT: andi a3, a3, 16 ; RV64-NEXT: andi a0, a0, 127 -; RV64-NEXT: andi a3, a0, 8 -; RV64-NEXT: or a2, a2, a3 +; RV64-NEXT: andi a4, a0, 8 +; RV64-NEXT: or a3, a3, a4 +; RV64-NEXT: or a1, a1, a3 +; RV64-NEXT: srli a3, a0, 2 +; RV64-NEXT: andi a3, a3, 4 +; RV64-NEXT: srli a4, a0, 4 +; RV64-NEXT: and a2, a4, a2 +; RV64-NEXT: or a2, a3, a2 ; RV64-NEXT: or a1, a1, a2 -; RV64-NEXT: srliw a2, a0, 2 -; RV64-NEXT: andi a2, a2, 4 -; RV64-NEXT: srliw a3, a0, 4 -; RV64-NEXT: andi a3, a3, 2 -; RV64-NEXT: or a2, a2, a3 -; RV64-NEXT: or a1, a1, a2 -; RV64-NEXT: srliw a0, a0, 6 -; RV64-NEXT: andi a0, a0, 1 +; RV64-NEXT: srli a0, a0, 6 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: ret %rev = call i7 @llvm.bitreverse.i7(i7 %x) @@ -179,39 +172,39 @@ define i24 @bitreverse_i24(i24 %x) { ; ; RV64-LABEL: bitreverse_i24: ; RV64: # %bb.0: -; RV64-NEXT: slli a1, a0, 16 -; RV64-NEXT: lui a2, 4096 -; RV64-NEXT: addi a2, a2, -1 -; RV64-NEXT: and a0, a0, a2 -; RV64-NEXT: srliw a0, a0, 16 -; RV64-NEXT: or a0, a0, a1 -; RV64-NEXT: lui a1, 65521 -; RV64-NEXT: addi a1, a1, -241 -; RV64-NEXT: slli a1, a1, 4 -; RV64-NEXT: and a3, a1, a2 +; RV64-NEXT: lui a1, 4096 +; RV64-NEXT: addiw a1, a1, -1 +; RV64-NEXT: slli a2, a0, 16 +; RV64-NEXT: and a0, a0, a1 +; RV64-NEXT: srli a0, a0, 16 +; RV64-NEXT: or a0, a0, a2 +; RV64-NEXT: lui a2, 65521 +; RV64-NEXT: addiw a2, a2, -241 +; RV64-NEXT: slli a2, a2, 4 +; RV64-NEXT: and a3, a2, a1 ; RV64-NEXT: and a3, a0, a3 -; RV64-NEXT: srliw a3, a3, 4 +; RV64-NEXT: srli a3, a3, 4 ; RV64-NEXT: slli a0, a0, 4 -; RV64-NEXT: and a0, a0, a1 +; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: or a0, a3, a0 -; RV64-NEXT: lui a1, 261939 -; RV64-NEXT: addi a1, a1, 819 -; RV64-NEXT: slli a1, a1, 2 -; RV64-NEXT: and a3, a1, a2 +; RV64-NEXT: lui a2, 261939 +; RV64-NEXT: addiw a2, a2, 819 +; RV64-NEXT: slli a2, a2, 2 +; RV64-NEXT: and a3, a2, a1 ; RV64-NEXT: and a3, a0, a3 -; RV64-NEXT: srliw a3, a3, 2 +; RV64-NEXT: srli a3, a3, 2 ; RV64-NEXT: slli a0, a0, 2 -; RV64-NEXT: and a0, a0, a1 +; RV64-NEXT: and a0, a0, a2 ; RV64-NEXT: or a0, a3, a0 -; RV64-NEXT: lui a1, 523605 -; RV64-NEXT: addiw a1, a1, 1365 -; RV64-NEXT: slli a1, a1, 1 -; RV64-NEXT: and a2, a1, a2 -; RV64-NEXT: and a2, a0, a2 -; RV64-NEXT: srliw a2, a2, 1 -; RV64-NEXT: slliw a0, a0, 1 -; RV64-NEXT: and a0, a0, a1 -; RV64-NEXT: or a0, a2, a0 +; RV64-NEXT: lui a2, 523605 +; RV64-NEXT: addiw a2, a2, 1365 +; RV64-NEXT: slli a2, a2, 1 +; RV64-NEXT: and a1, a2, a1 +; RV64-NEXT: and a1, a0, a1 +; RV64-NEXT: srli a1, a1, 1 +; RV64-NEXT: slli a0, a0, 1 +; RV64-NEXT: and a0, a0, a2 +; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: ret %rev = call i24 @llvm.bitreverse.i24(i24 %x) ret i24 %rev diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll b/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll index 716af2e6c6a52..93d14c288db2e 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/combine.ll @@ -42,10 +42,18 @@ define i32 @mul_to_shift(i32 %x) { ; RV32-NEXT: slli a0, a0, 2 ; RV32-NEXT: ret ; -; RV64-LABEL: mul_to_shift: -; RV64: # %bb.0: -; RV64-NEXT: slliw a0, a0, 2 -; RV64-NEXT: ret +; RV64-O0-LABEL: mul_to_shift: +; RV64-O0: # %bb.0: +; RV64-O0-NEXT: li a1, 2 +; RV64-O0-NEXT: sll a0, a0, a1 +; RV64-O0-NEXT: ret +; +; RV64-OPT-LABEL: mul_to_shift: +; RV64-OPT: # %bb.0: +; RV64-OPT-NEXT: slli a0, a0, 2 +; RV64-OPT-NEXT: ret %a = mul i32 %x, 4 ret i32 %a } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; RV64: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll index 92b4dc9cd2adc..05989c310541b 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll @@ -31,8 +31,8 @@ define i8 @abs8(i8 %x) { ; ; RV64I-LABEL: abs8: ; RV64I: # %bb.0: -; RV64I-NEXT: slli a1, a0, 24 -; RV64I-NEXT: sraiw a1, a1, 31 +; RV64I-NEXT: slli a1, a0, 56 +; RV64I-NEXT: srai a1, a1, 63 ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret @@ -65,8 +65,8 @@ define i16 @abs16(i16 %x) { ; ; RV64I-LABEL: abs16: ; RV64I: # %bb.0: -; RV64I-NEXT: slli a1, a0, 16 -; RV64I-NEXT: sraiw a1, a1, 31 +; RV64I-NEXT: slli a1, a0, 48 +; RV64I-NEXT: srai a1, a1, 63 ; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1 ; RV64I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir index 8be7ae4b3d405..90d92b615c876 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir @@ -20,12 +20,9 @@ body: | ; RV64I-NEXT: $x10 = COPY [[SLLW]] ; RV64I-NEXT: PseudoRET implicit $x10 %0:gprb(s64) = COPY $x10 - %1:gprb(s32) = G_TRUNC %0(s64) - %2:gprb(s64) = COPY $x11 - %3:gprb(s32) = G_TRUNC %2(s64) - %4:gprb(s32) = G_SHL %1, %3(s32) - %5:gprb(s64) = G_ANYEXT %4(s32) - $x10 = COPY %5(s64) + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SLLW %0, %1 + $x10 = COPY %2(s64) PseudoRET implicit $x10 ... @@ -42,15 +39,13 @@ body: | ; RV64I: liveins: $x10 ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 - ; RV64I-NEXT: [[SLLIW:%[0-9]+]]:gpr = SLLIW [[COPY]], 31 - ; RV64I-NEXT: $x10 = COPY [[SLLIW]] + ; RV64I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31 + ; RV64I-NEXT: $x10 = COPY [[SLLI]] ; RV64I-NEXT: PseudoRET implicit $x10 %0:gprb(s64) = COPY $x10 - %1:gprb(s32) = G_TRUNC %0(s64) - %2:gprb(s32) = G_CONSTANT i32 31 - %3:gprb(s32) = G_SHL %1, %2 - %4:gprb(s64) = G_ANYEXT %3(s32) - $x10 = COPY %4(s64) + %1:gprb(s64) = G_CONSTANT i64 31 + %2:gprb(s64) = G_SHL %0, %1 + $x10 = COPY %2(s64) PseudoRET implicit $x10 ... @@ -72,12 +67,9 @@ body: | ; RV64I-NEXT: $x10 = COPY [[SRAW]] ; RV64I-NEXT: PseudoRET implicit $x10 %0:gprb(s64) = COPY $x10 - %1:gprb(s32) = G_TRUNC %0(s64) - %2:gprb(s64) = COPY $x11 - %3:gprb(s32) = G_TRUNC %2(s64) - %4:gprb(s32) = G_ASHR %1, %3(s32) - %5:gprb(s64) = G_ANYEXT %4(s32) - $x10 = COPY %5(s64) + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SRAW %0, %1 + $x10 = COPY %2(s64) PseudoRET implicit $x10 ... @@ -98,11 +90,10 @@ body: | ; RV64I-NEXT: $x10 = COPY [[SRAIW]] ; RV64I-NEXT: PseudoRET implicit $x10 %0:gprb(s64) = COPY $x10 - %1:gprb(s32) = G_TRUNC %0(s64) - %2:gprb(s32) = G_CONSTANT i32 31 - %3:gprb(s32) = G_ASHR %1, %2 - %4:gprb(s64) = G_ANYEXT %3(s32) - $x10 = COPY %4(s64) + %1:gprb(s64) = G_CONSTANT i64 31 + %2:gprb(s64) = G_SEXT_INREG %0, 32 + %3:gprb(s64) = G_ASHR %2, %1(s64) + $x10 = COPY %3(s64) PseudoRET implicit $x10 ... @@ -124,12 +115,9 @@ body: | ; RV64I-NEXT: $x10 = COPY [[SRLW]] ; RV64I-NEXT: PseudoRET implicit $x10 %0:gprb(s64) = COPY $x10 - %1:gprb(s32) = G_TRUNC %0(s64) - %2:gprb(s64) = COPY $x11 - %3:gprb(s32) = G_TRUNC %2(s64) - %4:gprb(s32) = G_LSHR %1, %3(s32) - %5:gprb(s64) = G_ANYEXT %4(s32) - $x10 = COPY %5(s64) + %1:gprb(s64) = COPY $x11 + %2:gprb(s64) = G_SRLW %0, %1 + $x10 = COPY %2(s64) PseudoRET implicit $x10 ... @@ -150,10 +138,10 @@ body: | ; RV64I-NEXT: $x10 = COPY [[SRLIW]] ; RV64I-NEXT: PseudoRET implicit $x10 %0:gprb(s64) = COPY $x10 - %1:gprb(s32) = G_TRUNC %0(s64) - %2:gprb(s32) = G_CONSTANT i32 31 - %3:gprb(s32) = G_LSHR %1, %2 - %4:gprb(s64) = G_ANYEXT %3(s32) + %1:gprb(s64) = G_CONSTANT i64 31 + %2:gprb(s64) = G_CONSTANT i64 4294967295 + %3:gprb(s64) = G_AND %0, %2 + %4:gprb(s64) = G_LSHR %3, %1(s64) $x10 = COPY %4(s64) PseudoRET implicit $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir index 5068c60e971b9..f4a88377d4a31 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir @@ -12,17 +12,17 @@ body: | ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64) - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C1]](s32) - ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) - ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32) - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_ZEXT]], [[ANYEXT]] - ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ANYEXT]] - ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C2]] - ; RV64I-NEXT: $x10 = COPY [[AND]](s64) + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C2]](s64) + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C2]](s64) + ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64) + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_ZEXT]], [[ASHR1]] + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C1]] + ; RV64I-NEXT: $x10 = COPY [[AND1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: abs_i8 @@ -52,14 +52,15 @@ body: | ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64) - ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR]](s32) - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ANYEXT]] - ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ANYEXT]] - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 - ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[C1]](s64) - ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64) + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[AND]](s64) + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]] + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[C2]](s64) + ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C2]](s64) ; RV64I-NEXT: $x10 = COPY [[ASHR1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; @@ -87,12 +88,11 @@ body: | ; RV64I-LABEL: name: abs_i32 ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32 - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_SEXT]](s64) ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 - ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR]](s32) - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ANYEXT]] - ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ANYEXT]] + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) + ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[ZEXT]](s64) + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]] + ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]] ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32 ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir index 50ff500af4874..0d097a5128c18 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ashr-rv64.mir @@ -8,17 +8,13 @@ body: | ; CHECK-LABEL: name: ashr_i8 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32) - ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) - ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[TRUNC]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 @@ -37,17 +33,13 @@ body: | ; CHECK-LABEL: name: ashr_i15 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 17 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32) - ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) - ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[TRUNC]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 49 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 @@ -66,17 +58,13 @@ body: | ; CHECK-LABEL: name: ashr_i16 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C1]](s32) - ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32) - ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[TRUNC]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR1]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48 + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64) + ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[ASHR1]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 @@ -95,11 +83,8 @@ body: | ; CHECK-LABEL: name: ashr_i32 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) - ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[TRUNC1]](s32) - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: [[SRAW:%[0-9]+]]:_(s64) = G_SRAW [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SRAW]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir index 18d1b244300b0..d7063dfd9a0f0 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bitreverse-rv64.mir @@ -12,55 +12,46 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT1]], [[ANYEXT2]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16 - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[ANYEXT3]] - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C2]](s32) - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64) - ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC3]], [[C2]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) - ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT3]] - ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[ANYEXT5]], [[AND3]] + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR]], [[ANYEXT1]] + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[AND2]], [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND3]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[AND3]](s64) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[ANYEXT1]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[AND5]] ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -52 - ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[ANYEXT6]] - ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[AND5]](s64) - ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC4]], [[C4]](s32) - ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[OR1]](s64) - ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC5]], [[C4]](s32) - ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL2]](s32) - ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[ANYEXT6]] - ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[ANYEXT8]], [[AND6]] + ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[ANYEXT3]] + ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[C1]] + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND6]], [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[AND7]](s64) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[AND7]](s64) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SHL2]], [[ANYEXT3]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[AND9]] ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 -86 - ; CHECK-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT9]] - ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND7]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[AND8]](s64) - ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC6]], [[C6]](s32) - ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64) - ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[TRUNC7]], [[C6]](s32) - ; CHECK-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL3]](s32) - ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ANYEXT10]], [[ANYEXT9]] - ; CHECK-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[ANYEXT11]], [[AND9]] + ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT5]] + ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ANYEXT6]], [[C1]] + ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[AND10]], [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND12]], [[AND11]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[AND11]](s64) + ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s64) = G_AND [[SHL3]], [[ANYEXT5]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[AND13]] ; CHECK-NEXT: $x10 = COPY [[OR3]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 @@ -82,55 +73,46 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT1]], [[ANYEXT2]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -3856 - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[ANYEXT3]] - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C2]](s32) - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64) - ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC3]], [[C2]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) - ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT3]] - ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[ANYEXT5]], [[AND3]] + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR]], [[ANYEXT1]] + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[AND2]], [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND3]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[AND3]](s64) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[ANYEXT1]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[AND5]] ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -13108 - ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[ANYEXT6]] - ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[AND5]](s64) - ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC4]], [[C4]](s32) - ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[OR1]](s64) - ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC5]], [[C4]](s32) - ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL2]](s32) - ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[ANYEXT6]] - ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[ANYEXT8]], [[AND6]] + ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[ANYEXT3]] + ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[C1]] + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND6]], [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[AND7]](s64) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[AND7]](s64) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SHL2]], [[ANYEXT3]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[AND9]] ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 -21846 - ; CHECK-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT9]] - ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND7]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[AND8]](s64) - ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC6]], [[C6]](s32) - ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64) - ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[TRUNC7]], [[C6]](s32) - ; CHECK-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL3]](s32) - ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ANYEXT10]], [[ANYEXT9]] - ; CHECK-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[ANYEXT11]], [[AND9]] + ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT5]] + ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ANYEXT6]], [[C1]] + ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[AND10]], [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND12]], [[AND11]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[AND11]](s64) + ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s64) = G_AND [[SHL3]], [[ANYEXT5]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[AND13]] ; CHECK-NEXT: $x10 = COPY [[OR3]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 @@ -151,61 +133,53 @@ body: | ; CHECK: liveins: $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT]], [[ANYEXT1]] - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280 - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) - ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[ANYEXT3]] - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C2]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT2]] - ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND1]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64) - ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136 - ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT5]] - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C3]](s32) - ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC2]], [[C3]](s32) - ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL2]](s32) - ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT6]], [[ANYEXT5]] - ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[ANYEXT7]], [[AND3]] - ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[OR3]](s64) - ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460 - ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[ANYEXT8]] - ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[AND4]](s64) - ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC5]], [[C5]](s32) - ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[TRUNC4]], [[C5]](s32) - ; CHECK-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL3]](s32) - ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ANYEXT9]], [[ANYEXT8]] - ; CHECK-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[ANYEXT10]], [[AND5]] - ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[OR4]](s64) - ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766 - ; CHECK-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) - ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[ANYEXT11]] - ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[AND6]](s64) - ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC7]], [[C7]](s32) - ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[TRUNC6]], [[C7]](s32) - ; CHECK-NEXT: [[ANYEXT12:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL4]](s32) - ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ANYEXT12]], [[ANYEXT11]] - ; CHECK-NEXT: [[ANYEXT13:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR4]](s32) - ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[ANYEXT13]], [[AND7]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[ZEXT]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[ZEXT]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280 + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] + ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C3]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[AND1]], [[ZEXT1]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[ZEXT1]](s64) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND2]] + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -252645136 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT1]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C1]] + ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[C4]](s32) + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[ZEXT2]](s64) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[ZEXT2]](s64) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SHL2]], [[ANYEXT1]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[AND5]] + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 -858993460 + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[ANYEXT2]] + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[AND6]], [[C1]] + ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[C6]](s32) + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[ZEXT3]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR3]], [[ZEXT3]](s64) + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[SHL3]], [[ANYEXT2]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[AND8]] + ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1431655766 + ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[ANYEXT3]] + ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[AND9]], [[C1]] + ; CHECK-NEXT: [[ZEXT4:%[0-9]+]]:_(s64) = G_ZEXT [[C8]](s32) + ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[ZEXT4]](s64) + ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL [[OR4]], [[ZEXT4]](s64) + ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[SHL4]], [[ANYEXT3]] + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[LSHR4]], [[AND11]] ; CHECK-NEXT: $x10 = COPY [[OR5]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 @@ -297,21 +271,18 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]] - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[ANYEXT4]] - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[ANYEXT1]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[COPY1]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[AND3]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 @@ -333,28 +304,25 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]] - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[ANYEXT1]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[ANYEXT4]] - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND2]] - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64) + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[AND4]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND]](s64) ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) - ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT5]], [[ANYEXT6]] - ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[AND3]] + ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT3]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[AND5]] ; CHECK-NEXT: $x10 = COPY [[OR1]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 @@ -376,34 +344,31 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]] - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C2]](s32) - ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[ANYEXT3]] - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]] - ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT4]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[ANYEXT1]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND2]](s64) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[ANYEXT3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[AND3]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND2]](s64) ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT5]], [[ANYEXT6]] - ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[AND3]] - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32) - ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[ANYEXT8]] - ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND4]] + ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT4]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[AND5]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ANYEXT2]](s64) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[COPY1]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND6]] ; CHECK-NEXT: $x10 = COPY [[OR2]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 @@ -425,53 +390,50 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]] - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C2]](s32) - ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[ANYEXT3]] - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[AND1]] - ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C4]](s32) - ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL2]](s32) - ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT5]] - ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[AND2]] - ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 127 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SHL]], [[ANYEXT1]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND2]](s64) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[ANYEXT3]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[AND3]] + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[C1]] + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND4]](s64) + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SHL2]], [[ANYEXT5]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[AND5]] + ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT6]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C6]](s32) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ANYEXT6]], [[C1]] + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[AND6]](s64) ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) - ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[ANYEXT8]] - ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND4]] - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C4]](s32) - ; CHECK-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; CHECK-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ANYEXT9]], [[ANYEXT10]] - ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[AND5]] - ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) - ; CHECK-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; CHECK-NEXT: [[ANYEXT12:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) - ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ANYEXT11]], [[ANYEXT12]] - ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[AND6]] - ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32) + ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT7]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND8]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[AND4]](s64) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT2]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[AND9]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[AND2]](s64) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ANYEXT4]](s64) + ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[LSHR2]], [[COPY1]] + ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[AND10]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[AND]](s64) ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[ANYEXT13:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; CHECK-NEXT: [[ANYEXT14:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) - ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ANYEXT13]], [[ANYEXT14]] - ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[AND7]] + ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) + ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[LSHR3]], [[ANYEXT8]] + ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR4]], [[AND11]] ; CHECK-NEXT: $x10 = COPY [[OR5]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 @@ -493,55 +455,46 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT1]], [[ANYEXT2]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16777215 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -986896 - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[ANYEXT3]] - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C2]](s32) - ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC2]], [[C2]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) - ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT3]] - ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[ANYEXT5]], [[AND3]] + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR]], [[ANYEXT1]] + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[AND2]], [[C1]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND3]](s64) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[AND3]](s64) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SHL1]], [[ANYEXT1]] + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[AND5]] ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -3355444 - ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[OR1]](s64) - ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[ANYEXT6]] - ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[AND5]](s64) - ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC5]], [[C4]](s32) - ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC4]], [[C4]](s32) - ; CHECK-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL2]](s32) - ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[ANYEXT6]] - ; CHECK-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[ANYEXT8]], [[AND6]] + ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[ANYEXT3]] + ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[C1]] + ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND6]], [[C1]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[AND7]](s64) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[AND7]](s64) + ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SHL2]], [[ANYEXT3]] + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[LSHR2]], [[AND9]] ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 -5592406 - ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64) - ; CHECK-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT9]] - ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND7]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[AND8]](s64) - ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC7]], [[C6]](s32) - ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[TRUNC6]], [[C6]](s32) - ; CHECK-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL3]](s32) - ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ANYEXT10]], [[ANYEXT9]] - ; CHECK-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[ANYEXT11]], [[AND9]] + ; CHECK-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT5]] + ; CHECK-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ANYEXT6]], [[C1]] + ; CHECK-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[AND10]], [[C1]] + ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND12]], [[AND11]](s64) + ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[AND11]](s64) + ; CHECK-NEXT: [[AND13:%[0-9]+]]:_(s64) = G_AND [[SHL3]], [[ANYEXT5]] + ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[AND13]] ; CHECK-NEXT: $x10 = COPY [[OR3]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir index a2a23477e0936..a732f93cca680 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir @@ -17,15 +17,14 @@ body: | ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 16 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64) - ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT]], [[ANYEXT1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] - ; RV64I-NEXT: $x10 = COPY [[AND]](s64) + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[AND]](s64) + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ASSERT_ZEXT]], [[AND]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: $x10 = COPY [[AND1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB_OR_RV64ZBKB-LABEL: name: bswap_i16 @@ -56,24 +55,20 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 32 - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[ASSERT_ZEXT]](s64) ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT]], [[ANYEXT1]] + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) + ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[ZEXT]](s64) + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[ASSERT_ZEXT]], [[ZEXT]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65280 ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ASSERT_ZEXT]], [[ANYEXT2]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[C2]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) - ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[ANYEXT3]] - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C2]](s32) - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT2]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ASSERT_ZEXT]], [[ANYEXT]] + ; RV64I-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C2]](s32) + ; RV64I-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[ZEXT1]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[SHL1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[ASSERT_ZEXT]], [[ZEXT1]](s64) + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT]] ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[AND1]] ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C3]] diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir index bda94ba1b9856..f3f72b7b5668b 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir @@ -15,59 +15,53 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[ANYEXT1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[ANYEXT2]] + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C1]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C3]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[ANYEXT3]] - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C]](s32) + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[AND4]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[AND]](s64) ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT5]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR2]], [[AND4]] - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[AND5]](s64) - ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC4]], [[C2]](s32) + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[LSHR3]], [[ANYEXT3]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR2]], [[AND7]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[AND2]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR4]](s32) - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ANYEXT6]], [[ANYEXT7]] - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT7]] - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[AND7]] - ; RV64I-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) - ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC5]], [[C3]](s32) - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR5]](s32) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT8]], [[ADD]] + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[LSHR4]], [[ANYEXT4]] + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT4]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND9]], [[AND10]] + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C1]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[AND4]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR5]], [[ADD]] ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 - ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT9]] + ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT5]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64I-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND8]], [[ANYEXT10]] - ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[AND9]](s64) - ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC6]], [[C7]](s32) + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND12]], [[COPY1]] + ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND13:%[0-9]+]]:_(s64) = G_AND [[ANYEXT6]], [[C1]] + ; RV64I-NEXT: [[AND14:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND14]], [[AND13]](s64) ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) - ; RV64I-NEXT: [[ANYEXT12:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR6]](s32) - ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT11]], [[ANYEXT12]] + ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT7]], [[LSHR6]] ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; @@ -102,65 +96,57 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[ANYEXT1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[ANYEXT2]] + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C1]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C3]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[ANYEXT3]] + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[AND4]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C4]](s32) - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[ANYEXT4]] - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[AND4]](s64) - ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC4]], [[C]](s32) + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[C1]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[AND6]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C1]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[AND]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR4]](s32) - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ANYEXT5]], [[ANYEXT6]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR3]], [[AND5]] - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[AND6]](s64) - ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC5]], [[C2]](s32) + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[LSHR4]], [[ANYEXT4]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR3]], [[AND9]] + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[AND2]](s64) ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR5]](s32) - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[ANYEXT8]] - ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT8]] - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND7]], [[AND8]] - ; RV64I-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) - ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC6]], [[C3]](s32) - ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR6]](s32) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT9]], [[ADD]] + ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[ANYEXT5]] + ; RV64I-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT5]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND11]], [[AND12]] + ; RV64I-NEXT: [[AND13:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C1]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND13]], [[AND4]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR6]], [[ADD]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 - ; RV64I-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT10]] + ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND14:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT6]] ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257 - ; RV64I-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND9]], [[ANYEXT11]] - ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[AND10]](s64) - ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC7]], [[C4]](s32) + ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND14]], [[ANYEXT7]] + ; RV64I-NEXT: [[AND15:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND15]], [[AND6]](s64) ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; RV64I-NEXT: [[ANYEXT12:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) - ; RV64I-NEXT: [[ANYEXT13:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR7]](s32) - ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT12]], [[ANYEXT13]] + ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT8]], [[LSHR7]] ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; @@ -194,63 +180,61 @@ body: | ; RV64I: liveins: $x10 ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64) - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C1]](s32) - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[OR1]](s64) - ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C2]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[ANYEXT2]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64) - ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C3]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[ANYEXT3]] - ; RV64I-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[OR3]](s64) - ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC4]], [[C4]](s32) - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR4]](s32) - ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[ANYEXT4]] - ; RV64I-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[OR4]](s64) - ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC5]], [[C]](s32) - ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR5]](s32) - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT5]], [[ANYEXT6]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND]] - ; RV64I-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) - ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC6]], [[C1]](s32) - ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR6]](s32) - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[ANYEXT8]] - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT8]] - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND1]], [[AND2]] - ; RV64I-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) - ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC7]], [[C2]](s32) - ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR7]](s32) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT9]], [[ADD]] - ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 - ; RV64I-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT10]] - ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 - ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; RV64I-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND3]], [[ANYEXT11]] - ; RV64I-NEXT: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64) - ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC8]], [[C9]](s32) - ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 - ; RV64I-NEXT: [[ANYEXT12:%[0-9]+]]:_(s64) = G_ANYEXT [[C10]](s32) - ; RV64I-NEXT: [[ANYEXT13:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR8]](s32) - ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT12]], [[ANYEXT13]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[ZEXT]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C2]](s32) + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[ZEXT1]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[C3]](s32) + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[ZEXT2]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[C4]](s32) + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[ZEXT3]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C1]] + ; RV64I-NEXT: [[ZEXT4:%[0-9]+]]:_(s64) = G_ZEXT [[C5]](s32) + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[ZEXT4]](s64) + ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[LSHR4]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[C1]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[ZEXT]](s64) + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[ANYEXT]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND6]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[ZEXT1]](s64) + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[ANYEXT1]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]] + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C1]] + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[ZEXT2]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[ADD]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT2]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND11]], [[ANYEXT3]] + ; RV64I-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[ZEXT5:%[0-9]+]]:_(s64) = G_ZEXT [[C10]](s32) + ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[AND12]], [[ZEXT5]](s64) + ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C11]](s32) + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT4]], [[LSHR8]] ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; @@ -343,59 +327,53 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[ANYEXT1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[ANYEXT2]] + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C1]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C3]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[ANYEXT3]] - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C]](s32) + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[AND4]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[AND]](s64) ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT5]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR2]], [[AND4]] - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[AND5]](s64) - ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC4]], [[C2]](s32) + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[LSHR3]], [[ANYEXT3]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR2]], [[AND7]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[AND2]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR4]](s32) - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ANYEXT6]], [[ANYEXT7]] - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT7]] - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[AND7]] - ; RV64I-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) - ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC5]], [[C3]](s32) - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR5]](s32) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT8]], [[ADD]] + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[LSHR4]], [[ANYEXT4]] + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT4]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND9]], [[AND10]] + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C1]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[AND4]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR5]], [[ADD]] ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 - ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT9]] + ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT5]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64I-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND8]], [[ANYEXT10]] - ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[AND9]](s64) - ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC6]], [[C7]](s32) + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND12]], [[COPY1]] + ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND13:%[0-9]+]]:_(s64) = G_AND [[ANYEXT6]], [[C1]] + ; RV64I-NEXT: [[AND14:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND14]], [[AND13]](s64) ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) - ; RV64I-NEXT: [[ANYEXT12:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR6]](s32) - ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT11]], [[ANYEXT12]] + ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT7]], [[LSHR6]] ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; @@ -430,65 +408,57 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[ANYEXT1]] + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[ANYEXT2]] + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C1]] + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[AND2]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C3]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[ANYEXT3]] + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[AND4]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C4]](s32) - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[ANYEXT4]] - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[AND4]](s64) - ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC4]], [[C]](s32) + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[C1]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[AND6]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C1]] + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[AND]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR4]](s32) - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ANYEXT5]], [[ANYEXT6]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR3]], [[AND5]] - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[AND6]](s64) - ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC5]], [[C2]](s32) + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[LSHR4]], [[ANYEXT4]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR3]], [[AND9]] + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[AND2]](s64) ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR5]](s32) - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[ANYEXT8]] - ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT8]] - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND7]], [[AND8]] - ; RV64I-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) - ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC6]], [[C3]](s32) - ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR6]](s32) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT9]], [[ADD]] + ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[ANYEXT5]] + ; RV64I-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT5]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND11]], [[AND12]] + ; RV64I-NEXT: [[AND13:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C1]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND13]], [[AND4]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR6]], [[ADD]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 - ; RV64I-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT10]] + ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND14:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT6]] ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257 - ; RV64I-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND9]], [[ANYEXT11]] - ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[AND10]](s64) - ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC7]], [[C4]](s32) + ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND14]], [[ANYEXT7]] + ; RV64I-NEXT: [[AND15:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND15]], [[AND6]](s64) ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; RV64I-NEXT: [[ANYEXT12:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) - ; RV64I-NEXT: [[ANYEXT13:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR7]](s32) - ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT12]], [[ANYEXT13]] + ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT8]], [[LSHR7]] ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; @@ -522,63 +492,61 @@ body: | ; RV64I: liveins: $x10 ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[OR]](s64) - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C1]](s32) - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[OR1]](s64) - ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C2]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[ANYEXT2]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[OR2]](s64) - ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C3]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[ANYEXT3]] - ; RV64I-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[OR3]](s64) - ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC4]], [[C4]](s32) - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR4]](s32) - ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[ANYEXT4]] - ; RV64I-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[OR4]](s64) - ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC5]], [[C]](s32) - ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR5]](s32) - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT5]], [[ANYEXT6]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND]] - ; RV64I-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) - ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC6]], [[C1]](s32) - ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR6]](s32) - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[ANYEXT8]] - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT8]] - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND1]], [[AND2]] - ; RV64I-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) - ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC7]], [[C2]](s32) - ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR7]](s32) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT9]], [[ADD]] - ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 - ; RV64I-NEXT: [[ANYEXT10:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT10]] - ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 - ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; RV64I-NEXT: [[ANYEXT11:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND3]], [[ANYEXT11]] - ; RV64I-NEXT: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64) - ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC8]], [[C9]](s32) - ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 - ; RV64I-NEXT: [[ANYEXT12:%[0-9]+]]:_(s64) = G_ANYEXT [[C10]](s32) - ; RV64I-NEXT: [[ANYEXT13:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR8]](s32) - ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT12]], [[ANYEXT13]] + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[ZEXT]](s64) + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[LSHR]] + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR]], [[C1]] + ; RV64I-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C2]](s32) + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[ZEXT1]](s64) + ; RV64I-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[OR]], [[LSHR1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[C1]] + ; RV64I-NEXT: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[C3]](s32) + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[ZEXT2]](s64) + ; RV64I-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR1]], [[LSHR2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[C1]] + ; RV64I-NEXT: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[C4]](s32) + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[ZEXT3]](s64) + ; RV64I-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[OR2]], [[LSHR3]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[OR3]], [[C1]] + ; RV64I-NEXT: [[ZEXT4:%[0-9]+]]:_(s64) = G_ZEXT [[C5]](s32) + ; RV64I-NEXT: [[LSHR4:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[ZEXT4]](s64) + ; RV64I-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[LSHR4]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[OR4]], [[C1]] + ; RV64I-NEXT: [[LSHR5:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[ZEXT]](s64) + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR5]], [[ANYEXT]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[OR4]], [[AND6]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[ZEXT1]](s64) + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[ANYEXT1]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]] + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C1]] + ; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[AND10]], [[ZEXT2]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[ADD]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT2]] + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV64I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND11]], [[ANYEXT3]] + ; RV64I-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[ZEXT5:%[0-9]+]]:_(s64) = G_ZEXT [[C10]](s32) + ; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s64) = G_LSHR [[AND12]], [[ZEXT5]](s64) + ; RV64I-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 32 + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C11]](s32) + ; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT4]], [[LSHR8]] ; RV64I-NEXT: $x10 = COPY [[SUB1]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir index 23bff1ae62528..ff26a84647951 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir @@ -15,42 +15,42 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[ANYEXT2]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND1]] + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT1]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND2]] ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C3]](s32) + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND3]](s64) ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[ANYEXT4]] - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT4]] - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[AND4]] + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT3]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT3]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND5]], [[AND6]] ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C5]](s32) - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT5]], [[ADD]] + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[C1]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[AND7]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]] ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT6]] + ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT5]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND5]], [[ANYEXT7]] - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND6]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C7]](s32) - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: $x10 = COPY [[ANYEXT8]](s64) + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ANYEXT]](s64) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND9]], [[COPY1]] + ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ANYEXT6]], [[C1]] + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[AND10]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: ctpop_i8 @@ -82,43 +82,43 @@ body: | ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[ANYEXT2]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND1]] + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT1]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND2]] ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C3]](s32) + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C1]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND3]](s64) ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[ANYEXT4]] - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT4]] - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[AND4]] + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT3]] + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT3]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND5]], [[AND6]] ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C5]](s32) - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT5]], [[ADD]] + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[C1]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C1]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[AND7]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]] ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT6]] + ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT5]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 257 ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND5]], [[ANYEXT7]] - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[ANYEXT]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND6]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C8]](s32) - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: $x10 = COPY [[ANYEXT8]](s64) + ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND9]], [[ANYEXT6]] + ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[C1]] + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND11]], [[AND10]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: ctpop_i16 @@ -149,39 +149,40 @@ body: | ; RV64I: liveins: $x10 ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 - ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[ANYEXT1]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) - ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) - ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[ANYEXT3]] - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT3]] - ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND1]], [[AND2]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) - ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C4]](s32) - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT4]], [[ADD]] - ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT5]] - ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 - ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND3]], [[ANYEXT6]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C7]](s32) - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: $x10 = COPY [[ANYEXT7]](s64) + ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[ZEXT]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[AND1]] + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C1]] + ; RV64I-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C3]](s32) + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[ZEXT1]](s64) + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT1]] + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] + ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND3]], [[AND4]] + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C1]] + ; RV64I-NEXT: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[C5]](s32) + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[ZEXT2]](s64) + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[ANYEXT2]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[ANYEXT3]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C1]] + ; RV64I-NEXT: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[C8]](s32) + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND7]], [[ZEXT3]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: ctpop_i32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir index 21bc62bb585b7..f4c05d2211d4c 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-cttz-rv64.mir @@ -20,42 +20,42 @@ body: | ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ANYEXT]] ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C1]](s32) + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C2]] + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[ANYEXT3]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT2]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND3]] ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C4]](s32) + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[C2]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[AND4]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT5]] - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT5]] - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT4]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT4]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[AND7]] ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[ADD1]](s64) - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C6]](s32) - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT6]], [[ADD1]] + ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ANYEXT5]], [[C2]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C2]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[AND8]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT7]] + ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT6]] ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[ANYEXT8]] - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND7]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C8]](s32) - ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: $x10 = COPY [[ANYEXT9]](s64) + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ANYEXT1]](s64) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[COPY1]] + ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[C2]] + ; RV64I-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C2]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND12]], [[AND11]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: cttz_i8 @@ -92,43 +92,43 @@ body: | ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ANYEXT]] ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C1]](s32) + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C2]] + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[ANYEXT3]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT2]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND3]] ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C4]](s32) + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[C2]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[AND4]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT5]] - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT5]] - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT4]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT4]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[AND7]] ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[ADD1]](s64) - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C6]](s32) - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT6]], [[ADD1]] + ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ANYEXT5]], [[C2]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C2]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[AND8]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT7]] + ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT6]] ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257 ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[ANYEXT8]] - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND7]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C9]](s32) - ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: $x10 = COPY [[ANYEXT9]](s64) + ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[ANYEXT7]] + ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ANYEXT8]], [[C2]] + ; RV64I-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C2]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND12]], [[AND11]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: cttz_i16 @@ -164,39 +164,40 @@ body: | ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[ANYEXT]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ANYEXT]] ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C1]](s32) - ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[ANYEXT2]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND1]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) - ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C3]](s32) - ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[ANYEXT4]] - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT4]] - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND2]], [[AND3]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[ADD1]](s64) - ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C5]](s32) - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT5]], [[ADD1]] - ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT6]] - ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 - ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND4]], [[ANYEXT7]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C8]](s32) - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: $x10 = COPY [[ANYEXT8]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C1]](s32) + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[ZEXT]](s64) + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT1]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C4]](s32) + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[ZEXT1]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT2]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT2]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C2]] + ; RV64I-NEXT: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[C6]](s32) + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[ZEXT2]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT3]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND7]], [[ANYEXT4]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C2]] + ; RV64I-NEXT: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[C9]](s32) + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[ZEXT3]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: cttz_i32 @@ -280,42 +281,42 @@ body: | ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ANYEXT]] ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C1]](s32) + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C2]] + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 85 - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[ANYEXT3]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT2]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND3]] ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C4]](s32) + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[C2]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[AND4]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 51 - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT5]] - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT5]] - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT4]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT4]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[AND7]] ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[ADD1]](s64) - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C6]](s32) - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT6]], [[ADD1]] + ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ANYEXT5]], [[C2]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C2]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[AND8]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT7]] + ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT6]] ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[ANYEXT8]] - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND7]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C8]](s32) - ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: $x10 = COPY [[ANYEXT9]](s64) + ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[ANYEXT1]](s64) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[COPY1]] + ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ANYEXT7]], [[C2]] + ; RV64I-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C2]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND12]], [[AND11]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: cttz_zero_undef_i8 @@ -352,43 +353,43 @@ body: | ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ANYEXT]] ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C1]](s32) + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C2]] + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845 - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[ANYEXT3]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT2]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND3]] ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C4]](s32) + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[C2]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[AND4]](s64) ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107 - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ANYEXT4]], [[ANYEXT5]] - ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT5]] - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT4]] + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT4]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND6]], [[AND7]] ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[ADD1]](s64) - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C6]](s32) - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT6]], [[ADD1]] + ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[ANYEXT5]], [[C2]] + ; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C2]] + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND9]], [[AND8]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT7]] + ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT6]] ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257 ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND6]], [[ANYEXT8]] - ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND7]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C9]](s32) - ; RV64I-NEXT: [[ANYEXT9:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: $x10 = COPY [[ANYEXT9]](s64) + ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[ANYEXT7]] + ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[C9]](s32) + ; RV64I-NEXT: [[AND11:%[0-9]+]]:_(s64) = G_AND [[ANYEXT8]], [[C2]] + ; RV64I-NEXT: [[AND12:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C2]] + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND12]], [[AND11]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: cttz_zero_undef_i16 @@ -424,39 +425,40 @@ body: | ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[ANYEXT]] ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ANYEXT]] ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ADD]] - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C1]](s32) - ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 - ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[ANYEXT2]] - ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND1]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[SUB]](s64) - ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 - ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C3]](s32) - ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C4]](s32) - ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT3]], [[ANYEXT4]] - ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT4]] - ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND2]], [[AND3]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[ADD1]](s64) - ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C5]](s32) - ; RV64I-NEXT: [[ANYEXT5:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR2]](s32) - ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT5]], [[ADD1]] - ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 - ; RV64I-NEXT: [[ANYEXT6:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) - ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT6]] - ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 - ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 - ; RV64I-NEXT: [[ANYEXT7:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) - ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND4]], [[ANYEXT7]] - ; RV64I-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64) - ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[C8]](s32) - ; RV64I-NEXT: [[ANYEXT8:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32) - ; RV64I-NEXT: $x10 = COPY [[ANYEXT8]](s64) + ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; RV64I-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C1]](s32) + ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[ZEXT]](s64) + ; RV64I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765 + ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) + ; RV64I-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[ANYEXT1]] + ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[AND]], [[AND2]] + ; RV64I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C2]] + ; RV64I-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C4]](s32) + ; RV64I-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND3]], [[ZEXT1]](s64) + ; RV64I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459 + ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C5]](s32) + ; RV64I-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR1]], [[ANYEXT2]] + ; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT2]] + ; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[AND4]], [[AND5]] + ; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C2]] + ; RV64I-NEXT: [[ZEXT2:%[0-9]+]]:_(s64) = G_ZEXT [[C6]](s32) + ; RV64I-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND6]], [[ZEXT2]](s64) + ; RV64I-NEXT: [[ADD2:%[0-9]+]]:_(s64) = G_ADD [[LSHR2]], [[ADD1]] + ; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135 + ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32) + ; RV64I-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[ADD2]], [[ANYEXT3]] + ; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009 + ; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24 + ; RV64I-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32) + ; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND7]], [[ANYEXT4]] + ; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[MUL]], [[C2]] + ; RV64I-NEXT: [[ZEXT3:%[0-9]+]]:_(s64) = G_ZEXT [[C9]](s32) + ; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[AND8]], [[ZEXT3]](s64) + ; RV64I-NEXT: $x10 = COPY [[LSHR3]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; ; RV64ZBB-LABEL: name: cttz_zero_undef_i32 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir index a426d75ae2974..0402ccba90074 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fshl-fshr-rv64.mir @@ -22,19 +22,16 @@ body: | ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[ANYEXT1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ANYEXT]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[TRUNC]](s32) - ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C2]](s32) - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[TRUNC3]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT3]], [[ANYEXT4]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C3]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND2]](s64) + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C3]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND3]](s64) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C3]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[AND5]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR1]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %3:_(s64) = COPY $x10 @@ -69,19 +66,16 @@ body: | ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[ANYEXT1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ANYEXT]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[TRUNC]](s32) - ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[C2]](s32) - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[TRUNC3]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT3]], [[ANYEXT4]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C3]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND2]](s64) + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C3]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND3]](s64) + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C3]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[AND5]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR1]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %3:_(s64) = COPY $x10 @@ -106,26 +100,23 @@ body: | ; CHECK: liveins: $x10, $x11, $x12 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[ANYEXT1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[TRUNC2]](s32) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[TRUNC3]](s32) - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR1]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT2]], [[ANYEXT3]] + ; CHECK-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND]] + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C2]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[ZEXT]](s64) + ; CHECK-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[LSHR]], [[AND1]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SLLW]], [[SRLW]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %3:_(s64) = COPY $x10 @@ -192,19 +183,16 @@ body: | ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[ANYEXT1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ANYEXT]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C2]](s32) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[TRUNC1]](s32) - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[TRUNC2]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT3]], [[ANYEXT4]] + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C3]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND2]](s64) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C3]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND3]](s64) + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C3]] + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[AND4]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %3:_(s64) = COPY $x10 @@ -239,19 +227,16 @@ body: | ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[ANYEXT1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ANYEXT]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C2]](s32) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[TRUNC1]](s32) - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[TRUNC2]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT3]], [[ANYEXT4]] + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT2]], [[C3]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND2]](s64) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C3]] + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[SHL]], [[AND3]](s64) + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C3]] + ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C3]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND5]], [[AND4]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %3:_(s64) = COPY $x10 @@ -276,26 +261,21 @@ body: | ; CHECK: liveins: $x10, $x11, $x12 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1 ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[ANYEXT1]] ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C2]](s32) - ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[SHL]], [[TRUNC3]](s32) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[TRUNC2]](s32) - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT2]], [[ANYEXT3]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C2]](s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[ZEXT]](s64) + ; CHECK-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[SHL]], [[AND1]] + ; CHECK-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY1]], [[AND]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SLLW]], [[SRLW]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %3:_(s64) = COPY $x10 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir index 6ba25ffd8c612..f749648ac51bd 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir @@ -276,10 +276,11 @@ body: | ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C1]](s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[ZEXT]](s64) ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT]], [[ANYEXT1]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ANYEXT1]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 ; @@ -324,24 +325,24 @@ body: | ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD]](p0) :: (load (s8) from unknown-address + 1) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ZEXTLOAD1]], [[C1]](s32) - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD1]](s32) + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C1]](s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[ZEXT]](s64) ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT]], [[ANYEXT1]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ANYEXT1]] ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64) ; CHECK-NEXT: [[ZEXTLOAD2:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 2) ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 3) - ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL1]](s32) + ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) + ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT2]], [[ZEXT]](s64) ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD2]](s32) - ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[ANYEXT2]], [[ANYEXT3]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[OR1]](s64) + ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ANYEXT3]] ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[C3]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL2]](s32) - ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[ANYEXT4]], [[OR]] + ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C3]](s32) + ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR1]], [[ZEXT1]](s64) + ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL2]], [[OR]] ; CHECK-NEXT: $x10 = COPY [[OR2]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 ; @@ -386,10 +387,11 @@ body: | ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C1]](s32) - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32) + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C1]](s32) + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ANYEXT]], [[ZEXT]](s64) ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ZEXTLOAD]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT]], [[ANYEXT1]] + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ANYEXT1]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 ; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir index a6c6764743e82..ae58e2c1ff1c1 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-lshr-rv64.mir @@ -8,15 +8,11 @@ body: | ; CHECK-LABEL: name: lshr_i8 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[TRUNC]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 @@ -35,15 +31,11 @@ body: | ; CHECK-LABEL: name: lshr_i15 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[TRUNC]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 @@ -62,15 +54,11 @@ body: | ; CHECK-LABEL: name: lshr_i16 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[TRUNC]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 @@ -89,11 +77,8 @@ body: | ; CHECK-LABEL: name: lshr_i32 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[TRUNC1]](s32) - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SRLW]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 @@ -329,11 +314,11 @@ body: | ; CHECK: liveins: $x10 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C]](s32) - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[C]](s64) + ; CHECK-NEXT: $x10 = COPY [[LSHR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %1:_(s64) = COPY $x10 %0:_(s48) = G_TRUNC %1(s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir index d17306a64c278..cc21d58d968d2 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir @@ -23,20 +23,14 @@ body: | ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT]], [[COPY1]] ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT1]] - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[TRUNC]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64) ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[TRUNC2]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT3]], [[ANYEXT4]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[AND2]], [[C2]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND3]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 @@ -66,20 +60,14 @@ body: | ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT]], [[COPY1]] ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT1]] - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[TRUNC]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND1]](s64) ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC3]], [[TRUNC2]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT3]], [[ANYEXT4]] + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[AND2]], [[C2]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND3]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[LSHR]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 @@ -102,7 +90,6 @@ body: | ; RV64I: liveins: $x10, $x11 ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 @@ -110,14 +97,10 @@ body: | ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT]], [[COPY1]] ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[TRUNC1]](s32) + ; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND]] ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[TRUNC2]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT2]], [[ANYEXT3]] + ; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND1]] + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SLLW]], [[SRLW]] ; RV64I-NEXT: $x10 = COPY [[OR]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; @@ -193,21 +176,14 @@ body: | ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT]], [[COPY1]] ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT1]] - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[TRUNC]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[TRUNC3]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT3]], [[ANYEXT4]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C2]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND4]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 @@ -237,21 +213,14 @@ body: | ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT]], [[COPY1]] ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT1]] - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[C2]](s32) - ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT2]] - ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND2]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC2]], [[TRUNC]](s32) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C2]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C2]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] - ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[AND3]](s64) - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC1]](s32) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[TRUNC3]](s32) - ; CHECK-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; CHECK-NEXT: [[ANYEXT4:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT3]], [[ANYEXT4]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C2]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND4]](s64) + ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[LSHR]], [[SHL]] ; CHECK-NEXT: $x10 = COPY [[OR]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 @@ -274,7 +243,6 @@ body: | ; RV64I: liveins: $x10, $x11 ; RV64I-NEXT: {{ $}} ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 - ; RV64I-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 @@ -282,14 +250,10 @@ body: | ; RV64I-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[ANYEXT]], [[COPY1]] ; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; RV64I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[TRUNC1]](s32) + ; RV64I-NEXT: [[SRLW:%[0-9]+]]:_(s64) = G_SRLW [[COPY]], [[AND]] ; RV64I-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[ANYEXT1]] - ; RV64I-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64) - ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[TRUNC2]](s32) - ; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32) - ; RV64I-NEXT: [[ANYEXT3:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[ANYEXT2]], [[ANYEXT3]] + ; RV64I-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[AND1]] + ; RV64I-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SRLW]], [[SLLW]] ; RV64I-NEXT: $x10 = COPY [[OR]](s64) ; RV64I-NEXT: PseudoRET implicit $x10 ; diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir index 972b7ebbb5da7..6985ad5511f67 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-sat-rv64.mir @@ -93,15 +93,16 @@ body: | ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[ADD]](s64), [[SEXT_INREG2]] ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 - ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY2]], [[C]](s32) + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SEXT_INREG2]](s64) + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[ZEXT]](s64) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT]], [[ANYEXT1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[ANYEXT]] ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ADD1]](s64) ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[COPY2]] - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT2]](s64) + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 %0:_(s32) = G_TRUNC %2(s64) @@ -247,15 +248,16 @@ body: | ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ne), [[SUB]](s64), [[SEXT_INREG2]] ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31 - ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY2]], [[C]](s32) + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY [[SEXT_INREG2]](s64) + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) + ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY3]], [[ZEXT]](s64) ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ANYEXT]], [[ANYEXT1]] + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASHR]], [[ANYEXT]] ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[ADD]](s64) ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s64), [[TRUNC1]], [[COPY2]] - ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT2]](s64) + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[SELECT]](s32) + ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %2:_(s64) = COPY $x10 %0:_(s32) = G_TRUNC %2(s64) diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir index 8d935af8a6064..2ee4520b14bdb 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-shl-rv64.mir @@ -8,14 +8,10 @@ body: | ; CHECK-LABEL: name: shl_i8 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[TRUNC]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 @@ -34,14 +30,10 @@ body: | ; CHECK-LABEL: name: shl_i15 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[TRUNC]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 @@ -60,14 +52,10 @@ body: | ; CHECK-LABEL: name: shl_i16 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC1]], [[TRUNC]](s32) - ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT1]](s64) + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] + ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) + ; CHECK-NEXT: $x10 = COPY [[SHL]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 @@ -86,11 +74,8 @@ body: | ; CHECK-LABEL: name: shl_i32 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 - ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) - ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[TRUNC1]](s32) - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32) - ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64) + ; CHECK-NEXT: [[SLLW:%[0-9]+]]:_(s64) = G_SLLW [[COPY]], [[COPY1]] + ; CHECK-NEXT: $x10 = COPY [[SLLW]](s64) ; CHECK-NEXT: PseudoRET implicit $x10 %0:_(s64) = COPY $x10 %1:_(s64) = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir index bb2ed424e9049..9fde63784a9e0 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir +++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir @@ -262,15 +262,16 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 - ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C]](s32) + ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64) ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s8)) - ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 1) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64) + ; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 1) ; CHECK-NEXT: PseudoRET ; ; UNALIGNED-LABEL: name: store_i16_unaligned @@ -313,24 +314,33 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64) - ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[ZEXT]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C3]](s32) - ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[ANYEXT]] - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[AND]](s64) - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) - ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C4]](s64) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 65535 + ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C4]] + ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C4]] + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND2]], [[AND1]](s64) + ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C5]](s64) ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s8)) - ; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1) - ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 - ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[LSHR]], [[C5]](s32) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64) - ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2) - ; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3) + ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64) + ; CHECK-NEXT: G_STORE [[TRUNC2]](s32), [[PTR_ADD1]](p0) :: (store (s8) into unknown-address + 1) + ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 + ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32) + ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C4]] + ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[LSHR]], [[C4]] + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[AND4]], [[AND3]](s64) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C5]](s64) + ; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p0) :: (store (s8) into unknown-address + 2) + ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR2]](s64) + ; CHECK-NEXT: G_STORE [[TRUNC3]](s32), [[PTR_ADD2]](p0) :: (store (s8) into unknown-address + 3) ; CHECK-NEXT: PseudoRET ; ; UNALIGNED-LABEL: name: store_i32_unaligned @@ -373,11 +383,15 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C]](s32) - ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) + ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[ZEXT]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64) ; CHECK-NEXT: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store (s16)) - ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 2) + ; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 2) ; CHECK-NEXT: PseudoRET ; ; UNALIGNED-LABEL: name: store_i32_align2 @@ -423,16 +437,21 @@ body: | ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64) ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s64) ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C2]](s32) - ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 - ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C3]](s64) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 + ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C3]] + ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[C2]](s32) + ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[AND]], [[ZEXT]](s64) + ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR1]](s64) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C4]](s64) ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16)) - ; CHECK-NEXT: G_STORE [[LSHR1]](s32), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 2) - ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64) - ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C2]](s32) - ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C3]](s64) - ; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4) - ; CHECK-NEXT: G_STORE [[LSHR2]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 6) + ; CHECK-NEXT: G_STORE [[TRUNC1]](s32), [[PTR_ADD1]](p0) :: (store (s16) into unknown-address + 2) + ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64) + ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR [[LSHR]], [[ZEXT]](s64) + ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR2]](s64) + ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C4]](s64) + ; CHECK-NEXT: G_STORE [[TRUNC2]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 4) + ; CHECK-NEXT: G_STORE [[TRUNC3]](s32), [[PTR_ADD2]](p0) :: (store (s16) into unknown-address + 6) ; CHECK-NEXT: PseudoRET ; ; UNALIGNED-LABEL: name: store_i64_align2 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll index 2f2e6b2bccf58..d2694098e1646 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb-zbkb.ll @@ -146,15 +146,18 @@ define void @rol_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind { ret void } +; FIXME: Bad materialization of -2 as 0xfffffffe. define signext i32 @rol_i32_neg_constant_rhs(i32 signext %a) nounwind { ; RV64I-LABEL: rol_i32_neg_constant_rhs: ; RV64I: # %bb.0: -; RV64I-NEXT: li a1, -2 -; RV64I-NEXT: neg a2, a0 +; RV64I-NEXT: neg a1, a0 ; RV64I-NEXT: andi a0, a0, 31 -; RV64I-NEXT: sllw a0, a1, a0 -; RV64I-NEXT: andi a2, a2, 31 -; RV64I-NEXT: srlw a1, a1, a2 +; RV64I-NEXT: li a2, 1 +; RV64I-NEXT: slli a2, a2, 32 +; RV64I-NEXT: addi a2, a2, -2 +; RV64I-NEXT: sllw a0, a2, a0 +; RV64I-NEXT: andi a1, a1, 31 +; RV64I-NEXT: srlw a1, a2, a1 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; @@ -232,15 +235,18 @@ define void @ror_i32_nosext(i32 signext %a, i32 signext %b, ptr %x) nounwind { ret void } +; FIXME: Bad materialization of -2 as 0xfffffffe. define signext i32 @ror_i32_neg_constant_rhs(i32 signext %a) nounwind { ; RV64I-LABEL: ror_i32_neg_constant_rhs: ; RV64I: # %bb.0: -; RV64I-NEXT: li a1, -2 -; RV64I-NEXT: neg a2, a0 +; RV64I-NEXT: neg a1, a0 ; RV64I-NEXT: andi a0, a0, 31 -; RV64I-NEXT: srlw a0, a1, a0 -; RV64I-NEXT: andi a2, a2, 31 -; RV64I-NEXT: sllw a1, a1, a2 +; RV64I-NEXT: li a2, 1 +; RV64I-NEXT: slli a2, a2, 32 +; RV64I-NEXT: addi a2, a2, -2 +; RV64I-NEXT: srlw a0, a2, a0 +; RV64I-NEXT: andi a1, a1, 31 +; RV64I-NEXT: sllw a1, a2, a1 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; @@ -418,12 +424,11 @@ define i64 @rori_i64_fshr(i64 %a) nounwind { ret i64 %1 } -; FIXME: We should use srli instead of srliw for better compression. define i8 @srli_i8(i8 %a) nounwind { ; CHECK-LABEL: srli_i8: ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 255 -; CHECK-NEXT: srliw a0, a0, 6 +; CHECK-NEXT: srli a0, a0, 6 ; CHECK-NEXT: ret %1 = lshr i8 %a, 6 ret i8 %1 @@ -433,20 +438,20 @@ define i8 @srli_i8(i8 %a) nounwind { define i8 @srai_i8(i8 %a) nounwind { ; RV64I-LABEL: srai_i8: ; RV64I: # %bb.0: -; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: sraiw a0, a0, 29 +; RV64I-NEXT: slli a0, a0, 56 +; RV64I-NEXT: srai a0, a0, 61 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: srai_i8: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: sext.b a0, a0 -; RV64ZBB-NEXT: sraiw a0, a0, 5 +; RV64ZBB-NEXT: srai a0, a0, 5 ; RV64ZBB-NEXT: ret ; ; RV64ZBKB-LABEL: srai_i8: ; RV64ZBKB: # %bb.0: -; RV64ZBKB-NEXT: slli a0, a0, 24 -; RV64ZBKB-NEXT: sraiw a0, a0, 29 +; RV64ZBKB-NEXT: slli a0, a0, 56 +; RV64ZBKB-NEXT: srai a0, a0, 61 ; RV64ZBKB-NEXT: ret %1 = ashr i8 %a, 5 ret i8 %1 @@ -457,38 +462,38 @@ define i16 @srli_i16(i16 %a) nounwind { ; RV64I-LABEL: srli_i16: ; RV64I: # %bb.0: ; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addi a1, a1, -1 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: and a0, a0, a1 -; RV64I-NEXT: srliw a0, a0, 6 +; RV64I-NEXT: srli a0, a0, 6 ; RV64I-NEXT: ret ; ; RV64ZBB-ZBKB-LABEL: srli_i16: ; RV64ZBB-ZBKB: # %bb.0: ; RV64ZBB-ZBKB-NEXT: zext.h a0, a0 -; RV64ZBB-ZBKB-NEXT: srliw a0, a0, 6 +; RV64ZBB-ZBKB-NEXT: srli a0, a0, 6 ; RV64ZBB-ZBKB-NEXT: ret %1 = lshr i16 %a, 6 ret i16 %1 } -; FIXME: We should use slli+srai with Zbb/Zbkb for better compression. +; FIXME: We should use slli+srai with Zbb for better compression. define i16 @srai_i16(i16 %a) nounwind { ; RV64I-LABEL: srai_i16: ; RV64I: # %bb.0: -; RV64I-NEXT: slli a0, a0, 16 -; RV64I-NEXT: sraiw a0, a0, 25 +; RV64I-NEXT: slli a0, a0, 48 +; RV64I-NEXT: srai a0, a0, 57 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: srai_i16: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: sext.h a0, a0 -; RV64ZBB-NEXT: sraiw a0, a0, 9 +; RV64ZBB-NEXT: srai a0, a0, 9 ; RV64ZBB-NEXT: ret ; ; RV64ZBKB-LABEL: srai_i16: ; RV64ZBKB: # %bb.0: -; RV64ZBKB-NEXT: slli a0, a0, 16 -; RV64ZBKB-NEXT: sraiw a0, a0, 25 +; RV64ZBKB-NEXT: slli a0, a0, 48 +; RV64ZBKB-NEXT: srai a0, a0, 57 ; RV64ZBKB-NEXT: ret %1 = ashr i16 %a, 9 ret i16 %1 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll index 0a1a9fcf8bae8..715eaaf8a36a3 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbb.ll @@ -37,7 +37,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -93,7 +93,7 @@ define signext i32 @log2_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -162,7 +162,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -202,10 +202,11 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: li s0, -1 -; RV64I-NEXT: srliw a0, a0, 1 -; RV64I-NEXT: or a0, s1, a0 +; RV64I-NEXT: slli a1, a0, 32 +; RV64I-NEXT: srli s1, a1, 32 +; RV64I-NEXT: srliw a1, a0, 1 +; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 2 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 4 @@ -225,7 +226,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -233,8 +234,6 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: lui a1, 4112 ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: call __muldi3 -; RV64I-NEXT: slli s1, s1, 32 -; RV64I-NEXT: srli s1, s1, 32 ; RV64I-NEXT: beqz s1, .LBB3_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: srliw a0, a0, 24 @@ -268,41 +267,41 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind { ret i32 %4 } -; FIXME: We don't need the shift pair before the beqz for RV64I. define i32 @ctlz_lshr_i32(i32 signext %a) { ; RV64I-LABEL: ctlz_lshr_i32: ; RV64I: # %bb.0: ; RV64I-NEXT: srliw a1, a0, 1 -; RV64I-NEXT: slli a2, a1, 32 -; RV64I-NEXT: srli a2, a2, 32 -; RV64I-NEXT: beqz a2, .LBB4_2 +; RV64I-NEXT: beqz a1, .LBB4_2 ; RV64I-NEXT: # %bb.1: # %cond.false ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: .cfi_def_cfa_offset 16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: li a2, 2 ; RV64I-NEXT: srliw a0, a0, 2 ; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 2 +; RV64I-NEXT: srl a1, a0, a2 ; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 8 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 16 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: srliw a1, a0, 1 -; RV64I-NEXT: lui a2, 349525 -; RV64I-NEXT: addiw a2, a2, 1365 -; RV64I-NEXT: and a1, a1, a2 +; RV64I-NEXT: lui a3, 349525 +; RV64I-NEXT: addiw a3, a3, 1365 +; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: sub a0, a0, a1 -; RV64I-NEXT: srliw a1, a0, 2 +; RV64I-NEXT: slli a1, a0, 32 +; RV64I-NEXT: srli a1, a1, 32 +; RV64I-NEXT: srl a1, a1, a2 ; RV64I-NEXT: lui a2, 209715 ; RV64I-NEXT: addiw a2, a2, 819 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -434,7 +433,7 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -479,7 +478,7 @@ define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -525,7 +524,7 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -586,7 +585,7 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -600,8 +599,9 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind { ; RV64I-NEXT: li a0, 0 ; RV64I-NEXT: beqz s0, .LBB9_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: srliw a0, a1, 24 -; RV64I-NEXT: addiw a0, a0, 1 +; RV64I-NEXT: li a0, 1 +; RV64I-NEXT: srliw a1, a1, 24 +; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: .LBB9_2: ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -709,7 +709,7 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -746,7 +746,7 @@ define i1 @ctpop_i32_ult_two(i32 signext %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -755,8 +755,6 @@ define i1 @ctpop_i32_ult_two(i32 signext %a) nounwind { ; RV64I-NEXT: addiw a1, a1, 257 ; RV64I-NEXT: call __muldi3 ; RV64I-NEXT: srliw a0, a0, 24 -; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: sltiu a0, a0, 2 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -777,8 +775,8 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 0(a0) -; RV64I-NEXT: srliw a1, a0, 1 +; RV64I-NEXT: lwu a0, 0(a0) +; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: addiw a2, a2, 1365 ; RV64I-NEXT: and a1, a1, a2 @@ -789,7 +787,7 @@ define signext i32 @ctpop_i32_load(ptr %p) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: add a0, a1, a0 -; RV64I-NEXT: srliw a1, a0, 4 +; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: lui a1, 61681 ; RV64I-NEXT: addiw a1, a1, -241 @@ -1124,12 +1122,14 @@ define i32 @abs_i32(i32 %x) { ret i32 %abs } +; FIXME: sext.w is not needed define signext i32 @abs_i32_sext(i32 signext %x) { ; RV64I-LABEL: abs_i32_sext: ; RV64I: # %bb.0: -; RV64I-NEXT: sraiw a1, a0, 31 -; RV64I-NEXT: addw a0, a0, a1 +; RV64I-NEXT: srai a1, a0, 31 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: xor a0, a0, a1 +; RV64I-NEXT: sext.w a0, a0 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: abs_i32_sext: diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll index 82928e35e4abf..1c2bafdcb3057 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv64zbkb.ll @@ -170,22 +170,18 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind { ret i32 %or } -; FIXME: Use packh define i32 @packh_i32_2(i32 %a, i32 %b) nounwind { ; RV64I-LABEL: packh_i32_2: ; RV64I: # %bb.0: ; RV64I-NEXT: andi a0, a0, 255 ; RV64I-NEXT: andi a1, a1, 255 -; RV64I-NEXT: slliw a1, a1, 8 +; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: packh_i32_2: ; RV64ZBKB: # %bb.0: -; RV64ZBKB-NEXT: andi a0, a0, 255 -; RV64ZBKB-NEXT: andi a1, a1, 255 -; RV64ZBKB-NEXT: slliw a1, a1, 8 -; RV64ZBKB-NEXT: or a0, a1, a0 +; RV64ZBKB-NEXT: packh a0, a0, a1 ; RV64ZBKB-NEXT: ret %and = and i32 %a, 255 %and1 = and i32 %b, 255 @@ -242,22 +238,16 @@ define i64 @packh_i64_2(i64 %a, i64 %b) nounwind { ret i64 %or } -; FIXME: Use packh define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind { ; RV64I-LABEL: packh_i16: ; RV64I: # %bb.0: -; RV64I-NEXT: slliw a1, a1, 8 +; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: or a0, a1, a0 -; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addiw a1, a1, -1 -; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: packh_i16: ; RV64ZBKB: # %bb.0: -; RV64ZBKB-NEXT: slli a1, a1, 8 -; RV64ZBKB-NEXT: or a0, a1, a0 -; RV64ZBKB-NEXT: zext.h a0, a0 +; RV64ZBKB-NEXT: packh a0, a0, a1 ; RV64ZBKB-NEXT: ret %zext = zext i8 %a to i16 %zext1 = zext i8 %b to i16 @@ -266,26 +256,19 @@ define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind { ret i16 %or } -; FIXME: Use packh define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) { ; RV64I-LABEL: packh_i16_2: ; RV64I: # %bb.0: ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: andi a0, a0, 255 -; RV64I-NEXT: slliw a0, a0, 8 +; RV64I-NEXT: slli a0, a0, 8 ; RV64I-NEXT: or a0, a0, a2 -; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addiw a1, a1, -1 -; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: packh_i16_2: ; RV64ZBKB: # %bb.0: ; RV64ZBKB-NEXT: add a0, a1, a0 -; RV64ZBKB-NEXT: andi a0, a0, 255 -; RV64ZBKB-NEXT: slli a0, a0, 8 -; RV64ZBKB-NEXT: or a0, a0, a2 -; RV64ZBKB-NEXT: zext.h a0, a0 +; RV64ZBKB-NEXT: packh a0, a2, a0 ; RV64ZBKB-NEXT: ret %4 = add i8 %1, %0 %5 = zext i8 %4 to i16 @@ -295,7 +278,6 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) { ret i16 %8 } -; FIXME: Use packh define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) { ; RV64I-LABEL: packh_i16_3: ; RV64I: # %bb.0: @@ -309,9 +291,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) { ; RV64ZBKB-LABEL: packh_i16_3: ; RV64ZBKB: # %bb.0: ; RV64ZBKB-NEXT: add a0, a1, a0 -; RV64ZBKB-NEXT: andi a0, a0, 255 -; RV64ZBKB-NEXT: slli a0, a0, 8 -; RV64ZBKB-NEXT: or a0, a0, a2 +; RV64ZBKB-NEXT: packh a0, a2, a0 ; RV64ZBKB-NEXT: sh a0, 0(a3) ; RV64ZBKB-NEXT: ret %4 = add i8 %1, %0 diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll b/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll index 3e090507ad642..75e318a58fd45 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/shift.ll @@ -40,13 +40,14 @@ define i16 @test_shl_i48(i48 %x) { ; ; RV64-LABEL: test_shl_i48: ; RV64: # %bb.0: -; RV64-NEXT: slliw a0, a0, 8 +; RV64-NEXT: slli a0, a0, 8 ; RV64-NEXT: ret %shl = shl i48 %x, 8 %trunc = trunc i48 %shl to i16 ret i16 %trunc } +; FIXME: Could use srlw to remove slli+srli. define i16 @test_lshr_i48_2(i48 %x, i48 %y) { ; RV32-LABEL: test_lshr_i48_2: ; RV32: # %bb.0: @@ -57,7 +58,9 @@ define i16 @test_lshr_i48_2(i48 %x, i48 %y) { ; RV64-LABEL: test_lshr_i48_2: ; RV64: # %bb.0: ; RV64-NEXT: andi a1, a1, 15 -; RV64-NEXT: srlw a0, a0, a1 +; RV64-NEXT: slli a0, a0, 32 +; RV64-NEXT: srli a0, a0, 32 +; RV64-NEXT: srl a0, a0, a1 ; RV64-NEXT: ret %and = and i48 %y, 15 %lshr = lshr i48 %x, %and @@ -65,6 +68,7 @@ define i16 @test_lshr_i48_2(i48 %x, i48 %y) { ret i16 %trunc } +; FIXME: Could use sraw to remove the sext.w. define i16 @test_ashr_i48_2(i48 %x, i48 %y) { ; RV32-LABEL: test_ashr_i48_2: ; RV32: # %bb.0: @@ -75,7 +79,8 @@ define i16 @test_ashr_i48_2(i48 %x, i48 %y) { ; RV64-LABEL: test_ashr_i48_2: ; RV64: # %bb.0: ; RV64-NEXT: andi a1, a1, 15 -; RV64-NEXT: sraw a0, a0, a1 +; RV64-NEXT: sext.w a0, a0 +; RV64-NEXT: sra a0, a0, a1 ; RV64-NEXT: ret %and = and i48 %y, 15 %ashr = ashr i48 %x, %and @@ -93,7 +98,7 @@ define i16 @test_shl_i48_2(i48 %x, i48 %y) { ; RV64-LABEL: test_shl_i48_2: ; RV64: # %bb.0: ; RV64-NEXT: andi a1, a1, 15 -; RV64-NEXT: sllw a0, a0, a1 +; RV64-NEXT: sll a0, a0, a1 ; RV64-NEXT: ret %and = and i48 %y, 15 %shl = shl i48 %x, %and