diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
index 54e65335edf3a..1c8d92d149adc 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -101,20 +101,18 @@ class TargetRegisterInfo;
     SDep() : Dep(nullptr, Data) {}
 
     /// Constructs an SDep with the specified values.
-    SDep(SUnit *S, Kind kind, unsigned Reg)
-      : Dep(S, kind), Contents() {
+    SDep(SUnit *S, Kind kind, Register Reg) : Dep(S, kind), Contents() {
       switch (kind) {
       default:
         llvm_unreachable("Reg given for non-register dependence!");
       case Anti:
       case Output:
-        assert(Reg != 0 &&
-               "SDep::Anti and SDep::Output must use a non-zero Reg!");
-        Contents.Reg = Reg;
+        assert(Reg && "SDep::Anti and SDep::Output must use a non-zero Reg!");
+        Contents.Reg = Reg.id();
         Latency = 0;
         break;
       case Data:
-        Contents.Reg = Reg;
+        Contents.Reg = Reg.id();
         Latency = 1;
         break;
       }
@@ -208,14 +206,12 @@ class TargetRegisterInfo;
     }
 
     /// Tests if this is a Data dependence that is associated with a register.
-    bool isAssignedRegDep() const {
-      return getKind() == Data && Contents.Reg != 0;
-    }
+    bool isAssignedRegDep() const { return getKind() == Data && Contents.Reg; }
 
     /// Returns the register associated with this edge. This is only valid on
     /// Data, Anti, and Output edges. On Data edges, this value may be zero,
     /// meaning there is no associated register.
-    unsigned getReg() const {
+    Register getReg() const {
       assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
              "getReg called on non-register dependence edge!");
       return Contents.Reg;
@@ -225,14 +221,14 @@ class TargetRegisterInfo;
     /// Data, Anti, and Output edges. On Anti and Output edges, this value must
     /// not be zero. On Data edges, the value may be zero, which would mean that
     /// no specific register is associated with this edge.
-    void setReg(unsigned Reg) {
+    void setReg(Register Reg) {
       assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
              "setReg called on non-register dependence edge!");
-      assert((getKind() != Anti || Reg != 0) &&
+      assert((getKind() != Anti || Reg) &&
              "SDep::Anti edge cannot use the zero register!");
-      assert((getKind() != Output || Reg != 0) &&
+      assert((getKind() != Output || Reg) &&
              "SDep::Output edge cannot use the zero register!");
-      Contents.Reg = Reg;
+      Contents.Reg = Reg.id();
     }
 
     void dump(const TargetRegisterInfo *TRI = nullptr) const;
diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index 73200e705f213..72bcd5874ff83 100644
--- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -829,7 +829,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
         if ((Edge->getKind() != SDep::Anti) &&
             (Edge->getKind() != SDep::Output)) continue;
 
-        MCRegister AntiDepReg = MCRegister::from(Edge->getReg());
+        MCRegister AntiDepReg = Edge->getReg().asMCReg();
         LLVM_DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
         assert(AntiDepReg && "Anti-dependence on reg0?");
 
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 0c0c616aac660..c5d410fd0c3ec 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -3969,8 +3969,7 @@ void GenericScheduler::reschedulePhysReg(SUnit *SU, bool isTop) {
   // Find already scheduled copies with a single physreg dependence and move
   // them just above the scheduled instruction.
   for (SDep &Dep : Deps) {
-    if (Dep.getKind() != SDep::Data ||
-        !Register::isPhysicalRegister(Dep.getReg()))
+    if (Dep.getKind() != SDep::Data || !Dep.getReg().isPhysical())
       continue;
     SUnit *DepSU = Dep.getSUnit();
     if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)