diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h index 427d86ee1bb8e..d3026ca45c349 100644 --- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h +++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h @@ -495,7 +495,7 @@ class AArch64FunctionInfo final : public MachineFunctionInfo { /// Add a LOH directive of this @p Kind and this @p Args. void addLOHDirective(MCLOHType Kind, MILOHArgs Args) { LOHContainerSet.push_back(MILOHDirective(Kind, Args)); - LOHRelated.insert(Args.begin(), Args.end()); + LOHRelated.insert_range(Args); } SmallVectorImpl &getForwardedMustTailRegParms() { diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index bb36af8fce5cc..f7defe79c6d31 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -395,7 +395,7 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, StringRef CPU, auto TRI = getRegisterInfo(); StringSet<> ReservedRegNames; - ReservedRegNames.insert(ReservedRegsForRA.begin(), ReservedRegsForRA.end()); + ReservedRegNames.insert_range(ReservedRegsForRA); for (unsigned i = 0; i < 29; ++i) { if (ReservedRegNames.count(TRI->getName(AArch64::X0 + i))) ReserveXRegisterForRA.set(i); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp index 69a5ff182191d..98a70c0dbb912 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp @@ -1042,7 +1042,7 @@ bool AMDGPUPromoteAllocaImpl::tryPromoteAllocaToVector(AllocaInst &Alloca) { // Delete all instructions. On the first pass, new dummy loads may have been // added so we need to collect them too. DenseSet InstsToDelete(WorkList.begin(), WorkList.end()); - InstsToDelete.insert(DeferredLoads.begin(), DeferredLoads.end()); + InstsToDelete.insert_range(DeferredLoads); for (Instruction *I : InstsToDelete) { assert(I->use_empty()); I->eraseFromParent(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp index 2fcb485a822d2..212b16cb3da6e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUSplitModule.cpp @@ -569,7 +569,7 @@ void SplitGraph::buildGraph(CallGraph &CG) { LLVM_DEBUG(dbgs() << " indirect call found\n"); FnsWithIndirectCalls.push_back(&Fn); } else if (!KnownCallees.empty()) - DirectCallees.insert(KnownCallees.begin(), KnownCallees.end()); + DirectCallees.insert_range(KnownCallees); } Node &N = getNode(Cache, Fn); diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp index ce8a044715573..ea9bc88bbe86b 100644 --- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp @@ -1795,7 +1795,7 @@ bool PreRARematStage::sinkTriviallyRematInsts(const GCNSubtarget &ST, // Collect only regions that has a rematerializable def as a live-in. SmallSet ImpactedRegions; for (const auto &It : RematDefToLiveInRegions) - ImpactedRegions.insert(It.second.begin(), It.second.end()); + ImpactedRegions.insert_range(It.second); // Make copies of register pressure and live-ins cache that will be updated // as we rematerialize. diff --git a/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp b/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp index c1df7ef43cadd..2a3f33fc44b59 100644 --- a/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp +++ b/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp @@ -196,7 +196,7 @@ int ARMConstantPoolConstant::getExistingMachineCPValue(MachineConstantPool *CP, auto *CPV = static_cast( CP->getConstants()[index].Val.MachineCPVal); auto *Constant = cast(CPV); - Constant->GVars.insert(GVars.begin(), GVars.end()); + Constant->GVars.insert_range(GVars); } return index; } diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp index 79cfac31e2d0e..d4de436ce96c9 100644 --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -568,7 +568,7 @@ static bool TryRemove(MachineInstr *MI, ReachingDefAnalysis &RDA, } if (!ModifiedITs.empty()) return false; - Killed.insert(RemoveITs.begin(), RemoveITs.end()); + Killed.insert_range(RemoveITs); return true; }; @@ -577,7 +577,7 @@ static bool TryRemove(MachineInstr *MI, ReachingDefAnalysis &RDA, return false; if (WontCorruptITs(Uses, RDA)) { - ToRemove.insert(Uses.begin(), Uses.end()); + ToRemove.insert_range(Uses); LLVM_DEBUG(dbgs() << "ARM Loops: Able to remove: " << *MI << " - can also remove:\n"; for (auto *Use : Uses) @@ -586,7 +586,7 @@ static bool TryRemove(MachineInstr *MI, ReachingDefAnalysis &RDA, SmallPtrSet Killed; RDA.collectKilledOperands(MI, Killed); if (WontCorruptITs(Killed, RDA)) { - ToRemove.insert(Killed.begin(), Killed.end()); + ToRemove.insert_range(Killed); LLVM_DEBUG(for (auto *Dead : Killed) dbgs() << " - " << *Dead); } @@ -759,7 +759,7 @@ bool LowOverheadLoop::ValidateTailPredicate() { SmallPtrSet Ignore; unsigned ExpectedVectorWidth = getTailPredVectorWidth(VCTP->getOpcode()); - Ignore.insert(VCTPs.begin(), VCTPs.end()); + Ignore.insert_range(VCTPs); if (TryRemove(Def, RDA, ElementChain, Ignore)) { bool FoundSub = false; @@ -781,7 +781,7 @@ bool LowOverheadLoop::ValidateTailPredicate() { return false; } } - ToRemove.insert(ElementChain.begin(), ElementChain.end()); + ToRemove.insert_range(ElementChain); } } @@ -795,7 +795,7 @@ bool LowOverheadLoop::ValidateTailPredicate() { if (auto *Def = RDA.getUniqueReachingMIDef( &Preheader->back(), VCTP->getOperand(1).getReg().asMCReg())) { SmallPtrSet Ignore; - Ignore.insert(VCTPs.begin(), VCTPs.end()); + Ignore.insert_range(VCTPs); TryRemove(Def, RDA, ToRemove, Ignore); } } @@ -1693,7 +1693,7 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) { } } - LoLoop.ToRemove.insert(LoLoop.VCTPs.begin(), LoLoop.VCTPs.end()); + LoLoop.ToRemove.insert_range(LoLoop.VCTPs); } void ARMLowOverheadLoops::Expand(LowOverheadLoop &LoLoop) { diff --git a/llvm/lib/Target/ARM/ARMParallelDSP.cpp b/llvm/lib/Target/ARM/ARMParallelDSP.cpp index e8bbd15c1ca03..05667f4f8619e 100644 --- a/llvm/lib/Target/ARM/ARMParallelDSP.cpp +++ b/llvm/lib/Target/ARM/ARMParallelDSP.cpp @@ -534,7 +534,7 @@ bool ARMParallelDSP::MatchSMLAD(Function &F) { InsertParallelMACs(R); Changed = true; - AllAdds.insert(R.getAdds().begin(), R.getAdds().end()); + AllAdds.insert_range(R.getAdds()); LLVM_DEBUG(dbgs() << "BB after inserting parallel MACs:\n" << BB); } } diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp index 77b93f6329a5d..6cba3898edd36 100644 --- a/llvm/lib/Target/Hexagon/BitTracker.cpp +++ b/llvm/lib/Target/Hexagon/BitTracker.cpp @@ -942,7 +942,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) { else dbgs() << "\n does not fall through\n"; } - Targets.insert(BTs.begin(), BTs.end()); + Targets.insert_range(BTs); } ++It; } while (FallsThrough && It != End); diff --git a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp index ea7a429056be9..ea16489da8cb1 100644 --- a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp @@ -399,7 +399,7 @@ void HexagonCommonGEP::processGepInst(GetElementPtrInst *GepI, // After last node has been created, update the use information. if (!Us.empty()) { PN->Flags |= GepNode::Used; - Uses[PN].insert(Us.begin(), Us.end()); + Uses[PN].insert_range(Us); } // Link the last node with the originating GEP instruction. This is to @@ -606,7 +606,7 @@ void HexagonCommonGEP::common() { // original values of Min. if (NF & GepNode::Used) { auto &U = Uses[N]; - MinUs.insert(U.begin(), U.end()); + MinUs.insert_range(U); } Flags |= NF; } diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp index 55e8572f33198..aaed78184b29d 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -1470,7 +1470,7 @@ void HCE::assignInits(const ExtRoot &ER, unsigned Begin, unsigned End, ExtValue(ED).Offset == EV.Offset; }; if (all_of(P.second, SameValue)) { - F->second.insert(P.second.begin(), P.second.end()); + F->second.insert_range(P.second); P.second.clear(); } } diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp index 7635eb634380c..dd054846f03c8 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -195,9 +195,9 @@ bool Coloring::color() { Q.insert(N); for (unsigned I = 0; I != Q.size(); ++I) { NodeSet &Ns = Edges[Q[I]]; - Q.insert(Ns.begin(), Ns.end()); + Q.insert_range(Ns); } - FirstQ.insert(Q.begin(), Q.end()); + FirstQ.insert_range(Q); }; for (Node N : Needed) Enqueue(N); diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp index 3df2bed0ca96e..2c8889572a93f 100644 --- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -1325,7 +1325,7 @@ bool PolynomialMultiplyRecognize::convertShiftsToLeft(BasicBlock *LoopB, // Found a cycle. C.insert(&I); classifyCycle(&I, C, Early, Late); - Cycled.insert(C.begin(), C.end()); + Cycled.insert_range(C); RShifts.insert(&I); } diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index d1daf7cd3d0d8..0907239153226 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -7236,7 +7236,7 @@ static bool PeepholePPC64ZExtGather(SDValue Op32, return false; ToPromote.insert(Op32.getNode()); - ToPromote.insert(ToPromote1.begin(), ToPromote1.end()); + ToPromote.insert_range(ToPromote1); return true; } @@ -7253,7 +7253,7 @@ static bool PeepholePPC64ZExtGather(SDValue Op32, return false; ToPromote.insert(Op32.getNode()); - ToPromote.insert(ToPromote1.begin(), ToPromote1.end()); + ToPromote.insert_range(ToPromote1); return true; } @@ -7269,7 +7269,7 @@ static bool PeepholePPC64ZExtGather(SDValue Op32, return false; ToPromote.insert(Op32.getNode()); - ToPromote.insert(ToPromote1.begin(), ToPromote1.end()); + ToPromote.insert_range(ToPromote1); return true; } @@ -7287,10 +7287,10 @@ static bool PeepholePPC64ZExtGather(SDValue Op32, ToPromote.insert(Op32.getNode()); if (Op0OK) - ToPromote.insert(ToPromote1.begin(), ToPromote1.end()); + ToPromote.insert_range(ToPromote1); if (Op1OK) - ToPromote.insert(ToPromote2.begin(), ToPromote2.end()); + ToPromote.insert_range(ToPromote2); return true; } @@ -7310,7 +7310,7 @@ static bool PeepholePPC64ZExtGather(SDValue Op32, ToPromote.insert(Op32.getNode()); if (Op0OK) - ToPromote.insert(ToPromote1.begin(), ToPromote1.end()); + ToPromote.insert_range(ToPromote1); return true; } diff --git a/llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp b/llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp index c23a6c3e8bbe8..abacd4b4ef857 100644 --- a/llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp @@ -284,7 +284,7 @@ class ConvergenceRegionAnalyzer { return false; return Token.value() == CT.value(); }); - RegionBlocks.insert(N.begin(), N.end()); + RegionBlocks.insert_range(N); } } diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h index fd83a3e62e1f1..a0d47cb052b42 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h @@ -100,7 +100,7 @@ struct RequirementHandler { void addCapabilities(const CapabilityList &ToAdd); void addCapability(Capability::Capability ToAdd) { addCapabilities({ToAdd}); } void addExtensions(const ExtensionList &ToAdd) { - AllExtensions.insert(ToAdd.begin(), ToAdd.end()); + AllExtensions.insert_range(ToAdd); } void addExtension(Extension::Extension ToAdd) { AllExtensions.insert(ToAdd); } // Add the given requirements to the lists. If constraints conflict, or these diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp index 3587570931541..236a1272bcebb 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp @@ -160,7 +160,7 @@ void SPIRVSubtarget::initAvailableExtInstSets() { void SPIRVSubtarget::initAvailableExtensions( const std::set &AllowedExtIds) { AvailableExtensions.clear(); - AvailableExtensions.insert(AllowedExtIds.begin(), AllowedExtIds.end()); + AvailableExtensions.insert_range(AllowedExtIds); accountForAMDShaderTrinaryMinmax(); } diff --git a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp index 0df2a15753cf3..2939f19da9c62 100644 --- a/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp @@ -59,7 +59,7 @@ static void addHints(ArrayRef Order, const TargetRegisterClass *RC, const MachineRegisterInfo *MRI) { SmallSet CopyHints; - CopyHints.insert(Hints.begin(), Hints.end()); + CopyHints.insert_range(Hints); Hints.clear(); for (MCPhysReg Reg : Order) if (CopyHints.count(Reg) && diff --git a/llvm/lib/Target/X86/X86CmovConversion.cpp b/llvm/lib/Target/X86/X86CmovConversion.cpp index 908e4b63ab0c9..00bb1e588bd9b 100644 --- a/llvm/lib/Target/X86/X86CmovConversion.cpp +++ b/llvm/lib/Target/X86/X86CmovConversion.cpp @@ -416,7 +416,7 @@ bool X86CmovConverterPass::checkForProfitableCmovCandidates( SmallPtrSet CmovInstructions; for (auto &Group : CmovInstGroups) - CmovInstructions.insert(Group.begin(), Group.end()); + CmovInstructions.insert_range(Group); //===--------------------------------------------------------------------===// // Step 1: Calculate instruction depth and loop depth. diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index b59d980172458..4f8daf8abd7e8 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -1214,7 +1214,7 @@ bool X86RegisterInfo::getRegAllocationHints(Register VirtReg, }; SmallSet CopyHints; - CopyHints.insert(Hints.begin(), Hints.end()); + CopyHints.insert_range(Hints); Hints.clear(); for (auto Hint : CopyHints) { if (RC.contains(Hint) && !MRI->isReserved(Hint))