diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 275d0193452a5..ee3f5dd4eed38 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1053,10 +1053,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
   }
 
   auto &FPTruncActions = getActionDefinitionsBuilder(G_FPTRUNC);
-  if (ST.hasCvtPkF16F32Inst())
-    FPTruncActions.legalFor(
-        {{S32, S64}, {S16, S32}, {V2S16, V2S32}, {V2S16, V2S64}});
-  else
+  if (ST.hasCvtPkF16F32Inst()) {
+    FPTruncActions.legalFor({{S32, S64}, {S16, S32}, {V2S16, V2S32}})
+                  .customFor({V2S16, V2S64});
+  } else
     FPTruncActions.legalFor({{S32, S64}, {S16, S32}});
   FPTruncActions.scalarize(0).lower();
 
@@ -2155,6 +2155,8 @@ bool AMDGPULegalizerInfo::legalizeCustom(
   case TargetOpcode::G_FMINNUM_IEEE:
   case TargetOpcode::G_FMAXNUM_IEEE:
     return legalizeMinNumMaxNum(Helper, MI);
+  case TargetOpcode::G_FPTRUNC:
+    return legalizeFPTrunc(Helper, MI, MRI);
   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
     return legalizeExtractVectorElt(MI, MRI, B);
   case TargetOpcode::G_INSERT_VECTOR_ELT:
@@ -2741,6 +2743,29 @@ bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(LegalizerHelper &Helper,
   return Helper.lowerFMinNumMaxNum(MI) == LegalizerHelper::Legalized;
 }
 
+bool AMDGPULegalizerInfo::legalizeFPTrunc(LegalizerHelper &Helper,
+                                          MachineInstr &MI,
+                                          MachineRegisterInfo &MRI) const {
+  // TODO: We should only use fast math flag. But the global option is
+  // still used here to be consistent, especially when the fast math flag is
+  // not working for FP_ROUND on the SelectDAG path at this moment.
+  MachineFunction &MF = Helper.MIRBuilder.getMF();
+  bool AllowInaccurateFPTRUNC = MI.getFlag(MachineInstr::FmAfn) ||
+                                MF.getTarget().Options.UnsafeFPMath;
+
+  if (AllowInaccurateFPTRUNC) {
+    // Use the tablegen pattern to select native instructions.
+    return true;
+  }
+
+  Register DstReg = MI.getOperand(0).getReg();
+  LLT DstTy = MRI.getType(DstReg);
+
+  // Scalarize the vector and fall through to lower f64 -> f16.
+  return Helper.fewerElementsVector(MI, 0, DstTy.getElementType()) ==
+         LegalizerHelper::Legalized;
+}
+
 bool AMDGPULegalizerInfo::legalizeExtractVectorElt(
   MachineInstr &MI, MachineRegisterInfo &MRI,
   MachineIRBuilder &B) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index 1f4e02b0d600a..faab326f53fcf 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -56,6 +56,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
   bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
                      MachineIRBuilder &B, bool Signed) const;
   bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
+  bool legalizeFPTrunc(LegalizerHelper &Helper, MachineInstr &MI,
+                       MachineRegisterInfo &MRI) const;
   bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
                                 MachineIRBuilder &B) const;
   bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 356040da95672..c710336b4fd1b 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -916,7 +916,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
   }
 
   if (Subtarget->hasCvtPkF16F32Inst()) {
-    setOperationAction(ISD::FP_ROUND, MVT::v2f16, Legal);
+    setOperationAction(ISD::FP_ROUND, MVT::v2f16, Custom);
   }
 
   setTargetDAGCombine({ISD::ADD,
@@ -6893,6 +6893,19 @@ SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
     return Op;
 
   EVT DstVT = Op.getValueType();
+
+  if (DstVT == MVT::v2f16) {
+    // FIXME: We should only use fast math flag here. However, the fast math
+    // flag is lost during fptrunc to fp_round lowering. In addition, the flag
+    // is not propagated during subsequent lowering.
+    bool AllowInaccurateFP_ROUND = Op->getFlags().hasApproximateFuncs() ||
+                                   DAG.getTarget().Options.UnsafeFPMath;
+    // With fast math, the tablegen pattern is used to select native
+    // instructions. Otherwise, the vector will be scalarized and custom lowered
+    // to preserve the precision.
+    return AllowInaccurateFP_ROUND ? Op : SDValue();
+  }
+
   SDLoc DL(Op);
   if (DstVT == MVT::f16) {
     // TODO: Handle strictfp
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.fpmath.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.fpmath.ll
new file mode 100644
index 0000000000000..2587d18bbc1b0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.fpmath.ll
@@ -0,0 +1,1748 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 < %s | FileCheck -check-prefixes=GFX950,GFX950-SDAG,GFX950-SAFE-SDAG %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=1 < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL,GFX950-SAFE-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 -enable-unsafe-fp-math < %s | FileCheck -check-prefixes=GFX950,GFX950-SDAG,GFX950-UNSAFE,GFX950-UNSAFE-SDAG %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=1 -enable-unsafe-fp-math < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL,GFX950-UNSAFE,GFX950-UNSAFE-GISEL %s
+
+define half @v_test_cvt_f32_f16(float %src) {
+; GFX950-LABEL: v_test_cvt_f32_f16:
+; GFX950:       ; %bb.0:
+; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-NEXT:    s_setpc_b64 s[30:31]
+  %res = fptrunc float %src to half
+  ret half %res
+}
+
+define <2 x half> @v_test_cvt_v2f32_v2f16(<2 x float> %src) {
+; GFX950-LABEL: v_test_cvt_v2f32_v2f16:
+; GFX950:       ; %bb.0:
+; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
+; GFX950-NEXT:    s_setpc_b64 s[30:31]
+  %res = fptrunc <2 x float> %src to <2 x half>
+  ret <2 x half> %res
+}
+
+define <3 x half> @v_test_cvt_v3f32_v3f16(<3 x float> %src) {
+; GFX950-SDAG-LABEL: v_test_cvt_v3f32_v3f16:
+; GFX950-SDAG:       ; %bb.0:
+; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SDAG-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX950-SDAG-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
+; GFX950-SDAG-NEXT:    v_mov_b32_e32 v1, v2
+; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-GISEL-LABEL: v_test_cvt_v3f32_v3f16:
+; GFX950-GISEL:       ; %bb.0:
+; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v3, v1
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v2
+; GFX950-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v3
+; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %res = fptrunc <3 x float> %src to <3 x half>
+  ret <3 x half> %res
+}
+
+define <4 x half> @v_test_cvt_v4f32_v4f16(<4 x float> %src) {
+; GFX950-SDAG-LABEL: v_test_cvt_v4f32_v4f16:
+; GFX950-SDAG:       ; %bb.0:
+; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SDAG-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
+; GFX950-SDAG-NEXT:    v_cvt_pk_f16_f32 v1, v2, v3
+; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-GISEL-LABEL: v_test_cvt_v4f32_v4f16:
+; GFX950-GISEL:       ; %bb.0:
+; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX950-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX950-GISEL-NEXT:    v_pack_b32_f16 v1, v2, v3
+; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %res = fptrunc <4 x float> %src to <4 x half>
+  ret <4 x half> %res
+}
+
+define <8 x half> @v_test_cvt_v8f32_v8f16(<8 x float> %src) {
+; GFX950-SDAG-LABEL: v_test_cvt_v8f32_v8f16:
+; GFX950-SDAG:       ; %bb.0:
+; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SDAG-NEXT:    v_cvt_pk_f16_f32 v0, v0, v1
+; GFX950-SDAG-NEXT:    v_cvt_pk_f16_f32 v1, v2, v3
+; GFX950-SDAG-NEXT:    v_cvt_pk_f16_f32 v2, v4, v5
+; GFX950-SDAG-NEXT:    v_cvt_pk_f16_f32 v3, v6, v7
+; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-GISEL-LABEL: v_test_cvt_v8f32_v8f16:
+; GFX950-GISEL:       ; %bb.0:
+; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; GFX950-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX950-GISEL-NEXT:    v_pack_b32_f16 v1, v2, v3
+; GFX950-GISEL-NEXT:    v_pack_b32_f16 v2, v4, v5
+; GFX950-GISEL-NEXT:    v_pack_b32_f16 v3, v6, v7
+; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %res = fptrunc <8 x float> %src to <8 x half>
+  ret <8 x half> %res
+}
+
+define half @v_test_cvt_f64_f16(double %src) {
+; GFX950-SAFE-SDAG-LABEL: v_test_cvt_f64_f16:
+; GFX950-SAFE-SDAG:       ; %bb.0:
+; GFX950-SAFE-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s0, 0x1ff
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v1, s0, v0
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s0, 0xffe
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v3, v1, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v2, s0, v0
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v4, 0x3f1, v3
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v0
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v4, v4, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v5, v4, v2
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v4, v4, v5
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v4, v2
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v3, 0xfffffc10, v3
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v2, v5, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s0, 0x40f
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v4, 7, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v4
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v4
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v4, v4, v5
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v2, v2, v4
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v4, 0x7c00
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v3
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v5, 0x7e00
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s0, v3
+; GFX950-SAFE-SDAG-NEXT:    s_mov_b32 s0, 0x8000
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v1, s0, v0
+; GFX950-SAFE-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-SAFE-GISEL-LABEL: v_test_cvt_f64_f16:
+; GFX950-SAFE-GISEL:       ; %bb.0:
+; GFX950-SAFE-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v5, 0x1ff
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v1, v5, v0
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v2, v1, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v2, 0xfffffc10, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v4, 0xffe
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v3, v4, v0
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v6, 1, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v5, v2, 12, v0
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v6, v6, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v7, v6, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v0
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v4, 0x7c00
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v3, v3, 9, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v0, v7, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v5, 7, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v5
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v0, v0, v5
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v2
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v4, 0x40f
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v4
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v2, 0x8000
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v1, v2, v0
+; GFX950-SAFE-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-UNSAFE-LABEL: v_test_cvt_f64_f16:
+; GFX950-UNSAFE:       ; %bb.0:
+; GFX950-UNSAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-UNSAFE-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX950-UNSAFE-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-UNSAFE-NEXT:    s_setpc_b64 s[30:31]
+  %res = fptrunc double %src to half
+  ret half %res
+}
+
+define <2 x half> @v_test_cvt_v2f64_v2f16(<2 x double> %src) {
+; GFX950-SAFE-SDAG-LABEL: v_test_cvt_v2f64_v2f16:
+; GFX950-SAFE-SDAG:       ; %bb.0:
+; GFX950-SAFE-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s0, 0x1ff
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v1, s0, v0
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s1, 0xffe
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v5, v1, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v4, s1, v0
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v6, 0x3f1, v5
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v4, 0x1000, v0
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v6, v6, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v7, v6, v4
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v4
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v5, 0xfffffc10, v5
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v6, v5, 12, v0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v5
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s2, 0x40f
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v6, 7, v4
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
+; GFX950-SAFE-SDAG-NEXT:    s_mov_b32 s3, 0x8000
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v4, v4, v6
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v6, 0x7c00
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v5
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v7, 0x7e00
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v5
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v1, s3, v0
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v3, s0, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v3
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v4, v3, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v2, s1, v1
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v5, 0x3f1, v4
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v1
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v5, v5, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v8, v5, v2
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v5, v5, v8
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v5, v2
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v4, 0xfffffc10, v4
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v5, v4, 12, v1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v2, v8, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-SAFE-SDAG-NEXT:    s_mov_b32 s0, 0x5040100
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v5, 7, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v5
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v5, v5, v8
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v2, v2, v5
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v4
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v4
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v2, s3, v1
+; GFX950-SAFE-SDAG-NEXT:    v_perm_b32 v0, v1, v0, s0
+; GFX950-SAFE-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-SAFE-GISEL-LABEL: v_test_cvt_v2f64_v2f16:
+; GFX950-SAFE-GISEL:       ; %bb.0:
+; GFX950-SAFE-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v7, 0x1ff
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v1, v7, v0
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v4, v1, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v4, 0xfffffc10, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v6, 0xffe
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v5, v6, v0
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v10, 1, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v9, v4, 12, v0
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v10, v10, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v11, v10, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v10, v10, v11
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v10, v0
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v8, 0x7c00
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v5, v5, 9, v8
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v0, v11, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v3, v7, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v9, 7, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v9
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v0, v0, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v4
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v9, 0x40f
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v9
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v4, 0x8000
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v1, v4, v0
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v1, v3, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v1, 0xfffffc10, v1
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 8, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v5, v6, v2
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v7, 1, v1
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v6, v1, 12, v2
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v7, v7, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v2, 0x1000, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v10, v7, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v7, v7, v10
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v7, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v5, v5, 9, v8
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v2, v10, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v1
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v6, 7, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v6
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v2, v2, v6
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v1
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v9
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v1, v2, v4, v1
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX950-SAFE-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-UNSAFE-LABEL: v_test_cvt_v2f64_v2f16:
+; GFX950-UNSAFE:       ; %bb.0:
+; GFX950-UNSAFE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-UNSAFE-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
+; GFX950-UNSAFE-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX950-UNSAFE-NEXT:    v_cvt_pk_f16_f32 v0, v0, v2
+; GFX950-UNSAFE-NEXT:    s_setpc_b64 s[30:31]
+  %res = fptrunc <2 x double> %src to <2 x half>
+  ret <2 x half> %res
+}
+
+define <3 x half> @v_test_cvt_v3f64_v3f16(<3 x double> %src) {
+; GFX950-SAFE-SDAG-LABEL: v_test_cvt_v3f64_v3f16:
+; GFX950-SAFE-SDAG:       ; %bb.0:
+; GFX950-SAFE-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s0, 0x1ff
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v4, v5, s0, v4
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 8, v5
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s1, 0xffe
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v7, v5, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v4, v6, s1, v4
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v8, 0x3f1, v7
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, 0x1000, v4
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v8, v8, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v9, v8, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v8, v8, v9
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v8, v6
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v7, 0xfffffc10, v7
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v8, v7, 12, v4
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, v9, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v7
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s2, 0x40f
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v1, s0, v0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v8, 7, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v8
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v8
+; GFX950-SAFE-SDAG-NEXT:    s_mov_b32 s3, 0x8000
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v6, v6, v8
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v8, 0x7c00
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v7
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v9, 0x7e00
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v4, v8, v9, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v7
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v4, v5, s3, v4
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v6, v1, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v5, s1, v0
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v7, 0x3f1, v6
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v5, 0x1000, v0
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v7, v7, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v10, v7, v5
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v7, v7, v10
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v7, v5
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v6, 0xfffffc10, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v7, v6, 12, v0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v5, v10, v5
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v5, v7, v5, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v7, 7, v5
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v7
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v5, 2, v5
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v7
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v7, v7, v10
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v5, v5, v7
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v0, v8, v9, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v1, s3, v0
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v3, s0, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v3
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v5, v3, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v2, s1, v1
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v6, 0x3f1, v5
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v1
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v6, v6, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v7, v6, v2
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v2
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v5, 0xfffffc10, v5
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v6, v5, 12, v1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v2, v7, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v5
+; GFX950-SAFE-SDAG-NEXT:    s_mov_b32 s0, 0x5040100
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v6, 7, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v2, v2, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v5
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v1, v8, v9, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v5
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v2, s3, v1
+; GFX950-SAFE-SDAG-NEXT:    v_perm_b32 v0, v1, v0, s0
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v1, v4
+; GFX950-SAFE-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-SAFE-GISEL-LABEL: v_test_cvt_v3f64_v3f16:
+; GFX950-SAFE-GISEL:       ; %bb.0:
+; GFX950-SAFE-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v9, 0x1ff
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v1, v9, v0
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v6, v1, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v6, 0xfffffc10, v6
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v7, 8, v1
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v8, 0xffe
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v7, v8, v0
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v12, 1, v6
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v11, v6, 12, v0
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v12, v12, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v13, v12, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v12, v12, v13
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v12, v0
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v10, 0x7c00
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v7, v7, 9, v10
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v0, v13, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v6
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v3, v9, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v11, 7, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v11
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v0, v0, v11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v6
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v11, 0x40f
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v4, v5, v9, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v6, v11
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v6, 0x8000
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v1, v6, v0
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v1, v3, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v1, 0xfffffc10, v1
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v7, 8, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v7, v8, v2
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v13, 1, v1
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v12, v1, 12, v2
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v13, v13, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v2, 0x1000, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v14, v13, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v13, v13, v14
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v13, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v7, v7, 9, v10
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v2, v14, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v1
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v2, v12, v2, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v12, 7, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v12
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v12
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v2, v2, v12
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v1
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v11
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v7, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v2, v6, v1
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v1, v5, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v1, 0xfffffc10, v1
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 8, v5
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v3, v3, v8, v4
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v8, 1, v1
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v7, v1, 12, v3
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v8, v8, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v3, 0x1000, v3
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v9, v8, v3
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v8, v8, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v8, v3
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v4, v4, 9, v10
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v3, v9, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v1
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v7, 7, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v7
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v7
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v3, v3, v7
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v1
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v3, v3, v10, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v11
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v5
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v1, v3, v6, v1
+; GFX950-SAFE-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-UNSAFE-SDAG-LABEL: v_test_cvt_v3f64_v3f16:
+; GFX950-UNSAFE-SDAG:       ; %bb.0:
+; GFX950-UNSAFE-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v2, v1
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v1, v[4:5]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX950-UNSAFE-SDAG-NEXT:    s_mov_b32 s0, 0x5040100
+; GFX950-UNSAFE-SDAG-NEXT:    v_perm_b32 v0, v2, v0, s0
+; GFX950-UNSAFE-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-UNSAFE-GISEL-LABEL: v_test_cvt_v3f64_v3f16:
+; GFX950-UNSAFE-GISEL:       ; %bb.0:
+; GFX950-UNSAFE-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v2, v1
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, v[4:5]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX950-UNSAFE-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v2
+; GFX950-UNSAFE-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %res = fptrunc <3 x double> %src to <3 x half>
+  ret <3 x half> %res
+}
+
+define <4 x half> @v_test_cvt_v4f64_v4f16(<4 x double> %src) {
+; GFX950-SAFE-SDAG-LABEL: v_test_cvt_v4f64_v4f16:
+; GFX950-SAFE-SDAG:       ; %bb.0:
+; GFX950-SAFE-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s0, 0x1ff
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v4, v5, s0, v4
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 8, v5
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s1, 0xffe
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v9, v5, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v4, v8, s1, v4
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v10, 0x3f1, v9
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v8, 0x1000, v4
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v10, v10, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v11, v10, v8
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v10, v10, v11
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v10, v8
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v9, 0xfffffc10, v9
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v10, v9, 12, v4
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v8, v11, v8
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v9
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s2, 0x40f
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v10, 7, v8
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v10
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 2, v8
+; GFX950-SAFE-SDAG-NEXT:    s_mov_b32 s3, 0x8000
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v10
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v1, s0, v0
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v8, v8, v10
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v10, 0x7c00
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v9
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v11, 0x7e00
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v4, v10, v11, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v9
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v4, v5, s3, v4
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v5, v7, s0, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 8, v7
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v8, v7, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v5, v6, s1, v5
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v9, 0x3f1, v8
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, 0x1000, v5
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v9, v9, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v12, v9, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v9, v9, v12
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v9, v6
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v8, 0xfffffc10, v8
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v9, v8, 12, v5
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, v12, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v8
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v6, v9, v6, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v9, 7, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v9
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v9
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v9, v9, v12
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v6, v6, v9
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v8
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v6, v10, v6, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v5, v10, v11, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v8
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 16, v7
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v5, v6, s3, v5
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 8, v1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v7, v1, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v6, s1, v0
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v8, 0x3f1, v7
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, 0x1000, v0
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v8, v8, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v9, v8, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v8, v8, v9
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v8, v6
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v7, 0xfffffc10, v7
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v8, v7, 12, v0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, v9, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v7
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v8, 7, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v8
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v8
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v8, v8, v9
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v6, v6, v8
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v7
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v6, v10, v6, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v0, v10, v11, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v7
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v1, s3, v0
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v3, s0, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v3
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v6, v3, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v2, s1, v1
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v7, 0x3f1, v6
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v1
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v7, v7, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v8, v7, v2
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v7, v7, v8
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v7, v2
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v6, 0xfffffc10, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v7, v6, 12, v1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v2, v8, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v6
+; GFX950-SAFE-SDAG-NEXT:    s_mov_b32 s0, 0x5040100
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v7, 7, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v7
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v7
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v7, v7, v8
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v2, v2, v7
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v1, v10, v11, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v2, s3, v1
+; GFX950-SAFE-SDAG-NEXT:    v_perm_b32 v0, v1, v0, s0
+; GFX950-SAFE-SDAG-NEXT:    v_perm_b32 v1, v5, v4, s0
+; GFX950-SAFE-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-SAFE-GISEL-LABEL: v_test_cvt_v4f64_v4f16:
+; GFX950-SAFE-GISEL:       ; %bb.0:
+; GFX950-SAFE-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v11, 0x1ff
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v1, v11, v0
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v8, v1, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v8, 0xfffffc10, v8
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v9, 8, v1
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v10, 0xffe
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v9, v10, v0
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v14, 1, v8
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v13, v8, 12, v0
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v14, v14, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v15, v14, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v14, v14, v15
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v14, v0
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v12, 0x7c00
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v9, v9, 9, v12
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v0, v15, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v8
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v3, v11, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v13, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v13, 7, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v13
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v13
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v0, v0, v13
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v8
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v13, 0x40f
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v4, v5, v11, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v12, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v8, v13
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v8, 0x8000
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v1, v8, v0
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v1, v3, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v1, 0xfffffc10, v1
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v9, 8, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v9, v10, v2
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v15, 1, v1
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v14, v1, 12, v2
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v15, v15, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v2, 0x1000, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v16, v15, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v15, v15, v16
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v15, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v9, v9, 9, v12
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v2, v16, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v1
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v2, v14, v2, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v14, 7, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v14
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v14
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v2, v2, v14
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v1
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v12, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v13
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v9, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v1, v2, v8, v1
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v2, v5, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v2, 0xfffffc10, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 8, v5
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v3, v3, v10, v4
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v14, 1, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v9, v2, 12, v3
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v14, v14, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v3, 0x1000, v3
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v15, v14, v3
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v14, v14, v15
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v14, v3
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v4, v4, 9, v12
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v3, v15, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v2
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v9, 7, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v9
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v3, v3, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v2
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v3, v3, v12, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v13
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v5
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v5, v7, v11, v6
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v3, v8, v2
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v3, v7, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v3, 0xfffffc10, v3
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 8, v7
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v4, v4, v10, v5
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v9, 1, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v6, v3, 12, v4
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v9, v9, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v4, 0x1000, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v10, v9, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v9, v9, v10
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v9, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v5, v5, 9, v12
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v1, 0xffff, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v4, v10, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v6, 7, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v6
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v4, v4, v6
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v3
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v13
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v7
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v3, v4, v8, v3
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
+; GFX950-SAFE-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-UNSAFE-SDAG-LABEL: v_test_cvt_v4f64_v4f16:
+; GFX950-UNSAFE-SDAG:       ; %bb.0:
+; GFX950-UNSAFE-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v4, v[4:5]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v5, v[6:7]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v2, v5
+; GFX950-UNSAFE-SDAG-NEXT:    s_mov_b32 s0, 0x5040100
+; GFX950-UNSAFE-SDAG-NEXT:    v_perm_b32 v0, v1, v0, s0
+; GFX950-UNSAFE-SDAG-NEXT:    v_perm_b32 v1, v2, v4, s0
+; GFX950-UNSAFE-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-UNSAFE-GISEL-LABEL: v_test_cvt_v4f64_v4f16:
+; GFX950-UNSAFE-GISEL:       ; %bb.0:
+; GFX950-UNSAFE-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v2, v[4:5]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v3, v[6:7]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX950-UNSAFE-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX950-UNSAFE-GISEL-NEXT:    v_pack_b32_f16 v1, v2, v3
+; GFX950-UNSAFE-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %res = fptrunc <4 x double> %src to <4 x half>
+  ret <4 x half> %res
+}
+
+define <8 x half> @v_test_cvt_v8f64_v8f16(<8 x double> %src) {
+; GFX950-SAFE-SDAG-LABEL: v_test_cvt_v8f64_v8f16:
+; GFX950-SAFE-SDAG:       ; %bb.0:
+; GFX950-SAFE-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s0, 0x1ff
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v12, v13, s0, v12
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v16, 8, v13
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s1, 0xffe
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v17, v16, s1, v12
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v16, v13, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v18, 0x3f1, v16
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v12, 0x1000, v17
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v18, v18, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v19, v18, v12
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v18, v18, v19
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v18, v12
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v18, 0xfffffc10, v16
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v16, v18, 12, v17
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v12, v19, v12
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v18
+; GFX950-SAFE-SDAG-NEXT:    s_movk_i32 s2, 0x40f
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v14, v15, s0, v14
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v16, 7, v12
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v16
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v12, 2, v12
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v13, 16, v13
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v16
+; GFX950-SAFE-SDAG-NEXT:    s_mov_b32 s3, 0x8000
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v8, v9, s0, v8
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v16, v16, v19
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v16, v12, v16
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v12, 0x7c00
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v18
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v4, v5, s0, v4
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v1, s0, v0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v19, v12, v16, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_mov_b32_e32 v16, 0x7e00
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v17
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v17, v12, v16, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v18
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v18, v15, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v17, v19, v17, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v13, v13, s3, v17
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v17, 8, v15
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v14, v17, s1, v14
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v19, 0x3f1, v18
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v17, 0x1000, v14
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v19, v19, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v20, v19, v17
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v19, v19, v20
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v19, v17
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v18, 0xfffffc10, v18
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v19, v18, 12, v14
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v17, v20, v17
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v18
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v15, 16, v15
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v17, v19, v17, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v19, 7, v17
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v19
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v17, 2, v17
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v19
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v19, v19, v20
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v17, v17, v19
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v18
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v17, v12, v17, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v14, v12, v16, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v18
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v14, v17, v14, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v14, v15, s3, v14
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v15, 8, v9
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v17, v9, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v8, v15, s1, v8
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v18, 0x3f1, v17
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v15, 0x1000, v8
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v18, v18, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v19, v18, v15
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v18, v18, v19
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v18, v15
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v17, 0xfffffc10, v17
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v18, v17, 12, v8
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v15, v19, v15
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v17
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v9, 16, v9
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v15, v18, v15, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v18, 7, v15
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v18
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v15, 2, v15
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v18
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v18, v18, v19
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v15, v15, v18
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v17
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v15, v12, v15, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v8, v12, v16, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v17
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v8, v15, v8, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v8, v9, s3, v8
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v9, v11, s0, v10
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v10, 8, v11
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v15, v11, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v9, v10, s1, v9
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v17, 0x3f1, v15
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v10, 0x1000, v9
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v17, v17, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v18, v17, v10
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v17, v17, v18
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v17, v10
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v15, 0xfffffc10, v15
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v17, v15, 12, v9
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v10, v18, v10
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v15
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v10, v17, v10, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v17, 7, v10
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v17
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v10, 2, v10
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v17
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v17, v17, v18
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v10, v10, v17
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v15
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v9, v12, v16, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v15
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v9, v10, v9, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v10, 16, v11
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v9, v10, s3, v9
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v10, 8, v5
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v11, v5, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v4, v10, s1, v4
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v15, 0x3f1, v11
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v10, 0x1000, v4
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v15, v15, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v17, v15, v10
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v15, v15, v17
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v15, v10
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v11, 0xfffffc10, v11
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v15, v11, 12, v4
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v10, v17, v10
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v11
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v5, 16, v5
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v10, v15, v10, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v15, 7, v10
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v15
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v10, 2, v10
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v15
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v15, v15, v17
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v10, v10, v15
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v11
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v10, v12, v10, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v4, v12, v16, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v11
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v4, v10, v4, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v4, v5, s3, v4
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v5, v7, s0, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 8, v7
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v10, v7, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v5, v6, s1, v5
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v11, 0x3f1, v10
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, 0x1000, v5
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v11, v11, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v15, v11, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v11, v11, v15
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v11, v6
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v10, 0xfffffc10, v10
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v11, v10, 12, v5
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, v15, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v10
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v6, v11, v6, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v11, 7, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v11
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v11
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v11, v11, v15
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v6, v6, v11
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v10
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v6, v12, v6, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v5, v12, v16, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v10
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 16, v7
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v5, v6, s3, v5
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 8, v1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v7, v1, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v6, s1, v0
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v10, 0x3f1, v7
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, 0x1000, v0
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v10, v10, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v11, v10, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v10, v10, v11
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v10, v6
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v7, 0xfffffc10, v7
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v10, v7, 12, v0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v6, v11, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v7
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v6, v10, v6, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v10, 7, v6
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v10
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v10
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v10, v10, v11
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v6, v6, v10
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v7
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v6, v12, v6, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v0, v12, v16, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v7
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v0, v1, s3, v0
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v3, s0, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v3
+; GFX950-SAFE-SDAG-NEXT:    v_bfe_u32 v6, v3, 20, 11
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v2, s1, v1
+; GFX950-SAFE-SDAG-NEXT:    v_sub_u32_e32 v7, 0x3f1, v6
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v1
+; GFX950-SAFE-SDAG-NEXT:    v_med3_i32 v7, v7, 0, 13
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v10, v7, v2
+; GFX950-SAFE-SDAG-NEXT:    v_lshlrev_b32_e32 v7, v7, v10
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v7, v2
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v6, 0xfffffc10, v6
+; GFX950-SAFE-SDAG-NEXT:    v_lshl_or_b32 v7, v6, 12, v1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v2, v10, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v6
+; GFX950-SAFE-SDAG-NEXT:    s_mov_b32 s0, 0x5040100
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_and_b32_e32 v7, 7, v2
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v7
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-SDAG-NEXT:    s_nop 0
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v7
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_or_b32_e32 v7, v7, v10
+; GFX950-SAFE-SDAG-NEXT:    v_add_u32_e32 v2, v2, v7
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v2, v12, v2, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v1, v12, v16, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v6
+; GFX950-SAFE-SDAG-NEXT:    s_nop 1
+; GFX950-SAFE-SDAG-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX950-SAFE-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-SAFE-SDAG-NEXT:    v_and_or_b32 v1, v2, s3, v1
+; GFX950-SAFE-SDAG-NEXT:    v_perm_b32 v0, v1, v0, s0
+; GFX950-SAFE-SDAG-NEXT:    v_perm_b32 v1, v5, v4, s0
+; GFX950-SAFE-SDAG-NEXT:    v_perm_b32 v2, v9, v8, s0
+; GFX950-SAFE-SDAG-NEXT:    v_perm_b32 v3, v14, v13, s0
+; GFX950-SAFE-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-SAFE-GISEL-LABEL: v_test_cvt_v8f64_v8f16:
+; GFX950-SAFE-GISEL:       ; %bb.0:
+; GFX950-SAFE-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v17, 0x1ff
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v0, v1, v17, v0
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v16, v1, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v19, 0xfffffc10, v16
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v18, 8, v1
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v16, 0xffe
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v18, v18, v16, v0
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v22, 1, v19
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v18
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v21, v19, 12, v18
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v22, v22, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v18, 0x1000, v18
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v23, v22, v18
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v22, v22, v23
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v22, v18
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v0, 0x7c00
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v20, v20, 9, v0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v18, v23, v18
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v19
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v3, v17, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v18, v21, v18, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v21, 7, v18
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v21
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v21
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v18, 2, v18
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v21, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v18, v18, v21
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v19
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v4, v5, v17, v4
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v6, v7, v17, v6
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v21, v18, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v18, 0x40f
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v19, v18
+; GFX950-SAFE-GISEL-NEXT:    v_mov_b32_e32 v19, 0x8000
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v20, v21, v20, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v1, v1, v19, v20
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v20, v3, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v20, 0xfffffc10, v20
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v21, 8, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v21, v16, v2
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v23, 1, v20
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v22, v20, 12, v2
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v23, v23, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v2, 0x1000, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v24, v23, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v23, v23, v24
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v23, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v21, v21, 9, v0
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 16, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v2, v24, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v20
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v2, v22, v2, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v22, 7, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v22
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v22
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v22, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v2, v2, v22
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v20
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v20, v18
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v20, 8, v5
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v21, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v2, v3, v19, v2
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v3, v5, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v3, 0xfffffc10, v3
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v22, 1, v3
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v4, v20, v16, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v21, v3, 12, v4
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v22, v22, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v4, 0x1000, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v23, v22, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v22, v22, v23
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v22, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v20, v20, 9, v0
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v4, v23, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v3
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v4, v21, v4, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v21, 7, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v21
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v21
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v21, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v4, v4, v21
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v3
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v4, v4, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v18
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v20, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 16, v5
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v3, v4, v19, v3
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v4, v7, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v4, 0xfffffc10, v4
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 8, v7
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v5, v5, v16, v6
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v21, 1, v4
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v20, v4, 12, v5
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v21, v21, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v5, 0x1000, v5
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v22, v21, v5
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v21, v21, v22
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v21, v5
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v6, v6, 9, v0
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v5, v22, v5
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v5, v20, v5, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v20, 7, v5
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v20
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v20
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 2, v5
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v20, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v5, v5, v20
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v4
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v5, v5, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v18
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 16, v7
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v7, v9, v17, v8
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v4, v5, v19, v4
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v5, v9, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v5, 0xfffffc10, v5
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v6, 8, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v6, v6, v16, v7
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v20, 1, v5
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v8, v5, 12, v6
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v20, v20, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v6, 0x1000, v6
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v21, v20, v6
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v20, v20, v21
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v20, v6
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v7, v7, 9, v0
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v6, v21, v6
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v5
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v8, 7, v6
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v8
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v8
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v6, 2, v6
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v6, v6, v8
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v5
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v8, v11, v17, v10
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v6, v6, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v18
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v5, v6, v7, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v6, 16, v9
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v5, v6, v19, v5
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v6, v11, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v6, 0xfffffc10, v6
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v7, 8, v11
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v7, v7, v16, v8
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v10, 1, v6
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v9, v6, 12, v7
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v10, v10, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v7, 0x1000, v7
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v20, v10, v7
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v10, v10, v20
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v10, v7
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v8, v8, 9, v0
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v7, v20, v7
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v6
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v9, 7, v7
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v9
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v7, 2, v7
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v7, v7, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v6
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v9, v13, v17, v12
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v7, v7, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v6, v18
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v6, v7, v8, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v7, 16, v11
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v6, v7, v19, v6
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v7, v13, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v7, 0xfffffc10, v7
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v8, 8, v13
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v8, v8, v16, v9
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v11, 1, v7
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v10, v7, 12, v8
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v11, v11, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v8, 0x1000, v8
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v12, v11, v8
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v11, v11, v12
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v11, v8
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v9, v9, 9, v0
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v8, v12, v8
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v7
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v8, v10, v8, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v10, 7, v8
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v10
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v10
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v8, 2, v8
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v8, v8, v10
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v7
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v10, v15, v17, v14
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v8, v8, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v7, v18
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v8, 16, v13
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v7, v8, v19, v7
+; GFX950-SAFE-GISEL-NEXT:    v_bfe_u32 v8, v15, 20, 11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v8, 0xfffffc10, v8
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v9, 8, v15
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v9, v9, v16, v10
+; GFX950-SAFE-GISEL-NEXT:    v_sub_u32_e32 v12, 1, v8
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v11, v8, 12, v9
+; GFX950-SAFE-GISEL-NEXT:    v_med3_i32 v12, v12, 0, 13
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v9, 0x1000, v9
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v13, v12, v9
+; GFX950-SAFE-GISEL-NEXT:    v_lshlrev_b32_e32 v12, v12, v13
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v12, v9
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v10, v10, 9, v0
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_or_b32_e32 v9, v13, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v8
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v11, 7, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v11
+; GFX950-SAFE-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v9, 2, v9
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[0:1]
+; GFX950-SAFE-GISEL-NEXT:    v_add_u32_e32 v9, v9, v11
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v8
+; GFX950-SAFE-GISEL-NEXT:    s_nop 1
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v8, v18
+; GFX950-SAFE-GISEL-NEXT:    v_lshrrev_b32_e32 v8, 16, v15
+; GFX950-SAFE-GISEL-NEXT:    s_nop 0
+; GFX950-SAFE-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v10, vcc
+; GFX950-SAFE-GISEL-NEXT:    v_and_or_b32 v8, v8, v19, v0
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v1
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v1, 0xffff, v3
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v2, 0xffff, v5
+; GFX950-SAFE-GISEL-NEXT:    v_and_b32_e32 v3, 0xffff, v7
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v1, v4, 16, v1
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v2, v6, 16, v2
+; GFX950-SAFE-GISEL-NEXT:    v_lshl_or_b32 v3, v8, 16, v3
+; GFX950-SAFE-GISEL-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-UNSAFE-SDAG-LABEL: v_test_cvt_v8f64_v8f16:
+; GFX950-UNSAFE-SDAG:       ; %bb.0:
+; GFX950-UNSAFE-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v12, v[12:13]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v13, v[14:15]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v8, v[8:9]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v9, v[10:11]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v4, v[4:5]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v5, v[6:7]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v12, v12
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v13, v13
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v8, v8
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v2, v5
+; GFX950-UNSAFE-SDAG-NEXT:    v_cvt_f16_f32_e32 v3, v9
+; GFX950-UNSAFE-SDAG-NEXT:    s_mov_b32 s0, 0x5040100
+; GFX950-UNSAFE-SDAG-NEXT:    v_perm_b32 v0, v1, v0, s0
+; GFX950-UNSAFE-SDAG-NEXT:    v_perm_b32 v1, v2, v4, s0
+; GFX950-UNSAFE-SDAG-NEXT:    v_perm_b32 v2, v3, v8, s0
+; GFX950-UNSAFE-SDAG-NEXT:    v_perm_b32 v3, v13, v12, s0
+; GFX950-UNSAFE-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-UNSAFE-GISEL-LABEL: v_test_cvt_v8f64_v8f16:
+; GFX950-UNSAFE-GISEL:       ; %bb.0:
+; GFX950-UNSAFE-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, v[2:3]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v2, v[4:5]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v3, v[6:7]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v4, v[8:9]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v5, v[10:11]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v6, v[12:13]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v7, v[14:15]
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v2, v2
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v3, v3
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v4, v4
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v5, v5
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v6, v6
+; GFX950-UNSAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v7, v7
+; GFX950-UNSAFE-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
+; GFX950-UNSAFE-GISEL-NEXT:    v_pack_b32_f16 v1, v2, v3
+; GFX950-UNSAFE-GISEL-NEXT:    v_pack_b32_f16 v2, v4, v5
+; GFX950-UNSAFE-GISEL-NEXT:    v_pack_b32_f16 v3, v6, v7
+; GFX950-UNSAFE-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %res = fptrunc <8 x double> %src to <8 x half>
+  ret <8 x half> %res
+}