diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h index d214ab9306c2f..426e430b947f9 100644 --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -257,6 +257,8 @@ namespace llvm { /// branches. extern char &BranchFolderPassID; + MachineFunctionPass *createBranchFolderPass(bool EnableTailMerge); + /// BranchRelaxation - This pass replaces branches that need to jump further /// than is supported by a branch instruction. extern char &BranchRelaxationPassID; diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp index 6f5afbd2a996a..5d015d7313b5c 100644 --- a/llvm/lib/CodeGen/BranchFolding.cpp +++ b/llvm/lib/CodeGen/BranchFolding.cpp @@ -90,10 +90,13 @@ namespace { /// BranchFolderPass - Wrap branch folder in a machine function pass. class BranchFolderLegacy : public MachineFunctionPass { + bool EnableTailMerge; + public: static char ID; - explicit BranchFolderLegacy() : MachineFunctionPass(ID) {} + explicit BranchFolderLegacy(bool EnableTailMerge = true) + : MachineFunctionPass(ID), EnableTailMerge(EnableTailMerge) {} bool runOnMachineFunction(MachineFunction &MF) override; @@ -152,7 +155,8 @@ bool BranchFolderLegacy::runOnMachineFunction(MachineFunction &MF) { // TailMerge can create jump into if branches that make CFG irreducible for // HW that requires structurized CFG. bool EnableTailMerge = !MF.getTarget().requiresStructuredCFG() && - PassConfig->getEnableTailMerge(); + PassConfig->getEnableTailMerge() && + this->EnableTailMerge; MBFIWrapper MBBFreqInfo( getAnalysis().getMBFI()); BranchFolder Folder( @@ -2080,3 +2084,7 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) { ++NumHoist; return true; } + +MachineFunctionPass *llvm::createBranchFolderPass(bool EnableTailMerge = true) { + return new BranchFolderLegacy(EnableTailMerge); +} diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 7fb64be3975d5..543bed9281fc5 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -18,6 +18,7 @@ #include "RISCVTargetTransformInfo.h" #include "TargetInfo/RISCVTargetInfo.h" #include "llvm/Analysis/TargetTransformInfo.h" +#include "llvm/CodeGen/BranchFoldingPass.h" #include "llvm/CodeGen/GlobalISel/CSEInfo.h" #include "llvm/CodeGen/GlobalISel/IRTranslator.h" #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" @@ -570,6 +571,7 @@ void RISCVPassConfig::addPreEmitPass() { addPass(createMachineCopyPropagationPass(true)); if (TM->getOptLevel() >= CodeGenOptLevel::Default) addPass(createRISCVLateBranchOptPass()); + addPass(createBranchFolderPass(false)); addPass(&BranchRelaxationPassID); addPass(createRISCVMakeCompressibleOptPass()); } diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll index 95af7861d4798..74ec7308cb646 100644 --- a/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll +++ b/llvm/test/CodeGen/RISCV/GlobalISel/rv32zbb.ll @@ -357,11 +357,6 @@ define i64 @ctpop_i64(i64 %a) nounwind { define i1 @ctpop_i64_ugt_two(i64 %a) nounwind { ; RV32I-LABEL: ctpop_i64_ugt_two: ; RV32I: # %bb.0: -; RV32I-NEXT: j .LBB6_2 -; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: sltiu a0, zero, 0 -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB6_2: ; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: lui a3, 349525 ; RV32I-NEXT: lui a4, 209715 @@ -404,11 +399,6 @@ define i1 @ctpop_i64_ugt_two(i64 %a) nounwind { ; ; RV32ZBB-LABEL: ctpop_i64_ugt_two: ; RV32ZBB: # %bb.0: -; RV32ZBB-NEXT: j .LBB6_2 -; RV32ZBB-NEXT: # %bb.1: -; RV32ZBB-NEXT: sltiu a0, zero, 0 -; RV32ZBB-NEXT: ret -; RV32ZBB-NEXT: .LBB6_2: ; RV32ZBB-NEXT: cpop a0, a0 ; RV32ZBB-NEXT: cpop a1, a1 ; RV32ZBB-NEXT: add a0, a1, a0 @@ -422,11 +412,6 @@ define i1 @ctpop_i64_ugt_two(i64 %a) nounwind { define i1 @ctpop_i64_ugt_one(i64 %a) nounwind { ; RV32I-LABEL: ctpop_i64_ugt_one: ; RV32I: # %bb.0: -; RV32I-NEXT: j .LBB7_2 -; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: snez a0, zero -; RV32I-NEXT: ret -; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: lui a3, 349525 ; RV32I-NEXT: lui a4, 209715 @@ -470,11 +455,6 @@ define i1 @ctpop_i64_ugt_one(i64 %a) nounwind { ; ; RV32ZBB-LABEL: ctpop_i64_ugt_one: ; RV32ZBB: # %bb.0: -; RV32ZBB-NEXT: j .LBB7_2 -; RV32ZBB-NEXT: # %bb.1: -; RV32ZBB-NEXT: snez a0, zero -; RV32ZBB-NEXT: ret -; RV32ZBB-NEXT: .LBB7_2: ; RV32ZBB-NEXT: cpop a0, a0 ; RV32ZBB-NEXT: cpop a1, a1 ; RV32ZBB-NEXT: add a0, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll index 694662eab1681..32df712503296 100644 --- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll @@ -22,7 +22,7 @@ ; CHECK-NEXT: Expand large div/rem ; CHECK-NEXT: Expand fp ; CHECK-NEXT: Expand Atomic instructions -; CHECK-NEXT: RISC-V Zacas ABI fix +; CHECK-NEXT: RISC-V Zacas ABI fix ; CHECK-NEXT: Module Verifier ; CHECK-NEXT: Lower Garbage Collection Instructions ; CHECK-NEXT: Shadow Stack GC Lowering @@ -62,6 +62,10 @@ ; CHECK-NEXT: Insert fentry calls ; CHECK-NEXT: Insert XRay ops ; CHECK-NEXT: Implement the 'patchable-function' attribute +; CHECK-NEXT: MachineDominator Tree Construction +; CHECK-NEXT: Machine Natural Loop Construction +; CHECK-NEXT: Machine Block Frequency Analysis +; CHECK-NEXT: Control Flow Optimizer ; CHECK-NEXT: Branch relaxation pass ; CHECK-NEXT: RISC-V Make Compressible ; CHECK-NEXT: Contiguously Lay Out Funclets diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index 19de864422bc5..d3a0b89fc2c36 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -26,7 +26,7 @@ ; CHECK-NEXT: Expand large div/rem ; CHECK-NEXT: Expand fp ; CHECK-NEXT: Expand Atomic instructions -; CHECK-NEXT: RISC-V Zacas ABI fix +; CHECK-NEXT: RISC-V Zacas ABI fix ; CHECK-NEXT: Dominator Tree Construction ; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Canonicalize natural loops @@ -195,6 +195,10 @@ ; CHECK-NEXT: Implement the 'patchable-function' attribute ; CHECK-NEXT: Machine Copy Propagation Pass ; CHECK-NEXT: RISC-V Late Branch Optimisation Pass +; CHECK-NEXT: MachineDominator Tree Construction +; CHECK-NEXT: Machine Natural Loop Construction +; CHECK-NEXT: Machine Block Frequency Analysis +; CHECK-NEXT: Control Flow Optimizer ; CHECK-NEXT: Branch relaxation pass ; CHECK-NEXT: RISC-V Make Compressible ; CHECK-NEXT: Contiguously Lay Out Funclets diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll index b9702e9fe0fc2..7c45eccc86bcc 100644 --- a/llvm/test/CodeGen/RISCV/atomic-signext.ll +++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll @@ -4992,20 +4992,20 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA: # %bb.0: ; RV32IA-NEXT: andi a2, a1, 1 ; RV32IA-NEXT: mv a1, a0 -; RV32IA-NEXT: beqz a2, .LBB60_2 -; RV32IA-NEXT: # %bb.1: # %then -; RV32IA-NEXT: li a0, 1 -; RV32IA-NEXT: amomax.w a0, a0, (a1) -; RV32IA-NEXT: ret -; RV32IA-NEXT: .LBB60_2: # %else +; RV32IA-NEXT: bnez a2, .LBB60_4 +; RV32IA-NEXT: # %bb.1: # %else ; RV32IA-NEXT: lw a0, 0(a1) ; RV32IA-NEXT: mv a2, a0 -; RV32IA-NEXT: bgtz a0, .LBB60_4 -; RV32IA-NEXT: # %bb.3: # %else +; RV32IA-NEXT: bgtz a0, .LBB60_3 +; RV32IA-NEXT: # %bb.2: # %else ; RV32IA-NEXT: li a2, 1 -; RV32IA-NEXT: .LBB60_4: # %else +; RV32IA-NEXT: .LBB60_3: # %else ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret +; RV32IA-NEXT: .LBB60_4: # %then +; RV32IA-NEXT: li a0, 1 +; RV32IA-NEXT: amomax.w a0, a0, (a1) +; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_max_i32_monotonic_crossbb: ; RV64I: # %bb.0: @@ -5056,19 +5056,19 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA: # %bb.0: ; RV64IA-NEXT: andi a2, a1, 1 ; RV64IA-NEXT: mv a1, a0 -; RV64IA-NEXT: beqz a2, .LBB60_2 -; RV64IA-NEXT: # %bb.1: # %then -; RV64IA-NEXT: li a0, 1 -; RV64IA-NEXT: amomax.w a0, a0, (a1) -; RV64IA-NEXT: ret -; RV64IA-NEXT: .LBB60_2: # %else +; RV64IA-NEXT: bnez a2, .LBB60_4 +; RV64IA-NEXT: # %bb.1: # %else ; RV64IA-NEXT: lw a0, 0(a1) ; RV64IA-NEXT: mv a2, a0 -; RV64IA-NEXT: bgtz a0, .LBB60_4 -; RV64IA-NEXT: # %bb.3: # %else +; RV64IA-NEXT: bgtz a0, .LBB60_3 +; RV64IA-NEXT: # %bb.2: # %else ; RV64IA-NEXT: li a2, 1 -; RV64IA-NEXT: .LBB60_4: # %else +; RV64IA-NEXT: .LBB60_3: # %else ; RV64IA-NEXT: sw a2, 0(a1) +; RV64IA-NEXT: ret +; RV64IA-NEXT: .LBB60_4: # %then +; RV64IA-NEXT: li a0, 1 +; RV64IA-NEXT: amomax.w a0, a0, (a1) ; RV64IA-NEXT: ret br i1 %c, label %then, label %else @@ -5140,20 +5140,20 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA: # %bb.0: ; RV32IA-NEXT: andi a2, a1, 1 ; RV32IA-NEXT: mv a1, a0 -; RV32IA-NEXT: beqz a2, .LBB61_2 -; RV32IA-NEXT: # %bb.1: # %then -; RV32IA-NEXT: li a0, 1 -; RV32IA-NEXT: amomin.w a0, a0, (a1) -; RV32IA-NEXT: ret -; RV32IA-NEXT: .LBB61_2: # %else +; RV32IA-NEXT: bnez a2, .LBB61_4 +; RV32IA-NEXT: # %bb.1: # %else ; RV32IA-NEXT: lw a0, 0(a1) ; RV32IA-NEXT: mv a2, a0 -; RV32IA-NEXT: blez a0, .LBB61_4 -; RV32IA-NEXT: # %bb.3: # %else +; RV32IA-NEXT: blez a0, .LBB61_3 +; RV32IA-NEXT: # %bb.2: # %else ; RV32IA-NEXT: li a2, 1 -; RV32IA-NEXT: .LBB61_4: # %else +; RV32IA-NEXT: .LBB61_3: # %else ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret +; RV32IA-NEXT: .LBB61_4: # %then +; RV32IA-NEXT: li a0, 1 +; RV32IA-NEXT: amomin.w a0, a0, (a1) +; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_min_i32_monotonic_crossbb: ; RV64I: # %bb.0: @@ -5206,19 +5206,19 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA: # %bb.0: ; RV64IA-NEXT: andi a2, a1, 1 ; RV64IA-NEXT: mv a1, a0 -; RV64IA-NEXT: beqz a2, .LBB61_2 -; RV64IA-NEXT: # %bb.1: # %then -; RV64IA-NEXT: li a0, 1 -; RV64IA-NEXT: amomin.w a0, a0, (a1) -; RV64IA-NEXT: ret -; RV64IA-NEXT: .LBB61_2: # %else +; RV64IA-NEXT: bnez a2, .LBB61_4 +; RV64IA-NEXT: # %bb.1: # %else ; RV64IA-NEXT: lw a0, 0(a1) ; RV64IA-NEXT: mv a2, a0 -; RV64IA-NEXT: blez a0, .LBB61_4 -; RV64IA-NEXT: # %bb.3: # %else +; RV64IA-NEXT: blez a0, .LBB61_3 +; RV64IA-NEXT: # %bb.2: # %else ; RV64IA-NEXT: li a2, 1 -; RV64IA-NEXT: .LBB61_4: # %else +; RV64IA-NEXT: .LBB61_3: # %else ; RV64IA-NEXT: sw a2, 0(a1) +; RV64IA-NEXT: ret +; RV64IA-NEXT: .LBB61_4: # %then +; RV64IA-NEXT: li a0, 1 +; RV64IA-NEXT: amomin.w a0, a0, (a1) ; RV64IA-NEXT: ret br i1 %c, label %then, label %else @@ -5418,21 +5418,21 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV32IA: # %bb.0: ; RV32IA-NEXT: andi a2, a1, 1 ; RV32IA-NEXT: mv a1, a0 -; RV32IA-NEXT: beqz a2, .LBB63_2 -; RV32IA-NEXT: # %bb.1: # %then -; RV32IA-NEXT: li a0, 1 -; RV32IA-NEXT: amominu.w a0, a0, (a1) -; RV32IA-NEXT: ret -; RV32IA-NEXT: .LBB63_2: # %else +; RV32IA-NEXT: bnez a2, .LBB63_4 +; RV32IA-NEXT: # %bb.1: # %else ; RV32IA-NEXT: lw a0, 0(a1) ; RV32IA-NEXT: li a3, 1 ; RV32IA-NEXT: mv a2, a0 -; RV32IA-NEXT: bltu a0, a3, .LBB63_4 -; RV32IA-NEXT: # %bb.3: # %else +; RV32IA-NEXT: bltu a0, a3, .LBB63_3 +; RV32IA-NEXT: # %bb.2: # %else ; RV32IA-NEXT: li a2, 1 -; RV32IA-NEXT: .LBB63_4: # %else +; RV32IA-NEXT: .LBB63_3: # %else ; RV32IA-NEXT: sw a2, 0(a1) ; RV32IA-NEXT: ret +; RV32IA-NEXT: .LBB63_4: # %then +; RV32IA-NEXT: li a0, 1 +; RV32IA-NEXT: amominu.w a0, a0, (a1) +; RV32IA-NEXT: ret ; ; RV64I-LABEL: atomicrmw_umin_i32_monotonic_crossbb: ; RV64I: # %bb.0: @@ -5486,20 +5486,20 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind ; RV64IA: # %bb.0: ; RV64IA-NEXT: andi a2, a1, 1 ; RV64IA-NEXT: mv a1, a0 -; RV64IA-NEXT: beqz a2, .LBB63_2 -; RV64IA-NEXT: # %bb.1: # %then -; RV64IA-NEXT: li a0, 1 -; RV64IA-NEXT: amominu.w a0, a0, (a1) -; RV64IA-NEXT: ret -; RV64IA-NEXT: .LBB63_2: # %else +; RV64IA-NEXT: bnez a2, .LBB63_4 +; RV64IA-NEXT: # %bb.1: # %else ; RV64IA-NEXT: lw a0, 0(a1) ; RV64IA-NEXT: li a3, 1 ; RV64IA-NEXT: mv a2, a0 -; RV64IA-NEXT: bltu a0, a3, .LBB63_4 -; RV64IA-NEXT: # %bb.3: # %else +; RV64IA-NEXT: bltu a0, a3, .LBB63_3 +; RV64IA-NEXT: # %bb.2: # %else ; RV64IA-NEXT: li a2, 1 -; RV64IA-NEXT: .LBB63_4: # %else +; RV64IA-NEXT: .LBB63_3: # %else ; RV64IA-NEXT: sw a2, 0(a1) +; RV64IA-NEXT: ret +; RV64IA-NEXT: .LBB63_4: # %then +; RV64IA-NEXT: li a0, 1 +; RV64IA-NEXT: amominu.w a0, a0, (a1) ; RV64IA-NEXT: ret br i1 %c, label %then, label %else diff --git a/llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll b/llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll index b2558cde29832..41049195360fc 100644 --- a/llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll @@ -11,20 +11,12 @@ declare bfloat @dummy(bfloat) define void @br_fcmp_false(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-LABEL: br_fcmp_false: ; RV32IZFBFMIN: # %bb.0: -; RV32IZFBFMIN-NEXT: j .LBB0_2 -; RV32IZFBFMIN-NEXT: # %bb.1: # %if.then -; RV32IZFBFMIN-NEXT: ret -; RV32IZFBFMIN-NEXT: .LBB0_2: # %if.else ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_false: ; RV64IZFBFMIN: # %bb.0: -; RV64IZFBFMIN-NEXT: j .LBB0_2 -; RV64IZFBFMIN-NEXT: # %bb.1: # %if.then -; RV64IZFBFMIN-NEXT: ret -; RV64IZFBFMIN-NEXT: .LBB0_2: # %if.else ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFBFMIN-NEXT: call abort @@ -581,20 +573,12 @@ if.then: define void @br_fcmp_true(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-LABEL: br_fcmp_true: ; RV32IZFBFMIN: # %bb.0: -; RV32IZFBFMIN-NEXT: j .LBB16_2 -; RV32IZFBFMIN-NEXT: # %bb.1: # %if.else -; RV32IZFBFMIN-NEXT: ret -; RV32IZFBFMIN-NEXT: .LBB16_2: # %if.then ; RV32IZFBFMIN-NEXT: addi sp, sp, -16 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFBFMIN-NEXT: call abort ; ; RV64IZFBFMIN-LABEL: br_fcmp_true: ; RV64IZFBFMIN: # %bb.0: -; RV64IZFBFMIN-NEXT: j .LBB16_2 -; RV64IZFBFMIN-NEXT: # %bb.1: # %if.else -; RV64IZFBFMIN-NEXT: ret -; RV64IZFBFMIN-NEXT: .LBB16_2: # %if.then ; RV64IZFBFMIN-NEXT: addi sp, sp, -16 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFBFMIN-NEXT: call abort diff --git a/llvm/test/CodeGen/RISCV/bittest.ll b/llvm/test/CodeGen/RISCV/bittest.ll index d69ab0550a034..ccc9d30f2ef1b 100644 --- a/llvm/test/CodeGen/RISCV/bittest.ll +++ b/llvm/test/CodeGen/RISCV/bittest.ll @@ -444,93 +444,93 @@ define void @bittest_switch(i32 signext %0) { ; RV32I-LABEL: bittest_switch: ; RV32I: # %bb.0: ; RV32I-NEXT: li a1, 31 -; RV32I-NEXT: bltu a1, a0, .LBB14_3 +; RV32I-NEXT: bltu a1, a0, .LBB14_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: lui a1, 524291 ; RV32I-NEXT: addi a1, a1, 768 ; RV32I-NEXT: srl a0, a1, a0 ; RV32I-NEXT: andi a0, a0, 1 -; RV32I-NEXT: beqz a0, .LBB14_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB14_3: +; RV32I-NEXT: bnez a0, .LBB14_3 +; RV32I-NEXT: .LBB14_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB14_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: bittest_switch: ; RV64I: # %bb.0: ; RV64I-NEXT: li a1, 31 -; RV64I-NEXT: bltu a1, a0, .LBB14_3 +; RV64I-NEXT: bltu a1, a0, .LBB14_2 ; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: lui a1, 2048 ; RV64I-NEXT: addiw a1, a1, 51 ; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: srl a0, a1, a0 ; RV64I-NEXT: andi a0, a0, 1 -; RV64I-NEXT: beqz a0, .LBB14_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB14_3: +; RV64I-NEXT: bnez a0, .LBB14_3 +; RV64I-NEXT: .LBB14_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB14_3: +; RV64I-NEXT: tail bar ; ; RV32ZBS-LABEL: bittest_switch: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: li a1, 31 -; RV32ZBS-NEXT: bltu a1, a0, .LBB14_3 +; RV32ZBS-NEXT: bltu a1, a0, .LBB14_2 ; RV32ZBS-NEXT: # %bb.1: ; RV32ZBS-NEXT: lui a1, 524291 ; RV32ZBS-NEXT: addi a1, a1, 768 ; RV32ZBS-NEXT: bext a0, a1, a0 -; RV32ZBS-NEXT: beqz a0, .LBB14_3 -; RV32ZBS-NEXT: # %bb.2: -; RV32ZBS-NEXT: tail bar -; RV32ZBS-NEXT: .LBB14_3: +; RV32ZBS-NEXT: bnez a0, .LBB14_3 +; RV32ZBS-NEXT: .LBB14_2: ; RV32ZBS-NEXT: ret +; RV32ZBS-NEXT: .LBB14_3: +; RV32ZBS-NEXT: tail bar ; ; RV64ZBS-LABEL: bittest_switch: ; RV64ZBS: # %bb.0: ; RV64ZBS-NEXT: li a1, 31 -; RV64ZBS-NEXT: bltu a1, a0, .LBB14_3 +; RV64ZBS-NEXT: bltu a1, a0, .LBB14_2 ; RV64ZBS-NEXT: # %bb.1: ; RV64ZBS-NEXT: lui a1, 2048 ; RV64ZBS-NEXT: addiw a1, a1, 51 ; RV64ZBS-NEXT: slli a1, a1, 8 ; RV64ZBS-NEXT: bext a0, a1, a0 -; RV64ZBS-NEXT: beqz a0, .LBB14_3 -; RV64ZBS-NEXT: # %bb.2: -; RV64ZBS-NEXT: tail bar -; RV64ZBS-NEXT: .LBB14_3: +; RV64ZBS-NEXT: bnez a0, .LBB14_3 +; RV64ZBS-NEXT: .LBB14_2: ; RV64ZBS-NEXT: ret +; RV64ZBS-NEXT: .LBB14_3: +; RV64ZBS-NEXT: tail bar ; ; RV32XTHEADBS-LABEL: bittest_switch: ; RV32XTHEADBS: # %bb.0: ; RV32XTHEADBS-NEXT: li a1, 31 -; RV32XTHEADBS-NEXT: bltu a1, a0, .LBB14_3 +; RV32XTHEADBS-NEXT: bltu a1, a0, .LBB14_2 ; RV32XTHEADBS-NEXT: # %bb.1: ; RV32XTHEADBS-NEXT: lui a1, 524291 ; RV32XTHEADBS-NEXT: addi a1, a1, 768 ; RV32XTHEADBS-NEXT: srl a0, a1, a0 ; RV32XTHEADBS-NEXT: andi a0, a0, 1 -; RV32XTHEADBS-NEXT: beqz a0, .LBB14_3 -; RV32XTHEADBS-NEXT: # %bb.2: -; RV32XTHEADBS-NEXT: tail bar -; RV32XTHEADBS-NEXT: .LBB14_3: +; RV32XTHEADBS-NEXT: bnez a0, .LBB14_3 +; RV32XTHEADBS-NEXT: .LBB14_2: ; RV32XTHEADBS-NEXT: ret +; RV32XTHEADBS-NEXT: .LBB14_3: +; RV32XTHEADBS-NEXT: tail bar ; ; RV64XTHEADBS-LABEL: bittest_switch: ; RV64XTHEADBS: # %bb.0: ; RV64XTHEADBS-NEXT: li a1, 31 -; RV64XTHEADBS-NEXT: bltu a1, a0, .LBB14_3 +; RV64XTHEADBS-NEXT: bltu a1, a0, .LBB14_2 ; RV64XTHEADBS-NEXT: # %bb.1: ; RV64XTHEADBS-NEXT: lui a1, 2048 ; RV64XTHEADBS-NEXT: addiw a1, a1, 51 ; RV64XTHEADBS-NEXT: slli a1, a1, 8 ; RV64XTHEADBS-NEXT: srl a0, a1, a0 ; RV64XTHEADBS-NEXT: andi a0, a0, 1 -; RV64XTHEADBS-NEXT: beqz a0, .LBB14_3 -; RV64XTHEADBS-NEXT: # %bb.2: -; RV64XTHEADBS-NEXT: tail bar -; RV64XTHEADBS-NEXT: .LBB14_3: +; RV64XTHEADBS-NEXT: bnez a0, .LBB14_3 +; RV64XTHEADBS-NEXT: .LBB14_2: ; RV64XTHEADBS-NEXT: ret +; RV64XTHEADBS-NEXT: .LBB14_3: +; RV64XTHEADBS-NEXT: tail bar switch i32 %0, label %3 [ i32 8, label %2 i32 9, label %2 @@ -1241,11 +1241,11 @@ define void @bit_10_z_branch_i32(i32 signext %0) { ; CHECK-LABEL: bit_10_z_branch_i32: ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1024 -; CHECK-NEXT: bnez a0, .LBB37_2 +; CHECK-NEXT: beqz a0, .LBB37_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar -; CHECK-NEXT: .LBB37_2: ; CHECK-NEXT: ret +; CHECK-NEXT: .LBB37_2: +; CHECK-NEXT: tail bar %2 = and i32 %0, 1024 %3 = icmp eq i32 %2, 0 br i1 %3, label %4, label %5 @@ -1262,11 +1262,11 @@ define void @bit_10_nz_branch_i32(i32 signext %0) { ; CHECK-LABEL: bit_10_nz_branch_i32: ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1024 -; CHECK-NEXT: beqz a0, .LBB38_2 +; CHECK-NEXT: bnez a0, .LBB38_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar -; CHECK-NEXT: .LBB38_2: ; CHECK-NEXT: ret +; CHECK-NEXT: .LBB38_2: +; CHECK-NEXT: tail bar %2 = and i32 %0, 1024 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -1283,20 +1283,20 @@ define void @bit_11_z_branch_i32(i32 signext %0) { ; RV32-LABEL: bit_11_z_branch_i32: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 20 -; RV32-NEXT: bltz a0, .LBB39_2 +; RV32-NEXT: bgez a0, .LBB39_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB39_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB39_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_11_z_branch_i32: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 52 -; RV64-NEXT: bltz a0, .LBB39_2 +; RV64-NEXT: bgez a0, .LBB39_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB39_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB39_2: +; RV64-NEXT: tail bar %2 = and i32 %0, 2048 %3 = icmp eq i32 %2, 0 br i1 %3, label %4, label %5 @@ -1313,20 +1313,20 @@ define void @bit_11_nz_branch_i32(i32 signext %0) { ; RV32-LABEL: bit_11_nz_branch_i32: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 20 -; RV32-NEXT: bgez a0, .LBB40_2 +; RV32-NEXT: bltz a0, .LBB40_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB40_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB40_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_11_nz_branch_i32: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 52 -; RV64-NEXT: bgez a0, .LBB40_2 +; RV64-NEXT: bltz a0, .LBB40_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB40_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB40_2: +; RV64-NEXT: tail bar %2 = and i32 %0, 2048 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -1343,20 +1343,20 @@ define void @bit_24_z_branch_i32(i32 signext %0) { ; RV32-LABEL: bit_24_z_branch_i32: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 7 -; RV32-NEXT: bltz a0, .LBB41_2 +; RV32-NEXT: bgez a0, .LBB41_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB41_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB41_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_24_z_branch_i32: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 39 -; RV64-NEXT: bltz a0, .LBB41_2 +; RV64-NEXT: bgez a0, .LBB41_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB41_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB41_2: +; RV64-NEXT: tail bar %2 = and i32 %0, 16777216 %3 = icmp eq i32 %2, 0 br i1 %3, label %4, label %5 @@ -1373,20 +1373,20 @@ define void @bit_24_nz_branch_i32(i32 signext %0) { ; RV32-LABEL: bit_24_nz_branch_i32: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 7 -; RV32-NEXT: bgez a0, .LBB42_2 +; RV32-NEXT: bltz a0, .LBB42_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB42_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB42_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_24_nz_branch_i32: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 39 -; RV64-NEXT: bgez a0, .LBB42_2 +; RV64-NEXT: bltz a0, .LBB42_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB42_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB42_2: +; RV64-NEXT: tail bar %2 = and i32 %0, 16777216 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -1402,21 +1402,21 @@ define void @bit_24_nz_branch_i32(i32 signext %0) { define void @bit_31_z_branch_i32(i32 signext %0) { ; RV32-LABEL: bit_31_z_branch_i32: ; RV32: # %bb.0: -; RV32-NEXT: bltz a0, .LBB43_2 +; RV32-NEXT: bgez a0, .LBB43_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB43_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB43_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_31_z_branch_i32: ; RV64: # %bb.0: ; RV64-NEXT: lui a1, 524288 ; RV64-NEXT: and a0, a0, a1 -; RV64-NEXT: bnez a0, .LBB43_2 +; RV64-NEXT: beqz a0, .LBB43_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB43_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB43_2: +; RV64-NEXT: tail bar %2 = and i32 %0, 2147483648 %3 = icmp eq i32 %2, 0 br i1 %3, label %4, label %5 @@ -1432,21 +1432,21 @@ define void @bit_31_z_branch_i32(i32 signext %0) { define void @bit_31_nz_branch_i32(i32 signext %0) { ; RV32-LABEL: bit_31_nz_branch_i32: ; RV32: # %bb.0: -; RV32-NEXT: bgez a0, .LBB44_2 +; RV32-NEXT: bltz a0, .LBB44_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB44_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB44_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_31_nz_branch_i32: ; RV64: # %bb.0: ; RV64-NEXT: lui a1, 524288 ; RV64-NEXT: and a0, a0, a1 -; RV64-NEXT: beqz a0, .LBB44_2 +; RV64-NEXT: bnez a0, .LBB44_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB44_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB44_2: +; RV64-NEXT: tail bar %2 = and i32 %0, 2147483648 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -1463,11 +1463,11 @@ define void @bit_10_z_branch_i64(i64 %0) { ; CHECK-LABEL: bit_10_z_branch_i64: ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1024 -; CHECK-NEXT: bnez a0, .LBB45_2 +; CHECK-NEXT: beqz a0, .LBB45_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar -; CHECK-NEXT: .LBB45_2: ; CHECK-NEXT: ret +; CHECK-NEXT: .LBB45_2: +; CHECK-NEXT: tail bar %2 = and i64 %0, 1024 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -1484,11 +1484,11 @@ define void @bit_10_nz_branch_i64(i64 %0) { ; CHECK-LABEL: bit_10_nz_branch_i64: ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1024 -; CHECK-NEXT: beqz a0, .LBB46_2 +; CHECK-NEXT: bnez a0, .LBB46_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar -; CHECK-NEXT: .LBB46_2: ; CHECK-NEXT: ret +; CHECK-NEXT: .LBB46_2: +; CHECK-NEXT: tail bar %2 = and i64 %0, 1024 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -1505,20 +1505,20 @@ define void @bit_11_z_branch_i64(i64 %0) { ; RV32-LABEL: bit_11_z_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 20 -; RV32-NEXT: bltz a0, .LBB47_2 +; RV32-NEXT: bgez a0, .LBB47_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB47_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB47_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_11_z_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 52 -; RV64-NEXT: bltz a0, .LBB47_2 +; RV64-NEXT: bgez a0, .LBB47_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB47_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB47_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 2048 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -1535,20 +1535,20 @@ define void @bit_11_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_11_nz_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 20 -; RV32-NEXT: bgez a0, .LBB48_2 +; RV32-NEXT: bltz a0, .LBB48_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB48_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB48_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_11_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 52 -; RV64-NEXT: bgez a0, .LBB48_2 +; RV64-NEXT: bltz a0, .LBB48_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB48_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB48_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 2048 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -1565,20 +1565,20 @@ define void @bit_24_z_branch_i64(i64 %0) { ; RV32-LABEL: bit_24_z_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 7 -; RV32-NEXT: bltz a0, .LBB49_2 +; RV32-NEXT: bgez a0, .LBB49_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB49_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB49_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_24_z_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 39 -; RV64-NEXT: bltz a0, .LBB49_2 +; RV64-NEXT: bgez a0, .LBB49_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB49_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB49_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 16777216 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -1595,20 +1595,20 @@ define void @bit_24_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_24_nz_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 7 -; RV32-NEXT: bgez a0, .LBB50_2 +; RV32-NEXT: bltz a0, .LBB50_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB50_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB50_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_24_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 39 -; RV64-NEXT: bgez a0, .LBB50_2 +; RV64-NEXT: bltz a0, .LBB50_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB50_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB50_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 16777216 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -1624,20 +1624,20 @@ define void @bit_24_nz_branch_i64(i64 %0) { define void @bit_31_z_branch_i64(i64 %0) { ; RV32-LABEL: bit_31_z_branch_i64: ; RV32: # %bb.0: -; RV32-NEXT: bltz a0, .LBB51_2 +; RV32-NEXT: bgez a0, .LBB51_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB51_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB51_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_31_z_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 32 -; RV64-NEXT: bltz a0, .LBB51_2 +; RV64-NEXT: bgez a0, .LBB51_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB51_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB51_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 2147483648 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -1653,20 +1653,20 @@ define void @bit_31_z_branch_i64(i64 %0) { define void @bit_31_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_31_nz_branch_i64: ; RV32: # %bb.0: -; RV32-NEXT: bgez a0, .LBB52_2 +; RV32-NEXT: bltz a0, .LBB52_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB52_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB52_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_31_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 32 -; RV64-NEXT: bgez a0, .LBB52_2 +; RV64-NEXT: bltz a0, .LBB52_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB52_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB52_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 2147483648 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -1683,20 +1683,20 @@ define void @bit_32_z_branch_i64(i64 %0) { ; RV32-LABEL: bit_32_z_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: andi a1, a1, 1 -; RV32-NEXT: bnez a1, .LBB53_2 +; RV32-NEXT: beqz a1, .LBB53_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB53_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB53_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_32_z_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 31 -; RV64-NEXT: bltz a0, .LBB53_2 +; RV64-NEXT: bgez a0, .LBB53_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB53_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB53_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 4294967296 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -1713,20 +1713,20 @@ define void @bit_32_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_32_nz_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: andi a1, a1, 1 -; RV32-NEXT: beqz a1, .LBB54_2 +; RV32-NEXT: bnez a1, .LBB54_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB54_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB54_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_32_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 31 -; RV64-NEXT: bgez a0, .LBB54_2 +; RV64-NEXT: bltz a0, .LBB54_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB54_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB54_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 4294967296 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -1743,20 +1743,20 @@ define void @bit_62_z_branch_i64(i64 %0) { ; RV32-LABEL: bit_62_z_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: slli a1, a1, 1 -; RV32-NEXT: bltz a1, .LBB55_2 +; RV32-NEXT: bgez a1, .LBB55_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB55_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB55_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_62_z_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 1 -; RV64-NEXT: bltz a0, .LBB55_2 +; RV64-NEXT: bgez a0, .LBB55_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB55_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB55_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 4611686018427387904 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -1773,20 +1773,20 @@ define void @bit_62_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_62_nz_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: slli a1, a1, 1 -; RV32-NEXT: bgez a1, .LBB56_2 +; RV32-NEXT: bltz a1, .LBB56_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB56_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB56_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_62_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 1 -; RV64-NEXT: bgez a0, .LBB56_2 +; RV64-NEXT: bltz a0, .LBB56_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB56_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB56_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 4611686018427387904 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -1802,19 +1802,19 @@ define void @bit_62_nz_branch_i64(i64 %0) { define void @bit_63_z_branch_i64(i64 %0) { ; RV32-LABEL: bit_63_z_branch_i64: ; RV32: # %bb.0: -; RV32-NEXT: bltz a1, .LBB57_2 +; RV32-NEXT: bgez a1, .LBB57_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB57_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB57_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_63_z_branch_i64: ; RV64: # %bb.0: -; RV64-NEXT: bltz a0, .LBB57_2 +; RV64-NEXT: bgez a0, .LBB57_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB57_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB57_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 9223372036854775808 %3 = icmp eq i64 %2, 0 br i1 %3, label %4, label %5 @@ -1830,19 +1830,19 @@ define void @bit_63_z_branch_i64(i64 %0) { define void @bit_63_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_63_nz_branch_i64: ; RV32: # %bb.0: -; RV32-NEXT: bgez a1, .LBB58_2 +; RV32-NEXT: bltz a1, .LBB58_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB58_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB58_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_63_nz_branch_i64: ; RV64: # %bb.0: -; RV64-NEXT: bgez a0, .LBB58_2 +; RV64-NEXT: bltz a0, .LBB58_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB58_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB58_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 9223372036854775808 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -2692,11 +2692,11 @@ define void @bit_10_1_nz_branch_i32(i32 signext %0) { ; CHECK-LABEL: bit_10_1_nz_branch_i32: ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1023 -; CHECK-NEXT: beqz a0, .LBB90_2 +; CHECK-NEXT: bnez a0, .LBB90_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar -; CHECK-NEXT: .LBB90_2: ; CHECK-NEXT: ret +; CHECK-NEXT: .LBB90_2: +; CHECK-NEXT: tail bar %2 = and i32 %0, 1023 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -2734,11 +2734,11 @@ define void @bit_11_1_nz_branch_i32(i32 signext %0) { ; CHECK-LABEL: bit_11_1_nz_branch_i32: ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 2047 -; CHECK-NEXT: beqz a0, .LBB92_2 +; CHECK-NEXT: bnez a0, .LBB92_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar -; CHECK-NEXT: .LBB92_2: ; CHECK-NEXT: ret +; CHECK-NEXT: .LBB92_2: +; CHECK-NEXT: tail bar %2 = and i32 %0, 2047 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -2785,20 +2785,20 @@ define void @bit_16_1_nz_branch_i32(i32 signext %0) { ; RV32-LABEL: bit_16_1_nz_branch_i32: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 16 -; RV32-NEXT: beqz a0, .LBB94_2 +; RV32-NEXT: bnez a0, .LBB94_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB94_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB94_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_16_1_nz_branch_i32: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 48 -; RV64-NEXT: beqz a0, .LBB94_2 +; RV64-NEXT: bnez a0, .LBB94_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB94_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB94_2: +; RV64-NEXT: tail bar %2 = and i32 %0, 65535 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -2845,20 +2845,20 @@ define void @bit_24_1_nz_branch_i32(i32 signext %0) { ; RV32-LABEL: bit_24_1_nz_branch_i32: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 8 -; RV32-NEXT: beqz a0, .LBB96_2 +; RV32-NEXT: bnez a0, .LBB96_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB96_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB96_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_24_1_nz_branch_i32: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 40 -; RV64-NEXT: beqz a0, .LBB96_2 +; RV64-NEXT: bnez a0, .LBB96_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB96_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB96_2: +; RV64-NEXT: tail bar %2 = and i32 %0, 16777215 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -2905,20 +2905,20 @@ define void @bit_31_1_nz_branch_i32(i32 signext %0) { ; RV32-LABEL: bit_31_1_nz_branch_i32: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 1 -; RV32-NEXT: beqz a0, .LBB98_2 +; RV32-NEXT: bnez a0, .LBB98_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB98_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB98_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_31_1_nz_branch_i32: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 33 -; RV64-NEXT: beqz a0, .LBB98_2 +; RV64-NEXT: bnez a0, .LBB98_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB98_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB98_2: +; RV64-NEXT: tail bar %2 = and i32 %0, 2147483647 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -2954,11 +2954,11 @@ define void @bit_32_1_z_branch_i32(i32 signext %0) { define void @bit_32_1_nz_branch_i32(i32 signext %0) { ; CHECK-LABEL: bit_32_1_nz_branch_i32: ; CHECK: # %bb.0: -; CHECK-NEXT: beqz a0, .LBB100_2 +; CHECK-NEXT: bnez a0, .LBB100_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar -; CHECK-NEXT: .LBB100_2: ; CHECK-NEXT: ret +; CHECK-NEXT: .LBB100_2: +; CHECK-NEXT: tail bar %2 = and i32 %0, 4294967295 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -2997,11 +2997,11 @@ define void @bit_10_1_nz_branch_i64(i64 %0) { ; CHECK-LABEL: bit_10_1_nz_branch_i64: ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 1023 -; CHECK-NEXT: beqz a0, .LBB102_2 +; CHECK-NEXT: bnez a0, .LBB102_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar -; CHECK-NEXT: .LBB102_2: ; CHECK-NEXT: ret +; CHECK-NEXT: .LBB102_2: +; CHECK-NEXT: tail bar %2 = and i64 %0, 1023 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -3039,11 +3039,11 @@ define void @bit_11_1_nz_branch_i64(i64 %0) { ; CHECK-LABEL: bit_11_1_nz_branch_i64: ; CHECK: # %bb.0: ; CHECK-NEXT: andi a0, a0, 2047 -; CHECK-NEXT: beqz a0, .LBB104_2 +; CHECK-NEXT: bnez a0, .LBB104_2 ; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: tail bar -; CHECK-NEXT: .LBB104_2: ; CHECK-NEXT: ret +; CHECK-NEXT: .LBB104_2: +; CHECK-NEXT: tail bar %2 = and i64 %0, 2047 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -3090,20 +3090,20 @@ define void @bit_16_1_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_16_1_nz_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 16 -; RV32-NEXT: beqz a0, .LBB106_2 +; RV32-NEXT: bnez a0, .LBB106_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB106_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB106_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_16_1_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 48 -; RV64-NEXT: beqz a0, .LBB106_2 +; RV64-NEXT: bnez a0, .LBB106_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB106_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB106_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 65535 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -3150,20 +3150,20 @@ define void @bit_24_1_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_24_1_nz_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 8 -; RV32-NEXT: beqz a0, .LBB108_2 +; RV32-NEXT: bnez a0, .LBB108_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB108_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB108_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_24_1_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 40 -; RV64-NEXT: beqz a0, .LBB108_2 +; RV64-NEXT: bnez a0, .LBB108_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB108_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB108_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 16777215 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -3210,20 +3210,20 @@ define void @bit_31_1_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_31_1_nz_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: slli a0, a0, 1 -; RV32-NEXT: beqz a0, .LBB110_2 +; RV32-NEXT: bnez a0, .LBB110_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB110_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB110_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_31_1_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 33 -; RV64-NEXT: beqz a0, .LBB110_2 +; RV64-NEXT: bnez a0, .LBB110_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB110_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB110_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 2147483647 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -3268,20 +3268,20 @@ define void @bit_32_1_z_branch_i64(i64 %0) { define void @bit_32_1_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_32_1_nz_branch_i64: ; RV32: # %bb.0: -; RV32-NEXT: beqz a0, .LBB112_2 +; RV32-NEXT: bnez a0, .LBB112_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB112_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB112_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_32_1_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: sext.w a0, a0 -; RV64-NEXT: beqz a0, .LBB112_2 +; RV64-NEXT: bnez a0, .LBB112_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB112_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB112_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 4294967295 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -3332,20 +3332,20 @@ define void @bit_62_1_nz_branch_i64(i64 %0) { ; RV32-NEXT: slli a1, a1, 2 ; RV32-NEXT: srli a1, a1, 2 ; RV32-NEXT: or a0, a0, a1 -; RV32-NEXT: beqz a0, .LBB114_2 +; RV32-NEXT: bnez a0, .LBB114_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB114_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB114_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_62_1_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 2 -; RV64-NEXT: beqz a0, .LBB114_2 +; RV64-NEXT: bnez a0, .LBB114_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB114_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB114_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 4611686018427387903 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -3417,41 +3417,41 @@ define void @bit_63_1_nz_branch_i64(i64 %0) { ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: beqz a0, .LBB116_2 +; RV32I-NEXT: bnez a0, .LBB116_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB116_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB116_2: +; RV32I-NEXT: tail bar ; ; RV64-LABEL: bit_63_1_nz_branch_i64: ; RV64: # %bb.0: ; RV64-NEXT: slli a0, a0, 1 -; RV64-NEXT: beqz a0, .LBB116_2 +; RV64-NEXT: bnez a0, .LBB116_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB116_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB116_2: +; RV64-NEXT: tail bar ; ; RV32ZBS-LABEL: bit_63_1_nz_branch_i64: ; RV32ZBS: # %bb.0: ; RV32ZBS-NEXT: bclri a1, a1, 31 ; RV32ZBS-NEXT: or a0, a0, a1 -; RV32ZBS-NEXT: beqz a0, .LBB116_2 +; RV32ZBS-NEXT: bnez a0, .LBB116_2 ; RV32ZBS-NEXT: # %bb.1: -; RV32ZBS-NEXT: tail bar -; RV32ZBS-NEXT: .LBB116_2: ; RV32ZBS-NEXT: ret +; RV32ZBS-NEXT: .LBB116_2: +; RV32ZBS-NEXT: tail bar ; ; RV32XTHEADBS-LABEL: bit_63_1_nz_branch_i64: ; RV32XTHEADBS: # %bb.0: ; RV32XTHEADBS-NEXT: slli a1, a1, 1 ; RV32XTHEADBS-NEXT: srli a1, a1, 1 ; RV32XTHEADBS-NEXT: or a0, a0, a1 -; RV32XTHEADBS-NEXT: beqz a0, .LBB116_2 +; RV32XTHEADBS-NEXT: bnez a0, .LBB116_2 ; RV32XTHEADBS-NEXT: # %bb.1: -; RV32XTHEADBS-NEXT: tail bar -; RV32XTHEADBS-NEXT: .LBB116_2: ; RV32XTHEADBS-NEXT: ret +; RV32XTHEADBS-NEXT: .LBB116_2: +; RV32XTHEADBS-NEXT: tail bar %2 = and i64 %0, 9223372036854775807 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 @@ -3497,19 +3497,19 @@ define void @bit_64_1_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_64_1_nz_branch_i64: ; RV32: # %bb.0: ; RV32-NEXT: or a0, a0, a1 -; RV32-NEXT: beqz a0, .LBB118_2 +; RV32-NEXT: bnez a0, .LBB118_2 ; RV32-NEXT: # %bb.1: -; RV32-NEXT: tail bar -; RV32-NEXT: .LBB118_2: ; RV32-NEXT: ret +; RV32-NEXT: .LBB118_2: +; RV32-NEXT: tail bar ; ; RV64-LABEL: bit_64_1_nz_branch_i64: ; RV64: # %bb.0: -; RV64-NEXT: beqz a0, .LBB118_2 +; RV64-NEXT: bnez a0, .LBB118_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar -; RV64-NEXT: .LBB118_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB118_2: +; RV64-NEXT: tail bar %2 = and i64 %0, 18446744073709551615 %3 = icmp ne i64 %2, 0 br i1 %3, label %4, label %5 diff --git a/llvm/test/CodeGen/RISCV/branch_zero.ll b/llvm/test/CodeGen/RISCV/branch_zero.ll index 9f96f0d94a27a..93b99a8683d0c 100644 --- a/llvm/test/CodeGen/RISCV/branch_zero.ll +++ b/llvm/test/CodeGen/RISCV/branch_zero.ll @@ -5,13 +5,12 @@ define void @foo(i16 %finder_idx) { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # %bb.1: # %for.body ; CHECK-NEXT: slli a0, a0, 48 -; CHECK-NEXT: bltz a0, .LBB0_4 -; CHECK-NEXT: # %bb.2: # %while.cond.preheader.i +; CHECK-NEXT: bltz a0, .LBB0_3 +; CHECK-NEXT: # %bb.1: # %while.cond.preheader.i ; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: # %bb.3: # %while.body -; CHECK-NEXT: .LBB0_4: # %while.cond1.preheader.i +; CHECK-NEXT: # %bb.2: # %while.body +; CHECK-NEXT: .LBB0_3: # %while.cond1.preheader.i entry: br label %for.body @@ -43,13 +42,12 @@ if.then: define void @bar(i16 %finder_idx) { ; CHECK-LABEL: bar: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: # %bb.1: # %for.body ; CHECK-NEXT: slli a0, a0, 48 -; CHECK-NEXT: bgez a0, .LBB1_4 -; CHECK-NEXT: # %bb.2: # %while.cond.preheader.i +; CHECK-NEXT: bgez a0, .LBB1_3 +; CHECK-NEXT: # %bb.1: # %while.cond.preheader.i ; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: # %bb.3: # %while.body -; CHECK-NEXT: .LBB1_4: # %while.cond1.preheader.i +; CHECK-NEXT: # %bb.2: # %while.body +; CHECK-NEXT: .LBB1_3: # %while.cond1.preheader.i entry: br label %for.body diff --git a/llvm/test/CodeGen/RISCV/cmp-bool.ll b/llvm/test/CodeGen/RISCV/cmp-bool.ll index 547e12cce0a06..a4247bf37cf5c 100644 --- a/llvm/test/CodeGen/RISCV/cmp-bool.ll +++ b/llvm/test/CodeGen/RISCV/cmp-bool.ll @@ -33,19 +33,19 @@ if.end: define void @bool_ne(i1 zeroext %a, i1 zeroext %b, ptr nocapture %c) nounwind { ; RV32-LABEL: bool_ne: ; RV32: # %bb.0: # %entry -; RV32-NEXT: beq a0, a1, .LBB1_2 -; RV32-NEXT: # %bb.1: # %if.then -; RV32-NEXT: jr a2 -; RV32-NEXT: .LBB1_2: # %if.end +; RV32-NEXT: bne a0, a1, .LBB1_2 +; RV32-NEXT: # %bb.1: # %if.end ; RV32-NEXT: ret +; RV32-NEXT: .LBB1_2: # %if.then +; RV32-NEXT: jr a2 ; ; RV64-LABEL: bool_ne: ; RV64: # %bb.0: # %entry -; RV64-NEXT: beq a0, a1, .LBB1_2 -; RV64-NEXT: # %bb.1: # %if.then -; RV64-NEXT: jr a2 -; RV64-NEXT: .LBB1_2: # %if.end +; RV64-NEXT: bne a0, a1, .LBB1_2 +; RV64-NEXT: # %bb.1: # %if.end ; RV64-NEXT: ret +; RV64-NEXT: .LBB1_2: # %if.then +; RV64-NEXT: jr a2 entry: %cmp = xor i1 %a, %b br i1 %cmp, label %if.then, label %if.end diff --git a/llvm/test/CodeGen/RISCV/csr-first-use-cost.ll b/llvm/test/CodeGen/RISCV/csr-first-use-cost.ll index 7a14a6ca30961..cc8e899185520 100644 --- a/llvm/test/CodeGen/RISCV/csr-first-use-cost.ll +++ b/llvm/test/CodeGen/RISCV/csr-first-use-cost.ll @@ -13,28 +13,22 @@ define fastcc void @Perl_sv_setnv(i8 %c, ptr %.str.54.3682) nounwind { ; ZERO-COST-NEXT: li a2, 2 ; ZERO-COST-NEXT: blt a2, a0, .LBB0_3 ; ZERO-COST-NEXT: # %bb.1: # %entry -; ZERO-COST-NEXT: beqz a0, .LBB0_4 +; ZERO-COST-NEXT: beqz a0, .LBB0_7 ; ZERO-COST-NEXT: # %bb.2: # %entry ; ZERO-COST-NEXT: mv s0, a1 ; ZERO-COST-NEXT: li a1, 1 -; ZERO-COST-NEXT: beq a0, a1, .LBB0_6 -; ZERO-COST-NEXT: j .LBB0_7 +; ZERO-COST-NEXT: beq a0, a1, .LBB0_5 +; ZERO-COST-NEXT: j .LBB0_6 ; ZERO-COST-NEXT: .LBB0_3: # %entry ; ZERO-COST-NEXT: li a2, 3 -; ZERO-COST-NEXT: bne a0, a2, .LBB0_5 -; ZERO-COST-NEXT: .LBB0_4: # %sw.bb3 -; ZERO-COST-NEXT: ld ra, 24(sp) # 8-byte Folded Reload -; ZERO-COST-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; ZERO-COST-NEXT: ld s1, 8(sp) # 8-byte Folded Reload -; ZERO-COST-NEXT: addi sp, sp, 32 -; ZERO-COST-NEXT: ret -; ZERO-COST-NEXT: .LBB0_5: # %entry +; ZERO-COST-NEXT: beq a0, a2, .LBB0_7 +; ZERO-COST-NEXT: # %bb.4: # %entry ; ZERO-COST-NEXT: mv s0, a1 ; ZERO-COST-NEXT: li a1, 12 -; ZERO-COST-NEXT: bne a0, a1, .LBB0_7 -; ZERO-COST-NEXT: .LBB0_6: # %sw.bb34.i +; ZERO-COST-NEXT: bne a0, a1, .LBB0_6 +; ZERO-COST-NEXT: .LBB0_5: # %sw.bb34.i ; ZERO-COST-NEXT: li s0, 0 -; ZERO-COST-NEXT: .LBB0_7: # %Perl_sv_reftype.exit +; ZERO-COST-NEXT: .LBB0_6: # %Perl_sv_reftype.exit ; ZERO-COST-NEXT: li s1, 0 ; ZERO-COST-NEXT: li a0, 0 ; ZERO-COST-NEXT: li a1, 0 @@ -43,6 +37,12 @@ define fastcc void @Perl_sv_setnv(i8 %c, ptr %.str.54.3682) nounwind { ; ZERO-COST-NEXT: mv a1, s0 ; ZERO-COST-NEXT: li a2, 0 ; ZERO-COST-NEXT: jalr s1 +; ZERO-COST-NEXT: .LBB0_7: # %sw.bb3 +; ZERO-COST-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; ZERO-COST-NEXT: ld s0, 16(sp) # 8-byte Folded Reload +; ZERO-COST-NEXT: ld s1, 8(sp) # 8-byte Folded Reload +; ZERO-COST-NEXT: addi sp, sp, 32 +; ZERO-COST-NEXT: ret ; ; DEFAULT-COST-LABEL: Perl_sv_setnv: ; DEFAULT-COST: # %bb.0: # %entry @@ -53,27 +53,22 @@ define fastcc void @Perl_sv_setnv(i8 %c, ptr %.str.54.3682) nounwind { ; DEFAULT-COST-NEXT: li a2, 2 ; DEFAULT-COST-NEXT: blt a2, a0, .LBB0_3 ; DEFAULT-COST-NEXT: # %bb.1: # %entry -; DEFAULT-COST-NEXT: beqz a0, .LBB0_4 +; DEFAULT-COST-NEXT: beqz a0, .LBB0_7 ; DEFAULT-COST-NEXT: # %bb.2: # %entry ; DEFAULT-COST-NEXT: sd a1, 8(sp) # 8-byte Folded Spill ; DEFAULT-COST-NEXT: li a1, 1 -; DEFAULT-COST-NEXT: beq a0, a1, .LBB0_6 -; DEFAULT-COST-NEXT: j .LBB0_7 +; DEFAULT-COST-NEXT: beq a0, a1, .LBB0_5 +; DEFAULT-COST-NEXT: j .LBB0_6 ; DEFAULT-COST-NEXT: .LBB0_3: # %entry ; DEFAULT-COST-NEXT: li a2, 3 -; DEFAULT-COST-NEXT: bne a0, a2, .LBB0_5 -; DEFAULT-COST-NEXT: .LBB0_4: # %sw.bb3 -; DEFAULT-COST-NEXT: ld ra, 24(sp) # 8-byte Folded Reload -; DEFAULT-COST-NEXT: ld s0, 16(sp) # 8-byte Folded Reload -; DEFAULT-COST-NEXT: addi sp, sp, 32 -; DEFAULT-COST-NEXT: ret -; DEFAULT-COST-NEXT: .LBB0_5: # %entry +; DEFAULT-COST-NEXT: beq a0, a2, .LBB0_7 +; DEFAULT-COST-NEXT: # %bb.4: # %entry ; DEFAULT-COST-NEXT: sd a1, 8(sp) # 8-byte Folded Spill ; DEFAULT-COST-NEXT: li a1, 12 -; DEFAULT-COST-NEXT: bne a0, a1, .LBB0_7 -; DEFAULT-COST-NEXT: .LBB0_6: # %sw.bb34.i +; DEFAULT-COST-NEXT: bne a0, a1, .LBB0_6 +; DEFAULT-COST-NEXT: .LBB0_5: # %sw.bb34.i ; DEFAULT-COST-NEXT: sd zero, 8(sp) # 8-byte Folded Spill -; DEFAULT-COST-NEXT: .LBB0_7: # %Perl_sv_reftype.exit +; DEFAULT-COST-NEXT: .LBB0_6: # %Perl_sv_reftype.exit ; DEFAULT-COST-NEXT: li s0, 0 ; DEFAULT-COST-NEXT: li a0, 0 ; DEFAULT-COST-NEXT: li a1, 0 @@ -82,6 +77,11 @@ define fastcc void @Perl_sv_setnv(i8 %c, ptr %.str.54.3682) nounwind { ; DEFAULT-COST-NEXT: ld a1, 8(sp) # 8-byte Folded Reload ; DEFAULT-COST-NEXT: li a2, 0 ; DEFAULT-COST-NEXT: jalr s0 +; DEFAULT-COST-NEXT: .LBB0_7: # %sw.bb3 +; DEFAULT-COST-NEXT: ld ra, 24(sp) # 8-byte Folded Reload +; DEFAULT-COST-NEXT: ld s0, 16(sp) # 8-byte Folded Reload +; DEFAULT-COST-NEXT: addi sp, sp, 32 +; DEFAULT-COST-NEXT: ret entry: switch i8 %c, label %Perl_sv_reftype.exit [ i8 1, label %sw.bb4 diff --git a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll index b2c882878f8bc..bea51fc4322d0 100644 --- a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll @@ -14,40 +14,24 @@ declare void @exit(i32) define void @br_fcmp_false(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_false: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: j .LBB0_2 -; RV32IFD-NEXT: # %bb.1: # %if.then -; RV32IFD-NEXT: ret -; RV32IFD-NEXT: .LBB0_2: # %if.else ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_false: ; RV64IFD: # %bb.0: -; RV64IFD-NEXT: j .LBB0_2 -; RV64IFD-NEXT: # %bb.1: # %if.then -; RV64IFD-NEXT: ret -; RV64IFD-NEXT: .LBB0_2: # %if.else ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_false: ; RV32IZFINXZDINX: # %bb.0: -; RV32IZFINXZDINX-NEXT: j .LBB0_2 -; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.then -; RV32IZFINXZDINX-NEXT: ret -; RV32IZFINXZDINX-NEXT: .LBB0_2: # %if.else ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_false: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: j .LBB0_2 -; RV64IZFINXZDINX-NEXT: # %bb.1: # %if.then -; RV64IZFINXZDINX-NEXT: ret -; RV64IZFINXZDINX-NEXT: .LBB0_2: # %if.else ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: call abort @@ -893,40 +877,24 @@ if.then: define void @br_fcmp_true(double %a, double %b) nounwind { ; RV32IFD-LABEL: br_fcmp_true: ; RV32IFD: # %bb.0: -; RV32IFD-NEXT: j .LBB16_2 -; RV32IFD-NEXT: # %bb.1: # %if.else -; RV32IFD-NEXT: ret -; RV32IFD-NEXT: .LBB16_2: # %if.then ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: call abort ; ; RV64IFD-LABEL: br_fcmp_true: ; RV64IFD: # %bb.0: -; RV64IFD-NEXT: j .LBB16_2 -; RV64IFD-NEXT: # %bb.1: # %if.else -; RV64IFD-NEXT: ret -; RV64IFD-NEXT: .LBB16_2: # %if.then ; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: call abort ; ; RV32IZFINXZDINX-LABEL: br_fcmp_true: ; RV32IZFINXZDINX: # %bb.0: -; RV32IZFINXZDINX-NEXT: j .LBB16_2 -; RV32IZFINXZDINX-NEXT: # %bb.1: # %if.else -; RV32IZFINXZDINX-NEXT: ret -; RV32IZFINXZDINX-NEXT: .LBB16_2: # %if.then ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call abort ; ; RV64IZFINXZDINX-LABEL: br_fcmp_true: ; RV64IZFINXZDINX: # %bb.0: -; RV64IZFINXZDINX-NEXT: j .LBB16_2 -; RV64IZFINXZDINX-NEXT: # %bb.1: # %if.else -; RV64IZFINXZDINX-NEXT: ret -; RV64IZFINXZDINX-NEXT: .LBB16_2: # %if.then ; RV64IZFINXZDINX-NEXT: addi sp, sp, -16 ; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINXZDINX-NEXT: call abort diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll index b2892115cac7a..c4f23f251c535 100644 --- a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll @@ -15,40 +15,24 @@ declare float @dummy(float) define void @br_fcmp_false(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_false: ; RV32IF: # %bb.0: -; RV32IF-NEXT: j .LBB0_2 -; RV32IF-NEXT: # %bb.1: # %if.then -; RV32IF-NEXT: ret -; RV32IF-NEXT: .LBB0_2: # %if.else ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_false: ; RV64IF: # %bb.0: -; RV64IF-NEXT: j .LBB0_2 -; RV64IF-NEXT: # %bb.1: # %if.then -; RV64IF-NEXT: ret -; RV64IF-NEXT: .LBB0_2: # %if.else ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_false: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: j .LBB0_2 -; RV32IZFINX-NEXT: # %bb.1: # %if.then -; RV32IZFINX-NEXT: ret -; RV32IZFINX-NEXT: .LBB0_2: # %if.else ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_false: ; RV64IZFINX: # %bb.0: -; RV64IZFINX-NEXT: j .LBB0_2 -; RV64IZFINX-NEXT: # %bb.1: # %if.then -; RV64IZFINX-NEXT: ret -; RV64IZFINX-NEXT: .LBB0_2: # %if.else ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINX-NEXT: call abort @@ -894,40 +878,24 @@ if.then: define void @br_fcmp_true(float %a, float %b) nounwind { ; RV32IF-LABEL: br_fcmp_true: ; RV32IF: # %bb.0: -; RV32IF-NEXT: j .LBB16_2 -; RV32IF-NEXT: # %bb.1: # %if.else -; RV32IF-NEXT: ret -; RV32IF-NEXT: .LBB16_2: # %if.then ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: call abort ; ; RV64IF-LABEL: br_fcmp_true: ; RV64IF: # %bb.0: -; RV64IF-NEXT: j .LBB16_2 -; RV64IF-NEXT: # %bb.1: # %if.else -; RV64IF-NEXT: ret -; RV64IF-NEXT: .LBB16_2: # %if.then ; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: call abort ; ; RV32IZFINX-LABEL: br_fcmp_true: ; RV32IZFINX: # %bb.0: -; RV32IZFINX-NEXT: j .LBB16_2 -; RV32IZFINX-NEXT: # %bb.1: # %if.else -; RV32IZFINX-NEXT: ret -; RV32IZFINX-NEXT: .LBB16_2: # %if.then ; RV32IZFINX-NEXT: addi sp, sp, -16 ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: call abort ; ; RV64IZFINX-LABEL: br_fcmp_true: ; RV64IZFINX: # %bb.0: -; RV64IZFINX-NEXT: j .LBB16_2 -; RV64IZFINX-NEXT: # %bb.1: # %if.else -; RV64IZFINX-NEXT: ret -; RV64IZFINX-NEXT: .LBB16_2: # %if.then ; RV64IZFINX-NEXT: addi sp, sp, -16 ; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFINX-NEXT: call abort diff --git a/llvm/test/CodeGen/RISCV/frame-info.ll b/llvm/test/CodeGen/RISCV/frame-info.ll index 4979c9f75ef94..c36007651f199 100644 --- a/llvm/test/CodeGen/RISCV/frame-info.ll +++ b/llvm/test/CodeGen/RISCV/frame-info.ll @@ -330,10 +330,8 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-LABEL: branch_and_tail_call: ; RV32: # %bb.0: ; RV32-NEXT: andi a0, a0, 1 -; RV32-NEXT: beqz a0, .LBB2_2 -; RV32-NEXT: # %bb.1: # %blue_pill -; RV32-NEXT: tail callee1 -; RV32-NEXT: .LBB2_2: # %red_pill +; RV32-NEXT: bnez a0, .LBB2_2 +; RV32-NEXT: # %bb.1: # %red_pill ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill @@ -344,14 +342,14 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 ; RV32-NEXT: ret +; RV32-NEXT: .LBB2_2: # %blue_pill +; RV32-NEXT: tail callee1 ; ; RV64-LABEL: branch_and_tail_call: ; RV64: # %bb.0: ; RV64-NEXT: andi a0, a0, 1 -; RV64-NEXT: beqz a0, .LBB2_2 -; RV64-NEXT: # %bb.1: # %blue_pill -; RV64-NEXT: tail callee1 -; RV64-NEXT: .LBB2_2: # %red_pill +; RV64-NEXT: bnez a0, .LBB2_2 +; RV64-NEXT: # %bb.1: # %red_pill ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill @@ -362,14 +360,14 @@ define void @branch_and_tail_call(i1 %a) { ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: .cfi_def_cfa_offset 0 ; RV64-NEXT: ret +; RV64-NEXT: .LBB2_2: # %blue_pill +; RV64-NEXT: tail callee1 ; ; RV32-WITHFP-LABEL: branch_and_tail_call: ; RV32-WITHFP: # %bb.0: ; RV32-WITHFP-NEXT: andi a0, a0, 1 -; RV32-WITHFP-NEXT: beqz a0, .LBB2_2 -; RV32-WITHFP-NEXT: # %bb.1: # %blue_pill -; RV32-WITHFP-NEXT: tail callee1 -; RV32-WITHFP-NEXT: .LBB2_2: # %red_pill +; RV32-WITHFP-NEXT: bnez a0, .LBB2_2 +; RV32-WITHFP-NEXT: # %bb.1: # %red_pill ; RV32-WITHFP-NEXT: addi sp, sp, -16 ; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 16 ; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill @@ -387,14 +385,14 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-WITHFP-NEXT: addi sp, sp, 16 ; RV32-WITHFP-NEXT: .cfi_def_cfa_offset 0 ; RV32-WITHFP-NEXT: ret +; RV32-WITHFP-NEXT: .LBB2_2: # %blue_pill +; RV32-WITHFP-NEXT: tail callee1 ; ; RV64-WITHFP-LABEL: branch_and_tail_call: ; RV64-WITHFP: # %bb.0: ; RV64-WITHFP-NEXT: andi a0, a0, 1 -; RV64-WITHFP-NEXT: beqz a0, .LBB2_2 -; RV64-WITHFP-NEXT: # %bb.1: # %blue_pill -; RV64-WITHFP-NEXT: tail callee1 -; RV64-WITHFP-NEXT: .LBB2_2: # %red_pill +; RV64-WITHFP-NEXT: bnez a0, .LBB2_2 +; RV64-WITHFP-NEXT: # %bb.1: # %red_pill ; RV64-WITHFP-NEXT: addi sp, sp, -16 ; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 16 ; RV64-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill @@ -412,6 +410,8 @@ define void @branch_and_tail_call(i1 %a) { ; RV64-WITHFP-NEXT: addi sp, sp, 16 ; RV64-WITHFP-NEXT: .cfi_def_cfa_offset 0 ; RV64-WITHFP-NEXT: ret +; RV64-WITHFP-NEXT: .LBB2_2: # %blue_pill +; RV64-WITHFP-NEXT: tail callee1 ; ; RV32-DISABLESW-LABEL: branch_and_tail_call: ; RV32-DISABLESW: # %bb.0: @@ -421,21 +421,21 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-DISABLESW-NEXT: .cfi_offset ra, -4 ; RV32-DISABLESW-NEXT: .cfi_remember_state ; RV32-DISABLESW-NEXT: andi a0, a0, 1 -; RV32-DISABLESW-NEXT: beqz a0, .LBB2_2 -; RV32-DISABLESW-NEXT: # %bb.1: # %blue_pill +; RV32-DISABLESW-NEXT: bnez a0, .LBB2_2 +; RV32-DISABLESW-NEXT: # %bb.1: # %red_pill +; RV32-DISABLESW-NEXT: call callee2 ; RV32-DISABLESW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-DISABLESW-NEXT: .cfi_restore ra ; RV32-DISABLESW-NEXT: addi sp, sp, 16 ; RV32-DISABLESW-NEXT: .cfi_def_cfa_offset 0 -; RV32-DISABLESW-NEXT: tail callee1 -; RV32-DISABLESW-NEXT: .LBB2_2: # %red_pill +; RV32-DISABLESW-NEXT: ret +; RV32-DISABLESW-NEXT: .LBB2_2: # %blue_pill ; RV32-DISABLESW-NEXT: .cfi_restore_state -; RV32-DISABLESW-NEXT: call callee2 ; RV32-DISABLESW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-DISABLESW-NEXT: .cfi_restore ra ; RV32-DISABLESW-NEXT: addi sp, sp, 16 ; RV32-DISABLESW-NEXT: .cfi_def_cfa_offset 0 -; RV32-DISABLESW-NEXT: ret +; RV32-DISABLESW-NEXT: tail callee1 ; ; RV64-DISABLESW-LABEL: branch_and_tail_call: ; RV64-DISABLESW: # %bb.0: @@ -445,21 +445,21 @@ define void @branch_and_tail_call(i1 %a) { ; RV64-DISABLESW-NEXT: .cfi_offset ra, -8 ; RV64-DISABLESW-NEXT: .cfi_remember_state ; RV64-DISABLESW-NEXT: andi a0, a0, 1 -; RV64-DISABLESW-NEXT: beqz a0, .LBB2_2 -; RV64-DISABLESW-NEXT: # %bb.1: # %blue_pill +; RV64-DISABLESW-NEXT: bnez a0, .LBB2_2 +; RV64-DISABLESW-NEXT: # %bb.1: # %red_pill +; RV64-DISABLESW-NEXT: call callee2 ; RV64-DISABLESW-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-DISABLESW-NEXT: .cfi_restore ra ; RV64-DISABLESW-NEXT: addi sp, sp, 16 ; RV64-DISABLESW-NEXT: .cfi_def_cfa_offset 0 -; RV64-DISABLESW-NEXT: tail callee1 -; RV64-DISABLESW-NEXT: .LBB2_2: # %red_pill +; RV64-DISABLESW-NEXT: ret +; RV64-DISABLESW-NEXT: .LBB2_2: # %blue_pill ; RV64-DISABLESW-NEXT: .cfi_restore_state -; RV64-DISABLESW-NEXT: call callee2 ; RV64-DISABLESW-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-DISABLESW-NEXT: .cfi_restore ra ; RV64-DISABLESW-NEXT: addi sp, sp, 16 ; RV64-DISABLESW-NEXT: .cfi_def_cfa_offset 0 -; RV64-DISABLESW-NEXT: ret +; RV64-DISABLESW-NEXT: tail callee1 ; ; RV32-WITHFP-DISABLESW-LABEL: branch_and_tail_call: ; RV32-WITHFP-DISABLESW: # %bb.0: @@ -473,8 +473,9 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-WITHFP-DISABLESW-NEXT: .cfi_def_cfa s0, 0 ; RV32-WITHFP-DISABLESW-NEXT: .cfi_remember_state ; RV32-WITHFP-DISABLESW-NEXT: andi a0, a0, 1 -; RV32-WITHFP-DISABLESW-NEXT: beqz a0, .LBB2_2 -; RV32-WITHFP-DISABLESW-NEXT: # %bb.1: # %blue_pill +; RV32-WITHFP-DISABLESW-NEXT: bnez a0, .LBB2_2 +; RV32-WITHFP-DISABLESW-NEXT: # %bb.1: # %red_pill +; RV32-WITHFP-DISABLESW-NEXT: call callee2 ; RV32-WITHFP-DISABLESW-NEXT: .cfi_def_cfa sp, 16 ; RV32-WITHFP-DISABLESW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-WITHFP-DISABLESW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -482,10 +483,9 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-WITHFP-DISABLESW-NEXT: .cfi_restore s0 ; RV32-WITHFP-DISABLESW-NEXT: addi sp, sp, 16 ; RV32-WITHFP-DISABLESW-NEXT: .cfi_def_cfa_offset 0 -; RV32-WITHFP-DISABLESW-NEXT: tail callee1 -; RV32-WITHFP-DISABLESW-NEXT: .LBB2_2: # %red_pill +; RV32-WITHFP-DISABLESW-NEXT: ret +; RV32-WITHFP-DISABLESW-NEXT: .LBB2_2: # %blue_pill ; RV32-WITHFP-DISABLESW-NEXT: .cfi_restore_state -; RV32-WITHFP-DISABLESW-NEXT: call callee2 ; RV32-WITHFP-DISABLESW-NEXT: .cfi_def_cfa sp, 16 ; RV32-WITHFP-DISABLESW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-WITHFP-DISABLESW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -493,7 +493,7 @@ define void @branch_and_tail_call(i1 %a) { ; RV32-WITHFP-DISABLESW-NEXT: .cfi_restore s0 ; RV32-WITHFP-DISABLESW-NEXT: addi sp, sp, 16 ; RV32-WITHFP-DISABLESW-NEXT: .cfi_def_cfa_offset 0 -; RV32-WITHFP-DISABLESW-NEXT: ret +; RV32-WITHFP-DISABLESW-NEXT: tail callee1 ; ; RV64-WITHFP-DISABLESW-LABEL: branch_and_tail_call: ; RV64-WITHFP-DISABLESW: # %bb.0: @@ -507,8 +507,9 @@ define void @branch_and_tail_call(i1 %a) { ; RV64-WITHFP-DISABLESW-NEXT: .cfi_def_cfa s0, 0 ; RV64-WITHFP-DISABLESW-NEXT: .cfi_remember_state ; RV64-WITHFP-DISABLESW-NEXT: andi a0, a0, 1 -; RV64-WITHFP-DISABLESW-NEXT: beqz a0, .LBB2_2 -; RV64-WITHFP-DISABLESW-NEXT: # %bb.1: # %blue_pill +; RV64-WITHFP-DISABLESW-NEXT: bnez a0, .LBB2_2 +; RV64-WITHFP-DISABLESW-NEXT: # %bb.1: # %red_pill +; RV64-WITHFP-DISABLESW-NEXT: call callee2 ; RV64-WITHFP-DISABLESW-NEXT: .cfi_def_cfa sp, 16 ; RV64-WITHFP-DISABLESW-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-WITHFP-DISABLESW-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -516,10 +517,9 @@ define void @branch_and_tail_call(i1 %a) { ; RV64-WITHFP-DISABLESW-NEXT: .cfi_restore s0 ; RV64-WITHFP-DISABLESW-NEXT: addi sp, sp, 16 ; RV64-WITHFP-DISABLESW-NEXT: .cfi_def_cfa_offset 0 -; RV64-WITHFP-DISABLESW-NEXT: tail callee1 -; RV64-WITHFP-DISABLESW-NEXT: .LBB2_2: # %red_pill +; RV64-WITHFP-DISABLESW-NEXT: ret +; RV64-WITHFP-DISABLESW-NEXT: .LBB2_2: # %blue_pill ; RV64-WITHFP-DISABLESW-NEXT: .cfi_restore_state -; RV64-WITHFP-DISABLESW-NEXT: call callee2 ; RV64-WITHFP-DISABLESW-NEXT: .cfi_def_cfa sp, 16 ; RV64-WITHFP-DISABLESW-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64-WITHFP-DISABLESW-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -527,7 +527,7 @@ define void @branch_and_tail_call(i1 %a) { ; RV64-WITHFP-DISABLESW-NEXT: .cfi_restore s0 ; RV64-WITHFP-DISABLESW-NEXT: addi sp, sp, 16 ; RV64-WITHFP-DISABLESW-NEXT: .cfi_def_cfa_offset 0 -; RV64-WITHFP-DISABLESW-NEXT: ret +; RV64-WITHFP-DISABLESW-NEXT: tail callee1 br i1 %a, label %blue_pill, label %red_pill blue_pill: tail call void @callee1() diff --git a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll index ab8f7cd4e6bfd..ceb49747c543c 100644 --- a/llvm/test/CodeGen/RISCV/half-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/half-br-fcmp.ll @@ -23,80 +23,48 @@ declare half @dummy(half) define void @br_fcmp_false(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_false: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: j .LBB0_2 -; RV32IZFH-NEXT: # %bb.1: # %if.then -; RV32IZFH-NEXT: ret -; RV32IZFH-NEXT: .LBB0_2: # %if.else ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_false: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: j .LBB0_2 -; RV64IZFH-NEXT: # %bb.1: # %if.then -; RV64IZFH-NEXT: ret -; RV64IZFH-NEXT: .LBB0_2: # %if.else ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_false: ; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: j .LBB0_2 -; RV32IZHINX-NEXT: # %bb.1: # %if.then -; RV32IZHINX-NEXT: ret -; RV32IZHINX-NEXT: .LBB0_2: # %if.else ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_false: ; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: j .LBB0_2 -; RV64IZHINX-NEXT: # %bb.1: # %if.then -; RV64IZHINX-NEXT: ret -; RV64IZHINX-NEXT: .LBB0_2: # %if.else ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_false: ; RV32IZFHMIN: # %bb.0: -; RV32IZFHMIN-NEXT: j .LBB0_2 -; RV32IZFHMIN-NEXT: # %bb.1: # %if.then -; RV32IZFHMIN-NEXT: ret -; RV32IZFHMIN-NEXT: .LBB0_2: # %if.else ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_false: ; RV64IZFHMIN: # %bb.0: -; RV64IZFHMIN-NEXT: j .LBB0_2 -; RV64IZFHMIN-NEXT: # %bb.1: # %if.then -; RV64IZFHMIN-NEXT: ret -; RV64IZFHMIN-NEXT: .LBB0_2: # %if.else ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_false: ; RV32IZHINXMIN: # %bb.0: -; RV32IZHINXMIN-NEXT: j .LBB0_2 -; RV32IZHINXMIN-NEXT: # %bb.1: # %if.then -; RV32IZHINXMIN-NEXT: ret -; RV32IZHINXMIN-NEXT: .LBB0_2: # %if.else ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_false: ; RV64IZHINXMIN: # %bb.0: -; RV64IZHINXMIN-NEXT: j .LBB0_2 -; RV64IZHINXMIN-NEXT: # %bb.1: # %if.then -; RV64IZHINXMIN-NEXT: ret -; RV64IZHINXMIN-NEXT: .LBB0_2: # %if.else ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: call abort @@ -1754,80 +1722,48 @@ if.then: define void @br_fcmp_true(half %a, half %b) nounwind { ; RV32IZFH-LABEL: br_fcmp_true: ; RV32IZFH: # %bb.0: -; RV32IZFH-NEXT: j .LBB16_2 -; RV32IZFH-NEXT: # %bb.1: # %if.else -; RV32IZFH-NEXT: ret -; RV32IZFH-NEXT: .LBB16_2: # %if.then ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: call abort ; ; RV64IZFH-LABEL: br_fcmp_true: ; RV64IZFH: # %bb.0: -; RV64IZFH-NEXT: j .LBB16_2 -; RV64IZFH-NEXT: # %bb.1: # %if.else -; RV64IZFH-NEXT: ret -; RV64IZFH-NEXT: .LBB16_2: # %if.then ; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: call abort ; ; RV32IZHINX-LABEL: br_fcmp_true: ; RV32IZHINX: # %bb.0: -; RV32IZHINX-NEXT: j .LBB16_2 -; RV32IZHINX-NEXT: # %bb.1: # %if.else -; RV32IZHINX-NEXT: ret -; RV32IZHINX-NEXT: .LBB16_2: # %if.then ; RV32IZHINX-NEXT: addi sp, sp, -16 ; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINX-NEXT: call abort ; ; RV64IZHINX-LABEL: br_fcmp_true: ; RV64IZHINX: # %bb.0: -; RV64IZHINX-NEXT: j .LBB16_2 -; RV64IZHINX-NEXT: # %bb.1: # %if.else -; RV64IZHINX-NEXT: ret -; RV64IZHINX-NEXT: .LBB16_2: # %if.then ; RV64IZHINX-NEXT: addi sp, sp, -16 ; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINX-NEXT: call abort ; ; RV32IZFHMIN-LABEL: br_fcmp_true: ; RV32IZFHMIN: # %bb.0: -; RV32IZFHMIN-NEXT: j .LBB16_2 -; RV32IZFHMIN-NEXT: # %bb.1: # %if.else -; RV32IZFHMIN-NEXT: ret -; RV32IZFHMIN-NEXT: .LBB16_2: # %if.then ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: call abort ; ; RV64IZFHMIN-LABEL: br_fcmp_true: ; RV64IZFHMIN: # %bb.0: -; RV64IZFHMIN-NEXT: j .LBB16_2 -; RV64IZFHMIN-NEXT: # %bb.1: # %if.else -; RV64IZFHMIN-NEXT: ret -; RV64IZFHMIN-NEXT: .LBB16_2: # %if.then ; RV64IZFHMIN-NEXT: addi sp, sp, -16 ; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFHMIN-NEXT: call abort ; ; RV32IZHINXMIN-LABEL: br_fcmp_true: ; RV32IZHINXMIN: # %bb.0: -; RV32IZHINXMIN-NEXT: j .LBB16_2 -; RV32IZHINXMIN-NEXT: # %bb.1: # %if.else -; RV32IZHINXMIN-NEXT: ret -; RV32IZHINXMIN-NEXT: .LBB16_2: # %if.then ; RV32IZHINXMIN-NEXT: addi sp, sp, -16 ; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZHINXMIN-NEXT: call abort ; ; RV64IZHINXMIN-LABEL: br_fcmp_true: ; RV64IZHINXMIN: # %bb.0: -; RV64IZHINXMIN-NEXT: j .LBB16_2 -; RV64IZHINXMIN-NEXT: # %bb.1: # %if.else -; RV64IZHINXMIN-NEXT: ret -; RV64IZHINXMIN-NEXT: .LBB16_2: # %if.then ; RV64IZHINXMIN-NEXT: addi sp, sp, -16 ; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZHINXMIN-NEXT: call abort diff --git a/llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll b/llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll index f506d30e7b6f8..d0c146e31eff4 100644 --- a/llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll +++ b/llvm/test/CodeGen/RISCV/machine-sink-load-immediate.ll @@ -13,71 +13,11 @@ define i1 @sink_li(ptr %text, ptr %text.addr.0) nounwind { ; CHECK-NEXT: mv s0, a0 ; CHECK-NEXT: call toupper ; CHECK-NEXT: li a1, 0 -; CHECK-NEXT: beqz s0, .LBB0_25 -; CHECK-NEXT: .LBB0_1: # %while.body +; CHECK-NEXT: beqz s0, .LBB0_2 +; CHECK-NEXT: .LBB0_1: # %while.body.6 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: j .LBB0_3 -; CHECK-NEXT: # %bb.2: # %while.body -; CHECK-NEXT: j .LBB0_15 -; CHECK-NEXT: .LBB0_3: # %while.body.1 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: j .LBB0_5 -; CHECK-NEXT: # %bb.4: # %while.body.1 -; CHECK-NEXT: j .LBB0_16 -; CHECK-NEXT: .LBB0_5: # %while.body.3 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: j .LBB0_7 -; CHECK-NEXT: # %bb.6: # %while.body.3 -; CHECK-NEXT: j .LBB0_18 -; CHECK-NEXT: .LBB0_7: # %while.body.4 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: j .LBB0_9 -; CHECK-NEXT: # %bb.8: # %while.body.4 -; CHECK-NEXT: j .LBB0_20 -; CHECK-NEXT: .LBB0_9: # %while.body.5 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 -; CHECK-NEXT: j .LBB0_11 -; CHECK-NEXT: # %bb.10: # %while.body.5 -; CHECK-NEXT: j .LBB0_22 -; CHECK-NEXT: .LBB0_11: # %while.body.6 -; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 ; CHECK-NEXT: j .LBB0_1 -; CHECK-NEXT: # %bb.12: # %while.body.6 -; CHECK-NEXT: # %bb.13: # %while.body.6 -; CHECK-NEXT: # %bb.14: # %strdup.exit.split.loop.exit126 -; CHECK-NEXT: addi s0, s1, 7 -; CHECK-NEXT: j .LBB0_24 -; CHECK-NEXT: .LBB0_15: # %while.body -; CHECK-NEXT: j .LBB0_17 -; CHECK-NEXT: .LBB0_16: # %while.body.1 -; CHECK-NEXT: .LBB0_17: # %strdup.exit.loopexit -; CHECK-NEXT: li s0, 0 -; CHECK-NEXT: j .LBB0_24 -; CHECK-NEXT: .LBB0_18: # %while.body.3 -; CHECK-NEXT: # %bb.19: # %strdup.exit.split.loop.exit120 -; CHECK-NEXT: addi s0, s1, 4 -; CHECK-NEXT: j .LBB0_24 -; CHECK-NEXT: .LBB0_20: # %while.body.4 -; CHECK-NEXT: # %bb.21: # %strdup.exit.split.loop.exit122 -; CHECK-NEXT: addi s0, s1, 5 -; CHECK-NEXT: j .LBB0_24 -; CHECK-NEXT: .LBB0_22: # %while.body.5 -; CHECK-NEXT: j .LBB0_24 -; CHECK-NEXT: # %bb.23: -; CHECK-NEXT: li a1, 0 -; CHECK-NEXT: j .LBB0_25 -; CHECK-NEXT: .LBB0_24: # %strdup.exit -; CHECK-NEXT: li s1, 0 -; CHECK-NEXT: mv s2, a0 -; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: mv a1, s0 -; CHECK-NEXT: jalr s1 -; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: mv a1, s2 -; CHECK-NEXT: li a2, 0 -; CHECK-NEXT: jalr s1 -; CHECK-NEXT: li a1, 1 -; CHECK-NEXT: .LBB0_25: # %return +; CHECK-NEXT: .LBB0_2: # %return ; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/pr93587.ll b/llvm/test/CodeGen/RISCV/rvv/pr93587.ll index c2998bf20fa0a..52cbb0959e116 100644 --- a/llvm/test/CodeGen/RISCV/rvv/pr93587.ll +++ b/llvm/test/CodeGen/RISCV/rvv/pr93587.ll @@ -9,21 +9,11 @@ define i16 @f() { ; CHECK: # %bb.0: # %BB ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: j .LBB0_1 ; CHECK-NEXT: .LBB0_1: # %BB1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: sd a0, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: j .LBB0_1 -; CHECK-NEXT: # %bb.2: # %BB1 -; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: bnez a0, .LBB0_1 -; CHECK-NEXT: j .LBB0_3 -; CHECK-NEXT: .LBB0_3: # %BB2 -; CHECK-NEXT: ld a0, 8(sp) # 8-byte Folded Reload -; CHECK-NEXT: addi sp, sp, 16 -; CHECK-NEXT: .cfi_def_cfa_offset 0 -; CHECK-NEXT: ret BB: br label %BB1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll b/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll index ed6b7f1e6efb8..60766bd7138ed 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll @@ -74,15 +74,15 @@ define dso_local void @test_store1(ptr nocapture noundef writeonly %dst, ptr noc ; ; RV64-LABEL: test_store1: ; RV64: # %bb.0: # %entry -; RV64-NEXT: blez a3, .LBB0_6 +; RV64-NEXT: blez a3, .LBB0_10 ; RV64-NEXT: # %bb.1: # %for.body.preheader ; RV64-NEXT: li a5, 8 ; RV64-NEXT: li a4, 0 -; RV64-NEXT: bltu a3, a5, .LBB0_7 +; RV64-NEXT: bltu a3, a5, .LBB0_6 ; RV64-NEXT: # %bb.2: # %for.body.preheader ; RV64-NEXT: sub a5, a0, a1 ; RV64-NEXT: li a6, 31 -; RV64-NEXT: bgeu a6, a5, .LBB0_7 +; RV64-NEXT: bgeu a6, a5, .LBB0_6 ; RV64-NEXT: # %bb.3: # %vector.ph ; RV64-NEXT: lui a4, 524288 ; RV64-NEXT: addiw a4, a4, -8 @@ -104,29 +104,29 @@ define dso_local void @test_store1(ptr nocapture noundef writeonly %dst, ptr noc ; RV64-NEXT: add a0, a0, a7 ; RV64-NEXT: bne a6, a5, .LBB0_4 ; RV64-NEXT: # %bb.5: # %middle.block -; RV64-NEXT: bne a4, a3, .LBB0_7 -; RV64-NEXT: .LBB0_6: # %for.cond.cleanup -; RV64-NEXT: ret -; RV64-NEXT: .LBB0_7: # %for.body.preheader13 +; RV64-NEXT: beq a4, a3, .LBB0_10 +; RV64-NEXT: .LBB0_6: # %for.body.preheader13 ; RV64-NEXT: slli a4, a4, 2 ; RV64-NEXT: slli a5, a3, 2 ; RV64-NEXT: add a3, a1, a4 ; RV64-NEXT: add a1, a1, a5 -; RV64-NEXT: j .LBB0_9 -; RV64-NEXT: .LBB0_8: # %for.inc -; RV64-NEXT: # in Loop: Header=BB0_9 Depth=1 +; RV64-NEXT: j .LBB0_8 +; RV64-NEXT: .LBB0_7: # %for.inc +; RV64-NEXT: # in Loop: Header=BB0_8 Depth=1 ; RV64-NEXT: addi a3, a3, 4 -; RV64-NEXT: beq a3, a1, .LBB0_6 -; RV64-NEXT: .LBB0_9: # %for.body +; RV64-NEXT: beq a3, a1, .LBB0_10 +; RV64-NEXT: .LBB0_8: # %for.body ; RV64-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NEXT: lw a4, 0(a3) -; RV64-NEXT: bge a4, a2, .LBB0_8 -; RV64-NEXT: # %bb.10: # %if.then -; RV64-NEXT: # in Loop: Header=BB0_9 Depth=1 +; RV64-NEXT: bge a4, a2, .LBB0_7 +; RV64-NEXT: # %bb.9: # %if.then +; RV64-NEXT: # in Loop: Header=BB0_8 Depth=1 ; RV64-NEXT: addi a5, a0, 4 ; RV64-NEXT: sw a4, 0(a0) ; RV64-NEXT: mv a0, a5 -; RV64-NEXT: j .LBB0_8 +; RV64-NEXT: j .LBB0_7 +; RV64-NEXT: .LBB0_10: # %for.cond.cleanup +; RV64-NEXT: ret entry: %cmp8 = icmp sgt i32 %n, 0 br i1 %cmp8, label %for.body.preheader, label %for.cond.cleanup diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll index 35311bb156f44..39f282a5a3236 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll @@ -1060,18 +1060,18 @@ define void @cross_block_avl_extend_backwards(i1 %cond, %v, pt ; CHECK-LABEL: cross_block_avl_extend_backwards: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi a0, a0, 1 -; CHECK-NEXT: beqz a0, .LBB25_2 -; CHECK-NEXT: # %bb.1: # %exit -; CHECK-NEXT: ret -; CHECK-NEXT: .LBB25_2: # %bar +; CHECK-NEXT: bnez a0, .LBB25_3 +; CHECK-NEXT: # %bb.1: # %bar ; CHECK-NEXT: addi a2, a2, 1 -; CHECK-NEXT: .LBB25_3: # %foo +; CHECK-NEXT: .LBB25_2: # %foo ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma ; CHECK-NEXT: vse8.v v8, (a1) -; CHECK-NEXT: j .LBB25_3 +; CHECK-NEXT: j .LBB25_2 +; CHECK-NEXT: .LBB25_3: # %exit +; CHECK-NEXT: ret entry: br i1 %cond, label %exit, label %bar foo: diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll index 75f4b977a98b0..77119e50d5add 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll @@ -14,9 +14,9 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_dst_stride, ptr nocapture noundef readonly %src1, i32 noundef signext %i_src1_stride, ptr nocapture noundef readonly %src2, i32 noundef signext %i_src2_stride, i32 noundef signext %i_width, i32 noundef signext %i_height) { ; RV32-LABEL: test1: ; RV32: # %bb.0: # %entry -; RV32-NEXT: blez a7, .LBB0_17 +; RV32-NEXT: blez a7, .LBB0_13 ; RV32-NEXT: # %bb.1: # %for.cond1.preheader.lr.ph -; RV32-NEXT: blez a6, .LBB0_17 +; RV32-NEXT: blez a6, .LBB0_13 ; RV32-NEXT: # %bb.2: # %for.cond1.preheader.us.preheader ; RV32-NEXT: addi t0, a7, -1 ; RV32-NEXT: csrr t2, vlenb @@ -26,9 +26,7 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV32-NEXT: slli t1, t2, 1 ; RV32-NEXT: li t6, 32 ; RV32-NEXT: mv t0, t1 -; RV32-NEXT: # %bb.3: # %for.cond1.preheader.us.preheader ; RV32-NEXT: li t0, 32 -; RV32-NEXT: # %bb.4: # %for.cond1.preheader.us.preheader ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill @@ -37,22 +35,16 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV32-NEXT: .cfi_offset s0, -4 ; RV32-NEXT: .cfi_offset s1, -8 ; RV32-NEXT: .cfi_offset s2, -12 -; RV32-NEXT: .cfi_remember_state ; RV32-NEXT: add t3, a0, t3 ; RV32-NEXT: add t4, a2, t4 ; RV32-NEXT: add s0, a4, t5 -; RV32-NEXT: bltu t6, t1, .LBB0_6 -; RV32-NEXT: # %bb.5: # %for.cond1.preheader.us.preheader +; RV32-NEXT: bltu t6, t1, .LBB0_4 +; RV32-NEXT: # %bb.3: # %for.cond1.preheader.us.preheader ; RV32-NEXT: li t1, 32 -; RV32-NEXT: .LBB0_6: # %for.cond1.preheader.us.preheader +; RV32-NEXT: .LBB0_4: # %for.cond1.preheader.us.preheader ; RV32-NEXT: add t3, t3, a6 ; RV32-NEXT: add t5, t4, a6 ; RV32-NEXT: add t4, s0, a6 -; RV32-NEXT: j .LBB0_8 -; RV32-NEXT: # %bb.7: # %for.cond1.preheader.us.preheader -; RV32-NEXT: mv t1, t0 -; RV32-NEXT: .LBB0_8: # %for.cond1.preheader.us.preheader -; RV32-NEXT: .cfi_restore_state ; RV32-NEXT: li t0, 0 ; RV32-NEXT: sltu t5, a0, t5 ; RV32-NEXT: sltu t6, a2, t3 @@ -71,25 +63,25 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV32-NEXT: or t1, t1, t3 ; RV32-NEXT: andi t1, t1, 1 ; RV32-NEXT: slli t2, t2, 1 -; RV32-NEXT: j .LBB0_10 -; RV32-NEXT: .LBB0_9: # %for.cond1.for.cond.cleanup3_crit_edge.us -; RV32-NEXT: # in Loop: Header=BB0_10 Depth=1 +; RV32-NEXT: j .LBB0_6 +; RV32-NEXT: .LBB0_5: # %for.cond1.for.cond.cleanup3_crit_edge.us +; RV32-NEXT: # in Loop: Header=BB0_6 Depth=1 ; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: add a2, a2, a3 ; RV32-NEXT: addi t0, t0, 1 ; RV32-NEXT: add a4, a4, a5 -; RV32-NEXT: beq t0, a7, .LBB0_16 -; RV32-NEXT: .LBB0_10: # %for.cond1.preheader.us +; RV32-NEXT: beq t0, a7, .LBB0_12 +; RV32-NEXT: .LBB0_6: # %for.cond1.preheader.us ; RV32-NEXT: # =>This Loop Header: Depth=1 -; RV32-NEXT: # Child Loop BB0_13 Depth 2 -; RV32-NEXT: # Child Loop BB0_15 Depth 2 -; RV32-NEXT: beqz t1, .LBB0_12 -; RV32-NEXT: # %bb.11: # in Loop: Header=BB0_10 Depth=1 +; RV32-NEXT: # Child Loop BB0_9 Depth 2 +; RV32-NEXT: # Child Loop BB0_11 Depth 2 +; RV32-NEXT: beqz t1, .LBB0_8 +; RV32-NEXT: # %bb.7: # in Loop: Header=BB0_6 Depth=1 ; RV32-NEXT: li t4, 0 ; RV32-NEXT: li t3, 0 -; RV32-NEXT: j .LBB0_15 -; RV32-NEXT: .LBB0_12: # %vector.ph -; RV32-NEXT: # in Loop: Header=BB0_10 Depth=1 +; RV32-NEXT: j .LBB0_11 +; RV32-NEXT: .LBB0_8: # %vector.ph +; RV32-NEXT: # in Loop: Header=BB0_6 Depth=1 ; RV32-NEXT: li t3, 0 ; RV32-NEXT: neg t4, t2 ; RV32-NEXT: and t4, t4, a6 @@ -97,8 +89,8 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV32-NEXT: li t6, 0 ; RV32-NEXT: li t5, 0 ; RV32-NEXT: vsetvli s0, zero, e8, m2, ta, ma -; RV32-NEXT: .LBB0_13: # %vector.body -; RV32-NEXT: # Parent Loop BB0_10 Depth=1 +; RV32-NEXT: .LBB0_9: # %vector.body +; RV32-NEXT: # Parent Loop BB0_6 Depth=1 ; RV32-NEXT: # => This Inner Loop Header: Depth=2 ; RV32-NEXT: add s0, a2, t6 ; RV32-NEXT: add s1, a4, t6 @@ -113,12 +105,12 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV32-NEXT: or s2, t6, t5 ; RV32-NEXT: vs2r.v v8, (s0) ; RV32-NEXT: mv t6, s1 -; RV32-NEXT: bnez s2, .LBB0_13 -; RV32-NEXT: # %bb.14: # %middle.block -; RV32-NEXT: # in Loop: Header=BB0_10 Depth=1 -; RV32-NEXT: beq t4, a6, .LBB0_9 -; RV32-NEXT: .LBB0_15: # %for.body4.us -; RV32-NEXT: # Parent Loop BB0_10 Depth=1 +; RV32-NEXT: bnez s2, .LBB0_9 +; RV32-NEXT: # %bb.10: # %middle.block +; RV32-NEXT: # in Loop: Header=BB0_6 Depth=1 +; RV32-NEXT: beq t4, a6, .LBB0_5 +; RV32-NEXT: .LBB0_11: # %for.body4.us +; RV32-NEXT: # Parent Loop BB0_6 Depth=1 ; RV32-NEXT: # => This Inner Loop Header: Depth=2 ; RV32-NEXT: add t5, a2, t4 ; RV32-NEXT: add t6, a4, t4 @@ -134,9 +126,9 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV32-NEXT: srli t5, t5, 1 ; RV32-NEXT: or t6, t6, t3 ; RV32-NEXT: sb t5, 0(s0) -; RV32-NEXT: bnez t6, .LBB0_15 -; RV32-NEXT: j .LBB0_9 -; RV32-NEXT: .LBB0_16: +; RV32-NEXT: bnez t6, .LBB0_11 +; RV32-NEXT: j .LBB0_5 +; RV32-NEXT: .LBB0_12: ; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s2, 4(sp) # 4-byte Folded Reload @@ -145,7 +137,7 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_ ; RV32-NEXT: .cfi_restore s2 ; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: .cfi_def_cfa_offset 0 -; RV32-NEXT: .LBB0_17: # %for.cond.cleanup +; RV32-NEXT: .LBB0_13: # %for.cond.cleanup ; RV32-NEXT: ret ; ; RV64P670-LABEL: test1: diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll index fabb573e98d2a..3d72c55a510eb 100644 --- a/llvm/test/CodeGen/RISCV/setcc-logic.ll +++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll @@ -562,23 +562,23 @@ define void @and_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 sign define void @or_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_sge_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: bge a0, a1, .LBB21_3 +; RV32I-NEXT: bge a0, a1, .LBB21_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: beq a2, a3, .LBB21_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB21_3: +; RV32I-NEXT: bne a2, a3, .LBB21_3 +; RV32I-NEXT: .LBB21_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB21_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: or_sge_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: bge a0, a1, .LBB21_3 +; RV64I-NEXT: bge a0, a1, .LBB21_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: beq a2, a3, .LBB21_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB21_3: +; RV64I-NEXT: bne a2, a3, .LBB21_3 +; RV64I-NEXT: .LBB21_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB21_3: +; RV64I-NEXT: tail bar %5 = icmp sge i32 %0, %1 %6 = icmp eq i32 %2, %3 %7 = or i1 %5, %6 @@ -595,23 +595,23 @@ define void @or_sge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_sle_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: bge a1, a0, .LBB22_3 +; RV32I-NEXT: bge a1, a0, .LBB22_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: beq a2, a3, .LBB22_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB22_3: +; RV32I-NEXT: bne a2, a3, .LBB22_3 +; RV32I-NEXT: .LBB22_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB22_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: or_sle_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: bge a1, a0, .LBB22_3 +; RV64I-NEXT: bge a1, a0, .LBB22_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: beq a2, a3, .LBB22_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB22_3: +; RV64I-NEXT: bne a2, a3, .LBB22_3 +; RV64I-NEXT: .LBB22_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB22_3: +; RV64I-NEXT: tail bar %5 = icmp sle i32 %0, %1 %6 = icmp eq i32 %2, %3 %7 = or i1 %5, %6 @@ -628,23 +628,23 @@ define void @or_sle_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_uge_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: bgeu a0, a1, .LBB23_3 +; RV32I-NEXT: bgeu a0, a1, .LBB23_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: beq a2, a3, .LBB23_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB23_3: +; RV32I-NEXT: bne a2, a3, .LBB23_3 +; RV32I-NEXT: .LBB23_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB23_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: or_uge_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: bgeu a0, a1, .LBB23_3 +; RV64I-NEXT: bgeu a0, a1, .LBB23_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: beq a2, a3, .LBB23_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB23_3: +; RV64I-NEXT: bne a2, a3, .LBB23_3 +; RV64I-NEXT: .LBB23_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB23_3: +; RV64I-NEXT: tail bar %5 = icmp uge i32 %0, %1 %6 = icmp eq i32 %2, %3 %7 = or i1 %5, %6 @@ -661,23 +661,23 @@ define void @or_uge_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_ule_eq: ; RV32I: # %bb.0: -; RV32I-NEXT: bgeu a1, a0, .LBB24_3 +; RV32I-NEXT: bgeu a1, a0, .LBB24_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: beq a2, a3, .LBB24_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB24_3: +; RV32I-NEXT: bne a2, a3, .LBB24_3 +; RV32I-NEXT: .LBB24_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB24_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: or_ule_eq: ; RV64I: # %bb.0: -; RV64I-NEXT: bgeu a1, a0, .LBB24_3 +; RV64I-NEXT: bgeu a1, a0, .LBB24_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: beq a2, a3, .LBB24_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB24_3: +; RV64I-NEXT: bne a2, a3, .LBB24_3 +; RV64I-NEXT: .LBB24_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB24_3: +; RV64I-NEXT: tail bar %5 = icmp ule i32 %0, %1 %6 = icmp eq i32 %2, %3 %7 = or i1 %5, %6 @@ -694,23 +694,23 @@ define void @or_ule_eq(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_sge_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: bge a0, a1, .LBB25_3 +; RV32I-NEXT: bge a0, a1, .LBB25_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: bne a2, a3, .LBB25_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB25_3: +; RV32I-NEXT: beq a2, a3, .LBB25_3 +; RV32I-NEXT: .LBB25_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB25_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: or_sge_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: bge a0, a1, .LBB25_3 +; RV64I-NEXT: bge a0, a1, .LBB25_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: bne a2, a3, .LBB25_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB25_3: +; RV64I-NEXT: beq a2, a3, .LBB25_3 +; RV64I-NEXT: .LBB25_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB25_3: +; RV64I-NEXT: tail bar %5 = icmp sge i32 %0, %1 %6 = icmp ne i32 %2, %3 %7 = or i1 %5, %6 @@ -727,23 +727,23 @@ define void @or_sge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_sle_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: bge a1, a0, .LBB26_3 +; RV32I-NEXT: bge a1, a0, .LBB26_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: bne a2, a3, .LBB26_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB26_3: +; RV32I-NEXT: beq a2, a3, .LBB26_3 +; RV32I-NEXT: .LBB26_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB26_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: or_sle_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: bge a1, a0, .LBB26_3 +; RV64I-NEXT: bge a1, a0, .LBB26_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: bne a2, a3, .LBB26_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB26_3: +; RV64I-NEXT: beq a2, a3, .LBB26_3 +; RV64I-NEXT: .LBB26_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB26_3: +; RV64I-NEXT: tail bar %5 = icmp sle i32 %0, %1 %6 = icmp ne i32 %2, %3 %7 = or i1 %5, %6 @@ -760,23 +760,23 @@ define void @or_sle_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_uge_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: bgeu a0, a1, .LBB27_3 +; RV32I-NEXT: bgeu a0, a1, .LBB27_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: bne a2, a3, .LBB27_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB27_3: +; RV32I-NEXT: beq a2, a3, .LBB27_3 +; RV32I-NEXT: .LBB27_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB27_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: or_uge_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: bgeu a0, a1, .LBB27_3 +; RV64I-NEXT: bgeu a0, a1, .LBB27_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: bne a2, a3, .LBB27_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB27_3: +; RV64I-NEXT: beq a2, a3, .LBB27_3 +; RV64I-NEXT: .LBB27_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB27_3: +; RV64I-NEXT: tail bar %5 = icmp uge i32 %0, %1 %6 = icmp ne i32 %2, %3 %7 = or i1 %5, %6 @@ -793,23 +793,23 @@ define void @or_uge_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signe define void @or_ule_ne(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) { ; RV32I-LABEL: or_ule_ne: ; RV32I: # %bb.0: -; RV32I-NEXT: bgeu a1, a0, .LBB28_3 +; RV32I-NEXT: bgeu a1, a0, .LBB28_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: bne a2, a3, .LBB28_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB28_3: +; RV32I-NEXT: beq a2, a3, .LBB28_3 +; RV32I-NEXT: .LBB28_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB28_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: or_ule_ne: ; RV64I: # %bb.0: -; RV64I-NEXT: bgeu a1, a0, .LBB28_3 +; RV64I-NEXT: bgeu a1, a0, .LBB28_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: bne a2, a3, .LBB28_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB28_3: +; RV64I-NEXT: beq a2, a3, .LBB28_3 +; RV64I-NEXT: .LBB28_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB28_3: +; RV64I-NEXT: tail bar %5 = icmp ule i32 %0, %1 %6 = icmp ne i32 %2, %3 %7 = or i1 %5, %6 @@ -1156,23 +1156,23 @@ define void @and_sle_lt1(i32 signext %0, i32 signext %1, i32 signext %2) { define void @or_uge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) { ; RV32I-LABEL: or_uge_gt0: ; RV32I: # %bb.0: -; RV32I-NEXT: bgeu a0, a1, .LBB39_3 +; RV32I-NEXT: bgeu a0, a1, .LBB39_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: bgtz a2, .LBB39_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB39_3: +; RV32I-NEXT: blez a2, .LBB39_3 +; RV32I-NEXT: .LBB39_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB39_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: or_uge_gt0: ; RV64I: # %bb.0: -; RV64I-NEXT: bgeu a0, a1, .LBB39_3 +; RV64I-NEXT: bgeu a0, a1, .LBB39_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: bgtz a2, .LBB39_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB39_3: +; RV64I-NEXT: blez a2, .LBB39_3 +; RV64I-NEXT: .LBB39_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB39_3: +; RV64I-NEXT: tail bar %4 = icmp uge i32 %0, %1 %5 = icmp sgt i32 %2, 0 %6 = or i1 %4, %5 @@ -1189,23 +1189,23 @@ define void @or_uge_gt0(i32 signext %0, i32 signext %1, i32 signext %2) { define void @or_ule_lt1(i32 signext %0, i32 signext %1, i32 signext %2) { ; RV32I-LABEL: or_ule_lt1: ; RV32I: # %bb.0: -; RV32I-NEXT: bgeu a1, a0, .LBB40_3 +; RV32I-NEXT: bgeu a1, a0, .LBB40_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: blez a2, .LBB40_3 -; RV32I-NEXT: # %bb.2: -; RV32I-NEXT: tail bar -; RV32I-NEXT: .LBB40_3: +; RV32I-NEXT: bgtz a2, .LBB40_3 +; RV32I-NEXT: .LBB40_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB40_3: +; RV32I-NEXT: tail bar ; ; RV64I-LABEL: or_ule_lt1: ; RV64I: # %bb.0: -; RV64I-NEXT: bgeu a1, a0, .LBB40_3 +; RV64I-NEXT: bgeu a1, a0, .LBB40_2 ; RV64I-NEXT: # %bb.1: -; RV64I-NEXT: blez a2, .LBB40_3 -; RV64I-NEXT: # %bb.2: -; RV64I-NEXT: tail bar -; RV64I-NEXT: .LBB40_3: +; RV64I-NEXT: bgtz a2, .LBB40_3 +; RV64I-NEXT: .LBB40_2: ; RV64I-NEXT: ret +; RV64I-NEXT: .LBB40_3: +; RV64I-NEXT: tail bar %4 = icmp ule i32 %0, %1 %5 = icmp slt i32 %2, 1 %6 = or i1 %4, %5 diff --git a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll index bdbe4ed216919..9fe8fc64c8e99 100644 --- a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll +++ b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll @@ -754,20 +754,20 @@ define i64 @dec_of_zexted_cmp_i64(i64 %x) { define void @zext_nneg_dominating_icmp_i64(i16 signext %0) { ; RV32I-LABEL: zext_nneg_dominating_icmp_i64: ; RV32I: # %bb.0: -; RV32I-NEXT: bltz a0, .LBB46_2 +; RV32I-NEXT: bgez a0, .LBB46_2 ; RV32I-NEXT: # %bb.1: +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB46_2: ; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: tail bar_i64 -; RV32I-NEXT: .LBB46_2: -; RV32I-NEXT: ret ; ; RV64-LABEL: zext_nneg_dominating_icmp_i64: ; RV64: # %bb.0: -; RV64-NEXT: bltz a0, .LBB46_2 +; RV64-NEXT: bgez a0, .LBB46_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar_i64 -; RV64-NEXT: .LBB46_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB46_2: +; RV64-NEXT: tail bar_i64 %2 = icmp sgt i16 %0, -1 br i1 %2, label %3, label %5 @@ -785,19 +785,19 @@ declare void @bar_i64(i64) define void @zext_nneg_dominating_icmp_i32(i16 signext %0) { ; RV32I-LABEL: zext_nneg_dominating_icmp_i32: ; RV32I: # %bb.0: -; RV32I-NEXT: bltz a0, .LBB47_2 +; RV32I-NEXT: bgez a0, .LBB47_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: tail bar_i32 -; RV32I-NEXT: .LBB47_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB47_2: +; RV32I-NEXT: tail bar_i32 ; ; RV64-LABEL: zext_nneg_dominating_icmp_i32: ; RV64: # %bb.0: -; RV64-NEXT: bltz a0, .LBB47_2 +; RV64-NEXT: bgez a0, .LBB47_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar_i32 -; RV64-NEXT: .LBB47_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB47_2: +; RV64-NEXT: tail bar_i32 %2 = icmp sgt i16 %0, -1 br i1 %2, label %3, label %5 @@ -817,19 +817,19 @@ declare void @bar_i32(i32) define void @zext_nneg_dominating_icmp_i32_signext(i16 signext %0) { ; RV32I-LABEL: zext_nneg_dominating_icmp_i32_signext: ; RV32I: # %bb.0: -; RV32I-NEXT: bltz a0, .LBB48_2 +; RV32I-NEXT: bgez a0, .LBB48_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: tail bar_i32 -; RV32I-NEXT: .LBB48_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB48_2: +; RV32I-NEXT: tail bar_i32 ; ; RV64-LABEL: zext_nneg_dominating_icmp_i32_signext: ; RV64: # %bb.0: -; RV64-NEXT: bltz a0, .LBB48_2 +; RV64-NEXT: bgez a0, .LBB48_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar_i32 -; RV64-NEXT: .LBB48_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB48_2: +; RV64-NEXT: tail bar_i32 %2 = icmp sgt i16 %0, -1 br i1 %2, label %3, label %5 @@ -847,19 +847,19 @@ define void @zext_nneg_dominating_icmp_i32_signext(i16 signext %0) { define void @zext_nneg_dominating_icmp_i32_zeroext(i16 signext %0) { ; RV32I-LABEL: zext_nneg_dominating_icmp_i32_zeroext: ; RV32I: # %bb.0: -; RV32I-NEXT: bltz a0, .LBB49_2 +; RV32I-NEXT: bgez a0, .LBB49_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: tail bar_i32 -; RV32I-NEXT: .LBB49_2: ; RV32I-NEXT: ret +; RV32I-NEXT: .LBB49_2: +; RV32I-NEXT: tail bar_i32 ; ; RV64-LABEL: zext_nneg_dominating_icmp_i32_zeroext: ; RV64: # %bb.0: -; RV64-NEXT: bltz a0, .LBB49_2 +; RV64-NEXT: bgez a0, .LBB49_2 ; RV64-NEXT: # %bb.1: -; RV64-NEXT: tail bar_i32 -; RV64-NEXT: .LBB49_2: ; RV64-NEXT: ret +; RV64-NEXT: .LBB49_2: +; RV64-NEXT: tail bar_i32 %2 = icmp sgt i16 %0, -1 br i1 %2, label %3, label %5 @@ -883,8 +883,13 @@ define void @load_zext_nneg_sext_cse(ptr %p) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: lh s0, 0(a0) -; RV32I-NEXT: bltz s0, .LBB50_2 -; RV32I-NEXT: # %bb.1: # %bb1 +; RV32I-NEXT: bgez s0, .LBB50_2 +; RV32I-NEXT: # %bb.1: # %bb2 +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; RV32I-NEXT: .LBB50_2: # %bb1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call bar_i16 ; RV32I-NEXT: mv a0, s0 @@ -892,11 +897,6 @@ define void @load_zext_nneg_sext_cse(ptr %p) nounwind { ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: tail bar_i32 -; RV32I-NEXT: .LBB50_2: # %bb2 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 -; RV32I-NEXT: ret ; ; RV64-LABEL: load_zext_nneg_sext_cse: ; RV64: # %bb.0: @@ -904,8 +904,13 @@ define void @load_zext_nneg_sext_cse(ptr %p) nounwind { ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64-NEXT: lh s0, 0(a0) -; RV64-NEXT: bltz s0, .LBB50_2 -; RV64-NEXT: # %bb.1: # %bb1 +; RV64-NEXT: bgez s0, .LBB50_2 +; RV64-NEXT: # %bb.1: # %bb2 +; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 16 +; RV64-NEXT: ret +; RV64-NEXT: .LBB50_2: # %bb1 ; RV64-NEXT: mv a0, s0 ; RV64-NEXT: call bar_i16 ; RV64-NEXT: mv a0, s0 @@ -913,11 +918,6 @@ define void @load_zext_nneg_sext_cse(ptr %p) nounwind { ; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: tail bar_i32 -; RV64-NEXT: .LBB50_2: # %bb2 -; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload -; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload -; RV64-NEXT: addi sp, sp, 16 -; RV64-NEXT: ret %load = load i16, ptr %p %zext = zext nneg i16 %load to i32 %cmp = icmp sgt i16 %load, -1 diff --git a/llvm/test/CodeGen/RISCV/simplify-condbr.ll b/llvm/test/CodeGen/RISCV/simplify-condbr.ll index 6dabd7d93cbc1..e5a3cc0d8e12f 100644 --- a/llvm/test/CodeGen/RISCV/simplify-condbr.ll +++ b/llvm/test/CodeGen/RISCV/simplify-condbr.ll @@ -30,7 +30,7 @@ define fastcc i32 @S_regrepeat(ptr %startposp, i32 %max, i8 %0, i1 %cmp343) noun ; CHECK-NEXT: bltu a1, a2, .LBB0_8 ; CHECK-NEXT: # %bb.2: # %do_exactf ; CHECK-NEXT: andi a3, a3, 1 -; CHECK-NEXT: beqz a3, .LBB0_10 +; CHECK-NEXT: beqz a3, .LBB0_8 ; CHECK-NEXT: # %bb.3: # %land.rhs251 ; CHECK-NEXT: lw zero, 0(zero) ; CHECK-NEXT: li s0, 1 @@ -62,8 +62,6 @@ define fastcc i32 @S_regrepeat(ptr %startposp, i32 %max, i8 %0, i1 %cmp343) noun ; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB0_10: -; CHECK-NEXT: j .LBB0_8 entry: switch i8 %0, label %if.else1492 [ i8 19, label %sw.bb336 @@ -113,30 +111,28 @@ define ptr @Perl_pp_refassign(ptr %PL_stack_sp, i1 %tobool.not, i1 %tobool3.not, ; CHECK-LABEL: Perl_pp_refassign: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi a1, a1, 1 -; CHECK-NEXT: beqz a1, .LBB1_3 +; CHECK-NEXT: beqz a1, .LBB1_4 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: andi a2, a2, 1 -; CHECK-NEXT: bnez a2, .LBB1_4 +; CHECK-NEXT: bnez a2, .LBB1_5 ; CHECK-NEXT: .LBB1_2: # %cond.true4 ; CHECK-NEXT: ld a0, 0(a0) ; CHECK-NEXT: snez a0, a0 -; CHECK-NEXT: bnez a0, .LBB1_5 -; CHECK-NEXT: j .LBB1_6 -; CHECK-NEXT: .LBB1_3: # %cond.true -; CHECK-NEXT: ld a1, 0(a0) -; CHECK-NEXT: andi a2, a2, 1 -; CHECK-NEXT: beqz a2, .LBB1_2 -; CHECK-NEXT: .LBB1_4: -; CHECK-NEXT: j .LBB1_6 -; CHECK-NEXT: .LBB1_5: # %sw.bb85 +; CHECK-NEXT: beqz a0, .LBB1_5 +; CHECK-NEXT: # %bb.3: # %sw.bb85 ; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: ld a0, 0(a1) ; CHECK-NEXT: call Perl_av_store ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: addi sp, sp, 16 -; CHECK-NEXT: .LBB1_6: # %common.ret +; CHECK-NEXT: j .LBB1_5 +; CHECK-NEXT: .LBB1_4: # %cond.true +; CHECK-NEXT: ld a1, 0(a0) +; CHECK-NEXT: andi a2, a2, 1 +; CHECK-NEXT: beqz a2, .LBB1_2 +; CHECK-NEXT: .LBB1_5: # %common.ret ; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/xcvbi.ll b/llvm/test/CodeGen/RISCV/xcvbi.ll index ca2e416e334f0..67ee49e371c6b 100644 --- a/llvm/test/CodeGen/RISCV/xcvbi.ll +++ b/llvm/test/CodeGen/RISCV/xcvbi.ll @@ -8,8 +8,7 @@ define i32 @beqimm(i32 %a) { ; CHECK_NOPT-LABEL: beqimm: ; CHECK_NOPT: # %bb.0: ; CHECK_NOPT-NEXT: cv.beqimm a0, 5, .LBB0_2 -; CHECK_NOPT-NEXT: j .LBB0_1 -; CHECK_NOPT-NEXT: .LBB0_1: # %f +; CHECK_NOPT-NEXT: # %bb.1: # %f ; CHECK_NOPT-NEXT: li a0, 0 ; CHECK_NOPT-NEXT: ret ; CHECK_NOPT-NEXT: .LBB0_2: # %t @@ -37,8 +36,7 @@ define i32 @bneimm(i32 %a) { ; CHECK_NOPT-LABEL: bneimm: ; CHECK_NOPT: # %bb.0: ; CHECK_NOPT-NEXT: cv.bneimm a0, 5, .LBB1_2 -; CHECK_NOPT-NEXT: j .LBB1_1 -; CHECK_NOPT-NEXT: .LBB1_1: # %f +; CHECK_NOPT-NEXT: # %bb.1: # %f ; CHECK_NOPT-NEXT: li a0, 0 ; CHECK_NOPT-NEXT: ret ; CHECK_NOPT-NEXT: .LBB1_2: # %t diff --git a/llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll b/llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll index 7353acd7228cd..d6b89a66f5cc3 100644 --- a/llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll +++ b/llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-drop-solution.ll @@ -8,30 +8,30 @@ define ptr @foo(ptr %a0, ptr %a1, i64 %a2) { ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vsetvli a4, a2, e8, m8, ta, ma -; CHECK-NEXT: bne a4, a2, .LBB0_2 -; CHECK-NEXT: # %bb.1: -; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma -; CHECK-NEXT: vle8.v v8, (a1) -; CHECK-NEXT: vse8.v v8, (a0) -; CHECK-NEXT: ret -; CHECK-NEXT: .LBB0_2: # %if.then +; CHECK-NEXT: beq a4, a2, .LBB0_4 +; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: add a2, a0, a2 ; CHECK-NEXT: sub a5, a2, a4 ; CHECK-NEXT: mv a3, a0 -; CHECK-NEXT: .LBB0_3: # %do.body +; CHECK-NEXT: .LBB0_2: # %do.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vle8.v v8, (a1) ; CHECK-NEXT: vse8.v v8, (a3) ; CHECK-NEXT: add a3, a3, a4 ; CHECK-NEXT: add a1, a1, a4 -; CHECK-NEXT: bltu a3, a5, .LBB0_3 -; CHECK-NEXT: # %bb.4: # %do.end +; CHECK-NEXT: bltu a3, a5, .LBB0_2 +; CHECK-NEXT: # %bb.3: # %do.end ; CHECK-NEXT: sub a2, a2, a3 ; CHECK-NEXT: vsetvli a2, a2, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: vle8.v v8, (a1) ; CHECK-NEXT: vse8.v v8, (a3) ; CHECK-NEXT: ret +; CHECK-NEXT: .LBB0_4: +; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma +; CHECK-NEXT: vle8.v v8, (a1) +; CHECK-NEXT: vse8.v v8, (a0) +; CHECK-NEXT: ret entry: %0 = ptrtoint ptr %a0 to i64 %1 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %a2, i64 0, i64 3)