diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index d65e921dfc660..81d58543b456f 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -24504,7 +24504,7 @@ RISCVTargetLowering::emitDynamicProbedAlloc(MachineInstr &MI, MachineFunction &MF = *MBB->getParent(); MachineBasicBlock::iterator MBBI = MI.getIterator(); DebugLoc DL = MBB->findDebugLoc(MBBI); - Register TargetReg = MI.getOperand(1).getReg(); + Register TargetReg = MI.getOperand(0).getReg(); const RISCVInstrInfo *TII = Subtarget.getInstrInfo(); bool IsRV64 = Subtarget.is64Bit(); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 4a4290483e94b..91903a9ea1f78 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -103,8 +103,7 @@ def riscv_add_tprel : SDNode<"RISCVISD::ADD_TPREL", SDTCisInt<0>]>>; def riscv_probed_alloca : SDNode<"RISCVISD::PROBED_ALLOCA", - SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, - SDTCisVT<0, i32>]>, + SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, [SDNPHasChain, SDNPMayStore]>; //===----------------------------------------------------------------------===// @@ -1456,17 +1455,17 @@ let hasSideEffects = 1, mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in { // Probed stack allocation of a constant size, used in function prologues when // stack-clash protection is enabled. def PROBED_STACKALLOC : Pseudo<(outs GPR:$sp), - (ins GPR:$scratch), + (ins GPR:$target), []>, Sched<[]>; def PROBED_STACKALLOC_RVV : Pseudo<(outs GPR:$sp), - (ins GPR:$scratch), + (ins GPR:$target), []>, Sched<[]>; let usesCustomInserter = 1 in -def PROBED_STACKALLOC_DYN : Pseudo<(outs GPR:$rd), - (ins GPR:$scratch), - [(set GPR:$rd, (riscv_probed_alloca GPR:$scratch))]>, +def PROBED_STACKALLOC_DYN : Pseudo<(outs), + (ins GPR:$target), + [(riscv_probed_alloca GPR:$target)]>, Sched<[]>; }