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[X86] splitVector - use collectConcatOps to find pre-split subvectors #142774

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Merged
merged 1 commit into from
Jun 4, 2025
Merged

[X86] splitVector - use collectConcatOps to find pre-split subvectors #142774

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12 changes: 6 additions & 6 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4349,13 +4349,13 @@ static std::pair<SDValue, SDValue> splitVector(SDValue Op, SelectionDAG &DAG,
assert((NumElems % 2) == 0 && (SizeInBits % 2) == 0 &&
"Can't split odd sized vector");

if (Op.getOpcode() == ISD::CONCAT_VECTORS) {
assert((Op.getNumOperands() % 2) == 0 &&
"Can't split odd sized vector concat");
unsigned HalfOps = Op.getNumOperands() / 2;
SmallVector<SDValue, 4> SubOps;
if (collectConcatOps(Op.getNode(), SubOps, DAG)) {
assert((SubOps.size() % 2) == 0 && "Can't split odd sized vector concat");
unsigned HalfOps = SubOps.size() / 2;
EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
SmallVector<SDValue, 2> LoOps(Op->op_begin(), Op->op_begin() + HalfOps);
SmallVector<SDValue, 2> HiOps(Op->op_begin() + HalfOps, Op->op_end());
SmallVector<SDValue, 2> LoOps(SubOps.begin(), SubOps.begin() + HalfOps);
SmallVector<SDValue, 2> HiOps(SubOps.begin() + HalfOps, SubOps.end());
SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, LoOps);
SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, HiOps);
return std::make_pair(Lo, Hi);
Expand Down
84 changes: 40 additions & 44 deletions llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1105,19 +1105,18 @@ define void @load_i16_stride2_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) no
; AVX512-VL-NEXT: vmovdqa64 64(%rdi), %zmm1
; AVX512-VL-NEXT: vmovdqa64 128(%rdi), %zmm2
; AVX512-VL-NEXT: vmovdqa64 192(%rdi), %zmm3
; AVX512-VL-NEXT: vpmovdw %zmm1, %ymm4
; AVX512-VL-NEXT: vpsrld $16, %zmm1, %zmm1
; AVX512-VL-NEXT: vpsrld $16, %zmm0, %zmm5
; AVX512-VL-NEXT: vpsrld $16, %zmm3, %zmm6
; AVX512-VL-NEXT: vpsrld $16, %zmm2, %zmm7
; AVX512-VL-NEXT: vpsrld $16, %zmm0, %zmm4
; AVX512-VL-NEXT: vpsrld $16, %zmm1, %zmm5
; AVX512-VL-NEXT: vpsrld $16, %zmm2, %zmm6
; AVX512-VL-NEXT: vpsrld $16, %zmm3, %zmm7
; AVX512-VL-NEXT: vpmovdw %zmm1, 32(%rsi)
; AVX512-VL-NEXT: vpmovdw %zmm0, (%rsi)
; AVX512-VL-NEXT: vmovdqa %ymm4, 32(%rsi)
; AVX512-VL-NEXT: vpmovdw %zmm2, 64(%rsi)
; AVX512-VL-NEXT: vpmovdw %zmm3, 96(%rsi)
; AVX512-VL-NEXT: vpmovdw %zmm7, 64(%rdx)
; AVX512-VL-NEXT: vpmovdw %zmm6, 96(%rdx)
; AVX512-VL-NEXT: vpmovdw %zmm5, (%rdx)
; AVX512-VL-NEXT: vpmovdw %zmm1, 32(%rdx)
; AVX512-VL-NEXT: vpmovdw %zmm2, 64(%rsi)
; AVX512-VL-NEXT: vpmovdw %zmm7, 96(%rdx)
; AVX512-VL-NEXT: vpmovdw %zmm6, 64(%rdx)
; AVX512-VL-NEXT: vpmovdw %zmm5, 32(%rdx)
; AVX512-VL-NEXT: vpmovdw %zmm4, (%rdx)
; AVX512-VL-NEXT: vzeroupper
; AVX512-VL-NEXT: retq
;
Expand All @@ -1127,19 +1126,18 @@ define void @load_i16_stride2_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) no
; AVX512-FCP-NEXT: vmovdqa64 64(%rdi), %zmm1
; AVX512-FCP-NEXT: vmovdqa64 128(%rdi), %zmm2
; AVX512-FCP-NEXT: vmovdqa64 192(%rdi), %zmm3
; AVX512-FCP-NEXT: vpmovdw %zmm1, %ymm4
; AVX512-FCP-NEXT: vpsrld $16, %zmm1, %zmm1
; AVX512-FCP-NEXT: vpsrld $16, %zmm0, %zmm5
; AVX512-FCP-NEXT: vpsrld $16, %zmm3, %zmm6
; AVX512-FCP-NEXT: vpsrld $16, %zmm2, %zmm7
; AVX512-FCP-NEXT: vpsrld $16, %zmm0, %zmm4
; AVX512-FCP-NEXT: vpsrld $16, %zmm1, %zmm5
; AVX512-FCP-NEXT: vpsrld $16, %zmm2, %zmm6
; AVX512-FCP-NEXT: vpsrld $16, %zmm3, %zmm7
; AVX512-FCP-NEXT: vpmovdw %zmm1, 32(%rsi)
; AVX512-FCP-NEXT: vpmovdw %zmm0, (%rsi)
; AVX512-FCP-NEXT: vmovdqa %ymm4, 32(%rsi)
; AVX512-FCP-NEXT: vpmovdw %zmm2, 64(%rsi)
; AVX512-FCP-NEXT: vpmovdw %zmm3, 96(%rsi)
; AVX512-FCP-NEXT: vpmovdw %zmm7, 64(%rdx)
; AVX512-FCP-NEXT: vpmovdw %zmm6, 96(%rdx)
; AVX512-FCP-NEXT: vpmovdw %zmm5, (%rdx)
; AVX512-FCP-NEXT: vpmovdw %zmm1, 32(%rdx)
; AVX512-FCP-NEXT: vpmovdw %zmm2, 64(%rsi)
; AVX512-FCP-NEXT: vpmovdw %zmm7, 96(%rdx)
; AVX512-FCP-NEXT: vpmovdw %zmm6, 64(%rdx)
; AVX512-FCP-NEXT: vpmovdw %zmm5, 32(%rdx)
; AVX512-FCP-NEXT: vpmovdw %zmm4, (%rdx)
; AVX512-FCP-NEXT: vzeroupper
; AVX512-FCP-NEXT: retq
;
Expand All @@ -1149,19 +1147,18 @@ define void @load_i16_stride2_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) no
; AVX512DQ-NEXT: vmovdqa64 64(%rdi), %zmm1
; AVX512DQ-NEXT: vmovdqa64 128(%rdi), %zmm2
; AVX512DQ-NEXT: vmovdqa64 192(%rdi), %zmm3
; AVX512DQ-NEXT: vpmovdw %zmm1, %ymm4
; AVX512DQ-NEXT: vpsrld $16, %zmm1, %zmm1
; AVX512DQ-NEXT: vpsrld $16, %zmm0, %zmm5
; AVX512DQ-NEXT: vpsrld $16, %zmm3, %zmm6
; AVX512DQ-NEXT: vpsrld $16, %zmm2, %zmm7
; AVX512DQ-NEXT: vpsrld $16, %zmm0, %zmm4
; AVX512DQ-NEXT: vpsrld $16, %zmm1, %zmm5
; AVX512DQ-NEXT: vpsrld $16, %zmm2, %zmm6
; AVX512DQ-NEXT: vpsrld $16, %zmm3, %zmm7
; AVX512DQ-NEXT: vpmovdw %zmm1, 32(%rsi)
; AVX512DQ-NEXT: vpmovdw %zmm0, (%rsi)
; AVX512DQ-NEXT: vmovdqa %ymm4, 32(%rsi)
; AVX512DQ-NEXT: vpmovdw %zmm2, 64(%rsi)
; AVX512DQ-NEXT: vpmovdw %zmm3, 96(%rsi)
; AVX512DQ-NEXT: vpmovdw %zmm7, 64(%rdx)
; AVX512DQ-NEXT: vpmovdw %zmm6, 96(%rdx)
; AVX512DQ-NEXT: vpmovdw %zmm5, (%rdx)
; AVX512DQ-NEXT: vpmovdw %zmm1, 32(%rdx)
; AVX512DQ-NEXT: vpmovdw %zmm2, 64(%rsi)
; AVX512DQ-NEXT: vpmovdw %zmm7, 96(%rdx)
; AVX512DQ-NEXT: vpmovdw %zmm6, 64(%rdx)
; AVX512DQ-NEXT: vpmovdw %zmm5, 32(%rdx)
; AVX512DQ-NEXT: vpmovdw %zmm4, (%rdx)
; AVX512DQ-NEXT: vzeroupper
; AVX512DQ-NEXT: retq
;
Expand All @@ -1171,19 +1168,18 @@ define void @load_i16_stride2_vf64(ptr %in.vec, ptr %out.vec0, ptr %out.vec1) no
; AVX512DQ-FCP-NEXT: vmovdqa64 64(%rdi), %zmm1
; AVX512DQ-FCP-NEXT: vmovdqa64 128(%rdi), %zmm2
; AVX512DQ-FCP-NEXT: vmovdqa64 192(%rdi), %zmm3
; AVX512DQ-FCP-NEXT: vpmovdw %zmm1, %ymm4
; AVX512DQ-FCP-NEXT: vpsrld $16, %zmm1, %zmm1
; AVX512DQ-FCP-NEXT: vpsrld $16, %zmm0, %zmm5
; AVX512DQ-FCP-NEXT: vpsrld $16, %zmm3, %zmm6
; AVX512DQ-FCP-NEXT: vpsrld $16, %zmm2, %zmm7
; AVX512DQ-FCP-NEXT: vpsrld $16, %zmm0, %zmm4
; AVX512DQ-FCP-NEXT: vpsrld $16, %zmm1, %zmm5
; AVX512DQ-FCP-NEXT: vpsrld $16, %zmm2, %zmm6
; AVX512DQ-FCP-NEXT: vpsrld $16, %zmm3, %zmm7
; AVX512DQ-FCP-NEXT: vpmovdw %zmm1, 32(%rsi)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm0, (%rsi)
; AVX512DQ-FCP-NEXT: vmovdqa %ymm4, 32(%rsi)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm2, 64(%rsi)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm3, 96(%rsi)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm7, 64(%rdx)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm6, 96(%rdx)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm5, (%rdx)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm1, 32(%rdx)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm2, 64(%rsi)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm7, 96(%rdx)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm6, 64(%rdx)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm5, 32(%rdx)
; AVX512DQ-FCP-NEXT: vpmovdw %zmm4, (%rdx)
; AVX512DQ-FCP-NEXT: vzeroupper
; AVX512DQ-FCP-NEXT: retq
;
Expand Down
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