diff --git a/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp b/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp index 39603b92cc2f7..4beca19c611dd 100644 --- a/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp +++ b/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp @@ -264,12 +264,6 @@ bool RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad( {ResVTy, PtrTy, XLenTy}, {LI->getPointerOperand(), Mask, VL}); } else { - static const Intrinsic::ID IntrIds[] = { - Intrinsic::riscv_vlseg2, Intrinsic::riscv_vlseg3, - Intrinsic::riscv_vlseg4, Intrinsic::riscv_vlseg5, - Intrinsic::riscv_vlseg6, Intrinsic::riscv_vlseg7, - Intrinsic::riscv_vlseg8}; - unsigned SEW = DL.getTypeSizeInBits(ResVTy->getElementType()); unsigned NumElts = ResVTy->getElementCount().getKnownMinValue(); Type *VecTupTy = TargetExtType::get( @@ -277,13 +271,23 @@ bool RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad( ScalableVectorType::get(Type::getInt8Ty(LI->getContext()), NumElts * SEW / 8), Factor); - Value *VL = Constant::getAllOnesValue(XLenTy); + Value *Mask = Builder.getAllOnesMask(ResVTy->getElementCount()); + + Function *VlsegNFunc = Intrinsic::getOrInsertDeclaration( + LI->getModule(), ScalableVlsegIntrIds[Factor - 2], + {VecTupTy, PtrTy, Mask->getType(), VL->getType()}); - Value *Vlseg = Builder.CreateIntrinsic( - IntrIds[Factor - 2], {VecTupTy, PtrTy, XLenTy}, - {PoisonValue::get(VecTupTy), LI->getPointerOperand(), VL, - ConstantInt::get(XLenTy, Log2_64(SEW))}); + Value *Operands[] = { + PoisonValue::get(VecTupTy), + LI->getPointerOperand(), + Mask, + VL, + ConstantInt::get(XLenTy, + RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC), + ConstantInt::get(XLenTy, Log2_64(SEW))}; + + CallInst *Vlseg = Builder.CreateCall(VlsegNFunc, Operands); SmallVector AggrTypes{Factor, ResVTy}; Return = PoisonValue::get(StructType::get(LI->getContext(), AggrTypes)); @@ -338,12 +342,6 @@ bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore( Builder.CreateCall(VssegNFunc, Ops); } else { - static const Intrinsic::ID IntrIds[] = { - Intrinsic::riscv_vsseg2, Intrinsic::riscv_vsseg3, - Intrinsic::riscv_vsseg4, Intrinsic::riscv_vsseg5, - Intrinsic::riscv_vsseg6, Intrinsic::riscv_vsseg7, - Intrinsic::riscv_vsseg8}; - unsigned SEW = DL.getTypeSizeInBits(InVTy->getElementType()); unsigned NumElts = InVTy->getElementCount().getKnownMinValue(); Type *VecTupTy = TargetExtType::get( @@ -352,10 +350,8 @@ bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore( NumElts * SEW / 8), Factor); - Function *VssegNFunc = Intrinsic::getOrInsertDeclaration( - SI->getModule(), IntrIds[Factor - 2], {VecTupTy, PtrTy, XLenTy}); - Value *VL = Constant::getAllOnesValue(XLenTy); + Value *Mask = Builder.getAllOnesMask(InVTy->getElementCount()); Value *StoredVal = PoisonValue::get(VecTupTy); for (unsigned i = 0; i < Factor; ++i) @@ -363,8 +359,14 @@ bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore( Intrinsic::riscv_tuple_insert, {VecTupTy, InVTy}, {StoredVal, InterleaveValues[i], Builder.getInt32(i)}); - Builder.CreateCall(VssegNFunc, {StoredVal, SI->getPointerOperand(), VL, - ConstantInt::get(XLenTy, Log2_64(SEW))}); + Function *VssegNFunc = Intrinsic::getOrInsertDeclaration( + SI->getModule(), ScalableVssegIntrIds[Factor - 2], + {VecTupTy, PtrTy, Mask->getType(), VL->getType()}); + + Value *Operands[] = {StoredVal, SI->getPointerOperand(), Mask, VL, + ConstantInt::get(XLenTy, Log2_64(SEW))}; + + Builder.CreateCall(VssegNFunc, Operands); } return true; @@ -468,14 +470,12 @@ bool RISCVTargetLowering::lowerInterleavedVPLoad( NumElts * SEW / 8), Factor); - Value *PoisonVal = PoisonValue::get(VecTupTy); - Function *VlsegNFunc = Intrinsic::getOrInsertDeclaration( Load->getModule(), ScalableVlsegIntrIds[Factor - 2], {VecTupTy, PtrTy, Mask->getType(), EVL->getType()}); Value *Operands[] = { - PoisonVal, + PoisonValue::get(VecTupTy), Load->getArgOperand(0), Mask, EVL, diff --git a/llvm/test/Transforms/InterleavedAccess/RISCV/addrspace.ll b/llvm/test/Transforms/InterleavedAccess/RISCV/addrspace.ll index 8d156cfd4e526..f8e4ce9548147 100644 --- a/llvm/test/Transforms/InterleavedAccess/RISCV/addrspace.ll +++ b/llvm/test/Transforms/InterleavedAccess/RISCV/addrspace.ll @@ -20,7 +20,7 @@ define void @load_factor2(ptr addrspace(1) %ptr) { define void @load_factor2_vscale(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define void @load_factor2_vscale( ; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p1.i64(target("riscv.vector.tuple", , 2) poison, ptr addrspace(1) [[PTR]], i64 -1, i64 5) +; CHECK-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p1.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr addrspace(1) [[PTR]], splat (i1 true), i64 -1, i64 3, i64 5) ; CHECK-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv8i32.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2) [[TMP1]], i32 0) ; CHECK-NEXT: [[TMP3:%.*]] = insertvalue { , } poison, [[TMP2]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv8i32.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2) [[TMP1]], i32 1) diff --git a/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll b/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll index 72c1f22032bb7..672e94962da6d 100644 --- a/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll +++ b/llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll @@ -25,7 +25,7 @@ define void @load_factor2(ptr %ptr) { define void @load_factor2_vscale(ptr %ptr) { ; RV32-LABEL: @load_factor2_vscale( -; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i32(target("riscv.vector.tuple", , 2) poison, ptr [[PTR:%.*]], i32 -1, i32 5) +; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i32(target("riscv.vector.tuple", , 2) poison, ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3, i32 5) ; RV32-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv8i32.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2) [[TMP1]], i32 0) ; RV32-NEXT: [[TMP3:%.*]] = insertvalue { , } poison, [[TMP2]], 0 ; RV32-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv8i32.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2) [[TMP1]], i32 1) @@ -35,7 +35,7 @@ define void @load_factor2_vscale(ptr %ptr) { ; RV32-NEXT: ret void ; ; RV64-LABEL: @load_factor2_vscale( -; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv32i8_2t.p0.i64(target("riscv.vector.tuple", , 2) poison, ptr [[PTR:%.*]], i64 -1, i64 5) +; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv32i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) poison, ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3, i64 5) ; RV64-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv8i32.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2) [[TMP1]], i32 0) ; RV64-NEXT: [[TMP3:%.*]] = insertvalue { , } poison, [[TMP2]], 0 ; RV64-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv8i32.triscv.vector.tuple_nxv32i8_2t(target("riscv.vector.tuple", , 2) [[TMP1]], i32 1) @@ -75,7 +75,7 @@ define void @load_factor3(ptr %ptr) { define void @load_factor3_vscale(ptr %ptr) { ; RV32-LABEL: @load_factor3_vscale( -; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i32(target("riscv.vector.tuple", , 3) poison, ptr [[PTR:%.*]], i32 -1, i32 5) +; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i32(target("riscv.vector.tuple", , 3) poison, ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3, i32 5) ; RV32-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", , 3) [[TMP1]], i32 0) ; RV32-NEXT: [[TMP3:%.*]] = insertvalue { , , } poison, [[TMP2]], 0 ; RV32-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", , 3) [[TMP1]], i32 1) @@ -88,7 +88,7 @@ define void @load_factor3_vscale(ptr %ptr) { ; RV32-NEXT: ret void ; ; RV64-LABEL: @load_factor3_vscale( -; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) poison, ptr [[PTR:%.*]], i64 -1, i64 5) +; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 3) poison, ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3, i64 5) ; RV64-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", , 3) [[TMP1]], i32 0) ; RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , } poison, [[TMP2]], 0 ; RV64-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_3t(target("riscv.vector.tuple", , 3) [[TMP1]], i32 1) @@ -135,7 +135,7 @@ define void @load_factor4(ptr %ptr) { define void @load_factor4_vscale(ptr %ptr) { ; RV32-LABEL: @load_factor4_vscale( -; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i32(target("riscv.vector.tuple", , 4) poison, ptr [[PTR:%.*]], i32 -1, i32 5) +; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i32(target("riscv.vector.tuple", , 4) poison, ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3, i32 5) ; RV32-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv4i32.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", , 4) [[TMP1]], i32 0) ; RV32-NEXT: [[TMP3:%.*]] = insertvalue { , , , } poison, [[TMP2]], 0 ; RV32-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv4i32.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", , 4) [[TMP1]], i32 1) @@ -151,7 +151,7 @@ define void @load_factor4_vscale(ptr %ptr) { ; RV32-NEXT: ret void ; ; RV64-LABEL: @load_factor4_vscale( -; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv16i8_4t.p0.i64(target("riscv.vector.tuple", , 4) poison, ptr [[PTR:%.*]], i64 -1, i64 5) +; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv16i8_4t.p0.nxv4i1.i64(target("riscv.vector.tuple", , 4) poison, ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3, i64 5) ; RV64-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv4i32.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", , 4) [[TMP1]], i32 0) ; RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } poison, [[TMP2]], 0 ; RV64-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv4i32.triscv.vector.tuple_nxv16i8_4t(target("riscv.vector.tuple", , 4) [[TMP1]], i32 1) @@ -205,7 +205,7 @@ define void @load_factor5(ptr %ptr) { define void @load_factor5_vscale(ptr %ptr) { ; RV32-LABEL: @load_factor5_vscale( -; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i32(target("riscv.vector.tuple", , 5) poison, ptr [[PTR:%.*]], i32 -1, i32 5) +; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i32(target("riscv.vector.tuple", , 5) poison, ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3, i32 5) ; RV32-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", , 5) [[TMP1]], i32 0) ; RV32-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } poison, [[TMP2]], 0 ; RV32-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", , 5) [[TMP1]], i32 1) @@ -224,7 +224,7 @@ define void @load_factor5_vscale(ptr %ptr) { ; RV32-NEXT: ret void ; ; RV64-LABEL: @load_factor5_vscale( -; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) poison, ptr [[PTR:%.*]], i64 -1, i64 5) +; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 5) poison, ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3, i64 5) ; RV64-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", , 5) [[TMP1]], i32 0) ; RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } poison, [[TMP2]], 0 ; RV64-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_5t(target("riscv.vector.tuple", , 5) [[TMP1]], i32 1) @@ -285,7 +285,7 @@ define void @load_factor6(ptr %ptr) { define void @load_factor6_vscale(ptr %ptr) { ; RV32-LABEL: @load_factor6_vscale( -; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i32(target("riscv.vector.tuple", , 6) poison, ptr [[PTR:%.*]], i32 -1, i32 5) +; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i32(target("riscv.vector.tuple", , 6) poison, ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3, i32 5) ; RV32-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", , 6) [[TMP1]], i32 0) ; RV32-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } poison, [[TMP2]], 0 ; RV32-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", , 6) [[TMP1]], i32 1) @@ -307,7 +307,7 @@ define void @load_factor6_vscale(ptr %ptr) { ; RV32-NEXT: ret void ; ; RV64-LABEL: @load_factor6_vscale( -; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) poison, ptr [[PTR:%.*]], i64 -1, i64 5) +; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 6) poison, ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3, i64 5) ; RV64-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", , 6) [[TMP1]], i32 0) ; RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } poison, [[TMP2]], 0 ; RV64-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_6t(target("riscv.vector.tuple", , 6) [[TMP1]], i32 1) @@ -375,7 +375,7 @@ define void @load_factor7(ptr %ptr) { define void @load_factor7_vscale(ptr %ptr) { ; RV32-LABEL: @load_factor7_vscale( -; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i32(target("riscv.vector.tuple", , 7) poison, ptr [[PTR:%.*]], i32 -1, i32 5) +; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i32(target("riscv.vector.tuple", , 7) poison, ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3, i32 5) ; RV32-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", , 7) [[TMP1]], i32 0) ; RV32-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } poison, [[TMP2]], 0 ; RV32-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", , 7) [[TMP1]], i32 1) @@ -400,7 +400,7 @@ define void @load_factor7_vscale(ptr %ptr) { ; RV32-NEXT: ret void ; ; RV64-LABEL: @load_factor7_vscale( -; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) poison, ptr [[PTR:%.*]], i64 -1, i64 5) +; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 7) poison, ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3, i64 5) ; RV64-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", , 7) [[TMP1]], i32 0) ; RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } poison, [[TMP2]], 0 ; RV64-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_7t(target("riscv.vector.tuple", , 7) [[TMP1]], i32 1) @@ -475,7 +475,7 @@ define void @load_factor8(ptr %ptr) { define void @load_factor8_vscale(ptr %ptr) { ; RV32-LABEL: @load_factor8_vscale( -; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i32(target("riscv.vector.tuple", , 8) poison, ptr [[PTR:%.*]], i32 -1, i32 5) +; RV32-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i32(target("riscv.vector.tuple", , 8) poison, ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3, i32 5) ; RV32-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", , 8) [[TMP1]], i32 0) ; RV32-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } poison, [[TMP2]], 0 ; RV32-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", , 8) [[TMP1]], i32 1) @@ -503,7 +503,7 @@ define void @load_factor8_vscale(ptr %ptr) { ; RV32-NEXT: ret void ; ; RV64-LABEL: @load_factor8_vscale( -; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) poison, ptr [[PTR:%.*]], i64 -1, i64 5) +; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv2i1.i64(target("riscv.vector.tuple", , 8) poison, ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3, i64 5) ; RV64-NEXT: [[TMP2:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", , 8) [[TMP1]], i32 0) ; RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } poison, [[TMP2]], 0 ; RV64-NEXT: [[TMP4:%.*]] = call @llvm.riscv.tuple.extract.nxv2i32.triscv.vector.tuple_nxv8i8_8t(target("riscv.vector.tuple", , 8) [[TMP1]], i32 1) @@ -566,13 +566,13 @@ define void @store_factor2_vscale(ptr %ptr, %v0, , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_2t.nxv8i8(target("riscv.vector.tuple", , 2) poison, [[V0:%.*]], i32 0) ; RV32-NEXT: [[TMP2:%.*]] = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_2t.nxv8i8(target("riscv.vector.tuple", , 2) [[TMP1]], [[V1:%.*]], i32 1) -; RV32-NEXT: call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i32(target("riscv.vector.tuple", , 2) [[TMP2]], ptr [[PTR:%.*]], i32 -1, i32 3) +; RV32-NEXT: call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i32(target("riscv.vector.tuple", , 2) [[TMP2]], ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3) ; RV32-NEXT: ret void ; ; RV64-LABEL: @store_factor2_vscale( ; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_2t.nxv8i8(target("riscv.vector.tuple", , 2) poison, [[V0:%.*]], i32 0) ; RV64-NEXT: [[TMP2:%.*]] = call target("riscv.vector.tuple", , 2) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_2t.nxv8i8(target("riscv.vector.tuple", , 2) [[TMP1]], [[V1:%.*]], i32 1) -; RV64-NEXT: call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv8i8_2t.p0.i64(target("riscv.vector.tuple", , 2) [[TMP2]], ptr [[PTR:%.*]], i64 -1, i64 3) +; RV64-NEXT: call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv8i8_2t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 2) [[TMP2]], ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3) ; RV64-NEXT: ret void ; %interleaved.vec = call @llvm.vector.interleave2.nxv8i8( %v0, %v1) @@ -611,14 +611,14 @@ define void @store_factor3_vscale(ptr %ptr, %v0, , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv8i8(target("riscv.vector.tuple", , 3) poison, [[V0:%.*]], i32 0) ; RV32-NEXT: [[TMP2:%.*]] = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv8i8(target("riscv.vector.tuple", , 3) [[TMP1]], [[V1:%.*]], i32 1) ; RV32-NEXT: [[TMP3:%.*]] = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv8i8(target("riscv.vector.tuple", , 3) [[TMP2]], [[V2:%.*]], i32 2) -; RV32-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i32(target("riscv.vector.tuple", , 3) [[TMP3]], ptr [[PTR:%.*]], i32 -1, i32 3) +; RV32-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i32(target("riscv.vector.tuple", , 3) [[TMP3]], ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3) ; RV32-NEXT: ret void ; ; RV64-LABEL: @store_factor3_vscale( ; RV64-NEXT: [[TMP1:%.*]] = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv8i8(target("riscv.vector.tuple", , 3) poison, [[V0:%.*]], i32 0) ; RV64-NEXT: [[TMP2:%.*]] = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv8i8(target("riscv.vector.tuple", , 3) [[TMP1]], [[V1:%.*]], i32 1) ; RV64-NEXT: [[TMP3:%.*]] = call target("riscv.vector.tuple", , 3) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_3t.nxv8i8(target("riscv.vector.tuple", , 3) [[TMP2]], [[V2:%.*]], i32 2) -; RV64-NEXT: call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv8i8_3t.p0.i64(target("riscv.vector.tuple", , 3) [[TMP3]], ptr [[PTR:%.*]], i64 -1, i64 3) +; RV64-NEXT: call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv8i8_3t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 3) [[TMP3]], ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3) ; RV64-NEXT: ret void ; %interleaved.vec = call @llvm.vector.interleave3.nxv8i8( %v0, %v1, %v2) @@ -660,7 +660,7 @@ define void @store_factor4_vscale(ptr %ptr, %v0, , 4) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_4t.nxv8i8(target("riscv.vector.tuple", , 4) [[TMP1]], [[V1:%.*]], i32 1) ; RV32-NEXT: [[TMP3:%.*]] = call target("riscv.vector.tuple", , 4) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_4t.nxv8i8(target("riscv.vector.tuple", , 4) [[TMP2]], [[V2:%.*]], i32 2) ; RV32-NEXT: [[TMP4:%.*]] = call target("riscv.vector.tuple", , 4) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_4t.nxv8i8(target("riscv.vector.tuple", , 4) [[TMP3]], [[V3:%.*]], i32 3) -; RV32-NEXT: call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i32(target("riscv.vector.tuple", , 4) [[TMP4]], ptr [[PTR:%.*]], i32 -1, i32 3) +; RV32-NEXT: call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i32(target("riscv.vector.tuple", , 4) [[TMP4]], ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3) ; RV32-NEXT: ret void ; ; RV64-LABEL: @store_factor4_vscale( @@ -668,7 +668,7 @@ define void @store_factor4_vscale(ptr %ptr, %v0, , 4) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_4t.nxv8i8(target("riscv.vector.tuple", , 4) [[TMP1]], [[V1:%.*]], i32 1) ; RV64-NEXT: [[TMP3:%.*]] = call target("riscv.vector.tuple", , 4) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_4t.nxv8i8(target("riscv.vector.tuple", , 4) [[TMP2]], [[V2:%.*]], i32 2) ; RV64-NEXT: [[TMP4:%.*]] = call target("riscv.vector.tuple", , 4) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_4t.nxv8i8(target("riscv.vector.tuple", , 4) [[TMP3]], [[V3:%.*]], i32 3) -; RV64-NEXT: call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv8i8_4t.p0.i64(target("riscv.vector.tuple", , 4) [[TMP4]], ptr [[PTR:%.*]], i64 -1, i64 3) +; RV64-NEXT: call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv8i8_4t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 4) [[TMP4]], ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3) ; RV64-NEXT: ret void ; %interleaved.vec = call @llvm.vector.interleave4.nxv8i8( %v0, %v1, %v2, %v3) @@ -683,7 +683,7 @@ define void @store_factor5_vscale(ptr %ptr, %v0, , 5) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_5t.nxv8i8(target("riscv.vector.tuple", , 5) [[TMP2]], [[V2:%.*]], i32 2) ; RV32-NEXT: [[TMP4:%.*]] = call target("riscv.vector.tuple", , 5) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_5t.nxv8i8(target("riscv.vector.tuple", , 5) [[TMP3]], [[V3:%.*]], i32 3) ; RV32-NEXT: [[TMP5:%.*]] = call target("riscv.vector.tuple", , 5) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_5t.nxv8i8(target("riscv.vector.tuple", , 5) [[TMP4]], [[V4:%.*]], i32 4) -; RV32-NEXT: call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i32(target("riscv.vector.tuple", , 5) [[TMP5]], ptr [[PTR:%.*]], i32 -1, i32 3) +; RV32-NEXT: call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i32(target("riscv.vector.tuple", , 5) [[TMP5]], ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3) ; RV32-NEXT: ret void ; ; RV64-LABEL: @store_factor5_vscale( @@ -692,7 +692,7 @@ define void @store_factor5_vscale(ptr %ptr, %v0, , 5) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_5t.nxv8i8(target("riscv.vector.tuple", , 5) [[TMP2]], [[V2:%.*]], i32 2) ; RV64-NEXT: [[TMP4:%.*]] = call target("riscv.vector.tuple", , 5) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_5t.nxv8i8(target("riscv.vector.tuple", , 5) [[TMP3]], [[V3:%.*]], i32 3) ; RV64-NEXT: [[TMP5:%.*]] = call target("riscv.vector.tuple", , 5) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_5t.nxv8i8(target("riscv.vector.tuple", , 5) [[TMP4]], [[V4:%.*]], i32 4) -; RV64-NEXT: call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv8i8_5t.p0.i64(target("riscv.vector.tuple", , 5) [[TMP5]], ptr [[PTR:%.*]], i64 -1, i64 3) +; RV64-NEXT: call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv8i8_5t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 5) [[TMP5]], ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3) ; RV64-NEXT: ret void ; %interleaved.vec = call @llvm.vector.interleave5.nxv8i8( %v0, %v1, %v2, %v3, %v4) @@ -780,7 +780,7 @@ define void @store_factor6_vscale(ptr %ptr, %v0, , 6) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_6t.nxv8i8(target("riscv.vector.tuple", , 6) [[TMP3]], [[V3:%.*]], i32 3) ; RV32-NEXT: [[TMP5:%.*]] = call target("riscv.vector.tuple", , 6) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_6t.nxv8i8(target("riscv.vector.tuple", , 6) [[TMP4]], [[V4:%.*]], i32 4) ; RV32-NEXT: [[TMP6:%.*]] = call target("riscv.vector.tuple", , 6) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_6t.nxv8i8(target("riscv.vector.tuple", , 6) [[TMP5]], [[V5:%.*]], i32 5) -; RV32-NEXT: call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i32(target("riscv.vector.tuple", , 6) [[TMP6]], ptr [[PTR:%.*]], i32 -1, i32 3) +; RV32-NEXT: call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i32(target("riscv.vector.tuple", , 6) [[TMP6]], ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3) ; RV32-NEXT: ret void ; ; RV64-LABEL: @store_factor6_vscale( @@ -790,7 +790,7 @@ define void @store_factor6_vscale(ptr %ptr, %v0, , 6) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_6t.nxv8i8(target("riscv.vector.tuple", , 6) [[TMP3]], [[V3:%.*]], i32 3) ; RV64-NEXT: [[TMP5:%.*]] = call target("riscv.vector.tuple", , 6) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_6t.nxv8i8(target("riscv.vector.tuple", , 6) [[TMP4]], [[V4:%.*]], i32 4) ; RV64-NEXT: [[TMP6:%.*]] = call target("riscv.vector.tuple", , 6) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_6t.nxv8i8(target("riscv.vector.tuple", , 6) [[TMP5]], [[V5:%.*]], i32 5) -; RV64-NEXT: call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv8i8_6t.p0.i64(target("riscv.vector.tuple", , 6) [[TMP6]], ptr [[PTR:%.*]], i64 -1, i64 3) +; RV64-NEXT: call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv8i8_6t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 6) [[TMP6]], ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3) ; RV64-NEXT: ret void ; %interleaved.vec = call @llvm.vector.interleave6.nxv8i8( %v0, %v1, %v2, %v3, %v4, %v5) @@ -807,7 +807,7 @@ define void @store_factor7_vscale(ptr %ptr, %v0, , 7) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_7t.nxv8i8(target("riscv.vector.tuple", , 7) [[TMP4]], [[V4:%.*]], i32 4) ; RV32-NEXT: [[TMP6:%.*]] = call target("riscv.vector.tuple", , 7) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_7t.nxv8i8(target("riscv.vector.tuple", , 7) [[TMP5]], [[V5:%.*]], i32 5) ; RV32-NEXT: [[TMP7:%.*]] = call target("riscv.vector.tuple", , 7) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_7t.nxv8i8(target("riscv.vector.tuple", , 7) [[TMP6]], [[V6:%.*]], i32 6) -; RV32-NEXT: call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i32(target("riscv.vector.tuple", , 7) [[TMP7]], ptr [[PTR:%.*]], i32 -1, i32 3) +; RV32-NEXT: call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i32(target("riscv.vector.tuple", , 7) [[TMP7]], ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3) ; RV32-NEXT: ret void ; ; RV64-LABEL: @store_factor7_vscale( @@ -818,7 +818,7 @@ define void @store_factor7_vscale(ptr %ptr, %v0, , 7) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_7t.nxv8i8(target("riscv.vector.tuple", , 7) [[TMP4]], [[V4:%.*]], i32 4) ; RV64-NEXT: [[TMP6:%.*]] = call target("riscv.vector.tuple", , 7) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_7t.nxv8i8(target("riscv.vector.tuple", , 7) [[TMP5]], [[V5:%.*]], i32 5) ; RV64-NEXT: [[TMP7:%.*]] = call target("riscv.vector.tuple", , 7) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_7t.nxv8i8(target("riscv.vector.tuple", , 7) [[TMP6]], [[V6:%.*]], i32 6) -; RV64-NEXT: call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv8i8_7t.p0.i64(target("riscv.vector.tuple", , 7) [[TMP7]], ptr [[PTR:%.*]], i64 -1, i64 3) +; RV64-NEXT: call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv8i8_7t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 7) [[TMP7]], ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3) ; RV64-NEXT: ret void ; %interleaved.vec = call @llvm.vector.interleave7.nxv8i8( %v0, %v1, %v2, %v3, %v4, %v5, %v6) @@ -836,7 +836,7 @@ define void @store_factor8_vscale(ptr %ptr, %v0, , 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv8i8(target("riscv.vector.tuple", , 8) [[TMP5]], [[V5:%.*]], i32 5) ; RV32-NEXT: [[TMP7:%.*]] = call target("riscv.vector.tuple", , 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv8i8(target("riscv.vector.tuple", , 8) [[TMP6]], [[V6:%.*]], i32 6) ; RV32-NEXT: [[TMP8:%.*]] = call target("riscv.vector.tuple", , 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv8i8(target("riscv.vector.tuple", , 8) [[TMP7]], [[V7:%.*]], i32 7) -; RV32-NEXT: call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i32(target("riscv.vector.tuple", , 8) [[TMP8]], ptr [[PTR:%.*]], i32 -1, i32 3) +; RV32-NEXT: call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i32(target("riscv.vector.tuple", , 8) [[TMP8]], ptr [[PTR:%.*]], splat (i1 true), i32 -1, i32 3) ; RV32-NEXT: ret void ; ; RV64-LABEL: @store_factor8_vscale( @@ -848,7 +848,7 @@ define void @store_factor8_vscale(ptr %ptr, %v0, , 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv8i8(target("riscv.vector.tuple", , 8) [[TMP5]], [[V5:%.*]], i32 5) ; RV64-NEXT: [[TMP7:%.*]] = call target("riscv.vector.tuple", , 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv8i8(target("riscv.vector.tuple", , 8) [[TMP6]], [[V6:%.*]], i32 6) ; RV64-NEXT: [[TMP8:%.*]] = call target("riscv.vector.tuple", , 8) @llvm.riscv.tuple.insert.triscv.vector.tuple_nxv8i8_8t.nxv8i8(target("riscv.vector.tuple", , 8) [[TMP7]], [[V7:%.*]], i32 7) -; RV64-NEXT: call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv8i8_8t.p0.i64(target("riscv.vector.tuple", , 8) [[TMP8]], ptr [[PTR:%.*]], i64 -1, i64 3) +; RV64-NEXT: call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv8i8_8t.p0.nxv8i1.i64(target("riscv.vector.tuple", , 8) [[TMP8]], ptr [[PTR:%.*]], splat (i1 true), i64 -1, i64 3) ; RV64-NEXT: ret void ; %interleaved.vec = call @llvm.vector.interleave8.nxv8i8( %v0, %v1, %v2, %v3, %v4, %v5, %v6, %v7)