From f32a0b01357dad8af7ec87fec197575f5908368e Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Tue, 2 Sep 2025 12:29:22 -0500 Subject: [PATCH] [PowerPC] Implement vector unpack instructions Implement the set of vector uncompress instructions: * vupkhsntob * vupklsntob * vupkint4tobf16 * vupkint8tobf16 * vupkint4tofp32 * vupkint8tofp32 --- llvm/lib/Target/PowerPC/PPCInstrFuture.td | 78 +++++++++++++++++++ .../PowerPC/ppc-encoding-ISAFuture.txt | 18 +++++ .../PowerPC/ppc64le-encoding-ISAFuture.txt | 18 +++++ llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 24 ++++++ 4 files changed, 138 insertions(+) diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index 9eef7332f573b..e8a4e52780e80 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -45,6 +45,67 @@ multiclass XOForm_RTAB5_L1r opcode, bits<9> xo, dag OOL, dag IOL, } } +class VXForm_VRTB5 xo, bits<5> R, dag OOL, dag IOL, string asmstr, + list pattern> : I<4, OOL, IOL, asmstr, NoItinerary> { + bits<5> VRT; + bits<5> VRB; + + let Pattern = pattern; + + let Inst{6 -10} = VRT; + let Inst{11 -15} = R; + let Inst{16 -20} = VRB; + let Inst{21 -31} = xo; +} + +class VXForm_VRTB5_UIM2 xo, bits<3> R, dag OOL, dag IOL, string asmstr, + list pattern> + : I<4, OOL, IOL, asmstr, NoItinerary> { + bits<5> VRT; + bits<5> VRB; + bits<2> UIM; + + let Pattern = pattern; + + let Inst{6 -10} = VRT; + let Inst{11 -13} = R; + let Inst{14 -15} = UIM; + let Inst{16 -20} = VRB; + let Inst{21 -31} = xo; +} + +class VXForm_VRTB5_UIM1 xo, bits<4> R, dag OOL, dag IOL, string asmstr, + list pattern> + : I<4, OOL, IOL, asmstr, NoItinerary> { + bits<5> VRT; + bits<5> VRB; + bits<1> UIM; + + let Pattern = pattern; + + let Inst{6 -10} = VRT; + let Inst{11 -14} = R; + let Inst{15} = UIM; + let Inst{16 -20} = VRB; + let Inst{21 -31} = xo; +} + +class VXForm_VRTB5_UIM3 xo, bits<2> R, dag OOL, dag IOL, string asmstr, + list pattern> + : I<4, OOL, IOL, asmstr, NoItinerary> { + bits<5> VRT; + bits<5> VRB; + bits<3> UIM; + + let Pattern = pattern; + + let Inst{6 -10} = VRT; + let Inst{11 -12} = R; + let Inst{13 -15} = UIM; + let Inst{16 -20} = VRB; + let Inst{21 -31} = xo; +} + let Predicates = [IsISAFuture] in { defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, u1imm:$L), @@ -81,4 +142,21 @@ let Predicates = [HasVSX, IsISAFuture] in { (ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB), "stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>; } + + def VUPKHSNTOB : VXForm_VRTB5<387, 0, (outs vrrc:$VRT), (ins vrrc:$VRB), + "vupkhsntob $VRT, $VRB", []>; + def VUPKLSNTOB : VXForm_VRTB5<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB), + "vupklsntob $VRT, $VRB", []>; + def VUPKINT4TOBF16 + : VXForm_VRTB5_UIM2<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM), + "vupkint4tobf16 $VRT, $VRB, $UIM", []>; + def VUPKINT8TOBF16 + : VXForm_VRTB5_UIM1<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB, u1imm:$UIM), + "vupkint8tobf16 $VRT, $VRB, $UIM", []>; + def VUPKINT8TOFP32 + : VXForm_VRTB5_UIM2<387, 3, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM), + "vupkint8tofp32 $VRT, $VRB, $UIM", []>; + def VUPKINT4TOFP32 + : VXForm_VRTB5_UIM3<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u3imm:$UIM), + "vupkint4tofp32 $VRT, $VRB, $UIM", []>; } diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt index 4bea42243f83b..6adaa5cfdaefc 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt @@ -195,3 +195,21 @@ #CHECK: dmxxsha224256pad 0, 1 0xf0,0x18,0x0e,0x94 + +#CHECK: vupkhsntob 2, 4 +0x10,0x40,0x21,0x83 + +#CHECK: vupklsntob 2, 4 +0x10,0x41,0x21,0x83 + +#CHECK: vupkint4tobf16 2, 4, 3 +0x10,0x4b,0x21,0x83 + +#CHECK: vupkint8tobf16 1, 3, 1 +0x10,0x23,0x19,0x83 + +#CHECK: vupkint4tofp32 3, 5, 2 +0x10,0x72,0x29,0x83 + +#CHECK: vupkint8tofp32 3, 5, 2 +0x10,0x6e,0x29,0x83 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt index 233693e67292e..84f9bc8e67b60 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt @@ -189,3 +189,21 @@ #CHECK: dmxxsha224256pad 0, 1 0x94,0x0e,0x18,0xf0 + +#CHECK: vupkhsntob 2, 4 +0x83,0x21,0x40,0x10 + +#CHECK: vupklsntob 2, 4 +0x83,0x21,0x41,0x10 + +#CHECK: vupkint4tobf16 2, 4, 3 +0x83,0x21,0x4b,0x10 + +#CHECK: vupkint8tobf16 1, 3, 1 +0x83,0x19,0x23,0x10 + +#CHECK: vupkint4tofp32 3, 5, 2 +0x83,0x29,0x72,0x10 + +#CHECK: vupkint8tofp32 3, 5, 2 +0x83,0x29,0x6e,0x10 diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s index cba93291e4595..8316bbd9854ea 100644 --- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s +++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s @@ -282,3 +282,27 @@ dmxxsha224256pad 0, 1 #CHECK-BE: dmxxsha224256pad 0, 1 # encoding: [0xf0,0x18,0x0e,0x94] #CHECK-LE: dmxxsha224256pad 0, 1 # encoding: [0x94,0x0e,0x18,0xf0] + + vupkhsntob 2, 4 +#CHECK-BE: vupkhsntob 2, 4 # encoding: [0x10,0x40,0x21,0x83] +#CHECK-LE: vupkhsntob 2, 4 # encoding: [0x83,0x21,0x40,0x10] + + vupklsntob 2, 4 +#CHECK-BE: vupklsntob 2, 4 # encoding: [0x10,0x41,0x21,0x83] +#CHECK-LE: vupklsntob 2, 4 # encoding: [0x83,0x21,0x41,0x10] + + vupkint4tobf16 2, 4, 3 +#CHECK-BE: vupkint4tobf16 2, 4, 3 # encoding: [0x10,0x4b,0x21,0x83] +#CHECK-LE: vupkint4tobf16 2, 4, 3 # encoding: [0x83,0x21,0x4b,0x10] + + vupkint8tobf16 1, 3, 1 +#CHECK-BE: vupkint8tobf16 1, 3, 1 # encoding: [0x10,0x23,0x19,0x83] +#CHECK-LE: vupkint8tobf16 1, 3, 1 # encoding: [0x83,0x19,0x23,0x10] + + vupkint4tofp32 3, 5, 2 +#CHECK-BE: vupkint4tofp32 3, 5, 2 # encoding: [0x10,0x72,0x29,0x83] +#CHECK-LE: vupkint4tofp32 3, 5, 2 # encoding: [0x83,0x29,0x72,0x10] + + vupkint8tofp32 3, 5, 2 +#CHECK-BE: vupkint8tofp32 3, 5, 2 # encoding: [0x10,0x6e,0x29,0x83] +#CHECK-LE: vupkint8tofp32 3, 5, 2 # encoding: [0x83,0x29,0x6e,0x10]