diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 23f5a848137c4..5b0973f13eb58 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1465,11 +1465,12 @@ def : PatGprUimmLog2XLen; def : PatGprUimmLog2XLen; def : PatGprUimmLog2XLen; -// Select 'or' as ADDI if the immediate bits are known to be 0 in $rs1. This -// can improve compressibility. def riscv_or_disjoint : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ return orDisjoint(N); }]>; +// Select 'or' as ADD or ADDI if known disjoint. There is no c.ori, and c.add allows +// more registers than c.or. +def : PatGprGpr; def : PatGprSimm12; def add_like : PatFrags<(ops node:$lhs, node:$rhs), diff --git a/llvm/test/CodeGen/RISCV/add-before-shl.ll b/llvm/test/CodeGen/RISCV/add-before-shl.ll index 35a39b89a2cb7..4cb25fcaf1286 100644 --- a/llvm/test/CodeGen/RISCV/add-before-shl.ll +++ b/llvm/test/CodeGen/RISCV/add-before-shl.ll @@ -172,14 +172,14 @@ define i128 @add_wide_operand(i128 %a) nounwind { ; RV32I-NEXT: srli a5, a2, 29 ; RV32I-NEXT: slli a6, a3, 3 ; RV32I-NEXT: srli a3, a3, 29 -; RV32I-NEXT: or a5, a6, a5 +; RV32I-NEXT: add a5, a6, a5 ; RV32I-NEXT: slli a6, a4, 3 -; RV32I-NEXT: or a3, a6, a3 +; RV32I-NEXT: add a3, a6, a3 ; RV32I-NEXT: lui a6, 128 ; RV32I-NEXT: srli a4, a4, 29 ; RV32I-NEXT: slli a1, a1, 3 ; RV32I-NEXT: slli a2, a2, 3 -; RV32I-NEXT: or a1, a1, a4 +; RV32I-NEXT: add a1, a1, a4 ; RV32I-NEXT: add a1, a1, a6 ; RV32I-NEXT: sw a2, 0(a0) ; RV32I-NEXT: sw a5, 4(a0) @@ -192,7 +192,7 @@ define i128 @add_wide_operand(i128 %a) nounwind { ; RV64I-NEXT: srli a2, a0, 61 ; RV64I-NEXT: slli a1, a1, 3 ; RV64I-NEXT: slli a0, a0, 3 -; RV64I-NEXT: or a1, a1, a2 +; RV64I-NEXT: add a1, a1, a2 ; RV64I-NEXT: addi a2, zero, 1 ; RV64I-NEXT: slli a2, a2, 51 ; RV64I-NEXT: add a1, a1, a2 @@ -208,18 +208,18 @@ define i128 @add_wide_operand(i128 %a) nounwind { ; RV32C-NEXT: add a6, a4, a5 ; RV32C-NEXT: srli a5, a2, 29 ; RV32C-NEXT: slli a4, a3, 3 -; RV32C-NEXT: c.or a4, a5 +; RV32C-NEXT: c.add a4, a5 ; RV32C-NEXT: srli a5, a1, 29 ; RV32C-NEXT: c.srli a3, 29 ; RV32C-NEXT: c.slli a1, 3 ; RV32C-NEXT: c.slli a2, 3 ; RV32C-NEXT: c.slli a6, 3 -; RV32C-NEXT: c.or a1, a3 -; RV32C-NEXT: or a3, a6, a5 +; RV32C-NEXT: c.add a1, a3 +; RV32C-NEXT: c.add a5, a6 ; RV32C-NEXT: c.sw a2, 0(a0) ; RV32C-NEXT: c.sw a4, 4(a0) ; RV32C-NEXT: c.sw a1, 8(a0) -; RV32C-NEXT: c.sw a3, 12(a0) +; RV32C-NEXT: c.sw a5, 12(a0) ; RV32C-NEXT: c.jr ra ; ; RV64C-LABEL: add_wide_operand: @@ -227,7 +227,7 @@ define i128 @add_wide_operand(i128 %a) nounwind { ; RV64C-NEXT: srli a2, a0, 61 ; RV64C-NEXT: c.slli a1, 3 ; RV64C-NEXT: c.slli a0, 3 -; RV64C-NEXT: c.or a1, a2 +; RV64C-NEXT: c.add a1, a2 ; RV64C-NEXT: c.li a2, 1 ; RV64C-NEXT: c.slli a2, 51 ; RV64C-NEXT: c.add a1, a2 diff --git a/llvm/test/CodeGen/RISCV/addcarry.ll b/llvm/test/CodeGen/RISCV/addcarry.ll index ff0d1e75c746c..4ba8ba9701c17 100644 --- a/llvm/test/CodeGen/RISCV/addcarry.ll +++ b/llvm/test/CodeGen/RISCV/addcarry.ll @@ -32,13 +32,13 @@ define i64 @addcarry(i64 %x, i64 %y) nounwind { ; RISCV32-NEXT: # %bb.3: ; RISCV32-NEXT: sub a5, a5, a0 ; RISCV32-NEXT: .LBB0_4: -; RISCV32-NEXT: slli a5, a5, 30 -; RISCV32-NEXT: srli a1, a4, 2 +; RISCV32-NEXT: slli a1, a5, 30 +; RISCV32-NEXT: srli a3, a4, 2 ; RISCV32-NEXT: slli a4, a4, 30 ; RISCV32-NEXT: mul a0, a0, a2 -; RISCV32-NEXT: or a1, a5, a1 +; RISCV32-NEXT: add a1, a1, a3 ; RISCV32-NEXT: srli a0, a0, 2 -; RISCV32-NEXT: or a0, a4, a0 +; RISCV32-NEXT: add a0, a4, a0 ; RISCV32-NEXT: ret %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2); ret i64 %tmp; diff --git a/llvm/test/CodeGen/RISCV/alu64.ll b/llvm/test/CodeGen/RISCV/alu64.ll index c7938a718de70..eac57b8f0c5f2 100644 --- a/llvm/test/CodeGen/RISCV/alu64.ll +++ b/llvm/test/CodeGen/RISCV/alu64.ll @@ -120,7 +120,7 @@ define i64 @slli(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: srli a2, a0, 25 ; RV32I-NEXT: slli a1, a1, 7 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 7 ; RV32I-NEXT: ret %1 = shl i64 %a, 7 @@ -137,7 +137,7 @@ define i64 @srli(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: slli a2, a1, 24 ; RV32I-NEXT: srli a0, a0, 8 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: srli a1, a1, 8 ; RV32I-NEXT: ret %1 = lshr i64 %a, 8 @@ -154,7 +154,7 @@ define i64 @srai(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: slli a2, a1, 23 ; RV32I-NEXT: srli a0, a0, 9 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: srai a1, a1, 9 ; RV32I-NEXT: ret %1 = ashr i64 %a, 9 diff --git a/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll b/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll index b16672d3c4a16..ecdcbbe043d9a 100644 --- a/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll +++ b/llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll @@ -8,7 +8,7 @@ define i1 @test1(i64 %x) { ; RV32-NEXT: slli a2, a1, 2 ; RV32-NEXT: srli a0, a0, 30 ; RV32-NEXT: srai a1, a1, 30 -; RV32-NEXT: or a0, a0, a2 +; RV32-NEXT: add a0, a0, a2 ; RV32-NEXT: xori a0, a0, -2 ; RV32-NEXT: not a1, a1 ; RV32-NEXT: or a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/avgceils.ll b/llvm/test/CodeGen/RISCV/avgceils.ll index 64410fad6029a..6e3fe4ace89af 100644 --- a/llvm/test/CodeGen/RISCV/avgceils.ll +++ b/llvm/test/CodeGen/RISCV/avgceils.ll @@ -189,7 +189,7 @@ define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind { ; RV32I-NEXT: slli a1, a1, 31 ; RV32I-NEXT: srli a3, a3, 1 ; RV32I-NEXT: sub a4, a4, a2 -; RV32I-NEXT: or a3, a3, a1 +; RV32I-NEXT: add a3, a3, a1 ; RV32I-NEXT: sltu a1, a0, a3 ; RV32I-NEXT: sub a1, a4, a1 ; RV32I-NEXT: sub a0, a0, a3 @@ -220,7 +220,7 @@ define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind { ; RV32I-NEXT: slli a1, a1, 31 ; RV32I-NEXT: srli a3, a3, 1 ; RV32I-NEXT: sub a4, a4, a2 -; RV32I-NEXT: or a3, a3, a1 +; RV32I-NEXT: add a3, a3, a1 ; RV32I-NEXT: sltu a1, a0, a3 ; RV32I-NEXT: sub a1, a4, a1 ; RV32I-NEXT: sub a0, a0, a3 diff --git a/llvm/test/CodeGen/RISCV/avgceilu.ll b/llvm/test/CodeGen/RISCV/avgceilu.ll index 1c1d1cbfd12cb..3bde33d51f329 100644 --- a/llvm/test/CodeGen/RISCV/avgceilu.ll +++ b/llvm/test/CodeGen/RISCV/avgceilu.ll @@ -185,7 +185,7 @@ define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind { ; RV32I-NEXT: slli a1, a1, 31 ; RV32I-NEXT: srli a3, a3, 1 ; RV32I-NEXT: sub a4, a4, a2 -; RV32I-NEXT: or a3, a3, a1 +; RV32I-NEXT: add a3, a3, a1 ; RV32I-NEXT: sltu a1, a0, a3 ; RV32I-NEXT: sub a1, a4, a1 ; RV32I-NEXT: sub a0, a0, a3 @@ -216,7 +216,7 @@ define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind { ; RV32I-NEXT: slli a1, a1, 31 ; RV32I-NEXT: srli a3, a3, 1 ; RV32I-NEXT: sub a4, a4, a2 -; RV32I-NEXT: or a3, a3, a1 +; RV32I-NEXT: add a3, a3, a1 ; RV32I-NEXT: sltu a1, a0, a3 ; RV32I-NEXT: sub a1, a4, a1 ; RV32I-NEXT: sub a0, a0, a3 diff --git a/llvm/test/CodeGen/RISCV/avgfloors.ll b/llvm/test/CodeGen/RISCV/avgfloors.ll index b321f4c2f2939..4de15fb0e7220 100644 --- a/llvm/test/CodeGen/RISCV/avgfloors.ll +++ b/llvm/test/CodeGen/RISCV/avgfloors.ll @@ -175,7 +175,7 @@ define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind { ; RV32I-NEXT: xor a4, a0, a2 ; RV32I-NEXT: slli a1, a1, 31 ; RV32I-NEXT: srli a4, a4, 1 -; RV32I-NEXT: or a1, a4, a1 +; RV32I-NEXT: add a1, a4, a1 ; RV32I-NEXT: and a2, a0, a2 ; RV32I-NEXT: add a0, a2, a1 ; RV32I-NEXT: sltu a1, a0, a2 @@ -206,7 +206,7 @@ define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind { ; RV32I-NEXT: xor a4, a0, a2 ; RV32I-NEXT: slli a1, a1, 31 ; RV32I-NEXT: srli a4, a4, 1 -; RV32I-NEXT: or a1, a4, a1 +; RV32I-NEXT: add a1, a4, a1 ; RV32I-NEXT: and a2, a0, a2 ; RV32I-NEXT: add a0, a2, a1 ; RV32I-NEXT: sltu a1, a0, a2 diff --git a/llvm/test/CodeGen/RISCV/avgflooru.ll b/llvm/test/CodeGen/RISCV/avgflooru.ll index 2e56f3359434c..ef1867e6d049a 100644 --- a/llvm/test/CodeGen/RISCV/avgflooru.ll +++ b/llvm/test/CodeGen/RISCV/avgflooru.ll @@ -176,8 +176,8 @@ define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind { ; RV32I-NEXT: srli a3, a1, 1 ; RV32I-NEXT: slli a4, a1, 31 ; RV32I-NEXT: srli a0, a0, 1 -; RV32I-NEXT: or a1, a3, a2 -; RV32I-NEXT: or a0, a0, a4 +; RV32I-NEXT: add a1, a3, a2 +; RV32I-NEXT: add a0, a0, a4 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_fixed_i64: @@ -209,8 +209,8 @@ define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind { ; RV32I-NEXT: srli a3, a1, 1 ; RV32I-NEXT: slli a4, a1, 31 ; RV32I-NEXT: srli a0, a0, 1 -; RV32I-NEXT: or a1, a3, a2 -; RV32I-NEXT: or a0, a0, a4 +; RV32I-NEXT: add a1, a3, a2 +; RV32I-NEXT: add a0, a0, a4 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_ext_i64: diff --git a/llvm/test/CodeGen/RISCV/bfloat-arith.ll b/llvm/test/CodeGen/RISCV/bfloat-arith.ll index 871b43e61df50..c5ed98dee861d 100644 --- a/llvm/test/CodeGen/RISCV/bfloat-arith.ll +++ b/llvm/test/CodeGen/RISCV/bfloat-arith.ll @@ -79,7 +79,7 @@ define bfloat @fsgnj_bf16(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: fmv.x.h a1, fa0 ; RV32IZFBFMIN-NEXT: slli a1, a1, 17 ; RV32IZFBFMIN-NEXT: srli a1, a1, 17 -; RV32IZFBFMIN-NEXT: or a0, a1, a0 +; RV32IZFBFMIN-NEXT: add a0, a1, a0 ; RV32IZFBFMIN-NEXT: fmv.h.x fa0, a0 ; RV32IZFBFMIN-NEXT: ret ; @@ -91,7 +91,7 @@ define bfloat @fsgnj_bf16(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: fmv.x.h a1, fa0 ; RV64IZFBFMIN-NEXT: slli a1, a1, 49 ; RV64IZFBFMIN-NEXT: srli a1, a1, 49 -; RV64IZFBFMIN-NEXT: or a0, a1, a0 +; RV64IZFBFMIN-NEXT: add a0, a1, a0 ; RV64IZFBFMIN-NEXT: fmv.h.x fa0, a0 ; RV64IZFBFMIN-NEXT: ret %1 = call bfloat @llvm.copysign.bf16(bfloat %a, bfloat %b) @@ -133,7 +133,7 @@ define bfloat @fsgnjn_bf16(bfloat %a, bfloat %b) nounwind { ; RV32IZFBFMIN-NEXT: fmv.x.h a1, fa0 ; RV32IZFBFMIN-NEXT: slli a1, a1, 17 ; RV32IZFBFMIN-NEXT: srli a1, a1, 17 -; RV32IZFBFMIN-NEXT: or a0, a1, a0 +; RV32IZFBFMIN-NEXT: add a0, a1, a0 ; RV32IZFBFMIN-NEXT: fmv.h.x fa0, a0 ; RV32IZFBFMIN-NEXT: ret ; @@ -150,7 +150,7 @@ define bfloat @fsgnjn_bf16(bfloat %a, bfloat %b) nounwind { ; RV64IZFBFMIN-NEXT: fmv.x.h a1, fa0 ; RV64IZFBFMIN-NEXT: slli a1, a1, 49 ; RV64IZFBFMIN-NEXT: srli a1, a1, 49 -; RV64IZFBFMIN-NEXT: or a0, a1, a0 +; RV64IZFBFMIN-NEXT: add a0, a1, a0 ; RV64IZFBFMIN-NEXT: fmv.h.x fa0, a0 ; RV64IZFBFMIN-NEXT: ret %1 = fadd bfloat %a, %b diff --git a/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll b/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll index 1605e686e9177..e56e57b88a0be 100644 --- a/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll +++ b/llvm/test/CodeGen/RISCV/bswap-bitreverse.ll @@ -26,7 +26,7 @@ define i16 @test_bswap_i16(i16 %a) nounwind { ; RV32I-NEXT: slli a1, a0, 8 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 24 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bswap_i16: @@ -34,7 +34,7 @@ define i16 @test_bswap_i16(i16 %a) nounwind { ; RV64I-NEXT: slli a1, a0, 8 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 56 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV32ZB-LABEL: test_bswap_i16: @@ -61,11 +61,11 @@ define i32 @test_bswap_i32(i32 %a) nounwind { ; RV32I-NEXT: addi a2, a2, -256 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a2, a0, a2 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: slli a2, a2, 8 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, a2 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bswap_i32: @@ -76,11 +76,11 @@ define i32 @test_bswap_i32(i32 %a) nounwind { ; RV64I-NEXT: addi a2, a2, -256 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a2, a0, a2 -; RV64I-NEXT: or a1, a1, a3 +; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: slli a2, a2, 8 ; RV64I-NEXT: slliw a0, a0, 24 -; RV64I-NEXT: or a0, a0, a2 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32ZB-LABEL: test_bswap_i32: @@ -106,20 +106,20 @@ define i64 @test_bswap_i64(i64 %a) nounwind { ; RV32I-NEXT: srli a5, a0, 8 ; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: and a2, a2, a3 -; RV32I-NEXT: or a2, a2, a4 +; RV32I-NEXT: add a2, a2, a4 ; RV32I-NEXT: srli a4, a0, 24 ; RV32I-NEXT: and a5, a5, a3 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: slli a5, a1, 24 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: slli a1, a1, 8 -; RV32I-NEXT: or a1, a5, a1 +; RV32I-NEXT: add a1, a5, a1 ; RV32I-NEXT: and a3, a0, a3 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a0, a3 -; RV32I-NEXT: or a0, a1, a2 -; RV32I-NEXT: or a1, a3, a4 +; RV32I-NEXT: add a3, a0, a3 +; RV32I-NEXT: add a0, a1, a2 +; RV32I-NEXT: add a1, a3, a4 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bswap_i64: @@ -131,24 +131,24 @@ define i64 @test_bswap_i64(i64 %a) nounwind { ; RV64I-NEXT: lui a5, 4080 ; RV64I-NEXT: addi a2, a2, -256 ; RV64I-NEXT: and a1, a1, a2 -; RV64I-NEXT: or a1, a1, a3 +; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: srli a3, a0, 8 ; RV64I-NEXT: and a4, a4, a5 ; RV64I-NEXT: srliw a3, a3, 24 ; RV64I-NEXT: slli a3, a3, 24 -; RV64I-NEXT: or a3, a3, a4 +; RV64I-NEXT: add a3, a3, a4 ; RV64I-NEXT: srliw a4, a0, 24 ; RV64I-NEXT: and a5, a0, a5 ; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a4, a4, 32 ; RV64I-NEXT: slli a5, a5, 24 -; RV64I-NEXT: or a4, a5, a4 +; RV64I-NEXT: add a4, a5, a4 ; RV64I-NEXT: slli a2, a2, 40 -; RV64I-NEXT: or a1, a3, a1 -; RV64I-NEXT: or a0, a0, a2 -; RV64I-NEXT: or a0, a0, a4 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a1, a3, a1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a4 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32ZB-LABEL: test_bswap_i64: @@ -176,31 +176,31 @@ define i7 @test_bitreverse_i7(i7 %a) nounwind { ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a2, a0, a2 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: slli a2, a2, 8 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: lui a2, 209715 ; RV32I-NEXT: addi a3, a3, -241 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: lui a3, 344064 ; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: lui a2, 348160 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: slli a0, a0, 1 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a0, a0, 25 ; RV32I-NEXT: ret ; @@ -215,49 +215,49 @@ define i7 @test_bitreverse_i7(i7 %a) nounwind { ; RV64I-NEXT: srliw a7, a0, 24 ; RV64I-NEXT: addi a2, a2, -256 ; RV64I-NEXT: and a1, a1, a2 -; RV64I-NEXT: or a1, a1, a3 +; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: lui a3, 61681 ; RV64I-NEXT: and a4, a4, a5 ; RV64I-NEXT: srliw a6, a6, 24 ; RV64I-NEXT: slli a6, a6, 24 -; RV64I-NEXT: or a4, a6, a4 +; RV64I-NEXT: add a4, a6, a4 ; RV64I-NEXT: lui a6, 209715 ; RV64I-NEXT: and a5, a0, a5 ; RV64I-NEXT: slli a7, a7, 32 ; RV64I-NEXT: addi a3, a3, -241 ; RV64I-NEXT: addi a6, a6, 819 ; RV64I-NEXT: slli a5, a5, 24 -; RV64I-NEXT: or a5, a5, a7 +; RV64I-NEXT: add a5, a5, a7 ; RV64I-NEXT: slli a7, a3, 32 ; RV64I-NEXT: add a3, a3, a7 ; RV64I-NEXT: slli a7, a6, 32 ; RV64I-NEXT: add a6, a6, a7 -; RV64I-NEXT: or a1, a4, a1 +; RV64I-NEXT: add a1, a4, a1 ; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a2, a2, 40 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: li a2, 21 -; RV64I-NEXT: or a0, a0, a5 +; RV64I-NEXT: add a0, a0, a5 ; RV64I-NEXT: li a4, 85 ; RV64I-NEXT: slli a2, a2, 58 ; RV64I-NEXT: slli a4, a4, 56 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: slli a0, a0, 4 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: and a0, a0, a6 ; RV64I-NEXT: and a1, a1, a6 ; RV64I-NEXT: slli a0, a0, 2 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a0, a0, a4 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slli a0, a0, 1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a0, a0, 57 ; RV64I-NEXT: ret ; @@ -272,19 +272,19 @@ define i7 @test_bitreverse_i7(i7 %a) nounwind { ; RV32ZBB-NEXT: lui a1, 209715 ; RV32ZBB-NEXT: addi a1, a1, 819 ; RV32ZBB-NEXT: slli a0, a0, 4 -; RV32ZBB-NEXT: or a0, a2, a0 +; RV32ZBB-NEXT: add a0, a2, a0 ; RV32ZBB-NEXT: srli a2, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a1 ; RV32ZBB-NEXT: and a1, a2, a1 ; RV32ZBB-NEXT: lui a2, 344064 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: lui a1, 348160 ; RV32ZBB-NEXT: and a1, a0, a1 ; RV32ZBB-NEXT: srli a0, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: slli a1, a1, 1 -; RV32ZBB-NEXT: or a0, a0, a1 +; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: srli a0, a0, 25 ; RV32ZBB-NEXT: ret ; @@ -304,7 +304,7 @@ define i7 @test_bitreverse_i7(i7 %a) nounwind { ; RV64ZBB-NEXT: and a0, a0, a1 ; RV64ZBB-NEXT: li a1, 21 ; RV64ZBB-NEXT: slli a0, a0, 4 -; RV64ZBB-NEXT: or a0, a3, a0 +; RV64ZBB-NEXT: add a0, a3, a0 ; RV64ZBB-NEXT: srli a3, a0, 2 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a2, a3, a2 @@ -312,12 +312,12 @@ define i7 @test_bitreverse_i7(i7 %a) nounwind { ; RV64ZBB-NEXT: slli a1, a1, 58 ; RV64ZBB-NEXT: slli a3, a3, 56 ; RV64ZBB-NEXT: slli a0, a0, 2 -; RV64ZBB-NEXT: or a0, a2, a0 +; RV64ZBB-NEXT: add a0, a2, a0 ; RV64ZBB-NEXT: srli a2, a0, 1 ; RV64ZBB-NEXT: and a0, a0, a3 ; RV64ZBB-NEXT: and a1, a2, a1 ; RV64ZBB-NEXT: slli a0, a0, 1 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a0, a0, 57 ; RV64ZBB-NEXT: ret ; @@ -345,17 +345,17 @@ define i8 @test_bitreverse_i8(i8 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 4 ; RV32I-NEXT: srli a0, a0, 28 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: andi a1, a0, 51 ; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: slli a1, a1, 2 ; RV32I-NEXT: andi a0, a0, 51 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: andi a1, a0, 85 ; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: andi a0, a0, 85 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bitreverse_i8: @@ -364,17 +364,17 @@ define i8 @test_bitreverse_i8(i8 %a) nounwind { ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a1, a1, 4 ; RV64I-NEXT: srli a0, a0, 60 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: andi a1, a0, 51 ; RV64I-NEXT: srli a0, a0, 2 ; RV64I-NEXT: slli a1, a1, 2 ; RV64I-NEXT: andi a0, a0, 51 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: andi a1, a0, 85 ; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: slli a1, a1, 1 ; RV64I-NEXT: andi a0, a0, 85 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_bitreverse_i8: @@ -383,17 +383,17 @@ define i8 @test_bitreverse_i8(i8 %a) nounwind { ; RV32ZBB-NEXT: slli a0, a0, 24 ; RV32ZBB-NEXT: slli a1, a1, 4 ; RV32ZBB-NEXT: srli a0, a0, 28 -; RV32ZBB-NEXT: or a0, a0, a1 +; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: andi a1, a0, 51 ; RV32ZBB-NEXT: srli a0, a0, 2 ; RV32ZBB-NEXT: slli a1, a1, 2 ; RV32ZBB-NEXT: andi a0, a0, 51 -; RV32ZBB-NEXT: or a0, a0, a1 +; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: andi a1, a0, 85 ; RV32ZBB-NEXT: srli a0, a0, 1 ; RV32ZBB-NEXT: slli a1, a1, 1 ; RV32ZBB-NEXT: andi a0, a0, 85 -; RV32ZBB-NEXT: or a0, a0, a1 +; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: test_bitreverse_i8: @@ -402,17 +402,17 @@ define i8 @test_bitreverse_i8(i8 %a) nounwind { ; RV64ZBB-NEXT: slli a0, a0, 56 ; RV64ZBB-NEXT: slli a1, a1, 4 ; RV64ZBB-NEXT: srli a0, a0, 60 -; RV64ZBB-NEXT: or a0, a0, a1 +; RV64ZBB-NEXT: add a0, a0, a1 ; RV64ZBB-NEXT: andi a1, a0, 51 ; RV64ZBB-NEXT: srli a0, a0, 2 ; RV64ZBB-NEXT: slli a1, a1, 2 ; RV64ZBB-NEXT: andi a0, a0, 51 -; RV64ZBB-NEXT: or a0, a0, a1 +; RV64ZBB-NEXT: add a0, a0, a1 ; RV64ZBB-NEXT: andi a1, a0, 85 ; RV64ZBB-NEXT: srli a0, a0, 1 ; RV64ZBB-NEXT: slli a1, a1, 1 ; RV64ZBB-NEXT: andi a0, a0, 85 -; RV64ZBB-NEXT: or a0, a0, a1 +; RV64ZBB-NEXT: add a0, a0, a1 ; RV64ZBB-NEXT: ret ; ; RV32ZBKB-LABEL: test_bitreverse_i8: @@ -436,26 +436,26 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind { ; RV32I-NEXT: lui a2, 1 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: addi a2, a2, -241 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: lui a2, 3 ; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: lui a2, 5 ; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 1 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bitreverse_i16: @@ -465,26 +465,26 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind { ; RV64I-NEXT: lui a2, 1 ; RV64I-NEXT: srli a0, a0, 56 ; RV64I-NEXT: addi a2, a2, -241 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 3 ; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: slli a0, a0, 4 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 5 ; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: slli a0, a0, 2 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slli a0, a0, 1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_bitreverse_i16: @@ -498,19 +498,19 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind { ; RV32ZBB-NEXT: srli a0, a0, 20 ; RV32ZBB-NEXT: addi a2, a2, 819 ; RV32ZBB-NEXT: andi a0, a0, -241 -; RV32ZBB-NEXT: or a0, a0, a1 +; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: srli a1, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: lui a2, 5 ; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: slli a0, a0, 1 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: test_bitreverse_i16: @@ -524,19 +524,19 @@ define i16 @test_bitreverse_i16(i16 %a) nounwind { ; RV64ZBB-NEXT: srli a0, a0, 52 ; RV64ZBB-NEXT: addi a2, a2, 819 ; RV64ZBB-NEXT: andi a0, a0, -241 -; RV64ZBB-NEXT: or a0, a0, a1 +; RV64ZBB-NEXT: add a0, a0, a1 ; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: lui a2, 5 ; RV64ZBB-NEXT: addi a2, a2, 1365 ; RV64ZBB-NEXT: slli a0, a0, 2 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: slli a0, a0, 1 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: ret ; ; RV32ZBKB-LABEL: test_bitreverse_i16: @@ -566,13 +566,13 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a2, a0, a2 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: slli a2, a2, 8 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: lui a2, 209715 ; RV32I-NEXT: addi a3, a3, -241 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a1, a1, a3 @@ -580,17 +580,17 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: slli a0, a0, 1 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bitreverse_i32: @@ -602,13 +602,13 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: slliw a0, a0, 24 -; RV64I-NEXT: or a1, a1, a3 +; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: lui a3, 61681 ; RV64I-NEXT: slli a2, a2, 8 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: lui a2, 209715 ; RV64I-NEXT: addi a3, a3, -241 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a1, a1, a3 @@ -616,17 +616,17 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: addi a3, a3, 1365 ; RV64I-NEXT: slliw a0, a0, 4 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slliw a0, a0, 2 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: slliw a0, a0, 1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_bitreverse_i32: @@ -640,19 +640,19 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; RV32ZBB-NEXT: lui a1, 209715 ; RV32ZBB-NEXT: addi a1, a1, 819 ; RV32ZBB-NEXT: slli a0, a0, 4 -; RV32ZBB-NEXT: or a0, a2, a0 +; RV32ZBB-NEXT: add a0, a2, a0 ; RV32ZBB-NEXT: srli a2, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a1 ; RV32ZBB-NEXT: and a1, a2, a1 ; RV32ZBB-NEXT: lui a2, 349525 ; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: slli a0, a0, 1 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: test_bitreverse_i32: @@ -669,19 +669,19 @@ define i32 @test_bitreverse_i32(i32 %a) nounwind { ; RV64ZBB-NEXT: lui a2, 209715 ; RV64ZBB-NEXT: addi a2, a2, 819 ; RV64ZBB-NEXT: sext.w a0, a0 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: lui a2, 349525 ; RV64ZBB-NEXT: addi a2, a2, 1365 ; RV64ZBB-NEXT: slliw a0, a0, 2 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: slliw a0, a0, 1 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: ret ; ; RV32ZBKB-LABEL: test_bitreverse_i32: @@ -711,14 +711,14 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV32I-NEXT: srli a7, a0, 8 ; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: and a2, a2, a3 -; RV32I-NEXT: or a2, a2, a4 +; RV32I-NEXT: add a2, a2, a4 ; RV32I-NEXT: srli a4, a0, 24 ; RV32I-NEXT: and a7, a7, a3 -; RV32I-NEXT: or a4, a7, a4 +; RV32I-NEXT: add a4, a7, a4 ; RV32I-NEXT: lui a7, 209715 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: slli a1, a1, 8 -; RV32I-NEXT: or a1, a5, a1 +; RV32I-NEXT: add a1, a5, a1 ; RV32I-NEXT: lui a5, 349525 ; RV32I-NEXT: and a3, a0, a3 ; RV32I-NEXT: slli a0, a0, 24 @@ -726,9 +726,9 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV32I-NEXT: addi a7, a7, 819 ; RV32I-NEXT: addi a5, a5, 1365 ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a0, a0, a3 -; RV32I-NEXT: or a1, a1, a2 -; RV32I-NEXT: or a0, a0, a4 +; RV32I-NEXT: add a0, a0, a3 +; RV32I-NEXT: add a1, a1, a2 +; RV32I-NEXT: add a0, a0, a4 ; RV32I-NEXT: srli a2, a1, 4 ; RV32I-NEXT: and a1, a1, a6 ; RV32I-NEXT: srli a3, a0, 4 @@ -737,8 +737,8 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV32I-NEXT: slli a1, a1, 4 ; RV32I-NEXT: and a3, a3, a6 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a1, a2, a1 -; RV32I-NEXT: or a0, a3, a0 +; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: add a0, a3, a0 ; RV32I-NEXT: srli a2, a1, 2 ; RV32I-NEXT: and a1, a1, a7 ; RV32I-NEXT: srli a3, a0, 2 @@ -747,8 +747,8 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV32I-NEXT: slli a1, a1, 2 ; RV32I-NEXT: and a3, a3, a7 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a1, a2, a1 -; RV32I-NEXT: or a0, a3, a0 +; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: add a0, a3, a0 ; RV32I-NEXT: srli a2, a1, 1 ; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: srli a3, a0, 1 @@ -757,8 +757,8 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: slli a4, a0, 1 -; RV32I-NEXT: or a0, a2, a1 -; RV32I-NEXT: or a1, a3, a4 +; RV32I-NEXT: add a0, a2, a1 +; RV32I-NEXT: add a1, a3, a4 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bitreverse_i64: @@ -773,12 +773,12 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV64I-NEXT: lui t0, 61681 ; RV64I-NEXT: addi a2, a2, -256 ; RV64I-NEXT: and a1, a1, a2 -; RV64I-NEXT: or a1, a1, a3 +; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: lui a3, 209715 ; RV64I-NEXT: and a4, a4, a5 ; RV64I-NEXT: srliw a6, a6, 24 ; RV64I-NEXT: slli a6, a6, 24 -; RV64I-NEXT: or a4, a6, a4 +; RV64I-NEXT: add a4, a6, a4 ; RV64I-NEXT: lui a6, 349525 ; RV64I-NEXT: and a5, a0, a5 ; RV64I-NEXT: slli a7, a7, 32 @@ -786,35 +786,35 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV64I-NEXT: addi a3, a3, 819 ; RV64I-NEXT: addi a6, a6, 1365 ; RV64I-NEXT: slli a5, a5, 24 -; RV64I-NEXT: or a5, a5, a7 +; RV64I-NEXT: add a5, a5, a7 ; RV64I-NEXT: slli a7, t0, 32 ; RV64I-NEXT: add a7, t0, a7 ; RV64I-NEXT: slli t0, a3, 32 ; RV64I-NEXT: add a3, a3, t0 ; RV64I-NEXT: slli t0, a6, 32 ; RV64I-NEXT: add a6, a6, t0 -; RV64I-NEXT: or a1, a4, a1 +; RV64I-NEXT: add a1, a4, a1 ; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a2, a2, 40 -; RV64I-NEXT: or a0, a0, a2 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a5 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 4 ; RV64I-NEXT: and a0, a0, a7 ; RV64I-NEXT: and a1, a1, a7 ; RV64I-NEXT: slli a0, a0, 4 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: slli a0, a0, 2 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a0, a0, a6 ; RV64I-NEXT: and a1, a1, a6 ; RV64I-NEXT: slli a0, a0, 1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_bitreverse_i64: @@ -835,8 +835,8 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: slli a1, a1, 4 ; RV32ZBB-NEXT: slli a0, a0, 4 -; RV32ZBB-NEXT: or a1, a4, a1 -; RV32ZBB-NEXT: or a0, a5, a0 +; RV32ZBB-NEXT: add a1, a4, a1 +; RV32ZBB-NEXT: add a0, a5, a0 ; RV32ZBB-NEXT: srli a4, a1, 2 ; RV32ZBB-NEXT: and a1, a1, a3 ; RV32ZBB-NEXT: srli a5, a0, 2 @@ -845,8 +845,8 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV32ZBB-NEXT: slli a1, a1, 2 ; RV32ZBB-NEXT: and a3, a5, a3 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a1, a4, a1 -; RV32ZBB-NEXT: or a0, a3, a0 +; RV32ZBB-NEXT: add a1, a4, a1 +; RV32ZBB-NEXT: add a0, a3, a0 ; RV32ZBB-NEXT: srli a3, a1, 1 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: srli a4, a0, 1 @@ -855,8 +855,8 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV32ZBB-NEXT: slli a1, a1, 1 ; RV32ZBB-NEXT: and a2, a4, a2 ; RV32ZBB-NEXT: slli a4, a0, 1 -; RV32ZBB-NEXT: or a0, a3, a1 -; RV32ZBB-NEXT: or a1, a2, a4 +; RV32ZBB-NEXT: add a0, a3, a1 +; RV32ZBB-NEXT: add a1, a2, a4 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: test_bitreverse_i64: @@ -878,17 +878,17 @@ define i64 @test_bitreverse_i64(i64 %a) nounwind { ; RV64ZBB-NEXT: and a4, a4, a1 ; RV64ZBB-NEXT: and a0, a0, a1 ; RV64ZBB-NEXT: slli a0, a0, 4 -; RV64ZBB-NEXT: or a0, a4, a0 +; RV64ZBB-NEXT: add a0, a4, a0 ; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: slli a0, a0, 2 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: and a0, a0, a3 ; RV64ZBB-NEXT: and a1, a1, a3 ; RV64ZBB-NEXT: slli a0, a0, 1 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: ret ; ; RV32ZBKB-LABEL: test_bitreverse_i64: @@ -919,19 +919,19 @@ define i16 @test_bswap_bitreverse_i16(i16 %a) nounwind { ; RV32I-NEXT: lui a2, 3 ; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: lui a2, 5 ; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 1 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bswap_bitreverse_i16: @@ -944,19 +944,19 @@ define i16 @test_bswap_bitreverse_i16(i16 %a) nounwind { ; RV64I-NEXT: lui a2, 3 ; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: slli a0, a0, 4 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 5 ; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: slli a0, a0, 2 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slli a0, a0, 1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_bswap_bitreverse_i16: @@ -969,19 +969,19 @@ define i16 @test_bswap_bitreverse_i16(i16 %a) nounwind { ; RV32ZBB-NEXT: lui a2, 3 ; RV32ZBB-NEXT: addi a2, a2, 819 ; RV32ZBB-NEXT: slli a0, a0, 4 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: lui a2, 5 ; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: slli a0, a0, 1 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: test_bswap_bitreverse_i16: @@ -994,19 +994,19 @@ define i16 @test_bswap_bitreverse_i16(i16 %a) nounwind { ; RV64ZBB-NEXT: lui a2, 3 ; RV64ZBB-NEXT: addi a2, a2, 819 ; RV64ZBB-NEXT: slli a0, a0, 4 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: lui a2, 5 ; RV64ZBB-NEXT: addi a2, a2, 1365 ; RV64ZBB-NEXT: slli a0, a0, 2 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: slli a0, a0, 1 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: ret ; ; RV32ZBKB-LABEL: test_bswap_bitreverse_i16: @@ -1034,19 +1034,19 @@ define i32 @test_bswap_bitreverse_i32(i32 %a) nounwind { ; RV32I-NEXT: lui a2, 209715 ; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 1 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bswap_bitreverse_i32: @@ -1059,19 +1059,19 @@ define i32 @test_bswap_bitreverse_i32(i32 %a) nounwind { ; RV64I-NEXT: lui a2, 209715 ; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: slliw a0, a0, 4 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: slliw a0, a0, 2 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slliw a0, a0, 1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_bswap_bitreverse_i32: @@ -1084,19 +1084,19 @@ define i32 @test_bswap_bitreverse_i32(i32 %a) nounwind { ; RV32ZBB-NEXT: lui a2, 209715 ; RV32ZBB-NEXT: addi a2, a2, 819 ; RV32ZBB-NEXT: slli a0, a0, 4 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: lui a2, 349525 ; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: slli a0, a0, 1 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: test_bswap_bitreverse_i32: @@ -1109,19 +1109,19 @@ define i32 @test_bswap_bitreverse_i32(i32 %a) nounwind { ; RV64ZBB-NEXT: lui a2, 209715 ; RV64ZBB-NEXT: addi a2, a2, 819 ; RV64ZBB-NEXT: slliw a0, a0, 4 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: lui a2, 349525 ; RV64ZBB-NEXT: addi a2, a2, 1365 ; RV64ZBB-NEXT: slliw a0, a0, 2 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: slliw a0, a0, 1 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: ret ; ; RV32ZBKB-LABEL: test_bswap_bitreverse_i32: @@ -1155,8 +1155,8 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind { ; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: slli a0, a0, 4 ; RV32I-NEXT: slli a1, a1, 4 -; RV32I-NEXT: or a0, a2, a0 -; RV32I-NEXT: or a1, a5, a1 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: add a1, a5, a1 ; RV32I-NEXT: srli a2, a0, 2 ; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: srli a5, a1, 2 @@ -1165,8 +1165,8 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: and a4, a5, a4 ; RV32I-NEXT: slli a1, a1, 2 -; RV32I-NEXT: or a0, a2, a0 -; RV32I-NEXT: or a1, a4, a1 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: add a1, a4, a1 ; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: srli a4, a1, 1 @@ -1175,8 +1175,8 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: slli a1, a1, 1 -; RV32I-NEXT: or a0, a2, a0 -; RV32I-NEXT: or a1, a3, a1 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bswap_bitreverse_i64: @@ -1197,17 +1197,17 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind { ; RV64I-NEXT: and a4, a4, a1 ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: slli a0, a0, 4 -; RV64I-NEXT: or a0, a4, a0 +; RV64I-NEXT: add a0, a4, a0 ; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slli a0, a0, 2 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: slli a0, a0, 1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_bswap_bitreverse_i64: @@ -1226,8 +1226,8 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind { ; RV32ZBB-NEXT: addi a3, a3, 1365 ; RV32ZBB-NEXT: slli a0, a0, 4 ; RV32ZBB-NEXT: slli a1, a1, 4 -; RV32ZBB-NEXT: or a0, a2, a0 -; RV32ZBB-NEXT: or a1, a5, a1 +; RV32ZBB-NEXT: add a0, a2, a0 +; RV32ZBB-NEXT: add a1, a5, a1 ; RV32ZBB-NEXT: srli a2, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a4 ; RV32ZBB-NEXT: srli a5, a1, 2 @@ -1236,8 +1236,8 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind { ; RV32ZBB-NEXT: slli a0, a0, 2 ; RV32ZBB-NEXT: and a4, a5, a4 ; RV32ZBB-NEXT: slli a1, a1, 2 -; RV32ZBB-NEXT: or a0, a2, a0 -; RV32ZBB-NEXT: or a1, a4, a1 +; RV32ZBB-NEXT: add a0, a2, a0 +; RV32ZBB-NEXT: add a1, a4, a1 ; RV32ZBB-NEXT: srli a2, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a3 ; RV32ZBB-NEXT: srli a4, a1, 1 @@ -1246,8 +1246,8 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind { ; RV32ZBB-NEXT: slli a0, a0, 1 ; RV32ZBB-NEXT: and a3, a4, a3 ; RV32ZBB-NEXT: slli a1, a1, 1 -; RV32ZBB-NEXT: or a0, a2, a0 -; RV32ZBB-NEXT: or a1, a3, a1 +; RV32ZBB-NEXT: add a0, a2, a0 +; RV32ZBB-NEXT: add a1, a3, a1 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: test_bswap_bitreverse_i64: @@ -1268,17 +1268,17 @@ define i64 @test_bswap_bitreverse_i64(i64 %a) nounwind { ; RV64ZBB-NEXT: and a4, a4, a1 ; RV64ZBB-NEXT: and a0, a0, a1 ; RV64ZBB-NEXT: slli a0, a0, 4 -; RV64ZBB-NEXT: or a0, a4, a0 +; RV64ZBB-NEXT: add a0, a4, a0 ; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: slli a0, a0, 2 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: and a0, a0, a3 ; RV64ZBB-NEXT: and a1, a1, a3 ; RV64ZBB-NEXT: slli a0, a0, 1 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: ret ; ; RV32ZBKB-LABEL: test_bswap_bitreverse_i64: @@ -1307,19 +1307,19 @@ define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind { ; RV32I-NEXT: lui a2, 3 ; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: lui a2, 5 ; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 1 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bitreverse_bswap_i16: @@ -1332,19 +1332,19 @@ define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind { ; RV64I-NEXT: lui a2, 3 ; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: slli a0, a0, 4 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 5 ; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: slli a0, a0, 2 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slli a0, a0, 1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_bitreverse_bswap_i16: @@ -1357,19 +1357,19 @@ define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind { ; RV32ZBB-NEXT: lui a2, 3 ; RV32ZBB-NEXT: addi a2, a2, 819 ; RV32ZBB-NEXT: slli a0, a0, 4 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: lui a2, 5 ; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: slli a0, a0, 1 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: test_bitreverse_bswap_i16: @@ -1382,19 +1382,19 @@ define i16 @test_bitreverse_bswap_i16(i16 %a) nounwind { ; RV64ZBB-NEXT: lui a2, 3 ; RV64ZBB-NEXT: addi a2, a2, 819 ; RV64ZBB-NEXT: slli a0, a0, 4 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: lui a2, 5 ; RV64ZBB-NEXT: addi a2, a2, 1365 ; RV64ZBB-NEXT: slli a0, a0, 2 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: slli a0, a0, 1 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: ret ; ; RV32ZBKB-LABEL: test_bitreverse_bswap_i16: @@ -1422,19 +1422,19 @@ define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind { ; RV32I-NEXT: lui a2, 209715 ; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: lui a2, 349525 ; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 1 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bitreverse_bswap_i32: @@ -1447,19 +1447,19 @@ define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind { ; RV64I-NEXT: lui a2, 209715 ; RV64I-NEXT: addi a2, a2, 819 ; RV64I-NEXT: slliw a0, a0, 4 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: lui a2, 349525 ; RV64I-NEXT: addi a2, a2, 1365 ; RV64I-NEXT: slliw a0, a0, 2 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slliw a0, a0, 1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_bitreverse_bswap_i32: @@ -1472,19 +1472,19 @@ define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind { ; RV32ZBB-NEXT: lui a2, 209715 ; RV32ZBB-NEXT: addi a2, a2, 819 ; RV32ZBB-NEXT: slli a0, a0, 4 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: lui a2, 349525 ; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: slli a0, a0, 1 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: test_bitreverse_bswap_i32: @@ -1497,19 +1497,19 @@ define i32 @test_bitreverse_bswap_i32(i32 %a) nounwind { ; RV64ZBB-NEXT: lui a2, 209715 ; RV64ZBB-NEXT: addi a2, a2, 819 ; RV64ZBB-NEXT: slliw a0, a0, 4 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: lui a2, 349525 ; RV64ZBB-NEXT: addi a2, a2, 1365 ; RV64ZBB-NEXT: slliw a0, a0, 2 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: slliw a0, a0, 1 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: ret ; ; RV32ZBKB-LABEL: test_bitreverse_bswap_i32: @@ -1543,8 +1543,8 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind { ; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: slli a0, a0, 4 ; RV32I-NEXT: slli a1, a1, 4 -; RV32I-NEXT: or a0, a2, a0 -; RV32I-NEXT: or a1, a5, a1 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: add a1, a5, a1 ; RV32I-NEXT: srli a2, a0, 2 ; RV32I-NEXT: and a0, a0, a4 ; RV32I-NEXT: srli a5, a1, 2 @@ -1553,8 +1553,8 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 2 ; RV32I-NEXT: and a4, a5, a4 ; RV32I-NEXT: slli a1, a1, 2 -; RV32I-NEXT: or a0, a2, a0 -; RV32I-NEXT: or a1, a4, a1 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: add a1, a4, a1 ; RV32I-NEXT: srli a2, a0, 1 ; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: srli a4, a1, 1 @@ -1563,8 +1563,8 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind { ; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: and a3, a4, a3 ; RV32I-NEXT: slli a1, a1, 1 -; RV32I-NEXT: or a0, a2, a0 -; RV32I-NEXT: or a1, a3, a1 +; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: test_bitreverse_bswap_i64: @@ -1585,17 +1585,17 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind { ; RV64I-NEXT: and a4, a4, a1 ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: slli a0, a0, 4 -; RV64I-NEXT: or a0, a4, a0 +; RV64I-NEXT: add a0, a4, a0 ; RV64I-NEXT: srli a1, a0, 2 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slli a0, a0, 2 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a1, a1, a3 ; RV64I-NEXT: slli a0, a0, 1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV32ZBB-LABEL: test_bitreverse_bswap_i64: @@ -1614,8 +1614,8 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind { ; RV32ZBB-NEXT: addi a3, a3, 1365 ; RV32ZBB-NEXT: slli a0, a0, 4 ; RV32ZBB-NEXT: slli a1, a1, 4 -; RV32ZBB-NEXT: or a0, a2, a0 -; RV32ZBB-NEXT: or a1, a5, a1 +; RV32ZBB-NEXT: add a0, a2, a0 +; RV32ZBB-NEXT: add a1, a5, a1 ; RV32ZBB-NEXT: srli a2, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a4 ; RV32ZBB-NEXT: srli a5, a1, 2 @@ -1624,8 +1624,8 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind { ; RV32ZBB-NEXT: slli a0, a0, 2 ; RV32ZBB-NEXT: and a4, a5, a4 ; RV32ZBB-NEXT: slli a1, a1, 2 -; RV32ZBB-NEXT: or a0, a2, a0 -; RV32ZBB-NEXT: or a1, a4, a1 +; RV32ZBB-NEXT: add a0, a2, a0 +; RV32ZBB-NEXT: add a1, a4, a1 ; RV32ZBB-NEXT: srli a2, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a3 ; RV32ZBB-NEXT: srli a4, a1, 1 @@ -1634,8 +1634,8 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind { ; RV32ZBB-NEXT: slli a0, a0, 1 ; RV32ZBB-NEXT: and a3, a4, a3 ; RV32ZBB-NEXT: slli a1, a1, 1 -; RV32ZBB-NEXT: or a0, a2, a0 -; RV32ZBB-NEXT: or a1, a3, a1 +; RV32ZBB-NEXT: add a0, a2, a0 +; RV32ZBB-NEXT: add a1, a3, a1 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: test_bitreverse_bswap_i64: @@ -1656,17 +1656,17 @@ define i64 @test_bitreverse_bswap_i64(i64 %a) nounwind { ; RV64ZBB-NEXT: and a4, a4, a1 ; RV64ZBB-NEXT: and a0, a0, a1 ; RV64ZBB-NEXT: slli a0, a0, 4 -; RV64ZBB-NEXT: or a0, a4, a0 +; RV64ZBB-NEXT: add a0, a4, a0 ; RV64ZBB-NEXT: srli a1, a0, 2 ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: and a1, a1, a2 ; RV64ZBB-NEXT: slli a0, a0, 2 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: srli a1, a0, 1 ; RV64ZBB-NEXT: and a0, a0, a3 ; RV64ZBB-NEXT: and a1, a1, a3 ; RV64ZBB-NEXT: slli a0, a0, 1 -; RV64ZBB-NEXT: or a0, a1, a0 +; RV64ZBB-NEXT: add a0, a1, a0 ; RV64ZBB-NEXT: ret ; ; RV32ZBKB-LABEL: test_bitreverse_bswap_i64: diff --git a/llvm/test/CodeGen/RISCV/condbinops.ll b/llvm/test/CodeGen/RISCV/condbinops.ll index 91052bce9704c..fd0abed877219 100644 --- a/llvm/test/CodeGen/RISCV/condbinops.ll +++ b/llvm/test/CodeGen/RISCV/condbinops.ll @@ -464,7 +464,7 @@ define i64 @shl64(i64 %x, i64 %y, i1 %c) { ; RV32ZICOND-NEXT: czero.nez a3, a0, a4 ; RV32ZICOND-NEXT: or a1, a1, a2 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4 -; RV32ZICOND-NEXT: or a1, a1, a3 +; RV32ZICOND-NEXT: add a1, a1, a3 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 ; RV32ZICOND-NEXT: ret ; @@ -541,8 +541,8 @@ define i64 @ashr64(i64 %x, i64 %y, i1 %c) { ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4 ; RV32ZICOND-NEXT: czero.nez a2, a5, a4 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 -; RV32ZICOND-NEXT: or a0, a0, a3 -; RV32ZICOND-NEXT: or a1, a1, a2 +; RV32ZICOND-NEXT: add a0, a0, a3 +; RV32ZICOND-NEXT: add a1, a1, a2 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: ashr64: @@ -615,7 +615,7 @@ define i64 @lshr64(i64 %x, i64 %y, i1 %c) { ; RV32ZICOND-NEXT: czero.nez a3, a1, a4 ; RV32ZICOND-NEXT: or a0, a0, a2 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 -; RV32ZICOND-NEXT: or a0, a0, a3 +; RV32ZICOND-NEXT: add a0, a0, a3 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4 ; RV32ZICOND-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll index 6c2ba493ffcd5..c452bbb452cce 100644 --- a/llvm/test/CodeGen/RISCV/condops.ll +++ b/llvm/test/CodeGen/RISCV/condops.ll @@ -1306,15 +1306,15 @@ define i64 @basic(i1 zeroext %rc, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a1, a3 -; RV32XVENTANACONDOPS-NEXT: or a1, a2, a4 +; RV32XVENTANACONDOPS-NEXT: add a0, a1, a3 +; RV32XVENTANACONDOPS-NEXT: add a1, a2, a4 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: basic: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: basic: @@ -1329,15 +1329,15 @@ define i64 @basic(i1 zeroext %rc, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.eqz a1, a1, a0 ; RV32ZICOND-NEXT: czero.nez a4, a4, a0 ; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 -; RV32ZICOND-NEXT: or a0, a1, a3 -; RV32ZICOND-NEXT: or a1, a2, a4 +; RV32ZICOND-NEXT: add a0, a1, a3 +; RV32ZICOND-NEXT: add a1, a2, a4 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: basic: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: czero.nez a2, a2, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 -; RV64ZICOND-NEXT: or a0, a0, a2 +; RV64ZICOND-NEXT: add a0, a0, a2 ; RV64ZICOND-NEXT: ret %sel = select i1 %rc, i64 %rs1, i64 %rs2 ret i64 %sel @@ -1376,8 +1376,8 @@ define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a4, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: seteq: @@ -1385,7 +1385,7 @@ define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: seteq: @@ -1404,8 +1404,8 @@ define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.nez a2, a4, a0 ; RV32ZICOND-NEXT: czero.eqz a3, a7, a0 ; RV32ZICOND-NEXT: czero.nez a4, a5, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a4, a3 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a4, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: seteq: @@ -1413,7 +1413,7 @@ define i64 @seteq(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: xor a0, a0, a1 ; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 ; RV64ZICOND-NEXT: czero.nez a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp eq i64 %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -1453,8 +1453,8 @@ define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a4, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setne: @@ -1462,7 +1462,7 @@ define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: xor a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setne: @@ -1481,8 +1481,8 @@ define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.eqz a2, a4, a0 ; RV32ZICOND-NEXT: czero.nez a3, a7, a0 ; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a4, a3 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a4, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setne: @@ -1490,7 +1490,7 @@ define i64 @setne(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: xor a0, a0, a1 ; RV64ZICOND-NEXT: czero.nez a1, a3, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp ne i64 %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -1532,13 +1532,13 @@ define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 -; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV32XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a4, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setgt: @@ -1546,7 +1546,7 @@ define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setgt: @@ -1563,13 +1563,13 @@ define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: sltu a0, a2, a0 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: czero.nez a1, a6, a0 ; RV32ZICOND-NEXT: czero.eqz a2, a4, a0 ; RV32ZICOND-NEXT: czero.nez a3, a7, a0 ; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a4, a3 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a4, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setgt: @@ -1577,7 +1577,7 @@ define i64 @setgt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: slt a0, a1, a0 ; RV64ZICOND-NEXT: czero.nez a1, a3, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp sgt i64 %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -1619,13 +1619,13 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 -; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV32XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a4, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setge: @@ -1633,7 +1633,7 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setge: @@ -1650,13 +1650,13 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: sltu a0, a0, a2 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a6, a0 ; RV32ZICOND-NEXT: czero.nez a2, a4, a0 ; RV32ZICOND-NEXT: czero.eqz a3, a7, a0 ; RV32ZICOND-NEXT: czero.nez a4, a5, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a4, a3 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a4, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setge: @@ -1664,7 +1664,7 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: slt a0, a0, a1 ; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 ; RV64ZICOND-NEXT: czero.nez a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp sge i64 %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -1706,13 +1706,13 @@ define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 -; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV32XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a4, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setlt: @@ -1720,7 +1720,7 @@ define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: slt a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setlt: @@ -1737,13 +1737,13 @@ define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: sltu a0, a0, a2 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: czero.nez a1, a6, a0 ; RV32ZICOND-NEXT: czero.eqz a2, a4, a0 ; RV32ZICOND-NEXT: czero.nez a3, a7, a0 ; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a4, a3 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a4, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setlt: @@ -1751,7 +1751,7 @@ define i64 @setlt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: slt a0, a0, a1 ; RV64ZICOND-NEXT: czero.nez a1, a3, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp slt i64 %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -1793,13 +1793,13 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 -; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV32XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a4, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setle: @@ -1807,7 +1807,7 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: slt a0, a1, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setle: @@ -1824,13 +1824,13 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: sltu a0, a2, a0 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a6, a0 ; RV32ZICOND-NEXT: czero.nez a2, a4, a0 ; RV32ZICOND-NEXT: czero.eqz a3, a7, a0 ; RV32ZICOND-NEXT: czero.nez a4, a5, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a4, a3 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a4, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setle: @@ -1838,7 +1838,7 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: slt a0, a1, a0 ; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 ; RV64ZICOND-NEXT: czero.nez a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp sle i64 %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -1880,13 +1880,13 @@ define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 -; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV32XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a4, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setugt: @@ -1894,7 +1894,7 @@ define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setugt: @@ -1911,13 +1911,13 @@ define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: sltu a0, a2, a0 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: czero.nez a1, a6, a0 ; RV32ZICOND-NEXT: czero.eqz a2, a4, a0 ; RV32ZICOND-NEXT: czero.nez a3, a7, a0 ; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a4, a3 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a4, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setugt: @@ -1925,7 +1925,7 @@ define i64 @setugt(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: sltu a0, a1, a0 ; RV64ZICOND-NEXT: czero.nez a1, a3, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp ugt i64 %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -1967,13 +1967,13 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 -; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV32XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a4, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setuge: @@ -1981,7 +1981,7 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setuge: @@ -1998,13 +1998,13 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: sltu a0, a0, a2 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a6, a0 ; RV32ZICOND-NEXT: czero.nez a2, a4, a0 ; RV32ZICOND-NEXT: czero.eqz a3, a7, a0 ; RV32ZICOND-NEXT: czero.nez a4, a5, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a4, a3 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a4, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setuge: @@ -2012,7 +2012,7 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: sltu a0, a0, a1 ; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 ; RV64ZICOND-NEXT: czero.nez a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp uge i64 %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -2054,13 +2054,13 @@ define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: sltu a0, a0, a2 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 -; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV32XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a6, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a7, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a4, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setult: @@ -2068,7 +2068,7 @@ define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: sltu a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a2, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setult: @@ -2085,13 +2085,13 @@ define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: sltu a0, a0, a2 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: czero.nez a1, a6, a0 ; RV32ZICOND-NEXT: czero.eqz a2, a4, a0 ; RV32ZICOND-NEXT: czero.nez a3, a7, a0 ; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a4, a3 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a4, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setult: @@ -2099,7 +2099,7 @@ define i64 @setult(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: sltu a0, a0, a1 ; RV64ZICOND-NEXT: czero.nez a1, a3, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp ult i64 %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -2141,13 +2141,13 @@ define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: sltu a0, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, t0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, t0 -; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV32XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a6, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a4, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a7, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a4, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a4, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setule: @@ -2155,7 +2155,7 @@ define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: sltu a0, a1, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a3, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a2, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setule: @@ -2172,13 +2172,13 @@ define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: sltu a0, a2, a0 ; RV32ZICOND-NEXT: czero.eqz a1, a1, t0 ; RV32ZICOND-NEXT: czero.nez a0, a0, t0 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a6, a0 ; RV32ZICOND-NEXT: czero.nez a2, a4, a0 ; RV32ZICOND-NEXT: czero.eqz a3, a7, a0 ; RV32ZICOND-NEXT: czero.nez a4, a5, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a4, a3 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a4, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setule: @@ -2186,7 +2186,7 @@ define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: sltu a0, a1, a0 ; RV64ZICOND-NEXT: czero.eqz a1, a3, a0 ; RV64ZICOND-NEXT: czero.nez a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = icmp ule i64 %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -2222,15 +2222,15 @@ define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a3, a4 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: seteq_zero: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: seteq_zero: @@ -2246,15 +2246,15 @@ define i64 @seteq_zero(i64 %a, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.nez a2, a2, a0 ; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 ; RV32ZICOND-NEXT: czero.nez a3, a3, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a3, a4 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a3, a4 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: seteq_zero: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: czero.eqz a2, a2, a0 ; RV64ZICOND-NEXT: czero.nez a0, a1, a0 -; RV64ZICOND-NEXT: or a0, a0, a2 +; RV64ZICOND-NEXT: add a0, a0, a2 ; RV64ZICOND-NEXT: ret %rc = icmp eq i64 %a, 0 %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -2290,15 +2290,15 @@ define i64 @setne_zero(i64 %a, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a3, a4 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setne_zero: ; RV64XVENTANACONDOPS: # %bb.0: ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setne_zero: @@ -2314,15 +2314,15 @@ define i64 @setne_zero(i64 %a, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 ; RV32ZICOND-NEXT: czero.nez a4, a5, a0 ; RV32ZICOND-NEXT: czero.eqz a3, a3, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a3, a4 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a3, a4 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setne_zero: ; RV64ZICOND: # %bb.0: ; RV64ZICOND-NEXT: czero.nez a2, a2, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 -; RV64ZICOND-NEXT: or a0, a0, a2 +; RV64ZICOND-NEXT: add a0, a0, a2 ; RV64ZICOND-NEXT: ret %rc = icmp ne i64 %a, 0 %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -2361,8 +2361,8 @@ define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a3, a4 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: seteq_constant: @@ -2370,7 +2370,7 @@ define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -123 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: seteq_constant: @@ -2388,8 +2388,8 @@ define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.nez a2, a2, a0 ; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 ; RV32ZICOND-NEXT: czero.nez a3, a3, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a3, a4 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a3, a4 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: seteq_constant: @@ -2397,7 +2397,7 @@ define i64 @seteq_constant(i64 %a, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: addi a0, a0, -123 ; RV64ZICOND-NEXT: czero.eqz a2, a2, a0 ; RV64ZICOND-NEXT: czero.nez a0, a1, a0 -; RV64ZICOND-NEXT: or a0, a0, a2 +; RV64ZICOND-NEXT: add a0, a0, a2 ; RV64ZICOND-NEXT: ret %rc = icmp eq i64 %a, 123 %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -2436,8 +2436,8 @@ define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a3, a4 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setne_constant: @@ -2445,7 +2445,7 @@ define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -456 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setne_constant: @@ -2463,8 +2463,8 @@ define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 ; RV32ZICOND-NEXT: czero.nez a4, a5, a0 ; RV32ZICOND-NEXT: czero.eqz a3, a3, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a3, a4 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a3, a4 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setne_constant: @@ -2472,7 +2472,7 @@ define i64 @setne_constant(i64 %a, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: addi a0, a0, -456 ; RV64ZICOND-NEXT: czero.nez a2, a2, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 -; RV64ZICOND-NEXT: or a0, a0, a2 +; RV64ZICOND-NEXT: add a0, a0, a2 ; RV64ZICOND-NEXT: ret %rc = icmp ne i64 %a, 456 %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -2511,8 +2511,8 @@ define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a3, a4 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: seteq_2048: @@ -2520,7 +2520,7 @@ define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: addi a0, a0, -2048 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: seteq_2048: @@ -2538,8 +2538,8 @@ define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.nez a2, a2, a0 ; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 ; RV32ZICOND-NEXT: czero.nez a3, a3, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a3, a4 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a3, a4 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: seteq_2048: @@ -2547,7 +2547,7 @@ define i64 @seteq_2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: addi a0, a0, -2048 ; RV64ZICOND-NEXT: czero.eqz a2, a2, a0 ; RV64ZICOND-NEXT: czero.nez a0, a1, a0 -; RV64ZICOND-NEXT: or a0, a0, a2 +; RV64ZICOND-NEXT: add a0, a0, a2 ; RV64ZICOND-NEXT: ret %rc = icmp eq i64 %a, 2048 %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -2588,8 +2588,8 @@ define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a4, a5, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a3, a3, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a3, a4 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: seteq_neg2048: @@ -2597,7 +2597,7 @@ define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a1, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: seteq_neg2048: @@ -2616,8 +2616,8 @@ define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.nez a2, a2, a0 ; RV32ZICOND-NEXT: czero.eqz a4, a5, a0 ; RV32ZICOND-NEXT: czero.nez a3, a3, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a3, a4 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a3, a4 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: seteq_neg2048: @@ -2625,7 +2625,7 @@ define i64 @seteq_neg2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: xori a0, a0, -2048 ; RV64ZICOND-NEXT: czero.eqz a2, a2, a0 ; RV64ZICOND-NEXT: czero.nez a0, a1, a0 -; RV64ZICOND-NEXT: or a0, a0, a2 +; RV64ZICOND-NEXT: add a0, a0, a2 ; RV64ZICOND-NEXT: ret %rc = icmp eq i64 %a, -2048 %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -2666,8 +2666,8 @@ define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a4, a5, a0 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a0 -; RV32XVENTANACONDOPS-NEXT: or a0, a2, a1 -; RV32XVENTANACONDOPS-NEXT: or a1, a3, a4 +; RV32XVENTANACONDOPS-NEXT: add a0, a2, a1 +; RV32XVENTANACONDOPS-NEXT: add a1, a3, a4 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setne_neg2048: @@ -2675,7 +2675,7 @@ define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: xori a0, a0, -2048 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a0, a1, a0 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a2 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a2 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setne_neg2048: @@ -2694,8 +2694,8 @@ define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 ; RV32ZICOND-NEXT: czero.nez a4, a5, a0 ; RV32ZICOND-NEXT: czero.eqz a3, a3, a0 -; RV32ZICOND-NEXT: or a0, a2, a1 -; RV32ZICOND-NEXT: or a1, a3, a4 +; RV32ZICOND-NEXT: add a0, a2, a1 +; RV32ZICOND-NEXT: add a1, a3, a4 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setne_neg2048: @@ -2703,7 +2703,7 @@ define i64 @setne_neg2048(i64 %a, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: xori a0, a0, -2048 ; RV64ZICOND-NEXT: czero.nez a2, a2, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 -; RV64ZICOND-NEXT: or a0, a0, a2 +; RV64ZICOND-NEXT: add a0, a0, a2 ; RV64ZICOND-NEXT: ret %rc = icmp ne i64 %a, -2048 %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -4009,7 +4009,7 @@ define i32 @setune_32(float %a, float %b, i32 %rs1, i32 %rs2) { ; RV32XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 -; RV32XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV32XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setune_32: @@ -4017,7 +4017,7 @@ define i32 @setune_32(float %a, float %b, i32 %rs1, i32 %rs2) { ; RV64XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setune_32: @@ -4031,7 +4031,7 @@ define i32 @setune_32(float %a, float %b, i32 %rs1, i32 %rs2) { ; RV32ZICOND-NEXT: feq.s a2, fa0, fa1 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 ; RV32ZICOND-NEXT: czero.nez a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setune_32: @@ -4039,7 +4039,7 @@ define i32 @setune_32(float %a, float %b, i32 %rs1, i32 %rs2) { ; RV64ZICOND-NEXT: feq.s a2, fa0, fa1 ; RV64ZICOND-NEXT: czero.eqz a1, a1, a2 ; RV64ZICOND-NEXT: czero.nez a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = fcmp une float %a, %b %sel = select i1 %rc, i32 %rs1, i32 %rs2 @@ -4073,8 +4073,8 @@ define i64 @setune_64(float %a, float %b, i64 %rs1, i64 %rs2) { ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a4 ; RV32XVENTANACONDOPS-NEXT: vt.maskc a3, a3, a4 ; RV32XVENTANACONDOPS-NEXT: vt.maskcn a1, a1, a4 -; RV32XVENTANACONDOPS-NEXT: or a0, a0, a2 -; RV32XVENTANACONDOPS-NEXT: or a1, a1, a3 +; RV32XVENTANACONDOPS-NEXT: add a0, a0, a2 +; RV32XVENTANACONDOPS-NEXT: add a1, a1, a3 ; RV32XVENTANACONDOPS-NEXT: ret ; ; RV64XVENTANACONDOPS-LABEL: setune_64: @@ -4082,7 +4082,7 @@ define i64 @setune_64(float %a, float %b, i64 %rs1, i64 %rs2) { ; RV64XVENTANACONDOPS-NEXT: feq.s a2, fa0, fa1 ; RV64XVENTANACONDOPS-NEXT: vt.maskc a1, a1, a2 ; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a0, a2 -; RV64XVENTANACONDOPS-NEXT: or a0, a0, a1 +; RV64XVENTANACONDOPS-NEXT: add a0, a0, a1 ; RV64XVENTANACONDOPS-NEXT: ret ; ; RV64XTHEADCONDMOV-LABEL: setune_64: @@ -4098,8 +4098,8 @@ define i64 @setune_64(float %a, float %b, i64 %rs1, i64 %rs2) { ; RV32ZICOND-NEXT: czero.nez a0, a0, a4 ; RV32ZICOND-NEXT: czero.eqz a3, a3, a4 ; RV32ZICOND-NEXT: czero.nez a1, a1, a4 -; RV32ZICOND-NEXT: or a0, a0, a2 -; RV32ZICOND-NEXT: or a1, a1, a3 +; RV32ZICOND-NEXT: add a0, a0, a2 +; RV32ZICOND-NEXT: add a1, a1, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: setune_64: @@ -4107,7 +4107,7 @@ define i64 @setune_64(float %a, float %b, i64 %rs1, i64 %rs2) { ; RV64ZICOND-NEXT: feq.s a2, fa0, fa1 ; RV64ZICOND-NEXT: czero.eqz a1, a1, a2 ; RV64ZICOND-NEXT: czero.nez a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %rc = fcmp une float %a, %b %sel = select i1 %rc, i64 %rs1, i64 %rs2 @@ -4164,9 +4164,9 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, ; RV32XVENTANACONDOPS-NEXT: addi sp, sp, -16 ; RV32XVENTANACONDOPS-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32XVENTANACONDOPS-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 -; RV32XVENTANACONDOPS-NEXT: vt.maskcn s0, a3, a0 -; RV32XVENTANACONDOPS-NEXT: or s0, s0, a2 +; RV32XVENTANACONDOPS-NEXT: vt.maskc s0, a2, a0 +; RV32XVENTANACONDOPS-NEXT: vt.maskcn a0, a3, a0 +; RV32XVENTANACONDOPS-NEXT: add s0, a0, s0 ; RV32XVENTANACONDOPS-NEXT: beqz a1, .LBB60_2 ; RV32XVENTANACONDOPS-NEXT: # %bb.1: ; RV32XVENTANACONDOPS-NEXT: mv a0, s0 @@ -4183,9 +4183,9 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, ; RV64XVENTANACONDOPS-NEXT: addi sp, sp, -16 ; RV64XVENTANACONDOPS-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64XVENTANACONDOPS-NEXT: sd s0, 0(sp) # 8-byte Folded Spill -; RV64XVENTANACONDOPS-NEXT: vt.maskc a2, a2, a0 -; RV64XVENTANACONDOPS-NEXT: vt.maskcn s0, a3, a0 -; RV64XVENTANACONDOPS-NEXT: or s0, s0, a2 +; RV64XVENTANACONDOPS-NEXT: vt.maskc s0, a2, a0 +; RV64XVENTANACONDOPS-NEXT: vt.maskcn a0, a3, a0 +; RV64XVENTANACONDOPS-NEXT: add s0, a0, s0 ; RV64XVENTANACONDOPS-NEXT: beqz a1, .LBB60_2 ; RV64XVENTANACONDOPS-NEXT: # %bb.1: ; RV64XVENTANACONDOPS-NEXT: mv a0, s0 @@ -4220,9 +4220,9 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, ; RV32ZICOND-NEXT: addi sp, sp, -16 ; RV32ZICOND-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32ZICOND-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32ZICOND-NEXT: czero.eqz a2, a2, a0 -; RV32ZICOND-NEXT: czero.nez s0, a3, a0 -; RV32ZICOND-NEXT: or s0, s0, a2 +; RV32ZICOND-NEXT: czero.eqz s0, a2, a0 +; RV32ZICOND-NEXT: czero.nez a0, a3, a0 +; RV32ZICOND-NEXT: add s0, a0, s0 ; RV32ZICOND-NEXT: beqz a1, .LBB60_2 ; RV32ZICOND-NEXT: # %bb.1: ; RV32ZICOND-NEXT: mv a0, s0 @@ -4239,9 +4239,9 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2, ; RV64ZICOND-NEXT: addi sp, sp, -16 ; RV64ZICOND-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64ZICOND-NEXT: sd s0, 0(sp) # 8-byte Folded Spill -; RV64ZICOND-NEXT: czero.eqz a2, a2, a0 -; RV64ZICOND-NEXT: czero.nez s0, a3, a0 -; RV64ZICOND-NEXT: or s0, s0, a2 +; RV64ZICOND-NEXT: czero.eqz s0, a2, a0 +; RV64ZICOND-NEXT: czero.nez a0, a3, a0 +; RV64ZICOND-NEXT: add s0, a0, s0 ; RV64ZICOND-NEXT: beqz a1, .LBB60_2 ; RV64ZICOND-NEXT: # %bb.1: ; RV64ZICOND-NEXT: mv a0, s0 diff --git a/llvm/test/CodeGen/RISCV/copysign-casts.ll b/llvm/test/CodeGen/RISCV/copysign-casts.ll index 53de36f1699a9..8217a7350f118 100644 --- a/llvm/test/CodeGen/RISCV/copysign-casts.ll +++ b/llvm/test/CodeGen/RISCV/copysign-casts.ll @@ -48,7 +48,7 @@ define double @fold_promote_d_s(double %a, float %b) nounwind { ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: srli a1, a1, 1 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fold_promote_d_s: @@ -58,7 +58,7 @@ define double @fold_promote_d_s(double %a, float %b) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slli a1, a1, 32 ; RV64I-NEXT: srli a0, a0, 1 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32IF-LABEL: fold_promote_d_s: @@ -68,7 +68,7 @@ define double @fold_promote_d_s(double %a, float %b) nounwind { ; RV32IF-NEXT: slli a1, a1, 1 ; RV32IF-NEXT: and a2, a2, a3 ; RV32IF-NEXT: srli a1, a1, 1 -; RV32IF-NEXT: or a1, a1, a2 +; RV32IF-NEXT: add a1, a1, a2 ; RV32IF-NEXT: ret ; ; RV32IFD-LABEL: fold_promote_d_s: @@ -90,7 +90,7 @@ define double @fold_promote_d_s(double %a, float %b) nounwind { ; RV32IFZFH-NEXT: slli a1, a1, 1 ; RV32IFZFH-NEXT: and a2, a2, a3 ; RV32IFZFH-NEXT: srli a1, a1, 1 -; RV32IFZFH-NEXT: or a1, a1, a2 +; RV32IFZFH-NEXT: add a1, a1, a2 ; RV32IFZFH-NEXT: ret ; ; RV32IFDZFH-LABEL: fold_promote_d_s: @@ -112,7 +112,7 @@ define double @fold_promote_d_s(double %a, float %b) nounwind { ; RV32IFZFHMIN-NEXT: slli a1, a1, 1 ; RV32IFZFHMIN-NEXT: and a2, a2, a3 ; RV32IFZFHMIN-NEXT: srli a1, a1, 1 -; RV32IFZFHMIN-NEXT: or a1, a1, a2 +; RV32IFZFHMIN-NEXT: add a1, a1, a2 ; RV32IFZFHMIN-NEXT: ret ; ; RV32IFDZFHMIN-LABEL: fold_promote_d_s: @@ -151,7 +151,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind { ; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: slli a2, a2, 16 ; RV32I-NEXT: srli a1, a1, 1 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fold_promote_d_h: @@ -161,7 +161,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slli a1, a1, 48 ; RV64I-NEXT: srli a0, a0, 1 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32IF-LABEL: fold_promote_d_h: @@ -172,7 +172,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind { ; RV32IF-NEXT: and a2, a2, a3 ; RV32IF-NEXT: slli a2, a2, 16 ; RV32IF-NEXT: srli a1, a1, 1 -; RV32IF-NEXT: or a1, a1, a2 +; RV32IF-NEXT: add a1, a1, a2 ; RV32IF-NEXT: ret ; ; RV32IFD-LABEL: fold_promote_d_h: @@ -213,7 +213,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind { ; RV32IFZFH-NEXT: and a2, a2, a3 ; RV32IFZFH-NEXT: slli a2, a2, 16 ; RV32IFZFH-NEXT: srli a1, a1, 1 -; RV32IFZFH-NEXT: or a1, a1, a2 +; RV32IFZFH-NEXT: add a1, a1, a2 ; RV32IFZFH-NEXT: ret ; ; RV32IFDZFH-LABEL: fold_promote_d_h: @@ -236,7 +236,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind { ; RV32IFZFHMIN-NEXT: and a2, a2, a3 ; RV32IFZFHMIN-NEXT: slli a2, a2, 16 ; RV32IFZFHMIN-NEXT: srli a1, a1, 1 -; RV32IFZFHMIN-NEXT: or a1, a1, a2 +; RV32IFZFHMIN-NEXT: add a1, a1, a2 ; RV32IFZFHMIN-NEXT: ret ; ; RV32IFDZFHMIN-LABEL: fold_promote_d_h: @@ -296,7 +296,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind { ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: srli a0, a0, 1 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fold_promote_f_h: @@ -306,7 +306,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind { ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: slliw a1, a1, 16 ; RV64I-NEXT: srli a0, a0, 33 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32IF-LABEL: fold_promote_f_h: @@ -426,7 +426,7 @@ define float @fold_demote_s_d(float %a, double %b) nounwind { ; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: srli a0, a0, 1 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fold_demote_s_d: @@ -436,7 +436,7 @@ define float @fold_demote_s_d(float %a, double %b) nounwind { ; RV64I-NEXT: srli a0, a0, 33 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: srli a1, a1, 32 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32IF-LABEL: fold_demote_s_d: @@ -519,7 +519,7 @@ define half @fold_demote_h_s(half %a, float %b) nounwind { ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: srli a1, a1, 16 ; RV32I-NEXT: srli a0, a0, 17 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fold_demote_h_s: @@ -528,7 +528,7 @@ define half @fold_demote_h_s(half %a, float %b) nounwind { ; RV64I-NEXT: slli a0, a0, 49 ; RV64I-NEXT: slli a1, a1, 15 ; RV64I-NEXT: srli a0, a0, 49 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32IF-LABEL: fold_demote_h_s: @@ -540,9 +540,9 @@ define half @fold_demote_h_s(half %a, float %b) nounwind { ; RV32IF-NEXT: slli a0, a0, 17 ; RV32IF-NEXT: srli a1, a1, 16 ; RV32IF-NEXT: srli a0, a0, 17 -; RV32IF-NEXT: or a0, a0, a1 +; RV32IF-NEXT: add a0, a0, a1 ; RV32IF-NEXT: lui a1, 1048560 -; RV32IF-NEXT: or a0, a0, a1 +; RV32IF-NEXT: add a0, a0, a1 ; RV32IF-NEXT: fmv.w.x fa0, a0 ; RV32IF-NEXT: ret ; @@ -555,9 +555,9 @@ define half @fold_demote_h_s(half %a, float %b) nounwind { ; RV32IFD-NEXT: slli a0, a0, 17 ; RV32IFD-NEXT: srli a1, a1, 16 ; RV32IFD-NEXT: srli a0, a0, 17 -; RV32IFD-NEXT: or a0, a0, a1 +; RV32IFD-NEXT: add a0, a0, a1 ; RV32IFD-NEXT: lui a1, 1048560 -; RV32IFD-NEXT: or a0, a0, a1 +; RV32IFD-NEXT: add a0, a0, a1 ; RV32IFD-NEXT: fmv.w.x fa0, a0 ; RV32IFD-NEXT: ret ; @@ -570,7 +570,7 @@ define half @fold_demote_h_s(half %a, float %b) nounwind { ; RV64IFD-NEXT: slli a0, a0, 49 ; RV64IFD-NEXT: srli a1, a1, 16 ; RV64IFD-NEXT: srli a0, a0, 49 -; RV64IFD-NEXT: or a0, a0, a1 +; RV64IFD-NEXT: add a0, a0, a1 ; RV64IFD-NEXT: lui a1, 1048560 ; RV64IFD-NEXT: or a0, a0, a1 ; RV64IFD-NEXT: fmv.w.x fa0, a0 @@ -602,7 +602,7 @@ define half @fold_demote_h_s(half %a, float %b) nounwind { ; RV32IFZFHMIN-NEXT: slli a1, a1, 17 ; RV32IFZFHMIN-NEXT: slli a0, a0, 15 ; RV32IFZFHMIN-NEXT: srli a1, a1, 17 -; RV32IFZFHMIN-NEXT: or a0, a1, a0 +; RV32IFZFHMIN-NEXT: add a0, a1, a0 ; RV32IFZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV32IFZFHMIN-NEXT: ret ; @@ -614,7 +614,7 @@ define half @fold_demote_h_s(half %a, float %b) nounwind { ; RV32IFDZFHMIN-NEXT: slli a1, a1, 17 ; RV32IFDZFHMIN-NEXT: slli a0, a0, 15 ; RV32IFDZFHMIN-NEXT: srli a1, a1, 17 -; RV32IFDZFHMIN-NEXT: or a0, a1, a0 +; RV32IFDZFHMIN-NEXT: add a0, a1, a0 ; RV32IFDZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV32IFDZFHMIN-NEXT: ret ; @@ -626,7 +626,7 @@ define half @fold_demote_h_s(half %a, float %b) nounwind { ; RV64IFDZFHMIN-NEXT: slli a1, a1, 49 ; RV64IFDZFHMIN-NEXT: slli a0, a0, 15 ; RV64IFDZFHMIN-NEXT: srli a1, a1, 49 -; RV64IFDZFHMIN-NEXT: or a0, a1, a0 +; RV64IFDZFHMIN-NEXT: add a0, a1, a0 ; RV64IFDZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV64IFDZFHMIN-NEXT: ret ; @@ -640,8 +640,8 @@ define half @fold_demote_h_s(half %a, float %b) nounwind { ; RV32IZDINX-NEXT: lui a2, 1048560 ; RV32IZDINX-NEXT: srli a0, a0, 17 ; RV32IZDINX-NEXT: srli a1, a1, 16 -; RV32IZDINX-NEXT: or a0, a0, a2 -; RV32IZDINX-NEXT: or a0, a0, a1 +; RV32IZDINX-NEXT: add a0, a0, a2 +; RV32IZDINX-NEXT: add a0, a0, a1 ; RV32IZDINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10 ; RV32IZDINX-NEXT: ret ; @@ -652,10 +652,10 @@ define half @fold_demote_h_s(half %a, float %b) nounwind { ; RV64IZDINX-NEXT: lui a2, 524288 ; RV64IZDINX-NEXT: slli a0, a0, 49 ; RV64IZDINX-NEXT: and a1, a1, a2 -; RV64IZDINX-NEXT: lui a2, 1048560 ; RV64IZDINX-NEXT: srli a0, a0, 49 ; RV64IZDINX-NEXT: srli a1, a1, 16 -; RV64IZDINX-NEXT: or a0, a0, a2 +; RV64IZDINX-NEXT: add a0, a0, a1 +; RV64IZDINX-NEXT: lui a1, 1048560 ; RV64IZDINX-NEXT: or a0, a0, a1 ; RV64IZDINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10 ; RV64IZDINX-NEXT: ret @@ -672,7 +672,7 @@ define half @fold_demote_h_d(half %a, double %b) nounwind { ; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: srli a1, a1, 16 ; RV32I-NEXT: srli a0, a0, 17 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fold_demote_h_d: @@ -682,7 +682,7 @@ define half @fold_demote_h_d(half %a, double %b) nounwind { ; RV64I-NEXT: srli a0, a0, 49 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: srli a1, a1, 48 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32IF-LABEL: fold_demote_h_d: @@ -693,9 +693,9 @@ define half @fold_demote_h_d(half %a, double %b) nounwind { ; RV32IF-NEXT: slli a0, a0, 17 ; RV32IF-NEXT: srli a1, a1, 16 ; RV32IF-NEXT: srli a0, a0, 17 -; RV32IF-NEXT: or a0, a0, a1 +; RV32IF-NEXT: add a0, a0, a1 ; RV32IF-NEXT: lui a1, 1048560 -; RV32IF-NEXT: or a0, a0, a1 +; RV32IF-NEXT: add a0, a0, a1 ; RV32IF-NEXT: fmv.w.x fa0, a0 ; RV32IF-NEXT: ret ; @@ -711,8 +711,8 @@ define half @fold_demote_h_d(half %a, double %b) nounwind { ; RV32IFD-NEXT: slli a1, a1, 17 ; RV32IFD-NEXT: srli a1, a1, 17 ; RV32IFD-NEXT: srli a0, a0, 16 -; RV32IFD-NEXT: or a1, a1, a2 -; RV32IFD-NEXT: or a0, a1, a0 +; RV32IFD-NEXT: add a1, a1, a2 +; RV32IFD-NEXT: add a0, a1, a0 ; RV32IFD-NEXT: fmv.w.x fa0, a0 ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -727,8 +727,8 @@ define half @fold_demote_h_d(half %a, double %b) nounwind { ; RV64IFD-NEXT: srli a1, a1, 49 ; RV64IFD-NEXT: slli a0, a0, 63 ; RV64IFD-NEXT: srli a0, a0, 48 -; RV64IFD-NEXT: or a1, a1, a2 -; RV64IFD-NEXT: or a0, a1, a0 +; RV64IFD-NEXT: add a1, a1, a2 +; RV64IFD-NEXT: add a0, a1, a0 ; RV64IFD-NEXT: fmv.w.x fa0, a0 ; RV64IFD-NEXT: ret ; @@ -758,7 +758,7 @@ define half @fold_demote_h_d(half %a, double %b) nounwind { ; RV32IFZFHMIN-NEXT: slli a1, a1, 15 ; RV32IFZFHMIN-NEXT: slli a0, a0, 17 ; RV32IFZFHMIN-NEXT: srli a0, a0, 17 -; RV32IFZFHMIN-NEXT: or a0, a0, a1 +; RV32IFZFHMIN-NEXT: add a0, a0, a1 ; RV32IFZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV32IFZFHMIN-NEXT: ret ; @@ -772,7 +772,7 @@ define half @fold_demote_h_d(half %a, double %b) nounwind { ; RV32IFDZFHMIN-NEXT: srli a0, a0, 31 ; RV32IFDZFHMIN-NEXT: slli a0, a0, 15 ; RV32IFDZFHMIN-NEXT: srli a1, a1, 17 -; RV32IFDZFHMIN-NEXT: or a0, a1, a0 +; RV32IFDZFHMIN-NEXT: add a0, a1, a0 ; RV32IFDZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV32IFDZFHMIN-NEXT: addi sp, sp, 16 ; RV32IFDZFHMIN-NEXT: ret @@ -785,7 +785,7 @@ define half @fold_demote_h_d(half %a, double %b) nounwind { ; RV64IFDZFHMIN-NEXT: slli a1, a1, 49 ; RV64IFDZFHMIN-NEXT: slli a0, a0, 15 ; RV64IFDZFHMIN-NEXT: srli a1, a1, 49 -; RV64IFDZFHMIN-NEXT: or a0, a1, a0 +; RV64IFDZFHMIN-NEXT: add a0, a1, a0 ; RV64IFDZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV64IFDZFHMIN-NEXT: ret ; @@ -798,8 +798,8 @@ define half @fold_demote_h_d(half %a, double %b) nounwind { ; RV32IZDINX-NEXT: lui a2, 1048560 ; RV32IZDINX-NEXT: srli a0, a0, 17 ; RV32IZDINX-NEXT: srli a1, a1, 16 -; RV32IZDINX-NEXT: or a0, a0, a2 -; RV32IZDINX-NEXT: or a0, a0, a1 +; RV32IZDINX-NEXT: add a0, a0, a2 +; RV32IZDINX-NEXT: add a0, a0, a1 ; RV32IZDINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10 ; RV32IZDINX-NEXT: ret ; @@ -812,8 +812,8 @@ define half @fold_demote_h_d(half %a, double %b) nounwind { ; RV64IZDINX-NEXT: srli a0, a0, 49 ; RV64IZDINX-NEXT: slli a1, a1, 63 ; RV64IZDINX-NEXT: srli a1, a1, 48 -; RV64IZDINX-NEXT: or a0, a0, a2 -; RV64IZDINX-NEXT: or a0, a0, a1 +; RV64IZDINX-NEXT: add a0, a0, a2 +; RV64IZDINX-NEXT: add a0, a0, a1 ; RV64IZDINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10 ; RV64IZDINX-NEXT: ret %c = fptrunc double %b to half diff --git a/llvm/test/CodeGen/RISCV/div-pow2.ll b/llvm/test/CodeGen/RISCV/div-pow2.ll index 6ea5a37ba2963..580eaeb4c2a72 100644 --- a/llvm/test/CodeGen/RISCV/div-pow2.ll +++ b/llvm/test/CodeGen/RISCV/div-pow2.ll @@ -185,7 +185,7 @@ define i64 @sdiv64_pow2_2(i64 %a) { ; RV32I-NEXT: sltu a0, a2, a0 ; RV32I-NEXT: add a1, a1, a0 ; RV32I-NEXT: slli a0, a1, 31 -; RV32I-NEXT: or a0, a3, a0 +; RV32I-NEXT: add a0, a3, a0 ; RV32I-NEXT: srai a1, a1, 1 ; RV32I-NEXT: ret ; @@ -210,7 +210,7 @@ define i64 @sdiv64_pow2_negative_2(i64 %a) { ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: slli a1, a0, 31 ; RV32I-NEXT: srai a2, a0, 1 -; RV32I-NEXT: or a1, a3, a1 +; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: neg a0, a1 ; RV32I-NEXT: snez a1, a1 ; RV32I-NEXT: neg a2, a2 @@ -239,7 +239,7 @@ define i64 @sdiv64_pow2_2048(i64 %a) { ; RV32I-NEXT: sltu a0, a2, a0 ; RV32I-NEXT: add a1, a1, a0 ; RV32I-NEXT: slli a0, a1, 21 -; RV32I-NEXT: or a0, a3, a0 +; RV32I-NEXT: add a0, a3, a0 ; RV32I-NEXT: srai a1, a1, 11 ; RV32I-NEXT: ret ; @@ -266,7 +266,7 @@ define i64 @sdiv64_pow2_negative_2048(i64 %a) { ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: slli a1, a0, 21 ; RV32I-NEXT: srai a2, a0, 11 -; RV32I-NEXT: or a1, a3, a1 +; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: neg a0, a1 ; RV32I-NEXT: snez a1, a1 ; RV32I-NEXT: neg a2, a2 @@ -296,7 +296,7 @@ define i64 @sdiv64_pow2_4096(i64 %a) { ; RV32I-NEXT: sltu a0, a2, a0 ; RV32I-NEXT: add a1, a1, a0 ; RV32I-NEXT: slli a0, a1, 20 -; RV32I-NEXT: or a0, a3, a0 +; RV32I-NEXT: add a0, a3, a0 ; RV32I-NEXT: srai a1, a1, 12 ; RV32I-NEXT: ret ; @@ -323,7 +323,7 @@ define i64 @sdiv64_pow2_negative_4096(i64 %a) { ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: slli a1, a0, 20 ; RV32I-NEXT: srai a2, a0, 12 -; RV32I-NEXT: or a1, a3, a1 +; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: neg a0, a1 ; RV32I-NEXT: snez a1, a1 ; RV32I-NEXT: neg a2, a2 @@ -353,7 +353,7 @@ define i64 @sdiv64_pow2_65536(i64 %a) { ; RV32I-NEXT: sltu a0, a2, a0 ; RV32I-NEXT: add a1, a1, a0 ; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: or a0, a3, a0 +; RV32I-NEXT: add a0, a3, a0 ; RV32I-NEXT: srai a1, a1, 16 ; RV32I-NEXT: ret ; @@ -380,7 +380,7 @@ define i64 @sdiv64_pow2_negative_65536(i64 %a) { ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: slli a1, a0, 16 ; RV32I-NEXT: srai a2, a0, 16 -; RV32I-NEXT: or a1, a3, a1 +; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: neg a0, a1 ; RV32I-NEXT: snez a1, a1 ; RV32I-NEXT: neg a2, a2 diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll index d6c4f8d5f350f..8b1449ee63c66 100644 --- a/llvm/test/CodeGen/RISCV/double-arith.ll +++ b/llvm/test/CodeGen/RISCV/double-arith.ll @@ -228,7 +228,7 @@ define double @fsgnj_d(double %a, double %b) nounwind { ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: and a2, a3, a2 ; RV32I-NEXT: srli a1, a1, 1 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fsgnj_d: @@ -237,7 +237,7 @@ define double @fsgnj_d(double %a, double %b) nounwind { ; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: srli a0, a0, 1 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret %1 = call double @llvm.copysign.f64(double %a, double %b) ret double %1 @@ -330,7 +330,7 @@ define double @fsgnjn_d(double %a, double %b) nounwind { ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: srli a1, a1, 1 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fsgnjn_d: @@ -340,7 +340,7 @@ define double @fsgnjn_d(double %a, double %b) nounwind { ; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a1, a1, 63 ; RV64I-NEXT: slli a1, a1, 63 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret %1 = fsub double -0.0, %b %2 = call double @llvm.copysign.f64(double %a, double %1) @@ -1504,7 +1504,7 @@ define double @fsgnjx_f64(double %x, double %y) nounwind { ; RV32I-NEXT: lui a0, 524288 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: lui a1, 261888 -; RV32I-NEXT: or a1, a0, a1 +; RV32I-NEXT: add a1, a0, a1 ; RV32I-NEXT: li a0, 0 ; RV32I-NEXT: call __muldf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1519,7 +1519,7 @@ define double @fsgnjx_f64(double %x, double %y) nounwind { ; RV64I-NEXT: li a2, 1023 ; RV64I-NEXT: slli a0, a0, 63 ; RV64I-NEXT: slli a2, a2, 52 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: call __muldf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll index 14193bf4cb169..068d2ea004332 100644 --- a/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll +++ b/llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll @@ -115,7 +115,7 @@ define double @fcopysign_fneg(double %a, double %b) nounwind { ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: srli a1, a1, 1 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: ret ; ; RV32IFD-LABEL: fcopysign_fneg: @@ -146,7 +146,7 @@ define double @fcopysign_fneg(double %a, double %b) nounwind { ; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: srli a1, a1, 63 ; RV64I-NEXT: slli a1, a1, 63 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64IFD-LABEL: fcopysign_fneg: diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll index bb57665fa1801..0620544b9803c 100644 --- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll @@ -842,7 +842,7 @@ define double @copysign_f64(double %a, double %b) nounwind { ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: and a2, a3, a2 ; RV32I-NEXT: srli a1, a1, 1 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: ret ; ; RV64I-LABEL: copysign_f64: @@ -851,7 +851,7 @@ define double @copysign_f64(double %a, double %b) nounwind { ; RV64I-NEXT: slli a0, a0, 1 ; RV64I-NEXT: slli a1, a1, 63 ; RV64I-NEXT: srli a0, a0, 1 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret %1 = call double @llvm.copysign.f64(double %a, double %b) ret double %1 diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll index 57b3423da69a6..c533d19f777e6 100644 --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -198,7 +198,7 @@ define float @fsgnj_s(float %a, float %b) nounwind { ; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: srli a0, a0, 1 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fsgnj_s: @@ -207,7 +207,7 @@ define float @fsgnj_s(float %a, float %b) nounwind { ; RV64I-NEXT: slli a0, a0, 33 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: srli a0, a0, 33 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret %1 = call float @llvm.copysign.f32(float %a, float %b) ret float %1 @@ -287,7 +287,7 @@ define float @fsgnjn_s(float %a, float %b) nounwind { ; RV32I-NEXT: slli s0, s0, 1 ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: srli s0, s0, 1 -; RV32I-NEXT: or a0, s0, a0 +; RV32I-NEXT: add a0, s0, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -305,7 +305,7 @@ define float @fsgnjn_s(float %a, float %b) nounwind { ; RV64I-NEXT: slli s0, s0, 33 ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: srli s0, s0, 33 -; RV64I-NEXT: or a0, s0, a0 +; RV64I-NEXT: add a0, s0, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 @@ -1211,7 +1211,7 @@ define float @fsgnjx_f32(float %x, float %y) nounwind { ; RV32I-NEXT: lui a2, 524288 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: lui a2, 260096 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: call __mulsf3 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 @@ -1224,7 +1224,7 @@ define float @fsgnjx_f32(float %x, float %y) nounwind { ; RV64I-NEXT: lui a2, 524288 ; RV64I-NEXT: and a0, a0, a2 ; RV64I-NEXT: lui a2, 260096 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: call __mulsf3 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll index aaeb1b7c0b1fb..0e35df9a5fa04 100644 --- a/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll +++ b/llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll @@ -110,7 +110,7 @@ define float @fcopysign_fneg(float %a, float %b) nounwind { ; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: srli a0, a0, 1 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32IF-LABEL: fcopysign_fneg: @@ -134,7 +134,7 @@ define float @fcopysign_fneg(float %a, float %b) nounwind { ; RV64I-NEXT: slli a0, a0, 33 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: srli a0, a0, 33 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64IF-LABEL: fcopysign_fneg: diff --git a/llvm/test/CodeGen/RISCV/float-intrinsics.ll b/llvm/test/CodeGen/RISCV/float-intrinsics.ll index 8b8a3257a0027..3d961157464bb 100644 --- a/llvm/test/CodeGen/RISCV/float-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/float-intrinsics.ll @@ -831,7 +831,7 @@ define float @copysign_f32(float %a, float %b) nounwind { ; RV32I-NEXT: slli a0, a0, 1 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: srli a0, a0, 1 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: copysign_f32: @@ -840,7 +840,7 @@ define float @copysign_f32(float %a, float %b) nounwind { ; RV64I-NEXT: slli a0, a0, 33 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: srli a0, a0, 33 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret %1 = call float @llvm.copysign.f32(float %a, float %b) ret float %1 diff --git a/llvm/test/CodeGen/RISCV/fold-masked-merge.ll b/llvm/test/CodeGen/RISCV/fold-masked-merge.ll index 631b7109281e5..9eb7a3851ecc0 100644 --- a/llvm/test/CodeGen/RISCV/fold-masked-merge.ll +++ b/llvm/test/CodeGen/RISCV/fold-masked-merge.ll @@ -23,7 +23,7 @@ define i32 @masked_merge0(i32 %a0, i32 %a1, i32 %a2) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: and a1, a0, a1 ; CHECK-ZBB-NEXT: andn a0, a2, a0 -; CHECK-ZBB-NEXT: or a0, a1, a0 +; CHECK-ZBB-NEXT: add a0, a1, a0 ; CHECK-ZBB-NEXT: ret %and0 = and i32 %a0, %a1 %not = xor i32 %a0, -1 @@ -44,7 +44,7 @@ define i16 @masked_merge1(i16 %a0, i16 %a1, i16 %a2) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: and a1, a0, a1 ; CHECK-ZBB-NEXT: andn a0, a2, a0 -; CHECK-ZBB-NEXT: or a0, a1, a0 +; CHECK-ZBB-NEXT: add a0, a1, a0 ; CHECK-ZBB-NEXT: ret %and0 = and i16 %a0, %a1 %not = xor i16 %a0, -1 @@ -63,7 +63,7 @@ define i8 @masked_merge2(i8 %a0, i8 %a1, i8 %a2) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a2, a1, a0 ; CHECK-ZBB-NEXT: and a0, a1, a0 -; CHECK-ZBB-NEXT: or a0, a2, a0 +; CHECK-ZBB-NEXT: add a0, a2, a0 ; CHECK-ZBB-NEXT: ret %not = xor i8 %a0, -1 %and0 = and i8 %not, %a1 @@ -104,8 +104,8 @@ define i64 @masked_merge3(i64 %a0, i64 %a1, i64 %a2) { ; RV32ZBB-NEXT: andn a0, a0, a2 ; RV32ZBB-NEXT: andn a2, a7, a5 ; RV32ZBB-NEXT: andn a3, a6, a4 -; RV32ZBB-NEXT: or a0, a3, a0 -; RV32ZBB-NEXT: or a1, a2, a1 +; RV32ZBB-NEXT: add a0, a3, a0 +; RV32ZBB-NEXT: add a1, a2, a1 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: masked_merge3: @@ -113,7 +113,7 @@ define i64 @masked_merge3(i64 %a0, i64 %a1, i64 %a2) { ; RV64ZBB-NEXT: not a3, a0 ; RV64ZBB-NEXT: andn a2, a3, a2 ; RV64ZBB-NEXT: andn a0, a0, a1 -; RV64ZBB-NEXT: or a0, a2, a0 +; RV64ZBB-NEXT: add a0, a2, a0 ; RV64ZBB-NEXT: ret %v0 = xor i64 %a1, -1 %v1 = xor i64 %a2, -1 @@ -231,7 +231,7 @@ define i32 @masked_merge_no_transform0(i32 %a0, i32 %a1, i32 %a2, ptr %p1) { ; CHECK-I-NEXT: and a1, a0, a1 ; CHECK-I-NEXT: not a0, a0 ; CHECK-I-NEXT: and a0, a0, a2 -; CHECK-I-NEXT: or a0, a1, a0 +; CHECK-I-NEXT: add a0, a1, a0 ; CHECK-I-NEXT: sw a1, 0(a3) ; CHECK-I-NEXT: ret ; @@ -239,7 +239,7 @@ define i32 @masked_merge_no_transform0(i32 %a0, i32 %a1, i32 %a2, ptr %p1) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: and a1, a0, a1 ; CHECK-ZBB-NEXT: andn a0, a2, a0 -; CHECK-ZBB-NEXT: or a0, a1, a0 +; CHECK-ZBB-NEXT: add a0, a1, a0 ; CHECK-ZBB-NEXT: sw a1, 0(a3) ; CHECK-ZBB-NEXT: ret %and0 = and i32 %a0, %a1 @@ -256,7 +256,7 @@ define i32 @masked_merge_no_transform1(i32 %a0, i32 %a1, i32 %a2, ptr %p1) { ; CHECK-I-NEXT: and a1, a0, a1 ; CHECK-I-NEXT: not a4, a0 ; CHECK-I-NEXT: and a0, a4, a2 -; CHECK-I-NEXT: or a0, a1, a0 +; CHECK-I-NEXT: add a0, a1, a0 ; CHECK-I-NEXT: sw a4, 0(a3) ; CHECK-I-NEXT: ret ; @@ -265,7 +265,7 @@ define i32 @masked_merge_no_transform1(i32 %a0, i32 %a1, i32 %a2, ptr %p1) { ; CHECK-ZBB-NEXT: and a1, a0, a1 ; CHECK-ZBB-NEXT: not a4, a0 ; CHECK-ZBB-NEXT: andn a0, a2, a0 -; CHECK-ZBB-NEXT: or a0, a1, a0 +; CHECK-ZBB-NEXT: add a0, a1, a0 ; CHECK-ZBB-NEXT: sw a4, 0(a3) ; CHECK-ZBB-NEXT: ret %and0 = and i32 %a0, %a1 @@ -282,7 +282,7 @@ define i32 @masked_merge_no_transform2(i32 %a0, i32 %a1, i32 %a2, ptr %p1) { ; CHECK-I-NEXT: and a1, a0, a1 ; CHECK-I-NEXT: not a0, a0 ; CHECK-I-NEXT: and a2, a0, a2 -; CHECK-I-NEXT: or a0, a1, a2 +; CHECK-I-NEXT: add a0, a1, a2 ; CHECK-I-NEXT: sw a2, 0(a3) ; CHECK-I-NEXT: ret ; @@ -290,7 +290,7 @@ define i32 @masked_merge_no_transform2(i32 %a0, i32 %a1, i32 %a2, ptr %p1) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: and a1, a0, a1 ; CHECK-ZBB-NEXT: andn a2, a2, a0 -; CHECK-ZBB-NEXT: or a0, a1, a2 +; CHECK-ZBB-NEXT: add a0, a1, a2 ; CHECK-ZBB-NEXT: sw a2, 0(a3) ; CHECK-ZBB-NEXT: ret %and0 = and i32 %a0, %a1 diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll index 84163b52bb98d..93be7b8c500d4 100644 --- a/llvm/test/CodeGen/RISCV/half-arith.ll +++ b/llvm/test/CodeGen/RISCV/half-arith.ll @@ -428,7 +428,7 @@ define half @fsgnj_h(half %a, half %b) nounwind { ; RV32I-NEXT: slli a0, a0, 17 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: srli a0, a0, 17 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fsgnj_h: @@ -437,7 +437,7 @@ define half @fsgnj_h(half %a, half %b) nounwind { ; RV64I-NEXT: slli a0, a0, 49 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: srli a0, a0, 49 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32IZFHMIN-LABEL: fsgnj_h: @@ -448,7 +448,7 @@ define half @fsgnj_h(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: fmv.x.h a1, fa0 ; RV32IZFHMIN-NEXT: slli a1, a1, 17 ; RV32IZFHMIN-NEXT: srli a1, a1, 17 -; RV32IZFHMIN-NEXT: or a0, a1, a0 +; RV32IZFHMIN-NEXT: add a0, a1, a0 ; RV32IZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV32IZFHMIN-NEXT: ret ; @@ -460,7 +460,7 @@ define half @fsgnj_h(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: fmv.x.h a1, fa0 ; RV64IZFHMIN-NEXT: slli a1, a1, 49 ; RV64IZFHMIN-NEXT: srli a1, a1, 49 -; RV64IZFHMIN-NEXT: or a0, a1, a0 +; RV64IZFHMIN-NEXT: add a0, a1, a0 ; RV64IZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV64IZFHMIN-NEXT: ret ; @@ -472,7 +472,7 @@ define half @fsgnj_h(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: slli a0, a0, 17 ; RV32IZHINXMIN-NEXT: and a1, a1, a2 ; RV32IZHINXMIN-NEXT: srli a0, a0, 17 -; RV32IZHINXMIN-NEXT: or a0, a0, a1 +; RV32IZHINXMIN-NEXT: add a0, a0, a1 ; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV32IZHINXMIN-NEXT: ret ; @@ -484,7 +484,7 @@ define half @fsgnj_h(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: slli a0, a0, 49 ; RV64IZHINXMIN-NEXT: and a1, a1, a2 ; RV64IZHINXMIN-NEXT: srli a0, a0, 49 -; RV64IZHINXMIN-NEXT: or a0, a0, a1 +; RV64IZHINXMIN-NEXT: add a0, a0, a1 ; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV64IZHINXMIN-NEXT: ret %1 = call half @llvm.copysign.f16(half %a, half %b) @@ -647,7 +647,7 @@ define half @fsgnjn_h(half %a, half %b) nounwind { ; RV32I-NEXT: slli s1, s1, 17 ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: srli s1, s1, 17 -; RV32I-NEXT: or a0, s1, a0 +; RV32I-NEXT: add a0, s1, a0 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -686,7 +686,7 @@ define half @fsgnjn_h(half %a, half %b) nounwind { ; RV64I-NEXT: slli s1, s1, 49 ; RV64I-NEXT: and a0, a0, a1 ; RV64I-NEXT: srli s1, s1, 49 -; RV64I-NEXT: or a0, s1, a0 +; RV64I-NEXT: add a0, s1, a0 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -708,7 +708,7 @@ define half @fsgnjn_h(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: fmv.x.h a1, fa0 ; RV32IZFHMIN-NEXT: slli a1, a1, 17 ; RV32IZFHMIN-NEXT: srli a1, a1, 17 -; RV32IZFHMIN-NEXT: or a0, a1, a0 +; RV32IZFHMIN-NEXT: add a0, a1, a0 ; RV32IZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV32IZFHMIN-NEXT: ret ; @@ -725,7 +725,7 @@ define half @fsgnjn_h(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: fmv.x.h a1, fa0 ; RV64IZFHMIN-NEXT: slli a1, a1, 49 ; RV64IZFHMIN-NEXT: srli a1, a1, 49 -; RV64IZFHMIN-NEXT: or a0, a1, a0 +; RV64IZFHMIN-NEXT: add a0, a1, a0 ; RV64IZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV64IZFHMIN-NEXT: ret ; @@ -741,7 +741,7 @@ define half @fsgnjn_h(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: not a1, a1 ; RV32IZHINXMIN-NEXT: and a1, a1, a2 ; RV32IZHINXMIN-NEXT: srli a0, a0, 17 -; RV32IZHINXMIN-NEXT: or a0, a0, a1 +; RV32IZHINXMIN-NEXT: add a0, a0, a1 ; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV32IZHINXMIN-NEXT: ret ; @@ -757,7 +757,7 @@ define half @fsgnjn_h(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: not a1, a1 ; RV64IZHINXMIN-NEXT: and a1, a1, a2 ; RV64IZHINXMIN-NEXT: srli a0, a0, 49 -; RV64IZHINXMIN-NEXT: or a0, a0, a1 +; RV64IZHINXMIN-NEXT: add a0, a0, a1 ; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV64IZHINXMIN-NEXT: ret %1 = fadd half %a, %b @@ -2892,7 +2892,7 @@ define half @fsgnjx_f16(half %x, half %y) nounwind { ; RV32IZFHMIN-NEXT: and a1, a1, a2 ; RV32IZFHMIN-NEXT: slli a0, a0, 17 ; RV32IZFHMIN-NEXT: srli a0, a0, 17 -; RV32IZFHMIN-NEXT: or a0, a0, a1 +; RV32IZFHMIN-NEXT: add a0, a0, a1 ; RV32IZFHMIN-NEXT: fmv.h.x fa5, a0 ; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa1 @@ -2909,7 +2909,7 @@ define half @fsgnjx_f16(half %x, half %y) nounwind { ; RV64IZFHMIN-NEXT: and a1, a1, a2 ; RV64IZFHMIN-NEXT: slli a0, a0, 49 ; RV64IZFHMIN-NEXT: srli a0, a0, 49 -; RV64IZFHMIN-NEXT: or a0, a0, a1 +; RV64IZFHMIN-NEXT: add a0, a0, a1 ; RV64IZFHMIN-NEXT: fmv.h.x fa5, a0 ; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa5 ; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa1 @@ -2924,7 +2924,7 @@ define half @fsgnjx_f16(half %x, half %y) nounwind { ; CHECKIZHINXMIN-NEXT: and a0, a0, a2 ; CHECKIZHINXMIN-NEXT: li a2, 15 ; CHECKIZHINXMIN-NEXT: slli a2, a2, 10 -; CHECKIZHINXMIN-NEXT: or a0, a0, a2 +; CHECKIZHINXMIN-NEXT: add a0, a0, a2 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0 ; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1 ; CHECKIZHINXMIN-NEXT: fmul.s a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll b/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll index 730bde5af610b..6ecbfef2a701f 100644 --- a/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll +++ b/llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll @@ -168,7 +168,7 @@ define half @fcopysign_fneg(half %a, half %b) nounwind { ; RV32I-NEXT: slli a0, a0, 17 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: srli a0, a0, 17 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32IZFH-LABEL: fcopysign_fneg: @@ -186,7 +186,7 @@ define half @fcopysign_fneg(half %a, half %b) nounwind { ; RV64I-NEXT: slli a0, a0, 49 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: srli a0, a0, 49 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64IZFH-LABEL: fcopysign_fneg: @@ -214,7 +214,7 @@ define half @fcopysign_fneg(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: slli a0, a0, 17 ; RV32IZFHMIN-NEXT: and a1, a1, a2 ; RV32IZFHMIN-NEXT: srli a0, a0, 17 -; RV32IZFHMIN-NEXT: or a0, a0, a1 +; RV32IZFHMIN-NEXT: add a0, a0, a1 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: fcopysign_fneg: @@ -224,7 +224,7 @@ define half @fcopysign_fneg(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: slli a0, a0, 49 ; RV64IZFHMIN-NEXT: and a1, a1, a2 ; RV64IZFHMIN-NEXT: srli a0, a0, 49 -; RV64IZFHMIN-NEXT: or a0, a0, a1 +; RV64IZFHMIN-NEXT: add a0, a0, a1 ; RV64IZFHMIN-NEXT: ret ; ; RV32IZHINXMIN-LABEL: fcopysign_fneg: @@ -236,7 +236,7 @@ define half @fcopysign_fneg(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: slli a0, a0, 17 ; RV32IZHINXMIN-NEXT: and a1, a1, a2 ; RV32IZHINXMIN-NEXT: srli a0, a0, 17 -; RV32IZHINXMIN-NEXT: or a0, a0, a1 +; RV32IZHINXMIN-NEXT: add a0, a0, a1 ; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV32IZHINXMIN-NEXT: ret ; @@ -249,7 +249,7 @@ define half @fcopysign_fneg(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: slli a0, a0, 49 ; RV64IZHINXMIN-NEXT: and a1, a1, a2 ; RV64IZHINXMIN-NEXT: srli a0, a0, 49 -; RV64IZHINXMIN-NEXT: or a0, a0, a1 +; RV64IZHINXMIN-NEXT: add a0, a0, a1 ; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV64IZHINXMIN-NEXT: ret %1 = fneg half %b diff --git a/llvm/test/CodeGen/RISCV/half-intrinsics.ll b/llvm/test/CodeGen/RISCV/half-intrinsics.ll index 4f0026175e7c7..50e06bdb52baa 100644 --- a/llvm/test/CodeGen/RISCV/half-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/half-intrinsics.ll @@ -2154,7 +2154,7 @@ define half @copysign_f16(half %a, half %b) nounwind { ; RV32I-NEXT: slli a0, a0, 17 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: srli a0, a0, 17 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: copysign_f16: @@ -2163,7 +2163,7 @@ define half @copysign_f16(half %a, half %b) nounwind { ; RV64I-NEXT: slli a0, a0, 49 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: srli a0, a0, 49 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32IZFHMIN-LABEL: copysign_f16: @@ -2174,7 +2174,7 @@ define half @copysign_f16(half %a, half %b) nounwind { ; RV32IZFHMIN-NEXT: fmv.x.h a1, fa0 ; RV32IZFHMIN-NEXT: slli a1, a1, 17 ; RV32IZFHMIN-NEXT: srli a1, a1, 17 -; RV32IZFHMIN-NEXT: or a0, a1, a0 +; RV32IZFHMIN-NEXT: add a0, a1, a0 ; RV32IZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV32IZFHMIN-NEXT: ret ; @@ -2186,7 +2186,7 @@ define half @copysign_f16(half %a, half %b) nounwind { ; RV64IZFHMIN-NEXT: fmv.x.h a1, fa0 ; RV64IZFHMIN-NEXT: slli a1, a1, 49 ; RV64IZFHMIN-NEXT: srli a1, a1, 49 -; RV64IZFHMIN-NEXT: or a0, a1, a0 +; RV64IZFHMIN-NEXT: add a0, a1, a0 ; RV64IZFHMIN-NEXT: fmv.h.x fa0, a0 ; RV64IZFHMIN-NEXT: ret ; @@ -2198,7 +2198,7 @@ define half @copysign_f16(half %a, half %b) nounwind { ; RV32IZHINXMIN-NEXT: slli a0, a0, 17 ; RV32IZHINXMIN-NEXT: and a1, a1, a2 ; RV32IZHINXMIN-NEXT: srli a0, a0, 17 -; RV32IZHINXMIN-NEXT: or a0, a0, a1 +; RV32IZHINXMIN-NEXT: add a0, a0, a1 ; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV32IZHINXMIN-NEXT: ret ; @@ -2210,7 +2210,7 @@ define half @copysign_f16(half %a, half %b) nounwind { ; RV64IZHINXMIN-NEXT: slli a0, a0, 49 ; RV64IZHINXMIN-NEXT: and a1, a1, a2 ; RV64IZHINXMIN-NEXT: srli a0, a0, 49 -; RV64IZHINXMIN-NEXT: or a0, a0, a1 +; RV64IZHINXMIN-NEXT: add a0, a0, a1 ; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV64IZHINXMIN-NEXT: ret %1 = call half @llvm.copysign.f16(half %a, half %b) diff --git a/llvm/test/CodeGen/RISCV/llvm.exp10.ll b/llvm/test/CodeGen/RISCV/llvm.exp10.ll index 7b199504837e8..4720b24de8fde 100644 --- a/llvm/test/CodeGen/RISCV/llvm.exp10.ll +++ b/llvm/test/CodeGen/RISCV/llvm.exp10.ll @@ -162,7 +162,7 @@ define <3 x half> @exp10_v3f16(<3 x half> %x) { ; RV32IFD-NEXT: fmv.x.w a0, fa0 ; RV32IFD-NEXT: slli a0, a0, 16 ; RV32IFD-NEXT: srli a0, a0, 16 -; RV32IFD-NEXT: or s1, a0, s1 +; RV32IFD-NEXT: add s1, a0, s1 ; RV32IFD-NEXT: fmv.s fa0, fs0 ; RV32IFD-NEXT: call __extendhfsf2 ; RV32IFD-NEXT: call exp10f @@ -218,7 +218,7 @@ define <3 x half> @exp10_v3f16(<3 x half> %x) { ; RV64IFD-NEXT: fmv.x.w a0, fa0 ; RV64IFD-NEXT: slli a0, a0, 48 ; RV64IFD-NEXT: srli a0, a0, 48 -; RV64IFD-NEXT: or s1, a0, s1 +; RV64IFD-NEXT: add s1, a0, s1 ; RV64IFD-NEXT: fmv.w.x fa0, s2 ; RV64IFD-NEXT: call __extendhfsf2 ; RV64IFD-NEXT: call exp10f @@ -554,7 +554,7 @@ define <3 x float> @exp10_v3f32(<3 x float> %x) { ; RV64IFD-NEXT: fmv.x.w a0, fa0 ; RV64IFD-NEXT: slli a0, a0, 32 ; RV64IFD-NEXT: srli a0, a0, 32 -; RV64IFD-NEXT: or s1, a0, s1 +; RV64IFD-NEXT: add s1, a0, s1 ; RV64IFD-NEXT: fmv.s fa0, fs0 ; RV64IFD-NEXT: call exp10f ; RV64IFD-NEXT: sd s1, 0(s0) diff --git a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll index afc8e3553f8b1..c3aa6099e739b 100644 --- a/llvm/test/CodeGen/RISCV/memcmp-optsize.ll +++ b/llvm/test/CodeGen/RISCV/memcmp-optsize.ll @@ -3364,9 +3364,9 @@ define i32 @memcmp_size_3(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a3, 2(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lhu a1, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: slli a2, a2, 16 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: add a0, a0, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: slli a3, a3, 16 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: add a1, a1, a3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a2, a0, a1 @@ -3381,9 +3381,9 @@ define i32 @memcmp_size_3(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a3, 2(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 16 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 16 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a1, a1, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a0, a0, 32 @@ -3415,9 +3415,9 @@ define i32 @memcmp_size_3(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a3, 2(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lhu a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: slli a2, a2, 16 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: add a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: slli a3, a3, 16 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: add a1, a1, a3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 32 @@ -3750,9 +3750,9 @@ define i32 @memcmp_size_5(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a3, 4(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a1, a1, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 @@ -3949,9 +3949,9 @@ define i32 @memcmp_size_6(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a3, 4(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a1, a1, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 @@ -5327,19 +5327,19 @@ define i1 @memcmp_eq_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV32-NEXT: slli a2, a2, 8 ; CHECK-ALIGNED-RV32-NEXT: slli a3, a3, 16 ; CHECK-ALIGNED-RV32-NEXT: slli a4, a4, 24 -; CHECK-ALIGNED-RV32-NEXT: or a1, a2, a1 -; CHECK-ALIGNED-RV32-NEXT: or a3, a4, a3 +; CHECK-ALIGNED-RV32-NEXT: add a1, a2, a1 +; CHECK-ALIGNED-RV32-NEXT: add a3, a4, a3 ; CHECK-ALIGNED-RV32-NEXT: lbu a2, 1(a0) ; CHECK-ALIGNED-RV32-NEXT: lbu a4, 0(a0) ; CHECK-ALIGNED-RV32-NEXT: lbu a5, 2(a0) ; CHECK-ALIGNED-RV32-NEXT: lbu a0, 3(a0) ; CHECK-ALIGNED-RV32-NEXT: slli a2, a2, 8 -; CHECK-ALIGNED-RV32-NEXT: or a2, a2, a4 +; CHECK-ALIGNED-RV32-NEXT: add a2, a2, a4 ; CHECK-ALIGNED-RV32-NEXT: slli a5, a5, 16 ; CHECK-ALIGNED-RV32-NEXT: slli a0, a0, 24 -; CHECK-ALIGNED-RV32-NEXT: or a0, a0, a5 -; CHECK-ALIGNED-RV32-NEXT: or a1, a3, a1 -; CHECK-ALIGNED-RV32-NEXT: or a0, a0, a2 +; CHECK-ALIGNED-RV32-NEXT: add a0, a0, a5 +; CHECK-ALIGNED-RV32-NEXT: add a1, a3, a1 +; CHECK-ALIGNED-RV32-NEXT: add a0, a0, a2 ; CHECK-ALIGNED-RV32-NEXT: xor a0, a0, a1 ; CHECK-ALIGNED-RV32-NEXT: seqz a0, a0 ; CHECK-ALIGNED-RV32-NEXT: ret @@ -5353,19 +5353,19 @@ define i1 @memcmp_eq_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-NEXT: slli a2, a2, 8 ; CHECK-ALIGNED-RV64-NEXT: slli a3, a3, 16 ; CHECK-ALIGNED-RV64-NEXT: slli a4, a4, 24 -; CHECK-ALIGNED-RV64-NEXT: or a1, a2, a1 -; CHECK-ALIGNED-RV64-NEXT: or a3, a4, a3 +; CHECK-ALIGNED-RV64-NEXT: add a1, a2, a1 +; CHECK-ALIGNED-RV64-NEXT: add a3, a4, a3 ; CHECK-ALIGNED-RV64-NEXT: lbu a2, 1(a0) ; CHECK-ALIGNED-RV64-NEXT: lbu a4, 0(a0) ; CHECK-ALIGNED-RV64-NEXT: lbu a5, 2(a0) ; CHECK-ALIGNED-RV64-NEXT: lb a0, 3(a0) ; CHECK-ALIGNED-RV64-NEXT: slli a2, a2, 8 -; CHECK-ALIGNED-RV64-NEXT: or a2, a2, a4 +; CHECK-ALIGNED-RV64-NEXT: add a2, a2, a4 ; CHECK-ALIGNED-RV64-NEXT: slli a5, a5, 16 ; CHECK-ALIGNED-RV64-NEXT: slli a0, a0, 24 -; CHECK-ALIGNED-RV64-NEXT: or a0, a0, a5 -; CHECK-ALIGNED-RV64-NEXT: or a1, a3, a1 -; CHECK-ALIGNED-RV64-NEXT: or a0, a0, a2 +; CHECK-ALIGNED-RV64-NEXT: add a0, a0, a5 +; CHECK-ALIGNED-RV64-NEXT: add a1, a3, a1 +; CHECK-ALIGNED-RV64-NEXT: add a0, a0, a2 ; CHECK-ALIGNED-RV64-NEXT: xor a0, a0, a1 ; CHECK-ALIGNED-RV64-NEXT: seqz a0, a0 ; CHECK-ALIGNED-RV64-NEXT: ret @@ -5379,19 +5379,19 @@ define i1 @memcmp_eq_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV32-ZBB-NEXT: slli a2, a2, 8 ; CHECK-ALIGNED-RV32-ZBB-NEXT: slli a3, a3, 16 ; CHECK-ALIGNED-RV32-ZBB-NEXT: slli a4, a4, 24 -; CHECK-ALIGNED-RV32-ZBB-NEXT: or a1, a2, a1 -; CHECK-ALIGNED-RV32-ZBB-NEXT: or a3, a4, a3 +; CHECK-ALIGNED-RV32-ZBB-NEXT: add a1, a2, a1 +; CHECK-ALIGNED-RV32-ZBB-NEXT: add a3, a4, a3 ; CHECK-ALIGNED-RV32-ZBB-NEXT: lbu a2, 1(a0) ; CHECK-ALIGNED-RV32-ZBB-NEXT: lbu a4, 0(a0) ; CHECK-ALIGNED-RV32-ZBB-NEXT: lbu a5, 2(a0) ; CHECK-ALIGNED-RV32-ZBB-NEXT: lbu a0, 3(a0) ; CHECK-ALIGNED-RV32-ZBB-NEXT: slli a2, a2, 8 -; CHECK-ALIGNED-RV32-ZBB-NEXT: or a2, a2, a4 +; CHECK-ALIGNED-RV32-ZBB-NEXT: add a2, a2, a4 ; CHECK-ALIGNED-RV32-ZBB-NEXT: slli a5, a5, 16 ; CHECK-ALIGNED-RV32-ZBB-NEXT: slli a0, a0, 24 -; CHECK-ALIGNED-RV32-ZBB-NEXT: or a0, a0, a5 -; CHECK-ALIGNED-RV32-ZBB-NEXT: or a1, a3, a1 -; CHECK-ALIGNED-RV32-ZBB-NEXT: or a0, a0, a2 +; CHECK-ALIGNED-RV32-ZBB-NEXT: add a0, a0, a5 +; CHECK-ALIGNED-RV32-ZBB-NEXT: add a1, a3, a1 +; CHECK-ALIGNED-RV32-ZBB-NEXT: add a0, a0, a2 ; CHECK-ALIGNED-RV32-ZBB-NEXT: xor a0, a0, a1 ; CHECK-ALIGNED-RV32-ZBB-NEXT: seqz a0, a0 ; CHECK-ALIGNED-RV32-ZBB-NEXT: ret @@ -5405,19 +5405,19 @@ define i1 @memcmp_eq_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-ZBB-NEXT: slli a2, a2, 8 ; CHECK-ALIGNED-RV64-ZBB-NEXT: slli a3, a3, 16 ; CHECK-ALIGNED-RV64-ZBB-NEXT: slli a4, a4, 24 -; CHECK-ALIGNED-RV64-ZBB-NEXT: or a1, a2, a1 -; CHECK-ALIGNED-RV64-ZBB-NEXT: or a3, a4, a3 +; CHECK-ALIGNED-RV64-ZBB-NEXT: add a1, a2, a1 +; CHECK-ALIGNED-RV64-ZBB-NEXT: add a3, a4, a3 ; CHECK-ALIGNED-RV64-ZBB-NEXT: lbu a2, 1(a0) ; CHECK-ALIGNED-RV64-ZBB-NEXT: lbu a4, 0(a0) ; CHECK-ALIGNED-RV64-ZBB-NEXT: lbu a5, 2(a0) ; CHECK-ALIGNED-RV64-ZBB-NEXT: lb a0, 3(a0) ; CHECK-ALIGNED-RV64-ZBB-NEXT: slli a2, a2, 8 -; CHECK-ALIGNED-RV64-ZBB-NEXT: or a2, a2, a4 +; CHECK-ALIGNED-RV64-ZBB-NEXT: add a2, a2, a4 ; CHECK-ALIGNED-RV64-ZBB-NEXT: slli a5, a5, 16 ; CHECK-ALIGNED-RV64-ZBB-NEXT: slli a0, a0, 24 -; CHECK-ALIGNED-RV64-ZBB-NEXT: or a0, a0, a5 -; CHECK-ALIGNED-RV64-ZBB-NEXT: or a1, a3, a1 -; CHECK-ALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-ALIGNED-RV64-ZBB-NEXT: add a0, a0, a5 +; CHECK-ALIGNED-RV64-ZBB-NEXT: add a1, a3, a1 +; CHECK-ALIGNED-RV64-ZBB-NEXT: add a0, a0, a2 ; CHECK-ALIGNED-RV64-ZBB-NEXT: xor a0, a0, a1 ; CHECK-ALIGNED-RV64-ZBB-NEXT: seqz a0, a0 ; CHECK-ALIGNED-RV64-ZBB-NEXT: ret @@ -5456,12 +5456,12 @@ define i1 @memcmp_eq_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-ZBKB-NEXT: packh a5, a5, a6 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: slli a4, a4, 16 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: slli a1, a1, 24 -; CHECK-ALIGNED-RV64-ZBKB-NEXT: or a1, a1, a4 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: add a1, a1, a4 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: slli a3, a3, 16 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: slli a0, a0, 24 -; CHECK-ALIGNED-RV64-ZBKB-NEXT: or a0, a0, a3 -; CHECK-ALIGNED-RV64-ZBKB-NEXT: or a1, a1, a2 -; CHECK-ALIGNED-RV64-ZBKB-NEXT: or a0, a0, a5 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: add a0, a0, a3 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: add a1, a1, a2 +; CHECK-ALIGNED-RV64-ZBKB-NEXT: add a0, a0, a5 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: xor a0, a0, a1 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: seqz a0, a0 ; CHECK-ALIGNED-RV64-ZBKB-NEXT: ret @@ -5475,19 +5475,19 @@ define i1 @memcmp_eq_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV32-V-NEXT: slli a2, a2, 8 ; CHECK-ALIGNED-RV32-V-NEXT: slli a3, a3, 16 ; CHECK-ALIGNED-RV32-V-NEXT: slli a4, a4, 24 -; CHECK-ALIGNED-RV32-V-NEXT: or a1, a2, a1 -; CHECK-ALIGNED-RV32-V-NEXT: or a3, a4, a3 +; CHECK-ALIGNED-RV32-V-NEXT: add a1, a2, a1 +; CHECK-ALIGNED-RV32-V-NEXT: add a3, a4, a3 ; CHECK-ALIGNED-RV32-V-NEXT: lbu a2, 1(a0) ; CHECK-ALIGNED-RV32-V-NEXT: lbu a4, 0(a0) ; CHECK-ALIGNED-RV32-V-NEXT: lbu a5, 2(a0) ; CHECK-ALIGNED-RV32-V-NEXT: lbu a0, 3(a0) ; CHECK-ALIGNED-RV32-V-NEXT: slli a2, a2, 8 -; CHECK-ALIGNED-RV32-V-NEXT: or a2, a2, a4 +; CHECK-ALIGNED-RV32-V-NEXT: add a2, a2, a4 ; CHECK-ALIGNED-RV32-V-NEXT: slli a5, a5, 16 ; CHECK-ALIGNED-RV32-V-NEXT: slli a0, a0, 24 -; CHECK-ALIGNED-RV32-V-NEXT: or a0, a0, a5 -; CHECK-ALIGNED-RV32-V-NEXT: or a1, a3, a1 -; CHECK-ALIGNED-RV32-V-NEXT: or a0, a0, a2 +; CHECK-ALIGNED-RV32-V-NEXT: add a0, a0, a5 +; CHECK-ALIGNED-RV32-V-NEXT: add a1, a3, a1 +; CHECK-ALIGNED-RV32-V-NEXT: add a0, a0, a2 ; CHECK-ALIGNED-RV32-V-NEXT: xor a0, a0, a1 ; CHECK-ALIGNED-RV32-V-NEXT: seqz a0, a0 ; CHECK-ALIGNED-RV32-V-NEXT: ret @@ -5501,19 +5501,19 @@ define i1 @memcmp_eq_zero(ptr %s1, ptr %s2) nounwind optsize { ; CHECK-ALIGNED-RV64-V-NEXT: slli a2, a2, 8 ; CHECK-ALIGNED-RV64-V-NEXT: slli a3, a3, 16 ; CHECK-ALIGNED-RV64-V-NEXT: slli a4, a4, 24 -; CHECK-ALIGNED-RV64-V-NEXT: or a1, a2, a1 -; CHECK-ALIGNED-RV64-V-NEXT: or a3, a4, a3 +; CHECK-ALIGNED-RV64-V-NEXT: add a1, a2, a1 +; CHECK-ALIGNED-RV64-V-NEXT: add a3, a4, a3 ; CHECK-ALIGNED-RV64-V-NEXT: lbu a2, 1(a0) ; CHECK-ALIGNED-RV64-V-NEXT: lbu a4, 0(a0) ; CHECK-ALIGNED-RV64-V-NEXT: lbu a5, 2(a0) ; CHECK-ALIGNED-RV64-V-NEXT: lb a0, 3(a0) ; CHECK-ALIGNED-RV64-V-NEXT: slli a2, a2, 8 -; CHECK-ALIGNED-RV64-V-NEXT: or a2, a2, a4 +; CHECK-ALIGNED-RV64-V-NEXT: add a2, a2, a4 ; CHECK-ALIGNED-RV64-V-NEXT: slli a5, a5, 16 ; CHECK-ALIGNED-RV64-V-NEXT: slli a0, a0, 24 -; CHECK-ALIGNED-RV64-V-NEXT: or a0, a0, a5 -; CHECK-ALIGNED-RV64-V-NEXT: or a1, a3, a1 -; CHECK-ALIGNED-RV64-V-NEXT: or a0, a0, a2 +; CHECK-ALIGNED-RV64-V-NEXT: add a0, a0, a5 +; CHECK-ALIGNED-RV64-V-NEXT: add a1, a3, a1 +; CHECK-ALIGNED-RV64-V-NEXT: add a0, a0, a2 ; CHECK-ALIGNED-RV64-V-NEXT: xor a0, a0, a1 ; CHECK-ALIGNED-RV64-V-NEXT: seqz a0, a0 ; CHECK-ALIGNED-RV64-V-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/memcmp.ll b/llvm/test/CodeGen/RISCV/memcmp.ll index c737edb9acce9..cbf0cee32655a 100644 --- a/llvm/test/CodeGen/RISCV/memcmp.ll +++ b/llvm/test/CodeGen/RISCV/memcmp.ll @@ -3994,9 +3994,9 @@ define i32 @memcmp_size_3(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lbu a3, 2(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: lhu a1, 0(a1) ; CHECK-UNALIGNED-RV32-ZBB-NEXT: slli a2, a2, 16 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: add a0, a0, a2 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: slli a3, a3, 16 -; CHECK-UNALIGNED-RV32-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV32-ZBB-NEXT: add a1, a1, a3 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV32-ZBB-NEXT: sltu a2, a0, a1 @@ -4011,9 +4011,9 @@ define i32 @memcmp_size_3(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a3, 2(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 16 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 16 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a1, a1, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: srli a0, a0, 32 @@ -4045,9 +4045,9 @@ define i32 @memcmp_size_3(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lbu a3, 2(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: lhu a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: slli a2, a2, 16 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: add a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: slli a3, a3, 16 -; CHECK-UNALIGNED-RV64-ZBKB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBKB-NEXT: add a1, a1, a3 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBKB-NEXT: srli a0, a0, 32 @@ -4380,9 +4380,9 @@ define i32 @memcmp_size_5(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lbu a3, 4(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a1, a1, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 @@ -4579,9 +4579,9 @@ define i32 @memcmp_size_6(ptr %s1, ptr %s2) nounwind { ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lhu a3, 4(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: lwu a1, 0(a1) ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a2, a2, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a0, a0, a2 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a0, a0, a2 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: slli a3, a3, 32 -; CHECK-UNALIGNED-RV64-ZBB-NEXT: or a1, a1, a3 +; CHECK-UNALIGNED-RV64-ZBB-NEXT: add a1, a1, a3 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a0, a0 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: rev8 a1, a1 ; CHECK-UNALIGNED-RV64-ZBB-NEXT: sltu a2, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/memset-inline.ll b/llvm/test/CodeGen/RISCV/memset-inline.ll index 40915241543ee..7f1215ec0a0c5 100644 --- a/llvm/test/CodeGen/RISCV/memset-inline.ll +++ b/llvm/test/CodeGen/RISCV/memset-inline.ll @@ -45,7 +45,7 @@ define void @memset_2(ptr %a, i8 %value) nounwind { ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: zext.b a2, a1 ; RV32-FAST-NEXT: slli a1, a1, 8 -; RV32-FAST-NEXT: or a1, a1, a2 +; RV32-FAST-NEXT: add a1, a1, a2 ; RV32-FAST-NEXT: sh a1, 0(a0) ; RV32-FAST-NEXT: ret ; @@ -53,7 +53,7 @@ define void @memset_2(ptr %a, i8 %value) nounwind { ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: zext.b a2, a1 ; RV64-FAST-NEXT: slli a1, a1, 8 -; RV64-FAST-NEXT: or a1, a1, a2 +; RV64-FAST-NEXT: add a1, a1, a2 ; RV64-FAST-NEXT: sh a1, 0(a0) ; RV64-FAST-NEXT: ret tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 2, i1 0) @@ -511,7 +511,7 @@ define void @aligned_memset_2(ptr align 2 %a, i8 %value) nounwind { ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: zext.b a2, a1 ; RV32-BOTH-NEXT: slli a1, a1, 8 -; RV32-BOTH-NEXT: or a1, a1, a2 +; RV32-BOTH-NEXT: add a1, a1, a2 ; RV32-BOTH-NEXT: sh a1, 0(a0) ; RV32-BOTH-NEXT: ret ; @@ -519,7 +519,7 @@ define void @aligned_memset_2(ptr align 2 %a, i8 %value) nounwind { ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: zext.b a2, a1 ; RV64-BOTH-NEXT: slli a1, a1, 8 -; RV64-BOTH-NEXT: or a1, a1, a2 +; RV64-BOTH-NEXT: add a1, a1, a2 ; RV64-BOTH-NEXT: sh a1, 0(a0) ; RV64-BOTH-NEXT: ret tail call void @llvm.memset.inline.p0.i64(ptr align 2 %a, i8 %value, i64 2, i1 0) diff --git a/llvm/test/CodeGen/RISCV/mul-expand.ll b/llvm/test/CodeGen/RISCV/mul-expand.ll index a75a7355fa407..aabf3284e4bb8 100644 --- a/llvm/test/CodeGen/RISCV/mul-expand.ll +++ b/llvm/test/CodeGen/RISCV/mul-expand.ll @@ -335,7 +335,7 @@ define i64 @muli64_0x0fffffff(i64 %a) nounwind { ; RV32I-NEXT: srli a3, a0, 4 ; RV32I-NEXT: slli a4, a1, 28 ; RV32I-NEXT: sltu a5, a2, a0 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sub a1, a3, a1 ; RV32I-NEXT: sub a1, a1, a5 ; RV32I-NEXT: sub a0, a2, a0 @@ -502,7 +502,7 @@ define i64 @muli64_0x1000(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: srli a2, a0, 20 ; RV32I-NEXT: slli a1, a1, 12 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 12 ; RV32I-NEXT: ret ; @@ -537,7 +537,7 @@ define i64 @muli64_0x101(i64 %a) nounwind { ; RV32I-NEXT: srli a3, a0, 24 ; RV32I-NEXT: slli a4, a1, 8 ; RV32I-NEXT: add a0, a2, a0 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sltu a2, a0, a2 ; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: add a1, a1, a2 @@ -575,7 +575,7 @@ define i64 @muli64_0xfff(i64 %a) nounwind { ; RV32I-NEXT: srli a3, a0, 20 ; RV32I-NEXT: slli a4, a1, 12 ; RV32I-NEXT: sltu a5, a2, a0 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sub a1, a3, a1 ; RV32I-NEXT: sub a1, a1, a5 ; RV32I-NEXT: sub a0, a2, a0 @@ -613,7 +613,7 @@ define i64 @muli64_0x7fffffff(i64 %a) nounwind { ; RV32I-NEXT: srli a3, a0, 1 ; RV32I-NEXT: slli a4, a1, 31 ; RV32I-NEXT: sltu a5, a2, a0 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sub a1, a3, a1 ; RV32I-NEXT: sub a1, a1, a5 ; RV32I-NEXT: sub a0, a2, a0 diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll index 4c9a98cabb15f..65052a4d1eff3 100644 --- a/llvm/test/CodeGen/RISCV/mul.ll +++ b/llvm/test/CodeGen/RISCV/mul.ll @@ -167,7 +167,7 @@ define i64 @mul64_constant(i64 %a) nounwind { ; RV32I-NEXT: srli a3, a0, 30 ; RV32I-NEXT: slli a4, a1, 2 ; RV32I-NEXT: add a0, a2, a0 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sltu a2, a0, a2 ; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: add a1, a1, a2 @@ -252,10 +252,10 @@ define i32 @mulhs_positive_constant(i32 %a) nounwind { ; RV32I-NEXT: slli a2, a0, 2 ; RV32I-NEXT: srli a3, a0, 30 ; RV32I-NEXT: add a0, a2, a0 +; RV32I-NEXT: add a3, a3, a1 +; RV32I-NEXT: slli a1, a1, 2 ; RV32I-NEXT: sltu a0, a0, a2 -; RV32I-NEXT: slli a2, a1, 2 -; RV32I-NEXT: or a2, a2, a3 -; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; @@ -295,13 +295,13 @@ define i32 @mulhs_negative_constant(i32 %a) nounwind { ; RV32I-NEXT: srli a3, a0, 30 ; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: slli a4, a1, 2 +; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: sltu a2, a0, a2 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a1, a4, a1 ; RV32I-NEXT: snez a0, a0 -; RV32I-NEXT: add a1, a3, a1 -; RV32I-NEXT: add a0, a2, a0 -; RV32I-NEXT: add a0, a1, a0 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: neg a0, a0 +; RV32I-NEXT: sub a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32IM-LABEL: mulhs_negative_constant: @@ -879,7 +879,7 @@ define i64 @muli64_p65(i64 %a) nounwind { ; RV32I-NEXT: srli a3, a0, 26 ; RV32I-NEXT: slli a4, a1, 6 ; RV32I-NEXT: add a0, a2, a0 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sltu a2, a0, a2 ; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: add a1, a1, a2 @@ -918,7 +918,7 @@ define i64 @muli64_p63(i64 %a) nounwind { ; RV32I-NEXT: srli a3, a0, 26 ; RV32I-NEXT: slli a4, a1, 6 ; RV32I-NEXT: sltu a5, a2, a0 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sub a1, a3, a1 ; RV32I-NEXT: sub a1, a1, a5 ; RV32I-NEXT: sub a0, a2, a0 @@ -1101,7 +1101,7 @@ define i64 @muli64_m63(i64 %a) nounwind { ; RV32I-NEXT: srli a3, a0, 26 ; RV32I-NEXT: slli a4, a1, 6 ; RV32I-NEXT: sltu a5, a0, a2 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sub a1, a1, a3 ; RV32I-NEXT: sub a1, a1, a5 ; RV32I-NEXT: sub a0, a0, a2 @@ -1141,7 +1141,7 @@ define i64 @muli64_m65(i64 %a) nounwind { ; RV32I-NEXT: srli a3, a0, 26 ; RV32I-NEXT: slli a4, a1, 6 ; RV32I-NEXT: add a0, a2, a0 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sltu a2, a0, a2 ; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: snez a3, a0 @@ -1380,10 +1380,10 @@ define i64 @muli64_p4352(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: srli a2, a0, 24 ; RV32I-NEXT: slli a3, a1, 8 -; RV32I-NEXT: or a2, a3, a2 +; RV32I-NEXT: add a2, a3, a2 ; RV32I-NEXT: srli a3, a0, 20 ; RV32I-NEXT: slli a1, a1, 12 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: slli a3, a0, 8 ; RV32I-NEXT: slli a4, a0, 12 ; RV32I-NEXT: add a0, a4, a3 @@ -1428,10 +1428,10 @@ define i64 @muli64_p3840(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: srli a2, a0, 24 ; RV32I-NEXT: slli a3, a1, 8 -; RV32I-NEXT: or a2, a3, a2 +; RV32I-NEXT: add a2, a3, a2 ; RV32I-NEXT: srli a3, a0, 20 ; RV32I-NEXT: slli a1, a1, 12 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: slli a3, a0, 8 ; RV32I-NEXT: slli a0, a0, 12 ; RV32I-NEXT: sub a1, a1, a2 @@ -1518,10 +1518,10 @@ define i64 @muli64_m3840(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: srli a2, a0, 20 ; RV32I-NEXT: slli a3, a1, 12 -; RV32I-NEXT: or a2, a3, a2 +; RV32I-NEXT: add a2, a3, a2 ; RV32I-NEXT: srli a3, a0, 24 ; RV32I-NEXT: slli a1, a1, 8 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: slli a3, a0, 12 ; RV32I-NEXT: slli a0, a0, 8 ; RV32I-NEXT: sub a1, a1, a2 @@ -1570,25 +1570,25 @@ define i128 @muli128_m3840(i128 %a) nounwind { ; RV32I-NEXT: srli a7, a3, 24 ; RV32I-NEXT: slli t0, a2, 8 ; RV32I-NEXT: srli t1, a2, 20 -; RV32I-NEXT: or a1, a6, a1 +; RV32I-NEXT: add a1, a6, a1 ; RV32I-NEXT: slli a6, a4, 12 ; RV32I-NEXT: srli t2, a2, 24 ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a2, t0, a7 +; RV32I-NEXT: add a2, t0, a7 ; RV32I-NEXT: srli a7, a5, 20 -; RV32I-NEXT: or a6, a6, t1 +; RV32I-NEXT: add a6, a6, t1 ; RV32I-NEXT: slli t0, a3, 12 -; RV32I-NEXT: or t1, a4, t2 -; RV32I-NEXT: srli t2, a5, 24 +; RV32I-NEXT: add t2, a4, t2 +; RV32I-NEXT: srli t1, a5, 24 ; RV32I-NEXT: slli t3, a3, 8 -; RV32I-NEXT: or a3, t0, a7 +; RV32I-NEXT: add a3, t0, a7 ; RV32I-NEXT: slli a4, a5, 12 ; RV32I-NEXT: slli a5, a5, 8 -; RV32I-NEXT: or t0, t3, t2 -; RV32I-NEXT: sltu t2, a2, a1 -; RV32I-NEXT: sub a6, t1, a6 +; RV32I-NEXT: add t0, t3, t1 +; RV32I-NEXT: sltu t1, a2, a1 +; RV32I-NEXT: sub a6, t2, a6 ; RV32I-NEXT: sltu a7, a5, a4 -; RV32I-NEXT: sub a6, a6, t2 +; RV32I-NEXT: sub a6, a6, t1 ; RV32I-NEXT: mv t1, a7 ; RV32I-NEXT: beq t0, a3, .LBB43_2 ; RV32I-NEXT: # %bb.1: @@ -1665,10 +1665,10 @@ define i128 @muli128_m3840(i128 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: srli a2, a0, 52 ; RV64I-NEXT: slli a3, a1, 12 -; RV64I-NEXT: or a2, a3, a2 +; RV64I-NEXT: add a2, a3, a2 ; RV64I-NEXT: srli a3, a0, 56 ; RV64I-NEXT: slli a1, a1, 8 -; RV64I-NEXT: or a1, a1, a3 +; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: slli a3, a0, 12 ; RV64I-NEXT: slli a0, a0, 8 ; RV64I-NEXT: sub a1, a1, a2 @@ -1699,10 +1699,10 @@ define i128 @muli128_m63(i128 %a) nounwind { ; RV32I-NEXT: lw a2, 8(a1) ; RV32I-NEXT: lw a1, 12(a1) ; RV32I-NEXT: slli a6, a3, 6 -; RV32I-NEXT: srli a5, a3, 26 -; RV32I-NEXT: slli t0, a4, 6 +; RV32I-NEXT: srli t0, a3, 26 +; RV32I-NEXT: slli a5, a4, 6 ; RV32I-NEXT: sltu a7, a3, a6 -; RV32I-NEXT: or t0, t0, a5 +; RV32I-NEXT: add t0, a5, t0 ; RV32I-NEXT: mv a5, a7 ; RV32I-NEXT: beq a4, t0, .LBB44_2 ; RV32I-NEXT: # %bb.1: @@ -1714,16 +1714,16 @@ define i128 @muli128_m63(i128 %a) nounwind { ; RV32I-NEXT: slli t4, a1, 6 ; RV32I-NEXT: sub a4, a4, t0 ; RV32I-NEXT: sub a3, a3, a6 -; RV32I-NEXT: or a6, t2, t1 -; RV32I-NEXT: or t0, t4, t3 +; RV32I-NEXT: add t1, t2, t1 +; RV32I-NEXT: add t3, t4, t3 ; RV32I-NEXT: sub a4, a4, a7 -; RV32I-NEXT: sub a7, a2, a6 -; RV32I-NEXT: sltu a2, a2, a6 -; RV32I-NEXT: sub a1, a1, t0 -; RV32I-NEXT: sltu a6, a7, a5 +; RV32I-NEXT: sub a6, a2, t1 +; RV32I-NEXT: sltu a2, a2, t1 +; RV32I-NEXT: sub a1, a1, t3 +; RV32I-NEXT: sltu a7, a6, a5 ; RV32I-NEXT: sub a1, a1, a2 -; RV32I-NEXT: sub a2, a7, a5 -; RV32I-NEXT: sub a1, a1, a6 +; RV32I-NEXT: sub a2, a6, a5 +; RV32I-NEXT: sub a1, a1, a7 ; RV32I-NEXT: sw a3, 0(a0) ; RV32I-NEXT: sw a4, 4(a0) ; RV32I-NEXT: sw a2, 8(a0) @@ -1795,7 +1795,7 @@ define i128 @muli128_m63(i128 %a) nounwind { ; RV64I-NEXT: srli a3, a0, 58 ; RV64I-NEXT: slli a4, a1, 6 ; RV64I-NEXT: sltu a5, a0, a2 -; RV64I-NEXT: or a3, a4, a3 +; RV64I-NEXT: add a3, a4, a3 ; RV64I-NEXT: sub a1, a1, a3 ; RV64I-NEXT: sub a1, a1, a5 ; RV64I-NEXT: sub a0, a0, a2 diff --git a/llvm/test/CodeGen/RISCV/or-is-add.ll b/llvm/test/CodeGen/RISCV/or-is-add.ll index ab20312d2c4f6..21d2c408177b5 100644 --- a/llvm/test/CodeGen/RISCV/or-is-add.ll +++ b/llvm/test/CodeGen/RISCV/or-is-add.ll @@ -59,7 +59,7 @@ define i64 @test4(i64 %x) { ; RV32-NEXT: srli a2, a0, 28 ; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: slli a0, a0, 4 -; RV32-NEXT: or a1, a1, a2 +; RV32-NEXT: add a1, a1, a2 ; RV32-NEXT: addi a0, a0, 13 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/pr95284.ll b/llvm/test/CodeGen/RISCV/pr95284.ll index 82600d8d3df51..461d6d7a2b37b 100644 --- a/llvm/test/CodeGen/RISCV/pr95284.ll +++ b/llvm/test/CodeGen/RISCV/pr95284.ll @@ -10,7 +10,7 @@ define signext i64 @PR95284(i32 signext %0) { ; RV32I-NEXT: seqz a0, a0 ; RV32I-NEXT: slli a2, a0, 31 ; RV32I-NEXT: srli a1, a1, 1 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: addi a1, a1, 1 ; RV32I-NEXT: seqz a2, a1 ; RV32I-NEXT: sub a2, a2, a0 diff --git a/llvm/test/CodeGen/RISCV/rv32xandesperf.ll b/llvm/test/CodeGen/RISCV/rv32xandesperf.ll index 4a0cddb618a09..783f56282fa58 100644 --- a/llvm/test/CodeGen/RISCV/rv32xandesperf.ll +++ b/llvm/test/CodeGen/RISCV/rv32xandesperf.ll @@ -202,7 +202,7 @@ define i64 @bfoz_from_lshr_and_i64(i64 %x) { ; CHECK-NEXT: andi a1, a1, 15 ; CHECK-NEXT: srli a0, a0, 24 ; CHECK-NEXT: slli a1, a1, 8 -; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: ret %masked = and i64 %x, 68702699520 diff --git a/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll index 1360a29a3e10f..219f4b4f73225 100644 --- a/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32xtheadbb.ll @@ -589,11 +589,11 @@ define i32 @bswap_i32(i32 %a) nounwind { ; RV32I-NEXT: addi a2, a2, -256 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a2, a0, a2 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: slli a2, a2, 8 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, a2 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32XTHEADBB-NOB-LABEL: bswap_i32: @@ -620,20 +620,20 @@ define i64 @bswap_i64(i64 %a) { ; RV32I-NEXT: srli a5, a0, 8 ; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: and a2, a2, a3 -; RV32I-NEXT: or a2, a2, a4 +; RV32I-NEXT: add a2, a2, a4 ; RV32I-NEXT: srli a4, a0, 24 ; RV32I-NEXT: and a5, a5, a3 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: slli a5, a1, 24 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: slli a1, a1, 8 -; RV32I-NEXT: or a1, a5, a1 +; RV32I-NEXT: add a1, a5, a1 ; RV32I-NEXT: and a3, a0, a3 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a0, a3 -; RV32I-NEXT: or a0, a1, a2 -; RV32I-NEXT: or a1, a3, a4 +; RV32I-NEXT: add a3, a0, a3 +; RV32I-NEXT: add a0, a1, a2 +; RV32I-NEXT: add a1, a3, a4 ; RV32I-NEXT: ret ; ; RV32XTHEADBB-NOB-LABEL: bswap_i64: diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll index 1a6c87465d026..198944ae73be1 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll @@ -23,7 +23,7 @@ define i32 @orcb_knownbits(i32 %a) nounwind { ; RV32ZBB-NEXT: lui a1, 4080 ; RV32ZBB-NEXT: orc.b a0, a0 ; RV32ZBB-NEXT: addi a1, a1, 255 -; RV32ZBB-NEXT: or a0, a0, a1 +; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: ret %tmp = and i32 %a, 4278190080 ; 0xFF000000 %tmp2 = or i32 %tmp, 8388609 ; 0x800001 diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll index 7ab3d7c694568..57d7100fe5643 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll @@ -114,7 +114,7 @@ define i64 @xnor_i64(i64 %a, i64 %b) nounwind { define i32 @disjoint_or_xnor_i32(i32 %a, i32 %b) nounwind { ; RV32I-LABEL: disjoint_or_xnor_i32: ; RV32I: # %bb.0: -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: ret ; @@ -130,8 +130,8 @@ define i32 @disjoint_or_xnor_i32(i32 %a, i32 %b) nounwind { define i64 @disjoint_or_xnor_i64(i64 %a, i64 %b) nounwind { ; RV32I-LABEL: disjoint_or_xnor_i64: ; RV32I: # %bb.0: -; RV32I-NEXT: or a1, a1, a3 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a1, a1, a3 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a1, a1 ; RV32I-NEXT: ret @@ -151,7 +151,7 @@ define i32 @disjoint_or_xnor_knownbits_i32(i32 %x, i32 %y, i32 %z) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 126 ; RV32I-NEXT: andi a1, a1, -127 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: ret ; @@ -173,7 +173,7 @@ define i64 @disjoint_or_xnor_knownbits_i64(i64 %x, i64 %y, i64 %z) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 126 ; RV32I-NEXT: andi a1, a2, -127 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: not a1, a3 ; RV32I-NEXT: ret @@ -353,7 +353,7 @@ define i32 @rori_i32_fshl(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: slli a0, a0, 31 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32ZBB-ZBKB-LABEL: rori_i32_fshl: @@ -369,7 +369,7 @@ define i32 @rori_i32_fshr(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: slli a1, a0, 1 ; RV32I-NEXT: srli a0, a0, 31 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32ZBB-ZBKB-LABEL: rori_i32_fshr: @@ -387,8 +387,8 @@ define i64 @rori_i64(i64 %a) nounwind { ; CHECK-NEXT: slli a3, a1, 31 ; CHECK-NEXT: srli a1, a1, 1 ; CHECK-NEXT: slli a4, a0, 31 -; CHECK-NEXT: or a0, a3, a2 -; CHECK-NEXT: or a1, a4, a1 +; CHECK-NEXT: add a0, a3, a2 +; CHECK-NEXT: add a1, a4, a1 ; CHECK-NEXT: ret %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 63) ret i64 %1 @@ -401,8 +401,8 @@ define i64 @rori_i64_fshr(i64 %a) nounwind { ; CHECK-NEXT: slli a3, a0, 1 ; CHECK-NEXT: srli a4, a0, 31 ; CHECK-NEXT: slli a1, a1, 1 -; CHECK-NEXT: or a0, a3, a2 -; CHECK-NEXT: or a1, a1, a4 +; CHECK-NEXT: add a0, a3, a2 +; CHECK-NEXT: add a1, a1, a4 ; CHECK-NEXT: ret %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63) ret i64 %1 diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll index eb8b769b6d083..6448972a71d90 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll @@ -1314,11 +1314,11 @@ define i32 @bswap_i32(i32 %a) nounwind { ; RV32I-NEXT: addi a2, a2, -256 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a2, a0, a2 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: slli a2, a2, 8 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, a2 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: bswap_i32: @@ -1340,20 +1340,20 @@ define i64 @bswap_i64(i64 %a) { ; RV32I-NEXT: srli a5, a0, 8 ; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: and a2, a2, a3 -; RV32I-NEXT: or a2, a2, a4 +; RV32I-NEXT: add a2, a2, a4 ; RV32I-NEXT: srli a4, a0, 24 ; RV32I-NEXT: and a5, a5, a3 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: slli a5, a1, 24 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: slli a1, a1, 8 -; RV32I-NEXT: or a1, a5, a1 +; RV32I-NEXT: add a1, a5, a1 ; RV32I-NEXT: and a3, a0, a3 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a0, a3 -; RV32I-NEXT: or a0, a1, a2 -; RV32I-NEXT: or a1, a3, a4 +; RV32I-NEXT: add a3, a0, a3 +; RV32I-NEXT: add a0, a1, a2 +; RV32I-NEXT: add a1, a3, a4 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: bswap_i64: @@ -1417,7 +1417,7 @@ define i64 @orc_b_i64(i64 %a) { ; CHECK-NEXT: srli a3, a0, 24 ; CHECK-NEXT: slli a4, a1, 8 ; CHECK-NEXT: sltu a5, a2, a0 -; CHECK-NEXT: or a3, a4, a3 +; CHECK-NEXT: add a3, a4, a3 ; CHECK-NEXT: sub a1, a3, a1 ; CHECK-NEXT: sub a1, a1, a5 ; CHECK-NEXT: sub a0, a2, a0 diff --git a/llvm/test/CodeGen/RISCV/rv32zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbkb.ll index 42d326e359d9f..2b711db61dbae 100644 --- a/llvm/test/CodeGen/RISCV/rv32zbkb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbkb.ll @@ -10,7 +10,7 @@ define i32 @pack_i32(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: slli a1, a1, 16 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV32ZBKB-LABEL: pack_i32: @@ -27,7 +27,7 @@ define i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind { ; RV32I-LABEL: pack_i32_2: ; RV32I: # %bb.0: ; RV32I-NEXT: slli a1, a1, 16 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV32ZBKB-LABEL: pack_i32_2: @@ -45,8 +45,8 @@ define i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 %2) { ; RV32I-LABEL: pack_i32_3: ; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 16 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: add a1, a1, a2 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32ZBKB-LABEL: pack_i32_3: @@ -111,7 +111,7 @@ define i32 @packh_i32(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: zext.b a0, a0 ; RV32I-NEXT: slli a1, a1, 24 ; RV32I-NEXT: srli a1, a1, 16 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV32ZBKB-LABEL: packh_i32: @@ -131,7 +131,7 @@ define i32 @packh_i32_2(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: zext.b a0, a0 ; RV32I-NEXT: zext.b a1, a1 ; RV32I-NEXT: slli a1, a1, 8 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV32ZBKB-LABEL: packh_i32_2: @@ -151,7 +151,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: zext.b a0, a0 ; RV32I-NEXT: slli a2, a2, 24 ; RV32I-NEXT: srli a2, a2, 16 -; RV32I-NEXT: or a0, a2, a0 +; RV32I-NEXT: add a0, a2, a0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: ret ; @@ -173,7 +173,7 @@ define i64 @packh_i64_2(i64 %a, i64 %b) nounwind { ; RV32I-NEXT: zext.b a0, a0 ; RV32I-NEXT: zext.b a1, a2 ; RV32I-NEXT: slli a1, a1, 8 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: ret ; @@ -194,7 +194,7 @@ define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind { ; RV32I-LABEL: packh_i16: ; RV32I: # %bb.0: ; RV32I-NEXT: slli a1, a1, 8 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV32ZBKB-LABEL: packh_i16: @@ -214,7 +214,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) { ; RV32I: # %bb.0: ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: slli a0, a0, 8 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: ret @@ -237,7 +237,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) { ; RV32I: # %bb.0: ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: slli a0, a0, 8 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: sh a0, 0(a3) ; RV32I-NEXT: ret ; @@ -326,9 +326,9 @@ define i32 @pack_lo_packh_hi_packh(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ; RV32I-NEXT: slli a1, a1, 8 ; RV32I-NEXT: slli a2, a2, 16 ; RV32I-NEXT: slli a3, a3, 24 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: or a2, a2, a3 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: add a2, a2, a3 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: ret ; ; RV32ZBKB-LABEL: pack_lo_packh_hi_packh: @@ -359,9 +359,9 @@ define i32 @pack_lo_packh_hi_packh_2(i8 %0, i8 %1, i8 %2, i8 %3) nounwind { ; RV32I-NEXT: slli a3, a3, 24 ; RV32I-NEXT: slli a1, a1, 8 ; RV32I-NEXT: slli a2, a2, 16 -; RV32I-NEXT: or a0, a0, a1 -; RV32I-NEXT: or a2, a2, a3 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a1 +; RV32I-NEXT: add a2, a2, a3 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: ret ; ; RV32ZBKB-LABEL: pack_lo_packh_hi_packh_2: @@ -388,8 +388,8 @@ define i32 @pack_lo_zext_hi_packh(i16 zeroext %0, i8 zeroext %1, i8 zeroext %2) ; RV32I: # %bb.0: ; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a2, a2, 24 -; RV32I-NEXT: or a1, a2, a1 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV32ZBKB-LABEL: pack_lo_zext_hi_packh: @@ -414,7 +414,7 @@ define i32 @pack_lo_noext_hi_packh(i32 %a, i8 zeroext %1, i8 zeroext %2) nounwin ; RV32I: # %bb.0: ; RV32I-NEXT: slli a1, a1, 16 ; RV32I-NEXT: slli a2, a2, 24 -; RV32I-NEXT: or a1, a2, a1 +; RV32I-NEXT: add a1, a2, a1 ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; @@ -440,8 +440,8 @@ define i32 @pack_lo_noext_hi_packh_nozeroext(i32 %a, i8 %1, i8 %2) nounwind { ; RV32I-NEXT: zext.b a1, a1 ; RV32I-NEXT: slli a2, a2, 24 ; RV32I-NEXT: slli a1, a1, 16 -; RV32I-NEXT: or a0, a2, a0 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: ret ; ; RV32ZBKB-LABEL: pack_lo_noext_hi_packh_nozeroext: diff --git a/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll b/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll index 16f4119ef20b4..bccf37650dfc7 100644 --- a/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll +++ b/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll @@ -23,7 +23,7 @@ define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind { ; CHECK-NEXT: slli a0, a0, 32 ; CHECK-NEXT: slli s2, s2, 32 ; CHECK-NEXT: srli a1, s2, 32 -; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadba.ll b/llvm/test/CodeGen/RISCV/rv64xtheadba.ll index d20fb66dbbeea..fcc22a7ebefea 100644 --- a/llvm/test/CodeGen/RISCV/rv64xtheadba.ll +++ b/llvm/test/CodeGen/RISCV/rv64xtheadba.ll @@ -115,7 +115,7 @@ define i64 @disjointormul6(i64 %a, i64 %b) { ; RV64I-NEXT: slli a2, a0, 1 ; RV64I-NEXT: slli a0, a0, 3 ; RV64I-NEXT: sub a0, a0, a2 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64XTHEADBA-LABEL: disjointormul6: @@ -1052,7 +1052,7 @@ define i64 @add4104_2(i64 %a) { ; RV64I: # %bb.0: ; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: addi a1, a1, 8 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64XTHEADBA-LABEL: add4104_2: diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll index 24853ebafefcc..b4e3c43f2cdc2 100644 --- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll @@ -1035,11 +1035,11 @@ define signext i32 @bswap_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addi a2, a2, -256 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a2, a0, a2 -; RV64I-NEXT: or a1, a1, a3 +; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: slli a2, a2, 8 ; RV64I-NEXT: slliw a0, a0, 24 -; RV64I-NEXT: or a0, a0, a2 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64XTHEADBB-LABEL: bswap_i32: @@ -1060,11 +1060,11 @@ define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind { ; RV64I-NEXT: addi a3, a3, -256 ; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a3, a0, a3 -; RV64I-NEXT: or a2, a2, a4 +; RV64I-NEXT: add a2, a2, a4 ; RV64I-NEXT: slli a3, a3, 8 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, a3 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a3 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: ret ; @@ -1090,24 +1090,24 @@ define i64 @bswap_i64(i64 %a) { ; RV64I-NEXT: lui a5, 4080 ; RV64I-NEXT: addi a2, a2, -256 ; RV64I-NEXT: and a1, a1, a2 -; RV64I-NEXT: or a1, a1, a3 +; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: srli a3, a0, 8 ; RV64I-NEXT: and a4, a4, a5 ; RV64I-NEXT: srliw a3, a3, 24 ; RV64I-NEXT: slli a3, a3, 24 -; RV64I-NEXT: or a3, a3, a4 +; RV64I-NEXT: add a3, a3, a4 ; RV64I-NEXT: srliw a4, a0, 24 ; RV64I-NEXT: and a5, a0, a5 ; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a4, a4, 32 ; RV64I-NEXT: slli a5, a5, 24 -; RV64I-NEXT: or a4, a5, a4 +; RV64I-NEXT: add a4, a5, a4 ; RV64I-NEXT: slli a2, a2, 40 -; RV64I-NEXT: or a1, a3, a1 -; RV64I-NEXT: or a0, a0, a2 -; RV64I-NEXT: or a0, a0, a4 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a1, a3, a1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a4 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64XTHEADBB-NOB-LABEL: bswap_i64: diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll index b46f7cc440b7a..3c741972752cb 100644 --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -283,7 +283,7 @@ define i64 @sh1adduw_3(i64 %0, i64 %1) { ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 31 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh1adduw_3: @@ -355,7 +355,7 @@ define i64 @sh2adduw_3(i64 %0, i64 %1) { ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 30 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh2adduw_3: @@ -431,7 +431,7 @@ define i64 @sh3adduw_3(i64 %0, i64 %1) { ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 29 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: sh3adduw_3: @@ -524,7 +524,7 @@ define i64 @disjointormul6(i64 %a, i64 %b) { ; RV64I-NEXT: slli a2, a0, 1 ; RV64I-NEXT: slli a0, a0, 3 ; RV64I-NEXT: sub a0, a0, a2 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: disjointormul6: @@ -2084,7 +2084,7 @@ define i64 @add4104_2(i64 %a) { ; RV64I: # %bb.0: ; RV64I-NEXT: lui a1, 1 ; RV64I-NEXT: addi a1, a1, 8 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: add4104_2: @@ -3106,7 +3106,7 @@ define i64 @pack_i64(i64 %a, i64 %b) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: pack_i64: @@ -3132,7 +3132,7 @@ define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: pack_i64_2: @@ -3158,7 +3158,7 @@ define i64 @pack_i64_disjoint(i64 %a, i64 %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: pack_i64_disjoint: @@ -3180,7 +3180,7 @@ define i64 @pack_i64_disjoint_2(i32 signext %a, i64 %b) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: pack_i64_disjoint_2: @@ -3941,7 +3941,7 @@ define i64 @bext_mul132(i32 %1, i32 %2) { ; RV64I-NEXT: andi a0, a0, 1 ; RV64I-NEXT: slli a1, a0, 2 ; RV64I-NEXT: slli a0, a0, 7 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBANOZBB-LABEL: bext_mul132: @@ -4556,7 +4556,7 @@ define i64 @append_32ones(i64 %x) { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: li a1, -1 ; RV64I-NEXT: srli a1, a1, 32 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBA-LABEL: append_32ones: diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll index 500d51be80a66..2fa0cef67db3c 100644 --- a/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll @@ -32,8 +32,7 @@ define signext i32 @orcb32_knownbits(i32 signext %a) nounwind { ; RV64ZBB-NEXT: lui a1, 4080 ; RV64ZBB-NEXT: orc.b a0, a0 ; RV64ZBB-NEXT: addi a1, a1, 255 -; RV64ZBB-NEXT: or a0, a0, a1 -; RV64ZBB-NEXT: sext.w a0, a0 +; RV64ZBB-NEXT: addw a0, a0, a1 ; RV64ZBB-NEXT: ret %tmp = and i32 %a, 4278190080 ; 0xFF000000 %tmp2 = or i32 %tmp, 8388609 ; 0x800001 @@ -67,7 +66,7 @@ define i64 @orcb64_knownbits(i64 %a) nounwind { ; RV64ZBB-NEXT: slli a1, a2, 40 ; RV64ZBB-NEXT: orc.b a0, a0 ; RV64ZBB-NEXT: add a1, a2, a1 -; RV64ZBB-NEXT: or a0, a0, a1 +; RV64ZBB-NEXT: add a0, a0, a1 ; RV64ZBB-NEXT: ret %tmp = and i64 %a, 1099494850560 ; 0x000000ffff000000 %tmp2 = or i64 %tmp, 4611721202800525320 ; 0x4000200000100008 diff --git a/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll index f2c95f855e178..c8bdb4dbda7bc 100644 --- a/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbb-zbkb.ll @@ -116,7 +116,7 @@ define signext i32 @disjoint_or_xnor_i32(i32 signext %a, i32 signext %b) nounwin define i64 @disjoint_or_xnor_i64(i64 %a, i64 %b) nounwind { ; RV64I-LABEL: disjoint_or_xnor_i64: ; RV64I: # %bb.0: -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: ret ; @@ -134,7 +134,7 @@ define signext i32 @disjoint_or_xnor_knownbits_i32(i32 signext %x, i32 signext % ; RV64I: # %bb.0: ; RV64I-NEXT: andi a0, a0, 126 ; RV64I-NEXT: andi a1, a1, -127 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: ret ; @@ -156,7 +156,7 @@ define i64 @disjoint_or_xnor_knownbits_i64(i64 %x, i64 %y, i64 %z) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: andi a0, a0, 126 ; RV64I-NEXT: andi a1, a1, -127 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: ret ; @@ -380,7 +380,7 @@ define signext i32 @rori_i32_fshl(i32 signext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: srliw a1, a0, 1 ; RV64I-NEXT: slliw a0, a0, 31 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBB-ZBKB-LABEL: rori_i32_fshl: @@ -397,7 +397,7 @@ define void @rori_i32_fshl_nosext(i32 signext %a, ptr %x) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: srliw a2, a0, 1 ; RV64I-NEXT: slli a0, a0, 31 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: ret ; @@ -416,7 +416,7 @@ define signext i32 @rori_i32_fshr(i32 signext %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: slliw a1, a0, 1 ; RV64I-NEXT: srliw a0, a0, 31 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBB-ZBKB-LABEL: rori_i32_fshr: @@ -433,7 +433,7 @@ define void @rori_i32_fshr_nosext(i32 signext %a, ptr %x) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: slli a2, a0, 1 ; RV64I-NEXT: srliw a0, a0, 31 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: ret ; @@ -455,7 +455,7 @@ define signext i32 @not_rori_i32(i32 signext %x, i32 signext %y) nounwind { ; CHECK: # %bb.0: ; CHECK-NEXT: slliw a0, a0, 31 ; CHECK-NEXT: srliw a1, a1, 1 -; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: ret %a = shl i32 %x, 31 %b = lshr i32 %y, 1 @@ -491,7 +491,7 @@ define i64 @rori_i64_fshl(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: srli a1, a0, 1 ; RV64I-NEXT: slli a0, a0, 63 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBB-ZBKB-LABEL: rori_i64_fshl: @@ -507,7 +507,7 @@ define i64 @rori_i64_fshr(i64 %a) nounwind { ; RV64I: # %bb.0: ; RV64I-NEXT: slli a1, a0, 1 ; RV64I-NEXT: srli a0, a0, 63 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBB-ZBKB-LABEL: rori_i64_fshr: diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll index d133f9d1db389..3b8102b7d3cd5 100644 --- a/llvm/test/CodeGen/RISCV/rv64zbb.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll @@ -1456,11 +1456,11 @@ define signext i32 @bswap_i32(i32 signext %a) nounwind { ; RV64I-NEXT: addi a2, a2, -256 ; RV64I-NEXT: and a1, a1, a2 ; RV64I-NEXT: and a2, a0, a2 -; RV64I-NEXT: or a1, a1, a3 +; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: slli a2, a2, 8 ; RV64I-NEXT: slliw a0, a0, 24 -; RV64I-NEXT: or a0, a0, a2 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: bswap_i32: @@ -1482,11 +1482,11 @@ define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind { ; RV64I-NEXT: addi a3, a3, -256 ; RV64I-NEXT: and a2, a2, a3 ; RV64I-NEXT: and a3, a0, a3 -; RV64I-NEXT: or a2, a2, a4 +; RV64I-NEXT: add a2, a2, a4 ; RV64I-NEXT: slli a3, a3, 8 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, a3 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a3 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: ret ; @@ -1513,24 +1513,24 @@ define i64 @bswap_i64(i64 %a) { ; RV64I-NEXT: lui a5, 4080 ; RV64I-NEXT: addi a2, a2, -256 ; RV64I-NEXT: and a1, a1, a2 -; RV64I-NEXT: or a1, a1, a3 +; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: srli a3, a0, 8 ; RV64I-NEXT: and a4, a4, a5 ; RV64I-NEXT: srliw a3, a3, 24 ; RV64I-NEXT: slli a3, a3, 24 -; RV64I-NEXT: or a3, a3, a4 +; RV64I-NEXT: add a3, a3, a4 ; RV64I-NEXT: srliw a4, a0, 24 ; RV64I-NEXT: and a5, a0, a5 ; RV64I-NEXT: and a2, a0, a2 ; RV64I-NEXT: slli a0, a0, 56 ; RV64I-NEXT: slli a4, a4, 32 ; RV64I-NEXT: slli a5, a5, 24 -; RV64I-NEXT: or a4, a5, a4 +; RV64I-NEXT: add a4, a5, a4 ; RV64I-NEXT: slli a2, a2, 40 -; RV64I-NEXT: or a1, a3, a1 -; RV64I-NEXT: or a0, a0, a2 -; RV64I-NEXT: or a0, a0, a4 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a1, a3, a1 +; RV64I-NEXT: add a0, a0, a2 +; RV64I-NEXT: add a0, a0, a4 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBB-LABEL: bswap_i64: diff --git a/llvm/test/CodeGen/RISCV/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbkb.ll index 4537d187a9857..cb94e81962bb9 100644 --- a/llvm/test/CodeGen/RISCV/rv64zbkb.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbkb.ll @@ -10,7 +10,7 @@ define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind { ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 ; RV64I-NEXT: slliw a1, a1, 16 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: pack_i32: @@ -27,7 +27,7 @@ define signext i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind { ; RV64I-LABEL: pack_i32_2: ; RV64I: # %bb.0: ; RV64I-NEXT: slliw a1, a1, 16 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: pack_i32_2: @@ -46,7 +46,7 @@ define signext i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 signext %2) { ; RV64I-LABEL: pack_i32_3: ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 16 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: addw a0, a0, a2 ; RV64I-NEXT: ret ; @@ -69,7 +69,7 @@ define i64 @pack_i64(i64 %a, i64 %b) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: pack_i64: @@ -88,7 +88,7 @@ define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind { ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: pack_i64_2: @@ -108,7 +108,7 @@ define i64 @pack_i64_3(ptr %0, ptr %1) { ; RV64I-NEXT: lw a0, 0(a0) ; RV64I-NEXT: lwu a1, 0(a1) ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: pack_i64_3: @@ -132,7 +132,7 @@ define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind { ; RV64I-NEXT: zext.b a0, a0 ; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: srli a1, a1, 48 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: packh_i32: @@ -152,7 +152,7 @@ define i32 @packh_i32_2(i32 %a, i32 %b) nounwind { ; RV64I-NEXT: zext.b a0, a0 ; RV64I-NEXT: zext.b a1, a1 ; RV64I-NEXT: slli a1, a1, 8 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: packh_i32_2: @@ -172,7 +172,7 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind { ; RV64I-NEXT: zext.b a0, a0 ; RV64I-NEXT: slli a1, a1, 56 ; RV64I-NEXT: srli a1, a1, 48 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: packh_i64: @@ -192,7 +192,7 @@ define i64 @packh_i64_2(i64 %a, i64 %b) nounwind { ; RV64I-NEXT: zext.b a0, a0 ; RV64I-NEXT: zext.b a1, a1 ; RV64I-NEXT: slli a1, a1, 8 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: packh_i64_2: @@ -210,7 +210,7 @@ define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind { ; RV64I-LABEL: packh_i16: ; RV64I: # %bb.0: ; RV64I-NEXT: slli a1, a1, 8 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: packh_i16: @@ -229,7 +229,7 @@ define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) { ; RV64I: # %bb.0: ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: slli a0, a0, 8 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: slli a0, a0, 48 ; RV64I-NEXT: srli a0, a0, 48 ; RV64I-NEXT: ret @@ -252,7 +252,7 @@ define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) { ; RV64I: # %bb.0: ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: slli a0, a0, 8 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: sh a0, 0(a3) ; RV64I-NEXT: ret ; @@ -278,7 +278,7 @@ define i64 @pack_i64_allWUsers(i32 signext %0, i32 signext %1, i32 signext %2) { ; RV64I-NEXT: slli a2, a2, 32 ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: srli a2, a2, 32 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: pack_i64_allWUsers: @@ -299,7 +299,7 @@ define signext i32 @pack_i32_allWUsers(i16 zeroext %0, i16 zeroext %1, i16 zeroe ; RV64I: # %bb.0: ; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: slliw a0, a0, 16 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: pack_i32_allWUsers: @@ -399,9 +399,9 @@ define void @pack_lo_packh_hi_packh(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: slli a2, a2, 16 ; RV64I-NEXT: slli a3, a3, 24 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: or a2, a2, a3 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a2, a2, a3 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: sw a0, 0(a4) ; RV64I-NEXT: ret ; @@ -432,9 +432,9 @@ define void @pack_lo_packh_hi_packh_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext % ; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: slli a2, a2, 16 ; RV64I-NEXT: slli a3, a3, 24 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: or a2, a2, a3 -; RV64I-NEXT: or a0, a2, a0 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a2, a2, a3 +; RV64I-NEXT: add a0, a2, a0 ; RV64I-NEXT: sw a0, 0(a4) ; RV64I-NEXT: ret ; @@ -468,9 +468,9 @@ define void @pack_lo_packh_hi_packh_3(i8 %0, i8 %1, i8 %2, i8 %3, ptr %p) nounwi ; RV64I-NEXT: slli a3, a3, 24 ; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: slli a2, a2, 16 -; RV64I-NEXT: or a0, a3, a0 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: or a0, a2, a0 +; RV64I-NEXT: add a0, a3, a0 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a0, a2, a0 ; RV64I-NEXT: sw a0, 0(a4) ; RV64I-NEXT: ret ; @@ -501,9 +501,9 @@ define i32 @pack_lo_packh_hi_packh_4(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2 ; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: slli a2, a2, 16 ; RV64I-NEXT: slliw a3, a3, 24 -; RV64I-NEXT: or a0, a0, a1 -; RV64I-NEXT: or a2, a2, a3 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: add a0, a0, a1 +; RV64I-NEXT: add a2, a2, a3 +; RV64I-NEXT: add a0, a0, a2 ; RV64I-NEXT: ret ; ; RV64ZBKB-LABEL: pack_lo_packh_hi_packh_4: @@ -530,8 +530,8 @@ define void @pack_lo_zext_hi_packh(i16 zeroext %0, i8 zeroext %1, i8 zeroext %2, ; RV64I: # %bb.0: ; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a2, a2, 24 -; RV64I-NEXT: or a1, a2, a1 -; RV64I-NEXT: or a0, a1, a0 +; RV64I-NEXT: add a1, a2, a1 +; RV64I-NEXT: add a0, a1, a0 ; RV64I-NEXT: sw a0, 0(a3) ; RV64I-NEXT: ret ; @@ -559,7 +559,7 @@ define void @pack_lo_noext_hi_packh(i32 %a, i8 zeroext %1, i8 zeroext %2, ptr %p ; RV64I: # %bb.0: ; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a2, a2, 24 -; RV64I-NEXT: or a1, a2, a1 +; RV64I-NEXT: add a1, a2, a1 ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: sw a0, 0(a3) ; RV64I-NEXT: ret @@ -588,8 +588,8 @@ define void @pack_i32_lo_noext_hi_packh_nozeroext(i32 %a, i8 %1, i8 %2, ptr %p) ; RV64I-NEXT: zext.b a1, a1 ; RV64I-NEXT: slli a2, a2, 24 ; RV64I-NEXT: slli a1, a1, 16 -; RV64I-NEXT: or a0, a2, a0 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a1, a2, a1 +; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: sw a0, 0(a3) ; RV64I-NEXT: ret ; @@ -618,7 +618,7 @@ define i64 @pack_i64_lo_noext_hi_packh_nozeroext(i64 %a, i8 %1, i8 %2, ptr %p) n ; RV64I-NEXT: zext.b a2, a2 ; RV64I-NEXT: slli a1, a1, 16 ; RV64I-NEXT: slli a2, a2, 24 -; RV64I-NEXT: or a1, a2, a1 +; RV64I-NEXT: add a1, a2, a1 ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll index c97545691180e..607d0f4a1fe64 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll @@ -601,8 +601,8 @@ define <2 x i32> @build_vec_of_trunc_op(i64 %a, i64 %b) { ; RV32-NEXT: srli a0, a0, 1 ; RV32-NEXT: slli a3, a3, 31 ; RV32-NEXT: srli a2, a2, 1 -; RV32-NEXT: or a0, a0, a1 -; RV32-NEXT: or a2, a2, a3 +; RV32-NEXT: add a0, a0, a1 +; RV32-NEXT: add a2, a2, a3 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vslide1down.vx v8, v8, a2 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll index dba5d26c216fa..a246ebbef0af5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll @@ -918,7 +918,7 @@ define i32 @extractelt_v32i32_idx(ptr %x, i32 zeroext %idx) nounwind { ; RV32M-NEXT: vle32.v v8, (a0) ; RV32M-NEXT: slli a1, a1, 2 ; RV32M-NEXT: mv a0, sp -; RV32M-NEXT: or a1, a0, a1 +; RV32M-NEXT: add a1, a0, a1 ; RV32M-NEXT: vadd.vv v8, v8, v8 ; RV32M-NEXT: vse32.v v8, (a0) ; RV32M-NEXT: lw a0, 0(a1) @@ -968,7 +968,7 @@ define i32 @extractelt_v32i32_idx(ptr %x, i32 zeroext %idx) nounwind { ; RV64M-NEXT: vle32.v v8, (a0) ; RV64M-NEXT: slli a1, a1, 2 ; RV64M-NEXT: mv a0, sp -; RV64M-NEXT: or a1, a0, a1 +; RV64M-NEXT: add a1, a0, a1 ; RV64M-NEXT: vadd.vv v8, v8, v8 ; RV64M-NEXT: vse32.v v8, (a0) ; RV64M-NEXT: lw a0, 0(a1) @@ -991,7 +991,7 @@ define i32 @extractelt_v32i32_idx(ptr %x, i32 zeroext %idx) nounwind { ; VISNI-NEXT: vle32.v v8, (a0) ; VISNI-NEXT: slli a1, a1, 2 ; VISNI-NEXT: mv a0, sp -; VISNI-NEXT: or a1, a0, a1 +; VISNI-NEXT: add a1, a0, a1 ; VISNI-NEXT: vadd.vv v8, v8, v8 ; VISNI-NEXT: vse32.v v8, (a0) ; VISNI-NEXT: lw a0, 0(a1) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll index 9be93d5209121..8edd0a5feb08c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll @@ -131,13 +131,13 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) { ; ZVFH32-NEXT: slli a1, a1, 17 ; ZVFH32-NEXT: srli a1, a1, 17 ; ZVFH32-NEXT: slli a3, a2, 30 -; ZVFH32-NEXT: or a1, a1, a3 +; ZVFH32-NEXT: add a1, a1, a3 ; ZVFH32-NEXT: vmv.x.s a3, v9 ; ZVFH32-NEXT: slli a2, a2, 17 ; ZVFH32-NEXT: slli a3, a3, 17 ; ZVFH32-NEXT: srli a2, a2, 19 ; ZVFH32-NEXT: srli a3, a3, 2 -; ZVFH32-NEXT: or a1, a1, a3 +; ZVFH32-NEXT: add a1, a1, a3 ; ZVFH32-NEXT: sw a1, 0(a0) ; ZVFH32-NEXT: sh a2, 4(a0) ; ZVFH32-NEXT: ret @@ -156,8 +156,8 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) { ; ZVFH64-NEXT: slli a2, a2, 49 ; ZVFH64-NEXT: slli a3, a3, 30 ; ZVFH64-NEXT: srli a2, a2, 34 -; ZVFH64-NEXT: or a1, a1, a3 -; ZVFH64-NEXT: or a1, a1, a2 +; ZVFH64-NEXT: add a1, a1, a3 +; ZVFH64-NEXT: add a1, a1, a2 ; ZVFH64-NEXT: slli a2, a1, 19 ; ZVFH64-NEXT: srli a2, a2, 51 ; ZVFH64-NEXT: sw a1, 0(a0) @@ -175,13 +175,13 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) { ; ZVFHMIN32-NEXT: slli a1, a1, 17 ; ZVFHMIN32-NEXT: srli a1, a1, 17 ; ZVFHMIN32-NEXT: slli a3, a2, 30 -; ZVFHMIN32-NEXT: or a1, a1, a3 +; ZVFHMIN32-NEXT: add a1, a1, a3 ; ZVFHMIN32-NEXT: vmv.x.s a3, v9 ; ZVFHMIN32-NEXT: slli a2, a2, 17 ; ZVFHMIN32-NEXT: slli a3, a3, 17 ; ZVFHMIN32-NEXT: srli a2, a2, 19 ; ZVFHMIN32-NEXT: srli a3, a3, 2 -; ZVFHMIN32-NEXT: or a1, a1, a3 +; ZVFHMIN32-NEXT: add a1, a1, a3 ; ZVFHMIN32-NEXT: sw a1, 0(a0) ; ZVFHMIN32-NEXT: sh a2, 4(a0) ; ZVFHMIN32-NEXT: ret @@ -200,8 +200,8 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) { ; ZVFHMIN64-NEXT: slli a2, a2, 49 ; ZVFHMIN64-NEXT: slli a3, a3, 30 ; ZVFHMIN64-NEXT: srli a2, a2, 34 -; ZVFHMIN64-NEXT: or a1, a1, a3 -; ZVFHMIN64-NEXT: or a1, a1, a2 +; ZVFHMIN64-NEXT: add a1, a1, a3 +; ZVFHMIN64-NEXT: add a1, a1, a2 ; ZVFHMIN64-NEXT: slli a2, a1, 19 ; ZVFHMIN64-NEXT: srli a2, a2, 51 ; ZVFHMIN64-NEXT: sw a1, 0(a0) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll index d9bb007a10f71..eac4c4f9ada72 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -1396,38 +1396,38 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) { ; RV32VB-NEXT: slli a3, a3, 16 ; RV32VB-NEXT: slli a4, a4, 24 ; RV32VB-NEXT: slli a6, a6, 8 -; RV32VB-NEXT: or a1, a1, a2 -; RV32VB-NEXT: or a3, a4, a3 -; RV32VB-NEXT: or a2, a5, a6 -; RV32VB-NEXT: lbu a4, 8(a0) -; RV32VB-NEXT: lbu a5, 9(a0) +; RV32VB-NEXT: add a1, a1, a2 +; RV32VB-NEXT: add a3, a4, a3 +; RV32VB-NEXT: add a5, a5, a6 +; RV32VB-NEXT: lbu a2, 8(a0) +; RV32VB-NEXT: lbu a4, 9(a0) ; RV32VB-NEXT: lbu a6, 10(a0) ; RV32VB-NEXT: lbu t1, 11(a0) ; RV32VB-NEXT: slli a7, a7, 16 ; RV32VB-NEXT: slli t0, t0, 24 -; RV32VB-NEXT: slli a5, a5, 8 +; RV32VB-NEXT: slli a4, a4, 8 ; RV32VB-NEXT: slli a6, a6, 16 ; RV32VB-NEXT: slli t1, t1, 24 -; RV32VB-NEXT: or a7, t0, a7 -; RV32VB-NEXT: or a4, a4, a5 -; RV32VB-NEXT: or a5, t1, a6 -; RV32VB-NEXT: lbu a6, 13(a0) +; RV32VB-NEXT: add a7, t0, a7 +; RV32VB-NEXT: add a2, a2, a4 +; RV32VB-NEXT: add a6, t1, a6 +; RV32VB-NEXT: lbu a4, 13(a0) ; RV32VB-NEXT: lbu t0, 12(a0) ; RV32VB-NEXT: lbu t1, 14(a0) ; RV32VB-NEXT: lbu a0, 15(a0) -; RV32VB-NEXT: slli a6, a6, 8 -; RV32VB-NEXT: or a6, t0, a6 +; RV32VB-NEXT: slli a4, a4, 8 +; RV32VB-NEXT: add a4, t0, a4 ; RV32VB-NEXT: slli t1, t1, 16 ; RV32VB-NEXT: slli a0, a0, 24 -; RV32VB-NEXT: or a0, a0, t1 -; RV32VB-NEXT: or a1, a1, a3 -; RV32VB-NEXT: or a2, a2, a7 -; RV32VB-NEXT: or a4, a4, a5 -; RV32VB-NEXT: or a0, a6, a0 +; RV32VB-NEXT: add a0, a0, t1 +; RV32VB-NEXT: add a1, a1, a3 +; RV32VB-NEXT: add a5, a5, a7 +; RV32VB-NEXT: add a2, a2, a6 +; RV32VB-NEXT: add a0, a4, a0 ; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32VB-NEXT: vmv.v.x v8, a1 +; RV32VB-NEXT: vslide1down.vx v8, v8, a5 ; RV32VB-NEXT: vslide1down.vx v8, v8, a2 -; RV32VB-NEXT: vslide1down.vx v8, v8, a4 ; RV32VB-NEXT: vslide1down.vx v8, v8, a0 ; RV32VB-NEXT: ret ; @@ -1532,9 +1532,9 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) { ; RVA22U64-NEXT: slli a4, a4, 24 ; RVA22U64-NEXT: slli a5, a5, 32 ; RVA22U64-NEXT: slli a1, a1, 40 -; RVA22U64-NEXT: or a6, a6, a2 -; RVA22U64-NEXT: or t2, a4, a3 -; RVA22U64-NEXT: or t1, a1, a5 +; RVA22U64-NEXT: add a6, a6, a2 +; RVA22U64-NEXT: add t2, a4, a3 +; RVA22U64-NEXT: add t1, a1, a5 ; RVA22U64-NEXT: lbu a4, 8(a0) ; RVA22U64-NEXT: lbu a5, 9(a0) ; RVA22U64-NEXT: lbu a2, 10(a0) @@ -1544,27 +1544,27 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) { ; RVA22U64-NEXT: slli a5, a5, 8 ; RVA22U64-NEXT: slli a2, a2, 16 ; RVA22U64-NEXT: slli a1, a1, 24 -; RVA22U64-NEXT: or a7, t0, a7 -; RVA22U64-NEXT: or a4, a4, a5 -; RVA22U64-NEXT: or a1, a1, a2 +; RVA22U64-NEXT: add a7, a7, t0 +; RVA22U64-NEXT: add a4, a4, a5 +; RVA22U64-NEXT: add a1, a1, a2 ; RVA22U64-NEXT: lbu a2, 12(a0) ; RVA22U64-NEXT: lbu a5, 13(a0) ; RVA22U64-NEXT: lbu a3, 14(a0) ; RVA22U64-NEXT: lbu a0, 15(a0) ; RVA22U64-NEXT: slli a2, a2, 32 ; RVA22U64-NEXT: slli a5, a5, 40 -; RVA22U64-NEXT: or a2, a2, a5 +; RVA22U64-NEXT: add a2, a2, a5 ; RVA22U64-NEXT: slli a3, a3, 48 ; RVA22U64-NEXT: slli a0, a0, 56 -; RVA22U64-NEXT: or a0, a0, a3 -; RVA22U64-NEXT: or a3, a6, t2 -; RVA22U64-NEXT: or a5, a7, t1 -; RVA22U64-NEXT: or a1, a1, a4 -; RVA22U64-NEXT: or a0, a0, a2 -; RVA22U64-NEXT: or a3, a3, a5 -; RVA22U64-NEXT: or a0, a0, a1 +; RVA22U64-NEXT: add a0, a0, a3 +; RVA22U64-NEXT: add a6, a6, t2 +; RVA22U64-NEXT: add a7, a7, t1 +; RVA22U64-NEXT: add a1, a1, a4 +; RVA22U64-NEXT: add a0, a0, a2 +; RVA22U64-NEXT: add a6, a6, a7 +; RVA22U64-NEXT: add a0, a0, a1 ; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RVA22U64-NEXT: vmv.v.x v8, a3 +; RVA22U64-NEXT: vmv.v.x v8, a6 ; RVA22U64-NEXT: vslide1down.vx v8, v8, a0 ; RVA22U64-NEXT: ret ; @@ -1771,37 +1771,37 @@ define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) { ; RV32VB-NEXT: slli a3, a3, 16 ; RV32VB-NEXT: slli a4, a4, 24 ; RV32VB-NEXT: slli a7, a7, 8 -; RV32VB-NEXT: or a1, a1, a2 -; RV32VB-NEXT: or a3, a4, a3 -; RV32VB-NEXT: or a2, a6, a7 -; RV32VB-NEXT: lbu a4, 93(a0) -; RV32VB-NEXT: lbu a6, 105(a0) +; RV32VB-NEXT: add a1, a1, a2 +; RV32VB-NEXT: add a3, a4, a3 +; RV32VB-NEXT: add a6, a6, a7 +; RV32VB-NEXT: lbu a2, 93(a0) +; RV32VB-NEXT: lbu a4, 105(a0) ; RV32VB-NEXT: lbu a7, 124(a0) ; RV32VB-NEXT: lbu t2, 144(a0) ; RV32VB-NEXT: slli a5, a5, 16 ; RV32VB-NEXT: slli t0, t0, 24 -; RV32VB-NEXT: slli a4, a4, 8 -; RV32VB-NEXT: or a5, t0, a5 -; RV32VB-NEXT: or a4, t1, a4 +; RV32VB-NEXT: slli a2, a2, 8 +; RV32VB-NEXT: add a5, t0, a5 +; RV32VB-NEXT: add a2, t1, a2 ; RV32VB-NEXT: lbu t0, 161(a0) ; RV32VB-NEXT: lbu t1, 154(a0) ; RV32VB-NEXT: lbu a0, 163(a0) -; RV32VB-NEXT: slli a6, a6, 16 +; RV32VB-NEXT: slli a4, a4, 16 ; RV32VB-NEXT: slli t0, t0, 24 -; RV32VB-NEXT: or a6, t0, a6 +; RV32VB-NEXT: add a4, t0, a4 ; RV32VB-NEXT: slli a0, a0, 8 -; RV32VB-NEXT: or a0, a7, a0 +; RV32VB-NEXT: add a0, a7, a0 ; RV32VB-NEXT: slli t2, t2, 16 ; RV32VB-NEXT: slli t1, t1, 24 -; RV32VB-NEXT: or a7, t1, t2 -; RV32VB-NEXT: or a1, a1, a3 -; RV32VB-NEXT: or a2, a2, a5 -; RV32VB-NEXT: or a3, a4, a6 -; RV32VB-NEXT: or a0, a0, a7 +; RV32VB-NEXT: add t1, t1, t2 +; RV32VB-NEXT: add a1, a1, a3 +; RV32VB-NEXT: add a5, a6, a5 +; RV32VB-NEXT: add a2, a2, a4 +; RV32VB-NEXT: add a0, a0, t1 ; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32VB-NEXT: vmv.v.x v8, a1 +; RV32VB-NEXT: vslide1down.vx v8, v8, a5 ; RV32VB-NEXT: vslide1down.vx v8, v8, a2 -; RV32VB-NEXT: vslide1down.vx v8, v8, a3 ; RV32VB-NEXT: vslide1down.vx v8, v8, a0 ; RV32VB-NEXT: ret ; @@ -1907,38 +1907,38 @@ define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) { ; RVA22U64-NEXT: slli a4, a4, 24 ; RVA22U64-NEXT: slli a5, a5, 32 ; RVA22U64-NEXT: slli a1, a1, 40 -; RVA22U64-NEXT: or a7, a7, a2 -; RVA22U64-NEXT: or t3, a4, a3 -; RVA22U64-NEXT: or t2, a1, a5 +; RVA22U64-NEXT: add a7, a7, a2 +; RVA22U64-NEXT: add t3, a4, a3 +; RVA22U64-NEXT: add t2, a1, a5 ; RVA22U64-NEXT: lbu a4, 93(a0) ; RVA22U64-NEXT: lbu t4, 105(a0) ; RVA22U64-NEXT: lbu a2, 124(a0) -; RVA22U64-NEXT: lbu t5, 144(a0) +; RVA22U64-NEXT: lbu a1, 144(a0) ; RVA22U64-NEXT: slli a6, a6, 48 ; RVA22U64-NEXT: slli t0, t0, 56 ; RVA22U64-NEXT: slli a4, a4, 8 -; RVA22U64-NEXT: or a3, t0, a6 -; RVA22U64-NEXT: or a4, t1, a4 -; RVA22U64-NEXT: lbu a5, 161(a0) -; RVA22U64-NEXT: lbu a1, 154(a0) +; RVA22U64-NEXT: add a6, a6, t0 +; RVA22U64-NEXT: add a4, a4, t1 +; RVA22U64-NEXT: lbu a3, 161(a0) +; RVA22U64-NEXT: lbu a5, 154(a0) ; RVA22U64-NEXT: lbu a0, 163(a0) ; RVA22U64-NEXT: slli t4, t4, 16 -; RVA22U64-NEXT: slli a5, a5, 24 -; RVA22U64-NEXT: or a5, a5, t4 +; RVA22U64-NEXT: slli a3, a3, 24 +; RVA22U64-NEXT: add a3, a3, t4 ; RVA22U64-NEXT: slli a2, a2, 32 ; RVA22U64-NEXT: slli a0, a0, 40 -; RVA22U64-NEXT: or a0, a0, a2 -; RVA22U64-NEXT: slli t5, t5, 48 -; RVA22U64-NEXT: slli a1, a1, 56 -; RVA22U64-NEXT: or a1, a1, t5 -; RVA22U64-NEXT: or a2, a7, t3 -; RVA22U64-NEXT: or a3, a3, t2 -; RVA22U64-NEXT: or a4, a4, a5 -; RVA22U64-NEXT: or a0, a0, a1 -; RVA22U64-NEXT: or a2, a2, a3 -; RVA22U64-NEXT: or a0, a0, a4 +; RVA22U64-NEXT: add a0, a0, a2 +; RVA22U64-NEXT: slli a1, a1, 48 +; RVA22U64-NEXT: slli a5, a5, 56 +; RVA22U64-NEXT: add a1, a1, a5 +; RVA22U64-NEXT: add a7, a7, t3 +; RVA22U64-NEXT: add a6, a6, t2 +; RVA22U64-NEXT: add a3, a3, a4 +; RVA22U64-NEXT: add a0, a0, a1 +; RVA22U64-NEXT: add a6, a6, a7 +; RVA22U64-NEXT: add a0, a0, a3 ; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RVA22U64-NEXT: vmv.v.x v8, a2 +; RVA22U64-NEXT: vmv.v.x v8, a6 ; RVA22U64-NEXT: vslide1down.vx v8, v8, a0 ; RVA22U64-NEXT: ret ; @@ -2116,23 +2116,23 @@ define <16 x i8> @buildvec_v16i8_undef_low_half(ptr %p) { ; RV32VB-NEXT: lbu a3, 105(a0) ; RV32VB-NEXT: lbu a4, 124(a0) ; RV32VB-NEXT: slli a1, a1, 8 -; RV32VB-NEXT: or a1, a2, a1 +; RV32VB-NEXT: add a1, a2, a1 ; RV32VB-NEXT: lbu a2, 161(a0) ; RV32VB-NEXT: lbu a5, 144(a0) ; RV32VB-NEXT: lbu a6, 154(a0) ; RV32VB-NEXT: lbu a0, 163(a0) ; RV32VB-NEXT: slli a3, a3, 16 ; RV32VB-NEXT: slli a2, a2, 24 -; RV32VB-NEXT: or a2, a2, a3 +; RV32VB-NEXT: add a2, a2, a3 ; RV32VB-NEXT: slli a0, a0, 8 -; RV32VB-NEXT: or a0, a4, a0 +; RV32VB-NEXT: add a0, a4, a0 ; RV32VB-NEXT: slli a5, a5, 16 ; RV32VB-NEXT: slli a6, a6, 24 -; RV32VB-NEXT: or a3, a6, a5 +; RV32VB-NEXT: add a5, a6, a5 ; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32VB-NEXT: vmv.v.i v8, 0 -; RV32VB-NEXT: or a1, a1, a2 -; RV32VB-NEXT: or a0, a0, a3 +; RV32VB-NEXT: add a1, a1, a2 +; RV32VB-NEXT: add a0, a0, a5 ; RV32VB-NEXT: vslide1down.vx v8, v8, zero ; RV32VB-NEXT: vslide1down.vx v8, v8, a1 ; RV32VB-NEXT: vslide1down.vx v8, v8, a0 @@ -2191,23 +2191,23 @@ define <16 x i8> @buildvec_v16i8_undef_low_half(ptr %p) { ; RVA22U64-NEXT: lbu a3, 105(a0) ; RVA22U64-NEXT: lbu a4, 124(a0) ; RVA22U64-NEXT: slli a1, a1, 8 -; RVA22U64-NEXT: or a6, a2, a1 +; RVA22U64-NEXT: add a6, a2, a1 ; RVA22U64-NEXT: lbu a2, 161(a0) ; RVA22U64-NEXT: lbu a5, 144(a0) ; RVA22U64-NEXT: lbu a1, 154(a0) ; RVA22U64-NEXT: lbu a0, 163(a0) ; RVA22U64-NEXT: slli a3, a3, 16 ; RVA22U64-NEXT: slli a2, a2, 24 -; RVA22U64-NEXT: or a2, a2, a3 +; RVA22U64-NEXT: add a2, a2, a3 ; RVA22U64-NEXT: slli a4, a4, 32 ; RVA22U64-NEXT: slli a0, a0, 40 -; RVA22U64-NEXT: or a0, a0, a4 +; RVA22U64-NEXT: add a0, a0, a4 ; RVA22U64-NEXT: slli a5, a5, 48 ; RVA22U64-NEXT: slli a1, a1, 56 -; RVA22U64-NEXT: or a1, a1, a5 -; RVA22U64-NEXT: or a2, a6, a2 -; RVA22U64-NEXT: or a0, a0, a1 -; RVA22U64-NEXT: or a0, a0, a2 +; RVA22U64-NEXT: add a1, a1, a5 +; RVA22U64-NEXT: add a2, a2, a6 +; RVA22U64-NEXT: add a0, a0, a1 +; RVA22U64-NEXT: add a0, a0, a2 ; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RVA22U64-NEXT: vmv.v.i v8, 0 ; RVA22U64-NEXT: vslide1down.vx v8, v8, a0 @@ -2317,21 +2317,21 @@ define <16 x i8> @buildvec_v16i8_undef_high_half(ptr %p) { ; RV32VB-NEXT: lbu a3, 22(a0) ; RV32VB-NEXT: lbu a4, 31(a0) ; RV32VB-NEXT: slli a1, a1, 8 -; RV32VB-NEXT: or a1, a2, a1 +; RV32VB-NEXT: add a1, a2, a1 ; RV32VB-NEXT: lbu a2, 44(a0) ; RV32VB-NEXT: lbu a5, 55(a0) ; RV32VB-NEXT: slli a3, a3, 16 ; RV32VB-NEXT: slli a4, a4, 24 -; RV32VB-NEXT: or a3, a4, a3 +; RV32VB-NEXT: add a3, a4, a3 ; RV32VB-NEXT: lbu a4, 623(a0) ; RV32VB-NEXT: lbu a0, 75(a0) ; RV32VB-NEXT: slli a5, a5, 8 -; RV32VB-NEXT: or a2, a2, a5 +; RV32VB-NEXT: add a2, a2, a5 ; RV32VB-NEXT: slli a4, a4, 16 ; RV32VB-NEXT: slli a0, a0, 24 -; RV32VB-NEXT: or a0, a0, a4 -; RV32VB-NEXT: or a1, a1, a3 -; RV32VB-NEXT: or a0, a2, a0 +; RV32VB-NEXT: add a0, a0, a4 +; RV32VB-NEXT: add a1, a1, a3 +; RV32VB-NEXT: add a0, a2, a0 ; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32VB-NEXT: vmv.v.x v8, a1 ; RV32VB-NEXT: vslide1down.vx v8, v8, a0 @@ -2393,23 +2393,23 @@ define <16 x i8> @buildvec_v16i8_undef_high_half(ptr %p) { ; RVA22U64-NEXT: lbu a3, 22(a0) ; RVA22U64-NEXT: lbu a4, 31(a0) ; RVA22U64-NEXT: slli a1, a1, 8 -; RVA22U64-NEXT: or a1, a1, a2 +; RVA22U64-NEXT: add a1, a1, a2 ; RVA22U64-NEXT: lbu a2, 44(a0) ; RVA22U64-NEXT: lbu a5, 55(a0) ; RVA22U64-NEXT: slli a3, a3, 16 ; RVA22U64-NEXT: slli a4, a4, 24 -; RVA22U64-NEXT: or a3, a3, a4 +; RVA22U64-NEXT: add a3, a3, a4 ; RVA22U64-NEXT: lbu a4, 623(a0) ; RVA22U64-NEXT: lbu a0, 75(a0) ; RVA22U64-NEXT: slli a2, a2, 32 ; RVA22U64-NEXT: slli a5, a5, 40 -; RVA22U64-NEXT: or a2, a2, a5 +; RVA22U64-NEXT: add a2, a2, a5 ; RVA22U64-NEXT: slli a4, a4, 48 ; RVA22U64-NEXT: slli a0, a0, 56 -; RVA22U64-NEXT: or a0, a0, a4 -; RVA22U64-NEXT: or a1, a1, a3 -; RVA22U64-NEXT: or a0, a0, a2 -; RVA22U64-NEXT: or a0, a0, a1 +; RVA22U64-NEXT: add a0, a0, a4 +; RVA22U64-NEXT: add a1, a1, a3 +; RVA22U64-NEXT: add a0, a0, a2 +; RVA22U64-NEXT: add a0, a0, a1 ; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RVA22U64-NEXT: vmv.v.x v8, a0 ; RVA22U64-NEXT: vslide1down.vx v8, v8, zero @@ -2528,20 +2528,20 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) { ; RV32VB-NEXT: slli a2, a2, 8 ; RV32VB-NEXT: slli a1, a1, 16 ; RV32VB-NEXT: slli a4, a4, 24 -; RV32VB-NEXT: or a2, a5, a2 -; RV32VB-NEXT: or a1, a4, a1 +; RV32VB-NEXT: add a2, a5, a2 +; RV32VB-NEXT: add a1, a4, a1 ; RV32VB-NEXT: lbu a4, 93(a0) ; RV32VB-NEXT: lbu a5, 82(a0) ; RV32VB-NEXT: lbu a6, 105(a0) ; RV32VB-NEXT: lbu a0, 161(a0) ; RV32VB-NEXT: slli a4, a4, 8 -; RV32VB-NEXT: or a4, a5, a4 +; RV32VB-NEXT: add a4, a5, a4 ; RV32VB-NEXT: slli a6, a6, 16 ; RV32VB-NEXT: slli a0, a0, 24 -; RV32VB-NEXT: or a0, a0, a6 +; RV32VB-NEXT: add a0, a0, a6 ; RV32VB-NEXT: slli a3, a3, 24 -; RV32VB-NEXT: or a1, a2, a1 -; RV32VB-NEXT: or a0, a4, a0 +; RV32VB-NEXT: add a1, a2, a1 +; RV32VB-NEXT: add a0, a4, a0 ; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32VB-NEXT: vmv.v.x v8, a3 ; RV32VB-NEXT: vslide1down.vx v8, v8, a1 @@ -2616,21 +2616,21 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) { ; RVA22U64-NEXT: slli a3, a3, 40 ; RVA22U64-NEXT: slli a1, a1, 48 ; RVA22U64-NEXT: slli a5, a5, 56 -; RVA22U64-NEXT: or a2, a2, a3 -; RVA22U64-NEXT: or a1, a1, a5 +; RVA22U64-NEXT: add a2, a2, a3 +; RVA22U64-NEXT: add a1, a1, a5 ; RVA22U64-NEXT: lbu a3, 93(a0) ; RVA22U64-NEXT: lbu a5, 82(a0) ; RVA22U64-NEXT: lbu a4, 105(a0) ; RVA22U64-NEXT: lbu a0, 161(a0) ; RVA22U64-NEXT: slli a3, a3, 8 -; RVA22U64-NEXT: or a3, a3, a5 +; RVA22U64-NEXT: add a3, a3, a5 ; RVA22U64-NEXT: slli a4, a4, 16 ; RVA22U64-NEXT: slli a0, a0, 24 -; RVA22U64-NEXT: or a0, a0, a4 +; RVA22U64-NEXT: add a0, a0, a4 ; RVA22U64-NEXT: slli a6, a6, 24 -; RVA22U64-NEXT: or a1, a1, a2 +; RVA22U64-NEXT: add a1, a1, a2 ; RVA22U64-NEXT: add.uw a1, a6, a1 -; RVA22U64-NEXT: or a0, a0, a3 +; RVA22U64-NEXT: add a0, a0, a3 ; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RVA22U64-NEXT: vmv.v.x v8, a1 ; RVA22U64-NEXT: vslide1down.vx v8, v8, a0 @@ -2764,23 +2764,23 @@ define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) { ; RV32VB-NEXT: lbu a3, 44(a0) ; RV32VB-NEXT: lbu a4, 55(a0) ; RV32VB-NEXT: slli a1, a1, 8 -; RV32VB-NEXT: or a1, a2, a1 +; RV32VB-NEXT: add a1, a2, a1 ; RV32VB-NEXT: lbu a2, 75(a0) ; RV32VB-NEXT: lbu a5, 82(a0) ; RV32VB-NEXT: lbu a6, 93(a0) ; RV32VB-NEXT: lbu a7, 124(a0) ; RV32VB-NEXT: slli a4, a4, 8 -; RV32VB-NEXT: or a3, a3, a4 +; RV32VB-NEXT: add a3, a3, a4 ; RV32VB-NEXT: lbu a4, 144(a0) ; RV32VB-NEXT: lbu a0, 154(a0) ; RV32VB-NEXT: slli a6, a6, 8 -; RV32VB-NEXT: or a5, a5, a6 +; RV32VB-NEXT: add a5, a5, a6 ; RV32VB-NEXT: slli a4, a4, 16 ; RV32VB-NEXT: slli a0, a0, 24 -; RV32VB-NEXT: or a0, a0, a4 +; RV32VB-NEXT: add a0, a0, a4 ; RV32VB-NEXT: slli a2, a2, 24 -; RV32VB-NEXT: or a2, a3, a2 -; RV32VB-NEXT: or a0, a7, a0 +; RV32VB-NEXT: add a2, a3, a2 +; RV32VB-NEXT: add a0, a7, a0 ; RV32VB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32VB-NEXT: vmv.v.x v8, a1 ; RV32VB-NEXT: vslide1down.vx v8, v8, a2 @@ -2858,29 +2858,29 @@ define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) { ; RVA22U64-NEXT: lbu a3, 44(a0) ; RVA22U64-NEXT: lbu a4, 55(a0) ; RVA22U64-NEXT: slli a1, a1, 8 -; RVA22U64-NEXT: or a6, a2, a1 +; RVA22U64-NEXT: add a6, a2, a1 ; RVA22U64-NEXT: lbu a7, 75(a0) ; RVA22U64-NEXT: lbu a5, 82(a0) ; RVA22U64-NEXT: lbu a1, 93(a0) ; RVA22U64-NEXT: lbu a2, 124(a0) ; RVA22U64-NEXT: slli a3, a3, 32 ; RVA22U64-NEXT: slli a4, a4, 40 -; RVA22U64-NEXT: or a3, a3, a4 +; RVA22U64-NEXT: add a3, a3, a4 ; RVA22U64-NEXT: lbu a4, 144(a0) ; RVA22U64-NEXT: lbu a0, 154(a0) ; RVA22U64-NEXT: slli a1, a1, 8 -; RVA22U64-NEXT: or a1, a1, a5 +; RVA22U64-NEXT: add a1, a1, a5 ; RVA22U64-NEXT: slli a4, a4, 48 ; RVA22U64-NEXT: slli a0, a0, 56 -; RVA22U64-NEXT: or a0, a0, a4 +; RVA22U64-NEXT: add a0, a0, a4 ; RVA22U64-NEXT: slli a7, a7, 56 -; RVA22U64-NEXT: or a3, a7, a3 +; RVA22U64-NEXT: add a3, a3, a7 ; RVA22U64-NEXT: slli a2, a2, 32 -; RVA22U64-NEXT: or a0, a0, a2 -; RVA22U64-NEXT: or a2, a6, a3 -; RVA22U64-NEXT: or a0, a0, a1 +; RVA22U64-NEXT: add a0, a0, a2 +; RVA22U64-NEXT: add a3, a3, a6 +; RVA22U64-NEXT: add a0, a0, a1 ; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; RVA22U64-NEXT: vmv.v.x v8, a2 +; RVA22U64-NEXT: vmv.v.x v8, a3 ; RVA22U64-NEXT: vslide1down.vx v8, v8, a0 ; RVA22U64-NEXT: ret ; @@ -3028,15 +3028,15 @@ define <8 x i8> @buildvec_v8i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 % ; RV32VB-NEXT: slli a5, a5, 8 ; RV32VB-NEXT: slli a2, a2, 16 ; RV32VB-NEXT: slli a1, a1, 8 -; RV32VB-NEXT: or a6, a7, a6 -; RV32VB-NEXT: or a4, a4, a5 -; RV32VB-NEXT: or a2, a3, a2 -; RV32VB-NEXT: or a0, a0, a1 -; RV32VB-NEXT: or a1, a4, a6 -; RV32VB-NEXT: or a0, a0, a2 +; RV32VB-NEXT: add a6, a7, a6 +; RV32VB-NEXT: add a4, a4, a5 +; RV32VB-NEXT: add a2, a3, a2 +; RV32VB-NEXT: add a0, a0, a1 +; RV32VB-NEXT: add a4, a4, a6 +; RV32VB-NEXT: add a0, a0, a2 ; RV32VB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV32VB-NEXT: vmv.v.x v8, a0 -; RV32VB-NEXT: vslide1down.vx v8, v8, a1 +; RV32VB-NEXT: vslide1down.vx v8, v8, a4 ; RV32VB-NEXT: ret ; ; RV32VB-PACK-LABEL: buildvec_v8i8_pack: @@ -3083,13 +3083,13 @@ define <8 x i8> @buildvec_v8i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 % ; RVA22U64-NEXT: slli a2, a2, 16 ; RVA22U64-NEXT: slli a3, a3, 24 ; RVA22U64-NEXT: slli a1, a1, 8 -; RVA22U64-NEXT: or a5, a5, t0 -; RVA22U64-NEXT: or a4, a7, a4 -; RVA22U64-NEXT: or a2, a2, a3 -; RVA22U64-NEXT: or a0, a0, a1 -; RVA22U64-NEXT: or a4, a4, a5 -; RVA22U64-NEXT: or a0, a0, a2 -; RVA22U64-NEXT: or a0, a0, a4 +; RVA22U64-NEXT: add a5, a5, t0 +; RVA22U64-NEXT: add a4, a4, a7 +; RVA22U64-NEXT: add a2, a2, a3 +; RVA22U64-NEXT: add a0, a0, a1 +; RVA22U64-NEXT: add a4, a4, a5 +; RVA22U64-NEXT: add a0, a0, a2 +; RVA22U64-NEXT: add a0, a0, a4 ; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RVA22U64-NEXT: vmv.s.x v8, a0 ; RVA22U64-NEXT: ret @@ -3156,10 +3156,10 @@ define <6 x i8> @buildvec_v6i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 % ; RV32VB-NEXT: slli a2, a2, 16 ; RV32VB-NEXT: slli a1, a1, 8 ; RV32VB-NEXT: slli a5, a5, 8 -; RV32VB-NEXT: or a2, a3, a2 -; RV32VB-NEXT: or a0, a0, a1 -; RV32VB-NEXT: or a0, a0, a2 -; RV32VB-NEXT: or a4, a4, a5 +; RV32VB-NEXT: add a2, a3, a2 +; RV32VB-NEXT: add a0, a0, a1 +; RV32VB-NEXT: add a0, a0, a2 +; RV32VB-NEXT: add a4, a4, a5 ; RV32VB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV32VB-NEXT: vmv.v.x v8, a0 ; RV32VB-NEXT: vslide1down.vx v8, v8, a4 @@ -3203,11 +3203,11 @@ define <6 x i8> @buildvec_v6i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 % ; RVA22U64-NEXT: slli a1, a1, 8 ; RVA22U64-NEXT: slli a4, a4, 32 ; RVA22U64-NEXT: slli a5, a5, 40 -; RVA22U64-NEXT: or a2, a2, a3 -; RVA22U64-NEXT: or a0, a0, a1 -; RVA22U64-NEXT: or a0, a0, a2 -; RVA22U64-NEXT: or a4, a4, a5 -; RVA22U64-NEXT: or a0, a0, a4 +; RVA22U64-NEXT: add a2, a2, a3 +; RVA22U64-NEXT: add a0, a0, a1 +; RVA22U64-NEXT: add a0, a0, a2 +; RVA22U64-NEXT: add a4, a4, a5 +; RVA22U64-NEXT: add a0, a0, a4 ; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RVA22U64-NEXT: vmv.s.x v8, a0 ; RVA22U64-NEXT: ret @@ -3261,8 +3261,8 @@ define <4 x i16> @buildvec_v4i16_pack(i16 %e1, i16 %e2, i16 %e3, i16 %e4) { ; RV32VB-NEXT: zext.h a2, a2 ; RV32VB-NEXT: slli a1, a1, 16 ; RV32VB-NEXT: zext.h a0, a0 -; RV32VB-NEXT: or a2, a2, a3 -; RV32VB-NEXT: or a0, a0, a1 +; RV32VB-NEXT: add a2, a2, a3 +; RV32VB-NEXT: add a0, a0, a1 ; RV32VB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV32VB-NEXT: vmv.v.x v8, a0 ; RV32VB-NEXT: vslide1down.vx v8, v8, a2 @@ -3294,9 +3294,9 @@ define <4 x i16> @buildvec_v4i16_pack(i16 %e1, i16 %e2, i16 %e3, i16 %e4) { ; RVA22U64-NEXT: slli a1, a1, 48 ; RVA22U64-NEXT: srli a2, a2, 16 ; RVA22U64-NEXT: srli a1, a1, 32 -; RVA22U64-NEXT: or a2, a2, a3 -; RVA22U64-NEXT: or a0, a0, a1 -; RVA22U64-NEXT: or a0, a0, a2 +; RVA22U64-NEXT: add a2, a2, a3 +; RVA22U64-NEXT: add a0, a0, a1 +; RVA22U64-NEXT: add a0, a0, a2 ; RVA22U64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RVA22U64-NEXT: vmv.s.x v8, a0 ; RVA22U64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll index 4c35b2506d3e4..818190df1f061 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -14054,42 +14054,42 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) { ; RV32-NEXT: lbu t1, 0(a1) ; RV32-NEXT: lbu a1, 1(a1) ; RV32-NEXT: slli a0, a0, 8 -; RV32-NEXT: or a0, a0, a6 +; RV32-NEXT: add a0, a0, a6 ; RV32-NEXT: lbu a6, 0(a2) ; RV32-NEXT: lbu a2, 1(a2) ; RV32-NEXT: slli a1, a1, 8 -; RV32-NEXT: or a1, a1, t1 +; RV32-NEXT: add a1, a1, t1 ; RV32-NEXT: lbu t1, 0(a3) ; RV32-NEXT: lbu a3, 1(a3) ; RV32-NEXT: slli a2, a2, 8 -; RV32-NEXT: or a2, a2, a6 +; RV32-NEXT: add a2, a2, a6 ; RV32-NEXT: lbu a6, 0(a4) ; RV32-NEXT: lbu a4, 1(a4) ; RV32-NEXT: slli a3, a3, 8 -; RV32-NEXT: or a3, a3, t1 +; RV32-NEXT: add a3, a3, t1 ; RV32-NEXT: lbu t1, 0(a5) ; RV32-NEXT: lbu a5, 1(a5) ; RV32-NEXT: slli a4, a4, 8 -; RV32-NEXT: or a4, a4, a6 +; RV32-NEXT: add a4, a4, a6 ; RV32-NEXT: lbu a6, 0(a7) ; RV32-NEXT: lbu a7, 1(a7) ; RV32-NEXT: slli a5, a5, 8 -; RV32-NEXT: or a5, a5, t1 +; RV32-NEXT: add a5, a5, t1 ; RV32-NEXT: lbu t1, 0(t0) ; RV32-NEXT: lbu t0, 1(t0) ; RV32-NEXT: slli a7, a7, 8 -; RV32-NEXT: or a6, a7, a6 +; RV32-NEXT: add a6, a7, a6 ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV32-NEXT: vmv.v.i v0, 15 ; RV32-NEXT: slli t0, t0, 8 -; RV32-NEXT: or a7, t0, t1 +; RV32-NEXT: add t0, t0, t1 ; RV32-NEXT: vmv.v.x v8, a0 ; RV32-NEXT: vmv.v.x v9, a4 ; RV32-NEXT: vslide1down.vx v8, v8, a1 ; RV32-NEXT: vslide1down.vx v9, v9, a5 ; RV32-NEXT: vslide1down.vx v10, v8, a2 ; RV32-NEXT: vslide1down.vx v8, v9, a6 -; RV32-NEXT: vslide1down.vx v8, v8, a7 +; RV32-NEXT: vslide1down.vx v8, v8, t0 ; RV32-NEXT: vslide1down.vx v9, v10, a3 ; RV32-NEXT: vslidedown.vi v8, v9, 4, v0.t ; RV32-NEXT: ret @@ -14130,42 +14130,42 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) { ; RV64V-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV64V-NEXT: vse64.v v8, (a1) ; RV64V-NEXT: slli a0, a0, 8 -; RV64V-NEXT: or a0, a0, a4 +; RV64V-NEXT: add a0, a0, a4 ; RV64V-NEXT: slli a2, a2, 8 ; RV64V-NEXT: slli a3, a3, 8 -; RV64V-NEXT: or a1, a2, a6 -; RV64V-NEXT: or a2, a3, a7 -; RV64V-NEXT: ld a3, 32(sp) +; RV64V-NEXT: add a2, a2, a6 +; RV64V-NEXT: add a3, a3, a7 +; RV64V-NEXT: ld a1, 32(sp) ; RV64V-NEXT: ld a4, 40(sp) ; RV64V-NEXT: ld a6, 48(sp) ; RV64V-NEXT: ld a7, 56(sp) ; RV64V-NEXT: slli a5, a5, 8 -; RV64V-NEXT: or a5, a5, t0 -; RV64V-NEXT: lbu t0, 0(a3) -; RV64V-NEXT: lbu a3, 1(a3) +; RV64V-NEXT: add a5, a5, t0 +; RV64V-NEXT: lbu t0, 0(a1) +; RV64V-NEXT: lbu a1, 1(a1) ; RV64V-NEXT: vmv.v.x v8, a0 ; RV64V-NEXT: lbu a0, 0(a4) ; RV64V-NEXT: lbu a4, 1(a4) -; RV64V-NEXT: vslide1down.vx v8, v8, a1 -; RV64V-NEXT: lbu a1, 0(a6) -; RV64V-NEXT: lbu a6, 1(a6) ; RV64V-NEXT: vslide1down.vx v8, v8, a2 -; RV64V-NEXT: lbu a2, 0(a7) +; RV64V-NEXT: lbu a2, 0(a6) +; RV64V-NEXT: lbu a6, 1(a6) +; RV64V-NEXT: vslide1down.vx v8, v8, a3 +; RV64V-NEXT: lbu a3, 0(a7) ; RV64V-NEXT: lbu a7, 1(a7) ; RV64V-NEXT: vslide1down.vx v9, v8, a5 -; RV64V-NEXT: slli a3, a3, 8 +; RV64V-NEXT: slli a1, a1, 8 ; RV64V-NEXT: slli a4, a4, 8 ; RV64V-NEXT: slli a6, a6, 8 ; RV64V-NEXT: slli a7, a7, 8 -; RV64V-NEXT: or a3, a3, t0 -; RV64V-NEXT: or a0, a4, a0 -; RV64V-NEXT: or a1, a6, a1 -; RV64V-NEXT: or a2, a7, a2 -; RV64V-NEXT: vmv.v.x v8, a3 +; RV64V-NEXT: add a1, a1, t0 +; RV64V-NEXT: add a0, a4, a0 +; RV64V-NEXT: add a2, a6, a2 +; RV64V-NEXT: add a3, a7, a3 +; RV64V-NEXT: vmv.v.x v8, a1 ; RV64V-NEXT: vslide1down.vx v8, v8, a0 -; RV64V-NEXT: vslide1down.vx v8, v8, a1 -; RV64V-NEXT: vmv.v.i v0, 15 ; RV64V-NEXT: vslide1down.vx v8, v8, a2 +; RV64V-NEXT: vmv.v.i v0, 15 +; RV64V-NEXT: vslide1down.vx v8, v8, a3 ; RV64V-NEXT: vslidedown.vi v8, v9, 4, v0.t ; RV64V-NEXT: addi sp, s0, -128 ; RV64V-NEXT: .cfi_def_cfa sp, 128 @@ -14189,38 +14189,38 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) { ; RV64ZVE32F-NEXT: lbu t0, 13(a0) ; RV64ZVE32F-NEXT: slli a2, a2, 8 ; RV64ZVE32F-NEXT: slli a4, a4, 8 -; RV64ZVE32F-NEXT: or a1, a2, a1 -; RV64ZVE32F-NEXT: or a3, a4, a3 +; RV64ZVE32F-NEXT: add a1, a2, a1 +; RV64ZVE32F-NEXT: add a3, a4, a3 ; RV64ZVE32F-NEXT: lbu a2, 16(a0) ; RV64ZVE32F-NEXT: lbu a4, 17(a0) ; RV64ZVE32F-NEXT: lbu t1, 20(a0) ; RV64ZVE32F-NEXT: lbu t2, 21(a0) ; RV64ZVE32F-NEXT: slli a6, a6, 8 -; RV64ZVE32F-NEXT: or a5, a6, a5 +; RV64ZVE32F-NEXT: add a5, a6, a5 ; RV64ZVE32F-NEXT: slli t0, t0, 8 ; RV64ZVE32F-NEXT: slli a4, a4, 8 ; RV64ZVE32F-NEXT: slli t2, t2, 8 -; RV64ZVE32F-NEXT: or a6, t0, a7 -; RV64ZVE32F-NEXT: or a2, a4, a2 -; RV64ZVE32F-NEXT: or a4, t2, t1 -; RV64ZVE32F-NEXT: lbu a7, 25(a0) -; RV64ZVE32F-NEXT: lbu t0, 24(a0) -; RV64ZVE32F-NEXT: lbu t1, 28(a0) +; RV64ZVE32F-NEXT: add a7, t0, a7 +; RV64ZVE32F-NEXT: add a2, a4, a2 +; RV64ZVE32F-NEXT: add t1, t2, t1 +; RV64ZVE32F-NEXT: lbu a4, 25(a0) +; RV64ZVE32F-NEXT: lbu a6, 24(a0) +; RV64ZVE32F-NEXT: lbu t0, 28(a0) ; RV64ZVE32F-NEXT: lbu a0, 29(a0) -; RV64ZVE32F-NEXT: slli a7, a7, 8 -; RV64ZVE32F-NEXT: or a7, a7, t0 +; RV64ZVE32F-NEXT: slli a4, a4, 8 +; RV64ZVE32F-NEXT: add a4, a4, a6 ; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: slli a0, a0, 8 -; RV64ZVE32F-NEXT: or a0, a0, t1 +; RV64ZVE32F-NEXT: add a0, a0, t0 ; RV64ZVE32F-NEXT: vmv.v.x v8, a2 ; RV64ZVE32F-NEXT: vmv.v.x v9, a1 -; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a4 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, t1 ; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3 -; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7 +; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a5 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0 -; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a6 +; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a7 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll index 74f2cec04f0de..5d37a1e78b143 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll @@ -92,14 +92,14 @@ define void @store_v6i1(ptr %p, <6 x i1> %v) { ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: andi a3, a2, 2 ; CHECK-NEXT: andi a4, a2, 4 -; CHECK-NEXT: or a1, a1, a3 +; CHECK-NEXT: add a1, a1, a3 ; CHECK-NEXT: andi a3, a2, 8 -; CHECK-NEXT: or a3, a4, a3 +; CHECK-NEXT: add a3, a4, a3 ; CHECK-NEXT: andi a4, a2, 16 ; CHECK-NEXT: andi a2, a2, -32 -; CHECK-NEXT: or a1, a1, a3 -; CHECK-NEXT: or a2, a4, a2 -; CHECK-NEXT: or a1, a1, a2 +; CHECK-NEXT: add a1, a1, a3 +; CHECK-NEXT: add a2, a4, a2 +; CHECK-NEXT: add a1, a1, a2 ; CHECK-NEXT: andi a1, a1, 63 ; CHECK-NEXT: sb a1, 0(a0) ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll index dcf1ab08c3c24..42fd7ddb43074 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll @@ -87,7 +87,7 @@ define <2 x i16> @mgather_v2i16_align1(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> % ; RV32-SLOW-NEXT: lbu a2, 1(a1) ; RV32-SLOW-NEXT: lbu a1, 0(a1) ; RV32-SLOW-NEXT: slli a2, a2, 8 -; RV32-SLOW-NEXT: or a1, a2, a1 +; RV32-SLOW-NEXT: add a1, a2, a1 ; RV32-SLOW-NEXT: vsetvli zero, zero, e16, m2, tu, ma ; RV32-SLOW-NEXT: vmv.s.x v9, a1 ; RV32-SLOW-NEXT: .LBB4_2: # %else @@ -100,7 +100,7 @@ define <2 x i16> @mgather_v2i16_align1(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> % ; RV32-SLOW-NEXT: lbu a1, 1(a0) ; RV32-SLOW-NEXT: lbu a0, 0(a0) ; RV32-SLOW-NEXT: slli a1, a1, 8 -; RV32-SLOW-NEXT: or a0, a1, a0 +; RV32-SLOW-NEXT: add a0, a1, a0 ; RV32-SLOW-NEXT: vmv.s.x v8, a0 ; RV32-SLOW-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; RV32-SLOW-NEXT: vslideup.vi v9, v8, 1 @@ -121,7 +121,7 @@ define <2 x i16> @mgather_v2i16_align1(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> % ; RV64-SLOW-NEXT: lbu a2, 1(a1) ; RV64-SLOW-NEXT: lbu a1, 0(a1) ; RV64-SLOW-NEXT: slli a2, a2, 8 -; RV64-SLOW-NEXT: or a1, a2, a1 +; RV64-SLOW-NEXT: add a1, a2, a1 ; RV64-SLOW-NEXT: vsetvli zero, zero, e16, m2, tu, ma ; RV64-SLOW-NEXT: vmv.s.x v9, a1 ; RV64-SLOW-NEXT: .LBB4_2: # %else @@ -134,7 +134,7 @@ define <2 x i16> @mgather_v2i16_align1(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> % ; RV64-SLOW-NEXT: lbu a1, 1(a0) ; RV64-SLOW-NEXT: lbu a0, 0(a0) ; RV64-SLOW-NEXT: slli a1, a1, 8 -; RV64-SLOW-NEXT: or a0, a1, a0 +; RV64-SLOW-NEXT: add a0, a1, a0 ; RV64-SLOW-NEXT: vmv.s.x v8, a0 ; RV64-SLOW-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; RV64-SLOW-NEXT: vslideup.vi v9, v8, 1 @@ -207,7 +207,7 @@ define <2 x i64> @mgather_v2i64_align4(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i64> % ; RV64-SLOW-NEXT: lw a2, 4(a1) ; RV64-SLOW-NEXT: lwu a1, 0(a1) ; RV64-SLOW-NEXT: slli a2, a2, 32 -; RV64-SLOW-NEXT: or a1, a2, a1 +; RV64-SLOW-NEXT: add a1, a2, a1 ; RV64-SLOW-NEXT: vmv.s.x v9, a1 ; RV64-SLOW-NEXT: .LBB5_2: # %else ; RV64-SLOW-NEXT: andi a0, a0, 2 @@ -219,7 +219,7 @@ define <2 x i64> @mgather_v2i64_align4(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i64> % ; RV64-SLOW-NEXT: lw a1, 4(a0) ; RV64-SLOW-NEXT: lwu a0, 0(a0) ; RV64-SLOW-NEXT: slli a1, a1, 32 -; RV64-SLOW-NEXT: or a0, a1, a0 +; RV64-SLOW-NEXT: add a0, a1, a0 ; RV64-SLOW-NEXT: vmv.s.x v8, a0 ; RV64-SLOW-NEXT: vslideup.vi v9, v8, 1 ; RV64-SLOW-NEXT: .LBB5_4: # %else2 @@ -494,11 +494,11 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi ; RV32-SLOW-NEXT: lbu a5, 2(a0) ; RV32-SLOW-NEXT: lbu a6, 3(a0) ; RV32-SLOW-NEXT: slli a3, a3, 8 -; RV32-SLOW-NEXT: or a3, a3, a4 +; RV32-SLOW-NEXT: add a3, a3, a4 ; RV32-SLOW-NEXT: slli a5, a5, 16 ; RV32-SLOW-NEXT: slli a6, a6, 24 -; RV32-SLOW-NEXT: or a4, a6, a5 -; RV32-SLOW-NEXT: or a3, a4, a3 +; RV32-SLOW-NEXT: add a5, a6, a5 +; RV32-SLOW-NEXT: add a3, a5, a3 ; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32-SLOW-NEXT: vmv.s.x v8, a3 ; RV32-SLOW-NEXT: .LBB8_2: # %else @@ -510,11 +510,11 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi ; RV32-SLOW-NEXT: lbu a4, 6(a0) ; RV32-SLOW-NEXT: lbu a0, 7(a0) ; RV32-SLOW-NEXT: slli a2, a2, 8 -; RV32-SLOW-NEXT: or a2, a2, a3 +; RV32-SLOW-NEXT: add a2, a2, a3 ; RV32-SLOW-NEXT: slli a4, a4, 16 ; RV32-SLOW-NEXT: slli a0, a0, 24 -; RV32-SLOW-NEXT: or a0, a0, a4 -; RV32-SLOW-NEXT: or a0, a0, a2 +; RV32-SLOW-NEXT: add a0, a0, a4 +; RV32-SLOW-NEXT: add a0, a0, a2 ; RV32-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32-SLOW-NEXT: vmv.s.x v9, a0 ; RV32-SLOW-NEXT: vslideup.vi v8, v9, 1 @@ -538,11 +538,11 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi ; RV64-SLOW-NEXT: lbu a5, 2(a0) ; RV64-SLOW-NEXT: lb a6, 3(a0) ; RV64-SLOW-NEXT: slli a3, a3, 8 -; RV64-SLOW-NEXT: or a3, a3, a4 +; RV64-SLOW-NEXT: add a3, a3, a4 ; RV64-SLOW-NEXT: slli a5, a5, 16 ; RV64-SLOW-NEXT: slli a6, a6, 24 -; RV64-SLOW-NEXT: or a4, a6, a5 -; RV64-SLOW-NEXT: or a3, a4, a3 +; RV64-SLOW-NEXT: add a5, a6, a5 +; RV64-SLOW-NEXT: add a3, a5, a3 ; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64-SLOW-NEXT: vmv.s.x v8, a3 ; RV64-SLOW-NEXT: .LBB8_2: # %else @@ -554,11 +554,11 @@ define void @masked_load_v2i32_align1(ptr %a, <2 x i32> %m, ptr %res_ptr) nounwi ; RV64-SLOW-NEXT: lbu a4, 6(a0) ; RV64-SLOW-NEXT: lb a0, 7(a0) ; RV64-SLOW-NEXT: slli a2, a2, 8 -; RV64-SLOW-NEXT: or a2, a2, a3 +; RV64-SLOW-NEXT: add a2, a2, a3 ; RV64-SLOW-NEXT: slli a4, a4, 16 ; RV64-SLOW-NEXT: slli a0, a0, 24 -; RV64-SLOW-NEXT: or a0, a0, a4 -; RV64-SLOW-NEXT: or a0, a0, a2 +; RV64-SLOW-NEXT: add a0, a0, a4 +; RV64-SLOW-NEXT: add a0, a0, a2 ; RV64-SLOW-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64-SLOW-NEXT: vmv.s.x v9, a0 ; RV64-SLOW-NEXT: vslideup.vi v8, v9, 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll b/llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll index ac3cd84694f4c..b7a2f9ae8d76d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fp4-bitcast.ll @@ -15,13 +15,13 @@ define <2 x i8> @fp4(<4 x i4> %0) nounwind { ; CHECK-NEXT: vmv.x.s a2, v9 ; CHECK-NEXT: andi a1, a1, 15 ; CHECK-NEXT: slli a1, a1, 4 -; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: vmv.x.s a1, v8 ; CHECK-NEXT: andi a2, a2, 15 ; CHECK-NEXT: slli a1, a1, 12 ; CHECK-NEXT: slli a2, a2, 8 -; CHECK-NEXT: or a1, a2, a1 -; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: add a1, a2, a1 +; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: sh a0, 14(sp) ; CHECK-NEXT: addi a0, sp, 14 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma diff --git a/llvm/test/CodeGen/RISCV/rvv/memset-inline.ll b/llvm/test/CodeGen/RISCV/rvv/memset-inline.ll index 2c11bd1ff5dc5..fc557bf3fa57e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/memset-inline.ll +++ b/llvm/test/CodeGen/RISCV/rvv/memset-inline.ll @@ -45,7 +45,7 @@ define void @memset_2(ptr %a, i8 %value) nounwind { ; RV32-FAST: # %bb.0: ; RV32-FAST-NEXT: zext.b a2, a1 ; RV32-FAST-NEXT: slli a1, a1, 8 -; RV32-FAST-NEXT: or a1, a1, a2 +; RV32-FAST-NEXT: add a1, a1, a2 ; RV32-FAST-NEXT: sh a1, 0(a0) ; RV32-FAST-NEXT: ret ; @@ -53,7 +53,7 @@ define void @memset_2(ptr %a, i8 %value) nounwind { ; RV64-FAST: # %bb.0: ; RV64-FAST-NEXT: zext.b a2, a1 ; RV64-FAST-NEXT: slli a1, a1, 8 -; RV64-FAST-NEXT: or a1, a1, a2 +; RV64-FAST-NEXT: add a1, a1, a2 ; RV64-FAST-NEXT: sh a1, 0(a0) ; RV64-FAST-NEXT: ret tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 2, i1 0) @@ -225,7 +225,7 @@ define void @aligned_memset_2(ptr align 2 %a, i8 %value) nounwind { ; RV32-BOTH: # %bb.0: ; RV32-BOTH-NEXT: zext.b a2, a1 ; RV32-BOTH-NEXT: slli a1, a1, 8 -; RV32-BOTH-NEXT: or a1, a1, a2 +; RV32-BOTH-NEXT: add a1, a1, a2 ; RV32-BOTH-NEXT: sh a1, 0(a0) ; RV32-BOTH-NEXT: ret ; @@ -233,7 +233,7 @@ define void @aligned_memset_2(ptr align 2 %a, i8 %value) nounwind { ; RV64-BOTH: # %bb.0: ; RV64-BOTH-NEXT: zext.b a2, a1 ; RV64-BOTH-NEXT: slli a1, a1, 8 -; RV64-BOTH-NEXT: or a1, a1, a2 +; RV64-BOTH-NEXT: add a1, a1, a2 ; RV64-BOTH-NEXT: sh a1, 0(a0) ; RV64-BOTH-NEXT: ret tail call void @llvm.memset.inline.p0.i64(ptr align 2 %a, i8 %value, i64 2, i1 0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll b/llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll index afe918bd66648..be016fd0f2b99 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vec3-setcc-crash.ll @@ -31,7 +31,7 @@ define void @vec3_setcc_crash(ptr %in, ptr %out) { ; RV32-NEXT: and a2, a6, a2 ; RV32-NEXT: slli a3, a3, 8 ; RV32-NEXT: zext.b a0, a0 -; RV32-NEXT: or a0, a0, a3 +; RV32-NEXT: add a0, a0, a3 ; RV32-NEXT: sh a0, 0(a1) ; RV32-NEXT: sb a2, 2(a1) ; RV32-NEXT: ret @@ -58,7 +58,7 @@ define void @vec3_setcc_crash(ptr %in, ptr %out) { ; RV64-NEXT: and a2, a6, a2 ; RV64-NEXT: slli a3, a3, 8 ; RV64-NEXT: zext.b a0, a0 -; RV64-NEXT: or a0, a0, a3 +; RV64-NEXT: add a0, a0, a3 ; RV64-NEXT: sh a0, 0(a1) ; RV64-NEXT: sb a2, 2(a1) ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/select-binop-identity.ll b/llvm/test/CodeGen/RISCV/select-binop-identity.ll index 8ab66ba3f25f5..79d092fe340ea 100644 --- a/llvm/test/CodeGen/RISCV/select-binop-identity.ll +++ b/llvm/test/CodeGen/RISCV/select-binop-identity.ll @@ -304,7 +304,7 @@ define i64 @and_select_all_ones_i64_cmp2(i64 %x, i64 %y, i64 %z) { ; ZICOND32-NEXT: sltiu a4, a4, 4 ; ZICOND32-NEXT: czero.eqz a6, a6, a5 ; ZICOND32-NEXT: czero.nez a4, a4, a5 -; ZICOND32-NEXT: or a4, a4, a6 +; ZICOND32-NEXT: add a4, a4, a6 ; ZICOND32-NEXT: addi a4, a4, -1 ; ZICOND32-NEXT: or a1, a4, a1 ; ZICOND32-NEXT: or a0, a4, a0 diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll index e838710878d68..05e138c900873 100644 --- a/llvm/test/CodeGen/RISCV/select-const.ll +++ b/llvm/test/CodeGen/RISCV/select-const.ll @@ -810,7 +810,7 @@ define i32 @zext_or_constant(i32 signext %x) { ; RV32ZICOND-NEXT: xori a2, a0, 1 ; RV32ZICOND-NEXT: addi a1, a1, 417 ; RV32ZICOND-NEXT: czero.eqz a0, a1, a0 -; RV32ZICOND-NEXT: or a0, a2, a0 +; RV32ZICOND-NEXT: add a0, a2, a0 ; RV32ZICOND-NEXT: ret ; ; RV64I-LABEL: zext_or_constant: @@ -844,7 +844,7 @@ define i32 @zext_or_constant(i32 signext %x) { ; RV64ZICOND-NEXT: xori a2, a0, 1 ; RV64ZICOND-NEXT: addi a1, a1, 417 ; RV64ZICOND-NEXT: czero.eqz a0, a1, a0 -; RV64ZICOND-NEXT: or a0, a2, a0 +; RV64ZICOND-NEXT: add a0, a2, a0 ; RV64ZICOND-NEXT: ret %cmp = icmp sgt i32 %x, -1 %ext = zext i1 %cmp to i32 @@ -885,7 +885,7 @@ define i32 @zext_or_constant2(i32 signext %x) { ; RV32ZICOND-NEXT: addi a1, a1, 417 ; RV32ZICOND-NEXT: czero.nez a1, a1, a0 ; RV32ZICOND-NEXT: czero.eqz a0, a2, a0 -; RV32ZICOND-NEXT: or a0, a1, a0 +; RV32ZICOND-NEXT: add a0, a1, a0 ; RV32ZICOND-NEXT: ret ; ; RV64I-LABEL: zext_or_constant2: @@ -920,7 +920,7 @@ define i32 @zext_or_constant2(i32 signext %x) { ; RV64ZICOND-NEXT: addi a1, a1, 417 ; RV64ZICOND-NEXT: czero.nez a1, a1, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a1, a0 +; RV64ZICOND-NEXT: add a0, a1, a0 ; RV64ZICOND-NEXT: ret %cmp = icmp sgt i32 %x, -1 %ext = zext i1 %cmp to i32 @@ -961,7 +961,7 @@ define i32 @sext_or_constant(i32 signext %x) { ; RV32ZICOND-NEXT: addi a1, a1, 417 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a0 ; RV32ZICOND-NEXT: czero.nez a0, a2, a0 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64I-LABEL: sext_or_constant: @@ -996,7 +996,7 @@ define i32 @sext_or_constant(i32 signext %x) { ; RV64ZICOND-NEXT: addi a1, a1, 417 ; RV64ZICOND-NEXT: czero.eqz a1, a1, a0 ; RV64ZICOND-NEXT: czero.nez a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret %cmp = icmp sgt i32 %x, -1 %ext = sext i1 %cmp to i32 @@ -1037,7 +1037,7 @@ define i32 @sext_or_constant2(i32 signext %x) { ; RV32ZICOND-NEXT: addi a1, a1, 417 ; RV32ZICOND-NEXT: czero.nez a1, a1, a0 ; RV32ZICOND-NEXT: czero.eqz a0, a2, a0 -; RV32ZICOND-NEXT: or a0, a1, a0 +; RV32ZICOND-NEXT: add a0, a1, a0 ; RV32ZICOND-NEXT: ret ; ; RV64I-LABEL: sext_or_constant2: @@ -1072,7 +1072,7 @@ define i32 @sext_or_constant2(i32 signext %x) { ; RV64ZICOND-NEXT: addi a1, a1, 417 ; RV64ZICOND-NEXT: czero.nez a1, a1, a0 ; RV64ZICOND-NEXT: czero.eqz a0, a2, a0 -; RV64ZICOND-NEXT: or a0, a1, a0 +; RV64ZICOND-NEXT: add a0, a1, a0 ; RV64ZICOND-NEXT: ret %cmp = icmp sgt i32 %x, -1 %ext = sext i1 %cmp to i32 diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll index c897dd9368248..9addc1877b0ac 100644 --- a/llvm/test/CodeGen/RISCV/select.ll +++ b/llvm/test/CodeGen/RISCV/select.ll @@ -778,7 +778,7 @@ define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMXVTCONDOPS-NEXT: subw a1, a1, a2 ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 +; RV64IMXVTCONDOPS-NEXT: add a0, a0, a2 ; RV64IMXVTCONDOPS-NEXT: ret ; ; RV32IMZICOND-LABEL: select_sub_1: @@ -786,7 +786,7 @@ define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV32IMZICOND-NEXT: sub a1, a1, a2 ; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 ; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 -; RV32IMZICOND-NEXT: or a0, a0, a2 +; RV32IMZICOND-NEXT: add a0, a0, a2 ; RV32IMZICOND-NEXT: ret ; ; RV64IMZICOND-LABEL: select_sub_1: @@ -794,7 +794,7 @@ define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMZICOND-NEXT: subw a1, a1, a2 ; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 ; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 -; RV64IMZICOND-NEXT: or a0, a0, a2 +; RV64IMZICOND-NEXT: add a0, a0, a2 ; RV64IMZICOND-NEXT: ret entry: %c = sub i32 %a, %b @@ -1019,7 +1019,7 @@ define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMXVTCONDOPS-NEXT: divuw a1, a1, a2 ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 +; RV64IMXVTCONDOPS-NEXT: add a0, a0, a2 ; RV64IMXVTCONDOPS-NEXT: ret ; ; RV32IMZICOND-LABEL: select_udiv_1: @@ -1027,7 +1027,7 @@ define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV32IMZICOND-NEXT: divu a1, a1, a2 ; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 ; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 -; RV32IMZICOND-NEXT: or a0, a0, a2 +; RV32IMZICOND-NEXT: add a0, a0, a2 ; RV32IMZICOND-NEXT: ret ; ; RV64IMZICOND-LABEL: select_udiv_1: @@ -1035,7 +1035,7 @@ define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMZICOND-NEXT: divuw a1, a1, a2 ; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 ; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 -; RV64IMZICOND-NEXT: or a0, a0, a2 +; RV64IMZICOND-NEXT: add a0, a0, a2 ; RV64IMZICOND-NEXT: ret entry: %c = udiv i32 %a, %b @@ -1067,7 +1067,7 @@ define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMXVTCONDOPS-NEXT: divuw a2, a1, a2 ; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0 ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0 +; RV64IMXVTCONDOPS-NEXT: add a0, a1, a0 ; RV64IMXVTCONDOPS-NEXT: ret ; ; RV32IMZICOND-LABEL: select_udiv_2: @@ -1075,7 +1075,7 @@ define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) { ; RV32IMZICOND-NEXT: divu a2, a1, a2 ; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0 ; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 -; RV32IMZICOND-NEXT: or a0, a1, a0 +; RV32IMZICOND-NEXT: add a0, a1, a0 ; RV32IMZICOND-NEXT: ret ; ; RV64IMZICOND-LABEL: select_udiv_2: @@ -1083,7 +1083,7 @@ define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMZICOND-NEXT: divuw a2, a1, a2 ; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0 ; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 -; RV64IMZICOND-NEXT: or a0, a1, a0 +; RV64IMZICOND-NEXT: add a0, a1, a0 ; RV64IMZICOND-NEXT: ret entry: %c = udiv i32 %a, %b @@ -1127,7 +1127,7 @@ define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) { ; RV64IMXVTCONDOPS-NEXT: srli a2, a2, 34 ; RV64IMXVTCONDOPS-NEXT: vt.maskc a1, a1, a0 ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a0, a2, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a1, a0 +; RV64IMXVTCONDOPS-NEXT: add a0, a1, a0 ; RV64IMXVTCONDOPS-NEXT: ret ; ; RV32IMZICOND-LABEL: select_udiv_3: @@ -1139,7 +1139,7 @@ define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) { ; RV32IMZICOND-NEXT: srli a2, a2, 2 ; RV32IMZICOND-NEXT: czero.eqz a1, a1, a0 ; RV32IMZICOND-NEXT: czero.nez a0, a2, a0 -; RV32IMZICOND-NEXT: or a0, a1, a0 +; RV32IMZICOND-NEXT: add a0, a1, a0 ; RV32IMZICOND-NEXT: ret ; ; RV64IMZICOND-LABEL: select_udiv_3: @@ -1151,7 +1151,7 @@ define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) { ; RV64IMZICOND-NEXT: srli a2, a2, 34 ; RV64IMZICOND-NEXT: czero.eqz a1, a1, a0 ; RV64IMZICOND-NEXT: czero.nez a0, a2, a0 -; RV64IMZICOND-NEXT: or a0, a1, a0 +; RV64IMZICOND-NEXT: add a0, a1, a0 ; RV64IMZICOND-NEXT: ret entry: %c = udiv i32 %a, 42 @@ -1183,7 +1183,7 @@ define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMXVTCONDOPS-NEXT: sllw a1, a1, a2 ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 +; RV64IMXVTCONDOPS-NEXT: add a0, a0, a2 ; RV64IMXVTCONDOPS-NEXT: ret ; ; RV32IMZICOND-LABEL: select_shl_1: @@ -1191,7 +1191,7 @@ define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV32IMZICOND-NEXT: sll a1, a1, a2 ; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 ; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 -; RV32IMZICOND-NEXT: or a0, a0, a2 +; RV32IMZICOND-NEXT: add a0, a0, a2 ; RV32IMZICOND-NEXT: ret ; ; RV64IMZICOND-LABEL: select_shl_1: @@ -1199,7 +1199,7 @@ define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMZICOND-NEXT: sllw a1, a1, a2 ; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 ; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 -; RV64IMZICOND-NEXT: or a0, a0, a2 +; RV64IMZICOND-NEXT: add a0, a0, a2 ; RV64IMZICOND-NEXT: ret entry: %c = shl i32 %a, %b @@ -1280,7 +1280,7 @@ define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMXVTCONDOPS-NEXT: sraw a1, a1, a2 ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 +; RV64IMXVTCONDOPS-NEXT: add a0, a0, a2 ; RV64IMXVTCONDOPS-NEXT: ret ; ; RV32IMZICOND-LABEL: select_ashr_1: @@ -1288,7 +1288,7 @@ define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV32IMZICOND-NEXT: sra a1, a1, a2 ; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 ; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 -; RV32IMZICOND-NEXT: or a0, a0, a2 +; RV32IMZICOND-NEXT: add a0, a0, a2 ; RV32IMZICOND-NEXT: ret ; ; RV64IMZICOND-LABEL: select_ashr_1: @@ -1296,7 +1296,7 @@ define i32 @select_ashr_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMZICOND-NEXT: sraw a1, a1, a2 ; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 ; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 -; RV64IMZICOND-NEXT: or a0, a0, a2 +; RV64IMZICOND-NEXT: add a0, a0, a2 ; RV64IMZICOND-NEXT: ret entry: %c = ashr i32 %a, %b @@ -1377,7 +1377,7 @@ define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMXVTCONDOPS-NEXT: srlw a1, a1, a2 ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 ; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a1, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 +; RV64IMXVTCONDOPS-NEXT: add a0, a0, a2 ; RV64IMXVTCONDOPS-NEXT: ret ; ; RV32IMZICOND-LABEL: select_lshr_1: @@ -1385,7 +1385,7 @@ define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV32IMZICOND-NEXT: srl a1, a1, a2 ; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 ; RV32IMZICOND-NEXT: czero.eqz a0, a1, a0 -; RV32IMZICOND-NEXT: or a0, a0, a2 +; RV32IMZICOND-NEXT: add a0, a0, a2 ; RV32IMZICOND-NEXT: ret ; ; RV64IMZICOND-LABEL: select_lshr_1: @@ -1393,7 +1393,7 @@ define i32 @select_lshr_1(i1 zeroext %cond, i32 %a, i32 %b) { ; RV64IMZICOND-NEXT: srlw a1, a1, a2 ; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 ; RV64IMZICOND-NEXT: czero.eqz a0, a1, a0 -; RV64IMZICOND-NEXT: or a0, a0, a2 +; RV64IMZICOND-NEXT: add a0, a0, a2 ; RV64IMZICOND-NEXT: ret entry: %c = lshr i32 %a, %b @@ -2168,7 +2168,7 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) { ; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) ; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a2, a0 +; RV64IMXVTCONDOPS-NEXT: add a0, a2, a0 ; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1) ; RV64IMXVTCONDOPS-NEXT: ret ; @@ -2177,7 +2177,7 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) { ; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) ; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) ; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 -; RV32IMZICOND-NEXT: or a0, a2, a0 +; RV32IMZICOND-NEXT: add a0, a2, a0 ; RV32IMZICOND-NEXT: sw a0, 0(a1) ; RV32IMZICOND-NEXT: ret ; @@ -2186,7 +2186,7 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) { ; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) ; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) ; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 -; RV64IMZICOND-NEXT: or a0, a2, a0 +; RV64IMZICOND-NEXT: add a0, a2, a0 ; RV64IMZICOND-NEXT: sd a0, 0(a1) ; RV64IMZICOND-NEXT: ret entry: @@ -2222,7 +2222,7 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) { ; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) ; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) ; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 -; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 +; RV64IMXVTCONDOPS-NEXT: add a0, a0, a2 ; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1) ; RV64IMXVTCONDOPS-NEXT: ret ; @@ -2231,7 +2231,7 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) { ; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) ; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) ; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 -; RV32IMZICOND-NEXT: or a0, a0, a2 +; RV32IMZICOND-NEXT: add a0, a0, a2 ; RV32IMZICOND-NEXT: sw a0, 0(a1) ; RV32IMZICOND-NEXT: ret ; @@ -2240,7 +2240,7 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) { ; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) ; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) ; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 -; RV64IMZICOND-NEXT: or a0, a0, a2 +; RV64IMZICOND-NEXT: add a0, a0, a2 ; RV64IMZICOND-NEXT: sd a0, 0(a1) ; RV64IMZICOND-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll index b155feab9b4d9..1d32dbc36ef21 100644 --- a/llvm/test/CodeGen/RISCV/sextw-removal.ll +++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll @@ -1520,17 +1520,17 @@ define signext i32 @test21(i64 %arg1, i64 %arg2, i64 %arg3) { ; RV64I-NEXT: and a0, a0, a3 ; RV64I-NEXT: and a6, a6, a3 ; RV64I-NEXT: slli a0, a0, 4 -; RV64I-NEXT: or a0, a6, a0 +; RV64I-NEXT: add a0, a6, a0 ; RV64I-NEXT: srli a6, a0, 2 ; RV64I-NEXT: and a0, a0, a4 ; RV64I-NEXT: and a6, a6, a4 ; RV64I-NEXT: slli a0, a0, 2 -; RV64I-NEXT: or a0, a6, a0 +; RV64I-NEXT: add a0, a6, a0 ; RV64I-NEXT: andi a6, a0, 65 ; RV64I-NEXT: srli a0, a0, 1 ; RV64I-NEXT: slli a6, a6, 1 ; RV64I-NEXT: andi a0, a0, 1104 -; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: add a0, a0, a6 ; RV64I-NEXT: addi a2, a2, 1 ; RV64I-NEXT: addw a0, a0, a1 ; RV64I-NEXT: bltu a2, a5, .LBB25_1 @@ -1609,17 +1609,17 @@ define signext i32 @test22(i64 %arg1, i64 %arg2, i64 %arg3) { ; RV64I-NEXT: slli a0, a0, 3 ; RV64I-NEXT: and t2, t2, a3 ; RV64I-NEXT: and a0, a0, a4 -; RV64I-NEXT: or a0, a0, t2 +; RV64I-NEXT: add a0, a0, t2 ; RV64I-NEXT: srli t2, a0, 2 ; RV64I-NEXT: and a0, a0, a6 ; RV64I-NEXT: and t2, t2, a5 ; RV64I-NEXT: slli a0, a0, 2 -; RV64I-NEXT: or a0, t2, a0 +; RV64I-NEXT: add a0, t2, a0 ; RV64I-NEXT: srli t2, a0, 1 ; RV64I-NEXT: and a0, a0, t0 ; RV64I-NEXT: and t2, t2, a7 ; RV64I-NEXT: slli a0, a0, 1 -; RV64I-NEXT: or a0, t2, a0 +; RV64I-NEXT: add a0, t2, a0 ; RV64I-NEXT: srli a0, a0, 28 ; RV64I-NEXT: addi a2, a2, 1 ; RV64I-NEXT: add a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/shift-and.ll b/llvm/test/CodeGen/RISCV/shift-and.ll index c9efeea980f5a..30ee15bf6221d 100644 --- a/llvm/test/CodeGen/RISCV/shift-and.ll +++ b/llvm/test/CodeGen/RISCV/shift-and.ll @@ -30,7 +30,7 @@ define i64 @test2(i64 %x) { ; RV32I: # %bb.0: ; RV32I-NEXT: slli a2, a1, 27 ; RV32I-NEXT: srli a0, a0, 5 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: srli a1, a1, 5 ; RV32I-NEXT: andi a0, a0, -8 ; RV32I-NEXT: ret @@ -68,7 +68,7 @@ define i64 @test4(i64 %x) { ; RV32I-NEXT: slli a2, a1, 26 ; RV32I-NEXT: srli a0, a0, 6 ; RV32I-NEXT: srli a1, a1, 6 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: lui a2, 1048572 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: ret @@ -106,7 +106,7 @@ define i64 @test6(i64 %x) { ; RV32I-NEXT: srli a2, a0, 26 ; RV32I-NEXT: slli a1, a1, 6 ; RV32I-NEXT: srli a0, a0, 10 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 16 ; RV32I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/shlimm-addimm.ll b/llvm/test/CodeGen/RISCV/shlimm-addimm.ll index da7f62cd3ff0c..d3c35af0c00fa 100644 --- a/llvm/test/CodeGen/RISCV/shlimm-addimm.ll +++ b/llvm/test/CodeGen/RISCV/shlimm-addimm.ll @@ -49,7 +49,7 @@ define i64 @shl5_add1184_c(i64 %x) { ; RV32I-NEXT: srli a2, a0, 27 ; RV32I-NEXT: slli a1, a1, 5 ; RV32I-NEXT: slli a3, a0, 5 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: addi a0, a3, 1184 ; RV32I-NEXT: sltu a2, a0, a3 ; RV32I-NEXT: add a1, a1, a2 @@ -113,7 +113,7 @@ define i64 @shl5_add101024_c(i64 %x) { ; RV32I-NEXT: srli a2, a0, 27 ; RV32I-NEXT: slli a1, a1, 5 ; RV32I-NEXT: slli a3, a0, 5 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: lui a0, 25 ; RV32I-NEXT: addi a0, a0, -1376 ; RV32I-NEXT: add a0, a3, a0 @@ -181,7 +181,7 @@ define i64 @shl5_add47968_c(i64 %x) { ; RV32I-NEXT: srli a2, a0, 27 ; RV32I-NEXT: slli a1, a1, 5 ; RV32I-NEXT: slli a3, a0, 5 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: lui a0, 12 ; RV32I-NEXT: addi a0, a0, -1184 ; RV32I-NEXT: add a0, a3, a0 @@ -249,7 +249,7 @@ define i64 @shl5_add47969_c(i64 %x) { ; RV32I-NEXT: srli a2, a0, 27 ; RV32I-NEXT: slli a1, a1, 5 ; RV32I-NEXT: slli a3, a0, 5 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: lui a0, 12 ; RV32I-NEXT: addi a0, a0, -1183 ; RV32I-NEXT: add a0, a3, a0 @@ -317,7 +317,7 @@ define i64 @shl5_sub47968_c(i64 %x) { ; RV32I-NEXT: srli a2, a0, 27 ; RV32I-NEXT: slli a1, a1, 5 ; RV32I-NEXT: slli a3, a0, 5 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: lui a0, 1048564 ; RV32I-NEXT: addi a0, a0, 1184 ; RV32I-NEXT: add a0, a3, a0 @@ -386,7 +386,7 @@ define i64 @shl5_sub47969_c(i64 %x) { ; RV32I-NEXT: srli a2, a0, 27 ; RV32I-NEXT: slli a1, a1, 5 ; RV32I-NEXT: slli a3, a0, 5 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: lui a0, 1048564 ; RV32I-NEXT: addi a0, a0, 1183 ; RV32I-NEXT: add a0, a3, a0 diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll index 59a702ab6b17f..d60fb1d874406 100644 --- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll +++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll @@ -2369,10 +2369,10 @@ define i64 @select_bfos(i64 %A, i64 %B, i1 zeroext %cond) { ; RV32SFB-NEXT: slli a0, a0, 31 ; RV32SFB-NEXT: slli a1, a5, 15 ; RV32SFB-NEXT: srli a0, a0, 17 -; RV32SFB-NEXT: or a5, a6, a5 +; RV32SFB-NEXT: add a5, a5, a6 ; RV32SFB-NEXT: bnez a4, .LBB40_2 ; RV32SFB-NEXT: # %bb.1: # %entry -; RV32SFB-NEXT: or a2, a0, a1 +; RV32SFB-NEXT: add a2, a0, a1 ; RV32SFB-NEXT: .LBB40_2: # %entry ; RV32SFB-NEXT: bnez a4, .LBB40_4 ; RV32SFB-NEXT: # %bb.3: # %entry diff --git a/llvm/test/CodeGen/RISCV/split-store.ll b/llvm/test/CodeGen/RISCV/split-store.ll index 4aab869561a2d..bbb5855ac18fa 100644 --- a/llvm/test/CodeGen/RISCV/split-store.ll +++ b/llvm/test/CodeGen/RISCV/split-store.ll @@ -132,7 +132,7 @@ define void @int32_int32_pair(i32 %tmp1, i32 %tmp2, ptr %ref.tmp) { ; RV64-NEXT: slli a1, a1, 32 ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a0, a0, 32 -; RV64-NEXT: or a0, a1, a0 +; RV64-NEXT: add a0, a1, a0 ; RV64-NEXT: sd a0, 0(a2) ; RV64-NEXT: ret ; @@ -141,7 +141,7 @@ define void @int32_int32_pair(i32 %tmp1, i32 %tmp2, ptr %ref.tmp) { ; RV64D-NEXT: slli a1, a1, 32 ; RV64D-NEXT: slli a0, a0, 32 ; RV64D-NEXT: srli a0, a0, 32 -; RV64D-NEXT: or a0, a1, a0 +; RV64D-NEXT: add a0, a1, a0 ; RV64D-NEXT: sd a0, 0(a2) ; RV64D-NEXT: ret %t1 = zext i32 %tmp2 to i64 diff --git a/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll b/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll index eb70d7f43c0ef..d5847ad22c2c3 100644 --- a/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll +++ b/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll @@ -476,7 +476,7 @@ define iXLen2 @test_udiv_65537(iXLen2 %x) nounwind { ; RV32-NEXT: mulhu a4, a2, a5 ; RV32-NEXT: and a3, a4, a3 ; RV32-NEXT: srli a4, a4, 16 -; RV32-NEXT: or a3, a3, a4 +; RV32-NEXT: add a3, a3, a4 ; RV32-NEXT: sub a2, a2, a3 ; RV32-NEXT: sub a3, a0, a2 ; RV32-NEXT: sltu a0, a0, a2 @@ -529,7 +529,7 @@ define iXLen2 @test_udiv_12(iXLen2 %x) nounwind { ; RV32-NEXT: srli a0, a0, 2 ; RV32-NEXT: srli a1, a1, 2 ; RV32-NEXT: lui a3, 699051 -; RV32-NEXT: or a0, a0, a2 +; RV32-NEXT: add a0, a0, a2 ; RV32-NEXT: addi a2, a3, -1365 ; RV32-NEXT: addi a3, a3, -1366 ; RV32-NEXT: add a4, a0, a1 @@ -558,7 +558,7 @@ define iXLen2 @test_udiv_12(iXLen2 %x) nounwind { ; RV64-NEXT: srli a1, a1, 2 ; RV64-NEXT: lui a3, 699051 ; RV64-NEXT: lui a4, %hi(.LCPI10_0) -; RV64-NEXT: or a0, a0, a2 +; RV64-NEXT: add a0, a0, a2 ; RV64-NEXT: addi a2, a3, -1365 ; RV64-NEXT: ld a3, %lo(.LCPI10_0)(a4) ; RV64-NEXT: add a4, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll b/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll index bc4a99a00ac64..a910c1a21e515 100644 --- a/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll +++ b/llvm/test/CodeGen/RISCV/split-urem-by-constant.ll @@ -319,7 +319,7 @@ define iXLen2 @test_urem_65537(iXLen2 %x) nounwind { ; RV32-NEXT: mulhu a1, a0, a1 ; RV32-NEXT: and a2, a1, a2 ; RV32-NEXT: srli a1, a1, 16 -; RV32-NEXT: or a1, a2, a1 +; RV32-NEXT: add a1, a2, a1 ; RV32-NEXT: sub a0, a0, a1 ; RV32-NEXT: li a1, 0 ; RV32-NEXT: ret @@ -350,7 +350,7 @@ define iXLen2 @test_urem_12(iXLen2 %x) nounwind { ; RV32-NEXT: slli a2, a1, 30 ; RV32-NEXT: srli a3, a0, 2 ; RV32-NEXT: srli a1, a1, 2 -; RV32-NEXT: or a2, a3, a2 +; RV32-NEXT: add a2, a3, a2 ; RV32-NEXT: lui a3, 699051 ; RV32-NEXT: addi a3, a3, -1365 ; RV32-NEXT: add a1, a2, a1 @@ -363,7 +363,7 @@ define iXLen2 @test_urem_12(iXLen2 %x) nounwind { ; RV32-NEXT: sub a1, a1, a2 ; RV32-NEXT: slli a1, a1, 2 ; RV32-NEXT: andi a0, a0, 3 -; RV32-NEXT: or a0, a1, a0 +; RV32-NEXT: add a0, a1, a0 ; RV32-NEXT: li a1, 0 ; RV32-NEXT: ret ; @@ -372,7 +372,7 @@ define iXLen2 @test_urem_12(iXLen2 %x) nounwind { ; RV64-NEXT: slli a2, a1, 62 ; RV64-NEXT: srli a3, a0, 2 ; RV64-NEXT: lui a4, 699051 -; RV64-NEXT: or a2, a3, a2 +; RV64-NEXT: add a2, a3, a2 ; RV64-NEXT: addi a3, a4, -1365 ; RV64-NEXT: slli a4, a3, 32 ; RV64-NEXT: add a3, a3, a4 @@ -387,7 +387,7 @@ define iXLen2 @test_urem_12(iXLen2 %x) nounwind { ; RV64-NEXT: sub a1, a1, a2 ; RV64-NEXT: slli a1, a1, 2 ; RV64-NEXT: andi a0, a0, 3 -; RV64-NEXT: or a0, a1, a0 +; RV64-NEXT: add a0, a1, a0 ; RV64-NEXT: li a1, 0 ; RV64-NEXT: ret %a = urem iXLen2 %x, 12 diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll index bc23388315de7..84fef6f528264 100644 --- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll @@ -330,12 +330,12 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32-NEXT: lw a2, 8(a0) ; RV32-NEXT: lw a3, 4(a0) ; RV32-NEXT: lw a0, 0(a0) -; RV32-NEXT: slli a4, a1, 30 -; RV32-NEXT: srli s1, a2, 2 -; RV32-NEXT: slli a5, a2, 31 -; RV32-NEXT: or s1, s1, a4 +; RV32-NEXT: slli s1, a1, 30 +; RV32-NEXT: srli a4, a2, 2 +; RV32-NEXT: slli s2, a2, 31 +; RV32-NEXT: add s1, a4, s1 ; RV32-NEXT: srli a4, a3, 1 -; RV32-NEXT: or s2, a4, a5 +; RV32-NEXT: add s2, a4, s2 ; RV32-NEXT: srli a1, a1, 2 ; RV32-NEXT: srli a2, a2, 1 ; RV32-NEXT: slli a3, a3, 31 @@ -374,13 +374,13 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: andi a4, a0, 7 ; RV32-NEXT: slli a5, a1, 1 -; RV32-NEXT: or a2, a5, a2 +; RV32-NEXT: add a2, a5, a2 ; RV32-NEXT: srli a5, a1, 31 ; RV32-NEXT: andi a1, a1, 1 ; RV32-NEXT: slli a0, a0, 2 ; RV32-NEXT: slli a1, a1, 1 -; RV32-NEXT: or a0, a5, a0 -; RV32-NEXT: or a0, a0, a1 +; RV32-NEXT: add a0, a5, a0 +; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: sw a3, 0(s0) ; RV32-NEXT: sw a2, 4(s0) ; RV32-NEXT: sw a0, 8(s0) @@ -411,9 +411,9 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV64-NEXT: lwu a1, 8(s0) ; RV64-NEXT: slli a0, a0, 32 ; RV64-NEXT: srli a2, s3, 2 -; RV64-NEXT: or a0, a1, a0 +; RV64-NEXT: add a0, a1, a0 ; RV64-NEXT: slli a1, a1, 62 -; RV64-NEXT: or a1, a1, a2 +; RV64-NEXT: add a1, a1, a2 ; RV64-NEXT: slli a2, s3, 31 ; RV64-NEXT: slli a3, a0, 29 ; RV64-NEXT: srai a0, a1, 31 @@ -486,7 +486,7 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV64-NEXT: add a2, a4, a2 ; RV64-NEXT: slli a4, a6, 31 ; RV64-NEXT: srli a4, a4, 62 -; RV64-NEXT: or a4, a4, a5 +; RV64-NEXT: add a4, a4, a5 ; RV64-NEXT: slli a5, s3, 44 ; RV64-NEXT: add a3, a3, a5 ; RV64-NEXT: slli a5, s3, 60 @@ -505,12 +505,12 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV64-NEXT: sub a2, a2, a1 ; RV64-NEXT: slli a1, a2, 63 ; RV64-NEXT: srli a2, a2, 1 -; RV64-NEXT: or a1, a2, a1 +; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: sltu a1, a5, a1 ; RV64-NEXT: neg a1, a1 ; RV64-NEXT: slli a1, a1, 31 ; RV64-NEXT: srli a1, a1, 31 -; RV64-NEXT: or a1, a1, a6 +; RV64-NEXT: add a1, a1, a6 ; RV64-NEXT: sd a1, 0(s0) ; RV64-NEXT: sw a4, 8(s0) ; RV64-NEXT: sb a0, 12(s0) @@ -539,12 +539,12 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32M-NEXT: lw a2, 8(a0) ; RV32M-NEXT: lw a3, 4(a0) ; RV32M-NEXT: lw a0, 0(a0) -; RV32M-NEXT: slli a4, a1, 30 -; RV32M-NEXT: srli s1, a2, 2 -; RV32M-NEXT: slli a5, a2, 31 -; RV32M-NEXT: or s1, s1, a4 +; RV32M-NEXT: slli s1, a1, 30 +; RV32M-NEXT: srli a4, a2, 2 +; RV32M-NEXT: slli s2, a2, 31 +; RV32M-NEXT: add s1, a4, s1 ; RV32M-NEXT: srli a4, a3, 1 -; RV32M-NEXT: or s2, a4, a5 +; RV32M-NEXT: add s2, a4, s2 ; RV32M-NEXT: srli a1, a1, 2 ; RV32M-NEXT: srli a2, a2, 1 ; RV32M-NEXT: slli a3, a3, 31 @@ -583,13 +583,13 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32M-NEXT: addi a0, a0, -1 ; RV32M-NEXT: andi a4, a0, 7 ; RV32M-NEXT: slli a5, a1, 1 -; RV32M-NEXT: or a2, a5, a2 +; RV32M-NEXT: add a2, a5, a2 ; RV32M-NEXT: srli a5, a1, 31 ; RV32M-NEXT: andi a1, a1, 1 ; RV32M-NEXT: slli a0, a0, 2 ; RV32M-NEXT: slli a1, a1, 1 -; RV32M-NEXT: or a0, a5, a0 -; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: add a0, a5, a0 +; RV32M-NEXT: add a0, a0, a1 ; RV32M-NEXT: sw a3, 0(s0) ; RV32M-NEXT: sw a2, 4(s0) ; RV32M-NEXT: sw a0, 8(s0) @@ -617,10 +617,10 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV64M-NEXT: add a5, a5, a6 ; RV64M-NEXT: srli a6, a1, 2 ; RV64M-NEXT: slli a7, a2, 62 -; RV64M-NEXT: or a6, a7, a6 +; RV64M-NEXT: add a6, a7, a6 ; RV64M-NEXT: lui a7, %hi(.LCPI3_1) ; RV64M-NEXT: slli a3, a3, 32 -; RV64M-NEXT: or a2, a2, a3 +; RV64M-NEXT: add a2, a2, a3 ; RV64M-NEXT: lui a3, %hi(.LCPI3_2) ; RV64M-NEXT: ld a4, %lo(.LCPI3_0)(a4) ; RV64M-NEXT: ld a7, %lo(.LCPI3_1)(a7) @@ -639,7 +639,7 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV64M-NEXT: add a5, a5, a7 ; RV64M-NEXT: slli a7, a1, 63 ; RV64M-NEXT: srli a1, a1, 1 -; RV64M-NEXT: or a1, a1, a7 +; RV64M-NEXT: add a1, a1, a7 ; RV64M-NEXT: srli a7, a4, 63 ; RV64M-NEXT: srai a4, a4, 1 ; RV64M-NEXT: add a4, a4, a7 @@ -661,11 +661,11 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV64M-NEXT: addi a2, a2, -1 ; RV64M-NEXT: slli a4, a3, 33 ; RV64M-NEXT: slli a3, a3, 31 -; RV64M-NEXT: or a1, a1, a4 +; RV64M-NEXT: add a1, a1, a4 ; RV64M-NEXT: slli a4, a2, 2 ; RV64M-NEXT: srli a3, a3, 62 ; RV64M-NEXT: slli a2, a2, 29 -; RV64M-NEXT: or a3, a3, a4 +; RV64M-NEXT: add a3, a3, a4 ; RV64M-NEXT: srli a2, a2, 61 ; RV64M-NEXT: sd a1, 0(a0) ; RV64M-NEXT: sw a3, 8(a0) @@ -690,12 +690,12 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32MV-NEXT: lw a3, 4(a0) ; RV32MV-NEXT: lw a0, 0(a0) ; RV32MV-NEXT: li a4, 1 -; RV32MV-NEXT: slli a5, a2, 30 -; RV32MV-NEXT: srli s1, a1, 2 -; RV32MV-NEXT: slli a6, a1, 31 -; RV32MV-NEXT: or s1, s1, a5 +; RV32MV-NEXT: slli s1, a2, 30 +; RV32MV-NEXT: srli a5, a1, 2 +; RV32MV-NEXT: slli s2, a1, 31 +; RV32MV-NEXT: add s1, a5, s1 ; RV32MV-NEXT: srli a5, a3, 1 -; RV32MV-NEXT: or s2, a5, a6 +; RV32MV-NEXT: add s2, a5, s2 ; RV32MV-NEXT: li a5, -1 ; RV32MV-NEXT: srli a2, a2, 2 ; RV32MV-NEXT: srli a1, a1, 1 @@ -763,18 +763,18 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV32MV-NEXT: sub a4, a4, a0 ; RV32MV-NEXT: srli a0, a2, 30 ; RV32MV-NEXT: slli a3, a3, 2 -; RV32MV-NEXT: or a0, a3, a0 +; RV32MV-NEXT: add a0, a3, a0 ; RV32MV-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32MV-NEXT: vse32.v v8, (s0) ; RV32MV-NEXT: vslidedown.vi v8, v8, 3 ; RV32MV-NEXT: srli a1, a1, 31 ; RV32MV-NEXT: slli a2, a2, 2 -; RV32MV-NEXT: or a1, a1, a2 +; RV32MV-NEXT: add a1, a1, a2 ; RV32MV-NEXT: vmv.x.s a2, v8 ; RV32MV-NEXT: andi a2, a2, 1 ; RV32MV-NEXT: slli a2, a2, 1 ; RV32MV-NEXT: andi a0, a0, 7 -; RV32MV-NEXT: or a1, a1, a2 +; RV32MV-NEXT: add a1, a1, a2 ; RV32MV-NEXT: sw a4, 4(s0) ; RV32MV-NEXT: sw a1, 8(s0) ; RV32MV-NEXT: sb a0, 12(s0) @@ -807,10 +807,10 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV64MV-NEXT: vmv.s.x v10, a7 ; RV64MV-NEXT: slli a3, a3, 32 ; RV64MV-NEXT: srli a7, a1, 2 -; RV64MV-NEXT: or a3, a2, a3 +; RV64MV-NEXT: add a3, a2, a3 ; RV64MV-NEXT: slli a2, a2, 62 ; RV64MV-NEXT: slli a1, a1, 31 -; RV64MV-NEXT: or a2, a2, a7 +; RV64MV-NEXT: add a2, a2, a7 ; RV64MV-NEXT: srai a1, a1, 31 ; RV64MV-NEXT: slli a3, a3, 29 ; RV64MV-NEXT: srai a2, a2, 31 @@ -859,9 +859,9 @@ define void @test_srem_vec(ptr %X) nounwind { ; RV64MV-NEXT: slli a2, a2, 2 ; RV64MV-NEXT: slli a3, a3, 31 ; RV64MV-NEXT: srli a4, a4, 61 -; RV64MV-NEXT: or a1, a1, a5 +; RV64MV-NEXT: add a1, a1, a5 ; RV64MV-NEXT: srli a3, a3, 62 -; RV64MV-NEXT: or a2, a3, a2 +; RV64MV-NEXT: add a2, a3, a2 ; RV64MV-NEXT: sd a1, 0(a0) ; RV64MV-NEXT: sw a2, 8(a0) ; RV64MV-NEXT: sb a4, 12(a0) diff --git a/llvm/test/CodeGen/RISCV/unaligned-load-store.ll b/llvm/test/CodeGen/RISCV/unaligned-load-store.ll index b396d16b0eb26..c59123b391b83 100644 --- a/llvm/test/CodeGen/RISCV/unaligned-load-store.ll +++ b/llvm/test/CodeGen/RISCV/unaligned-load-store.ll @@ -29,7 +29,7 @@ define i16 @load_i16(ptr %p) { ; SLOW-NEXT: lbu a1, 1(a0) ; SLOW-NEXT: lbu a0, 0(a0) ; SLOW-NEXT: slli a1, a1, 8 -; SLOW-NEXT: or a0, a1, a0 +; SLOW-NEXT: add a0, a1, a0 ; SLOW-NEXT: ret ; ; FAST-LABEL: load_i16: @@ -47,9 +47,9 @@ define i24 @load_i24(ptr %p) { ; SLOWBASE-NEXT: lbu a2, 0(a0) ; SLOWBASE-NEXT: lbu a0, 2(a0) ; SLOWBASE-NEXT: slli a1, a1, 8 -; SLOWBASE-NEXT: or a1, a1, a2 +; SLOWBASE-NEXT: add a1, a1, a2 ; SLOWBASE-NEXT: slli a0, a0, 16 -; SLOWBASE-NEXT: or a0, a1, a0 +; SLOWBASE-NEXT: add a0, a1, a0 ; SLOWBASE-NEXT: ret ; ; RV32IZBKB-LABEL: load_i24: @@ -68,7 +68,7 @@ define i24 @load_i24(ptr %p) { ; RV64IZBKB-NEXT: lbu a0, 2(a0) ; RV64IZBKB-NEXT: packh a1, a1, a2 ; RV64IZBKB-NEXT: slli a0, a0, 16 -; RV64IZBKB-NEXT: or a0, a1, a0 +; RV64IZBKB-NEXT: add a0, a1, a0 ; RV64IZBKB-NEXT: ret ; ; FAST-LABEL: load_i24: @@ -76,7 +76,7 @@ define i24 @load_i24(ptr %p) { ; FAST-NEXT: lbu a1, 2(a0) ; FAST-NEXT: lhu a0, 0(a0) ; FAST-NEXT: slli a1, a1, 16 -; FAST-NEXT: or a0, a0, a1 +; FAST-NEXT: add a0, a0, a1 ; FAST-NEXT: ret %res = load i24, ptr %p, align 1 ret i24 %res @@ -90,11 +90,11 @@ define i32 @load_i32(ptr %p) { ; SLOWBASE-NEXT: lbu a3, 2(a0) ; SLOWBASE-NEXT: lbu a0, 3(a0) ; SLOWBASE-NEXT: slli a1, a1, 8 -; SLOWBASE-NEXT: or a1, a1, a2 +; SLOWBASE-NEXT: add a1, a1, a2 ; SLOWBASE-NEXT: slli a3, a3, 16 ; SLOWBASE-NEXT: slli a0, a0, 24 -; SLOWBASE-NEXT: or a0, a0, a3 -; SLOWBASE-NEXT: or a0, a0, a1 +; SLOWBASE-NEXT: add a0, a0, a3 +; SLOWBASE-NEXT: add a0, a0, a1 ; SLOWBASE-NEXT: ret ; ; RV32IZBKB-LABEL: load_i32: @@ -117,8 +117,8 @@ define i32 @load_i32(ptr %p) { ; RV64IZBKB-NEXT: packh a1, a1, a2 ; RV64IZBKB-NEXT: slli a3, a3, 16 ; RV64IZBKB-NEXT: slli a0, a0, 24 -; RV64IZBKB-NEXT: or a0, a0, a3 -; RV64IZBKB-NEXT: or a0, a0, a1 +; RV64IZBKB-NEXT: add a0, a0, a3 +; RV64IZBKB-NEXT: add a0, a0, a1 ; RV64IZBKB-NEXT: ret ; ; FAST-LABEL: load_i32: @@ -139,19 +139,19 @@ define i64 @load_i64(ptr %p) { ; RV32I-NEXT: slli a1, a1, 8 ; RV32I-NEXT: slli a2, a2, 16 ; RV32I-NEXT: slli a3, a3, 24 -; RV32I-NEXT: or a1, a1, a4 -; RV32I-NEXT: or a2, a3, a2 +; RV32I-NEXT: add a1, a1, a4 +; RV32I-NEXT: add a2, a3, a2 ; RV32I-NEXT: lbu a3, 5(a0) ; RV32I-NEXT: lbu a4, 4(a0) ; RV32I-NEXT: lbu a5, 6(a0) ; RV32I-NEXT: lbu a0, 7(a0) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a4 +; RV32I-NEXT: add a3, a3, a4 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a5, a0, a5 -; RV32I-NEXT: or a0, a2, a1 -; RV32I-NEXT: or a1, a5, a3 +; RV32I-NEXT: add a5, a0, a5 +; RV32I-NEXT: add a0, a2, a1 +; RV32I-NEXT: add a1, a5, a3 ; RV32I-NEXT: ret ; ; RV64I-LABEL: load_i64: @@ -163,21 +163,21 @@ define i64 @load_i64(ptr %p) { ; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: slli a2, a2, 16 ; RV64I-NEXT: slli a3, a3, 24 -; RV64I-NEXT: or a1, a1, a4 -; RV64I-NEXT: or a2, a3, a2 +; RV64I-NEXT: add a1, a1, a4 +; RV64I-NEXT: add a2, a3, a2 ; RV64I-NEXT: lbu a3, 5(a0) ; RV64I-NEXT: lbu a4, 4(a0) ; RV64I-NEXT: lbu a5, 6(a0) ; RV64I-NEXT: lbu a0, 7(a0) ; RV64I-NEXT: slli a3, a3, 8 -; RV64I-NEXT: or a3, a3, a4 +; RV64I-NEXT: add a3, a3, a4 ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a1, a2, a1 -; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: add a0, a0, a5 +; RV64I-NEXT: add a1, a2, a1 +; RV64I-NEXT: add a0, a0, a3 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32IZBKB-LABEL: load_i64: @@ -240,9 +240,9 @@ define i64 @load_i64_align2(ptr %p) { ; RV32I-NEXT: lhu a3, 6(a0) ; RV32I-NEXT: lhu a4, 4(a0) ; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: slli a1, a3, 16 -; RV32I-NEXT: or a1, a1, a4 +; RV32I-NEXT: add a1, a1, a4 ; RV32I-NEXT: ret ; ; RV64I-LABEL: load_i64_align2: @@ -252,11 +252,11 @@ define i64 @load_i64_align2(ptr %p) { ; RV64I-NEXT: lhu a3, 4(a0) ; RV64I-NEXT: lhu a0, 6(a0) ; RV64I-NEXT: slli a1, a1, 16 -; RV64I-NEXT: or a1, a1, a2 +; RV64I-NEXT: add a1, a1, a2 ; RV64I-NEXT: slli a3, a3, 32 ; RV64I-NEXT: slli a0, a0, 48 -; RV64I-NEXT: or a0, a0, a3 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: add a0, a0, a3 +; RV64I-NEXT: add a0, a0, a1 ; RV64I-NEXT: ret ; ; RV32IZBKB-LABEL: load_i64_align2: diff --git a/llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll b/llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll index efc8243df71e0..896beab118dd5 100644 --- a/llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll +++ b/llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll @@ -21,7 +21,7 @@ define i8 @out8(i8 %x, i8 %y, i8 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: and a0, a0, a2 ; CHECK-ZBB-NEXT: andn a1, a1, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %mx = and i8 %x, %mask %notmask = xor i8 %mask, -1 @@ -42,7 +42,7 @@ define i16 @out16(i16 %x, i16 %y, i16 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: and a0, a0, a2 ; CHECK-ZBB-NEXT: andn a1, a1, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %mx = and i16 %x, %mask %notmask = xor i16 %mask, -1 @@ -63,7 +63,7 @@ define i32 @out32(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: and a0, a0, a2 ; CHECK-ZBB-NEXT: andn a1, a1, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %mx = and i32 %x, %mask %notmask = xor i32 %mask, -1 @@ -96,15 +96,15 @@ define i64 @out64(i64 %x, i64 %y, i64 %mask) { ; RV32ZBB-NEXT: and a0, a0, a4 ; RV32ZBB-NEXT: andn a3, a3, a5 ; RV32ZBB-NEXT: andn a2, a2, a4 -; RV32ZBB-NEXT: or a0, a0, a2 -; RV32ZBB-NEXT: or a1, a1, a3 +; RV32ZBB-NEXT: add a0, a0, a2 +; RV32ZBB-NEXT: add a1, a1, a3 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: out64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: and a0, a0, a2 ; RV64ZBB-NEXT: andn a1, a1, a2 -; RV64ZBB-NEXT: or a0, a0, a1 +; RV64ZBB-NEXT: add a0, a0, a1 ; RV64ZBB-NEXT: ret %mx = and i64 %x, %mask %notmask = xor i64 %mask, -1 @@ -130,7 +130,7 @@ define i8 @in8(i8 %x, i8 %y, i8 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a1, a1, a2 ; CHECK-ZBB-NEXT: and a0, a0, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %n0 = xor i8 %x, %y %n1 = and i8 %n0, %mask @@ -150,7 +150,7 @@ define i16 @in16(i16 %x, i16 %y, i16 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a1, a1, a2 ; CHECK-ZBB-NEXT: and a0, a0, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %n0 = xor i16 %x, %y %n1 = and i16 %n0, %mask @@ -170,7 +170,7 @@ define i32 @in32(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a1, a1, a2 ; CHECK-ZBB-NEXT: and a0, a0, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %n0 = xor i32 %x, %y %n1 = and i32 %n0, %mask @@ -202,15 +202,15 @@ define i64 @in64(i64 %x, i64 %y, i64 %mask) { ; RV32ZBB-NEXT: and a0, a0, a4 ; RV32ZBB-NEXT: andn a3, a3, a5 ; RV32ZBB-NEXT: and a1, a1, a5 -; RV32ZBB-NEXT: or a0, a0, a2 -; RV32ZBB-NEXT: or a1, a1, a3 +; RV32ZBB-NEXT: add a0, a0, a2 +; RV32ZBB-NEXT: add a1, a1, a3 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: in64: ; RV64ZBB: # %bb.0: ; RV64ZBB-NEXT: andn a1, a1, a2 ; RV64ZBB-NEXT: and a0, a0, a2 -; RV64ZBB-NEXT: or a0, a0, a1 +; RV64ZBB-NEXT: add a0, a0, a1 ; RV64ZBB-NEXT: ret %n0 = xor i64 %x, %y %n1 = and i64 %n0, %mask @@ -234,7 +234,7 @@ define i32 @in_commutativity_0_0_1(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a1, a1, a2 ; CHECK-ZBB-NEXT: and a0, a0, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %n0 = xor i32 %x, %y %n1 = and i32 %mask, %n0 ; swapped @@ -254,7 +254,7 @@ define i32 @in_commutativity_0_1_0(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a1, a1, a2 ; CHECK-ZBB-NEXT: and a0, a0, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %n0 = xor i32 %x, %y %n1 = and i32 %n0, %mask @@ -274,7 +274,7 @@ define i32 @in_commutativity_0_1_1(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a1, a1, a2 ; CHECK-ZBB-NEXT: and a0, a0, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %n0 = xor i32 %x, %y %n1 = and i32 %mask, %n0 ; swapped @@ -294,7 +294,7 @@ define i32 @in_commutativity_1_0_0(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a0, a0, a2 ; CHECK-ZBB-NEXT: and a1, a1, a2 -; CHECK-ZBB-NEXT: or a0, a1, a0 +; CHECK-ZBB-NEXT: add a0, a1, a0 ; CHECK-ZBB-NEXT: ret %n0 = xor i32 %x, %y %n1 = and i32 %n0, %mask @@ -314,7 +314,7 @@ define i32 @in_commutativity_1_0_1(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a0, a0, a2 ; CHECK-ZBB-NEXT: and a1, a1, a2 -; CHECK-ZBB-NEXT: or a0, a1, a0 +; CHECK-ZBB-NEXT: add a0, a1, a0 ; CHECK-ZBB-NEXT: ret %n0 = xor i32 %x, %y %n1 = and i32 %mask, %n0 ; swapped @@ -334,7 +334,7 @@ define i32 @in_commutativity_1_1_0(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a0, a0, a2 ; CHECK-ZBB-NEXT: and a1, a1, a2 -; CHECK-ZBB-NEXT: or a0, a1, a0 +; CHECK-ZBB-NEXT: add a0, a1, a0 ; CHECK-ZBB-NEXT: ret %n0 = xor i32 %x, %y %n1 = and i32 %n0, %mask @@ -354,7 +354,7 @@ define i32 @in_commutativity_1_1_1(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a0, a0, a2 ; CHECK-ZBB-NEXT: and a1, a1, a2 -; CHECK-ZBB-NEXT: or a0, a1, a0 +; CHECK-ZBB-NEXT: add a0, a1, a0 ; CHECK-ZBB-NEXT: ret %n0 = xor i32 %x, %y %n1 = and i32 %mask, %n0 ; swapped @@ -380,7 +380,7 @@ define i32 @in_complex_y0(i32 %x, i32 %y_hi, i32 %y_low, i32 %mask) { ; CHECK-ZBB-NEXT: and a1, a1, a2 ; CHECK-ZBB-NEXT: and a0, a0, a3 ; CHECK-ZBB-NEXT: andn a1, a1, a3 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %y = and i32 %y_hi, %y_low %n0 = xor i32 %x, %y @@ -403,7 +403,7 @@ define i32 @in_complex_y1(i32 %x, i32 %y_hi, i32 %y_low, i32 %mask) { ; CHECK-ZBB-NEXT: and a1, a1, a2 ; CHECK-ZBB-NEXT: and a0, a0, a3 ; CHECK-ZBB-NEXT: andn a1, a1, a3 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %y = and i32 %y_hi, %y_low %n0 = xor i32 %x, %y @@ -430,7 +430,7 @@ define i32 @in_complex_m0(i32 %x, i32 %y, i32 %m_a, i32 %m_b) { ; CHECK-ZBB-NEXT: xor a2, a2, a3 ; CHECK-ZBB-NEXT: andn a1, a1, a2 ; CHECK-ZBB-NEXT: and a0, a0, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %mask = xor i32 %m_a, %m_b %n0 = xor i32 %x, %y @@ -453,7 +453,7 @@ define i32 @in_complex_m1(i32 %x, i32 %y, i32 %m_a, i32 %m_b) { ; CHECK-ZBB-NEXT: xor a2, a2, a3 ; CHECK-ZBB-NEXT: andn a1, a1, a2 ; CHECK-ZBB-NEXT: and a0, a0, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %mask = xor i32 %m_a, %m_b %n0 = xor i32 %x, %y @@ -482,7 +482,7 @@ define i32 @in_complex_y0_m0(i32 %x, i32 %y_hi, i32 %y_low, i32 %m_a, i32 %m_b) ; CHECK-ZBB-NEXT: xor a3, a3, a4 ; CHECK-ZBB-NEXT: andn a1, a1, a3 ; CHECK-ZBB-NEXT: and a0, a0, a3 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %y = and i32 %y_hi, %y_low %mask = xor i32 %m_a, %m_b @@ -508,7 +508,7 @@ define i32 @in_complex_y1_m0(i32 %x, i32 %y_hi, i32 %y_low, i32 %m_a, i32 %m_b) ; CHECK-ZBB-NEXT: xor a3, a3, a4 ; CHECK-ZBB-NEXT: andn a1, a1, a3 ; CHECK-ZBB-NEXT: and a0, a0, a3 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %y = and i32 %y_hi, %y_low %mask = xor i32 %m_a, %m_b @@ -534,7 +534,7 @@ define i32 @in_complex_y0_m1(i32 %x, i32 %y_hi, i32 %y_low, i32 %m_a, i32 %m_b) ; CHECK-ZBB-NEXT: xor a3, a3, a4 ; CHECK-ZBB-NEXT: andn a1, a1, a3 ; CHECK-ZBB-NEXT: and a0, a0, a3 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %y = and i32 %y_hi, %y_low %mask = xor i32 %m_a, %m_b @@ -560,7 +560,7 @@ define i32 @in_complex_y1_m1(i32 %x, i32 %y_hi, i32 %y_low, i32 %m_a, i32 %m_b) ; CHECK-ZBB-NEXT: xor a3, a3, a4 ; CHECK-ZBB-NEXT: andn a1, a1, a3 ; CHECK-ZBB-NEXT: and a0, a0, a3 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %y = and i32 %y_hi, %y_low %mask = xor i32 %m_a, %m_b @@ -662,7 +662,7 @@ define i32 @out_constant_varx_42(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB-NEXT: and a0, a2, a0 ; CHECK-ZBB-NEXT: li a1, 42 ; CHECK-ZBB-NEXT: andn a1, a1, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %notmask = xor i32 %mask, -1 %mx = and i32 %mask, %x @@ -704,7 +704,7 @@ define i32 @out_constant_varx_42_invmask(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a0, a0, a2 ; CHECK-ZBB-NEXT: andi a1, a2, 42 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %notmask = xor i32 %mask, -1 %mx = and i32 %notmask, %x @@ -727,7 +727,7 @@ define i32 @in_constant_varx_42_invmask(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a0, a0, a2 ; CHECK-ZBB-NEXT: andi a1, a2, 42 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %notmask = xor i32 %mask, -1 %n0 = xor i32 %x, 42 ; %x @@ -811,7 +811,7 @@ define i32 @out_constant_42_vary(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andi a0, a2, 42 ; CHECK-ZBB-NEXT: andn a1, a1, a2 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %notmask = xor i32 %mask, -1 %mx = and i32 %mask, 42 @@ -832,7 +832,7 @@ define i32 @in_constant_42_vary(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB: # %bb.0: ; CHECK-ZBB-NEXT: andn a0, a1, a2 ; CHECK-ZBB-NEXT: andi a1, a2, 42 -; CHECK-ZBB-NEXT: or a0, a1, a0 +; CHECK-ZBB-NEXT: add a0, a1, a0 ; CHECK-ZBB-NEXT: ret %n0 = xor i32 42, %y ; %x %n1 = and i32 %n0, %mask @@ -854,7 +854,7 @@ define i32 @out_constant_42_vary_invmask(i32 %x, i32 %y, i32 %mask) { ; CHECK-ZBB-NEXT: li a0, 42 ; CHECK-ZBB-NEXT: andn a0, a0, a2 ; CHECK-ZBB-NEXT: and a1, a2, a1 -; CHECK-ZBB-NEXT: or a0, a0, a1 +; CHECK-ZBB-NEXT: add a0, a0, a1 ; CHECK-ZBB-NEXT: ret %notmask = xor i32 %mask, -1 %mx = and i32 %notmask, 42 diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll index 636fdfae68438..9290937d9a674 100644 --- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll @@ -114,7 +114,7 @@ define i1 @test_urem_even(i27 %X) nounwind { ; RV32-NEXT: slli a1, a0, 26 ; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: srli a0, a0, 6 -; RV32-NEXT: or a0, a0, a1 +; RV32-NEXT: add a0, a0, a1 ; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: srli a0, a0, 5 ; RV32-NEXT: addi a1, a2, -1755 @@ -145,7 +145,7 @@ define i1 @test_urem_even(i27 %X) nounwind { ; RV64-NEXT: slli a1, a0, 26 ; RV64-NEXT: slli a0, a0, 37 ; RV64-NEXT: srli a0, a0, 38 -; RV64-NEXT: or a0, a0, a1 +; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: slli a0, a0, 37 ; RV64-NEXT: srli a0, a0, 37 ; RV64-NEXT: addi a1, a2, -1755 @@ -160,7 +160,7 @@ define i1 @test_urem_even(i27 %X) nounwind { ; RV32M-NEXT: slli a1, a0, 26 ; RV32M-NEXT: slli a0, a0, 5 ; RV32M-NEXT: srli a0, a0, 6 -; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: add a0, a0, a1 ; RV32M-NEXT: lui a1, 2341 ; RV32M-NEXT: slli a0, a0, 5 ; RV32M-NEXT: srli a0, a0, 5 @@ -176,7 +176,7 @@ define i1 @test_urem_even(i27 %X) nounwind { ; RV64M-NEXT: slli a1, a0, 26 ; RV64M-NEXT: slli a0, a0, 37 ; RV64M-NEXT: srli a0, a0, 38 -; RV64M-NEXT: or a0, a0, a1 +; RV64M-NEXT: add a0, a0, a1 ; RV64M-NEXT: lui a1, 2341 ; RV64M-NEXT: slli a0, a0, 37 ; RV64M-NEXT: srli a0, a0, 37 @@ -192,7 +192,7 @@ define i1 @test_urem_even(i27 %X) nounwind { ; RV32MV-NEXT: slli a1, a0, 26 ; RV32MV-NEXT: slli a0, a0, 5 ; RV32MV-NEXT: srli a0, a0, 6 -; RV32MV-NEXT: or a0, a0, a1 +; RV32MV-NEXT: add a0, a0, a1 ; RV32MV-NEXT: lui a1, 2341 ; RV32MV-NEXT: slli a0, a0, 5 ; RV32MV-NEXT: srli a0, a0, 5 @@ -208,7 +208,7 @@ define i1 @test_urem_even(i27 %X) nounwind { ; RV64MV-NEXT: slli a1, a0, 26 ; RV64MV-NEXT: slli a0, a0, 37 ; RV64MV-NEXT: srli a0, a0, 38 -; RV64MV-NEXT: or a0, a0, a1 +; RV64MV-NEXT: add a0, a0, a1 ; RV64MV-NEXT: lui a1, 2341 ; RV64MV-NEXT: slli a0, a0, 37 ; RV64MV-NEXT: srli a0, a0, 37 @@ -365,7 +365,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV32-NEXT: srli a3, a2, 22 ; RV32-NEXT: srli a4, a2, 11 ; RV32-NEXT: andi a2, a2, 2047 -; RV32-NEXT: or a1, a3, a1 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: slli a3, a2, 2 ; RV32-NEXT: slli a5, a2, 4 ; RV32-NEXT: slli a6, a2, 6 @@ -400,7 +400,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV32-NEXT: srli a3, a3, 22 ; RV32-NEXT: andi a1, a4, 2047 ; RV32-NEXT: andi a2, a2, 2047 -; RV32-NEXT: or a3, a3, a5 +; RV32-NEXT: add a3, a3, a5 ; RV32-NEXT: sltiu a1, a1, 293 ; RV32-NEXT: sltiu a2, a2, 2 ; RV32-NEXT: andi a3, a3, 2047 @@ -413,8 +413,8 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV32-NEXT: slli a1, a1, 11 ; RV32-NEXT: slli a2, a2, 22 ; RV32-NEXT: andi a3, a3, 2047 -; RV32-NEXT: or a1, a1, a2 -; RV32-NEXT: or a1, a3, a1 +; RV32-NEXT: add a1, a1, a2 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: sw a1, 0(a0) ; RV32-NEXT: sb a4, 4(a0) ; RV32-NEXT: ret @@ -424,7 +424,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV64-NEXT: lbu a1, 4(a0) ; RV64-NEXT: lwu a2, 0(a0) ; RV64-NEXT: slli a1, a1, 32 -; RV64-NEXT: or a1, a2, a1 +; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: srli a2, a1, 22 ; RV64-NEXT: srli a3, a1, 11 ; RV64-NEXT: andi a1, a1, 2047 @@ -462,7 +462,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV64-NEXT: srli a4, a4, 54 ; RV64-NEXT: andi a2, a3, 2047 ; RV64-NEXT: andi a1, a1, 2047 -; RV64-NEXT: or a4, a4, a5 +; RV64-NEXT: add a4, a4, a5 ; RV64-NEXT: sltiu a2, a2, 293 ; RV64-NEXT: sltiu a1, a1, 2 ; RV64-NEXT: andi a3, a4, 2047 @@ -474,8 +474,8 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: slli a2, a2, 11 ; RV64-NEXT: andi a3, a3, 2047 -; RV64-NEXT: or a1, a2, a1 -; RV64-NEXT: or a1, a3, a1 +; RV64-NEXT: add a1, a2, a1 +; RV64-NEXT: add a1, a3, a1 ; RV64-NEXT: slli a2, a1, 31 ; RV64-NEXT: srli a2, a2, 63 ; RV64-NEXT: sw a1, 0(a0) @@ -490,7 +490,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV32M-NEXT: li a4, 819 ; RV32M-NEXT: slli a1, a1, 10 ; RV32M-NEXT: srli a5, a2, 22 -; RV32M-NEXT: or a1, a5, a1 +; RV32M-NEXT: add a1, a5, a1 ; RV32M-NEXT: andi a5, a2, 2047 ; RV32M-NEXT: mul a3, a5, a3 ; RV32M-NEXT: li a5, 1463 @@ -503,7 +503,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV32M-NEXT: srli a3, a3, 22 ; RV32M-NEXT: addi a1, a1, -1638 ; RV32M-NEXT: andi a2, a2, 2047 -; RV32M-NEXT: or a3, a3, a5 +; RV32M-NEXT: add a3, a3, a5 ; RV32M-NEXT: andi a1, a1, 2047 ; RV32M-NEXT: sltiu a2, a2, 293 ; RV32M-NEXT: andi a3, a3, 2047 @@ -517,8 +517,8 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV32M-NEXT: slli a2, a2, 11 ; RV32M-NEXT: slli a1, a1, 22 ; RV32M-NEXT: andi a3, a3, 2047 -; RV32M-NEXT: or a1, a2, a1 -; RV32M-NEXT: or a1, a3, a1 +; RV32M-NEXT: add a1, a2, a1 +; RV32M-NEXT: add a1, a3, a1 ; RV32M-NEXT: sw a1, 0(a0) ; RV32M-NEXT: sb a4, 4(a0) ; RV32M-NEXT: ret @@ -530,7 +530,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV64M-NEXT: li a3, 683 ; RV64M-NEXT: li a4, 1463 ; RV64M-NEXT: slli a1, a1, 32 -; RV64M-NEXT: or a1, a2, a1 +; RV64M-NEXT: add a1, a2, a1 ; RV64M-NEXT: andi a2, a1, 2047 ; RV64M-NEXT: mul a2, a2, a3 ; RV64M-NEXT: srli a3, a1, 11 @@ -545,7 +545,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV64M-NEXT: srli a2, a2, 54 ; RV64M-NEXT: andi a3, a3, 2047 ; RV64M-NEXT: andi a1, a1, 2047 -; RV64M-NEXT: or a2, a2, a4 +; RV64M-NEXT: add a2, a2, a4 ; RV64M-NEXT: sltiu a3, a3, 293 ; RV64M-NEXT: sltiu a1, a1, 2 ; RV64M-NEXT: andi a2, a2, 2047 @@ -557,8 +557,8 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV64M-NEXT: addi a2, a2, -1 ; RV64M-NEXT: slli a3, a3, 11 ; RV64M-NEXT: andi a2, a2, 2047 -; RV64M-NEXT: or a1, a3, a1 -; RV64M-NEXT: or a1, a2, a1 +; RV64M-NEXT: add a1, a3, a1 +; RV64M-NEXT: add a1, a2, a1 ; RV64M-NEXT: slli a2, a1, 31 ; RV64M-NEXT: srli a2, a2, 63 ; RV64M-NEXT: sw a1, 0(a0) @@ -578,7 +578,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV32MV-NEXT: slli a2, a2, 10 ; RV32MV-NEXT: vmv.v.x v10, a3 ; RV32MV-NEXT: srli a3, a1, 22 -; RV32MV-NEXT: or a2, a3, a2 +; RV32MV-NEXT: add a2, a3, a2 ; RV32MV-NEXT: lui a3, 41121 ; RV32MV-NEXT: slli a1, a1, 10 ; RV32MV-NEXT: srli a1, a1, 21 @@ -616,13 +616,13 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV32MV-NEXT: vmv.x.s a2, v9 ; RV32MV-NEXT: andi a1, a1, 2047 ; RV32MV-NEXT: slli a3, a2, 22 -; RV32MV-NEXT: or a1, a1, a3 +; RV32MV-NEXT: add a1, a1, a3 ; RV32MV-NEXT: vmv.x.s a3, v8 ; RV32MV-NEXT: slli a2, a2, 21 ; RV32MV-NEXT: andi a3, a3, 2047 ; RV32MV-NEXT: srli a2, a2, 31 ; RV32MV-NEXT: slli a3, a3, 11 -; RV32MV-NEXT: or a1, a1, a3 +; RV32MV-NEXT: add a1, a1, a3 ; RV32MV-NEXT: sw a1, 0(a0) ; RV32MV-NEXT: sb a2, 4(a0) ; RV32MV-NEXT: ret @@ -638,7 +638,7 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV64MV-NEXT: vle16.v v9, (a3) ; RV64MV-NEXT: lui a3, 41121 ; RV64MV-NEXT: slli a2, a2, 32 -; RV64MV-NEXT: or a1, a1, a2 +; RV64MV-NEXT: add a1, a1, a2 ; RV64MV-NEXT: andi a2, a1, 2047 ; RV64MV-NEXT: vmv.v.x v10, a2 ; RV64MV-NEXT: slli a2, a1, 42 @@ -680,8 +680,8 @@ define void @test_urem_vec(ptr %X) nounwind { ; RV64MV-NEXT: andi a2, a2, 2047 ; RV64MV-NEXT: slli a3, a3, 22 ; RV64MV-NEXT: slli a2, a2, 11 -; RV64MV-NEXT: or a1, a1, a3 -; RV64MV-NEXT: or a1, a1, a2 +; RV64MV-NEXT: add a1, a1, a3 +; RV64MV-NEXT: add a1, a1, a2 ; RV64MV-NEXT: slli a2, a1, 31 ; RV64MV-NEXT: srli a2, a2, 63 ; RV64MV-NEXT: sw a1, 0(a0) diff --git a/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll b/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll index 09b2eeb19a69c..535b1c217beda 100644 --- a/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll +++ b/llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll @@ -11,12 +11,12 @@ define void @lshr_4bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: lb a0, 3(a0) ; RV64I-NEXT: lbu a1, 0(a1) ; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a3, a4, a3 +; RV64I-NEXT: add a3, a4, a3 ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: add a0, a0, a5 +; RV64I-NEXT: add a0, a0, a3 ; RV64I-NEXT: srlw a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 16 ; RV64I-NEXT: srli a3, a0, 24 @@ -36,19 +36,19 @@ define void @lshr_4bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a5, a5, 24 -; RV32I-NEXT: or a0, a3, a0 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a0, a3, a0 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: lbu a3, 1(a1) ; RV32I-NEXT: lbu a5, 0(a1) ; RV32I-NEXT: lbu a6, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a5 +; RV32I-NEXT: add a3, a3, a5 ; RV32I-NEXT: slli a6, a6, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a6 -; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a6 +; RV32I-NEXT: add a0, a4, a0 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: slli a1, a1, 3 ; RV32I-NEXT: srl a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 16 @@ -75,12 +75,12 @@ define void @shl_4bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: lb a0, 3(a0) ; RV64I-NEXT: lbu a1, 0(a1) ; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a3, a4, a3 +; RV64I-NEXT: add a3, a4, a3 ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: add a0, a0, a5 +; RV64I-NEXT: add a0, a0, a3 ; RV64I-NEXT: sllw a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 16 ; RV64I-NEXT: srli a3, a0, 24 @@ -100,19 +100,19 @@ define void @shl_4bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a5, a5, 24 -; RV32I-NEXT: or a0, a3, a0 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a0, a3, a0 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: lbu a3, 1(a1) ; RV32I-NEXT: lbu a5, 0(a1) ; RV32I-NEXT: lbu a6, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a5 +; RV32I-NEXT: add a3, a3, a5 ; RV32I-NEXT: slli a6, a6, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a6 -; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a6 +; RV32I-NEXT: add a0, a4, a0 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: slli a1, a1, 3 ; RV32I-NEXT: sll a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 16 @@ -139,12 +139,12 @@ define void @ashr_4bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: lb a0, 3(a0) ; RV64I-NEXT: lbu a1, 0(a1) ; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: or a3, a4, a3 +; RV64I-NEXT: add a3, a4, a3 ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: add a0, a0, a5 +; RV64I-NEXT: add a0, a0, a3 ; RV64I-NEXT: sraw a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 16 ; RV64I-NEXT: srli a3, a0, 24 @@ -164,19 +164,19 @@ define void @ashr_4bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a5, a5, 24 -; RV32I-NEXT: or a0, a3, a0 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a0, a3, a0 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: lbu a3, 1(a1) ; RV32I-NEXT: lbu a5, 0(a1) ; RV32I-NEXT: lbu a6, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a5 +; RV32I-NEXT: add a3, a3, a5 ; RV32I-NEXT: slli a6, a6, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a6 -; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a6 +; RV32I-NEXT: add a0, a4, a0 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: slli a1, a1, 3 ; RV32I-NEXT: sra a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 16 @@ -210,39 +210,39 @@ define void @lshr_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 4(a1) -; RV64I-NEXT: lbu a7, 5(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 4(a1) +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t0, 6(a1) ; RV64I-NEXT: lbu t2, 7(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t2, t0 -; RV64I-NEXT: lbu t0, 1(a1) +; RV64I-NEXT: add a0, a0, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t2, t0 +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t1, 0(a1) ; RV64I-NEXT: lbu t2, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a4, a7, a6 -; RV64I-NEXT: or a1, a1, t0 +; RV64I-NEXT: add a1, a1, t2 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a0, a0, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 3 ; RV64I-NEXT: slli a4, a4, 35 -; RV64I-NEXT: or a0, a0, a3 -; RV64I-NEXT: or a1, a4, a1 +; RV64I-NEXT: add a0, a0, a3 +; RV64I-NEXT: add a1, a4, a1 ; RV64I-NEXT: srl a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 48 ; RV64I-NEXT: srli a3, a0, 56 @@ -270,20 +270,20 @@ define void @lshr_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a5, a5, 24 -; RV32I-NEXT: or a3, a3, a6 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a3, a3, a6 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: lbu a5, 1(a1) ; RV32I-NEXT: lbu a6, 0(a1) ; RV32I-NEXT: lbu a7, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a5, a5, 8 -; RV32I-NEXT: or a6, a5, a6 +; RV32I-NEXT: add a6, a5, a6 ; RV32I-NEXT: slli a7, a7, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a7 -; RV32I-NEXT: or a5, a4, a3 -; RV32I-NEXT: or a4, a1, a6 -; RV32I-NEXT: slli a4, a4, 3 +; RV32I-NEXT: add a1, a1, a7 +; RV32I-NEXT: add a5, a4, a3 +; RV32I-NEXT: add a1, a1, a6 +; RV32I-NEXT: slli a4, a1, 3 ; RV32I-NEXT: addi a3, a4, -32 ; RV32I-NEXT: srl a1, a5, a4 ; RV32I-NEXT: bltz a3, .LBB3_2 @@ -296,13 +296,13 @@ define void @lshr_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu t0, 2(a0) ; RV32I-NEXT: lbu a0, 3(a0) ; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a6, a6, a7 +; RV32I-NEXT: add a6, a6, a7 ; RV32I-NEXT: slli a5, a5, 1 ; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: add a0, a0, t0 ; RV32I-NEXT: not a7, a4 -; RV32I-NEXT: or a0, a0, a6 +; RV32I-NEXT: add a0, a0, a6 ; RV32I-NEXT: srl a0, a0, a4 ; RV32I-NEXT: sll a4, a5, a7 ; RV32I-NEXT: or a0, a0, a4 @@ -346,39 +346,39 @@ define void @shl_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 4(a1) -; RV64I-NEXT: lbu a7, 5(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 4(a1) +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t0, 6(a1) ; RV64I-NEXT: lbu t2, 7(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t2, t0 -; RV64I-NEXT: lbu t0, 1(a1) +; RV64I-NEXT: add a0, a0, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t2, t0 +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t1, 0(a1) ; RV64I-NEXT: lbu t2, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a4, a7, a6 -; RV64I-NEXT: or a1, a1, t0 +; RV64I-NEXT: add a1, a1, t2 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a0, a0, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 3 ; RV64I-NEXT: slli a4, a4, 35 -; RV64I-NEXT: or a0, a0, a3 -; RV64I-NEXT: or a1, a4, a1 +; RV64I-NEXT: add a0, a0, a3 +; RV64I-NEXT: add a1, a4, a1 ; RV64I-NEXT: sll a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 48 ; RV64I-NEXT: srli a3, a0, 56 @@ -406,20 +406,20 @@ define void @shl_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a5, a5, 24 -; RV32I-NEXT: or a3, a3, a6 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a3, a3, a6 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: lbu a5, 1(a1) ; RV32I-NEXT: lbu a6, 0(a1) ; RV32I-NEXT: lbu a7, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a5, a5, 8 -; RV32I-NEXT: or a6, a5, a6 +; RV32I-NEXT: add a6, a5, a6 ; RV32I-NEXT: slli a7, a7, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a7 -; RV32I-NEXT: or a5, a4, a3 -; RV32I-NEXT: or a4, a1, a6 -; RV32I-NEXT: slli a4, a4, 3 +; RV32I-NEXT: add a1, a1, a7 +; RV32I-NEXT: add a5, a4, a3 +; RV32I-NEXT: add a1, a1, a6 +; RV32I-NEXT: slli a4, a1, 3 ; RV32I-NEXT: addi a3, a4, -32 ; RV32I-NEXT: sll a1, a5, a4 ; RV32I-NEXT: bltz a3, .LBB4_2 @@ -432,13 +432,13 @@ define void @shl_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu t0, 6(a0) ; RV32I-NEXT: lbu a0, 7(a0) ; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a6, a6, a7 +; RV32I-NEXT: add a6, a6, a7 ; RV32I-NEXT: srli a5, a5, 1 ; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: add a0, a0, t0 ; RV32I-NEXT: not a7, a4 -; RV32I-NEXT: or a0, a0, a6 +; RV32I-NEXT: add a0, a0, a6 ; RV32I-NEXT: sll a0, a0, a4 ; RV32I-NEXT: srl a4, a5, a7 ; RV32I-NEXT: or a0, a0, a4 @@ -482,39 +482,39 @@ define void @ashr_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 4(a1) -; RV64I-NEXT: lbu a7, 5(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 4(a1) +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t0, 6(a1) ; RV64I-NEXT: lbu t2, 7(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t2, t0 -; RV64I-NEXT: lbu t0, 1(a1) +; RV64I-NEXT: add a0, a0, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t2, t0 +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t1, 0(a1) ; RV64I-NEXT: lbu t2, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a4, a7, a6 -; RV64I-NEXT: or a1, a1, t0 +; RV64I-NEXT: add a1, a1, t2 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a0, a0, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 3 ; RV64I-NEXT: slli a4, a4, 35 -; RV64I-NEXT: or a0, a0, a3 -; RV64I-NEXT: or a1, a4, a1 +; RV64I-NEXT: add a0, a0, a3 +; RV64I-NEXT: add a1, a4, a1 ; RV64I-NEXT: sra a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 48 ; RV64I-NEXT: srli a3, a0, 56 @@ -540,22 +540,22 @@ define void @ashr_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu a5, 6(a0) ; RV32I-NEXT: lbu a6, 7(a0) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a4 +; RV32I-NEXT: add a3, a3, a4 ; RV32I-NEXT: lbu a4, 1(a1) ; RV32I-NEXT: lbu a7, 0(a1) ; RV32I-NEXT: lbu t0, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a7, a4, a7 +; RV32I-NEXT: add a7, a4, a7 ; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, t0 +; RV32I-NEXT: add a1, a1, t0 ; RV32I-NEXT: slli a4, a5, 16 ; RV32I-NEXT: slli a5, a6, 24 -; RV32I-NEXT: or a4, a5, a4 -; RV32I-NEXT: or a4, a4, a3 -; RV32I-NEXT: or a3, a1, a7 -; RV32I-NEXT: slli a3, a3, 3 +; RV32I-NEXT: add a4, a5, a4 +; RV32I-NEXT: add a4, a4, a3 +; RV32I-NEXT: add a1, a1, a7 +; RV32I-NEXT: slli a3, a1, 3 ; RV32I-NEXT: addi a6, a3, -32 ; RV32I-NEXT: sra a1, a4, a3 ; RV32I-NEXT: bltz a6, .LBB5_2 @@ -570,13 +570,13 @@ define void @ashr_8bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu a7, 2(a0) ; RV32I-NEXT: lbu a0, 3(a0) ; RV32I-NEXT: slli a5, a5, 8 -; RV32I-NEXT: or a5, a5, a6 +; RV32I-NEXT: add a5, a5, a6 ; RV32I-NEXT: slli a4, a4, 1 ; RV32I-NEXT: slli a7, a7, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, a7 +; RV32I-NEXT: add a0, a0, a7 ; RV32I-NEXT: not a6, a3 -; RV32I-NEXT: or a0, a0, a5 +; RV32I-NEXT: add a0, a0, a5 ; RV32I-NEXT: srl a0, a0, a3 ; RV32I-NEXT: sll a3, a4, a6 ; RV32I-NEXT: or a0, a0, a3 @@ -619,39 +619,39 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 4(a1) -; RV64I-NEXT: lbu a7, 5(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 4(a1) +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t0, 6(a1) ; RV64I-NEXT: lbu t3, 7(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t2, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t3, t0 -; RV64I-NEXT: lbu t0, 1(a1) +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t3, t0 +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t2, 0(a1) ; RV64I-NEXT: lbu t3, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t2 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t2 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, t1, a5 -; RV64I-NEXT: or a5, a7, a6 -; RV64I-NEXT: or a1, a1, t0 -; RV64I-NEXT: slli a4, a4, 32 +; RV64I-NEXT: add a1, a1, t3 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 +; RV64I-NEXT: slli a5, a7, 32 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: slli a6, a5, 35 -; RV64I-NEXT: or a5, a4, a3 -; RV64I-NEXT: or a4, a6, a1 +; RV64I-NEXT: slli a4, a4, 35 +; RV64I-NEXT: add a5, a5, a3 +; RV64I-NEXT: add a4, a4, a1 ; RV64I-NEXT: addi a3, a4, -64 ; RV64I-NEXT: srl a1, a5, a4 ; RV64I-NEXT: bltz a3, .LBB6_2 @@ -666,23 +666,23 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t0, t0, 24 -; RV64I-NEXT: or a6, a6, t1 -; RV64I-NEXT: or a7, t0, a7 +; RV64I-NEXT: add a6, a6, t1 +; RV64I-NEXT: add a7, t0, a7 ; RV64I-NEXT: lbu t0, 5(a0) ; RV64I-NEXT: lbu t1, 4(a0) ; RV64I-NEXT: lbu t2, 6(a0) ; RV64I-NEXT: lbu a0, 7(a0) ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: add t0, t0, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, t2 -; RV64I-NEXT: or a6, a7, a6 +; RV64I-NEXT: add a0, a0, t2 +; RV64I-NEXT: add a6, a7, a6 ; RV64I-NEXT: not a7, a4 ; RV64I-NEXT: slli a5, a5, 1 -; RV64I-NEXT: or a0, a0, t0 +; RV64I-NEXT: add a0, a0, t0 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: add a0, a0, a6 ; RV64I-NEXT: srl a0, a0, a4 ; RV64I-NEXT: sll a4, a5, a7 ; RV64I-NEXT: or a0, a0, a4 @@ -735,8 +735,8 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, a6, a5 +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a4, a6, a5 ; RV32I-NEXT: lbu a5, 8(a0) ; RV32I-NEXT: lbu a6, 9(a0) ; RV32I-NEXT: lbu t3, 10(a0) @@ -745,22 +745,22 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 ; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, t2, t1 -; RV32I-NEXT: or a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, t2, t1 +; RV32I-NEXT: add a5, a6, a5 ; RV32I-NEXT: lbu a6, 12(a0) -; RV32I-NEXT: lbu t1, 13(a0) +; RV32I-NEXT: lbu t0, 13(a0) ; RV32I-NEXT: lbu t2, 14(a0) ; RV32I-NEXT: lbu a0, 15(a0) ; RV32I-NEXT: slli t3, t3, 16 ; RV32I-NEXT: slli t4, t4, 24 -; RV32I-NEXT: slli t1, t1, 8 +; RV32I-NEXT: slli t0, t0, 8 ; RV32I-NEXT: slli t2, t2, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or t3, t4, t3 -; RV32I-NEXT: or a6, t1, a6 -; RV32I-NEXT: or a0, a0, t2 -; RV32I-NEXT: lbu t1, 0(a1) +; RV32I-NEXT: add t3, t4, t3 +; RV32I-NEXT: add a6, t0, a6 +; RV32I-NEXT: add a0, a0, t2 +; RV32I-NEXT: lbu t0, 0(a1) ; RV32I-NEXT: lbu t2, 1(a1) ; RV32I-NEXT: lbu t4, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) @@ -769,18 +769,18 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sw zero, 24(sp) ; RV32I-NEXT: sw zero, 28(sp) ; RV32I-NEXT: slli t2, t2, 8 -; RV32I-NEXT: or t1, t2, t1 +; RV32I-NEXT: add t0, t2, t0 ; RV32I-NEXT: mv t2, sp ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, t4 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, t0, a7 -; RV32I-NEXT: or a5, t3, a5 -; RV32I-NEXT: or a0, a0, a6 -; RV32I-NEXT: or a1, a1, t1 +; RV32I-NEXT: add a1, a1, t4 +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a7, t1, a7 +; RV32I-NEXT: add a5, t3, a5 +; RV32I-NEXT: add a0, a0, a6 +; RV32I-NEXT: add a1, a1, t0 ; RV32I-NEXT: sw a3, 0(sp) -; RV32I-NEXT: sw a4, 4(sp) +; RV32I-NEXT: sw a7, 4(sp) ; RV32I-NEXT: sw a5, 8(sp) ; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: slli a0, a1, 3 @@ -858,39 +858,39 @@ define void @lshr_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 4(a1) -; RV64I-NEXT: lbu a7, 5(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 4(a1) +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t0, 6(a1) ; RV64I-NEXT: lbu t3, 7(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t2, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t3, t0 -; RV64I-NEXT: lbu t0, 1(a1) +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t3, t0 +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t2, 0(a1) ; RV64I-NEXT: lbu t3, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t2 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t2 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, t1, a5 -; RV64I-NEXT: or a5, a7, a6 -; RV64I-NEXT: or a1, a1, t0 -; RV64I-NEXT: slli a4, a4, 32 +; RV64I-NEXT: add a1, a1, t3 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 +; RV64I-NEXT: slli a5, a7, 32 ; RV64I-NEXT: slli a1, a1, 5 -; RV64I-NEXT: slli a6, a5, 37 -; RV64I-NEXT: or a5, a4, a3 -; RV64I-NEXT: or a4, a6, a1 +; RV64I-NEXT: slli a4, a4, 37 +; RV64I-NEXT: add a5, a5, a3 +; RV64I-NEXT: add a4, a4, a1 ; RV64I-NEXT: addi a3, a4, -64 ; RV64I-NEXT: srl a1, a5, a4 ; RV64I-NEXT: bltz a3, .LBB7_2 @@ -905,23 +905,23 @@ define void @lshr_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t0, t0, 24 -; RV64I-NEXT: or a6, a6, t1 -; RV64I-NEXT: or a7, t0, a7 +; RV64I-NEXT: add a6, a6, t1 +; RV64I-NEXT: add a7, t0, a7 ; RV64I-NEXT: lbu t0, 5(a0) ; RV64I-NEXT: lbu t1, 4(a0) ; RV64I-NEXT: lbu t2, 6(a0) ; RV64I-NEXT: lbu a0, 7(a0) ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: add t0, t0, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, t2 -; RV64I-NEXT: or a6, a7, a6 +; RV64I-NEXT: add a0, a0, t2 +; RV64I-NEXT: add a6, a7, a6 ; RV64I-NEXT: not a7, a4 ; RV64I-NEXT: slli a5, a5, 1 -; RV64I-NEXT: or a0, a0, t0 +; RV64I-NEXT: add a0, a0, t0 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: add a0, a0, a6 ; RV64I-NEXT: srl a0, a0, a4 ; RV64I-NEXT: sll a4, a5, a7 ; RV64I-NEXT: or a0, a0, a4 @@ -979,11 +979,11 @@ define void @lshr_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 ; RV32I-NEXT: slli t0, t0, 8 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, a6, a5 -; RV32I-NEXT: or a5, t0, a7 -; RV32I-NEXT: lbu a6, 12(a0) -; RV32I-NEXT: lbu a7, 13(a0) +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: lbu a4, 12(a0) +; RV32I-NEXT: lbu a6, 13(a0) ; RV32I-NEXT: lbu t0, 14(a0) ; RV32I-NEXT: lbu a0, 15(a0) ; RV32I-NEXT: lbu a1, 0(a1) @@ -993,28 +993,28 @@ define void @lshr_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: sw zero, 28(sp) ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 -; RV32I-NEXT: or t1, t2, t1 +; RV32I-NEXT: add t1, t2, t1 ; RV32I-NEXT: mv t2, sp ; RV32I-NEXT: slli t4, t4, 8 ; RV32I-NEXT: slli t5, t5, 16 ; RV32I-NEXT: slli t6, t6, 24 -; RV32I-NEXT: slli a7, a7, 8 +; RV32I-NEXT: slli a6, a6, 8 ; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 2 -; RV32I-NEXT: or t3, t4, t3 -; RV32I-NEXT: or t4, t6, t5 -; RV32I-NEXT: or a6, a7, a6 -; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: add t3, t4, t3 +; RV32I-NEXT: add t5, t6, t5 +; RV32I-NEXT: add a4, a6, a4 +; RV32I-NEXT: add a0, a0, t0 ; RV32I-NEXT: andi a1, a1, 12 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, t1, a5 -; RV32I-NEXT: or a5, t4, t3 -; RV32I-NEXT: or a0, a0, a6 +; RV32I-NEXT: add a3, a5, a3 +; RV32I-NEXT: add a7, t1, a7 +; RV32I-NEXT: add t3, t5, t3 +; RV32I-NEXT: add a0, a0, a4 ; RV32I-NEXT: add a1, t2, a1 ; RV32I-NEXT: sw a3, 0(sp) -; RV32I-NEXT: sw a4, 4(sp) -; RV32I-NEXT: sw a5, 8(sp) +; RV32I-NEXT: sw a7, 4(sp) +; RV32I-NEXT: sw t3, 8(sp) ; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: lw a0, 8(a1) ; RV32I-NEXT: lw a3, 4(a1) @@ -1073,39 +1073,39 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 4(a1) -; RV64I-NEXT: lbu a7, 5(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 4(a1) +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t0, 6(a1) ; RV64I-NEXT: lbu t3, 7(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t2, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t3, t0 -; RV64I-NEXT: lbu t0, 1(a1) +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t3, t0 +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t2, 0(a1) ; RV64I-NEXT: lbu t3, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t2 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t2 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, t1, a5 -; RV64I-NEXT: or a5, a7, a6 -; RV64I-NEXT: or a1, a1, t0 -; RV64I-NEXT: slli a4, a4, 32 +; RV64I-NEXT: add a1, a1, t3 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 +; RV64I-NEXT: slli a5, a7, 32 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: slli a6, a5, 35 -; RV64I-NEXT: or a5, a4, a3 -; RV64I-NEXT: or a4, a6, a1 +; RV64I-NEXT: slli a4, a4, 35 +; RV64I-NEXT: add a5, a5, a3 +; RV64I-NEXT: add a4, a4, a1 ; RV64I-NEXT: addi a3, a4, -64 ; RV64I-NEXT: sll a1, a5, a4 ; RV64I-NEXT: bltz a3, .LBB8_2 @@ -1120,23 +1120,23 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t0, t0, 24 -; RV64I-NEXT: or a6, a6, t1 -; RV64I-NEXT: or a7, t0, a7 +; RV64I-NEXT: add a6, a6, t1 +; RV64I-NEXT: add a7, t0, a7 ; RV64I-NEXT: lbu t0, 13(a0) ; RV64I-NEXT: lbu t1, 12(a0) ; RV64I-NEXT: lbu t2, 14(a0) ; RV64I-NEXT: lbu a0, 15(a0) ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: add t0, t0, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, t2 -; RV64I-NEXT: or a6, a7, a6 +; RV64I-NEXT: add a0, a0, t2 +; RV64I-NEXT: add a6, a7, a6 ; RV64I-NEXT: not a7, a4 ; RV64I-NEXT: srli a5, a5, 1 -; RV64I-NEXT: or a0, a0, t0 +; RV64I-NEXT: add a0, a0, t0 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: add a0, a0, a6 ; RV64I-NEXT: sll a0, a0, a4 ; RV64I-NEXT: srl a4, a5, a7 ; RV64I-NEXT: or a0, a0, a4 @@ -1189,8 +1189,8 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, a6, a5 +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a4, a6, a5 ; RV32I-NEXT: lbu a5, 8(a0) ; RV32I-NEXT: lbu a6, 9(a0) ; RV32I-NEXT: lbu t3, 10(a0) @@ -1199,22 +1199,22 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 ; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, t2, t1 -; RV32I-NEXT: or a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, t2, t1 +; RV32I-NEXT: add a5, a6, a5 ; RV32I-NEXT: lbu a6, 12(a0) -; RV32I-NEXT: lbu t1, 13(a0) +; RV32I-NEXT: lbu t0, 13(a0) ; RV32I-NEXT: lbu t2, 14(a0) ; RV32I-NEXT: lbu a0, 15(a0) ; RV32I-NEXT: slli t3, t3, 16 ; RV32I-NEXT: slli t4, t4, 24 -; RV32I-NEXT: slli t1, t1, 8 +; RV32I-NEXT: slli t0, t0, 8 ; RV32I-NEXT: slli t2, t2, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or t3, t4, t3 -; RV32I-NEXT: or a6, t1, a6 -; RV32I-NEXT: or a0, a0, t2 -; RV32I-NEXT: lbu t1, 0(a1) +; RV32I-NEXT: add t3, t4, t3 +; RV32I-NEXT: add a6, t0, a6 +; RV32I-NEXT: add a0, a0, t2 +; RV32I-NEXT: lbu t0, 0(a1) ; RV32I-NEXT: lbu t2, 1(a1) ; RV32I-NEXT: lbu t4, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) @@ -1223,18 +1223,18 @@ define void @shl_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sw zero, 8(sp) ; RV32I-NEXT: sw zero, 12(sp) ; RV32I-NEXT: slli t2, t2, 8 -; RV32I-NEXT: or t1, t2, t1 +; RV32I-NEXT: add t0, t2, t0 ; RV32I-NEXT: addi t2, sp, 16 ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, t4 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, t0, a7 -; RV32I-NEXT: or a5, t3, a5 -; RV32I-NEXT: or a0, a0, a6 -; RV32I-NEXT: or a1, a1, t1 +; RV32I-NEXT: add a1, a1, t4 +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a7, t1, a7 +; RV32I-NEXT: add a5, t3, a5 +; RV32I-NEXT: add a0, a0, a6 +; RV32I-NEXT: add a1, a1, t0 ; RV32I-NEXT: sw a3, 16(sp) -; RV32I-NEXT: sw a4, 20(sp) +; RV32I-NEXT: sw a7, 20(sp) ; RV32I-NEXT: sw a5, 24(sp) ; RV32I-NEXT: sw a0, 28(sp) ; RV32I-NEXT: slli a0, a1, 3 @@ -1312,39 +1312,39 @@ define void @shl_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 4(a1) -; RV64I-NEXT: lbu a7, 5(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 4(a1) +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t0, 6(a1) ; RV64I-NEXT: lbu t3, 7(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t2, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t3, t0 -; RV64I-NEXT: lbu t0, 1(a1) +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t3, t0 +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t2, 0(a1) ; RV64I-NEXT: lbu t3, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t2 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t2 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, t1, a5 -; RV64I-NEXT: or a5, a7, a6 -; RV64I-NEXT: or a1, a1, t0 -; RV64I-NEXT: slli a4, a4, 32 +; RV64I-NEXT: add a1, a1, t3 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 +; RV64I-NEXT: slli a5, a7, 32 ; RV64I-NEXT: slli a1, a1, 5 -; RV64I-NEXT: slli a6, a5, 37 -; RV64I-NEXT: or a5, a4, a3 -; RV64I-NEXT: or a4, a6, a1 +; RV64I-NEXT: slli a4, a4, 37 +; RV64I-NEXT: add a5, a5, a3 +; RV64I-NEXT: add a4, a4, a1 ; RV64I-NEXT: addi a3, a4, -64 ; RV64I-NEXT: sll a1, a5, a4 ; RV64I-NEXT: bltz a3, .LBB9_2 @@ -1359,23 +1359,23 @@ define void @shl_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw ; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t0, t0, 24 -; RV64I-NEXT: or a6, a6, t1 -; RV64I-NEXT: or a7, t0, a7 +; RV64I-NEXT: add a6, a6, t1 +; RV64I-NEXT: add a7, t0, a7 ; RV64I-NEXT: lbu t0, 13(a0) ; RV64I-NEXT: lbu t1, 12(a0) ; RV64I-NEXT: lbu t2, 14(a0) ; RV64I-NEXT: lbu a0, 15(a0) ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: add t0, t0, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, t2 -; RV64I-NEXT: or a6, a7, a6 +; RV64I-NEXT: add a0, a0, t2 +; RV64I-NEXT: add a6, a7, a6 ; RV64I-NEXT: not a7, a4 ; RV64I-NEXT: srli a5, a5, 1 -; RV64I-NEXT: or a0, a0, t0 +; RV64I-NEXT: add a0, a0, t0 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: add a0, a0, a6 ; RV64I-NEXT: sll a0, a0, a4 ; RV64I-NEXT: srl a4, a5, a7 ; RV64I-NEXT: or a0, a0, a4 @@ -1433,11 +1433,11 @@ define void @shl_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 ; RV32I-NEXT: slli t0, t0, 8 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, a6, a5 -; RV32I-NEXT: or a5, t0, a7 -; RV32I-NEXT: lbu a6, 12(a0) -; RV32I-NEXT: lbu a7, 13(a0) +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: lbu a4, 12(a0) +; RV32I-NEXT: lbu a6, 13(a0) ; RV32I-NEXT: lbu t0, 14(a0) ; RV32I-NEXT: lbu a0, 15(a0) ; RV32I-NEXT: lbu a1, 0(a1) @@ -1447,28 +1447,28 @@ define void @shl_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw ; RV32I-NEXT: sw zero, 12(sp) ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 -; RV32I-NEXT: or t1, t2, t1 +; RV32I-NEXT: add t1, t2, t1 ; RV32I-NEXT: addi t2, sp, 16 ; RV32I-NEXT: slli t4, t4, 8 ; RV32I-NEXT: slli t5, t5, 16 ; RV32I-NEXT: slli t6, t6, 24 -; RV32I-NEXT: slli a7, a7, 8 +; RV32I-NEXT: slli a6, a6, 8 ; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 2 -; RV32I-NEXT: or t3, t4, t3 -; RV32I-NEXT: or t4, t6, t5 -; RV32I-NEXT: or a6, a7, a6 -; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: add t3, t4, t3 +; RV32I-NEXT: add t5, t6, t5 +; RV32I-NEXT: add a4, a6, a4 +; RV32I-NEXT: add a0, a0, t0 ; RV32I-NEXT: andi a1, a1, 12 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, t1, a5 -; RV32I-NEXT: or a5, t4, t3 -; RV32I-NEXT: or a0, a0, a6 +; RV32I-NEXT: add a3, a5, a3 +; RV32I-NEXT: add a7, t1, a7 +; RV32I-NEXT: add t3, t5, t3 +; RV32I-NEXT: add a0, a0, a4 ; RV32I-NEXT: sub a1, t2, a1 ; RV32I-NEXT: sw a3, 16(sp) -; RV32I-NEXT: sw a4, 20(sp) -; RV32I-NEXT: sw a5, 24(sp) +; RV32I-NEXT: sw a7, 20(sp) +; RV32I-NEXT: sw t3, 24(sp) ; RV32I-NEXT: sw a0, 28(sp) ; RV32I-NEXT: lw a0, 8(a1) ; RV32I-NEXT: lw a3, 4(a1) @@ -1528,39 +1528,39 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 4(a1) -; RV64I-NEXT: lbu a7, 5(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 4(a1) +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t0, 6(a1) ; RV64I-NEXT: lbu t3, 7(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t2, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t3, t0 -; RV64I-NEXT: lbu t0, 1(a1) +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t3, t0 +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t2, 0(a1) ; RV64I-NEXT: lbu t3, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t2 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t2 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a5, t1, a5 -; RV64I-NEXT: or a4, a7, a6 -; RV64I-NEXT: or a1, a1, t0 +; RV64I-NEXT: add a1, a1, t3 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a5, t1, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 ; RV64I-NEXT: slli a6, a5, 32 ; RV64I-NEXT: slli a1, a1, 3 ; RV64I-NEXT: slli a7, a4, 35 -; RV64I-NEXT: or a4, a6, a3 -; RV64I-NEXT: or a3, a7, a1 +; RV64I-NEXT: add a4, a6, a3 +; RV64I-NEXT: add a3, a7, a1 ; RV64I-NEXT: addi a6, a3, -64 ; RV64I-NEXT: sra a1, a4, a3 ; RV64I-NEXT: bltz a6, .LBB10_2 @@ -1577,23 +1577,23 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 8 ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 -; RV64I-NEXT: or a5, a5, t0 -; RV64I-NEXT: or a6, a7, a6 +; RV64I-NEXT: add a5, a5, t0 +; RV64I-NEXT: add a6, a7, a6 ; RV64I-NEXT: lbu a7, 5(a0) ; RV64I-NEXT: lbu t0, 4(a0) ; RV64I-NEXT: lbu t1, 6(a0) ; RV64I-NEXT: lbu a0, 7(a0) ; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 +; RV64I-NEXT: add a7, a7, t0 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: or a5, a6, a5 +; RV64I-NEXT: add a0, a0, t1 +; RV64I-NEXT: add a5, a6, a5 ; RV64I-NEXT: not a6, a3 ; RV64I-NEXT: slli a4, a4, 1 -; RV64I-NEXT: or a0, a0, a7 +; RV64I-NEXT: add a0, a0, a7 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a5 +; RV64I-NEXT: add a0, a0, a5 ; RV64I-NEXT: srl a0, a0, a3 ; RV64I-NEXT: sll a3, a4, a6 ; RV64I-NEXT: or a0, a0, a3 @@ -1642,7 +1642,7 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu t1, 6(a0) ; RV32I-NEXT: lbu t2, 7(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: lbu a4, 8(a0) ; RV32I-NEXT: lbu t3, 9(a0) ; RV32I-NEXT: lbu t4, 10(a0) @@ -1652,50 +1652,50 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli t0, t0, 8 ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a6, t0, a7 -; RV32I-NEXT: or a7, t2, t1 -; RV32I-NEXT: lbu t0, 12(a0) -; RV32I-NEXT: lbu t1, 13(a0) +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, t2, t1 +; RV32I-NEXT: lbu a6, 12(a0) +; RV32I-NEXT: lbu t0, 13(a0) ; RV32I-NEXT: lbu t2, 14(a0) ; RV32I-NEXT: lbu a0, 15(a0) ; RV32I-NEXT: slli t3, t3, 8 ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli t5, t5, 24 -; RV32I-NEXT: slli t1, t1, 8 -; RV32I-NEXT: or a4, t3, a4 -; RV32I-NEXT: or t3, t5, t4 -; RV32I-NEXT: or t0, t1, t0 -; RV32I-NEXT: lbu t1, 1(a1) -; RV32I-NEXT: lbu t4, 0(a1) +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: add a4, t3, a4 +; RV32I-NEXT: add t4, t5, t4 +; RV32I-NEXT: add a6, t0, a6 +; RV32I-NEXT: lbu t0, 1(a1) +; RV32I-NEXT: lbu t3, 0(a1) ; RV32I-NEXT: lbu t5, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) -; RV32I-NEXT: slli t1, t1, 8 -; RV32I-NEXT: or t1, t1, t4 +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: add t0, t0, t3 ; RV32I-NEXT: slli t5, t5, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, t5 -; RV32I-NEXT: mv t4, sp +; RV32I-NEXT: add a1, a1, t5 +; RV32I-NEXT: mv t3, sp ; RV32I-NEXT: slli t2, t2, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or t2, a0, t2 +; RV32I-NEXT: add t2, a0, t2 ; RV32I-NEXT: srai a0, a0, 31 -; RV32I-NEXT: or a3, a5, a3 -; RV32I-NEXT: or a5, a7, a6 -; RV32I-NEXT: or a4, t3, a4 -; RV32I-NEXT: or a6, t2, t0 -; RV32I-NEXT: or a1, a1, t1 +; RV32I-NEXT: add a3, a5, a3 +; RV32I-NEXT: add a7, t1, a7 +; RV32I-NEXT: add a4, t4, a4 +; RV32I-NEXT: add a6, t2, a6 +; RV32I-NEXT: add a1, a1, t0 ; RV32I-NEXT: sw a0, 16(sp) ; RV32I-NEXT: sw a0, 20(sp) ; RV32I-NEXT: sw a0, 24(sp) ; RV32I-NEXT: sw a0, 28(sp) ; RV32I-NEXT: sw a3, 0(sp) -; RV32I-NEXT: sw a5, 4(sp) +; RV32I-NEXT: sw a7, 4(sp) ; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a6, 12(sp) ; RV32I-NEXT: slli a0, a1, 3 ; RV32I-NEXT: andi a1, a1, 12 -; RV32I-NEXT: add a1, t4, a1 +; RV32I-NEXT: add a1, t3, a1 ; RV32I-NEXT: andi a3, a0, 24 ; RV32I-NEXT: xori a3, a3, 31 ; RV32I-NEXT: lw a4, 4(a1) @@ -1768,39 +1768,39 @@ define void @ashr_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 4(a1) -; RV64I-NEXT: lbu a7, 5(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 4(a1) +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t0, 6(a1) ; RV64I-NEXT: lbu t3, 7(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t2, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t3, t0 -; RV64I-NEXT: lbu t0, 1(a1) +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t3, t0 +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t2, 0(a1) ; RV64I-NEXT: lbu t3, 2(a1) ; RV64I-NEXT: lbu a1, 3(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t2 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t2 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a5, t1, a5 -; RV64I-NEXT: or a4, a7, a6 -; RV64I-NEXT: or a1, a1, t0 +; RV64I-NEXT: add a1, a1, t3 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a5, t1, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 ; RV64I-NEXT: slli a6, a5, 32 ; RV64I-NEXT: slli a1, a1, 5 ; RV64I-NEXT: slli a7, a4, 37 -; RV64I-NEXT: or a4, a6, a3 -; RV64I-NEXT: or a3, a7, a1 +; RV64I-NEXT: add a4, a6, a3 +; RV64I-NEXT: add a3, a7, a1 ; RV64I-NEXT: addi a6, a3, -64 ; RV64I-NEXT: sra a1, a4, a3 ; RV64I-NEXT: bltz a6, .LBB11_2 @@ -1817,23 +1817,23 @@ define void @ashr_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV64I-NEXT: slli a5, a5, 8 ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 -; RV64I-NEXT: or a5, a5, t0 -; RV64I-NEXT: or a6, a7, a6 +; RV64I-NEXT: add a5, a5, t0 +; RV64I-NEXT: add a6, a7, a6 ; RV64I-NEXT: lbu a7, 5(a0) ; RV64I-NEXT: lbu t0, 4(a0) ; RV64I-NEXT: lbu t1, 6(a0) ; RV64I-NEXT: lbu a0, 7(a0) ; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 +; RV64I-NEXT: add a7, a7, t0 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: or a5, a6, a5 +; RV64I-NEXT: add a0, a0, t1 +; RV64I-NEXT: add a5, a6, a5 ; RV64I-NEXT: not a6, a3 ; RV64I-NEXT: slli a4, a4, 1 -; RV64I-NEXT: or a0, a0, a7 +; RV64I-NEXT: add a0, a0, a7 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a5 +; RV64I-NEXT: add a0, a0, a5 ; RV64I-NEXT: srl a0, a0, a3 ; RV64I-NEXT: sll a3, a4, a6 ; RV64I-NEXT: or a0, a0, a3 @@ -1889,44 +1889,44 @@ define void @ashr_16bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 ; RV32I-NEXT: slli t0, t0, 8 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, a6, a5 -; RV32I-NEXT: or a5, t0, a7 -; RV32I-NEXT: lbu a6, 12(a0) -; RV32I-NEXT: lbu a7, 13(a0) +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: lbu a4, 12(a0) +; RV32I-NEXT: lbu a6, 13(a0) ; RV32I-NEXT: lbu t0, 14(a0) ; RV32I-NEXT: lbu a0, 15(a0) ; RV32I-NEXT: lbu a1, 0(a1) ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 -; RV32I-NEXT: or t1, t2, t1 +; RV32I-NEXT: add t1, t2, t1 ; RV32I-NEXT: mv t2, sp ; RV32I-NEXT: slli t4, t4, 8 ; RV32I-NEXT: slli t5, t5, 16 ; RV32I-NEXT: slli t6, t6, 24 -; RV32I-NEXT: slli a7, a7, 8 +; RV32I-NEXT: slli a6, a6, 8 ; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 2 -; RV32I-NEXT: or t3, t4, t3 -; RV32I-NEXT: or t4, t6, t5 -; RV32I-NEXT: or a6, a7, a6 -; RV32I-NEXT: or a7, a0, t0 +; RV32I-NEXT: add t3, t4, t3 +; RV32I-NEXT: add t5, t6, t5 +; RV32I-NEXT: add a4, a6, a4 +; RV32I-NEXT: add t0, a0, t0 ; RV32I-NEXT: srai a0, a0, 31 ; RV32I-NEXT: andi a1, a1, 12 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, t1, a5 -; RV32I-NEXT: or a5, t4, t3 -; RV32I-NEXT: or a6, a7, a6 +; RV32I-NEXT: add a3, a5, a3 +; RV32I-NEXT: add a7, t1, a7 +; RV32I-NEXT: add t3, t5, t3 +; RV32I-NEXT: add a4, t0, a4 ; RV32I-NEXT: sw a0, 16(sp) ; RV32I-NEXT: sw a0, 20(sp) ; RV32I-NEXT: sw a0, 24(sp) ; RV32I-NEXT: sw a0, 28(sp) ; RV32I-NEXT: add a1, t2, a1 ; RV32I-NEXT: sw a3, 0(sp) -; RV32I-NEXT: sw a4, 4(sp) -; RV32I-NEXT: sw a5, 8(sp) -; RV32I-NEXT: sw a6, 12(sp) +; RV32I-NEXT: sw a7, 4(sp) +; RV32I-NEXT: sw t3, 8(sp) +; RV32I-NEXT: sw a4, 12(sp) ; RV32I-NEXT: lw a0, 8(a1) ; RV32I-NEXT: lw a3, 4(a1) ; RV32I-NEXT: lw a4, 0(a1) @@ -2011,49 +2011,49 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli t0, t0, 8 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a4, a6, a5 +; RV64I-NEXT: add a5, t0, a7 +; RV64I-NEXT: add a6, t2, t1 ; RV64I-NEXT: lbu s8, 20(a0) ; RV64I-NEXT: lbu s9, 21(a0) ; RV64I-NEXT: lbu s10, 22(a0) ; RV64I-NEXT: lbu s11, 23(a0) -; RV64I-NEXT: slli t4, t4, 8 -; RV64I-NEXT: slli t5, t5, 16 +; RV64I-NEXT: slli a7, t4, 8 +; RV64I-NEXT: slli t0, t5, 16 ; RV64I-NEXT: slli t6, t6, 24 -; RV64I-NEXT: slli s1, s1, 8 -; RV64I-NEXT: slli s2, s2, 16 +; RV64I-NEXT: slli t1, s1, 8 +; RV64I-NEXT: slli t2, s2, 16 ; RV64I-NEXT: slli s3, s3, 24 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or t0, t6, t5 -; RV64I-NEXT: or t1, s1, s0 -; RV64I-NEXT: or t2, s3, s2 +; RV64I-NEXT: add a7, a7, t3 +; RV64I-NEXT: add t0, t6, t0 +; RV64I-NEXT: add t1, t1, s0 +; RV64I-NEXT: add t2, s3, t2 ; RV64I-NEXT: lbu t6, 24(a0) ; RV64I-NEXT: lbu s0, 25(a0) ; RV64I-NEXT: lbu s1, 26(a0) ; RV64I-NEXT: lbu s2, 27(a0) -; RV64I-NEXT: slli s5, s5, 8 -; RV64I-NEXT: slli s6, s6, 16 +; RV64I-NEXT: slli t3, s5, 8 +; RV64I-NEXT: slli t4, s6, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: slli s9, s9, 8 -; RV64I-NEXT: or t3, s5, s4 -; RV64I-NEXT: or t4, s7, s6 -; RV64I-NEXT: or t5, s9, s8 +; RV64I-NEXT: slli t5, s9, 8 +; RV64I-NEXT: add t3, t3, s4 +; RV64I-NEXT: add t4, s7, t4 +; RV64I-NEXT: add t5, t5, s8 ; RV64I-NEXT: lbu s3, 28(a0) ; RV64I-NEXT: lbu s4, 29(a0) ; RV64I-NEXT: lbu s5, 30(a0) ; RV64I-NEXT: lbu s6, 31(a0) -; RV64I-NEXT: slli s10, s10, 16 +; RV64I-NEXT: slli a0, s10, 16 ; RV64I-NEXT: slli s11, s11, 24 ; RV64I-NEXT: slli s0, s0, 8 ; RV64I-NEXT: slli s1, s1, 16 ; RV64I-NEXT: slli s2, s2, 24 ; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or a0, s11, s10 -; RV64I-NEXT: or t6, s0, t6 -; RV64I-NEXT: or s0, s2, s1 -; RV64I-NEXT: or s1, s4, s3 +; RV64I-NEXT: add a0, s11, a0 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s0, s2, s1 +; RV64I-NEXT: add s1, s4, s3 ; RV64I-NEXT: lbu s2, 0(a1) ; RV64I-NEXT: lbu s3, 1(a1) ; RV64I-NEXT: lbu s4, 2(a1) @@ -2063,47 +2063,47 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli s3, s3, 8 ; RV64I-NEXT: slli s4, s4, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: or s5, s6, s5 -; RV64I-NEXT: or s2, s3, s2 -; RV64I-NEXT: or s3, s7, s4 -; RV64I-NEXT: lbu s4, 5(a1) +; RV64I-NEXT: add s5, s6, s5 +; RV64I-NEXT: add s2, s3, s2 +; RV64I-NEXT: add s4, s7, s4 +; RV64I-NEXT: lbu s3, 5(a1) ; RV64I-NEXT: lbu s6, 4(a1) ; RV64I-NEXT: lbu s7, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or s4, s4, s6 +; RV64I-NEXT: slli s3, s3, 8 +; RV64I-NEXT: add s3, s3, s6 ; RV64I-NEXT: sd zero, 32(sp) ; RV64I-NEXT: sd zero, 40(sp) ; RV64I-NEXT: sd zero, 48(sp) ; RV64I-NEXT: sd zero, 56(sp) ; RV64I-NEXT: slli s7, s7, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, s7 +; RV64I-NEXT: add a1, a1, s7 ; RV64I-NEXT: mv s6, sp -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or a0, a0, t5 -; RV64I-NEXT: or t0, s0, t6 -; RV64I-NEXT: or t1, s5, s1 -; RV64I-NEXT: or t2, s3, s2 -; RV64I-NEXT: or a1, a1, s4 -; RV64I-NEXT: slli a4, a4, 32 -; RV64I-NEXT: slli a6, a6, 32 -; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add t3, t4, t3 +; RV64I-NEXT: add a0, a0, t5 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s1, s5, s1 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add a1, a1, s3 +; RV64I-NEXT: slli a5, a5, 32 ; RV64I-NEXT: slli t1, t1, 32 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: slli s1, s1, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a0, a0, a7 -; RV64I-NEXT: or a5, t1, t0 -; RV64I-NEXT: or a1, a1, t2 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a0, a0, t3 +; RV64I-NEXT: add t6, s1, t6 +; RV64I-NEXT: add a1, a1, s2 ; RV64I-NEXT: sd a3, 0(sp) -; RV64I-NEXT: sd a4, 8(sp) +; RV64I-NEXT: sd a7, 8(sp) ; RV64I-NEXT: sd a0, 16(sp) -; RV64I-NEXT: sd a5, 24(sp) +; RV64I-NEXT: sd t6, 24(sp) ; RV64I-NEXT: slli a4, a1, 3 ; RV64I-NEXT: andi a1, a1, 24 ; RV64I-NEXT: add a1, s6, a1 @@ -2247,34 +2247,34 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli t3, t3, 8 ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli s0, s0, 24 -; RV32I-NEXT: or a4, a4, s1 +; RV32I-NEXT: add a4, a4, s1 ; RV32I-NEXT: sw a4, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: or a4, a6, a5 -; RV32I-NEXT: or a5, t3, t1 -; RV32I-NEXT: or a6, s0, t4 +; RV32I-NEXT: add a4, a6, a5 +; RV32I-NEXT: add a5, t3, t1 +; RV32I-NEXT: add a6, s0, t4 ; RV32I-NEXT: lbu t1, 24(a0) ; RV32I-NEXT: lbu s0, 25(a0) ; RV32I-NEXT: lbu s1, 26(a0) ; RV32I-NEXT: lbu s2, 27(a0) ; RV32I-NEXT: slli s3, s3, 8 -; RV32I-NEXT: slli s6, s6, 16 +; RV32I-NEXT: slli t3, s6, 16 ; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: slli s10, s10, 8 -; RV32I-NEXT: or t2, s3, t2 -; RV32I-NEXT: or t3, s8, s6 -; RV32I-NEXT: or t4, s10, s9 +; RV32I-NEXT: slli t4, s10, 8 +; RV32I-NEXT: add t2, s3, t2 +; RV32I-NEXT: add t3, s8, t3 +; RV32I-NEXT: add t4, t4, s9 ; RV32I-NEXT: lbu s3, 28(a0) ; RV32I-NEXT: lbu s6, 29(a0) ; RV32I-NEXT: lbu s8, 30(a0) ; RV32I-NEXT: lbu s9, 31(a0) -; RV32I-NEXT: slli s4, s4, 16 +; RV32I-NEXT: slli a0, s4, 16 ; RV32I-NEXT: slli s7, s7, 24 -; RV32I-NEXT: slli s11, s11, 8 +; RV32I-NEXT: slli s4, s11, 8 ; RV32I-NEXT: slli ra, ra, 16 ; RV32I-NEXT: slli a3, a3, 24 -; RV32I-NEXT: or a0, s7, s4 -; RV32I-NEXT: or s4, s11, s5 -; RV32I-NEXT: or s5, a3, ra +; RV32I-NEXT: add a0, s7, a0 +; RV32I-NEXT: add s4, s4, s5 +; RV32I-NEXT: add s5, a3, ra ; RV32I-NEXT: lbu a3, 0(a1) ; RV32I-NEXT: lbu s7, 1(a1) ; RV32I-NEXT: lbu s10, 2(a1) @@ -2288,7 +2288,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sw zero, 48(sp) ; RV32I-NEXT: sw zero, 52(sp) ; RV32I-NEXT: slli t6, t6, 8 -; RV32I-NEXT: or t5, t6, t5 +; RV32I-NEXT: add t5, t6, t5 ; RV32I-NEXT: addi t6, sp, 8 ; RV32I-NEXT: slli a7, a7, 16 ; RV32I-NEXT: slli t0, t0, 24 @@ -2301,30 +2301,30 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli s7, s7, 8 ; RV32I-NEXT: slli s10, s10, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, s0, t1 -; RV32I-NEXT: or t1, s2, s1 -; RV32I-NEXT: or s0, s6, s3 -; RV32I-NEXT: or s1, s9, s8 -; RV32I-NEXT: or a3, s7, a3 -; RV32I-NEXT: or a1, a1, s10 -; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, a4, s2 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a6, t3, t2 -; RV32I-NEXT: or a0, a0, t4 -; RV32I-NEXT: or t2, s5, s4 -; RV32I-NEXT: or a7, a7, t5 -; RV32I-NEXT: or t0, t1, t0 -; RV32I-NEXT: or s0, s1, s0 -; RV32I-NEXT: or a1, a1, a3 -; RV32I-NEXT: sw t2, 24(sp) +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, s0, t1 +; RV32I-NEXT: add s1, s2, s1 +; RV32I-NEXT: add s3, s6, s3 +; RV32I-NEXT: add s8, s9, s8 +; RV32I-NEXT: add a3, s7, a3 +; RV32I-NEXT: add a1, a1, s10 +; RV32I-NEXT: lw t0, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: add a4, a4, t0 +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add t2, t3, t2 +; RV32I-NEXT: add a0, a0, t4 +; RV32I-NEXT: add s4, s5, s4 +; RV32I-NEXT: add a7, a7, t5 +; RV32I-NEXT: add t1, s1, t1 +; RV32I-NEXT: add s3, s8, s3 +; RV32I-NEXT: add a1, a1, a3 +; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw a7, 28(sp) -; RV32I-NEXT: sw t0, 32(sp) -; RV32I-NEXT: sw s0, 36(sp) +; RV32I-NEXT: sw t1, 32(sp) +; RV32I-NEXT: sw s3, 36(sp) ; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a5, 12(sp) -; RV32I-NEXT: sw a6, 16(sp) +; RV32I-NEXT: sw t2, 16(sp) ; RV32I-NEXT: sw a0, 20(sp) ; RV32I-NEXT: slli t1, a1, 3 ; RV32I-NEXT: andi a1, a1, 28 @@ -2489,49 +2489,49 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV64I-NEXT: slli t0, t0, 8 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a4, a6, a5 +; RV64I-NEXT: add a5, t0, a7 +; RV64I-NEXT: add a6, t2, t1 ; RV64I-NEXT: lbu s8, 20(a0) ; RV64I-NEXT: lbu s9, 21(a0) ; RV64I-NEXT: lbu s10, 22(a0) ; RV64I-NEXT: lbu s11, 23(a0) -; RV64I-NEXT: slli t4, t4, 8 -; RV64I-NEXT: slli t5, t5, 16 +; RV64I-NEXT: slli a7, t4, 8 +; RV64I-NEXT: slli t0, t5, 16 ; RV64I-NEXT: slli t6, t6, 24 -; RV64I-NEXT: slli s1, s1, 8 -; RV64I-NEXT: slli s2, s2, 16 +; RV64I-NEXT: slli t1, s1, 8 +; RV64I-NEXT: slli t2, s2, 16 ; RV64I-NEXT: slli s3, s3, 24 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or t0, t6, t5 -; RV64I-NEXT: or t1, s1, s0 -; RV64I-NEXT: or t2, s3, s2 +; RV64I-NEXT: add a7, a7, t3 +; RV64I-NEXT: add t0, t6, t0 +; RV64I-NEXT: add t1, t1, s0 +; RV64I-NEXT: add t2, s3, t2 ; RV64I-NEXT: lbu t6, 24(a0) ; RV64I-NEXT: lbu s0, 25(a0) ; RV64I-NEXT: lbu s1, 26(a0) ; RV64I-NEXT: lbu s2, 27(a0) -; RV64I-NEXT: slli s5, s5, 8 -; RV64I-NEXT: slli s6, s6, 16 +; RV64I-NEXT: slli t3, s5, 8 +; RV64I-NEXT: slli t4, s6, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: slli s9, s9, 8 -; RV64I-NEXT: or t3, s5, s4 -; RV64I-NEXT: or t4, s7, s6 -; RV64I-NEXT: or t5, s9, s8 +; RV64I-NEXT: slli t5, s9, 8 +; RV64I-NEXT: add t3, t3, s4 +; RV64I-NEXT: add t4, s7, t4 +; RV64I-NEXT: add t5, t5, s8 ; RV64I-NEXT: lbu s3, 28(a0) ; RV64I-NEXT: lbu s4, 29(a0) ; RV64I-NEXT: lbu s5, 30(a0) ; RV64I-NEXT: lbu s6, 31(a0) -; RV64I-NEXT: slli s10, s10, 16 +; RV64I-NEXT: slli a0, s10, 16 ; RV64I-NEXT: slli s11, s11, 24 ; RV64I-NEXT: slli s0, s0, 8 ; RV64I-NEXT: slli s1, s1, 16 ; RV64I-NEXT: slli s2, s2, 24 ; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or a0, s11, s10 -; RV64I-NEXT: or t6, s0, t6 -; RV64I-NEXT: or s0, s2, s1 -; RV64I-NEXT: or s1, s4, s3 +; RV64I-NEXT: add a0, s11, a0 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s0, s2, s1 +; RV64I-NEXT: add s1, s4, s3 ; RV64I-NEXT: lbu s2, 0(a1) ; RV64I-NEXT: lbu s3, 1(a1) ; RV64I-NEXT: lbu s4, 2(a1) @@ -2541,47 +2541,47 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV64I-NEXT: slli s3, s3, 8 ; RV64I-NEXT: slli s4, s4, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: or s5, s6, s5 -; RV64I-NEXT: or s2, s3, s2 -; RV64I-NEXT: or s3, s7, s4 -; RV64I-NEXT: lbu s4, 5(a1) +; RV64I-NEXT: add s5, s6, s5 +; RV64I-NEXT: add s2, s3, s2 +; RV64I-NEXT: add s4, s7, s4 +; RV64I-NEXT: lbu s3, 5(a1) ; RV64I-NEXT: lbu s6, 4(a1) ; RV64I-NEXT: lbu s7, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or s4, s4, s6 +; RV64I-NEXT: slli s3, s3, 8 +; RV64I-NEXT: add s3, s3, s6 ; RV64I-NEXT: sd zero, 32(sp) ; RV64I-NEXT: sd zero, 40(sp) ; RV64I-NEXT: sd zero, 48(sp) ; RV64I-NEXT: sd zero, 56(sp) ; RV64I-NEXT: slli s7, s7, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, s7 +; RV64I-NEXT: add a1, a1, s7 ; RV64I-NEXT: mv s6, sp -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or a0, a0, t5 -; RV64I-NEXT: or t0, s0, t6 -; RV64I-NEXT: or t1, s5, s1 -; RV64I-NEXT: or t2, s3, s2 -; RV64I-NEXT: or a1, a1, s4 -; RV64I-NEXT: slli a4, a4, 32 -; RV64I-NEXT: slli a6, a6, 32 -; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add t3, t4, t3 +; RV64I-NEXT: add a0, a0, t5 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s1, s5, s1 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add a1, a1, s3 +; RV64I-NEXT: slli a5, a5, 32 ; RV64I-NEXT: slli t1, t1, 32 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: slli s1, s1, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a0, a0, a7 -; RV64I-NEXT: or a5, t1, t0 -; RV64I-NEXT: or a1, a1, t2 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a0, a0, t3 +; RV64I-NEXT: add t6, s1, t6 +; RV64I-NEXT: add a1, a1, s2 ; RV64I-NEXT: sd a3, 0(sp) -; RV64I-NEXT: sd a4, 8(sp) +; RV64I-NEXT: sd a7, 8(sp) ; RV64I-NEXT: sd a0, 16(sp) -; RV64I-NEXT: sd a5, 24(sp) +; RV64I-NEXT: sd t6, 24(sp) ; RV64I-NEXT: slli a3, a1, 5 ; RV64I-NEXT: slli a1, a1, 2 ; RV64I-NEXT: andi a1, a1, 24 @@ -2724,9 +2724,9 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli s1, s1, 24 ; RV32I-NEXT: slli s8, s8, 8 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, s1, t1 -; RV32I-NEXT: or t1, s8, s7 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t0, s1, t1 +; RV32I-NEXT: add t1, s8, s7 ; RV32I-NEXT: lbu s1, 24(a0) ; RV32I-NEXT: lbu s7, 25(a0) ; RV32I-NEXT: lbu s8, 26(a0) @@ -2736,9 +2736,9 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: slli s10, s10, 8 ; RV32I-NEXT: slli s11, s11, 16 ; RV32I-NEXT: slli ra, ra, 24 -; RV32I-NEXT: or s4, s6, s4 -; RV32I-NEXT: or s5, s10, s5 -; RV32I-NEXT: or s6, ra, s11 +; RV32I-NEXT: add s4, s6, s4 +; RV32I-NEXT: add s5, s10, s5 +; RV32I-NEXT: add s6, ra, s11 ; RV32I-NEXT: lbu s10, 28(a0) ; RV32I-NEXT: lbu s11, 29(a0) ; RV32I-NEXT: lbu ra, 30(a0) @@ -2753,7 +2753,7 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: sw zero, 48(sp) ; RV32I-NEXT: sw zero, 52(sp) ; RV32I-NEXT: slli t6, t6, 8 -; RV32I-NEXT: or t4, t6, t4 +; RV32I-NEXT: add t4, t6, t4 ; RV32I-NEXT: addi t6, sp, 8 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 @@ -2770,32 +2770,32 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: slli ra, ra, 16 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 2 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a3, t2, a3 -; RV32I-NEXT: or a6, t5, t3 -; RV32I-NEXT: or a4, s0, a4 -; RV32I-NEXT: or t2, s3, s2 -; RV32I-NEXT: or t3, s7, s1 -; RV32I-NEXT: or t5, s9, s8 -; RV32I-NEXT: or s0, s11, s10 -; RV32I-NEXT: or a0, a0, ra +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a3, t2, a3 +; RV32I-NEXT: add t3, t5, t3 +; RV32I-NEXT: add a4, s0, a4 +; RV32I-NEXT: add s2, s3, s2 +; RV32I-NEXT: add s1, s7, s1 +; RV32I-NEXT: add s8, s9, s8 +; RV32I-NEXT: add s10, s11, s10 +; RV32I-NEXT: add a0, a0, ra ; RV32I-NEXT: andi a1, a1, 28 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, s4, t1 -; RV32I-NEXT: or t1, s6, s5 -; RV32I-NEXT: or a5, a5, t4 -; RV32I-NEXT: or a3, a6, a3 -; RV32I-NEXT: or a4, t2, a4 -; RV32I-NEXT: or a6, t5, t3 -; RV32I-NEXT: or a0, a0, s0 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, s4, t1 +; RV32I-NEXT: add s5, s6, s5 +; RV32I-NEXT: add a5, a5, t4 +; RV32I-NEXT: add a3, t3, a3 +; RV32I-NEXT: add a4, s2, a4 +; RV32I-NEXT: add s1, s8, s1 +; RV32I-NEXT: add a0, a0, s10 ; RV32I-NEXT: add t6, t6, a1 ; RV32I-NEXT: sw a3, 24(sp) ; RV32I-NEXT: sw a4, 28(sp) -; RV32I-NEXT: sw a6, 32(sp) +; RV32I-NEXT: sw s1, 32(sp) ; RV32I-NEXT: sw a0, 36(sp) ; RV32I-NEXT: sw a7, 8(sp) -; RV32I-NEXT: sw t0, 12(sp) -; RV32I-NEXT: sw t1, 16(sp) +; RV32I-NEXT: sw t1, 12(sp) +; RV32I-NEXT: sw s5, 16(sp) ; RV32I-NEXT: sw a5, 20(sp) ; RV32I-NEXT: lw a1, 0(t6) ; RV32I-NEXT: lw a0, 4(t6) @@ -2930,10 +2930,10 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV64I-NEXT: slli s8, s8, 8 ; RV64I-NEXT: slli s9, s9, 16 ; RV64I-NEXT: slli s10, s10, 24 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: or a7, s3, t2 -; RV64I-NEXT: or t0, s8, t0 -; RV64I-NEXT: or t2, s10, s9 +; RV64I-NEXT: add a5, a7, a5 +; RV64I-NEXT: add a7, s3, t2 +; RV64I-NEXT: add t0, s8, t0 +; RV64I-NEXT: add t2, s10, s9 ; RV64I-NEXT: lbu s3, 24(a0) ; RV64I-NEXT: lbu s8, 25(a0) ; RV64I-NEXT: lbu s9, 26(a0) @@ -2942,9 +2942,9 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV64I-NEXT: slli s5, s5, 16 ; RV64I-NEXT: slli s6, s6, 24 ; RV64I-NEXT: slli s11, s11, 8 -; RV64I-NEXT: or s2, s4, s2 -; RV64I-NEXT: or s4, s6, s5 -; RV64I-NEXT: or s5, s11, s7 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add s4, s6, s5 +; RV64I-NEXT: add s5, s11, s7 ; RV64I-NEXT: lbu s6, 28(a0) ; RV64I-NEXT: lbu s7, 29(a0) ; RV64I-NEXT: lbu s11, 30(a0) @@ -2956,7 +2956,7 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV64I-NEXT: sd zero, 56(sp) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t3, t1 +; RV64I-NEXT: add t1, t3, t1 ; RV64I-NEXT: mv t3, sp ; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t4, t4, 16 @@ -2971,34 +2971,34 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV64I-NEXT: slli s11, s11, 16 ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: or a3, a6, a3 -; RV64I-NEXT: or a6, t5, t4 -; RV64I-NEXT: or a4, t6, a4 -; RV64I-NEXT: or s0, s1, s0 -; RV64I-NEXT: or t4, s8, s3 -; RV64I-NEXT: or t5, s10, s9 -; RV64I-NEXT: or t6, s7, s6 -; RV64I-NEXT: or a0, a0, s11 +; RV64I-NEXT: add a3, a6, a3 +; RV64I-NEXT: add t4, t5, t4 +; RV64I-NEXT: add a4, t6, a4 +; RV64I-NEXT: add s0, s1, s0 +; RV64I-NEXT: add s3, s8, s3 +; RV64I-NEXT: add s9, s10, s9 +; RV64I-NEXT: add s6, s7, s6 +; RV64I-NEXT: add a0, a0, s11 ; RV64I-NEXT: andi a1, a1, 24 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: or a7, t2, t0 -; RV64I-NEXT: or t0, s4, s2 -; RV64I-NEXT: or t1, t1, s5 -; RV64I-NEXT: or a3, a6, a3 -; RV64I-NEXT: or a4, s0, a4 -; RV64I-NEXT: or a6, t5, t4 -; RV64I-NEXT: or a0, a0, t6 +; RV64I-NEXT: add a5, a7, a5 +; RV64I-NEXT: add t0, t2, t0 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add t1, t1, s5 +; RV64I-NEXT: add a3, t4, a3 +; RV64I-NEXT: add a4, s0, a4 +; RV64I-NEXT: add s3, s9, s3 +; RV64I-NEXT: add a0, a0, s6 ; RV64I-NEXT: add t3, t3, a1 -; RV64I-NEXT: slli a7, a7, 32 +; RV64I-NEXT: slli t0, t0, 32 ; RV64I-NEXT: slli t1, t1, 32 ; RV64I-NEXT: slli a4, a4, 32 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a1, a7, a5 -; RV64I-NEXT: or a5, t1, t0 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a0, a0, a6 -; RV64I-NEXT: sd a1, 0(sp) -; RV64I-NEXT: sd a5, 8(sp) +; RV64I-NEXT: add a5, t0, a5 +; RV64I-NEXT: add t1, t1, s2 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a0, a0, s3 +; RV64I-NEXT: sd a5, 0(sp) +; RV64I-NEXT: sd t1, 8(sp) ; RV64I-NEXT: sd a3, 16(sp) ; RV64I-NEXT: sd a0, 24(sp) ; RV64I-NEXT: ld a4, 16(t3) @@ -3124,9 +3124,9 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli s1, s1, 24 ; RV32I-NEXT: slli s8, s8, 8 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, s1, t1 -; RV32I-NEXT: or t1, s8, s7 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t0, s1, t1 +; RV32I-NEXT: add t1, s8, s7 ; RV32I-NEXT: lbu s1, 24(a0) ; RV32I-NEXT: lbu s7, 25(a0) ; RV32I-NEXT: lbu s8, 26(a0) @@ -3136,9 +3136,9 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV32I-NEXT: slli s10, s10, 8 ; RV32I-NEXT: slli s11, s11, 16 ; RV32I-NEXT: slli ra, ra, 24 -; RV32I-NEXT: or s4, s6, s4 -; RV32I-NEXT: or s5, s10, s5 -; RV32I-NEXT: or s6, ra, s11 +; RV32I-NEXT: add s4, s6, s4 +; RV32I-NEXT: add s5, s10, s5 +; RV32I-NEXT: add s6, ra, s11 ; RV32I-NEXT: lbu s10, 28(a0) ; RV32I-NEXT: lbu s11, 29(a0) ; RV32I-NEXT: lbu ra, 30(a0) @@ -3153,7 +3153,7 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV32I-NEXT: sw zero, 48(sp) ; RV32I-NEXT: sw zero, 52(sp) ; RV32I-NEXT: slli t6, t6, 8 -; RV32I-NEXT: or t4, t6, t4 +; RV32I-NEXT: add t4, t6, t4 ; RV32I-NEXT: addi t6, sp, 8 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 @@ -3170,32 +3170,32 @@ define void @lshr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV32I-NEXT: slli ra, ra, 16 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 3 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a3, t2, a3 -; RV32I-NEXT: or a6, t5, t3 -; RV32I-NEXT: or a4, s0, a4 -; RV32I-NEXT: or t2, s3, s2 -; RV32I-NEXT: or t3, s7, s1 -; RV32I-NEXT: or t5, s9, s8 -; RV32I-NEXT: or s0, s11, s10 -; RV32I-NEXT: or a0, a0, ra +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a3, t2, a3 +; RV32I-NEXT: add t3, t5, t3 +; RV32I-NEXT: add a4, s0, a4 +; RV32I-NEXT: add s2, s3, s2 +; RV32I-NEXT: add s1, s7, s1 +; RV32I-NEXT: add s8, s9, s8 +; RV32I-NEXT: add s10, s11, s10 +; RV32I-NEXT: add a0, a0, ra ; RV32I-NEXT: andi a1, a1, 24 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, s4, t1 -; RV32I-NEXT: or t1, s6, s5 -; RV32I-NEXT: or a5, a5, t4 -; RV32I-NEXT: or a3, a6, a3 -; RV32I-NEXT: or a4, t2, a4 -; RV32I-NEXT: or a6, t5, t3 -; RV32I-NEXT: or a0, a0, s0 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, s4, t1 +; RV32I-NEXT: add s5, s6, s5 +; RV32I-NEXT: add a5, a5, t4 +; RV32I-NEXT: add a3, t3, a3 +; RV32I-NEXT: add a4, s2, a4 +; RV32I-NEXT: add s1, s8, s1 +; RV32I-NEXT: add a0, a0, s10 ; RV32I-NEXT: add t6, t6, a1 ; RV32I-NEXT: sw a3, 24(sp) ; RV32I-NEXT: sw a4, 28(sp) -; RV32I-NEXT: sw a6, 32(sp) +; RV32I-NEXT: sw s1, 32(sp) ; RV32I-NEXT: sw a0, 36(sp) ; RV32I-NEXT: sw a7, 8(sp) -; RV32I-NEXT: sw t0, 12(sp) -; RV32I-NEXT: sw t1, 16(sp) +; RV32I-NEXT: sw t1, 12(sp) +; RV32I-NEXT: sw s5, 16(sp) ; RV32I-NEXT: sw a5, 20(sp) ; RV32I-NEXT: lw a1, 0(t6) ; RV32I-NEXT: lw a0, 4(t6) @@ -3326,49 +3326,49 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli t0, t0, 8 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a4, a6, a5 +; RV64I-NEXT: add a5, t0, a7 +; RV64I-NEXT: add a6, t2, t1 ; RV64I-NEXT: lbu s8, 20(a0) ; RV64I-NEXT: lbu s9, 21(a0) ; RV64I-NEXT: lbu s10, 22(a0) ; RV64I-NEXT: lbu s11, 23(a0) -; RV64I-NEXT: slli t4, t4, 8 -; RV64I-NEXT: slli t5, t5, 16 +; RV64I-NEXT: slli a7, t4, 8 +; RV64I-NEXT: slli t0, t5, 16 ; RV64I-NEXT: slli t6, t6, 24 -; RV64I-NEXT: slli s1, s1, 8 -; RV64I-NEXT: slli s2, s2, 16 +; RV64I-NEXT: slli t1, s1, 8 +; RV64I-NEXT: slli t2, s2, 16 ; RV64I-NEXT: slli s3, s3, 24 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or t0, t6, t5 -; RV64I-NEXT: or t1, s1, s0 -; RV64I-NEXT: or t2, s3, s2 +; RV64I-NEXT: add a7, a7, t3 +; RV64I-NEXT: add t0, t6, t0 +; RV64I-NEXT: add t1, t1, s0 +; RV64I-NEXT: add t2, s3, t2 ; RV64I-NEXT: lbu t6, 24(a0) ; RV64I-NEXT: lbu s0, 25(a0) ; RV64I-NEXT: lbu s1, 26(a0) ; RV64I-NEXT: lbu s2, 27(a0) -; RV64I-NEXT: slli s5, s5, 8 -; RV64I-NEXT: slli s6, s6, 16 +; RV64I-NEXT: slli t3, s5, 8 +; RV64I-NEXT: slli t4, s6, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: slli s9, s9, 8 -; RV64I-NEXT: or t3, s5, s4 -; RV64I-NEXT: or t4, s7, s6 -; RV64I-NEXT: or t5, s9, s8 +; RV64I-NEXT: slli t5, s9, 8 +; RV64I-NEXT: add t3, t3, s4 +; RV64I-NEXT: add t4, s7, t4 +; RV64I-NEXT: add t5, t5, s8 ; RV64I-NEXT: lbu s3, 28(a0) ; RV64I-NEXT: lbu s4, 29(a0) ; RV64I-NEXT: lbu s5, 30(a0) ; RV64I-NEXT: lbu s6, 31(a0) -; RV64I-NEXT: slli s10, s10, 16 +; RV64I-NEXT: slli a0, s10, 16 ; RV64I-NEXT: slli s11, s11, 24 ; RV64I-NEXT: slli s0, s0, 8 ; RV64I-NEXT: slli s1, s1, 16 ; RV64I-NEXT: slli s2, s2, 24 ; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or a0, s11, s10 -; RV64I-NEXT: or t6, s0, t6 -; RV64I-NEXT: or s0, s2, s1 -; RV64I-NEXT: or s1, s4, s3 +; RV64I-NEXT: add a0, s11, a0 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s0, s2, s1 +; RV64I-NEXT: add s1, s4, s3 ; RV64I-NEXT: lbu s2, 0(a1) ; RV64I-NEXT: lbu s3, 1(a1) ; RV64I-NEXT: lbu s4, 2(a1) @@ -3378,47 +3378,47 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli s3, s3, 8 ; RV64I-NEXT: slli s4, s4, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: or s5, s6, s5 -; RV64I-NEXT: or s2, s3, s2 -; RV64I-NEXT: or s3, s7, s4 -; RV64I-NEXT: lbu s4, 5(a1) +; RV64I-NEXT: add s5, s6, s5 +; RV64I-NEXT: add s2, s3, s2 +; RV64I-NEXT: add s4, s7, s4 +; RV64I-NEXT: lbu s3, 5(a1) ; RV64I-NEXT: lbu s6, 4(a1) ; RV64I-NEXT: lbu s7, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or s4, s4, s6 +; RV64I-NEXT: slli s3, s3, 8 +; RV64I-NEXT: add s3, s3, s6 ; RV64I-NEXT: sd zero, 0(sp) ; RV64I-NEXT: sd zero, 8(sp) ; RV64I-NEXT: sd zero, 16(sp) ; RV64I-NEXT: sd zero, 24(sp) ; RV64I-NEXT: slli s7, s7, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, s7 +; RV64I-NEXT: add a1, a1, s7 ; RV64I-NEXT: addi s6, sp, 32 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or a0, a0, t5 -; RV64I-NEXT: or t0, s0, t6 -; RV64I-NEXT: or t1, s5, s1 -; RV64I-NEXT: or t2, s3, s2 -; RV64I-NEXT: or a1, a1, s4 -; RV64I-NEXT: slli a4, a4, 32 -; RV64I-NEXT: slli a6, a6, 32 -; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add t3, t4, t3 +; RV64I-NEXT: add a0, a0, t5 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s1, s5, s1 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add a1, a1, s3 +; RV64I-NEXT: slli a5, a5, 32 ; RV64I-NEXT: slli t1, t1, 32 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: slli s1, s1, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a0, a0, a7 -; RV64I-NEXT: or a5, t1, t0 -; RV64I-NEXT: or a1, a1, t2 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a0, a0, t3 +; RV64I-NEXT: add t6, s1, t6 +; RV64I-NEXT: add a1, a1, s2 ; RV64I-NEXT: sd a3, 32(sp) -; RV64I-NEXT: sd a4, 40(sp) +; RV64I-NEXT: sd a7, 40(sp) ; RV64I-NEXT: sd a0, 48(sp) -; RV64I-NEXT: sd a5, 56(sp) +; RV64I-NEXT: sd t6, 56(sp) ; RV64I-NEXT: slli a0, a1, 3 ; RV64I-NEXT: andi a1, a1, 24 ; RV64I-NEXT: sub a1, s6, a1 @@ -3562,34 +3562,34 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli t3, t3, 8 ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli s0, s0, 24 -; RV32I-NEXT: or a4, a4, s1 +; RV32I-NEXT: add a4, a4, s1 ; RV32I-NEXT: sw a4, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: or a4, a6, a5 -; RV32I-NEXT: or a5, t3, t1 -; RV32I-NEXT: or a6, s0, t4 +; RV32I-NEXT: add a4, a6, a5 +; RV32I-NEXT: add a5, t3, t1 +; RV32I-NEXT: add a6, s0, t4 ; RV32I-NEXT: lbu t1, 24(a0) ; RV32I-NEXT: lbu s0, 25(a0) ; RV32I-NEXT: lbu s1, 26(a0) ; RV32I-NEXT: lbu s2, 27(a0) ; RV32I-NEXT: slli s3, s3, 8 -; RV32I-NEXT: slli s6, s6, 16 +; RV32I-NEXT: slli t3, s6, 16 ; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: slli s10, s10, 8 -; RV32I-NEXT: or t2, s3, t2 -; RV32I-NEXT: or t3, s8, s6 -; RV32I-NEXT: or t4, s10, s9 +; RV32I-NEXT: slli t4, s10, 8 +; RV32I-NEXT: add t2, s3, t2 +; RV32I-NEXT: add t3, s8, t3 +; RV32I-NEXT: add t4, t4, s9 ; RV32I-NEXT: lbu s3, 28(a0) ; RV32I-NEXT: lbu s6, 29(a0) ; RV32I-NEXT: lbu s8, 30(a0) ; RV32I-NEXT: lbu s9, 31(a0) -; RV32I-NEXT: slli s4, s4, 16 +; RV32I-NEXT: slli a0, s4, 16 ; RV32I-NEXT: slli s7, s7, 24 -; RV32I-NEXT: slli s11, s11, 8 +; RV32I-NEXT: slli s4, s11, 8 ; RV32I-NEXT: slli ra, ra, 16 ; RV32I-NEXT: slli a3, a3, 24 -; RV32I-NEXT: or a0, s7, s4 -; RV32I-NEXT: or s4, s11, s5 -; RV32I-NEXT: or s5, a3, ra +; RV32I-NEXT: add a0, s7, a0 +; RV32I-NEXT: add s4, s4, s5 +; RV32I-NEXT: add s5, a3, ra ; RV32I-NEXT: lbu a3, 0(a1) ; RV32I-NEXT: lbu s7, 1(a1) ; RV32I-NEXT: lbu s10, 2(a1) @@ -3603,7 +3603,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sw zero, 16(sp) ; RV32I-NEXT: sw zero, 20(sp) ; RV32I-NEXT: slli t6, t6, 8 -; RV32I-NEXT: or t5, t6, t5 +; RV32I-NEXT: add t5, t6, t5 ; RV32I-NEXT: addi t6, sp, 40 ; RV32I-NEXT: slli a7, a7, 16 ; RV32I-NEXT: slli t0, t0, 24 @@ -3616,30 +3616,30 @@ define void @shl_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli s7, s7, 8 ; RV32I-NEXT: slli s10, s10, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, s0, t1 -; RV32I-NEXT: or t1, s2, s1 -; RV32I-NEXT: or s0, s6, s3 -; RV32I-NEXT: or s1, s9, s8 -; RV32I-NEXT: or a3, s7, a3 -; RV32I-NEXT: or a1, a1, s10 -; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, a4, s2 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a6, t3, t2 -; RV32I-NEXT: or a0, a0, t4 -; RV32I-NEXT: or t2, s5, s4 -; RV32I-NEXT: or a7, a7, t5 -; RV32I-NEXT: or t0, t1, t0 -; RV32I-NEXT: or s0, s1, s0 -; RV32I-NEXT: or a1, a1, a3 -; RV32I-NEXT: sw t2, 56(sp) +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, s0, t1 +; RV32I-NEXT: add s1, s2, s1 +; RV32I-NEXT: add s3, s6, s3 +; RV32I-NEXT: add s8, s9, s8 +; RV32I-NEXT: add a3, s7, a3 +; RV32I-NEXT: add a1, a1, s10 +; RV32I-NEXT: lw t0, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: add a4, a4, t0 +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add t2, t3, t2 +; RV32I-NEXT: add a0, a0, t4 +; RV32I-NEXT: add s4, s5, s4 +; RV32I-NEXT: add a7, a7, t5 +; RV32I-NEXT: add t1, s1, t1 +; RV32I-NEXT: add s3, s8, s3 +; RV32I-NEXT: add a1, a1, a3 +; RV32I-NEXT: sw s4, 56(sp) ; RV32I-NEXT: sw a7, 60(sp) -; RV32I-NEXT: sw t0, 64(sp) -; RV32I-NEXT: sw s0, 68(sp) +; RV32I-NEXT: sw t1, 64(sp) +; RV32I-NEXT: sw s3, 68(sp) ; RV32I-NEXT: sw a4, 40(sp) ; RV32I-NEXT: sw a5, 44(sp) -; RV32I-NEXT: sw a6, 48(sp) +; RV32I-NEXT: sw t2, 48(sp) ; RV32I-NEXT: sw a0, 52(sp) ; RV32I-NEXT: slli a3, a1, 3 ; RV32I-NEXT: andi a1, a1, 28 @@ -3804,49 +3804,49 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw ; RV64I-NEXT: slli t0, t0, 8 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a4, a6, a5 +; RV64I-NEXT: add a5, t0, a7 +; RV64I-NEXT: add a6, t2, t1 ; RV64I-NEXT: lbu s8, 20(a0) ; RV64I-NEXT: lbu s9, 21(a0) ; RV64I-NEXT: lbu s10, 22(a0) ; RV64I-NEXT: lbu s11, 23(a0) -; RV64I-NEXT: slli t4, t4, 8 -; RV64I-NEXT: slli t5, t5, 16 +; RV64I-NEXT: slli a7, t4, 8 +; RV64I-NEXT: slli t0, t5, 16 ; RV64I-NEXT: slli t6, t6, 24 -; RV64I-NEXT: slli s1, s1, 8 -; RV64I-NEXT: slli s2, s2, 16 +; RV64I-NEXT: slli t1, s1, 8 +; RV64I-NEXT: slli t2, s2, 16 ; RV64I-NEXT: slli s3, s3, 24 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or t0, t6, t5 -; RV64I-NEXT: or t1, s1, s0 -; RV64I-NEXT: or t2, s3, s2 +; RV64I-NEXT: add a7, a7, t3 +; RV64I-NEXT: add t0, t6, t0 +; RV64I-NEXT: add t1, t1, s0 +; RV64I-NEXT: add t2, s3, t2 ; RV64I-NEXT: lbu t6, 24(a0) ; RV64I-NEXT: lbu s0, 25(a0) ; RV64I-NEXT: lbu s1, 26(a0) ; RV64I-NEXT: lbu s2, 27(a0) -; RV64I-NEXT: slli s5, s5, 8 -; RV64I-NEXT: slli s6, s6, 16 +; RV64I-NEXT: slli t3, s5, 8 +; RV64I-NEXT: slli t4, s6, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: slli s9, s9, 8 -; RV64I-NEXT: or t3, s5, s4 -; RV64I-NEXT: or t4, s7, s6 -; RV64I-NEXT: or t5, s9, s8 +; RV64I-NEXT: slli t5, s9, 8 +; RV64I-NEXT: add t3, t3, s4 +; RV64I-NEXT: add t4, s7, t4 +; RV64I-NEXT: add t5, t5, s8 ; RV64I-NEXT: lbu s3, 28(a0) ; RV64I-NEXT: lbu s4, 29(a0) ; RV64I-NEXT: lbu s5, 30(a0) ; RV64I-NEXT: lbu s6, 31(a0) -; RV64I-NEXT: slli s10, s10, 16 +; RV64I-NEXT: slli a0, s10, 16 ; RV64I-NEXT: slli s11, s11, 24 ; RV64I-NEXT: slli s0, s0, 8 ; RV64I-NEXT: slli s1, s1, 16 ; RV64I-NEXT: slli s2, s2, 24 ; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or a0, s11, s10 -; RV64I-NEXT: or t6, s0, t6 -; RV64I-NEXT: or s0, s2, s1 -; RV64I-NEXT: or s1, s4, s3 +; RV64I-NEXT: add a0, s11, a0 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s0, s2, s1 +; RV64I-NEXT: add s1, s4, s3 ; RV64I-NEXT: lbu s2, 0(a1) ; RV64I-NEXT: lbu s3, 1(a1) ; RV64I-NEXT: lbu s4, 2(a1) @@ -3856,47 +3856,47 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw ; RV64I-NEXT: slli s3, s3, 8 ; RV64I-NEXT: slli s4, s4, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: or s5, s6, s5 -; RV64I-NEXT: or s2, s3, s2 -; RV64I-NEXT: or s3, s7, s4 -; RV64I-NEXT: lbu s4, 5(a1) +; RV64I-NEXT: add s5, s6, s5 +; RV64I-NEXT: add s2, s3, s2 +; RV64I-NEXT: add s4, s7, s4 +; RV64I-NEXT: lbu s3, 5(a1) ; RV64I-NEXT: lbu s6, 4(a1) ; RV64I-NEXT: lbu s7, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or s4, s4, s6 +; RV64I-NEXT: slli s3, s3, 8 +; RV64I-NEXT: add s3, s3, s6 ; RV64I-NEXT: sd zero, 0(sp) ; RV64I-NEXT: sd zero, 8(sp) ; RV64I-NEXT: sd zero, 16(sp) ; RV64I-NEXT: sd zero, 24(sp) ; RV64I-NEXT: slli s7, s7, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, s7 +; RV64I-NEXT: add a1, a1, s7 ; RV64I-NEXT: addi s6, sp, 32 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or a0, a0, t5 -; RV64I-NEXT: or t0, s0, t6 -; RV64I-NEXT: or t1, s5, s1 -; RV64I-NEXT: or t2, s3, s2 -; RV64I-NEXT: or a1, a1, s4 -; RV64I-NEXT: slli a4, a4, 32 -; RV64I-NEXT: slli a6, a6, 32 -; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add t3, t4, t3 +; RV64I-NEXT: add a0, a0, t5 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s1, s5, s1 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add a1, a1, s3 +; RV64I-NEXT: slli a5, a5, 32 ; RV64I-NEXT: slli t1, t1, 32 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: slli s1, s1, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a0, a0, a7 -; RV64I-NEXT: or a5, t1, t0 -; RV64I-NEXT: or a1, a1, t2 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a0, a0, t3 +; RV64I-NEXT: add t6, s1, t6 +; RV64I-NEXT: add a1, a1, s2 ; RV64I-NEXT: sd a3, 32(sp) -; RV64I-NEXT: sd a4, 40(sp) +; RV64I-NEXT: sd a7, 40(sp) ; RV64I-NEXT: sd a0, 48(sp) -; RV64I-NEXT: sd a5, 56(sp) +; RV64I-NEXT: sd t6, 56(sp) ; RV64I-NEXT: slli a3, a1, 5 ; RV64I-NEXT: slli a1, a1, 2 ; RV64I-NEXT: andi a1, a1, 24 @@ -4039,9 +4039,9 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli s1, s1, 24 ; RV32I-NEXT: slli s8, s8, 8 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, s1, t1 -; RV32I-NEXT: or t1, s8, s7 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t0, s1, t1 +; RV32I-NEXT: add t1, s8, s7 ; RV32I-NEXT: lbu s1, 24(a0) ; RV32I-NEXT: lbu s7, 25(a0) ; RV32I-NEXT: lbu s8, 26(a0) @@ -4051,9 +4051,9 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw ; RV32I-NEXT: slli s10, s10, 8 ; RV32I-NEXT: slli s11, s11, 16 ; RV32I-NEXT: slli ra, ra, 24 -; RV32I-NEXT: or s4, s6, s4 -; RV32I-NEXT: or s5, s10, s5 -; RV32I-NEXT: or s6, ra, s11 +; RV32I-NEXT: add s4, s6, s4 +; RV32I-NEXT: add s5, s10, s5 +; RV32I-NEXT: add s6, ra, s11 ; RV32I-NEXT: lbu s10, 28(a0) ; RV32I-NEXT: lbu s11, 29(a0) ; RV32I-NEXT: lbu ra, 30(a0) @@ -4068,7 +4068,7 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw ; RV32I-NEXT: sw zero, 16(sp) ; RV32I-NEXT: sw zero, 20(sp) ; RV32I-NEXT: slli t6, t6, 8 -; RV32I-NEXT: or t4, t6, t4 +; RV32I-NEXT: add t4, t6, t4 ; RV32I-NEXT: addi t6, sp, 40 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 @@ -4085,41 +4085,41 @@ define void @shl_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) nounw ; RV32I-NEXT: slli ra, ra, 16 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 2 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a3, t2, a3 -; RV32I-NEXT: or a6, t5, t3 -; RV32I-NEXT: or a4, s0, a4 -; RV32I-NEXT: or t2, s3, s2 -; RV32I-NEXT: or t3, s7, s1 -; RV32I-NEXT: or t5, s9, s8 -; RV32I-NEXT: or s0, s11, s10 -; RV32I-NEXT: or a0, a0, ra +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a3, t2, a3 +; RV32I-NEXT: add t3, t5, t3 +; RV32I-NEXT: add a4, s0, a4 +; RV32I-NEXT: add s2, s3, s2 +; RV32I-NEXT: add s1, s7, s1 +; RV32I-NEXT: add s8, s9, s8 +; RV32I-NEXT: add s10, s11, s10 +; RV32I-NEXT: add a0, a0, ra ; RV32I-NEXT: andi a1, a1, 28 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, s4, t1 -; RV32I-NEXT: or t1, s6, s5 -; RV32I-NEXT: or a5, a5, t4 -; RV32I-NEXT: or a3, a6, a3 -; RV32I-NEXT: or a4, t2, a4 -; RV32I-NEXT: or a6, t5, t3 -; RV32I-NEXT: or a0, a0, s0 -; RV32I-NEXT: sub t2, t6, a1 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, s4, t1 +; RV32I-NEXT: add s5, s6, s5 +; RV32I-NEXT: add a5, a5, t4 +; RV32I-NEXT: add a3, t3, a3 +; RV32I-NEXT: add a4, s2, a4 +; RV32I-NEXT: add s1, s8, s1 +; RV32I-NEXT: add a0, a0, s10 +; RV32I-NEXT: sub t0, t6, a1 ; RV32I-NEXT: sw a3, 56(sp) ; RV32I-NEXT: sw a4, 60(sp) -; RV32I-NEXT: sw a6, 64(sp) +; RV32I-NEXT: sw s1, 64(sp) ; RV32I-NEXT: sw a0, 68(sp) ; RV32I-NEXT: sw a7, 40(sp) -; RV32I-NEXT: sw t0, 44(sp) -; RV32I-NEXT: sw t1, 48(sp) +; RV32I-NEXT: sw t1, 44(sp) +; RV32I-NEXT: sw s5, 48(sp) ; RV32I-NEXT: sw a5, 52(sp) -; RV32I-NEXT: lw a1, 0(t2) -; RV32I-NEXT: lw a0, 4(t2) -; RV32I-NEXT: lw a4, 8(t2) -; RV32I-NEXT: lw a3, 12(t2) -; RV32I-NEXT: lw a7, 24(t2) -; RV32I-NEXT: lw a5, 20(t2) -; RV32I-NEXT: lw a6, 16(t2) -; RV32I-NEXT: lw t0, 28(t2) +; RV32I-NEXT: lw a1, 0(t0) +; RV32I-NEXT: lw a0, 4(t0) +; RV32I-NEXT: lw a4, 8(t0) +; RV32I-NEXT: lw a3, 12(t0) +; RV32I-NEXT: lw a7, 24(t0) +; RV32I-NEXT: lw a5, 20(t0) +; RV32I-NEXT: lw a6, 16(t0) +; RV32I-NEXT: lw t0, 28(t0) ; RV32I-NEXT: srli t1, a7, 24 ; RV32I-NEXT: srli t2, a7, 16 ; RV32I-NEXT: srli t3, a7, 8 @@ -4245,10 +4245,10 @@ define void @shl_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) nou ; RV64I-NEXT: slli s8, s8, 8 ; RV64I-NEXT: slli s9, s9, 16 ; RV64I-NEXT: slli s10, s10, 24 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: or a7, s3, t2 -; RV64I-NEXT: or t0, s8, t0 -; RV64I-NEXT: or t2, s10, s9 +; RV64I-NEXT: add a5, a7, a5 +; RV64I-NEXT: add a7, s3, t2 +; RV64I-NEXT: add t0, s8, t0 +; RV64I-NEXT: add t2, s10, s9 ; RV64I-NEXT: lbu s3, 24(a0) ; RV64I-NEXT: lbu s8, 25(a0) ; RV64I-NEXT: lbu s9, 26(a0) @@ -4257,9 +4257,9 @@ define void @shl_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) nou ; RV64I-NEXT: slli s5, s5, 16 ; RV64I-NEXT: slli s6, s6, 24 ; RV64I-NEXT: slli s11, s11, 8 -; RV64I-NEXT: or s2, s4, s2 -; RV64I-NEXT: or s4, s6, s5 -; RV64I-NEXT: or s5, s11, s7 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add s4, s6, s5 +; RV64I-NEXT: add s5, s11, s7 ; RV64I-NEXT: lbu s6, 28(a0) ; RV64I-NEXT: lbu s7, 29(a0) ; RV64I-NEXT: lbu s11, 30(a0) @@ -4271,7 +4271,7 @@ define void @shl_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) nou ; RV64I-NEXT: sd zero, 24(sp) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t3, t1 +; RV64I-NEXT: add t1, t3, t1 ; RV64I-NEXT: addi t3, sp, 32 ; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t4, t4, 16 @@ -4286,40 +4286,40 @@ define void @shl_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) nou ; RV64I-NEXT: slli s11, s11, 16 ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: or a3, a6, a3 -; RV64I-NEXT: or a6, t5, t4 -; RV64I-NEXT: or a4, t6, a4 -; RV64I-NEXT: or s0, s1, s0 -; RV64I-NEXT: or t4, s8, s3 -; RV64I-NEXT: or t5, s10, s9 -; RV64I-NEXT: or t6, s7, s6 -; RV64I-NEXT: or a0, a0, s11 +; RV64I-NEXT: add a3, a6, a3 +; RV64I-NEXT: add t4, t5, t4 +; RV64I-NEXT: add a4, t6, a4 +; RV64I-NEXT: add s0, s1, s0 +; RV64I-NEXT: add s3, s8, s3 +; RV64I-NEXT: add s9, s10, s9 +; RV64I-NEXT: add s6, s7, s6 +; RV64I-NEXT: add a0, a0, s11 ; RV64I-NEXT: andi a1, a1, 24 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: or a7, t2, t0 -; RV64I-NEXT: or t0, s4, s2 -; RV64I-NEXT: or t1, t1, s5 -; RV64I-NEXT: or a3, a6, a3 -; RV64I-NEXT: or a4, s0, a4 -; RV64I-NEXT: or a6, t5, t4 -; RV64I-NEXT: or a0, a0, t6 -; RV64I-NEXT: sub t2, t3, a1 -; RV64I-NEXT: slli a7, a7, 32 +; RV64I-NEXT: add a5, a7, a5 +; RV64I-NEXT: add t0, t2, t0 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add t1, t1, s5 +; RV64I-NEXT: add a3, t4, a3 +; RV64I-NEXT: add a4, s0, a4 +; RV64I-NEXT: add s3, s9, s3 +; RV64I-NEXT: add a0, a0, s6 +; RV64I-NEXT: sub a6, t3, a1 +; RV64I-NEXT: slli t0, t0, 32 ; RV64I-NEXT: slli t1, t1, 32 ; RV64I-NEXT: slli a4, a4, 32 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a1, a7, a5 -; RV64I-NEXT: or a5, t1, t0 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a0, a0, a6 -; RV64I-NEXT: sd a1, 32(sp) -; RV64I-NEXT: sd a5, 40(sp) +; RV64I-NEXT: add a5, t0, a5 +; RV64I-NEXT: add t1, t1, s2 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a0, a0, s3 +; RV64I-NEXT: sd a5, 32(sp) +; RV64I-NEXT: sd t1, 40(sp) ; RV64I-NEXT: sd a3, 48(sp) ; RV64I-NEXT: sd a0, 56(sp) -; RV64I-NEXT: ld a4, 16(t2) -; RV64I-NEXT: ld a0, 8(t2) -; RV64I-NEXT: ld a1, 0(t2) -; RV64I-NEXT: ld a3, 24(t2) +; RV64I-NEXT: ld a4, 16(a6) +; RV64I-NEXT: ld a0, 8(a6) +; RV64I-NEXT: ld a1, 0(a6) +; RV64I-NEXT: ld a3, 24(a6) ; RV64I-NEXT: srli a5, a4, 56 ; RV64I-NEXT: srli a6, a4, 48 ; RV64I-NEXT: srli a7, a4, 40 @@ -4439,9 +4439,9 @@ define void @shl_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) nou ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli s1, s1, 24 ; RV32I-NEXT: slli s8, s8, 8 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, s1, t1 -; RV32I-NEXT: or t1, s8, s7 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t0, s1, t1 +; RV32I-NEXT: add t1, s8, s7 ; RV32I-NEXT: lbu s1, 24(a0) ; RV32I-NEXT: lbu s7, 25(a0) ; RV32I-NEXT: lbu s8, 26(a0) @@ -4451,9 +4451,9 @@ define void @shl_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) nou ; RV32I-NEXT: slli s10, s10, 8 ; RV32I-NEXT: slli s11, s11, 16 ; RV32I-NEXT: slli ra, ra, 24 -; RV32I-NEXT: or s4, s6, s4 -; RV32I-NEXT: or s5, s10, s5 -; RV32I-NEXT: or s6, ra, s11 +; RV32I-NEXT: add s4, s6, s4 +; RV32I-NEXT: add s5, s10, s5 +; RV32I-NEXT: add s6, ra, s11 ; RV32I-NEXT: lbu s10, 28(a0) ; RV32I-NEXT: lbu s11, 29(a0) ; RV32I-NEXT: lbu ra, 30(a0) @@ -4468,7 +4468,7 @@ define void @shl_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) nou ; RV32I-NEXT: sw zero, 16(sp) ; RV32I-NEXT: sw zero, 20(sp) ; RV32I-NEXT: slli t6, t6, 8 -; RV32I-NEXT: or t4, t6, t4 +; RV32I-NEXT: add t4, t6, t4 ; RV32I-NEXT: addi t6, sp, 40 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 @@ -4485,41 +4485,41 @@ define void @shl_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) nou ; RV32I-NEXT: slli ra, ra, 16 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 3 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a3, t2, a3 -; RV32I-NEXT: or a6, t5, t3 -; RV32I-NEXT: or a4, s0, a4 -; RV32I-NEXT: or t2, s3, s2 -; RV32I-NEXT: or t3, s7, s1 -; RV32I-NEXT: or t5, s9, s8 -; RV32I-NEXT: or s0, s11, s10 -; RV32I-NEXT: or a0, a0, ra +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a3, t2, a3 +; RV32I-NEXT: add t3, t5, t3 +; RV32I-NEXT: add a4, s0, a4 +; RV32I-NEXT: add s2, s3, s2 +; RV32I-NEXT: add s1, s7, s1 +; RV32I-NEXT: add s8, s9, s8 +; RV32I-NEXT: add s10, s11, s10 +; RV32I-NEXT: add a0, a0, ra ; RV32I-NEXT: andi a1, a1, 24 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, s4, t1 -; RV32I-NEXT: or t1, s6, s5 -; RV32I-NEXT: or a5, a5, t4 -; RV32I-NEXT: or a3, a6, a3 -; RV32I-NEXT: or a4, t2, a4 -; RV32I-NEXT: or a6, t5, t3 -; RV32I-NEXT: or a0, a0, s0 -; RV32I-NEXT: sub t2, t6, a1 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, s4, t1 +; RV32I-NEXT: add s5, s6, s5 +; RV32I-NEXT: add a5, a5, t4 +; RV32I-NEXT: add a3, t3, a3 +; RV32I-NEXT: add a4, s2, a4 +; RV32I-NEXT: add s1, s8, s1 +; RV32I-NEXT: add a0, a0, s10 +; RV32I-NEXT: sub t0, t6, a1 ; RV32I-NEXT: sw a3, 56(sp) ; RV32I-NEXT: sw a4, 60(sp) -; RV32I-NEXT: sw a6, 64(sp) +; RV32I-NEXT: sw s1, 64(sp) ; RV32I-NEXT: sw a0, 68(sp) ; RV32I-NEXT: sw a7, 40(sp) -; RV32I-NEXT: sw t0, 44(sp) -; RV32I-NEXT: sw t1, 48(sp) +; RV32I-NEXT: sw t1, 44(sp) +; RV32I-NEXT: sw s5, 48(sp) ; RV32I-NEXT: sw a5, 52(sp) -; RV32I-NEXT: lw a1, 0(t2) -; RV32I-NEXT: lw a0, 4(t2) -; RV32I-NEXT: lw a4, 8(t2) -; RV32I-NEXT: lw a3, 12(t2) -; RV32I-NEXT: lw a7, 24(t2) -; RV32I-NEXT: lw a5, 20(t2) -; RV32I-NEXT: lw a6, 16(t2) -; RV32I-NEXT: lw t0, 28(t2) +; RV32I-NEXT: lw a1, 0(t0) +; RV32I-NEXT: lw a0, 4(t0) +; RV32I-NEXT: lw a4, 8(t0) +; RV32I-NEXT: lw a3, 12(t0) +; RV32I-NEXT: lw a7, 24(t0) +; RV32I-NEXT: lw a5, 20(t0) +; RV32I-NEXT: lw a6, 16(t0) +; RV32I-NEXT: lw t0, 28(t0) ; RV32I-NEXT: srli t1, a7, 24 ; RV32I-NEXT: srli t2, a7, 16 ; RV32I-NEXT: srli t3, a7, 8 @@ -4641,49 +4641,49 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli t0, t0, 8 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a4, a6, a5 +; RV64I-NEXT: add a5, t0, a7 +; RV64I-NEXT: add a6, t2, t1 ; RV64I-NEXT: lbu s8, 20(a0) ; RV64I-NEXT: lbu s9, 21(a0) ; RV64I-NEXT: lbu s10, 22(a0) ; RV64I-NEXT: lbu s11, 23(a0) -; RV64I-NEXT: slli t4, t4, 8 -; RV64I-NEXT: slli t5, t5, 16 +; RV64I-NEXT: slli a7, t4, 8 +; RV64I-NEXT: slli t0, t5, 16 ; RV64I-NEXT: slli t6, t6, 24 -; RV64I-NEXT: slli s1, s1, 8 -; RV64I-NEXT: slli s2, s2, 16 +; RV64I-NEXT: slli t1, s1, 8 +; RV64I-NEXT: slli t2, s2, 16 ; RV64I-NEXT: slli s3, s3, 24 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or t0, t6, t5 -; RV64I-NEXT: or t1, s1, s0 -; RV64I-NEXT: or t2, s3, s2 +; RV64I-NEXT: add a7, a7, t3 +; RV64I-NEXT: add t0, t6, t0 +; RV64I-NEXT: add t1, t1, s0 +; RV64I-NEXT: add t2, s3, t2 ; RV64I-NEXT: lbu t6, 24(a0) ; RV64I-NEXT: lbu s0, 25(a0) ; RV64I-NEXT: lbu s1, 26(a0) ; RV64I-NEXT: lbu s2, 27(a0) -; RV64I-NEXT: slli s5, s5, 8 -; RV64I-NEXT: slli s6, s6, 16 +; RV64I-NEXT: slli t3, s5, 8 +; RV64I-NEXT: slli t4, s6, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: slli s9, s9, 8 -; RV64I-NEXT: or t3, s5, s4 -; RV64I-NEXT: or t4, s7, s6 -; RV64I-NEXT: or t5, s9, s8 +; RV64I-NEXT: slli t5, s9, 8 +; RV64I-NEXT: add t3, t3, s4 +; RV64I-NEXT: add t4, s7, t4 +; RV64I-NEXT: add t5, t5, s8 ; RV64I-NEXT: lbu s3, 28(a0) ; RV64I-NEXT: lbu s4, 29(a0) ; RV64I-NEXT: lbu s5, 30(a0) ; RV64I-NEXT: lbu s6, 31(a0) -; RV64I-NEXT: slli s10, s10, 16 +; RV64I-NEXT: slli a0, s10, 16 ; RV64I-NEXT: slli s11, s11, 24 ; RV64I-NEXT: slli s0, s0, 8 ; RV64I-NEXT: slli s1, s1, 16 ; RV64I-NEXT: slli s2, s2, 24 ; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or a0, s11, s10 -; RV64I-NEXT: or t6, s0, t6 -; RV64I-NEXT: or s0, s2, s1 -; RV64I-NEXT: or s1, s4, s3 +; RV64I-NEXT: add a0, s11, a0 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s0, s2, s1 +; RV64I-NEXT: add s1, s4, s3 ; RV64I-NEXT: lbu s2, 0(a1) ; RV64I-NEXT: lbu s3, 1(a1) ; RV64I-NEXT: lbu s4, 2(a1) @@ -4693,48 +4693,48 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli s3, s3, 8 ; RV64I-NEXT: slli s4, s4, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: or s5, s6, s5 -; RV64I-NEXT: or s2, s3, s2 -; RV64I-NEXT: or s3, s7, s4 -; RV64I-NEXT: lbu s4, 5(a1) +; RV64I-NEXT: add s5, s6, s5 +; RV64I-NEXT: add s2, s3, s2 +; RV64I-NEXT: add s4, s7, s4 +; RV64I-NEXT: lbu s3, 5(a1) ; RV64I-NEXT: lbu s6, 4(a1) ; RV64I-NEXT: lbu s7, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or s4, s4, s6 +; RV64I-NEXT: slli s3, s3, 8 +; RV64I-NEXT: add s3, s3, s6 ; RV64I-NEXT: slli s7, s7, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, s7 +; RV64I-NEXT: add a1, a1, s7 ; RV64I-NEXT: mv s6, sp -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or a0, a0, t5 -; RV64I-NEXT: or t0, s0, t6 -; RV64I-NEXT: or t1, s5, s1 -; RV64I-NEXT: or t2, s3, s2 -; RV64I-NEXT: or a1, a1, s4 -; RV64I-NEXT: slli a4, a4, 32 -; RV64I-NEXT: slli a6, a6, 32 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add t3, t4, t3 +; RV64I-NEXT: add a0, a0, t5 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s1, s5, s1 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add a1, a1, s3 +; RV64I-NEXT: slli a5, a5, 32 +; RV64I-NEXT: slli t1, t1, 32 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: slli t3, t1, 32 +; RV64I-NEXT: slli a4, s1, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: sraiw t1, t1, 31 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a0, a0, a7 -; RV64I-NEXT: or a5, t3, t0 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: sd t1, 32(sp) -; RV64I-NEXT: sd t1, 40(sp) -; RV64I-NEXT: sd t1, 48(sp) -; RV64I-NEXT: sd t1, 56(sp) +; RV64I-NEXT: sraiw a6, s1, 31 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a0, a0, t3 +; RV64I-NEXT: add a4, a4, t6 +; RV64I-NEXT: add a1, a1, s2 +; RV64I-NEXT: sd a6, 32(sp) +; RV64I-NEXT: sd a6, 40(sp) +; RV64I-NEXT: sd a6, 48(sp) +; RV64I-NEXT: sd a6, 56(sp) ; RV64I-NEXT: sd a3, 0(sp) -; RV64I-NEXT: sd a4, 8(sp) +; RV64I-NEXT: sd a7, 8(sp) ; RV64I-NEXT: sd a0, 16(sp) -; RV64I-NEXT: sd a5, 24(sp) +; RV64I-NEXT: sd a4, 24(sp) ; RV64I-NEXT: slli a4, a1, 3 ; RV64I-NEXT: andi a1, a1, 24 ; RV64I-NEXT: add a1, s6, a1 @@ -4878,40 +4878,40 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli t3, t3, 8 ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli t5, t5, 24 -; RV32I-NEXT: or a4, a4, t6 +; RV32I-NEXT: add a4, a4, t6 ; RV32I-NEXT: sw a4, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: or a4, a6, a5 -; RV32I-NEXT: or a5, t3, t1 -; RV32I-NEXT: or a6, t5, t4 +; RV32I-NEXT: add a4, a6, a5 +; RV32I-NEXT: add a5, t3, t1 +; RV32I-NEXT: add a6, t5, t4 ; RV32I-NEXT: lbu t1, 24(a0) ; RV32I-NEXT: lbu t5, 25(a0) ; RV32I-NEXT: lbu t6, 26(a0) ; RV32I-NEXT: lbu s0, 27(a0) ; RV32I-NEXT: slli s1, s1, 8 -; RV32I-NEXT: slli s7, s7, 16 +; RV32I-NEXT: slli t3, s7, 16 ; RV32I-NEXT: slli s8, s8, 24 -; RV32I-NEXT: slli s10, s10, 8 -; RV32I-NEXT: or t2, s1, t2 -; RV32I-NEXT: or t3, s8, s7 -; RV32I-NEXT: or t4, s10, s9 +; RV32I-NEXT: slli t4, s10, 8 +; RV32I-NEXT: add t2, s1, t2 +; RV32I-NEXT: add t3, s8, t3 +; RV32I-NEXT: add t4, t4, s9 ; RV32I-NEXT: lbu s1, 28(a0) ; RV32I-NEXT: lbu s7, 29(a0) ; RV32I-NEXT: lbu s8, 30(a0) ; RV32I-NEXT: lbu s9, 31(a0) -; RV32I-NEXT: slli s4, s4, 16 +; RV32I-NEXT: slli a0, s4, 16 ; RV32I-NEXT: slli s6, s6, 24 ; RV32I-NEXT: slli s11, s11, 8 -; RV32I-NEXT: slli ra, ra, 16 +; RV32I-NEXT: slli s4, ra, 16 ; RV32I-NEXT: slli a3, a3, 24 -; RV32I-NEXT: or a0, s6, s4 -; RV32I-NEXT: or s4, s11, s5 -; RV32I-NEXT: or s5, a3, ra +; RV32I-NEXT: add a0, s6, a0 +; RV32I-NEXT: add s5, s11, s5 +; RV32I-NEXT: add s4, a3, s4 ; RV32I-NEXT: lbu a3, 0(a1) ; RV32I-NEXT: lbu s6, 1(a1) ; RV32I-NEXT: lbu s10, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli s3, s3, 8 -; RV32I-NEXT: or s2, s3, s2 +; RV32I-NEXT: add s2, s3, s2 ; RV32I-NEXT: addi s3, sp, 8 ; RV32I-NEXT: slli a7, a7, 16 ; RV32I-NEXT: slli t0, t0, 24 @@ -4924,39 +4924,39 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli s6, s6, 8 ; RV32I-NEXT: slli s10, s10, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, t5, t1 -; RV32I-NEXT: or t1, s0, t6 -; RV32I-NEXT: or t5, s7, s1 -; RV32I-NEXT: or t6, s9, s8 -; RV32I-NEXT: or a3, s6, a3 -; RV32I-NEXT: or a1, a1, s10 -; RV32I-NEXT: srai s0, s9, 31 -; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, a4, s1 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a6, t3, t2 -; RV32I-NEXT: or a0, a0, t4 -; RV32I-NEXT: or t2, s5, s4 -; RV32I-NEXT: or a7, a7, s2 -; RV32I-NEXT: or t0, t1, t0 -; RV32I-NEXT: or t1, t6, t5 -; RV32I-NEXT: or a1, a1, a3 -; RV32I-NEXT: sw s0, 56(sp) -; RV32I-NEXT: sw s0, 60(sp) -; RV32I-NEXT: sw s0, 64(sp) -; RV32I-NEXT: sw s0, 68(sp) -; RV32I-NEXT: sw s0, 40(sp) -; RV32I-NEXT: sw s0, 44(sp) -; RV32I-NEXT: sw s0, 48(sp) -; RV32I-NEXT: sw s0, 52(sp) -; RV32I-NEXT: sw t2, 24(sp) +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, t5, t1 +; RV32I-NEXT: add t6, s0, t6 +; RV32I-NEXT: add s1, s7, s1 +; RV32I-NEXT: add s8, s9, s8 +; RV32I-NEXT: add a3, s6, a3 +; RV32I-NEXT: add a1, a1, s10 +; RV32I-NEXT: srai t0, s9, 31 +; RV32I-NEXT: lw t5, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: add a4, a4, t5 +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add t2, t3, t2 +; RV32I-NEXT: add a0, a0, t4 +; RV32I-NEXT: add s4, s4, s5 +; RV32I-NEXT: add a7, a7, s2 +; RV32I-NEXT: add t1, t6, t1 +; RV32I-NEXT: add s1, s8, s1 +; RV32I-NEXT: add a1, a1, a3 +; RV32I-NEXT: sw t0, 56(sp) +; RV32I-NEXT: sw t0, 60(sp) +; RV32I-NEXT: sw t0, 64(sp) +; RV32I-NEXT: sw t0, 68(sp) +; RV32I-NEXT: sw t0, 40(sp) +; RV32I-NEXT: sw t0, 44(sp) +; RV32I-NEXT: sw t0, 48(sp) +; RV32I-NEXT: sw t0, 52(sp) +; RV32I-NEXT: sw s4, 24(sp) ; RV32I-NEXT: sw a7, 28(sp) -; RV32I-NEXT: sw t0, 32(sp) -; RV32I-NEXT: sw t1, 36(sp) +; RV32I-NEXT: sw t1, 32(sp) +; RV32I-NEXT: sw s1, 36(sp) ; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a5, 12(sp) -; RV32I-NEXT: sw a6, 16(sp) +; RV32I-NEXT: sw t2, 16(sp) ; RV32I-NEXT: sw a0, 20(sp) ; RV32I-NEXT: slli t1, a1, 3 ; RV32I-NEXT: andi a1, a1, 28 @@ -5121,49 +5121,49 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV64I-NEXT: slli t0, t0, 8 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a4, a6, a5 +; RV64I-NEXT: add a5, t0, a7 +; RV64I-NEXT: add a6, t2, t1 ; RV64I-NEXT: lbu s8, 20(a0) ; RV64I-NEXT: lbu s9, 21(a0) ; RV64I-NEXT: lbu s10, 22(a0) ; RV64I-NEXT: lbu s11, 23(a0) -; RV64I-NEXT: slli t4, t4, 8 -; RV64I-NEXT: slli t5, t5, 16 +; RV64I-NEXT: slli a7, t4, 8 +; RV64I-NEXT: slli t0, t5, 16 ; RV64I-NEXT: slli t6, t6, 24 -; RV64I-NEXT: slli s1, s1, 8 -; RV64I-NEXT: slli s2, s2, 16 +; RV64I-NEXT: slli t1, s1, 8 +; RV64I-NEXT: slli t2, s2, 16 ; RV64I-NEXT: slli s3, s3, 24 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or t0, t6, t5 -; RV64I-NEXT: or t1, s1, s0 -; RV64I-NEXT: or t2, s3, s2 +; RV64I-NEXT: add a7, a7, t3 +; RV64I-NEXT: add t0, t6, t0 +; RV64I-NEXT: add t1, t1, s0 +; RV64I-NEXT: add t2, s3, t2 ; RV64I-NEXT: lbu t6, 24(a0) ; RV64I-NEXT: lbu s0, 25(a0) ; RV64I-NEXT: lbu s1, 26(a0) ; RV64I-NEXT: lbu s2, 27(a0) -; RV64I-NEXT: slli s5, s5, 8 -; RV64I-NEXT: slli s6, s6, 16 +; RV64I-NEXT: slli t3, s5, 8 +; RV64I-NEXT: slli t4, s6, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: slli s9, s9, 8 -; RV64I-NEXT: or t3, s5, s4 -; RV64I-NEXT: or t4, s7, s6 -; RV64I-NEXT: or t5, s9, s8 +; RV64I-NEXT: slli t5, s9, 8 +; RV64I-NEXT: add t3, t3, s4 +; RV64I-NEXT: add t4, s7, t4 +; RV64I-NEXT: add t5, t5, s8 ; RV64I-NEXT: lbu s3, 28(a0) ; RV64I-NEXT: lbu s4, 29(a0) ; RV64I-NEXT: lbu s5, 30(a0) ; RV64I-NEXT: lbu s6, 31(a0) -; RV64I-NEXT: slli s10, s10, 16 +; RV64I-NEXT: slli a0, s10, 16 ; RV64I-NEXT: slli s11, s11, 24 ; RV64I-NEXT: slli s0, s0, 8 ; RV64I-NEXT: slli s1, s1, 16 ; RV64I-NEXT: slli s2, s2, 24 ; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or a0, s11, s10 -; RV64I-NEXT: or t6, s0, t6 -; RV64I-NEXT: or s0, s2, s1 -; RV64I-NEXT: or s1, s4, s3 +; RV64I-NEXT: add a0, s11, a0 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s0, s2, s1 +; RV64I-NEXT: add s1, s4, s3 ; RV64I-NEXT: lbu s2, 0(a1) ; RV64I-NEXT: lbu s3, 1(a1) ; RV64I-NEXT: lbu s4, 2(a1) @@ -5173,48 +5173,48 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV64I-NEXT: slli s3, s3, 8 ; RV64I-NEXT: slli s4, s4, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: or s5, s6, s5 -; RV64I-NEXT: or s2, s3, s2 -; RV64I-NEXT: or s3, s7, s4 -; RV64I-NEXT: lbu s4, 5(a1) +; RV64I-NEXT: add s5, s6, s5 +; RV64I-NEXT: add s2, s3, s2 +; RV64I-NEXT: add s4, s7, s4 +; RV64I-NEXT: lbu s3, 5(a1) ; RV64I-NEXT: lbu s6, 4(a1) ; RV64I-NEXT: lbu s7, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or s4, s4, s6 +; RV64I-NEXT: slli s3, s3, 8 +; RV64I-NEXT: add s3, s3, s6 ; RV64I-NEXT: slli s7, s7, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, s7 +; RV64I-NEXT: add a1, a1, s7 ; RV64I-NEXT: mv s6, sp -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or a0, a0, t5 -; RV64I-NEXT: or t0, s0, t6 -; RV64I-NEXT: or t1, s5, s1 -; RV64I-NEXT: or t2, s3, s2 -; RV64I-NEXT: or a1, a1, s4 -; RV64I-NEXT: slli a4, a4, 32 -; RV64I-NEXT: slli a6, a6, 32 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add t3, t4, t3 +; RV64I-NEXT: add a0, a0, t5 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s1, s5, s1 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add a1, a1, s3 +; RV64I-NEXT: slli a5, a5, 32 +; RV64I-NEXT: slli t1, t1, 32 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: slli t3, t1, 32 +; RV64I-NEXT: slli a4, s1, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: sraiw t1, t1, 31 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a0, a0, a7 -; RV64I-NEXT: or a5, t3, t0 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: sd t1, 32(sp) -; RV64I-NEXT: sd t1, 40(sp) -; RV64I-NEXT: sd t1, 48(sp) -; RV64I-NEXT: sd t1, 56(sp) +; RV64I-NEXT: sraiw a6, s1, 31 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a0, a0, t3 +; RV64I-NEXT: add a4, a4, t6 +; RV64I-NEXT: add a1, a1, s2 +; RV64I-NEXT: sd a6, 32(sp) +; RV64I-NEXT: sd a6, 40(sp) +; RV64I-NEXT: sd a6, 48(sp) +; RV64I-NEXT: sd a6, 56(sp) ; RV64I-NEXT: sd a3, 0(sp) -; RV64I-NEXT: sd a4, 8(sp) +; RV64I-NEXT: sd a7, 8(sp) ; RV64I-NEXT: sd a0, 16(sp) -; RV64I-NEXT: sd a5, 24(sp) +; RV64I-NEXT: sd a4, 24(sp) ; RV64I-NEXT: slli a3, a1, 5 ; RV64I-NEXT: slli a1, a1, 2 ; RV64I-NEXT: andi a1, a1, 24 @@ -5357,9 +5357,9 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t6, t6, 24 ; RV32I-NEXT: slli s8, s8, 8 -; RV32I-NEXT: or a6, t0, a6 -; RV32I-NEXT: or t0, t6, t1 -; RV32I-NEXT: or t1, s8, s7 +; RV32I-NEXT: add a6, t0, a6 +; RV32I-NEXT: add t0, t6, t1 +; RV32I-NEXT: add t1, s8, s7 ; RV32I-NEXT: lbu t6, 24(a0) ; RV32I-NEXT: lbu s7, 25(a0) ; RV32I-NEXT: lbu s8, 26(a0) @@ -5369,16 +5369,16 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: slli s9, s9, 8 ; RV32I-NEXT: slli s10, s10, 16 ; RV32I-NEXT: slli s11, s11, 24 -; RV32I-NEXT: or s3, s5, s3 -; RV32I-NEXT: or s4, s9, s4 -; RV32I-NEXT: or s5, s11, s10 +; RV32I-NEXT: add s3, s5, s3 +; RV32I-NEXT: add s4, s9, s4 +; RV32I-NEXT: add s5, s11, s10 ; RV32I-NEXT: lbu s9, 28(a0) ; RV32I-NEXT: lbu s10, 29(a0) ; RV32I-NEXT: lbu s11, 30(a0) ; RV32I-NEXT: lbu a0, 31(a0) ; RV32I-NEXT: lbu a1, 0(a1) ; RV32I-NEXT: slli s6, s6, 8 -; RV32I-NEXT: or s2, s6, s2 +; RV32I-NEXT: add s2, s6, s2 ; RV32I-NEXT: addi s6, sp, 8 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a7, a7, 24 @@ -5395,25 +5395,25 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: slli s11, s11, 16 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 2 -; RV32I-NEXT: or a5, a7, a5 -; RV32I-NEXT: or a3, t2, a3 -; RV32I-NEXT: or a7, t4, t3 -; RV32I-NEXT: or a4, t5, a4 -; RV32I-NEXT: or s0, s1, s0 -; RV32I-NEXT: or t2, s7, t6 -; RV32I-NEXT: or t3, ra, s8 -; RV32I-NEXT: or t4, s10, s9 -; RV32I-NEXT: or t5, a0, s11 +; RV32I-NEXT: add a5, a7, a5 +; RV32I-NEXT: add a3, t2, a3 +; RV32I-NEXT: add t3, t4, t3 +; RV32I-NEXT: add a4, t5, a4 +; RV32I-NEXT: add s0, s1, s0 +; RV32I-NEXT: add t6, s7, t6 +; RV32I-NEXT: add s8, ra, s8 +; RV32I-NEXT: add s9, s10, s9 +; RV32I-NEXT: add s11, a0, s11 ; RV32I-NEXT: srai a0, a0, 31 ; RV32I-NEXT: andi a1, a1, 28 -; RV32I-NEXT: or a6, t0, a6 -; RV32I-NEXT: or t0, s3, t1 -; RV32I-NEXT: or t1, s5, s4 -; RV32I-NEXT: or a5, a5, s2 -; RV32I-NEXT: or a3, a7, a3 -; RV32I-NEXT: or a4, s0, a4 -; RV32I-NEXT: or a7, t3, t2 -; RV32I-NEXT: or t2, t5, t4 +; RV32I-NEXT: add a6, t0, a6 +; RV32I-NEXT: add t1, s3, t1 +; RV32I-NEXT: add s4, s5, s4 +; RV32I-NEXT: add a5, a5, s2 +; RV32I-NEXT: add a3, t3, a3 +; RV32I-NEXT: add a4, s0, a4 +; RV32I-NEXT: add t6, s8, t6 +; RV32I-NEXT: add s9, s11, s9 ; RV32I-NEXT: sw a0, 56(sp) ; RV32I-NEXT: sw a0, 60(sp) ; RV32I-NEXT: sw a0, 64(sp) @@ -5425,11 +5425,11 @@ define void @ashr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun ; RV32I-NEXT: add s6, s6, a1 ; RV32I-NEXT: sw a3, 24(sp) ; RV32I-NEXT: sw a4, 28(sp) -; RV32I-NEXT: sw a7, 32(sp) -; RV32I-NEXT: sw t2, 36(sp) +; RV32I-NEXT: sw t6, 32(sp) +; RV32I-NEXT: sw s9, 36(sp) ; RV32I-NEXT: sw a6, 8(sp) -; RV32I-NEXT: sw t0, 12(sp) -; RV32I-NEXT: sw t1, 16(sp) +; RV32I-NEXT: sw t1, 12(sp) +; RV32I-NEXT: sw s4, 16(sp) ; RV32I-NEXT: sw a5, 20(sp) ; RV32I-NEXT: lw a1, 0(s6) ; RV32I-NEXT: lw a0, 4(s6) @@ -5564,10 +5564,10 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV64I-NEXT: slli s8, s8, 8 ; RV64I-NEXT: slli s9, s9, 16 ; RV64I-NEXT: slli s10, s10, 24 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: or a7, s3, t1 -; RV64I-NEXT: or t0, s8, t0 -; RV64I-NEXT: or t1, s10, s9 +; RV64I-NEXT: add a5, a7, a5 +; RV64I-NEXT: add a7, s3, t1 +; RV64I-NEXT: add t0, s8, t0 +; RV64I-NEXT: add t1, s10, s9 ; RV64I-NEXT: lbu s3, 24(a0) ; RV64I-NEXT: lbu s8, 25(a0) ; RV64I-NEXT: lbu s9, 26(a0) @@ -5576,17 +5576,17 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV64I-NEXT: slli s5, s5, 16 ; RV64I-NEXT: slli s6, s6, 24 ; RV64I-NEXT: slli s11, s11, 8 -; RV64I-NEXT: or s2, s4, s2 -; RV64I-NEXT: or s4, s6, s5 -; RV64I-NEXT: or s5, s11, s7 -; RV64I-NEXT: lbu s6, 28(a0) -; RV64I-NEXT: lbu s7, 29(a0) +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add s4, s6, s5 +; RV64I-NEXT: add s7, s11, s7 +; RV64I-NEXT: lbu s5, 28(a0) +; RV64I-NEXT: lbu s6, 29(a0) ; RV64I-NEXT: lbu s11, 30(a0) ; RV64I-NEXT: lbu a0, 31(a0) ; RV64I-NEXT: lbu a1, 0(a1) ; RV64I-NEXT: slli t4, t4, 16 ; RV64I-NEXT: slli t5, t5, 24 -; RV64I-NEXT: or t4, t5, t4 +; RV64I-NEXT: add t4, t5, t4 ; RV64I-NEXT: mv t5, sp ; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t2, t2, 16 @@ -5597,43 +5597,43 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV64I-NEXT: slli s8, s8, 8 ; RV64I-NEXT: slli s9, s9, 16 ; RV64I-NEXT: slli s10, s10, 24 -; RV64I-NEXT: slli s7, s7, 8 +; RV64I-NEXT: slli s6, s6, 8 ; RV64I-NEXT: slli s11, s11, 16 ; RV64I-NEXT: slli a0, a0, 24 ; RV64I-NEXT: slli a1, a1, 3 -; RV64I-NEXT: or a3, a6, a3 -; RV64I-NEXT: or a6, t3, t2 -; RV64I-NEXT: or a4, t6, a4 -; RV64I-NEXT: or s0, s1, s0 -; RV64I-NEXT: or t2, s8, s3 -; RV64I-NEXT: or t3, s10, s9 -; RV64I-NEXT: or t6, s7, s6 -; RV64I-NEXT: or a0, a0, s11 +; RV64I-NEXT: add a3, a6, a3 +; RV64I-NEXT: add t2, t3, t2 +; RV64I-NEXT: add a4, t6, a4 +; RV64I-NEXT: add s0, s1, s0 +; RV64I-NEXT: add s3, s8, s3 +; RV64I-NEXT: add s9, s10, s9 +; RV64I-NEXT: add s5, s6, s5 +; RV64I-NEXT: add a0, a0, s11 ; RV64I-NEXT: andi a1, a1, 24 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: or a7, t1, t0 -; RV64I-NEXT: or t0, s4, s2 -; RV64I-NEXT: or t1, t4, s5 -; RV64I-NEXT: or a3, a6, a3 -; RV64I-NEXT: or a4, s0, a4 -; RV64I-NEXT: or a6, t3, t2 -; RV64I-NEXT: or a0, a0, t6 +; RV64I-NEXT: add a5, a7, a5 +; RV64I-NEXT: add t0, t1, t0 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add t4, t4, s7 +; RV64I-NEXT: add a3, t2, a3 +; RV64I-NEXT: add a4, s0, a4 +; RV64I-NEXT: add s3, s9, s3 +; RV64I-NEXT: add a0, a0, s5 ; RV64I-NEXT: add t5, t5, a1 -; RV64I-NEXT: slli a7, a7, 32 -; RV64I-NEXT: slli t1, t1, 32 +; RV64I-NEXT: slli t0, t0, 32 +; RV64I-NEXT: slli t4, t4, 32 ; RV64I-NEXT: slli a4, a4, 32 ; RV64I-NEXT: slli a1, a0, 32 ; RV64I-NEXT: sraiw a0, a0, 31 -; RV64I-NEXT: or a5, a7, a5 -; RV64I-NEXT: or a7, t1, t0 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a1, a1, a6 +; RV64I-NEXT: add a5, t0, a5 +; RV64I-NEXT: add t4, t4, s2 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a1, a1, s3 ; RV64I-NEXT: sd a0, 32(sp) ; RV64I-NEXT: sd a0, 40(sp) ; RV64I-NEXT: sd a0, 48(sp) ; RV64I-NEXT: sd a0, 56(sp) ; RV64I-NEXT: sd a5, 0(sp) -; RV64I-NEXT: sd a7, 8(sp) +; RV64I-NEXT: sd t4, 8(sp) ; RV64I-NEXT: sd a3, 16(sp) ; RV64I-NEXT: sd a1, 24(sp) ; RV64I-NEXT: ld a4, 16(t5) @@ -5759,9 +5759,9 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t6, t6, 24 ; RV32I-NEXT: slli s8, s8, 8 -; RV32I-NEXT: or a6, t0, a6 -; RV32I-NEXT: or t0, t6, t1 -; RV32I-NEXT: or t1, s8, s7 +; RV32I-NEXT: add a6, t0, a6 +; RV32I-NEXT: add t0, t6, t1 +; RV32I-NEXT: add t1, s8, s7 ; RV32I-NEXT: lbu t6, 24(a0) ; RV32I-NEXT: lbu s7, 25(a0) ; RV32I-NEXT: lbu s8, 26(a0) @@ -5771,16 +5771,16 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV32I-NEXT: slli s9, s9, 8 ; RV32I-NEXT: slli s10, s10, 16 ; RV32I-NEXT: slli s11, s11, 24 -; RV32I-NEXT: or s3, s5, s3 -; RV32I-NEXT: or s4, s9, s4 -; RV32I-NEXT: or s5, s11, s10 +; RV32I-NEXT: add s3, s5, s3 +; RV32I-NEXT: add s4, s9, s4 +; RV32I-NEXT: add s5, s11, s10 ; RV32I-NEXT: lbu s9, 28(a0) ; RV32I-NEXT: lbu s10, 29(a0) ; RV32I-NEXT: lbu s11, 30(a0) ; RV32I-NEXT: lbu a0, 31(a0) ; RV32I-NEXT: lbu a1, 0(a1) ; RV32I-NEXT: slli s6, s6, 8 -; RV32I-NEXT: or s2, s6, s2 +; RV32I-NEXT: add s2, s6, s2 ; RV32I-NEXT: addi s6, sp, 8 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a7, a7, 24 @@ -5797,25 +5797,25 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV32I-NEXT: slli s11, s11, 16 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 3 -; RV32I-NEXT: or a5, a7, a5 -; RV32I-NEXT: or a3, t2, a3 -; RV32I-NEXT: or a7, t4, t3 -; RV32I-NEXT: or a4, t5, a4 -; RV32I-NEXT: or s0, s1, s0 -; RV32I-NEXT: or t2, s7, t6 -; RV32I-NEXT: or t3, ra, s8 -; RV32I-NEXT: or t4, s10, s9 -; RV32I-NEXT: or t5, a0, s11 +; RV32I-NEXT: add a5, a7, a5 +; RV32I-NEXT: add a3, t2, a3 +; RV32I-NEXT: add t3, t4, t3 +; RV32I-NEXT: add a4, t5, a4 +; RV32I-NEXT: add s0, s1, s0 +; RV32I-NEXT: add t6, s7, t6 +; RV32I-NEXT: add s8, ra, s8 +; RV32I-NEXT: add s9, s10, s9 +; RV32I-NEXT: add s11, a0, s11 ; RV32I-NEXT: srai a0, a0, 31 ; RV32I-NEXT: andi a1, a1, 24 -; RV32I-NEXT: or a6, t0, a6 -; RV32I-NEXT: or t0, s3, t1 -; RV32I-NEXT: or t1, s5, s4 -; RV32I-NEXT: or a5, a5, s2 -; RV32I-NEXT: or a3, a7, a3 -; RV32I-NEXT: or a4, s0, a4 -; RV32I-NEXT: or a7, t3, t2 -; RV32I-NEXT: or t2, t5, t4 +; RV32I-NEXT: add a6, t0, a6 +; RV32I-NEXT: add t1, s3, t1 +; RV32I-NEXT: add s4, s5, s4 +; RV32I-NEXT: add a5, a5, s2 +; RV32I-NEXT: add a3, t3, a3 +; RV32I-NEXT: add a4, s0, a4 +; RV32I-NEXT: add t6, s8, t6 +; RV32I-NEXT: add s9, s11, s9 ; RV32I-NEXT: sw a0, 56(sp) ; RV32I-NEXT: sw a0, 60(sp) ; RV32I-NEXT: sw a0, 64(sp) @@ -5827,11 +5827,11 @@ define void @ashr_32bytes_dwordOff(ptr %src.ptr, ptr %dwordOff.ptr, ptr %dst) no ; RV32I-NEXT: add s6, s6, a1 ; RV32I-NEXT: sw a3, 24(sp) ; RV32I-NEXT: sw a4, 28(sp) -; RV32I-NEXT: sw a7, 32(sp) -; RV32I-NEXT: sw t2, 36(sp) +; RV32I-NEXT: sw t6, 32(sp) +; RV32I-NEXT: sw s9, 36(sp) ; RV32I-NEXT: sw a6, 8(sp) -; RV32I-NEXT: sw t0, 12(sp) -; RV32I-NEXT: sw t1, 16(sp) +; RV32I-NEXT: sw t1, 12(sp) +; RV32I-NEXT: sw s4, 16(sp) ; RV32I-NEXT: sw a5, 20(sp) ; RV32I-NEXT: lw a1, 0(s6) ; RV32I-NEXT: lw a0, 4(s6) diff --git a/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll b/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll index cd7f30d8f5898..3ab36202eed48 100644 --- a/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll +++ b/llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll @@ -10,12 +10,12 @@ define void @lshr_4bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: lbu a5, 2(a0) ; RV64I-NEXT: lb a0, 3(a0) ; RV64I-NEXT: slli a3, a3, 8 -; RV64I-NEXT: or a3, a3, a4 +; RV64I-NEXT: add a3, a3, a4 ; RV64I-NEXT: lbu a1, 0(a1) ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: add a0, a0, a5 +; RV64I-NEXT: add a0, a0, a3 ; RV64I-NEXT: srlw a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 16 ; RV64I-NEXT: srli a3, a0, 24 @@ -35,19 +35,19 @@ define void @lshr_4bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a5, a5, 24 -; RV32I-NEXT: or a0, a3, a0 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a0, a3, a0 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: lbu a3, 1(a1) ; RV32I-NEXT: lbu a5, 0(a1) ; RV32I-NEXT: lbu a6, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a5 +; RV32I-NEXT: add a3, a3, a5 ; RV32I-NEXT: slli a6, a6, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a6 -; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a6 +; RV32I-NEXT: add a0, a4, a0 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: srl a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: srli a3, a0, 24 @@ -71,12 +71,12 @@ define void @shl_4bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: lbu a5, 2(a0) ; RV64I-NEXT: lb a0, 3(a0) ; RV64I-NEXT: slli a3, a3, 8 -; RV64I-NEXT: or a3, a3, a4 +; RV64I-NEXT: add a3, a3, a4 ; RV64I-NEXT: lbu a1, 0(a1) ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: add a0, a0, a5 +; RV64I-NEXT: add a0, a0, a3 ; RV64I-NEXT: sllw a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 16 ; RV64I-NEXT: srli a3, a0, 24 @@ -96,19 +96,19 @@ define void @shl_4bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a5, a5, 24 -; RV32I-NEXT: or a0, a3, a0 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a0, a3, a0 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: lbu a3, 1(a1) ; RV32I-NEXT: lbu a5, 0(a1) ; RV32I-NEXT: lbu a6, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a5 +; RV32I-NEXT: add a3, a3, a5 ; RV32I-NEXT: slli a6, a6, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a6 -; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a6 +; RV32I-NEXT: add a0, a4, a0 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: sll a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: srli a3, a0, 24 @@ -132,12 +132,12 @@ define void @ashr_4bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: lbu a5, 2(a0) ; RV64I-NEXT: lb a0, 3(a0) ; RV64I-NEXT: slli a3, a3, 8 -; RV64I-NEXT: or a3, a3, a4 +; RV64I-NEXT: add a3, a3, a4 ; RV64I-NEXT: lbu a1, 0(a1) ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: add a0, a0, a5 +; RV64I-NEXT: add a0, a0, a3 ; RV64I-NEXT: sraw a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 16 ; RV64I-NEXT: srli a3, a0, 24 @@ -157,19 +157,19 @@ define void @ashr_4bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a5, a5, 24 -; RV32I-NEXT: or a0, a3, a0 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a0, a3, a0 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: lbu a3, 1(a1) ; RV32I-NEXT: lbu a5, 0(a1) ; RV32I-NEXT: lbu a6, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a5 +; RV32I-NEXT: add a3, a3, a5 ; RV32I-NEXT: slli a6, a6, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a6 -; RV32I-NEXT: or a0, a4, a0 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a6 +; RV32I-NEXT: add a0, a4, a0 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: sra a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 16 ; RV32I-NEXT: srli a3, a0, 24 @@ -201,38 +201,38 @@ define void @lshr_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 0(a1) -; RV64I-NEXT: lbu a7, 1(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 0(a1) +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t0, 2(a1) ; RV64I-NEXT: lbu t2, 3(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t2, t0 -; RV64I-NEXT: lbu t0, 5(a1) +; RV64I-NEXT: add a0, a0, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t2, t0 +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t1, 4(a1) ; RV64I-NEXT: lbu t2, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a4, a7, a6 -; RV64I-NEXT: or a1, a1, t0 +; RV64I-NEXT: add a1, a1, t2 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a0, a0, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a0, a0, a3 -; RV64I-NEXT: or a1, a1, a4 +; RV64I-NEXT: add a0, a0, a3 +; RV64I-NEXT: add a1, a1, a4 ; RV64I-NEXT: srl a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 48 ; RV64I-NEXT: srli a3, a0, 56 @@ -260,19 +260,19 @@ define void @lshr_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a5, a5, 24 -; RV32I-NEXT: or a3, a3, a6 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a3, a3, a6 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: lbu a5, 1(a1) ; RV32I-NEXT: lbu a6, 0(a1) ; RV32I-NEXT: lbu a7, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a5, a5, 8 -; RV32I-NEXT: or a6, a5, a6 +; RV32I-NEXT: add a6, a5, a6 ; RV32I-NEXT: slli a7, a7, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a7 -; RV32I-NEXT: or a5, a4, a3 -; RV32I-NEXT: or a4, a1, a6 +; RV32I-NEXT: add a1, a1, a7 +; RV32I-NEXT: add a5, a4, a3 +; RV32I-NEXT: add a4, a1, a6 ; RV32I-NEXT: addi a3, a4, -32 ; RV32I-NEXT: srl a1, a5, a4 ; RV32I-NEXT: bltz a3, .LBB3_2 @@ -285,13 +285,13 @@ define void @lshr_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu t0, 2(a0) ; RV32I-NEXT: lbu a0, 3(a0) ; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a6, a6, a7 +; RV32I-NEXT: add a6, a6, a7 ; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: add a0, a0, t0 ; RV32I-NEXT: not a7, a4 ; RV32I-NEXT: slli a5, a5, 1 -; RV32I-NEXT: or a0, a0, a6 +; RV32I-NEXT: add a0, a0, a6 ; RV32I-NEXT: srl a0, a0, a4 ; RV32I-NEXT: sll a4, a5, a7 ; RV32I-NEXT: or a0, a0, a4 @@ -334,38 +334,38 @@ define void @shl_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 0(a1) -; RV64I-NEXT: lbu a7, 1(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 0(a1) +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t0, 2(a1) ; RV64I-NEXT: lbu t2, 3(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t2, t0 -; RV64I-NEXT: lbu t0, 5(a1) +; RV64I-NEXT: add a0, a0, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t2, t0 +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t1, 4(a1) ; RV64I-NEXT: lbu t2, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a4, a7, a6 -; RV64I-NEXT: or a1, a1, t0 +; RV64I-NEXT: add a1, a1, t2 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a0, a0, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a0, a0, a3 -; RV64I-NEXT: or a1, a1, a4 +; RV64I-NEXT: add a0, a0, a3 +; RV64I-NEXT: add a1, a1, a4 ; RV64I-NEXT: sll a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 48 ; RV64I-NEXT: srli a3, a0, 56 @@ -393,19 +393,19 @@ define void @shl_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a3, a3, 8 ; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a5, a5, 24 -; RV32I-NEXT: or a3, a3, a6 -; RV32I-NEXT: or a4, a5, a4 +; RV32I-NEXT: add a3, a3, a6 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: lbu a5, 1(a1) ; RV32I-NEXT: lbu a6, 0(a1) ; RV32I-NEXT: lbu a7, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a5, a5, 8 -; RV32I-NEXT: or a6, a5, a6 +; RV32I-NEXT: add a6, a5, a6 ; RV32I-NEXT: slli a7, a7, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a7 -; RV32I-NEXT: or a5, a4, a3 -; RV32I-NEXT: or a4, a1, a6 +; RV32I-NEXT: add a1, a1, a7 +; RV32I-NEXT: add a5, a4, a3 +; RV32I-NEXT: add a4, a1, a6 ; RV32I-NEXT: addi a3, a4, -32 ; RV32I-NEXT: sll a1, a5, a4 ; RV32I-NEXT: bltz a3, .LBB4_2 @@ -418,13 +418,13 @@ define void @shl_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu t0, 6(a0) ; RV32I-NEXT: lbu a0, 7(a0) ; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a6, a6, a7 +; RV32I-NEXT: add a6, a6, a7 ; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, t0 +; RV32I-NEXT: add a0, a0, t0 ; RV32I-NEXT: not a7, a4 ; RV32I-NEXT: srli a5, a5, 1 -; RV32I-NEXT: or a0, a0, a6 +; RV32I-NEXT: add a0, a0, a6 ; RV32I-NEXT: sll a0, a0, a4 ; RV32I-NEXT: srl a4, a5, a7 ; RV32I-NEXT: or a0, a0, a4 @@ -467,38 +467,38 @@ define void @ashr_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 0(a1) -; RV64I-NEXT: lbu a7, 1(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 0(a1) +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t0, 2(a1) ; RV64I-NEXT: lbu t2, 3(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t2, t0 -; RV64I-NEXT: lbu t0, 5(a1) +; RV64I-NEXT: add a0, a0, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t2, t0 +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t1, 4(a1) ; RV64I-NEXT: lbu t2, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a0, a0, a5 -; RV64I-NEXT: or a4, a7, a6 -; RV64I-NEXT: or a1, a1, t0 +; RV64I-NEXT: add a1, a1, t2 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a0, a0, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a0, a0, a3 -; RV64I-NEXT: or a1, a1, a4 +; RV64I-NEXT: add a0, a0, a3 +; RV64I-NEXT: add a1, a1, a4 ; RV64I-NEXT: sra a0, a0, a1 ; RV64I-NEXT: srli a1, a0, 48 ; RV64I-NEXT: srli a3, a0, 56 @@ -524,21 +524,21 @@ define void @ashr_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu a5, 6(a0) ; RV32I-NEXT: lbu a6, 7(a0) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, a4 +; RV32I-NEXT: add a3, a3, a4 ; RV32I-NEXT: lbu a4, 1(a1) ; RV32I-NEXT: lbu a7, 0(a1) ; RV32I-NEXT: lbu t0, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a7, a4, a7 +; RV32I-NEXT: add a7, a4, a7 ; RV32I-NEXT: slli t0, t0, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, t0 +; RV32I-NEXT: add a1, a1, t0 ; RV32I-NEXT: slli a4, a5, 16 ; RV32I-NEXT: slli a5, a6, 24 -; RV32I-NEXT: or a4, a5, a4 -; RV32I-NEXT: or a4, a4, a3 -; RV32I-NEXT: or a3, a1, a7 +; RV32I-NEXT: add a4, a5, a4 +; RV32I-NEXT: add a4, a4, a3 +; RV32I-NEXT: add a3, a1, a7 ; RV32I-NEXT: addi a6, a3, -32 ; RV32I-NEXT: sra a1, a4, a3 ; RV32I-NEXT: bltz a6, .LBB5_2 @@ -553,13 +553,13 @@ define void @ashr_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu a7, 2(a0) ; RV32I-NEXT: lbu a0, 3(a0) ; RV32I-NEXT: slli a5, a5, 8 -; RV32I-NEXT: or a5, a5, a6 +; RV32I-NEXT: add a5, a5, a6 ; RV32I-NEXT: slli a7, a7, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, a7 +; RV32I-NEXT: add a0, a0, a7 ; RV32I-NEXT: not a6, a3 ; RV32I-NEXT: slli a4, a4, 1 -; RV32I-NEXT: or a0, a0, a5 +; RV32I-NEXT: add a0, a0, a5 ; RV32I-NEXT: srl a0, a0, a3 ; RV32I-NEXT: sll a3, a4, a6 ; RV32I-NEXT: or a0, a0, a3 @@ -601,38 +601,38 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 0(a1) -; RV64I-NEXT: lbu a7, 1(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 0(a1) +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t0, 2(a1) ; RV64I-NEXT: lbu t3, 3(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t2, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t3, t0 -; RV64I-NEXT: lbu t0, 5(a1) +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t3, t0 +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t2, 4(a1) ; RV64I-NEXT: lbu t3, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t2 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t2 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, t1, a5 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a1, a1, t0 -; RV64I-NEXT: slli a4, a4, 32 +; RV64I-NEXT: add a1, a1, t3 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 +; RV64I-NEXT: slli a5, a7, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a5, a4, a3 -; RV64I-NEXT: or a4, a1, a6 +; RV64I-NEXT: add a5, a5, a3 +; RV64I-NEXT: add a4, a1, a4 ; RV64I-NEXT: addi a3, a4, -64 ; RV64I-NEXT: srl a1, a5, a4 ; RV64I-NEXT: bltz a3, .LBB6_2 @@ -647,23 +647,23 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t0, t0, 24 -; RV64I-NEXT: or a6, a6, t1 -; RV64I-NEXT: or a7, t0, a7 +; RV64I-NEXT: add a6, a6, t1 +; RV64I-NEXT: add a7, t0, a7 ; RV64I-NEXT: lbu t0, 5(a0) ; RV64I-NEXT: lbu t1, 4(a0) ; RV64I-NEXT: lbu t2, 6(a0) ; RV64I-NEXT: lbu a0, 7(a0) ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: add t0, t0, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, t2 -; RV64I-NEXT: or a6, a7, a6 +; RV64I-NEXT: add a0, a0, t2 +; RV64I-NEXT: add a6, a7, a6 ; RV64I-NEXT: not a7, a4 ; RV64I-NEXT: slli a5, a5, 1 -; RV64I-NEXT: or a0, a0, t0 +; RV64I-NEXT: add a0, a0, t0 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: add a0, a0, a6 ; RV64I-NEXT: srl a0, a0, a4 ; RV64I-NEXT: sll a4, a5, a7 ; RV64I-NEXT: or a0, a0, a4 @@ -716,8 +716,8 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, a6, a5 +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a4, a6, a5 ; RV32I-NEXT: lbu a5, 8(a0) ; RV32I-NEXT: lbu a6, 9(a0) ; RV32I-NEXT: lbu t3, 10(a0) @@ -726,42 +726,42 @@ define void @lshr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 ; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, t2, t1 -; RV32I-NEXT: or a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, t2, t1 +; RV32I-NEXT: add a5, a6, a5 ; RV32I-NEXT: lbu a6, 12(a0) -; RV32I-NEXT: lbu t1, 13(a0) +; RV32I-NEXT: lbu t0, 13(a0) ; RV32I-NEXT: lbu t2, 14(a0) ; RV32I-NEXT: lbu a0, 15(a0) ; RV32I-NEXT: slli t3, t3, 16 ; RV32I-NEXT: slli t4, t4, 24 -; RV32I-NEXT: slli t1, t1, 8 +; RV32I-NEXT: slli t0, t0, 8 ; RV32I-NEXT: slli t2, t2, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or t3, t4, t3 -; RV32I-NEXT: or a6, t1, a6 -; RV32I-NEXT: or a0, a0, t2 -; RV32I-NEXT: lbu t1, 1(a1) +; RV32I-NEXT: add t3, t4, t3 +; RV32I-NEXT: add a6, t0, a6 +; RV32I-NEXT: add a0, a0, t2 +; RV32I-NEXT: lbu t0, 1(a1) ; RV32I-NEXT: lbu t2, 0(a1) ; RV32I-NEXT: lbu t4, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) -; RV32I-NEXT: slli t1, t1, 8 -; RV32I-NEXT: or t1, t1, t2 +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: add t0, t0, t2 ; RV32I-NEXT: sw zero, 16(sp) ; RV32I-NEXT: sw zero, 20(sp) ; RV32I-NEXT: sw zero, 24(sp) ; RV32I-NEXT: sw zero, 28(sp) ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, t4 +; RV32I-NEXT: add a1, a1, t4 ; RV32I-NEXT: mv t2, sp -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, t0, a7 -; RV32I-NEXT: or a5, t3, a5 -; RV32I-NEXT: or a0, a0, a6 -; RV32I-NEXT: or a1, a1, t1 +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a7, t1, a7 +; RV32I-NEXT: add a5, t3, a5 +; RV32I-NEXT: add a0, a0, a6 +; RV32I-NEXT: add a1, a1, t0 ; RV32I-NEXT: sw a3, 0(sp) -; RV32I-NEXT: sw a4, 4(sp) +; RV32I-NEXT: sw a7, 4(sp) ; RV32I-NEXT: sw a5, 8(sp) ; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: srli a0, a1, 3 @@ -837,38 +837,38 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 0(a1) -; RV64I-NEXT: lbu a7, 1(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 0(a1) +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t0, 2(a1) ; RV64I-NEXT: lbu t3, 3(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t2, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t3, t0 -; RV64I-NEXT: lbu t0, 5(a1) +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t3, t0 +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t2, 4(a1) ; RV64I-NEXT: lbu t3, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t2 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t2 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, t1, a5 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a1, a1, t0 -; RV64I-NEXT: slli a4, a4, 32 +; RV64I-NEXT: add a1, a1, t3 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a4, t0, a4 +; RV64I-NEXT: add a1, a1, a6 +; RV64I-NEXT: slli a5, a7, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a5, a4, a3 -; RV64I-NEXT: or a4, a1, a6 +; RV64I-NEXT: add a5, a5, a3 +; RV64I-NEXT: add a4, a1, a4 ; RV64I-NEXT: addi a3, a4, -64 ; RV64I-NEXT: sll a1, a5, a4 ; RV64I-NEXT: bltz a3, .LBB7_2 @@ -883,23 +883,23 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli a7, a7, 16 ; RV64I-NEXT: slli t0, t0, 24 -; RV64I-NEXT: or a6, a6, t1 -; RV64I-NEXT: or a7, t0, a7 +; RV64I-NEXT: add a6, a6, t1 +; RV64I-NEXT: add a7, t0, a7 ; RV64I-NEXT: lbu t0, 13(a0) ; RV64I-NEXT: lbu t1, 12(a0) ; RV64I-NEXT: lbu t2, 14(a0) ; RV64I-NEXT: lbu a0, 15(a0) ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t1 +; RV64I-NEXT: add t0, t0, t1 ; RV64I-NEXT: slli t2, t2, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, t2 -; RV64I-NEXT: or a6, a7, a6 +; RV64I-NEXT: add a0, a0, t2 +; RV64I-NEXT: add a6, a7, a6 ; RV64I-NEXT: not a7, a4 ; RV64I-NEXT: srli a5, a5, 1 -; RV64I-NEXT: or a0, a0, t0 +; RV64I-NEXT: add a0, a0, t0 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a6 +; RV64I-NEXT: add a0, a0, a6 ; RV64I-NEXT: sll a0, a0, a4 ; RV64I-NEXT: srl a4, a5, a7 ; RV64I-NEXT: or a0, a0, a4 @@ -952,8 +952,8 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: slli a5, a5, 16 ; RV32I-NEXT: slli a6, a6, 24 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, a6, a5 +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a4, a6, a5 ; RV32I-NEXT: lbu a5, 8(a0) ; RV32I-NEXT: lbu a6, 9(a0) ; RV32I-NEXT: lbu t3, 10(a0) @@ -962,42 +962,42 @@ define void @shl_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 ; RV32I-NEXT: slli a6, a6, 8 -; RV32I-NEXT: or a7, t0, a7 -; RV32I-NEXT: or t0, t2, t1 -; RV32I-NEXT: or a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, t2, t1 +; RV32I-NEXT: add a5, a6, a5 ; RV32I-NEXT: lbu a6, 12(a0) -; RV32I-NEXT: lbu t1, 13(a0) +; RV32I-NEXT: lbu t0, 13(a0) ; RV32I-NEXT: lbu t2, 14(a0) ; RV32I-NEXT: lbu a0, 15(a0) ; RV32I-NEXT: slli t3, t3, 16 ; RV32I-NEXT: slli t4, t4, 24 -; RV32I-NEXT: slli t1, t1, 8 +; RV32I-NEXT: slli t0, t0, 8 ; RV32I-NEXT: slli t2, t2, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or t3, t4, t3 -; RV32I-NEXT: or a6, t1, a6 -; RV32I-NEXT: or a0, a0, t2 -; RV32I-NEXT: lbu t1, 1(a1) +; RV32I-NEXT: add t3, t4, t3 +; RV32I-NEXT: add a6, t0, a6 +; RV32I-NEXT: add a0, a0, t2 +; RV32I-NEXT: lbu t0, 1(a1) ; RV32I-NEXT: lbu t2, 0(a1) ; RV32I-NEXT: lbu t4, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) -; RV32I-NEXT: slli t1, t1, 8 -; RV32I-NEXT: or t1, t1, t2 +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: add t0, t0, t2 ; RV32I-NEXT: sw zero, 0(sp) ; RV32I-NEXT: sw zero, 4(sp) ; RV32I-NEXT: sw zero, 8(sp) ; RV32I-NEXT: sw zero, 12(sp) ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, t4 +; RV32I-NEXT: add a1, a1, t4 ; RV32I-NEXT: addi t2, sp, 16 -; RV32I-NEXT: or a3, a4, a3 -; RV32I-NEXT: or a4, t0, a7 -; RV32I-NEXT: or a5, t3, a5 -; RV32I-NEXT: or a0, a0, a6 -; RV32I-NEXT: or a1, a1, t1 +; RV32I-NEXT: add a3, a4, a3 +; RV32I-NEXT: add a7, t1, a7 +; RV32I-NEXT: add a5, t3, a5 +; RV32I-NEXT: add a0, a0, a6 +; RV32I-NEXT: add a1, a1, t0 ; RV32I-NEXT: sw a3, 16(sp) -; RV32I-NEXT: sw a4, 20(sp) +; RV32I-NEXT: sw a7, 20(sp) ; RV32I-NEXT: sw a5, 24(sp) ; RV32I-NEXT: sw a0, 28(sp) ; RV32I-NEXT: srli a0, a1, 3 @@ -1073,38 +1073,38 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: lbu a6, 0(a1) -; RV64I-NEXT: lbu a7, 1(a1) +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: lbu a4, 0(a1) +; RV64I-NEXT: lbu a6, 1(a1) ; RV64I-NEXT: lbu t0, 2(a1) ; RV64I-NEXT: lbu t3, 3(a1) ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: slli a7, a7, 8 +; RV64I-NEXT: slli a6, a6, 8 ; RV64I-NEXT: slli t0, t0, 16 ; RV64I-NEXT: slli t3, t3, 24 -; RV64I-NEXT: or t1, t2, t1 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a7, t3, t0 -; RV64I-NEXT: lbu t0, 5(a1) +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add a4, a6, a4 +; RV64I-NEXT: add t0, t3, t0 +; RV64I-NEXT: lbu a6, 5(a1) ; RV64I-NEXT: lbu t2, 4(a1) ; RV64I-NEXT: lbu t3, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli t0, t0, 8 -; RV64I-NEXT: or t0, t0, t2 +; RV64I-NEXT: slli a6, a6, 8 +; RV64I-NEXT: add a6, a6, t2 ; RV64I-NEXT: slli t3, t3, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, t3 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a5, t1, a5 -; RV64I-NEXT: or a6, a7, a6 -; RV64I-NEXT: or a1, a1, t0 +; RV64I-NEXT: add a1, a1, t3 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a5, t1, a7 +; RV64I-NEXT: add t0, t0, a4 +; RV64I-NEXT: add a1, a1, a6 ; RV64I-NEXT: slli a4, a5, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a4, a4, a3 -; RV64I-NEXT: or a3, a1, a6 +; RV64I-NEXT: add a4, a4, a3 +; RV64I-NEXT: add a3, a1, t0 ; RV64I-NEXT: addi a6, a3, -64 ; RV64I-NEXT: sra a1, a4, a3 ; RV64I-NEXT: bltz a6, .LBB8_2 @@ -1121,23 +1121,23 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli a5, a5, 8 ; RV64I-NEXT: slli a6, a6, 16 ; RV64I-NEXT: slli a7, a7, 24 -; RV64I-NEXT: or a5, a5, t0 -; RV64I-NEXT: or a6, a7, a6 +; RV64I-NEXT: add a5, a5, t0 +; RV64I-NEXT: add a6, a7, a6 ; RV64I-NEXT: lbu a7, 5(a0) ; RV64I-NEXT: lbu t0, 4(a0) ; RV64I-NEXT: lbu t1, 6(a0) ; RV64I-NEXT: lbu a0, 7(a0) ; RV64I-NEXT: slli a7, a7, 8 -; RV64I-NEXT: or a7, a7, t0 +; RV64I-NEXT: add a7, a7, t0 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, t1 -; RV64I-NEXT: or a5, a6, a5 +; RV64I-NEXT: add a0, a0, t1 +; RV64I-NEXT: add a5, a6, a5 ; RV64I-NEXT: not a6, a3 ; RV64I-NEXT: slli a4, a4, 1 -; RV64I-NEXT: or a0, a0, a7 +; RV64I-NEXT: add a0, a0, a7 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: or a0, a0, a5 +; RV64I-NEXT: add a0, a0, a5 ; RV64I-NEXT: srl a0, a0, a3 ; RV64I-NEXT: sll a3, a4, a6 ; RV64I-NEXT: or a0, a0, a3 @@ -1186,7 +1186,7 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: lbu t1, 6(a0) ; RV32I-NEXT: lbu t2, 7(a0) ; RV32I-NEXT: slli a4, a4, 8 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: lbu a4, 8(a0) ; RV32I-NEXT: lbu t3, 9(a0) ; RV32I-NEXT: lbu t4, 10(a0) @@ -1196,47 +1196,47 @@ define void @ashr_16bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli t0, t0, 8 ; RV32I-NEXT: slli t1, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a6, t0, a7 -; RV32I-NEXT: or a7, t2, t1 -; RV32I-NEXT: lbu t0, 12(a0) -; RV32I-NEXT: lbu t1, 13(a0) +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, t2, t1 +; RV32I-NEXT: lbu a6, 12(a0) +; RV32I-NEXT: lbu t0, 13(a0) ; RV32I-NEXT: lbu t2, 14(a0) ; RV32I-NEXT: lbu a0, 15(a0) ; RV32I-NEXT: slli t3, t3, 8 ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli t5, t5, 24 -; RV32I-NEXT: slli t1, t1, 8 -; RV32I-NEXT: or a4, t3, a4 -; RV32I-NEXT: or t3, t5, t4 -; RV32I-NEXT: or t0, t1, t0 -; RV32I-NEXT: lbu t1, 1(a1) -; RV32I-NEXT: lbu t4, 0(a1) +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: add a4, t3, a4 +; RV32I-NEXT: add t4, t5, t4 +; RV32I-NEXT: add a6, t0, a6 +; RV32I-NEXT: lbu t0, 1(a1) +; RV32I-NEXT: lbu t3, 0(a1) ; RV32I-NEXT: lbu t5, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) -; RV32I-NEXT: slli t1, t1, 8 -; RV32I-NEXT: or t1, t1, t4 +; RV32I-NEXT: slli t0, t0, 8 +; RV32I-NEXT: add t0, t0, t3 ; RV32I-NEXT: slli t5, t5, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, t5 -; RV32I-NEXT: or a3, a5, a3 +; RV32I-NEXT: add a1, a1, t5 +; RV32I-NEXT: add a3, a5, a3 ; RV32I-NEXT: mv a5, sp ; RV32I-NEXT: slli t2, t2, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or t2, a0, t2 +; RV32I-NEXT: add t2, a0, t2 ; RV32I-NEXT: srai a0, a0, 31 -; RV32I-NEXT: or a6, a7, a6 -; RV32I-NEXT: or a4, t3, a4 -; RV32I-NEXT: or a7, t2, t0 -; RV32I-NEXT: or a1, a1, t1 +; RV32I-NEXT: add a7, t1, a7 +; RV32I-NEXT: add a4, t4, a4 +; RV32I-NEXT: add a6, t2, a6 +; RV32I-NEXT: add a1, a1, t0 ; RV32I-NEXT: sw a0, 16(sp) ; RV32I-NEXT: sw a0, 20(sp) ; RV32I-NEXT: sw a0, 24(sp) ; RV32I-NEXT: sw a0, 28(sp) ; RV32I-NEXT: sw a3, 0(sp) -; RV32I-NEXT: sw a6, 4(sp) +; RV32I-NEXT: sw a7, 4(sp) ; RV32I-NEXT: sw a4, 8(sp) -; RV32I-NEXT: sw a7, 12(sp) +; RV32I-NEXT: sw a6, 12(sp) ; RV32I-NEXT: srli a0, a1, 3 ; RV32I-NEXT: andi a3, a1, 31 ; RV32I-NEXT: andi a0, a0, 12 @@ -1312,9 +1312,9 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: sd s9, 80(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s10, 72(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s11, 64(sp) # 8-byte Folded Spill -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: lbu a4, 1(a0) -; RV64I-NEXT: lbu a5, 2(a0) +; RV64I-NEXT: lbu a5, 0(a0) +; RV64I-NEXT: lbu a3, 1(a0) +; RV64I-NEXT: lbu a4, 2(a0) ; RV64I-NEXT: lbu a6, 3(a0) ; RV64I-NEXT: lbu a7, 4(a0) ; RV64I-NEXT: lbu t0, 5(a0) @@ -1332,55 +1332,55 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: lbu s5, 17(a0) ; RV64I-NEXT: lbu s6, 18(a0) ; RV64I-NEXT: lbu s7, 19(a0) -; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: slli s8, a5, 16 +; RV64I-NEXT: slli a3, a3, 8 +; RV64I-NEXT: slli a4, a4, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a5, a4, a3 -; RV64I-NEXT: or a6, a6, s8 -; RV64I-NEXT: or a3, t0, a7 -; RV64I-NEXT: or a4, t2, t1 +; RV64I-NEXT: add a5, a3, a5 +; RV64I-NEXT: add a6, a6, a4 +; RV64I-NEXT: add a3, t0, a7 +; RV64I-NEXT: add a4, t2, t1 ; RV64I-NEXT: lbu s8, 20(a0) ; RV64I-NEXT: lbu s9, 21(a0) ; RV64I-NEXT: lbu s10, 22(a0) ; RV64I-NEXT: lbu s11, 23(a0) -; RV64I-NEXT: slli t4, t4, 8 -; RV64I-NEXT: slli t5, t5, 16 +; RV64I-NEXT: slli a7, t4, 8 +; RV64I-NEXT: slli t0, t5, 16 ; RV64I-NEXT: slli t6, t6, 24 -; RV64I-NEXT: slli s1, s1, 8 -; RV64I-NEXT: slli s2, s2, 16 +; RV64I-NEXT: slli t1, s1, 8 +; RV64I-NEXT: slli t2, s2, 16 ; RV64I-NEXT: slli s3, s3, 24 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or t0, t6, t5 -; RV64I-NEXT: or t1, s1, s0 -; RV64I-NEXT: or t2, s3, s2 +; RV64I-NEXT: add a7, a7, t3 +; RV64I-NEXT: add t0, t6, t0 +; RV64I-NEXT: add t1, t1, s0 +; RV64I-NEXT: add t2, s3, t2 ; RV64I-NEXT: lbu t6, 24(a0) ; RV64I-NEXT: lbu s0, 25(a0) ; RV64I-NEXT: lbu s1, 26(a0) ; RV64I-NEXT: lbu s2, 27(a0) -; RV64I-NEXT: slli s5, s5, 8 -; RV64I-NEXT: slli s6, s6, 16 +; RV64I-NEXT: slli t3, s5, 8 +; RV64I-NEXT: slli t4, s6, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: slli s9, s9, 8 -; RV64I-NEXT: or t3, s5, s4 -; RV64I-NEXT: or t4, s7, s6 -; RV64I-NEXT: or t5, s9, s8 +; RV64I-NEXT: slli t5, s9, 8 +; RV64I-NEXT: add t3, t3, s4 +; RV64I-NEXT: add t4, s7, t4 +; RV64I-NEXT: add t5, t5, s8 ; RV64I-NEXT: lbu s3, 28(a0) ; RV64I-NEXT: lbu s4, 29(a0) ; RV64I-NEXT: lbu s5, 30(a0) ; RV64I-NEXT: lbu s6, 31(a0) -; RV64I-NEXT: slli s10, s10, 16 +; RV64I-NEXT: slli a0, s10, 16 ; RV64I-NEXT: slli s11, s11, 24 ; RV64I-NEXT: slli s0, s0, 8 ; RV64I-NEXT: slli s1, s1, 16 ; RV64I-NEXT: slli s2, s2, 24 ; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or a0, s11, s10 -; RV64I-NEXT: or t6, s0, t6 -; RV64I-NEXT: or s0, s2, s1 -; RV64I-NEXT: or s1, s4, s3 +; RV64I-NEXT: add a0, s11, a0 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s0, s2, s1 +; RV64I-NEXT: add s1, s4, s3 ; RV64I-NEXT: lbu s2, 0(a1) ; RV64I-NEXT: lbu s3, 1(a1) ; RV64I-NEXT: lbu s4, 2(a1) @@ -1390,47 +1390,47 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli s3, s3, 8 ; RV64I-NEXT: slli s4, s4, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: or s5, s6, s5 -; RV64I-NEXT: or s2, s3, s2 -; RV64I-NEXT: or s3, s7, s4 -; RV64I-NEXT: lbu s4, 5(a1) +; RV64I-NEXT: add s5, s6, s5 +; RV64I-NEXT: add s2, s3, s2 +; RV64I-NEXT: add s4, s7, s4 +; RV64I-NEXT: lbu s3, 5(a1) ; RV64I-NEXT: lbu s6, 4(a1) ; RV64I-NEXT: lbu s7, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or s4, s4, s6 +; RV64I-NEXT: slli s3, s3, 8 +; RV64I-NEXT: add s3, s3, s6 ; RV64I-NEXT: slli s7, s7, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, s7 +; RV64I-NEXT: add a1, a1, s7 ; RV64I-NEXT: sd zero, 32(sp) ; RV64I-NEXT: sd zero, 40(sp) ; RV64I-NEXT: sd zero, 48(sp) ; RV64I-NEXT: sd zero, 56(sp) -; RV64I-NEXT: or a5, a6, a5 +; RV64I-NEXT: add a5, a6, a5 ; RV64I-NEXT: mv a6, sp -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, t0, a7 -; RV64I-NEXT: or a7, t2, t1 -; RV64I-NEXT: or t0, t4, t3 -; RV64I-NEXT: or a0, a0, t5 -; RV64I-NEXT: or t1, s0, t6 -; RV64I-NEXT: or t2, s5, s1 -; RV64I-NEXT: or t3, s3, s2 -; RV64I-NEXT: or a1, a1, s4 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add t3, t4, t3 +; RV64I-NEXT: add a0, a0, t5 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s1, s5, s1 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add a1, a1, s3 ; RV64I-NEXT: slli a3, a3, 32 -; RV64I-NEXT: slli a7, a7, 32 +; RV64I-NEXT: slli t1, t1, 32 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: slli t2, t2, 32 +; RV64I-NEXT: slli s1, s1, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a3, a3, a5 -; RV64I-NEXT: or a4, a7, a4 -; RV64I-NEXT: or a0, a0, t0 -; RV64I-NEXT: or a5, t2, t1 -; RV64I-NEXT: or a1, a1, t3 +; RV64I-NEXT: add a3, a3, a5 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a0, a0, t3 +; RV64I-NEXT: add t6, s1, t6 +; RV64I-NEXT: add a1, a1, s2 ; RV64I-NEXT: sd a3, 0(sp) -; RV64I-NEXT: sd a4, 8(sp) +; RV64I-NEXT: sd a7, 8(sp) ; RV64I-NEXT: sd a0, 16(sp) -; RV64I-NEXT: sd a5, 24(sp) +; RV64I-NEXT: sd t6, 24(sp) ; RV64I-NEXT: srli a0, a1, 3 ; RV64I-NEXT: andi a3, a1, 63 ; RV64I-NEXT: andi a0, a0, 24 @@ -1567,46 +1567,46 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: slli a6, a6, 16 ; RV32I-NEXT: slli a7, a7, 24 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sw a3, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: or a4, a7, a6 +; RV32I-NEXT: add a4, a7, a6 ; RV32I-NEXT: lbu s10, 20(a0) ; RV32I-NEXT: lbu s11, 21(a0) ; RV32I-NEXT: lbu ra, 22(a0) ; RV32I-NEXT: lbu a3, 23(a0) ; RV32I-NEXT: slli t0, t0, 8 -; RV32I-NEXT: slli t1, t1, 16 +; RV32I-NEXT: slli a6, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 -; RV32I-NEXT: slli t4, t4, 8 +; RV32I-NEXT: slli a7, t4, 8 ; RV32I-NEXT: slli t5, t5, 16 ; RV32I-NEXT: slli t6, t6, 24 -; RV32I-NEXT: or a5, t0, a5 -; RV32I-NEXT: or a6, t2, t1 -; RV32I-NEXT: or a7, t4, t3 -; RV32I-NEXT: or t0, t6, t5 +; RV32I-NEXT: add a5, t0, a5 +; RV32I-NEXT: add a6, t2, a6 +; RV32I-NEXT: add a7, a7, t3 +; RV32I-NEXT: add t0, t6, t5 ; RV32I-NEXT: lbu s1, 24(a0) ; RV32I-NEXT: lbu s3, 25(a0) ; RV32I-NEXT: lbu t4, 26(a0) ; RV32I-NEXT: lbu t5, 27(a0) -; RV32I-NEXT: slli s2, s2, 8 -; RV32I-NEXT: slli s4, s4, 16 +; RV32I-NEXT: slli t1, s2, 8 +; RV32I-NEXT: slli t2, s4, 16 ; RV32I-NEXT: slli s5, s5, 24 -; RV32I-NEXT: slli s7, s7, 8 -; RV32I-NEXT: or t1, s2, s0 -; RV32I-NEXT: or t2, s5, s4 -; RV32I-NEXT: or t3, s7, s6 +; RV32I-NEXT: slli t3, s7, 8 +; RV32I-NEXT: add t1, t1, s0 +; RV32I-NEXT: add t2, s5, t2 +; RV32I-NEXT: add t3, t3, s6 ; RV32I-NEXT: lbu t6, 28(a0) ; RV32I-NEXT: lbu s4, 29(a0) ; RV32I-NEXT: lbu s5, 30(a0) ; RV32I-NEXT: lbu s6, 31(a0) -; RV32I-NEXT: slli s8, s8, 16 +; RV32I-NEXT: slli a0, s8, 16 ; RV32I-NEXT: slli s9, s9, 24 -; RV32I-NEXT: slli s11, s11, 8 -; RV32I-NEXT: slli ra, ra, 16 +; RV32I-NEXT: slli s0, s11, 8 +; RV32I-NEXT: slli s2, ra, 16 ; RV32I-NEXT: slli a3, a3, 24 -; RV32I-NEXT: or a0, s9, s8 -; RV32I-NEXT: or s0, s11, s10 -; RV32I-NEXT: or s2, a3, ra +; RV32I-NEXT: add a0, s9, a0 +; RV32I-NEXT: add s0, s0, s10 +; RV32I-NEXT: add s2, a3, s2 ; RV32I-NEXT: lbu a3, 0(a1) ; RV32I-NEXT: lbu s7, 1(a1) ; RV32I-NEXT: lbu s8, 2(a1) @@ -1620,7 +1620,7 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sw zero, 48(sp) ; RV32I-NEXT: sw zero, 52(sp) ; RV32I-NEXT: slli s3, s3, 8 -; RV32I-NEXT: or s1, s3, s1 +; RV32I-NEXT: add s1, s3, s1 ; RV32I-NEXT: addi s3, sp, 8 ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli t5, t5, 24 @@ -1630,29 +1630,29 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli s7, s7, 8 ; RV32I-NEXT: slli s8, s8, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or t4, t5, t4 -; RV32I-NEXT: or t5, s4, t6 -; RV32I-NEXT: or t6, s6, s5 -; RV32I-NEXT: or a3, s7, a3 -; RV32I-NEXT: or a1, a1, s8 -; RV32I-NEXT: lw s4, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, a4, s4 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a6, t0, a7 -; RV32I-NEXT: or a7, t2, t1 -; RV32I-NEXT: or t0, a0, t3 -; RV32I-NEXT: or t1, s2, s0 -; RV32I-NEXT: or t2, t4, s1 -; RV32I-NEXT: or t3, t6, t5 -; RV32I-NEXT: or a0, a1, a3 -; RV32I-NEXT: sw t0, 24(sp) -; RV32I-NEXT: sw t1, 28(sp) -; RV32I-NEXT: sw t2, 32(sp) -; RV32I-NEXT: sw t3, 36(sp) +; RV32I-NEXT: add t4, t5, t4 +; RV32I-NEXT: add t6, s4, t6 +; RV32I-NEXT: add s5, s6, s5 +; RV32I-NEXT: add a3, s7, a3 +; RV32I-NEXT: add a1, a1, s8 +; RV32I-NEXT: lw t5, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: add a4, a4, t5 +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, t2, t1 +; RV32I-NEXT: add t3, a0, t3 +; RV32I-NEXT: add s0, s2, s0 +; RV32I-NEXT: add t4, t4, s1 +; RV32I-NEXT: add t6, s5, t6 +; RV32I-NEXT: add a0, a1, a3 +; RV32I-NEXT: sw t3, 24(sp) +; RV32I-NEXT: sw s0, 28(sp) +; RV32I-NEXT: sw t4, 32(sp) +; RV32I-NEXT: sw t6, 36(sp) ; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a5, 12(sp) -; RV32I-NEXT: sw a6, 16(sp) -; RV32I-NEXT: sw a7, 20(sp) +; RV32I-NEXT: sw a7, 16(sp) +; RV32I-NEXT: sw t1, 20(sp) ; RV32I-NEXT: srli a1, a0, 3 ; RV32I-NEXT: andi a3, a0, 31 ; RV32I-NEXT: andi a4, a1, 28 @@ -1788,9 +1788,9 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: sd s9, 80(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s10, 72(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s11, 64(sp) # 8-byte Folded Spill -; RV64I-NEXT: lbu a3, 0(a0) -; RV64I-NEXT: lbu a4, 1(a0) -; RV64I-NEXT: lbu a5, 2(a0) +; RV64I-NEXT: lbu a5, 0(a0) +; RV64I-NEXT: lbu a3, 1(a0) +; RV64I-NEXT: lbu a4, 2(a0) ; RV64I-NEXT: lbu a6, 3(a0) ; RV64I-NEXT: lbu a7, 4(a0) ; RV64I-NEXT: lbu t0, 5(a0) @@ -1808,55 +1808,55 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: lbu s5, 17(a0) ; RV64I-NEXT: lbu s6, 18(a0) ; RV64I-NEXT: lbu s7, 19(a0) -; RV64I-NEXT: slli a4, a4, 8 -; RV64I-NEXT: slli s8, a5, 16 +; RV64I-NEXT: slli a3, a3, 8 +; RV64I-NEXT: slli a4, a4, 16 ; RV64I-NEXT: slli a6, a6, 24 ; RV64I-NEXT: slli t0, t0, 8 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a5, a4, a3 -; RV64I-NEXT: or a6, a6, s8 -; RV64I-NEXT: or a3, t0, a7 -; RV64I-NEXT: or a4, t2, t1 +; RV64I-NEXT: add a5, a3, a5 +; RV64I-NEXT: add a6, a6, a4 +; RV64I-NEXT: add a3, t0, a7 +; RV64I-NEXT: add a4, t2, t1 ; RV64I-NEXT: lbu s8, 20(a0) ; RV64I-NEXT: lbu s9, 21(a0) ; RV64I-NEXT: lbu s10, 22(a0) ; RV64I-NEXT: lbu s11, 23(a0) -; RV64I-NEXT: slli t4, t4, 8 -; RV64I-NEXT: slli t5, t5, 16 +; RV64I-NEXT: slli a7, t4, 8 +; RV64I-NEXT: slli t0, t5, 16 ; RV64I-NEXT: slli t6, t6, 24 -; RV64I-NEXT: slli s1, s1, 8 -; RV64I-NEXT: slli s2, s2, 16 +; RV64I-NEXT: slli t1, s1, 8 +; RV64I-NEXT: slli t2, s2, 16 ; RV64I-NEXT: slli s3, s3, 24 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or t0, t6, t5 -; RV64I-NEXT: or t1, s1, s0 -; RV64I-NEXT: or t2, s3, s2 +; RV64I-NEXT: add a7, a7, t3 +; RV64I-NEXT: add t0, t6, t0 +; RV64I-NEXT: add t1, t1, s0 +; RV64I-NEXT: add t2, s3, t2 ; RV64I-NEXT: lbu t6, 24(a0) ; RV64I-NEXT: lbu s0, 25(a0) ; RV64I-NEXT: lbu s1, 26(a0) ; RV64I-NEXT: lbu s2, 27(a0) -; RV64I-NEXT: slli s5, s5, 8 -; RV64I-NEXT: slli s6, s6, 16 +; RV64I-NEXT: slli t3, s5, 8 +; RV64I-NEXT: slli t4, s6, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: slli s9, s9, 8 -; RV64I-NEXT: or t3, s5, s4 -; RV64I-NEXT: or t4, s7, s6 -; RV64I-NEXT: or t5, s9, s8 +; RV64I-NEXT: slli t5, s9, 8 +; RV64I-NEXT: add t3, t3, s4 +; RV64I-NEXT: add t4, s7, t4 +; RV64I-NEXT: add t5, t5, s8 ; RV64I-NEXT: lbu s3, 28(a0) ; RV64I-NEXT: lbu s4, 29(a0) ; RV64I-NEXT: lbu s5, 30(a0) ; RV64I-NEXT: lbu s6, 31(a0) -; RV64I-NEXT: slli s10, s10, 16 +; RV64I-NEXT: slli a0, s10, 16 ; RV64I-NEXT: slli s11, s11, 24 ; RV64I-NEXT: slli s0, s0, 8 ; RV64I-NEXT: slli s1, s1, 16 ; RV64I-NEXT: slli s2, s2, 24 ; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or a0, s11, s10 -; RV64I-NEXT: or t6, s0, t6 -; RV64I-NEXT: or s0, s2, s1 -; RV64I-NEXT: or s1, s4, s3 +; RV64I-NEXT: add a0, s11, a0 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s0, s2, s1 +; RV64I-NEXT: add s1, s4, s3 ; RV64I-NEXT: lbu s2, 0(a1) ; RV64I-NEXT: lbu s3, 1(a1) ; RV64I-NEXT: lbu s4, 2(a1) @@ -1866,47 +1866,47 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli s3, s3, 8 ; RV64I-NEXT: slli s4, s4, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: or s5, s6, s5 -; RV64I-NEXT: or s2, s3, s2 -; RV64I-NEXT: or s3, s7, s4 -; RV64I-NEXT: lbu s4, 5(a1) +; RV64I-NEXT: add s5, s6, s5 +; RV64I-NEXT: add s2, s3, s2 +; RV64I-NEXT: add s4, s7, s4 +; RV64I-NEXT: lbu s3, 5(a1) ; RV64I-NEXT: lbu s6, 4(a1) ; RV64I-NEXT: lbu s7, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or s4, s4, s6 +; RV64I-NEXT: slli s3, s3, 8 +; RV64I-NEXT: add s3, s3, s6 ; RV64I-NEXT: slli s7, s7, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, s7 +; RV64I-NEXT: add a1, a1, s7 ; RV64I-NEXT: sd zero, 0(sp) ; RV64I-NEXT: sd zero, 8(sp) ; RV64I-NEXT: sd zero, 16(sp) ; RV64I-NEXT: sd zero, 24(sp) -; RV64I-NEXT: or a5, a6, a5 +; RV64I-NEXT: add a5, a6, a5 ; RV64I-NEXT: addi a6, sp, 32 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, t0, a7 -; RV64I-NEXT: or a7, t2, t1 -; RV64I-NEXT: or t0, t4, t3 -; RV64I-NEXT: or a0, a0, t5 -; RV64I-NEXT: or t1, s0, t6 -; RV64I-NEXT: or t2, s5, s1 -; RV64I-NEXT: or t3, s3, s2 -; RV64I-NEXT: or a1, a1, s4 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add t3, t4, t3 +; RV64I-NEXT: add a0, a0, t5 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s1, s5, s1 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add a1, a1, s3 ; RV64I-NEXT: slli a3, a3, 32 -; RV64I-NEXT: slli a7, a7, 32 +; RV64I-NEXT: slli t1, t1, 32 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: slli t2, t2, 32 +; RV64I-NEXT: slli s1, s1, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: or a3, a3, a5 -; RV64I-NEXT: or a4, a7, a4 -; RV64I-NEXT: or a0, a0, t0 -; RV64I-NEXT: or a5, t2, t1 -; RV64I-NEXT: or a1, a1, t3 +; RV64I-NEXT: add a3, a3, a5 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a0, a0, t3 +; RV64I-NEXT: add t6, s1, t6 +; RV64I-NEXT: add a1, a1, s2 ; RV64I-NEXT: sd a3, 32(sp) -; RV64I-NEXT: sd a4, 40(sp) +; RV64I-NEXT: sd a7, 40(sp) ; RV64I-NEXT: sd a0, 48(sp) -; RV64I-NEXT: sd a5, 56(sp) +; RV64I-NEXT: sd t6, 56(sp) ; RV64I-NEXT: srli a0, a1, 3 ; RV64I-NEXT: andi a3, a1, 63 ; RV64I-NEXT: andi a0, a0, 24 @@ -2043,46 +2043,46 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: slli a6, a6, 16 ; RV32I-NEXT: slli a7, a7, 24 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sw a3, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: or a4, a7, a6 +; RV32I-NEXT: add a4, a7, a6 ; RV32I-NEXT: lbu s10, 20(a0) ; RV32I-NEXT: lbu s11, 21(a0) ; RV32I-NEXT: lbu ra, 22(a0) ; RV32I-NEXT: lbu a3, 23(a0) ; RV32I-NEXT: slli t0, t0, 8 -; RV32I-NEXT: slli t1, t1, 16 +; RV32I-NEXT: slli a6, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 -; RV32I-NEXT: slli t4, t4, 8 +; RV32I-NEXT: slli a7, t4, 8 ; RV32I-NEXT: slli t5, t5, 16 ; RV32I-NEXT: slli t6, t6, 24 -; RV32I-NEXT: or a5, t0, a5 -; RV32I-NEXT: or a6, t2, t1 -; RV32I-NEXT: or a7, t4, t3 -; RV32I-NEXT: or t0, t6, t5 +; RV32I-NEXT: add a5, t0, a5 +; RV32I-NEXT: add a6, t2, a6 +; RV32I-NEXT: add a7, a7, t3 +; RV32I-NEXT: add t0, t6, t5 ; RV32I-NEXT: lbu s1, 24(a0) ; RV32I-NEXT: lbu s3, 25(a0) ; RV32I-NEXT: lbu t4, 26(a0) ; RV32I-NEXT: lbu t5, 27(a0) -; RV32I-NEXT: slli s2, s2, 8 -; RV32I-NEXT: slli s4, s4, 16 +; RV32I-NEXT: slli t1, s2, 8 +; RV32I-NEXT: slli t2, s4, 16 ; RV32I-NEXT: slli s5, s5, 24 -; RV32I-NEXT: slli s7, s7, 8 -; RV32I-NEXT: or t1, s2, s0 -; RV32I-NEXT: or t2, s5, s4 -; RV32I-NEXT: or t3, s7, s6 +; RV32I-NEXT: slli t3, s7, 8 +; RV32I-NEXT: add t1, t1, s0 +; RV32I-NEXT: add t2, s5, t2 +; RV32I-NEXT: add t3, t3, s6 ; RV32I-NEXT: lbu t6, 28(a0) ; RV32I-NEXT: lbu s4, 29(a0) ; RV32I-NEXT: lbu s5, 30(a0) ; RV32I-NEXT: lbu s6, 31(a0) -; RV32I-NEXT: slli s8, s8, 16 +; RV32I-NEXT: slli a0, s8, 16 ; RV32I-NEXT: slli s9, s9, 24 -; RV32I-NEXT: slli s11, s11, 8 -; RV32I-NEXT: slli ra, ra, 16 +; RV32I-NEXT: slli s0, s11, 8 +; RV32I-NEXT: slli s2, ra, 16 ; RV32I-NEXT: slli a3, a3, 24 -; RV32I-NEXT: or a0, s9, s8 -; RV32I-NEXT: or s0, s11, s10 -; RV32I-NEXT: or s2, a3, ra +; RV32I-NEXT: add a0, s9, a0 +; RV32I-NEXT: add s0, s0, s10 +; RV32I-NEXT: add s2, a3, s2 ; RV32I-NEXT: lbu a3, 0(a1) ; RV32I-NEXT: lbu s7, 1(a1) ; RV32I-NEXT: lbu s8, 2(a1) @@ -2096,7 +2096,7 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: sw zero, 16(sp) ; RV32I-NEXT: sw zero, 20(sp) ; RV32I-NEXT: slli s3, s3, 8 -; RV32I-NEXT: or s1, s3, s1 +; RV32I-NEXT: add s1, s3, s1 ; RV32I-NEXT: addi s3, sp, 40 ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli t5, t5, 24 @@ -2106,29 +2106,29 @@ define void @shl_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli s7, s7, 8 ; RV32I-NEXT: slli s8, s8, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or t4, t5, t4 -; RV32I-NEXT: or t5, s4, t6 -; RV32I-NEXT: or t6, s6, s5 -; RV32I-NEXT: or a3, s7, a3 -; RV32I-NEXT: or a1, a1, s8 -; RV32I-NEXT: lw s4, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, a4, s4 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a6, t0, a7 -; RV32I-NEXT: or a7, t2, t1 -; RV32I-NEXT: or t0, a0, t3 -; RV32I-NEXT: or t1, s2, s0 -; RV32I-NEXT: or t2, t4, s1 -; RV32I-NEXT: or t3, t6, t5 -; RV32I-NEXT: or a0, a1, a3 -; RV32I-NEXT: sw t0, 56(sp) -; RV32I-NEXT: sw t1, 60(sp) -; RV32I-NEXT: sw t2, 64(sp) -; RV32I-NEXT: sw t3, 68(sp) +; RV32I-NEXT: add t4, t5, t4 +; RV32I-NEXT: add t6, s4, t6 +; RV32I-NEXT: add s5, s6, s5 +; RV32I-NEXT: add a3, s7, a3 +; RV32I-NEXT: add a1, a1, s8 +; RV32I-NEXT: lw t5, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: add a4, a4, t5 +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, t2, t1 +; RV32I-NEXT: add t3, a0, t3 +; RV32I-NEXT: add s0, s2, s0 +; RV32I-NEXT: add t4, t4, s1 +; RV32I-NEXT: add t6, s5, t6 +; RV32I-NEXT: add a0, a1, a3 +; RV32I-NEXT: sw t3, 56(sp) +; RV32I-NEXT: sw s0, 60(sp) +; RV32I-NEXT: sw t4, 64(sp) +; RV32I-NEXT: sw t6, 68(sp) ; RV32I-NEXT: sw a4, 40(sp) ; RV32I-NEXT: sw a5, 44(sp) -; RV32I-NEXT: sw a6, 48(sp) -; RV32I-NEXT: sw a7, 52(sp) +; RV32I-NEXT: sw a7, 48(sp) +; RV32I-NEXT: sw t1, 52(sp) ; RV32I-NEXT: srli a1, a0, 3 ; RV32I-NEXT: andi a3, a0, 31 ; RV32I-NEXT: andi a4, a1, 28 @@ -2290,49 +2290,49 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli t0, t0, 8 ; RV64I-NEXT: slli t1, t1, 16 ; RV64I-NEXT: slli t2, t2, 24 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a4, a6, a5 +; RV64I-NEXT: add a5, t0, a7 +; RV64I-NEXT: add a6, t2, t1 ; RV64I-NEXT: lbu s8, 20(a0) ; RV64I-NEXT: lbu s9, 21(a0) ; RV64I-NEXT: lbu s10, 22(a0) ; RV64I-NEXT: lbu s11, 23(a0) -; RV64I-NEXT: slli t4, t4, 8 -; RV64I-NEXT: slli t5, t5, 16 +; RV64I-NEXT: slli a7, t4, 8 +; RV64I-NEXT: slli t0, t5, 16 ; RV64I-NEXT: slli t6, t6, 24 -; RV64I-NEXT: slli s1, s1, 8 -; RV64I-NEXT: slli s2, s2, 16 +; RV64I-NEXT: slli t1, s1, 8 +; RV64I-NEXT: slli t2, s2, 16 ; RV64I-NEXT: slli s3, s3, 24 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or t0, t6, t5 -; RV64I-NEXT: or t1, s1, s0 -; RV64I-NEXT: or t2, s3, s2 +; RV64I-NEXT: add a7, a7, t3 +; RV64I-NEXT: add t0, t6, t0 +; RV64I-NEXT: add t1, t1, s0 +; RV64I-NEXT: add t2, s3, t2 ; RV64I-NEXT: lbu t6, 24(a0) ; RV64I-NEXT: lbu s0, 25(a0) ; RV64I-NEXT: lbu s1, 26(a0) ; RV64I-NEXT: lbu s2, 27(a0) -; RV64I-NEXT: slli s5, s5, 8 -; RV64I-NEXT: slli s6, s6, 16 +; RV64I-NEXT: slli t3, s5, 8 +; RV64I-NEXT: slli t4, s6, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: slli s9, s9, 8 -; RV64I-NEXT: or t3, s5, s4 -; RV64I-NEXT: or t4, s7, s6 -; RV64I-NEXT: or t5, s9, s8 +; RV64I-NEXT: slli t5, s9, 8 +; RV64I-NEXT: add t3, t3, s4 +; RV64I-NEXT: add t4, s7, t4 +; RV64I-NEXT: add t5, t5, s8 ; RV64I-NEXT: lbu s3, 28(a0) ; RV64I-NEXT: lbu s4, 29(a0) ; RV64I-NEXT: lbu s5, 30(a0) ; RV64I-NEXT: lbu s6, 31(a0) -; RV64I-NEXT: slli s10, s10, 16 +; RV64I-NEXT: slli a0, s10, 16 ; RV64I-NEXT: slli s11, s11, 24 ; RV64I-NEXT: slli s0, s0, 8 ; RV64I-NEXT: slli s1, s1, 16 ; RV64I-NEXT: slli s2, s2, 24 ; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or a0, s11, s10 -; RV64I-NEXT: or t6, s0, t6 -; RV64I-NEXT: or s0, s2, s1 -; RV64I-NEXT: or s1, s4, s3 +; RV64I-NEXT: add a0, s11, a0 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s0, s2, s1 +; RV64I-NEXT: add s1, s4, s3 ; RV64I-NEXT: lbu s2, 0(a1) ; RV64I-NEXT: lbu s3, 1(a1) ; RV64I-NEXT: lbu s4, 2(a1) @@ -2342,48 +2342,48 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV64I-NEXT: slli s3, s3, 8 ; RV64I-NEXT: slli s4, s4, 16 ; RV64I-NEXT: slli s7, s7, 24 -; RV64I-NEXT: or s5, s6, s5 -; RV64I-NEXT: or s2, s3, s2 -; RV64I-NEXT: or s3, s7, s4 -; RV64I-NEXT: lbu s4, 5(a1) +; RV64I-NEXT: add s5, s6, s5 +; RV64I-NEXT: add s2, s3, s2 +; RV64I-NEXT: add s4, s7, s4 +; RV64I-NEXT: lbu s3, 5(a1) ; RV64I-NEXT: lbu s6, 4(a1) ; RV64I-NEXT: lbu s7, 6(a1) ; RV64I-NEXT: lbu a1, 7(a1) -; RV64I-NEXT: slli s4, s4, 8 -; RV64I-NEXT: or s4, s4, s6 +; RV64I-NEXT: slli s3, s3, 8 +; RV64I-NEXT: add s3, s3, s6 ; RV64I-NEXT: slli s7, s7, 16 ; RV64I-NEXT: slli a1, a1, 24 -; RV64I-NEXT: or a1, a1, s7 +; RV64I-NEXT: add a1, a1, s7 ; RV64I-NEXT: mv s6, sp -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a5, t0, a7 -; RV64I-NEXT: or a6, t2, t1 -; RV64I-NEXT: or a7, t4, t3 -; RV64I-NEXT: or a0, a0, t5 -; RV64I-NEXT: or t0, s0, t6 -; RV64I-NEXT: or t1, s5, s1 -; RV64I-NEXT: or t2, s3, s2 -; RV64I-NEXT: or a1, a1, s4 -; RV64I-NEXT: slli a4, a4, 32 -; RV64I-NEXT: slli a6, a6, 32 +; RV64I-NEXT: add a3, a4, a3 +; RV64I-NEXT: add a5, a6, a5 +; RV64I-NEXT: add a7, t0, a7 +; RV64I-NEXT: add t1, t2, t1 +; RV64I-NEXT: add t3, t4, t3 +; RV64I-NEXT: add a0, a0, t5 +; RV64I-NEXT: add t6, s0, t6 +; RV64I-NEXT: add s1, s5, s1 +; RV64I-NEXT: add s2, s4, s2 +; RV64I-NEXT: add a1, a1, s3 +; RV64I-NEXT: slli a5, a5, 32 +; RV64I-NEXT: slli t1, t1, 32 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: slli t3, t1, 32 +; RV64I-NEXT: slli a4, s1, 32 ; RV64I-NEXT: slli a1, a1, 32 -; RV64I-NEXT: sraiw t1, t1, 31 -; RV64I-NEXT: or a3, a4, a3 -; RV64I-NEXT: or a4, a6, a5 -; RV64I-NEXT: or a0, a0, a7 -; RV64I-NEXT: or a5, t3, t0 -; RV64I-NEXT: or a1, a1, t2 -; RV64I-NEXT: sd t1, 32(sp) -; RV64I-NEXT: sd t1, 40(sp) -; RV64I-NEXT: sd t1, 48(sp) -; RV64I-NEXT: sd t1, 56(sp) +; RV64I-NEXT: sraiw a6, s1, 31 +; RV64I-NEXT: add a3, a5, a3 +; RV64I-NEXT: add a7, t1, a7 +; RV64I-NEXT: add a0, a0, t3 +; RV64I-NEXT: add a4, a4, t6 +; RV64I-NEXT: add a1, a1, s2 +; RV64I-NEXT: sd a6, 32(sp) +; RV64I-NEXT: sd a6, 40(sp) +; RV64I-NEXT: sd a6, 48(sp) +; RV64I-NEXT: sd a6, 56(sp) ; RV64I-NEXT: sd a3, 0(sp) -; RV64I-NEXT: sd a4, 8(sp) +; RV64I-NEXT: sd a7, 8(sp) ; RV64I-NEXT: sd a0, 16(sp) -; RV64I-NEXT: sd a5, 24(sp) +; RV64I-NEXT: sd a4, 24(sp) ; RV64I-NEXT: srli a0, a1, 3 ; RV64I-NEXT: andi a3, a1, 63 ; RV64I-NEXT: andi a0, a0, 24 @@ -2520,34 +2520,34 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli a4, a4, 8 ; RV32I-NEXT: slli a6, a6, 16 ; RV32I-NEXT: slli a7, a7, 24 -; RV32I-NEXT: or a3, a4, a3 +; RV32I-NEXT: add a3, a4, a3 ; RV32I-NEXT: sw a3, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: or a4, a7, a6 +; RV32I-NEXT: add a4, a7, a6 ; RV32I-NEXT: lbu s8, 20(a0) ; RV32I-NEXT: lbu s9, 21(a0) ; RV32I-NEXT: lbu s10, 22(a0) ; RV32I-NEXT: lbu s11, 23(a0) ; RV32I-NEXT: slli t0, t0, 8 -; RV32I-NEXT: slli t1, t1, 16 +; RV32I-NEXT: slli a6, t1, 16 ; RV32I-NEXT: slli t2, t2, 24 -; RV32I-NEXT: slli t4, t4, 8 +; RV32I-NEXT: slli a7, t4, 8 ; RV32I-NEXT: slli t5, t5, 16 ; RV32I-NEXT: slli t6, t6, 24 -; RV32I-NEXT: or a5, t0, a5 -; RV32I-NEXT: or a6, t2, t1 -; RV32I-NEXT: or a7, t4, t3 -; RV32I-NEXT: or t0, t6, t5 +; RV32I-NEXT: add a5, t0, a5 +; RV32I-NEXT: add a6, t2, a6 +; RV32I-NEXT: add a7, a7, t3 +; RV32I-NEXT: add t0, t6, t5 ; RV32I-NEXT: lbu ra, 24(a0) ; RV32I-NEXT: lbu a3, 25(a0) ; RV32I-NEXT: lbu t4, 26(a0) ; RV32I-NEXT: lbu t5, 27(a0) -; RV32I-NEXT: slli s1, s1, 8 -; RV32I-NEXT: slli s2, s2, 16 +; RV32I-NEXT: slli t1, s1, 8 +; RV32I-NEXT: slli t2, s2, 16 ; RV32I-NEXT: slli s3, s3, 24 -; RV32I-NEXT: slli s5, s5, 8 -; RV32I-NEXT: or t1, s1, s0 -; RV32I-NEXT: or t2, s3, s2 -; RV32I-NEXT: or t3, s5, s4 +; RV32I-NEXT: slli t3, s5, 8 +; RV32I-NEXT: add t1, t1, s0 +; RV32I-NEXT: add t2, s3, t2 +; RV32I-NEXT: add t3, t3, s4 ; RV32I-NEXT: lbu t6, 28(a0) ; RV32I-NEXT: lbu s0, 29(a0) ; RV32I-NEXT: lbu s1, 30(a0) @@ -2557,61 +2557,61 @@ define void @ashr_32bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind { ; RV32I-NEXT: slli s9, s9, 8 ; RV32I-NEXT: slli s10, s10, 16 ; RV32I-NEXT: slli s11, s11, 24 -; RV32I-NEXT: or s2, s7, s6 -; RV32I-NEXT: or s3, s9, s8 -; RV32I-NEXT: or s4, s11, s10 -; RV32I-NEXT: lbu s5, 0(a1) -; RV32I-NEXT: lbu s6, 1(a1) -; RV32I-NEXT: lbu s7, 2(a1) +; RV32I-NEXT: add s6, s7, s6 +; RV32I-NEXT: add s8, s9, s8 +; RV32I-NEXT: add s10, s11, s10 +; RV32I-NEXT: lbu s2, 0(a1) +; RV32I-NEXT: lbu s3, 1(a1) +; RV32I-NEXT: lbu s4, 2(a1) ; RV32I-NEXT: lbu a1, 3(a1) ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a3, a3, ra -; RV32I-NEXT: addi s8, sp, 8 +; RV32I-NEXT: add a3, a3, ra +; RV32I-NEXT: addi s5, sp, 8 ; RV32I-NEXT: slli t4, t4, 16 ; RV32I-NEXT: slli t5, t5, 24 ; RV32I-NEXT: slli s0, s0, 8 ; RV32I-NEXT: slli s1, s1, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: slli s6, s6, 8 -; RV32I-NEXT: slli s7, s7, 16 +; RV32I-NEXT: slli s3, s3, 8 +; RV32I-NEXT: slli s4, s4, 16 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or t4, t5, t4 -; RV32I-NEXT: or t5, s0, t6 -; RV32I-NEXT: or s1, a0, s1 -; RV32I-NEXT: or t6, s6, s5 -; RV32I-NEXT: or a1, a1, s7 -; RV32I-NEXT: srai s0, a0, 31 +; RV32I-NEXT: add t4, t5, t4 +; RV32I-NEXT: add t6, s0, t6 +; RV32I-NEXT: add s1, a0, s1 +; RV32I-NEXT: add s2, s3, s2 +; RV32I-NEXT: add a1, a1, s4 +; RV32I-NEXT: srai t5, a0, 31 ; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: or a4, a4, a0 -; RV32I-NEXT: or a5, a6, a5 -; RV32I-NEXT: or a6, t0, a7 -; RV32I-NEXT: or a7, t2, t1 -; RV32I-NEXT: or t0, s2, t3 -; RV32I-NEXT: or t1, s4, s3 -; RV32I-NEXT: or a3, t4, a3 -; RV32I-NEXT: or t2, s1, t5 -; RV32I-NEXT: or a0, a1, t6 -; RV32I-NEXT: sw s0, 56(sp) -; RV32I-NEXT: sw s0, 60(sp) -; RV32I-NEXT: sw s0, 64(sp) -; RV32I-NEXT: sw s0, 68(sp) -; RV32I-NEXT: sw s0, 40(sp) -; RV32I-NEXT: sw s0, 44(sp) -; RV32I-NEXT: sw s0, 48(sp) -; RV32I-NEXT: sw s0, 52(sp) -; RV32I-NEXT: sw t0, 24(sp) -; RV32I-NEXT: sw t1, 28(sp) +; RV32I-NEXT: add a4, a4, a0 +; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add a7, t0, a7 +; RV32I-NEXT: add t1, t2, t1 +; RV32I-NEXT: add t3, s6, t3 +; RV32I-NEXT: add s8, s10, s8 +; RV32I-NEXT: add a3, t4, a3 +; RV32I-NEXT: add t6, s1, t6 +; RV32I-NEXT: add a0, a1, s2 +; RV32I-NEXT: sw t5, 56(sp) +; RV32I-NEXT: sw t5, 60(sp) +; RV32I-NEXT: sw t5, 64(sp) +; RV32I-NEXT: sw t5, 68(sp) +; RV32I-NEXT: sw t5, 40(sp) +; RV32I-NEXT: sw t5, 44(sp) +; RV32I-NEXT: sw t5, 48(sp) +; RV32I-NEXT: sw t5, 52(sp) +; RV32I-NEXT: sw t3, 24(sp) +; RV32I-NEXT: sw s8, 28(sp) ; RV32I-NEXT: sw a3, 32(sp) -; RV32I-NEXT: sw t2, 36(sp) +; RV32I-NEXT: sw t6, 36(sp) ; RV32I-NEXT: sw a4, 8(sp) ; RV32I-NEXT: sw a5, 12(sp) -; RV32I-NEXT: sw a6, 16(sp) -; RV32I-NEXT: sw a7, 20(sp) +; RV32I-NEXT: sw a7, 16(sp) +; RV32I-NEXT: sw t1, 20(sp) ; RV32I-NEXT: srli a1, a0, 3 ; RV32I-NEXT: andi a3, a0, 31 ; RV32I-NEXT: andi a4, a1, 28 ; RV32I-NEXT: xori a1, a3, 31 -; RV32I-NEXT: add a4, s8, a4 +; RV32I-NEXT: add a4, s5, a4 ; RV32I-NEXT: lw a3, 0(a4) ; RV32I-NEXT: lw a5, 4(a4) ; RV32I-NEXT: lw a6, 8(a4) diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll index 2751332c9e3ae..0faa550bb422d 100644 --- a/llvm/test/CodeGen/RISCV/xaluo.ll +++ b/llvm/test/CodeGen/RISCV/xaluo.ll @@ -664,7 +664,7 @@ define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, ptr %res) { ; RV32ZICOND-NEXT: sltu a1, a3, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a5 ; RV32ZICOND-NEXT: czero.nez a0, a0, a5 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: sw a2, 0(a4) ; RV32ZICOND-NEXT: sw a3, 4(a4) ; RV32ZICOND-NEXT: ret @@ -1156,7 +1156,7 @@ define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, ptr %res) { ; RV32ZICOND-NEXT: sltu a1, a1, a3 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a5 ; RV32ZICOND-NEXT: czero.nez a0, a0, a5 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: sw a2, 0(a4) ; RV32ZICOND-NEXT: sw a3, 4(a4) ; RV32ZICOND-NEXT: ret @@ -2009,7 +2009,7 @@ define i32 @saddo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZICOND-NEXT: xor a2, a3, a2 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: saddo.select.i32: @@ -2019,7 +2019,7 @@ define i32 @saddo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV64ZICOND-NEXT: xor a2, a3, a2 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) @@ -2158,8 +2158,8 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 ; RV32ZICOND-NEXT: czero.nez a3, a3, a4 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4 -; RV32ZICOND-NEXT: or a0, a0, a2 -; RV32ZICOND-NEXT: or a1, a1, a3 +; RV32ZICOND-NEXT: add a0, a0, a2 +; RV32ZICOND-NEXT: add a1, a1, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: saddo.select.i64: @@ -2170,7 +2170,7 @@ define i64 @saddo.select.i64(i64 %v1, i64 %v2) { ; RV64ZICOND-NEXT: xor a2, a3, a2 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2) @@ -2298,7 +2298,7 @@ define i32 @uaddo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZICOND-NEXT: sltu a2, a2, a0 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: uaddo.select.i32: @@ -2307,7 +2307,7 @@ define i32 @uaddo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV64ZICOND-NEXT: sltu a2, a2, a0 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2) @@ -2432,13 +2432,13 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: sltu a4, a4, a1 ; RV32ZICOND-NEXT: czero.eqz a4, a4, a6 ; RV32ZICOND-NEXT: czero.nez a5, a5, a6 -; RV32ZICOND-NEXT: or a4, a5, a4 +; RV32ZICOND-NEXT: add a4, a5, a4 ; RV32ZICOND-NEXT: czero.nez a2, a2, a4 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 ; RV32ZICOND-NEXT: czero.nez a3, a3, a4 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4 -; RV32ZICOND-NEXT: or a0, a0, a2 -; RV32ZICOND-NEXT: or a1, a1, a3 +; RV32ZICOND-NEXT: add a0, a0, a2 +; RV32ZICOND-NEXT: add a1, a1, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: uaddo.select.i64: @@ -2447,7 +2447,7 @@ define i64 @uaddo.select.i64(i64 %v1, i64 %v2) { ; RV64ZICOND-NEXT: sltu a2, a2, a0 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2) @@ -2507,7 +2507,7 @@ define i1 @uaddo.not.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: sltu a1, a3, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 ; RV32ZICOND-NEXT: czero.nez a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: xori a0, a0, 1 ; RV32ZICOND-NEXT: ret ; @@ -2575,7 +2575,7 @@ define i32 @ssubo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZICOND-NEXT: xor a2, a2, a3 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: ssubo.select.i32: @@ -2585,7 +2585,7 @@ define i32 @ssubo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV64ZICOND-NEXT: xor a2, a3, a2 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2) @@ -2718,8 +2718,8 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 ; RV32ZICOND-NEXT: czero.nez a3, a3, a4 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4 -; RV32ZICOND-NEXT: or a0, a0, a2 -; RV32ZICOND-NEXT: or a1, a1, a3 +; RV32ZICOND-NEXT: add a0, a0, a2 +; RV32ZICOND-NEXT: add a1, a1, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: ssubo.select.i64: @@ -2730,7 +2730,7 @@ define i64 @ssubo.select.i64(i64 %v1, i64 %v2) { ; RV64ZICOND-NEXT: xor a2, a2, a3 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2) @@ -2852,7 +2852,7 @@ define i32 @usubo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZICOND-NEXT: sltu a2, a0, a2 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: usubo.select.i32: @@ -2861,7 +2861,7 @@ define i32 @usubo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV64ZICOND-NEXT: sltu a2, a0, a2 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2) @@ -2989,13 +2989,13 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: sltu a5, a1, a5 ; RV32ZICOND-NEXT: czero.eqz a5, a5, a6 ; RV32ZICOND-NEXT: czero.nez a4, a4, a6 -; RV32ZICOND-NEXT: or a4, a4, a5 +; RV32ZICOND-NEXT: add a4, a4, a5 ; RV32ZICOND-NEXT: czero.nez a2, a2, a4 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 ; RV32ZICOND-NEXT: czero.nez a3, a3, a4 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4 -; RV32ZICOND-NEXT: or a0, a0, a2 -; RV32ZICOND-NEXT: or a1, a1, a3 +; RV32ZICOND-NEXT: add a0, a0, a2 +; RV32ZICOND-NEXT: add a1, a1, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: usubo.select.i64: @@ -3004,7 +3004,7 @@ define i64 @usubo.select.i64(i64 %v1, i64 %v2) { ; RV64ZICOND-NEXT: sltu a2, a0, a2 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2) @@ -3071,7 +3071,7 @@ define i1 @usubo.not.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: sltu a1, a1, a3 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 ; RV32ZICOND-NEXT: czero.nez a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: xori a0, a0, 1 ; RV32ZICOND-NEXT: ret ; @@ -3139,7 +3139,7 @@ define i32 @smulo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZICOND-NEXT: xor a2, a2, a3 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: smulo.select.i32: @@ -3149,7 +3149,7 @@ define i32 @smulo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV64ZICOND-NEXT: xor a2, a3, a2 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2) @@ -3344,8 +3344,8 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 ; RV32ZICOND-NEXT: czero.nez a3, a3, a4 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4 -; RV32ZICOND-NEXT: or a0, a0, a2 -; RV32ZICOND-NEXT: or a1, a1, a3 +; RV32ZICOND-NEXT: add a0, a0, a2 +; RV32ZICOND-NEXT: add a1, a1, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: smulo.select.i64: @@ -3356,7 +3356,7 @@ define i64 @smulo.select.i64(i64 %v1, i64 %v2) { ; RV64ZICOND-NEXT: xor a2, a2, a3 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2) @@ -3543,7 +3543,7 @@ define i32 @umulo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV32ZICOND-NEXT: mulhu a2, a0, a1 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: umulo.select.i32: @@ -3554,7 +3554,7 @@ define i32 @umulo.select.i32(i32 signext %v1, i32 signext %v2) { ; RV64ZICOND-NEXT: srli a2, a2, 32 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2) @@ -3706,8 +3706,8 @@ define i64 @umulo.select.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: czero.eqz a0, a0, a4 ; RV32ZICOND-NEXT: czero.nez a3, a3, a4 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a4 -; RV32ZICOND-NEXT: or a0, a0, a2 -; RV32ZICOND-NEXT: or a1, a1, a3 +; RV32ZICOND-NEXT: add a0, a0, a2 +; RV32ZICOND-NEXT: add a1, a1, a3 ; RV32ZICOND-NEXT: ret ; ; RV64ZICOND-LABEL: umulo.select.i64: @@ -3715,7 +3715,7 @@ define i64 @umulo.select.i64(i64 %v1, i64 %v2) { ; RV64ZICOND-NEXT: mulhu a2, a0, a1 ; RV64ZICOND-NEXT: czero.nez a1, a1, a2 ; RV64ZICOND-NEXT: czero.eqz a0, a0, a2 -; RV64ZICOND-NEXT: or a0, a0, a1 +; RV64ZICOND-NEXT: add a0, a0, a1 ; RV64ZICOND-NEXT: ret entry: %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2) @@ -4161,7 +4161,7 @@ define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: sltu a1, a3, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 ; RV32ZICOND-NEXT: czero.nez a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: beqz a0, .LBB55_2 ; RV32ZICOND-NEXT: # %bb.1: # %overflow ; RV32ZICOND-NEXT: li a0, 0 @@ -4534,7 +4534,7 @@ define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) { ; RV32ZICOND-NEXT: sltu a1, a1, a3 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 ; RV32ZICOND-NEXT: czero.nez a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: beqz a0, .LBB59_2 ; RV32ZICOND-NEXT: # %bb.1: # %overflow ; RV32ZICOND-NEXT: li a0, 0 @@ -5270,7 +5270,7 @@ define zeroext i1 @umulo2.br.i64(i64 %v1) { ; RV32ZICOND-NEXT: sltu a1, a3, a1 ; RV32ZICOND-NEXT: czero.eqz a1, a1, a2 ; RV32ZICOND-NEXT: czero.nez a0, a0, a2 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: beqz a0, .LBB65_2 ; RV32ZICOND-NEXT: # %bb.1: # %overflow ; RV32ZICOND-NEXT: li a0, 0 diff --git a/llvm/test/CodeGen/RISCV/xandesbfhcvt.ll b/llvm/test/CodeGen/RISCV/xandesbfhcvt.ll index 72242f1dd312d..58931eba8eff9 100644 --- a/llvm/test/CodeGen/RISCV/xandesbfhcvt.ll +++ b/llvm/test/CodeGen/RISCV/xandesbfhcvt.ll @@ -32,7 +32,7 @@ define void @loadstorebf16(ptr %bf, ptr %sf) nounwind { ; XANDESBFHCVT: # %bb.0: # %entry ; XANDESBFHCVT-NEXT: lhu a2, 0(a0) ; XANDESBFHCVT-NEXT: lui a3, 1048560 -; XANDESBFHCVT-NEXT: or a2, a2, a3 +; XANDESBFHCVT-NEXT: add a2, a2, a3 ; XANDESBFHCVT-NEXT: fmv.w.x fa5, a2 ; XANDESBFHCVT-NEXT: nds.fcvt.s.bf16 fa5, fa5 ; XANDESBFHCVT-NEXT: fsw fa5, 0(a1) diff --git a/llvm/test/CodeGen/RISCV/xqciac.ll b/llvm/test/CodeGen/RISCV/xqciac.ll index 934deb5a0c327..e34e4f7731172 100644 --- a/llvm/test/CodeGen/RISCV/xqciac.ll +++ b/llvm/test/CodeGen/RISCV/xqciac.ll @@ -295,7 +295,7 @@ define dso_local i64 @shladd64(i64 %a, i64 %b) local_unnamed_addr #0 { ; RV32IM-NEXT: srli a4, a2, 1 ; RV32IM-NEXT: slli a3, a3, 31 ; RV32IM-NEXT: slli a2, a2, 31 -; RV32IM-NEXT: or a3, a3, a4 +; RV32IM-NEXT: add a3, a3, a4 ; RV32IM-NEXT: add a0, a2, a0 ; RV32IM-NEXT: sltu a2, a0, a2 ; RV32IM-NEXT: add a1, a3, a1 @@ -333,7 +333,7 @@ define dso_local i32 @shladd_ordisjoint(i32 %a, i32 %b) local_unnamed_addr #0 { ; RV32IM-LABEL: shladd_ordisjoint: ; RV32IM: # %bb.0: # %entry ; RV32IM-NEXT: slli a1, a1, 22 -; RV32IM-NEXT: or a0, a1, a0 +; RV32IM-NEXT: add a0, a1, a0 ; RV32IM-NEXT: ret ; ; RV32IMXQCIAC-LABEL: shladd_ordisjoint: @@ -409,7 +409,7 @@ define dso_local i64 @shladdc1c264(i64 %a, i64 %b) local_unnamed_addr #0 { ; RV32IM-NEXT: slli a1, a0, 23 ; RV32IM-NEXT: srli a0, a2, 12 ; RV32IM-NEXT: slli a3, a3, 20 -; RV32IM-NEXT: or a3, a3, a0 +; RV32IM-NEXT: add a3, a3, a0 ; RV32IM-NEXT: slli a0, a2, 20 ; RV32IM-NEXT: add a1, a1, a3 ; RV32IM-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll b/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll index 2fa06517508ce..5d295ac352c8b 100644 --- a/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll +++ b/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll @@ -970,17 +970,17 @@ define i8 @brev_i8(i8 %a0) { ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: slli a1, a1, 4 ; RV32I-NEXT: srli a0, a0, 28 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: andi a1, a0, 51 ; RV32I-NEXT: srli a0, a0, 2 ; RV32I-NEXT: slli a1, a1, 2 ; RV32I-NEXT: andi a0, a0, 51 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: andi a1, a0, 85 ; RV32I-NEXT: srli a0, a0, 1 ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: andi a0, a0, 85 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: brev_i8: @@ -989,17 +989,17 @@ define i8 @brev_i8(i8 %a0) { ; RV32ZBB-NEXT: slli a0, a0, 24 ; RV32ZBB-NEXT: slli a1, a1, 4 ; RV32ZBB-NEXT: srli a0, a0, 28 -; RV32ZBB-NEXT: or a0, a0, a1 +; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: andi a1, a0, 51 ; RV32ZBB-NEXT: srli a0, a0, 2 ; RV32ZBB-NEXT: slli a1, a1, 2 ; RV32ZBB-NEXT: andi a0, a0, 51 -; RV32ZBB-NEXT: or a0, a0, a1 +; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: andi a1, a0, 85 ; RV32ZBB-NEXT: srli a0, a0, 1 ; RV32ZBB-NEXT: slli a1, a1, 1 ; RV32ZBB-NEXT: andi a0, a0, 85 -; RV32ZBB-NEXT: or a0, a0, a1 +; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: ret ; ; RV32ZBBXQCIBM-LABEL: brev_i8: @@ -1019,26 +1019,26 @@ define i16 @brev_i16(i16 %a0) { ; RV32I-NEXT: lui a2, 1 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: addi a2, a2, -241 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: lui a2, 3 ; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: lui a2, 5 ; RV32I-NEXT: addi a2, a2, 1365 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 1 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: brev_i16: @@ -1052,19 +1052,19 @@ define i16 @brev_i16(i16 %a0) { ; RV32ZBB-NEXT: srli a0, a0, 20 ; RV32ZBB-NEXT: addi a2, a2, 819 ; RV32ZBB-NEXT: andi a0, a0, -241 -; RV32ZBB-NEXT: or a0, a0, a1 +; RV32ZBB-NEXT: add a0, a0, a1 ; RV32ZBB-NEXT: srli a1, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: lui a2, 5 ; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: slli a0, a0, 1 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: ret ; ; RV32ZBBXQCIBM-LABEL: brev_i16: @@ -1086,13 +1086,13 @@ define i32 @brev_i32(i32 %a0) { ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: and a2, a0, a2 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: add a1, a1, a3 ; RV32I-NEXT: lui a3, 61681 ; RV32I-NEXT: slli a2, a2, 8 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: lui a2, 209715 ; RV32I-NEXT: addi a3, a3, -241 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a1, a1, a3 @@ -1100,17 +1100,17 @@ define i32 @brev_i32(i32 %a0) { ; RV32I-NEXT: addi a2, a2, 819 ; RV32I-NEXT: addi a3, a3, 1365 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 2 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 1 ; RV32I-NEXT: and a0, a0, a3 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: slli a0, a0, 1 -; RV32I-NEXT: or a0, a1, a0 +; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: brev_i32: @@ -1124,19 +1124,19 @@ define i32 @brev_i32(i32 %a0) { ; RV32ZBB-NEXT: lui a1, 209715 ; RV32ZBB-NEXT: addi a1, a1, 819 ; RV32ZBB-NEXT: slli a0, a0, 4 -; RV32ZBB-NEXT: or a0, a2, a0 +; RV32ZBB-NEXT: add a0, a2, a0 ; RV32ZBB-NEXT: srli a2, a0, 2 ; RV32ZBB-NEXT: and a0, a0, a1 ; RV32ZBB-NEXT: and a1, a2, a1 ; RV32ZBB-NEXT: lui a2, 349525 ; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: srli a1, a0, 1 ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: slli a0, a0, 1 -; RV32ZBB-NEXT: or a0, a1, a0 +; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: ret ; ; RV32ZBBXQCIBM-LABEL: brev_i32: @@ -1158,14 +1158,14 @@ define i64 @brev_i64(i64 %a0) { ; RV32I-NEXT: srli a7, a0, 8 ; RV32I-NEXT: addi a3, a3, -256 ; RV32I-NEXT: and a2, a2, a3 -; RV32I-NEXT: or a2, a2, a4 +; RV32I-NEXT: add a2, a2, a4 ; RV32I-NEXT: srli a4, a0, 24 ; RV32I-NEXT: and a7, a7, a3 -; RV32I-NEXT: or a4, a7, a4 +; RV32I-NEXT: add a4, a7, a4 ; RV32I-NEXT: lui a7, 209715 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: slli a1, a1, 8 -; RV32I-NEXT: or a1, a5, a1 +; RV32I-NEXT: add a1, a5, a1 ; RV32I-NEXT: lui a5, 349525 ; RV32I-NEXT: and a3, a0, a3 ; RV32I-NEXT: slli a0, a0, 24 @@ -1173,9 +1173,9 @@ define i64 @brev_i64(i64 %a0) { ; RV32I-NEXT: addi a7, a7, 819 ; RV32I-NEXT: addi a5, a5, 1365 ; RV32I-NEXT: slli a3, a3, 8 -; RV32I-NEXT: or a0, a0, a3 -; RV32I-NEXT: or a1, a1, a2 -; RV32I-NEXT: or a0, a0, a4 +; RV32I-NEXT: add a0, a0, a3 +; RV32I-NEXT: add a1, a1, a2 +; RV32I-NEXT: add a0, a0, a4 ; RV32I-NEXT: srli a2, a1, 4 ; RV32I-NEXT: and a1, a1, a6 ; RV32I-NEXT: srli a3, a0, 4 @@ -1184,8 +1184,8 @@ define i64 @brev_i64(i64 %a0) { ; RV32I-NEXT: slli a1, a1, 4 ; RV32I-NEXT: and a3, a3, a6 ; RV32I-NEXT: slli a0, a0, 4 -; RV32I-NEXT: or a1, a2, a1 -; RV32I-NEXT: or a0, a3, a0 +; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: add a0, a3, a0 ; RV32I-NEXT: srli a2, a1, 2 ; RV32I-NEXT: and a1, a1, a7 ; RV32I-NEXT: srli a3, a0, 2 @@ -1194,8 +1194,8 @@ define i64 @brev_i64(i64 %a0) { ; RV32I-NEXT: slli a1, a1, 2 ; RV32I-NEXT: and a3, a3, a7 ; RV32I-NEXT: slli a0, a0, 2 -; RV32I-NEXT: or a1, a2, a1 -; RV32I-NEXT: or a0, a3, a0 +; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: add a0, a3, a0 ; RV32I-NEXT: srli a2, a1, 1 ; RV32I-NEXT: and a1, a1, a5 ; RV32I-NEXT: srli a3, a0, 1 @@ -1204,8 +1204,8 @@ define i64 @brev_i64(i64 %a0) { ; RV32I-NEXT: slli a1, a1, 1 ; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: slli a4, a0, 1 -; RV32I-NEXT: or a0, a2, a1 -; RV32I-NEXT: or a1, a3, a4 +; RV32I-NEXT: add a0, a2, a1 +; RV32I-NEXT: add a1, a3, a4 ; RV32I-NEXT: ret ; ; RV32ZBB-LABEL: brev_i64: @@ -1226,8 +1226,8 @@ define i64 @brev_i64(i64 %a0) { ; RV32ZBB-NEXT: addi a2, a2, 1365 ; RV32ZBB-NEXT: slli a1, a1, 4 ; RV32ZBB-NEXT: slli a0, a0, 4 -; RV32ZBB-NEXT: or a1, a4, a1 -; RV32ZBB-NEXT: or a0, a5, a0 +; RV32ZBB-NEXT: add a1, a4, a1 +; RV32ZBB-NEXT: add a0, a5, a0 ; RV32ZBB-NEXT: srli a4, a1, 2 ; RV32ZBB-NEXT: and a1, a1, a3 ; RV32ZBB-NEXT: srli a5, a0, 2 @@ -1236,8 +1236,8 @@ define i64 @brev_i64(i64 %a0) { ; RV32ZBB-NEXT: slli a1, a1, 2 ; RV32ZBB-NEXT: and a3, a5, a3 ; RV32ZBB-NEXT: slli a0, a0, 2 -; RV32ZBB-NEXT: or a1, a4, a1 -; RV32ZBB-NEXT: or a0, a3, a0 +; RV32ZBB-NEXT: add a1, a4, a1 +; RV32ZBB-NEXT: add a0, a3, a0 ; RV32ZBB-NEXT: srli a3, a1, 1 ; RV32ZBB-NEXT: and a1, a1, a2 ; RV32ZBB-NEXT: srli a4, a0, 1 @@ -1246,8 +1246,8 @@ define i64 @brev_i64(i64 %a0) { ; RV32ZBB-NEXT: slli a1, a1, 1 ; RV32ZBB-NEXT: and a2, a4, a2 ; RV32ZBB-NEXT: slli a4, a0, 1 -; RV32ZBB-NEXT: or a0, a3, a1 -; RV32ZBB-NEXT: or a1, a2, a4 +; RV32ZBB-NEXT: add a0, a3, a1 +; RV32ZBB-NEXT: add a1, a2, a4 ; RV32ZBB-NEXT: ret ; ; RV32ZBBXQCIBM-LABEL: brev_i64: diff --git a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll index 2a954ae1eb297..e3e793c1e2940 100644 --- a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll +++ b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll @@ -171,7 +171,7 @@ define i32 @test2(i32 %a) { ; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 10240 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32IXQCIBM-LABEL: test2: @@ -258,7 +258,7 @@ define i32 @test6(i32 %a) { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 182 ; RV32I-NEXT: addi a1, a1, -1326 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32IXQCIBM-LABEL: test6: @@ -287,7 +287,7 @@ define i32 @test7(i32 %a) { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 182 ; RV32I-NEXT: addi a1, a1, -1326 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: ret ; ; RV32IXQCIBM-LABEL: test7: @@ -315,10 +315,10 @@ define i64 @test8(i64 %a) { ; RV32I-NEXT: zext.b a0, a0 ; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: lui a2, 496944 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: add a0, a0, a2 ; RV32I-NEXT: lui a2, 9 ; RV32I-NEXT: addi a2, a2, -170 -; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: add a1, a1, a2 ; RV32I-NEXT: ret ; ; RV32IXQCIBM-LABEL: test8: diff --git a/llvm/test/CodeGen/RISCV/zcb-regalloc-hints.ll b/llvm/test/CodeGen/RISCV/zcb-regalloc-hints.ll index 6b47f0c46caeb..ff7153fec6522 100644 --- a/llvm/test/CodeGen/RISCV/zcb-regalloc-hints.ll +++ b/llvm/test/CodeGen/RISCV/zcb-regalloc-hints.ll @@ -52,9 +52,9 @@ define i64 @c_sext_h(i64 %x, i16 %y, i64 %z) { define i64 @c_zext_b(i64 %x, i8 %y, i64 %z) { ; CHECK-LABEL: c_zext_b: ; CHECK: # %bb.0: -; CHECK-NEXT: zext.b a1, a1 -; CHECK-NEXT: lui a0, 1 -; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: zext.b a0, a1 +; CHECK-NEXT: lui a1, 1 +; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: ret %a = zext i8 %y to i64 %b = or i64 %a, 4096 @@ -64,9 +64,9 @@ define i64 @c_zext_b(i64 %x, i8 %y, i64 %z) { define i64 @c_zext_h(i64 %x, i16 %y) { ; CHECK-LABEL: c_zext_h: ; CHECK: # %bb.0: -; CHECK-NEXT: zext.h a1, a1 -; CHECK-NEXT: lui a0, 4096 -; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: zext.h a0, a1 +; CHECK-NEXT: lui a1, 4096 +; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: ret %a = zext i16 %y to i64 %b = or i64 %a, 16777216 diff --git a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll index 1ef37f73b3b08..02187b24d8bfc 100644 --- a/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll +++ b/llvm/test/CodeGen/RISCV/zdinx-boundary-check.ll @@ -245,7 +245,7 @@ define void @foo7(ptr nocapture %p) nounwind { ; RV64ZDINX-NEXT: lw a2, 8(a2) ; RV64ZDINX-NEXT: lwu a1, %lo(d+4)(a1) ; RV64ZDINX-NEXT: slli a2, a2, 32 -; RV64ZDINX-NEXT: or a1, a2, a1 +; RV64ZDINX-NEXT: add a1, a2, a1 ; RV64ZDINX-NEXT: sd a1, 2044(a0) ; RV64ZDINX-NEXT: ret entry: @@ -340,7 +340,7 @@ define void @foo9(ptr nocapture %p) nounwind { ; RV64ZDINX-NEXT: lw a2, 4(a2) ; RV64ZDINX-NEXT: lwu a1, %lo(e)(a1) ; RV64ZDINX-NEXT: slli a2, a2, 32 -; RV64ZDINX-NEXT: or a1, a2, a1 +; RV64ZDINX-NEXT: add a1, a2, a1 ; RV64ZDINX-NEXT: sd a1, 2044(a0) ; RV64ZDINX-NEXT: ret entry: @@ -483,7 +483,7 @@ define double @foo13(ptr nocapture %p) nounwind { ; RV64ZDINX-NEXT: lw a1, %lo(f+8)(a0) ; RV64ZDINX-NEXT: lwu a0, %lo(f+4)(a0) ; RV64ZDINX-NEXT: slli a1, a1, 32 -; RV64ZDINX-NEXT: or a0, a1, a0 +; RV64ZDINX-NEXT: add a0, a1, a0 ; RV64ZDINX-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr @f, i64 4 diff --git a/llvm/test/CodeGen/RISCV/zicond-opts.ll b/llvm/test/CodeGen/RISCV/zicond-opts.ll index a16145d15db81..b1f5a821b8af3 100644 --- a/llvm/test/CodeGen/RISCV/zicond-opts.ll +++ b/llvm/test/CodeGen/RISCV/zicond-opts.ll @@ -69,8 +69,8 @@ define i64 @rotate_l_nez(i64 %x, i64 %rot.amt, i1 %cond) { ; RV32ZICOND-NEXT: czero.nez a1, a1, a3 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a3 ; RV32ZICOND-NEXT: not a3, a2 -; RV32ZICOND-NEXT: or a4, a5, a4 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a4, a5, a4 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: sll a1, a4, a2 ; RV32ZICOND-NEXT: srli a5, a0, 1 ; RV32ZICOND-NEXT: sll a2, a0, a2 @@ -104,8 +104,8 @@ define i64 @rotate_l_eqz(i64 %x, i64 %rot.amt, i1 %cond) { ; RV32ZICOND-NEXT: czero.nez a1, a1, a3 ; RV32ZICOND-NEXT: czero.eqz a0, a0, a3 ; RV32ZICOND-NEXT: not a3, a2 -; RV32ZICOND-NEXT: or a4, a5, a4 -; RV32ZICOND-NEXT: or a0, a0, a1 +; RV32ZICOND-NEXT: add a4, a5, a4 +; RV32ZICOND-NEXT: add a0, a0, a1 ; RV32ZICOND-NEXT: sll a1, a4, a2 ; RV32ZICOND-NEXT: srli a5, a0, 1 ; RV32ZICOND-NEXT: sll a2, a0, a2 @@ -202,7 +202,7 @@ define i64 @select_imm_reg_2048(i64 %t, i1 %cond) { ; RV32ZICOND-NEXT: bseti a3, zero, 11 ; RV32ZICOND-NEXT: czero.nez a0, a0, a2 ; RV32ZICOND-NEXT: czero.eqz a3, a3, a2 -; RV32ZICOND-NEXT: or a0, a3, a0 +; RV32ZICOND-NEXT: add a0, a3, a0 ; RV32ZICOND-NEXT: czero.nez a1, a1, a2 ; RV32ZICOND-NEXT: ret ; @@ -212,7 +212,7 @@ define i64 @select_imm_reg_2048(i64 %t, i1 %cond) { ; RV64ZICOND-NEXT: bseti a2, zero, 11 ; RV64ZICOND-NEXT: czero.nez a0, a0, a1 ; RV64ZICOND-NEXT: czero.eqz a1, a2, a1 -; RV64ZICOND-NEXT: or a0, a1, a0 +; RV64ZICOND-NEXT: add a0, a1, a0 ; RV64ZICOND-NEXT: ret %4 = select i1 %cond, i64 2048, i64 %t ret i64 %4 diff --git a/llvm/test/CodeGen/RISCV/zilsd.ll b/llvm/test/CodeGen/RISCV/zilsd.ll index 048ce964f9e18..64908e4dc6930 100644 --- a/llvm/test/CodeGen/RISCV/zilsd.ll +++ b/llvm/test/CodeGen/RISCV/zilsd.ll @@ -42,19 +42,19 @@ define i64 @load_unaligned(ptr %p) { ; SLOW-NEXT: slli a1, a1, 8 ; SLOW-NEXT: slli a2, a2, 16 ; SLOW-NEXT: slli a3, a3, 24 -; SLOW-NEXT: or a1, a1, a4 -; SLOW-NEXT: or a2, a3, a2 +; SLOW-NEXT: add a1, a1, a4 +; SLOW-NEXT: add a2, a3, a2 ; SLOW-NEXT: lbu a3, 5(a0) ; SLOW-NEXT: lbu a4, 4(a0) ; SLOW-NEXT: lbu a5, 6(a0) ; SLOW-NEXT: lbu a0, 7(a0) ; SLOW-NEXT: slli a3, a3, 8 -; SLOW-NEXT: or a3, a3, a4 +; SLOW-NEXT: add a3, a3, a4 ; SLOW-NEXT: slli a5, a5, 16 ; SLOW-NEXT: slli a0, a0, 24 -; SLOW-NEXT: or a5, a0, a5 -; SLOW-NEXT: or a0, a2, a1 -; SLOW-NEXT: or a1, a5, a3 +; SLOW-NEXT: add a5, a0, a5 +; SLOW-NEXT: add a0, a2, a1 +; SLOW-NEXT: add a1, a5, a3 ; SLOW-NEXT: ret ; ; FAST-LABEL: load_unaligned: