diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index ce2b4a5f6f2e9..c2f974111f165 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -248,6 +248,9 @@ extern char &AMDGPUPreloadKernArgPrologLegacyID;
 void initializeAMDGPUPreloadKernelArgumentsLegacyPass(PassRegistry &);
 extern char &AMDGPUPreloadKernelArgumentsLegacyID;
 
+void initializeAMDGPUNextUseAnalysisWrapperPass(PassRegistry &);
+extern char &AMDGPUNextUseAnalysisID;
+
 // Passes common to R600 and SI
 FunctionPass *createAMDGPUPromoteAlloca();
 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.cpp b/llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.cpp
new file mode 100644
index 0000000000000..8bdc109e80182
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.cpp
@@ -0,0 +1,445 @@
+#include "AMDGPU.h"
+#include "AMDGPUNextUseAnalysis.h"
+
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/PostOrderIterator.h"
+#include "llvm/ADT/iterator_range.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionAnalysis.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/InitializePasses.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/Passes/PassBuilder.h"
+#include "llvm/Passes/PassPlugin.h"
+#include "llvm/Support/Timer.h"
+
+#define DEBUG_TYPE "amdgpu-next-use"
+
+using namespace llvm;
+
+// Command-line option to enable timing instrumentation
+static cl::opt<bool> EnableTimers("amdgpu-next-use-analysis-timers",
+                                  cl::desc("Enable timing for Next Use Analysis"),
+                                  cl::init(false), cl::Hidden);
+
+// Static timers for performance tracking across all analysis runs
+static llvm::TimerGroup TG("amdgpu-next-use", "AMDGPU Next Use Analysis");
+static llvm::Timer AnalyzeTimer("analyze", "Time spent in analyze()", TG);
+static llvm::Timer GetDistanceTimer("getNextUseDistance", 
+                                     "Time spent in getNextUseDistance()", TG);
+
+// Three-tier ranking system for spiller decisions
+unsigned NextUseResult::materializeForRank(int64_t Stored, unsigned SnapshotOffset) const {
+  int64_t Mat64 = materialize(Stored, SnapshotOffset);
+
+  // Tier 1: Finite distances (0 to LoopTag-1) → return as-is
+  // Tier 2: Loop-exit distances (LoopTag to DeadTag-1) → map to 60000-64999 range
+  // Tier 3: Dead registers (DeadTag+) → return Infinity (65535)
+  if (Mat64 >= DeadTag) {
+    return Infinity;  // Tier 3: Dead registers get maximum distance
+  }
+  if (Mat64 >= LoopTag) {
+    // Tier 2: Loop-exit distances get mapped to high range [60000, 64999]
+    int64_t LoopRemainder = Mat64 - LoopTag;
+    // Clamp the remainder to fit in available range (5000 values)
+    unsigned ClampedRemainder = static_cast<unsigned>(
+        std::min(LoopRemainder, static_cast<int64_t>(4999)));
+    return 60000 + ClampedRemainder;
+  }
+  if (Mat64 <= 0) {
+    return 0;  // Tier 1: Zero-distance for immediate uses
+  }
+  return static_cast<unsigned>(Mat64);  // Tier 1: Finite distances as-is
+}
+
+
+void NextUseResult::init(const MachineFunction &MF) {
+  for (auto *L : LI->getLoopsInPreorder()) {
+    SmallVector<std::pair<MachineBasicBlock *, MachineBasicBlock *>> Exiting;
+    L->getExitEdges(Exiting);
+    for (auto P : Exiting) {
+      LoopExits[P.first->getNumber()] = P.second->getNumber();
+    }
+  }
+}
+
+void NextUseResult::analyze(const MachineFunction &MF) {
+  // Upward-exposed distances are only necessary to convey the data flow from
+  // the block to its predecessors. No need to store it beyond the analyze
+  // function as the analysis users are only interested in the use distances
+  // relatively to the given MI or the given block end.
+  DenseMap<unsigned, VRegDistances> UpwardNextUses;
+  if (EnableTimers)
+    AnalyzeTimer.startTimer();
+  bool Changed = true;
+  while (Changed) {
+    Changed = false;
+    for (const auto *MBB : post_order(&MF)) {
+      unsigned Offset = 0;
+      unsigned MBBNum = MBB->getNumber();
+      VRegDistances Curr, Prev;
+      if (UpwardNextUses.contains(MBBNum)) {
+        Prev = UpwardNextUses[MBBNum];
+      }
+
+      LLVM_DEBUG({
+        dbgs() << "\nMerging successors for "
+               << "MBB_" << MBB->getNumber() << "." << MBB->getName() << "\n";
+      });
+
+      for (auto *Succ : successors(MBB)) {
+        unsigned SuccNum = Succ->getNumber();
+
+        if (!UpwardNextUses.contains(SuccNum))
+          continue;
+
+        VRegDistances SuccDist = UpwardNextUses[SuccNum];
+        LLVM_DEBUG({
+          dbgs() << "\nMerging "
+                 << "MBB_" << Succ->getNumber() << "." << Succ->getName() << "\n";
+        });
+
+        // Check if the edge from MBB to Succ goes out of the Loop
+        int64_t EdgeWeight = 0;
+        if (LoopExits.contains(MBB->getNumber())) {
+          unsigned ExitTo = LoopExits[MBB->getNumber()];
+          if (SuccNum == ExitTo)
+            EdgeWeight = LoopTag;
+        }
+
+        if (LI->getLoopDepth(MBB) < LI->getLoopDepth(Succ)) {
+          // MBB->Succ is entering the Succ's loop
+          // Clear out the Loop-Exiting weights.
+          for (auto &P : SuccDist) {
+            auto &Dists = P.second;
+            // Collect items that need to be updated to avoid iterator invalidation
+            SmallVector<std::pair<LaneBitmask, int64_t>, 4> ToUpdate;
+            for (auto R : Dists) {
+              if (R.second >= LoopTag) {
+                ToUpdate.push_back(R);
+              }
+            }
+            // Now apply the updates
+            for (auto R : ToUpdate) {
+              Dists.erase(R);
+              R.second -= LoopTag;
+              Dists.insert(R);
+            }
+          }
+        }
+        LLVM_DEBUG({
+          dbgs() << "\nCurr:";
+          printVregDistances(Curr /*, 0 - we're at the block bottom*/);
+          dbgs() << "\nSucc:";
+          printVregDistances(SuccDist, EntryOff[SuccNum], EdgeWeight);
+        });
+
+        // Filter out successor's PHI operands with SourceBlock != MBB
+        // PHI operands are only live on their specific incoming edge
+        for (auto &PHI : Succ->phis()) {
+          // Check each PHI operand pair (value, source block)
+          for (unsigned OpIdx = 1; OpIdx < PHI.getNumOperands(); OpIdx += 2) {
+            const MachineOperand &UseOp = PHI.getOperand(OpIdx);
+            const MachineOperand &BlockOp = PHI.getOperand(OpIdx + 1);
+
+            // Skip if this operand doesn't come from current MBB
+            if (BlockOp.getMBB() != MBB) {
+              VRegMaskPair PhiVMP(UseOp, TRI, MRI);
+              // Remove this PHI operand from the successor distances
+              SuccDist.clear(PhiVMP);
+            }
+          }
+        }
+
+        Curr.merge(SuccDist, EntryOff[SuccNum], EdgeWeight);
+        LLVM_DEBUG({
+          dbgs() << "\nCurr after merge:";
+          printVregDistances(Curr);
+        });
+      }
+
+      NextUseMap[MBBNum].Bottom = Curr;
+
+      for (auto &MI : make_range(MBB->rbegin(), MBB->rend())) {
+
+        for (auto &MO : MI.operands()) {
+
+          // Only process virtual register operands
+          // Undef operands don't represent real uses
+          if (!MO.isReg() || !MO.getReg().isVirtual() || MO.isUndef())
+            continue;
+
+          VRegMaskPair P(MO, TRI, MRI);
+          if (MO.isUse()) {
+            Curr.insert(P, -(int64_t)Offset);
+            UsedInBlock[MBB->getNumber()].insert(P);
+          } else if (MO.isDef()) {
+            Curr.clear(P);
+            UsedInBlock[MBB->getNumber()].remove(P);
+          }
+        }
+        NextUseMap[MBBNum].InstrDist[&MI] = Curr;
+        NextUseMap[MBBNum].InstrOffset[&MI] = Offset;
+        // printVregDistances(Curr, Offset);
+        if (!MI.isPHI())
+          ++Offset;
+      }
+
+      // EntryOff needs the TOTAL instruction count for correct predecessor distances
+      // while InstrOffset uses individual instruction offsets for materialization
+
+      LLVM_DEBUG({
+        dbgs() << "\nFinal distances for MBB_" << MBB->getNumber() << "."
+               << MBB->getName() << "\n";
+        printVregDistances(Curr, Offset);
+        dbgs() << "\nPrevious distances for MBB_" << MBB->getNumber() << "."
+               << MBB->getName() << "\n";
+        printVregDistances(Prev, Offset);
+        dbgs() << "\nUsed in block:\n";
+        dumpUsedInBlock();
+      });
+
+      // EntryOff -offset of the first instruction in the block top-down walk
+      EntryOff[MBBNum] = Offset;
+      UpwardNextUses[MBBNum] = std::move(Curr);
+
+      bool Changed4MBB = (Prev != UpwardNextUses[MBBNum]);
+
+      Changed |= Changed4MBB;
+    }
+  }
+  // Dump complete analysis results for testing
+  LLVM_DEBUG(dumpAllNextUseDistances(MF));
+  if (EnableTimers) {
+    AnalyzeTimer.stopTimer();
+    TG.print(llvm::errs());
+  }
+}
+
+void NextUseResult::getFromSortedRecords(
+    const VRegDistances::SortedRecords &Dists, LaneBitmask Mask,
+    unsigned SnapshotOffset, unsigned &D) {
+  LLVM_DEBUG({
+    dbgs() << "Mask : [" << PrintLaneMask(Mask) << "]  "
+           << "SnapshotOffset=" << SnapshotOffset << "\n";
+  });
+
+  // Records are sorted by stored value in increasing order. Since all entries
+  // in this snapshot share the same SnapshotOffset, ordering by stored value
+  // is equivalent to ordering by materialized distance.
+  for (const auto &P : Dists) {
+    const LaneBitmask UseMask = P.first;
+    LLVM_DEBUG(dbgs() << "  UseMask : [" << PrintLaneMask(UseMask) << "]\n");
+
+    // Require full coverage: a use contributes only if it covers the queried
+    // lanes.
+    if ((Mask & UseMask) == Mask) {
+      // Use materializeForRank for three-tier ranking system
+      int64_t Stored = static_cast<int64_t>(P.second);
+      D = materializeForRank(Stored, SnapshotOffset);
+
+      break; // first covering record is the nearest for this snapshot
+    }
+  }
+}
+
+SmallVector<VRegMaskPair>
+NextUseResult::getSortedSubregUses(const MachineBasicBlock::iterator I,
+                                   const VRegMaskPair VMP) {
+  SmallVector<VRegMaskPair> Result;
+  const MachineBasicBlock *MBB = I->getParent();
+  unsigned MBBNum = MBB->getNumber();
+  if (NextUseMap.contains(MBBNum) &&
+      NextUseMap[MBBNum].InstrDist.contains(&*I)) {
+    // VRegDistances Dists = NextUseMap[MBBNum].InstrDist[&*I];
+    if (NextUseMap[MBBNum].InstrDist[&*I].contains(VMP.getVReg())) {
+      VRegDistances::SortedRecords Dists =
+          NextUseMap[MBBNum].InstrDist[&*I][VMP.getVReg()];
+      LLVM_DEBUG({
+        dbgs() << "Mask : [" << PrintLaneMask(VMP.getLaneMask()) << "]\n";
+      });
+      for (auto P : reverse(Dists)) {
+        LaneBitmask UseMask = P.first;
+        LLVM_DEBUG({
+          dbgs() << "Used mask : [" << PrintLaneMask(UseMask) << "]\n";
+        });
+        if ((UseMask & VMP.getLaneMask()) == UseMask) {
+          Result.push_back({VMP.getVReg(), UseMask});
+        }
+      }
+    }
+  }
+  return Result;
+}
+
+SmallVector<VRegMaskPair>
+NextUseResult::getSortedSubregUses(const MachineBasicBlock &MBB,
+                                   const VRegMaskPair VMP) {
+  SmallVector<VRegMaskPair> Result;
+  unsigned MBBNum = MBB.getNumber();
+  if (NextUseMap.contains(MBBNum) &&
+      NextUseMap[MBBNum].Bottom.contains(VMP.getVReg())) {
+    VRegDistances::SortedRecords Dists =
+        NextUseMap[MBBNum].Bottom[VMP.getVReg()];
+    LLVM_DEBUG({
+      dbgs() << "Mask : [" << PrintLaneMask(VMP.getLaneMask()) << "]\n";
+    });
+    for (auto P : reverse(Dists)) {
+      LaneBitmask UseMask = P.first;
+      LLVM_DEBUG(dbgs() << "Used mask : [" << PrintLaneMask(UseMask) << "]\n");
+      if ((UseMask & VMP.getLaneMask()) == UseMask) {
+        Result.push_back({VMP.getVReg(), UseMask});
+      }
+    }
+  }
+  return Result;
+}
+
+void NextUseResult::dumpUsedInBlock() {
+  for (auto P : UsedInBlock) {
+    dbgs() << "MBB_" << P.first << ":\n";
+    for (auto VMP : P.second) {
+      dbgs() << "[ " << printReg(VMP.getVReg()) << " : <"
+             << PrintLaneMask(VMP.getLaneMask()) << "> ]\n";
+    }
+  }
+}
+
+unsigned NextUseResult::getNextUseDistance(const MachineBasicBlock::iterator I,
+                                           const VRegMaskPair VMP) {
+  if (EnableTimers)
+    GetDistanceTimer.startTimer();
+  
+  unsigned Dist = Infinity;
+  const MachineBasicBlock *MBB = I->getParent();
+  unsigned MBBNum = MBB->getNumber();
+  if (NextUseMap.contains(MBBNum) &&
+      NextUseMap[MBBNum].InstrDist.contains(&*I)) {
+    VRegDistances Dists = NextUseMap[MBBNum].InstrDist[&*I];
+    if (NextUseMap[MBBNum].InstrDist[&*I].contains(VMP.getVReg())) {
+      // printSortedRecords(Dists[VMP.VReg], VMP.VReg);
+      unsigned SnapOff = NextUseMap[MBBNum].InstrOffset[&*I];
+      getFromSortedRecords(Dists[VMP.getVReg()], VMP.getLaneMask(),
+                           SnapOff, Dist);
+    }
+  }
+
+  if (EnableTimers)
+    GetDistanceTimer.stopTimer();
+  return Dist;
+}
+
+unsigned NextUseResult::getNextUseDistance(const MachineBasicBlock &MBB,
+                                           const VRegMaskPair VMP) {
+  if (EnableTimers)
+    GetDistanceTimer.startTimer();
+  
+  unsigned Dist = Infinity;
+  unsigned MBBNum = MBB.getNumber();
+  if (NextUseMap.contains(MBBNum)) {
+    if (NextUseMap[MBBNum].Bottom.contains(VMP.getVReg())) {
+      getFromSortedRecords(NextUseMap[MBBNum].Bottom[VMP.getVReg()],
+                           VMP.getLaneMask(), 0, Dist);
+    }
+  }
+  
+  if (EnableTimers)
+    GetDistanceTimer.stopTimer();
+  return Dist;
+}
+
+AMDGPUNextUseAnalysis::Result
+AMDGPUNextUseAnalysis::run(MachineFunction &MF,
+                           MachineFunctionAnalysisManager &MFAM) {
+  return AMDGPUNextUseAnalysis::Result(MF,
+                                       MFAM.getResult<SlotIndexesAnalysis>(MF),
+                                       MFAM.getResult<MachineLoopAnalysis>(MF));
+}
+
+AnalysisKey AMDGPUNextUseAnalysis::Key;
+
+char AMDGPUNextUseAnalysisWrapper::ID = 0;
+char &llvm::AMDGPUNextUseAnalysisID = AMDGPUNextUseAnalysisWrapper::ID;
+INITIALIZE_PASS_BEGIN(AMDGPUNextUseAnalysisWrapper, "amdgpu-next-use",
+                      "AMDGPU Next Use Analysis", false, false)
+INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
+INITIALIZE_PASS_END(AMDGPUNextUseAnalysisWrapper, "amdgpu-next-use",
+                    "AMDGPU Next Use Analysis", false, false)
+
+bool AMDGPUNextUseAnalysisWrapper::runOnMachineFunction(MachineFunction &MF) {
+  NU.Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
+  NU.LI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+  NU.MRI = &MF.getRegInfo();
+  NU.TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
+  assert(NU.MRI->isSSA());
+  NU.init(MF);
+  NU.analyze(MF);
+  //  LLVM_DEBUG(NU.dump());
+  return false;
+}
+
+void AMDGPUNextUseAnalysisWrapper::getAnalysisUsage(AnalysisUsage &AU) const {
+  AU.setPreservesAll();
+  AU.addRequired<MachineLoopInfoWrapperPass>();
+  AU.addRequired<SlotIndexesWrapperPass>();
+  MachineFunctionPass::getAnalysisUsage(AU);
+}
+
+AMDGPUNextUseAnalysisWrapper::AMDGPUNextUseAnalysisWrapper()
+    : MachineFunctionPass(ID) {
+  initializeAMDGPUNextUseAnalysisWrapperPass(*PassRegistry::getPassRegistry());
+}
+
+void NextUseResult::dumpAllNextUseDistances(const MachineFunction &MF) {
+  LLVM_DEBUG(dbgs() << "=== NextUseAnalysis Results for " << MF.getName()
+                    << " ===\n");
+
+  for (const auto &MBB : MF) {
+    const unsigned MBBNum = MBB.getNumber();
+    LLVM_DEBUG(dbgs() << "\n--- MBB_" << MBBNum << " ---\n");
+
+    if (!NextUseMap.contains(MBBNum)) {
+      LLVM_DEBUG(dbgs() << "  No analysis data for this block\n");
+      continue;
+    }
+
+    const NextUseInfo &Info = NextUseMap.at(MBBNum);
+
+    // Per-instruction dump (materialized with per-MI snapshot offset).
+    for (auto II = MBB.begin(), IE = MBB.end(); II != IE; ++II) {
+      const MachineInstr &MI = *II;
+
+      LLVM_DEBUG(dbgs() << "  Instr: ");
+      LLVM_DEBUG(MI.print(dbgs(), /*IsStandalone=*/false, /*SkipOpers=*/false,
+                          /*SkipDebugLoc=*/true, /*AddNewLine=*/false));
+      LLVM_DEBUG(dbgs() << "\n");
+
+      LLVM_DEBUG(dbgs() << "    Next-use distances:\n");
+      if (Info.InstrDist.contains(&MI)) {
+        const VRegDistances &Dists = Info.InstrDist.at(&MI);
+        const unsigned SnapOff = Info.InstrOffset.lookup(&MI); // 0 if absent
+        const bool Any =
+            printVregDistances(Dists, SnapOff, 0, dbgs(), "      ");
+        if (!Any)
+          LLVM_DEBUG(dbgs() << "      (no register uses)\n");
+      } else {
+        LLVM_DEBUG(dbgs() << "      (no distance data)\n");
+      }
+      LLVM_DEBUG(dbgs() << "\n");
+    }
+
+    // Block-end dump (materialized with offset = 0).
+    LLVM_DEBUG(dbgs() << "  Block End Distances:\n");
+    const bool AnyEnd = printVregDistances(Info.Bottom, /*SnapshotOffset=*/0,
+                                           /* EdgeWeight */ 0, dbgs(), "    ");
+    if (!AnyEnd)
+      LLVM_DEBUG(dbgs() << "    (no registers live at block end)\n");
+  }
+
+  LLVM_DEBUG(dbgs() << "\n=== End NextUseAnalysis Results ===\n");
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.h b/llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.h
new file mode 100644
index 0000000000000..c27fa182b521e
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPUNextUseAnalysis.h
@@ -0,0 +1,442 @@
+//===- AMDGPUNextUseAnalysis.h ----------------------------------------*- C++-
+//*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_NEXT_USE_ANALYSIS_H
+#define LLVM_LIB_TARGET_AMDGPU_NEXT_USE_ANALYSIS_H
+
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+
+#include "AMDGPUSSARAUtils.h"
+#include "GCNSubtarget.h"
+#include "SIRegisterInfo.h"
+#include "VRegMaskPair.h"
+
+#include <algorithm>
+#include <limits>
+#include <set>
+
+using namespace llvm;
+
+// namespace {
+
+// Helper function for rebasing successor distances into current block frame
+static inline int64_t rebaseFromSucc(int64_t SuccStored, unsigned SuccEntryOff,
+                                     int64_t EdgeWeight /*0 or LoopTag*/) {
+  // Move succ-relative value into "current block end" frame.
+  return (int64_t)SuccStored + (int64_t)SuccEntryOff + (int64_t)EdgeWeight;
+}
+
+class NextUseResult {
+  friend class AMDGPUNextUseAnalysisWrapper;
+  SlotIndexes *Indexes;
+  const MachineRegisterInfo *MRI;
+  const SIRegisterInfo *TRI;
+  MachineLoopInfo *LI;
+
+  class VRegDistances {
+
+    using Record = std::pair<LaneBitmask, int64_t>;
+    struct CompareByDist {
+      bool operator()(const Record &LHS, const Record &RHS) const {
+        if (LHS.second != RHS.second)     // Different distances
+          return LHS.second < RHS.second; // Closest first
+        return LHS.first.getAsInteger() <
+               RHS.first.getAsInteger(); // Tiebreaker
+      }
+    };
+
+  public:
+    using SortedRecords = std::set<Record, CompareByDist>;
+
+  private:
+    DenseMap<unsigned, SortedRecords> NextUseMap;
+
+  public:
+    auto begin() { return NextUseMap.begin(); }
+    auto end() { return NextUseMap.end(); }
+
+    auto begin() const { return NextUseMap.begin(); }
+    auto end() const { return NextUseMap.end(); }
+
+    size_t size() const { return NextUseMap.size(); }
+    std::pair<bool, SortedRecords> get(unsigned Key) const {
+      if (NextUseMap.contains(Key))
+        return {true, NextUseMap.find(Key)->second};
+      return {false, SortedRecords()};
+    }
+
+    SortedRecords &operator[](unsigned Key) { return NextUseMap[Key]; }
+
+    SmallVector<unsigned> keys() {
+      SmallVector<unsigned> Keys;
+      for (auto P : NextUseMap)
+        Keys.push_back(P.first);
+      return Keys;
+    }
+
+    bool contains(unsigned Key) { return NextUseMap.contains(Key); }
+
+    bool insert(VRegMaskPair VMP, int64_t Dist) {
+      Record R(VMP.getLaneMask(), Dist);
+      if (NextUseMap.contains(VMP.getVReg())) {
+        SortedRecords &Dists = NextUseMap[VMP.getVReg()];
+
+        if (Dists.find(R) == Dists.end()) {
+          SmallVector<SortedRecords::iterator, 4> ToErase;
+
+          for (auto It = Dists.begin(); It != Dists.end(); ++It) {
+            const Record &D = *It;
+
+            // Check if existing use covers the new use
+            if ((R.first & D.first) == R.first) {
+              // Existing use covers new use
+              if (D.second <= R.second) {
+                // Existing use is closer or equal → reject new use
+                return false;
+              }
+              // Existing use is further → continue (might replace it)
+            }
+
+            // Check if new use covers existing use
+            if ((D.first & R.first) == D.first) {
+              // New use covers existing use
+              if (R.second <= D.second) {
+                // New use is closer → mark existing for removal
+                ToErase.push_back(It);
+              } else {
+                // New use is further → reject it
+                return false;
+              }
+            }
+          }
+
+          // Remove all records that the new use supersedes
+          for (auto It : ToErase) {
+            Dists.erase(It);
+          }
+
+          // Add new record
+          return Dists.insert(R).second;
+        }
+        // Record already exists!
+        return false;
+      }
+      return NextUseMap[VMP.getVReg()].insert(R).second;
+    }
+
+    void clear(VRegMaskPair VMP) {
+      if (NextUseMap.contains(VMP.getVReg())) {
+        auto &Dists = NextUseMap[VMP.getVReg()];
+        for (auto It = Dists.begin(); It != Dists.end(); ) {
+          LaneBitmask Masked = It->first & ~VMP.getLaneMask();
+          if (Masked.none()) {
+            It = Dists.erase(It);
+          } else {
+            ++It;
+          }
+        }
+        if (Dists.empty())
+          NextUseMap.erase(VMP.getVReg());
+      }
+    }
+
+    bool operator==(const VRegDistances Other) const {
+
+      if (Other.size() != size())
+        return false;
+
+      for (auto P : NextUseMap) {
+
+        std::pair<bool, SortedRecords> OtherDists = Other.get(P.getFirst());
+        if (!OtherDists.first)
+          return false;
+        SortedRecords &Dists = P.getSecond();
+
+        if (Dists.size() != OtherDists.second.size())
+          return false;
+
+        for (auto R : OtherDists.second) {
+          SortedRecords::iterator I = Dists.find(R);
+          if (I == Dists.end())
+            return false;
+          if (R.second != I->second)
+            return false;
+        }
+      }
+
+      return true;
+    }
+
+    bool operator!=(const VRegDistances &Other) const {
+      return !operator==(Other);
+    }
+
+    // Adjust 'Other' (which is in successor's frame) into *this* frame,
+    // then take pointwise min by LaneBitmask.
+    void merge(const VRegDistances &Other, unsigned SuccEntryOff,
+               int64_t EdgeWeight = 0) {
+      for (const auto &P : Other) {
+        unsigned Key = P.getFirst();
+        const auto &OtherDists = P.getSecond();
+        auto &MineDists = NextUseMap[Key]; // creates empty if not present
+
+        for (const auto &D : OtherDists) {
+          // D.second is the successor's STORED value (signed, relative to succ)
+          int64_t Rebased = rebaseFromSucc(D.second, SuccEntryOff, EdgeWeight);
+
+          // Try to find existing record with the same LaneBitmask
+          auto It =
+              std::find_if(MineDists.begin(), MineDists.end(),
+                           [&](const Record &R) { return R.first == D.first; });
+
+          if (It == MineDists.end()) {
+            // No record → insert
+            MineDists.insert({D.first, Rebased});
+          } else if (It->second > Rebased) { // take MIN in the current frame
+            // Furthest wins (adjusted is more distant) → replace
+            MineDists.erase(It);
+            MineDists.insert({D.first, Rebased});
+          }
+        }
+      }
+    }
+  };
+  class NextUseInfo {
+    // FIXME: need to elaborate proper class interface!
+  public:
+    VRegDistances Bottom;
+    DenseMap<const MachineInstr *, VRegDistances> InstrDist;
+    DenseMap<const MachineInstr *, unsigned>
+        InstrOffset; // offset at that MI snapshot
+  };
+
+  DenseMap<unsigned, NextUseInfo> NextUseMap;
+  // Map MBB number to the maximal offset in given by the bottm-up walk
+  DenseMap<unsigned, unsigned> EntryOff;
+
+public:
+private:
+  DenseMap<unsigned, SetVector<VRegMaskPair>> UsedInBlock;
+  DenseMap<int, int> LoopExits;
+  // Signed tag used to mark "outside current loop" in stored values.
+  // Must be >> any finite distance you can accumulate in one function.
+  static constexpr int64_t LoopTag = (int64_t)1 << 40; // ~1e12 headroom
+  static constexpr int64_t DeadTag = (int64_t)1 << 60; // ~1e18, >> LoopTag
+
+  // Unsigned Infinity for external API/DAG users who want a sentinel.
+  static constexpr unsigned PrintedInfinity = std::numeric_limits<unsigned>::max();
+
+  const uint16_t Infinity = std::numeric_limits<unsigned short>::max();
+  void init(const MachineFunction &MF);
+  void analyze(const MachineFunction &MF);
+
+  // Core materialization: convert stored relative value + snapshot offset
+  // to full materialized distance with bounds checking.
+  int64_t materialize(int64_t Stored, unsigned SnapshotOffset) const {
+    int64_t Mat64 = Stored + static_cast<int64_t>(SnapshotOffset);
+    return (Mat64 <= 0) ? 0 : Mat64;
+  }
+
+  // Structure for enhanced distance ranking and printing
+  struct PrintDist {
+    bool IsInfinity;
+    bool IsDead;
+    int64_t LoopMultiplier;  // How many LoopTags are in the distance
+    int64_t Rema;            // remainder after extracting LoopTags
+    
+    PrintDist(int64_t Mat64) {
+      if (Mat64 >= DeadTag) {
+        IsInfinity = false;
+        IsDead = true;
+        LoopMultiplier = 0;
+        Rema = Mat64 - DeadTag;
+      } else if (Mat64 >= LoopTag) {
+        IsInfinity = true;
+        IsDead = false;
+        // Extract LoopTag multiples and remainder
+        LoopMultiplier = Mat64 / LoopTag;
+        Rema = Mat64 % LoopTag;
+      } else {
+        IsInfinity = false;
+        IsDead = false;
+        LoopMultiplier = 0;
+        Rema = Mat64;
+      }
+    }
+  };
+
+  // Materializer for spiller use: applies three-tier ranking system
+  unsigned materializeForRank(int64_t Stored, unsigned SnapshotOffset) const;
+
+  // Materializer for printing: returns PrintDist structure
+  PrintDist materializeForPrint(int64_t Stored, unsigned SnapshotOffset) const {
+    return PrintDist(materialize(Stored, SnapshotOffset));
+  }
+
+  // Print each (VReg, LaneMask) entry with materialized distances.
+  // Returns true if at least one record was printed.
+  LLVM_DUMP_METHOD
+  bool printSortedRecords(const VRegDistances::SortedRecords &Records,
+                          unsigned VReg, unsigned SnapshotOffset,
+                          int64_t EdgeWeigth = 0, raw_ostream &O = dbgs(),
+                          StringRef Indent = "      ") const {
+    bool Any = false;
+    O << "\n";
+    for (const auto &X : Records) {
+      const LaneBitmask UseMask = X.first;
+      const int64_t Stored = X.second; // stored relative (may be negative)
+
+      // Use enhanced materialization for display that shows three-tier
+      // structure
+      PrintDist PDist =
+          materializeForPrint(Stored + EdgeWeigth, SnapshotOffset);
+
+      O << Indent << "Vreg: ";
+      const LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg(VReg);
+      if (UseMask != FullMask) {
+        const unsigned SubRegIdx = getSubRegIndexForLaneMask(UseMask, TRI);
+        O << printReg(VReg, TRI, SubRegIdx, MRI);
+      } else {
+        O << printReg(VReg, TRI);
+      }
+
+      if (PDist.IsDead)
+        O << "[ DEAD ]\n";
+      else if (PDist.IsInfinity)
+        if (PDist.LoopMultiplier == 1)
+          O << "[ LoopTag+" << PDist.Rema << " ]\n";
+        else if (PDist.LoopMultiplier > 1)
+          O << "[ LoopTag*" << PDist.LoopMultiplier << "+" << PDist.Rema << " ]\n";
+        else
+          O << "[ INF+" << PDist.Rema << " ]\n";
+      else
+        O << "[ " << PDist.Rema << " ]\n";
+
+      Any = true;
+    }
+    return Any;
+  }
+
+  // Iterate VRegs and delegate to printSortedRecords.
+  // Returns true if anything was printed.
+  LLVM_DUMP_METHOD
+  bool printVregDistances(const VRegDistances &D, unsigned SnapshotOffset,
+                          int64_t EdgeWeight = 0, raw_ostream &O = dbgs(),
+                          StringRef Indent = "      ") const {
+    bool Any = false;
+    for (const auto &P : D) {
+      Any |= printSortedRecords(P.second, P.first, SnapshotOffset, EdgeWeight,
+                                O, Indent);
+    }
+    return Any;
+  }
+
+  // Backward-compat shim for block-end printing (offset = 0, default indent).
+  LLVM_DUMP_METHOD
+  bool printVregDistances(const VRegDistances &D,
+                          raw_ostream &O = dbgs()) const {
+    return printVregDistances(D, /*SnapshotOffset=*/0, /*EdgeWeight*/ 0, O);
+  }
+
+  void clear() {
+    NextUseMap.clear();
+    LoopExits.clear();
+  }
+
+public:
+  NextUseResult() = default;
+  NextUseResult(const MachineFunction &MF, SlotIndexes &SI, MachineLoopInfo &LI)
+      : Indexes(&SI), MRI(&MF.getRegInfo()), LI(&LI) {
+    init(MF);
+    analyze(MF);
+  }
+  ~NextUseResult() { clear(); }
+
+  // void print(raw_ostream &O) const { dump(O); }
+
+  unsigned getNextUseDistance(const MachineBasicBlock &MBB,
+                              const VRegMaskPair VMP);
+  unsigned getNextUseDistance(const MachineBasicBlock::iterator I,
+                              const VRegMaskPair VMP);
+  void getFromSortedRecords(const VRegDistances::SortedRecords &Dists,
+                            LaneBitmask Mask, unsigned SnapshotOffset,
+                            unsigned &D);
+
+  SmallVector<VRegMaskPair>
+  getSortedSubregUses(const MachineBasicBlock::iterator I,
+                      const VRegMaskPair VMP);
+
+  SmallVector<VRegMaskPair> getSortedSubregUses(const MachineBasicBlock &MBB,
+                                                const VRegMaskPair VMP);
+
+  bool isDead(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
+              const VRegMaskPair VMP) {
+    if (!VMP.getVReg().isVirtual())
+      report_fatal_error("Only virtual registers allowed!\n", true);
+    // FIXME: We use the same Infinity value to indicate both invalid distance
+    // and too long for out of block values. It is okay if the use out of block
+    // is at least one instruction further then the end of loop exit. In this
+    // case we have a distance Infinity + 1 and hence register is not considered
+    // dead. What if the register is defined by the last instruction in the loop
+    // exit block and out of loop use is in PHI? By design the dist of all PHIs
+    // from the beginning of block are ZERO and hence the distance of
+    // out-of-the-loop use will be exactly Infinity So, the register will be
+    // mistakenly considered DEAD! On another hand, any predecessor of the block
+    // containing PHI must have a branch as the last instruction. In this case
+    // the current design works.
+    return I == MBB.end() ? getNextUseDistance(MBB, VMP) == Infinity
+                          : getNextUseDistance(I, VMP) == Infinity;
+  }
+
+  SetVector<VRegMaskPair> &usedInBlock(MachineBasicBlock &MBB) {
+    return UsedInBlock[MBB.getNumber()];
+  }
+
+  LLVM_DUMP_METHOD void dumpUsedInBlock();
+
+  /// Dump complete next-use analysis results for testing
+  LLVM_DUMP_METHOD void dumpAllNextUseDistances(const MachineFunction &MF);
+};
+
+class AMDGPUNextUseAnalysis : public AnalysisInfoMixin<AMDGPUNextUseAnalysis> {
+  friend AnalysisInfoMixin<AMDGPUNextUseAnalysis>;
+  static AnalysisKey Key;
+
+public:
+  using Result = NextUseResult;
+  Result run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM);
+};
+
+class AMDGPUNextUseAnalysisWrapper : public MachineFunctionPass {
+  NextUseResult NU;
+
+public:
+  static char ID;
+
+  AMDGPUNextUseAnalysisWrapper();
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+  /// Pass entry point; Calculates LiveIntervals.
+  bool runOnMachineFunction(MachineFunction &) override;
+  void releaseMemory() override { NU.clear(); }
+
+  // /// Implement the dump method.
+  // void print(raw_ostream &O, const Module * = nullptr) const override {
+  //   NU.print(O);
+  // }
+
+  NextUseResult &getNU() { return NU; }
+};
+
+//}
+
+#endif // LLVM_LIB_TARGET_AMDGPU_NEXT_USE_ANALYSIS_H
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSSARAUtils.h b/llvm/lib/Target/AMDGPU/AMDGPUSSARAUtils.h
new file mode 100644
index 0000000000000..0bb163eed59a9
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSSARAUtils.h
@@ -0,0 +1,69 @@
+//===------- AMDGPUSSARAUtils.h ----------------------------------------*- C++-
+//*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_SSA_RA_UTILS_H
+#define LLVM_LIB_TARGET_AMDGPU_SSA_RA_UTILS_H
+
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
+#include "SIRegisterInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+using namespace llvm;
+
+inline LaneBitmask getOperandLaneMask(const MachineOperand &MO,
+                                      const SIRegisterInfo *TRI,
+                                      MachineRegisterInfo *MRI) {
+  assert(MO.isReg() && MO.getReg().isVirtual() &&
+         "Error: Only virtual register allowed!\n");
+  if (MO.getSubReg())
+    return TRI->getSubRegIndexLaneMask(MO.getSubReg());
+  return MRI->getMaxLaneMaskForVReg(MO.getReg());
+}
+
+inline unsigned getSubRegIndexForLaneMask(LaneBitmask Mask,
+                                          const SIRegisterInfo *TRI) {
+  for (unsigned Idx = 1; Idx < TRI->getNumSubRegIndices(); ++Idx) {
+    if (TRI->getSubRegIndexLaneMask(Idx) == Mask)
+      return Idx;
+  }
+  return AMDGPU::NoRegister;
+}
+
+inline SmallVector<unsigned>
+getCoveringSubRegsForLaneMask(LaneBitmask Mask, const TargetRegisterClass *RC,
+                              const SIRegisterInfo *TRI) {
+  SmallVector<unsigned> Candidates;
+  for (unsigned SubIdx = 1; SubIdx < TRI->getNumSubRegIndices(); ++SubIdx) {
+    if (!TRI->getSubClassWithSubReg(RC, SubIdx))
+      continue;
+
+    LaneBitmask SubMask = TRI->getSubRegIndexLaneMask(SubIdx);
+    if ((SubMask & Mask).any()) {
+      Candidates.push_back(SubIdx);
+    }
+  }
+
+  SmallVector<unsigned> OptimalSubIndices;
+  llvm::stable_sort(Candidates, [&](unsigned A, unsigned B) {
+    return TRI->getSubRegIndexLaneMask(A).getNumLanes() >
+           TRI->getSubRegIndexLaneMask(B).getNumLanes();
+  });
+  for (unsigned SubIdx : Candidates) {
+    LaneBitmask SubMask = TRI->getSubRegIndexLaneMask(SubIdx);
+    if ((Mask & SubMask) == SubMask) {
+      OptimalSubIndices.push_back(SubIdx);
+      Mask &= ~SubMask; // remove covered bits
+      if (Mask.none())
+        break;
+    }
+  }
+  return OptimalSubIndices;
+}
+#endif // LLVM_LIB_TARGET_AMDGPU_SSA_RA_UTILS_H
\ No newline at end of file
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 4958a200de4e0..f5a99a863f735 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -587,6 +587,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
   initializeAMDGPUReserveWWMRegsLegacyPass(*PR);
   initializeAMDGPURewriteAGPRCopyMFMALegacyPass(*PR);
   initializeAMDGPURewriteOutArgumentsPass(*PR);
+  initializeAMDGPUNextUseAnalysisWrapperPass(*PR);
   initializeAMDGPURewriteUndefForPHILegacyPass(*PR);
   initializeSIAnnotateControlFlowLegacyPass(*PR);
   initializeAMDGPUInsertDelayAluLegacyPass(*PR);
diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt
index 13f727b68c0d9..201b65b32b21e 100644
--- a/llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -186,6 +186,7 @@ add_llvm_target(AMDGPUCodeGen
   SIRegisterInfo.cpp
   SIShrinkInstructions.cpp
   SIWholeQuadMode.cpp
+  AMDGPUNextUseAnalysis.cpp
 
   LINK_COMPONENTS
   AMDGPUDesc
diff --git a/llvm/lib/Target/AMDGPU/VRegMaskPair.h b/llvm/lib/Target/AMDGPU/VRegMaskPair.h
new file mode 100644
index 0000000000000..e2f588dcb5bef
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/VRegMaskPair.h
@@ -0,0 +1,398 @@
+//===------- VRegMaskPair.h ----------------------------------------*-
+// C++-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// ile
+/// rief Defines VRegMaskPair and VRegMaskPairSet for managing sets of
+/// virtual registers and their lane masks.
+///
+/// Set operations (union, intersection, subtraction) are implemented based on
+/// *subregister coverage logic* rather than exact equality. This means:
+/// - Two VRegMaskPairs are considered overlapping if their LaneMasks overlap.
+/// - Intersection and subtraction operate on *overlapping masks*, not exact
+/// matches.
+///
+//===----------------------------------------------------------------------===//
+#ifndef LLVM_LIB_TARGET_VREGMASKPAIR_H
+#define LLVM_LIB_TARGET_VREGMASKPAIR_H
+
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Register.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/Support/Compiler.h"
+#include <cassert>
+
+class VRegMaskPairSet;
+
+class VRegMaskPair {
+  friend class VRegMaskPairSet;
+
+  Register VReg;
+  LaneBitmask LaneMask;
+
+public:
+  VRegMaskPair(Register VReg, LaneBitmask LaneMask)
+      : VReg(VReg), LaneMask(LaneMask) {}
+
+  VRegMaskPair() : VReg(AMDGPU::NoRegister), LaneMask(LaneBitmask::getNone()) {}
+  VRegMaskPair(const VRegMaskPair &Other) = default;
+  VRegMaskPair(VRegMaskPair &&Other) = default;
+  VRegMaskPair &operator=(const VRegMaskPair &Other) = default;
+  VRegMaskPair &operator=(VRegMaskPair &&Other) = default;
+
+  VRegMaskPair(const MachineOperand MO, const SIRegisterInfo *TRI,
+               const MachineRegisterInfo *MRI) {
+    assert(MO.isReg() && "Not a register operand!");
+    assert(MO.getReg().isVirtual() && "Not a virtual register!");
+    VReg = MO.getReg();
+    LaneMask = MO.getSubReg() ? TRI->getSubRegIndexLaneMask(MO.getSubReg())
+                              : MRI->getMaxLaneMaskForVReg(VReg);
+  }
+
+  const Register getVReg() const { return VReg; }
+  const LaneBitmask getLaneMask() const { return LaneMask; }
+
+  unsigned getSubReg(const MachineRegisterInfo *MRI,
+                     const SIRegisterInfo *TRI) const {
+    LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(VReg);
+    if (LaneMask == Mask)
+      return AMDGPU::NoRegister;
+    return getSubRegIndexForLaneMask(LaneMask, TRI);
+  }
+
+  const TargetRegisterClass *getRegClass(const MachineRegisterInfo *MRI,
+                                         const SIRegisterInfo *TRI) const {
+    const TargetRegisterClass *RC = TRI->getRegClassForReg(*MRI, VReg);
+    LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(VReg);
+    if (LaneMask != Mask) {
+      unsigned SubRegIdx = getSubRegIndexForLaneMask(LaneMask, TRI);
+      return TRI->getSubRegisterClass(RC, SubRegIdx);
+    }
+    return RC;
+  }
+
+  unsigned getSizeInRegs(const SIRegisterInfo *TRI) const {
+    return TRI->getNumCoveredRegs(LaneMask);
+  }
+
+  bool operator==(const VRegMaskPair &other) const {
+    return VReg == other.VReg && LaneMask == other.LaneMask;
+  }
+};
+
+class LaneCoverageResult {
+  friend class VRegMaskPairSet;
+  LaneBitmask Data;
+  LaneBitmask Covered;
+  LaneBitmask NotCovered;
+
+public:
+  LaneCoverageResult() = default;
+  LaneCoverageResult(const LaneBitmask Mask) : Data(Mask), NotCovered(Mask){};
+  bool isFullyCovered() { return Data == Covered; }
+  bool isFullyUncovered() { return Data == NotCovered; }
+  LaneBitmask getCovered() { return Covered; }
+  LaneBitmask getNotCovered() { return NotCovered; }
+};
+
+class VRegMaskPairSet {
+
+  using MaskSet = std::set<LaneBitmask>;
+  using SetStorageT = DenseMap<Register, MaskSet>;
+  using LinearStorageT = std::vector<VRegMaskPair>;
+
+  SetStorageT SetStorage;
+  LinearStorageT LinearStorage;
+
+public:
+  VRegMaskPairSet() = default;
+
+  template <typename ContainerT,
+            typename = std::enable_if_t<std::is_same<
+                typename ContainerT::value_type, VRegMaskPair>::value>>
+  VRegMaskPairSet(const ContainerT &Vec) {
+    for (const auto &VMP : Vec)
+      insert(VMP);
+  }
+
+  template <typename ContainerT,
+            typename = std::enable_if_t<std::is_same<
+                typename ContainerT::value_type, VRegMaskPair>::value>>
+  VRegMaskPairSet(ContainerT &&Vec) {
+    for (auto &&VMP : Vec)
+      insert(std::move(VMP));
+  }
+
+  bool insert(const VRegMaskPair &VMP) {
+    auto &MaskSet = SetStorage[VMP.VReg];
+    auto Inserted = MaskSet.insert(VMP.LaneMask);
+    if (!Inserted.second)
+      return false;
+    LinearStorage.push_back(VMP);
+    return true;
+  }
+
+  template <typename InputIt> void insert(InputIt First, InputIt Last) {
+    for (auto It = First; It != Last; ++It)
+      insert(*It);
+  }
+
+  void remove(const VRegMaskPair &VMP) {
+    auto MapIt = SetStorage.find(VMP.VReg);
+    if (MapIt == SetStorage.end())
+      return;
+
+    size_t Erased = MapIt->second.erase(VMP.LaneMask);
+    if (!Erased)
+      return;
+
+    if (MapIt->second.empty())
+      SetStorage.erase(MapIt);
+
+    auto VecIt = std::find(LinearStorage.begin(), LinearStorage.end(), VMP);
+    if (VecIt != LinearStorage.end()) {
+      LinearStorage.erase(VecIt);
+    } else {
+      llvm_unreachable("Inconsistent LinearStorage: VMP missing on remove");
+    }
+  }
+
+  template <typename Predicate> void remove_if(Predicate Pred) {
+    for (auto It = LinearStorage.begin(); It != LinearStorage.end();) {
+      const VRegMaskPair VMP = *It;
+      if (Pred(VMP)) {
+        It = LinearStorage.erase(It);
+        SetStorage[VMP.VReg].erase(VMP.LaneMask);
+        if (SetStorage[VMP.VReg].empty())
+          SetStorage.erase(VMP.VReg);
+      } else {
+        ++It;
+      }
+    }
+  }
+
+  bool count(const VRegMaskPair &VMP) const {
+    auto It = SetStorage.find(VMP.VReg);
+    if (It == SetStorage.end())
+      return false;
+
+    return It->second.count(VMP.LaneMask) > 0;
+  }
+
+  bool contains(const VRegMaskPair &VMP) const {
+    auto It = SetStorage.find(VMP.VReg);
+    return It != SetStorage.end() && It->second.find(VMP.LaneMask) != It->second.end();
+  }
+
+  void clear() {
+    SetStorage.clear();
+    LinearStorage.clear();
+  }
+
+  size_t size() const { return LinearStorage.size(); }
+  bool empty() const { return LinearStorage.empty(); }
+
+  void sort(llvm::function_ref<bool(const VRegMaskPair &, const VRegMaskPair &)>
+                Cmp) {
+    std::sort(LinearStorage.begin(), LinearStorage.end(), Cmp);
+  }
+
+  VRegMaskPair pop_back_val() {
+    assert(!LinearStorage.empty() && "Pop from empty set");
+    VRegMaskPair VMP = LinearStorage.back();
+    LinearStorage.pop_back();
+
+    auto It = SetStorage.find(VMP.VReg);
+    assert(It != SetStorage.end() && "Inconsistent SetStorage");
+    It->second.erase(VMP.LaneMask);
+    if (It->second.empty())
+      SetStorage.erase(It);
+
+    return VMP;
+  }
+
+  LaneCoverageResult getCoverage(const VRegMaskPair &VMP) const {
+    LaneCoverageResult Result(VMP.LaneMask);
+    auto It = SetStorage.find(VMP.VReg);
+    if (It != SetStorage.end()) {
+      MaskSet Masks = It->second;
+      for (auto Mask : Masks) {
+        Result.Covered |= (Mask & VMP.LaneMask);
+      }
+      Result.NotCovered = (VMP.LaneMask & ~Result.Covered);
+    }
+    return Result;
+  }
+
+  bool operator==(const VRegMaskPairSet &Other) const {
+    if (SetStorage.size() != Other.SetStorage.size())
+      return false;
+
+    for (const auto &Entry : SetStorage) {
+      auto It = Other.SetStorage.find(Entry.first);
+      if (It == Other.SetStorage.end())
+        return false;
+
+      if (Entry.second != It->second)
+        return false;
+    }
+
+    return true;
+  }
+
+  template <typename ContainerT>
+  VRegMaskPairSet &operator=(const ContainerT &Vec) {
+    static_assert(
+        std::is_same<typename ContainerT::value_type, VRegMaskPair>::value,
+        "Container must hold VRegMaskPair elements");
+
+    clear();
+    for (const auto &VMP : Vec)
+      insert(VMP);
+    return *this;
+  }
+
+  // Set operations based on subregister coverage logic
+
+  /// Adds all elements from Other whose (VReg, LaneMask) overlap with none
+  /// in *this.
+  void set_union(const VRegMaskPairSet &Other) {
+    for (const auto &VMP : Other)
+      insert(VMP);
+  }
+
+  /// Keeps only those elements in *this that are at least partially covered
+  /// by Other.
+  void set_intersect(const VRegMaskPairSet &Other) {
+    std::vector<VRegMaskPair> ToInsert;
+    remove_if([&](const VRegMaskPair &VMP) {
+      LaneCoverageResult Cov = Other.getCoverage(VMP);
+      if (Cov.isFullyUncovered())
+        return true;
+
+      if (!Cov.isFullyCovered()) {
+        ToInsert.push_back({VMP.VReg, Cov.getCovered()});
+        return true; // remove current, will reinsert trimmed version
+      }
+
+      return false; // keep as-is
+    });
+
+    insert(ToInsert.begin(), ToInsert.end());
+  }
+
+  /// Removes elements from *this that are at least partially covered by
+  /// Other.
+  void set_subtract(const VRegMaskPairSet &Other) {
+    std::vector<VRegMaskPair> ToInsert;
+    remove_if([&](const VRegMaskPair &VMP) {
+      LaneCoverageResult Cov = Other.getCoverage(VMP);
+      if (Cov.isFullyCovered())
+        return true;
+
+      if (!Cov.isFullyUncovered()) {
+        ToInsert.push_back({VMP.VReg, Cov.getNotCovered()});
+        return true; // remove and reinsert uncovered part
+      }
+
+      return false;
+    });
+
+    insert(ToInsert.begin(), ToInsert.end());
+  }
+
+  /// Returns the union (join) of this set and Other under coverage logic.
+  VRegMaskPairSet set_join(const VRegMaskPairSet &Other) const {
+    VRegMaskPairSet Result = *this;
+    Result.set_union(Other);
+    return Result;
+  }
+
+  /// Returns the intersection of this set and Other based on partial
+  /// overlap.
+  VRegMaskPairSet set_intersection(const VRegMaskPairSet &Other) const {
+    VRegMaskPairSet Result;
+    for (const auto &VMP : *this) {
+      LaneCoverageResult Cov = Other.getCoverage(VMP);
+      if (!Cov.isFullyUncovered()) {
+        Result.insert({VMP.VReg, Cov.getCovered()});
+      }
+    }
+    return Result;
+  }
+
+  /// Returns all elements of *this that do not overlap with anything in
+  /// Other.
+  VRegMaskPairSet set_difference(const VRegMaskPairSet &Other) const {
+    VRegMaskPairSet Result;
+    for (const auto &VMP : *this) {
+      LaneCoverageResult Cov = Other.getCoverage(VMP);
+      if (!Cov.isFullyCovered()) {
+        Result.insert({VMP.VReg, Cov.getNotCovered()});
+      }
+    }
+    return Result;
+  }
+
+  // Debug
+  void dump() const {
+    dbgs() << "=== VRegMaskPairSet Dump ===\n";
+
+    dbgs() << "SetStorage:\n";
+    for (const auto &Entry : SetStorage) {
+      dbgs() << "  VReg: " << printReg(Entry.first) << " => { ";
+      for (const auto &Mask : Entry.second) {
+        dbgs() << PrintLaneMask(Mask) << " ";
+      }
+      dbgs() << "}\n";
+    }
+
+    dbgs() << "LinearStorage (insertion order):\n";
+    for (const auto &VMP : LinearStorage) {
+      dbgs() << "  (" << printReg(VMP.getVReg()) << ", "
+             << PrintLaneMask(VMP.getLaneMask()) << ")\n";
+    }
+
+    dbgs() << "=============================\n";
+  }
+
+  // Iterators
+  using iterator = LinearStorageT::const_iterator;
+  iterator begin() const { return LinearStorage.begin(); }
+  iterator end() const { return LinearStorage.end(); }
+};
+
+namespace llvm {
+template <> struct DenseMapInfo<VRegMaskPair> {
+  static inline VRegMaskPair getEmptyKey() {
+    return {Register(DenseMapInfo<unsigned>::getEmptyKey()),
+            LaneBitmask(0xFFFFFFFFFFFFFFFFULL)};
+  }
+
+  static inline VRegMaskPair getTombstoneKey() {
+    return {Register(DenseMapInfo<unsigned>::getTombstoneKey()),
+            LaneBitmask(0xFFFFFFFFFFFFFFFEULL)};
+  }
+
+  static unsigned getHashValue(const VRegMaskPair &P) {
+    return DenseMapInfo<unsigned>::getHashValue(P.getVReg().id()) ^
+           DenseMapInfo<uint64_t>::getHashValue(P.getLaneMask().getAsInteger());
+  }
+
+  static bool isEqual(const VRegMaskPair &LHS, const VRegMaskPair &RHS) {
+    return DenseMapInfo<unsigned>::isEqual(LHS.getVReg().id(),
+                                           RHS.getVReg().id()) &&
+           DenseMapInfo<uint64_t>::isEqual(LHS.getLaneMask().getAsInteger(),
+                                           RHS.getLaneMask().getAsInteger());
+  }
+};
+
+} // namespace llvm
+#endif // LLVM_LIB_TARGET_VREGMASKPAIR_H
\ No newline at end of file
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/README.md b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/README.md
new file mode 100644
index 0000000000000..2cf6d44ef8a1f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/README.md
@@ -0,0 +1,116 @@
+# AMDGPU NextUseAnalysis
+
+This directory contains comprehensive tests for the AMDGPU NextUseAnalysis pass, which implements a three-tier ranking system for spiller decisions with EdgeWeight parameter support.
+
+## Overview
+
+The NextUseAnalysis pass calculates next-use distances for virtual registers to help the spiller make optimal decisions about which registers to spill. The analysis implements a sophisticated three-tier ranking system:
+
+- **Tier 1**: Finite distances (0 to LoopTag-1) - immediate uses
+- **Tier 2**: Loop-exit distances (LoopTag to DeadTag-1) - mapped to high range [60000, 64999]  
+- **Tier 3**: Dead registers (DeadTag+) - assigned maximum distance (65535)
+
+## EdgeWeight Parameter
+
+The analysis includes an `EdgeWeight` parameter that adds weight to distances when crossing loop exit edges:
+
+```cpp
+int64_t EdgeWeight = 0;
+if (LoopExits.contains(MBB->getNumber())) {
+  unsigned ExitTo = LoopExits[MBB->getNumber()];
+  if (SuccNum == ExitTo)
+    EdgeWeight = LoopTag;
+}
+```
+
+This ensures that registers used after loop exits are deprioritized for spilling within the loop.
+
+## Test Suite Structure
+
+### Basic Control Flow Tests
+- **`simple-linear-block-distances.mir`** - Linear control flow with conditional branches
+- **`simple-loop-3blocks.mir`** - Simple loop with minimal basic blocks
+
+### Single Loop Tests  
+- **`complex-single-loop-a.mir`** - Complex single loop with multiple internal paths
+- **`complex-single-loop-b.mir`** - Another variant of complex single loop
+- **`complex-single-loop.mir`** - Additional single loop complexity test
+
+### Sequential Loop Tests
+- **`sequence_2_loops.mir`** - Two loops executed sequentially
+- **`multi_exit_loop_followed_by_simple_loop.mir`** - Multi-exit loop followed by simple loop
+
+### Nested Loop Tests (True Nesting)
+- **`inner_cfg_in_2_nesteed_loops.mir`** - Inner control flow within 2 nested loops
+- **`if_else_with_loops_nested_in_2_outer_loops.mir`** - Conditional logic with loops nested in outer loops
+- **`loop_nested_in_3_outer_loops_complex_cfg.mir`** - Deep nesting with complex control flow
+- **`three_loops_sequence_nested_in_outer_loop.mir`** - Sequential loops within an outer loop container
+- **`triple-nested-loops.mir`** - Three levels of true loop nesting
+
+### Side Exit Tests
+- **`nested-loops-with-side-exits-a.mir`** - Nested loops with early exit paths
+- **`nested-loops-with-side-exits-b.mir`** - Alternative nested loops with side exits
+
+### Complex Control Flow Tests
+- **`complex-control-flow-11blocks.mir`** - Complex control flow with 11 basic blocks
+- **`complex-control-flow-14blocks.mir`** - More complex control flow with 14 basic blocks
+
+### Ranking System Tests
+- **`three-tier-ranking-nested-loops.mir`** - Specific test for the three-tier ranking system
+
+## Test Validation
+
+All tests include comprehensive CHECK patterns that validate:
+
+1. **Analysis Output Format**: Proper structure of NextUseAnalysis results
+2. **Distance Calculations**: Correct next-use distance computation
+3. **EdgeWeight Application**: Proper handling of loop-exit edge weights
+4. **Three-Tier Ranking**: Correct categorization into finite/loop-exit/dead tiers
+5. **Register Tracking**: Accurate virtual register next-use information
+
+## Running Tests
+
+To run all NextUseAnalysis tests:
+
+```bash
+cd /path/to/llvm-project/llvm/test/CodeGen/AMDGPU/NextUseAnalysis
+llvm-lit -v .
+```
+
+To run a specific test:
+
+```bash
+llvm-lit -v simple-loop-3blocks.mir
+```
+
+## Test Generation
+
+Tests were generated using the automated `update_test_checks.py` script:
+
+```bash
+python3 update_test_checks.py <test_file.mir> <path_to_llc>
+```
+
+This ensures consistent CHECK pattern formatting and comprehensive coverage of the analysis output.
+
+## Implementation Details
+
+The tests validate the core functionality:
+
+- **Loop Exit Detection**: Tests verify proper identification of loop exit edges
+- **Distance Materialization**: Validates the `materializeForRank()` function
+- **Offset Handling**: Ensures correct instruction offset calculations  
+- **Successor Merging**: Tests proper merging of successor block distances
+- **Three-Tier System**: Validates the ranking system across all complexity levels
+
+## Coverage
+
+The test suite provides comprehensive coverage across:
+- 17 test files
+- Simple to extremely complex control flow patterns
+- All three ranking tiers
+- Various loop nesting scenarios
+- EdgeWeight parameter functionality
+- 100% pass rate validation
+
+This ensures the NextUseAnalysis implementation is production-ready and handles all expected AMDGPU spilling scenarios.
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
new file mode 100644
index 0000000000000..b589afaee3792
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
@@ -0,0 +1,1269 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test2 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %27:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %26:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %27[ 14 ]
+# CHECK: Instr: %25:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %27[ 13 ]
+# CHECK: Instr: %24:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %27[ 12 ]
+# CHECK: Instr: %32:vgpr_32 = V_AND_B32_e64 1, killed %24, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %33:sreg_32 = V_CMP_NE_U32_e64 1, killed %32, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %27[ 10 ]
+# CHECK: Instr: %34:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %27[ 9 ]
+# CHECK: Instr: %1:sreg_32 = SI_IF %33, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 7 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %27[ 8 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %33[ 3 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %33[ 3 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %4:sreg_32 = PHI %37, %bb.3, %90, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %33[ 17 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Instr: %2:vreg_64 = PHI undef %35:vreg_64, %bb.3, %22, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %33[ 17 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Instr: %3:vreg_64 = PHI %6, %bb.3, undef %39:vreg_64, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %33[ 17 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Instr: SI_END_CF killed %7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %33[ 16 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %27[ 10 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Instr: %102:sreg_32 = S_AND_B32 killed %4, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %33[ 15 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %27[ 9 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Instr: %101:sreg_32 = COPY killed %102
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 7 ]
+# CHECK: Vreg: %33[ 14 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %27[ 8 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %33[ 13 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %33[ 13 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %63:vgpr_32 = DS_READ_U16_gfx9 %25, 0, 0, implicit $exec :: (load (s16) from %ir.p, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %33[ 10 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %20[ 9 ]
+# CHECK: Vreg: %27[ 17 ]
+# CHECK: Instr: %64:vgpr_32 = DS_READ_U16_gfx9 %25, 2, 0, implicit $exec :: (load (s16) from %ir.p + 2, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 15 ]
+# CHECK: Vreg: %33[ 9 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %63[ 4 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %20[ 8 ]
+# CHECK: Vreg: %27[ 16 ]
+# CHECK: Instr: %65:vgpr_32 = DS_READ_U16_gfx9 %25, 4, 0, implicit $exec :: (load (s16) from %ir.p + 4, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 3 ]
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %33[ 8 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %20[ 7 ]
+# CHECK: Vreg: %27[ 15 ]
+# CHECK: Instr: %66:vgpr_32 = DS_READ_U16_gfx9 %25, 6, 0, implicit $exec :: (load (s16) from %ir.p + 6, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 2 ]
+# CHECK: Vreg: %26[ 13 ]
+# CHECK: Vreg: %33[ 7 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %63[ 2 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %27[ 14 ]
+# CHECK: Instr: %68:vgpr_32 = V_LSHL_OR_B32_e64 killed %66, 16, killed %65, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %33[ 6 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %25[ 15 ]
+# CHECK: Vreg: %20[ 5 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 13 ]
+# CHECK: Instr: %69:vgpr_32 = V_LSHL_OR_B32_e64 killed %64, 16, killed %63, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %33[ 5 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %68[ 1 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %20[ 4 ]
+# CHECK: Vreg: %27[ 12 ]
+# CHECK: Instr: %88:vreg_64 = REG_SEQUENCE killed %69, %subreg.sub0, killed %68, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %33[ 4 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %25[ 13 ]
+# CHECK: Vreg: %20[ 3 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Instr: %5:vreg_64 = COPY killed %88
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %33[ 3 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %25[ 12 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %27[ 10 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Instr: %95:sreg_32 = COPY $exec_lo
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %33[ 2 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %27[ 9 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Instr: %98:sreg_32 = S_ANDN2_B32 killed %20, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 7 ]
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %25[ 10 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %27[ 8 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Vreg: %95[ 3 ]
+# CHECK: Instr: %99:sreg_32 = S_AND_B32 killed %33, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: Instr: %97:sreg_32 = S_OR_B32 killed %98, killed %99, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Vreg: %95[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %6:vreg_64 = DS_READ_B64_gfx9 %25, 8, 0, implicit $exec :: (load (s64) from %ir.gep2, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 13 ]
+# CHECK: Vreg: %33[ 2 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %27[ 14 ]
+# CHECK: Instr: %37:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %27[ 13 ]
+# CHECK: Instr: %7:sreg_32 = SI_IF %33, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %27[ 12 ]
+# CHECK: Instr: S_BRANCH %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %33[ 17 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %33[ 17 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %9:sreg_32 = PHI %14, %bb.6, %92, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %8:vreg_64 = PHI %12, %bb.6, %17, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: SI_END_CF killed %16, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Instr: %10:sreg_32 = SI_IF killed %9, %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %27[ 4 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %76:vreg_64 = DS_READ2_B32_gfx9 killed %25, 6, 7, 0, implicit $exec :: (load (s64) from %ir.gep3, align 4, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Instr: %104:vgpr_32, %106:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %76.sub0, killed %26, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %76:sub0[ 0 ]
+# CHECK: Vreg: %76:sub1[ 1 ]
+# CHECK: Instr: %105:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %76.sub1, killed %27, killed %106, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %104[ 1 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %76:sub1[ 0 ]
+# CHECK: Instr: %11:vreg_64 = REG_SEQUENCE killed %104, %subreg.sub0, killed %105, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %15:sreg_32 = PHI %20, %bb.8, %97, %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %14:sreg_32 = PHI %34, %bb.8, %95, %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %12:vreg_64 = PHI %18, %bb.8, undef %61:vreg_64, %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %13:vreg_64 = PHI %19, %bb.8, %5, %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %12[ 3 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: SI_END_CF killed %21, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %13:sub0[ 3 ]
+# CHECK: Vreg: %13:sub1[ 4 ]
+# CHECK: Vreg: %27[ 4 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %12[ 2 ]
+# CHECK: Instr: %16:sreg_32 = SI_IF killed %15, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %13:sub0[ 2 ]
+# CHECK: Vreg: %13:sub1[ 3 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %13:sub0[ 1 ]
+# CHECK: Vreg: %13:sub1[ 2 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %13:sub0[ 1 ]
+# CHECK: Vreg: %13:sub1[ 2 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: %112:vgpr_32, %114:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %13.sub0, %26, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %16[ 6 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %13:sub0[ 0 ]
+# CHECK: Vreg: %13:sub1[ 1 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Instr: %113:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %13.sub1, %27, killed %114, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %16[ 5 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %13:sub1[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %112[ 1 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Instr: %17:vreg_64 = REG_SEQUENCE killed %112, %subreg.sub0, killed %113, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %16[ 4 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %27[ 9 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Instr: %93:sreg_32 = S_ANDN2_B32 killed %14, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 7 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %16[ 3 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %27[ 8 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Instr: %92:sreg_32 = COPY killed %93
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %16[ 2 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: %20:sreg_32 = PHI %34, %bb.0, %101, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %33[ 13 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Instr: %18:vreg_64 = PHI undef %29:vreg_64, %bb.0, %2, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %33[ 13 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Instr: %19:vreg_64 = PHI undef %29:vreg_64, %bb.0, %3, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %33[ 13 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Instr: %21:sreg_32 = SI_ELSE killed %1, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %33[ 12 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %33[ 11 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %33[ 11 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: --- MBB_9 ---
+# CHECK: Instr: %41:vgpr_32 = DS_READ_U8_gfx9 %25, 32, 0, implicit $exec :: (load (s8) from %ir.gep4, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %7[ 19 ]
+# CHECK: Vreg: %33[ 35 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %27[ 15 ]
+# CHECK: Instr: %42:vgpr_32 = DS_READ_U8_gfx9 %25, 33, 0, implicit $exec :: (load (s8) from %ir.gep4 + 1, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 13 ]
+# CHECK: Vreg: %7[ 18 ]
+# CHECK: Vreg: %33[ 34 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %27[ 14 ]
+# CHECK: Vreg: %41[ 10 ]
+# CHECK: Instr: %43:vgpr_32 = DS_READ_U8_gfx9 %25, 34, 0, implicit $exec :: (load (s8) from %ir.gep4 + 2, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %7[ 17 ]
+# CHECK: Vreg: %33[ 33 ]
+# CHECK: Vreg: %42[ 9 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %27[ 13 ]
+# CHECK: Vreg: %41[ 9 ]
+# CHECK: Instr: %44:vgpr_32 = DS_READ_U8_gfx9 %25, 35, 0, implicit $exec :: (load (s8) from %ir.gep4 + 3, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %7[ 16 ]
+# CHECK: Vreg: %33[ 32 ]
+# CHECK: Vreg: %42[ 8 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %27[ 12 ]
+# CHECK: Vreg: %41[ 8 ]
+# CHECK: Vreg: %43[ 9 ]
+# CHECK: Instr: %45:vgpr_32 = DS_READ_U8_gfx9 %25, 36, 0, implicit $exec :: (load (s8) from %ir.gep4 + 4, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %7[ 15 ]
+# CHECK: Vreg: %33[ 31 ]
+# CHECK: Vreg: %42[ 7 ]
+# CHECK: Vreg: %44[ 8 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %41[ 7 ]
+# CHECK: Vreg: %43[ 8 ]
+# CHECK: Instr: %46:vgpr_32 = DS_READ_U8_gfx9 %25, 37, 0, implicit $exec :: (load (s8) from %ir.gep4 + 5, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %7[ 14 ]
+# CHECK: Vreg: %33[ 30 ]
+# CHECK: Vreg: %42[ 6 ]
+# CHECK: Vreg: %44[ 7 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %27[ 10 ]
+# CHECK: Vreg: %41[ 6 ]
+# CHECK: Vreg: %43[ 7 ]
+# CHECK: Instr: %47:vgpr_32 = DS_READ_U8_gfx9 %25, 38, 0, implicit $exec :: (load (s8) from %ir.gep4 + 6, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 2 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %7[ 13 ]
+# CHECK: Vreg: %33[ 29 ]
+# CHECK: Vreg: %42[ 5 ]
+# CHECK: Vreg: %44[ 6 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %46[ 2 ]
+# CHECK: Vreg: %27[ 9 ]
+# CHECK: Vreg: %41[ 5 ]
+# CHECK: Vreg: %43[ 6 ]
+# CHECK: Instr: %48:vgpr_32 = DS_READ_U8_gfx9 %25, 39, 0, implicit $exec :: (load (s8) from %ir.gep4 + 7, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %26[ 7 ]
+# CHECK: Vreg: %7[ 12 ]
+# CHECK: Vreg: %33[ 28 ]
+# CHECK: Vreg: %47[ 2 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %44[ 5 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %27[ 8 ]
+# CHECK: Vreg: %41[ 4 ]
+# CHECK: Vreg: %43[ 5 ]
+# CHECK: Instr: %50:vgpr_32 = V_LSHL_OR_B32_e64 killed %46, 8, killed %45, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %7[ 11 ]
+# CHECK: Vreg: %33[ 27 ]
+# CHECK: Vreg: %47[ 1 ]
+# CHECK: Vreg: %42[ 3 ]
+# CHECK: Vreg: %44[ 4 ]
+# CHECK: Vreg: %25[ 17 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %41[ 3 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %43[ 4 ]
+# CHECK: Instr: %51:vgpr_32 = V_LSHL_OR_B32_e64 killed %48, 8, killed %47, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %7[ 10 ]
+# CHECK: Vreg: %33[ 26 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %44[ 3 ]
+# CHECK: Vreg: %25[ 16 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %41[ 2 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Instr: %53:vgpr_32 = V_LSHL_OR_B32_e64 killed %51, 16, killed %50, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %7[ 9 ]
+# CHECK: Vreg: %33[ 25 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %44[ 2 ]
+# CHECK: Vreg: %25[ 15 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Instr: %54:vgpr_32 = V_LSHL_OR_B32_e64 killed %42, 8, killed %41, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %7[ 8 ]
+# CHECK: Vreg: %33[ 24 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %44[ 1 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %27[ 4 ]
+# CHECK: Vreg: %53[ 4 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %43[ 1 ]
+# CHECK: Instr: %55:vgpr_32 = V_LSHL_OR_B32_e64 killed %44, 8, killed %43, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %7[ 7 ]
+# CHECK: Vreg: %33[ 23 ]
+# CHECK: Vreg: %54[ 1 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 13 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %53[ 3 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Instr: %56:vgpr_32 = V_LSHL_OR_B32_e64 killed %55, 16, killed %54, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %7[ 6 ]
+# CHECK: Vreg: %33[ 22 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %25[ 12 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %53[ 2 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Instr: %120:vgpr_32, %122:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 killed %56, %26, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %33[ 21 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %53[ 1 ]
+# CHECK: Instr: %121:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %53, %27, killed %122, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 13 ]
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %33[ 20 ]
+# CHECK: Vreg: %120[ 1 ]
+# CHECK: Vreg: %25[ 10 ]
+# CHECK: Vreg: %122[ 0 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Instr: %22:vreg_64 = REG_SEQUENCE killed %120, %subreg.sub0, killed %121, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %33[ 19 ]
+# CHECK: Vreg: %120[ 0 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %27[ 13 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Instr: %90:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %33[ 18 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %27[ 12 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %33[ 17 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %33[ 17 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: --- MBB_10 ---
+# CHECK: Instr: %23:vreg_64 = PHI %8, %bb.4, %11, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Instr: SI_END_CF killed %10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %23:sub0[ 1 ]
+# CHECK: Vreg: %23:sub1[ 2 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %78:sreg_32_xm0 = V_READFIRSTLANE_B32 %23.sub0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %23:sub0[ 0 ]
+# CHECK: Vreg: %23:sub1[ 1 ]
+# CHECK: Instr: %80:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %23.sub1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %78[ 1 ]
+# CHECK: Vreg: %23:sub1[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %78
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %80[ 1 ]
+# CHECK: Instr: $sgpr1 = COPY killed %80
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %80[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0, killed $sgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i64 @test2(i1 %cond, ptr addrspace(3) %p, i64 %val) {
+  entry:
+    %gep2 = getelementptr i64, ptr addrspace(3) %p, i64 1
+    %gep3 = getelementptr i64, ptr addrspace(3) %p, i64 2  
+    %gep4 = getelementptr i64, ptr addrspace(3) %p, i64 3
+    br label %bb2
+  bb1:
+    br label %bb2
+  bb2:
+    br label %bb3
+  bb3:
+    br label %bb4
+  bb4:
+    br label %bb5
+  bb5:
+    br label %exit
+  exit:
+    ret i64 0
+  }
+
+...
+name:            test2
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+noVRegs:         false
+hasFakeUses:     false
+callsEHReturn:   false
+callsUnwindInit: false
+hasEHContTarget: false
+hasEHScopes:     false
+hasEHFunclets:   false
+isOutlined:      false
+debugInstrRef:   true
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+  - { id: 0, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 1, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 2, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 3, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 4, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 5, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 6, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 7, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 8, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 9, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 10, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 11, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 12, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 13, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 14, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 15, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 16, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 17, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 18, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 19, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 20, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 21, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 22, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 23, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 24, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 25, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 26, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 27, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 28, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 29, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 30, class: vreg_1, preferred-register: '', flags: [  ] }
+  - { id: 31, class: sreg_64, preferred-register: '', flags: [  ] }
+  - { id: 32, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 33, class: sreg_32, preferred-register: '$vcc_lo', flags: [  ] }
+  - { id: 34, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 35, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 36, class: vreg_1, preferred-register: '', flags: [  ] }
+  - { id: 37, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 38, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 39, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 40, class: vreg_1, preferred-register: '', flags: [  ] }
+  - { id: 41, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 42, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 43, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 44, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 45, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 46, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 47, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 48, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 49, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 50, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 51, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 52, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 53, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 54, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 55, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 56, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 57, class: sreg_64, preferred-register: '', flags: [  ] }
+  - { id: 58, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 59, class: vreg_1, preferred-register: '', flags: [  ] }
+  - { id: 60, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 61, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 62, class: vreg_1, preferred-register: '', flags: [  ] }
+  - { id: 63, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 64, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 65, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 66, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 67, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 68, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 69, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 70, class: sreg_64, preferred-register: '', flags: [  ] }
+  - { id: 71, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 72, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 73, class: vreg_1, preferred-register: '', flags: [  ] }
+  - { id: 74, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 75, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 76, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 77, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 78, class: sreg_32_xm0, preferred-register: '', flags: [  ] }
+  - { id: 79, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 80, class: sreg_32_xm0, preferred-register: '', flags: [  ] }
+  - { id: 81, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 82, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 83, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 84, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 85, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 86, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 87, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 88, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 89, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 90, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 91, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 92, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 93, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 94, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 95, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 96, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 97, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 98, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 99, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 100, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 101, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 102, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 103, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 104, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 105, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 106, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo', 
+      flags: [  ] }
+  - { id: 107, class: sreg_32_xm0_xexec, preferred-register: '', flags: [  ] }
+  - { id: 108, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 109, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 110, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 111, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 112, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 113, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 114, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo', 
+      flags: [  ] }
+  - { id: 115, class: sreg_32_xm0_xexec, preferred-register: '', flags: [  ] }
+  - { id: 116, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 117, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 118, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 119, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 120, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 121, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 122, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo', 
+      flags: [  ] }
+  - { id: 123, class: sreg_32_xm0_xexec, preferred-register: '', flags: [  ] }
+  - { id: 124, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 125, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 126, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 127, class: vgpr_32, preferred-register: '', flags: [  ] }
+liveins:
+  - { reg: '$vgpr0', virtual-reg: '%24' }
+  - { reg: '$vgpr1', virtual-reg: '%25' }
+  - { reg: '$vgpr2', virtual-reg: '%26' }
+  - { reg: '$vgpr3', virtual-reg: '%27' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  functionContext: ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  isCalleeSavedInfoValid: false
+  localFrameSize:  0
+  savePoint:
+  restorePoint:
+fixedStack:      []
+stack:           []
+entry_values:    []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo:
+  explicitKernArgSize: 0
+  maxKernArgAlign: 4
+  ldsSize:         0
+  gdsSize:         0
+  dynLDSAlign:     1
+  isEntryFunction: true
+  isChainFunction: false
+  noSignedZerosFPMath: false
+  memoryBound:     false
+  waveLimiter:     false
+  hasSpilledSGPRs: false
+  hasSpilledVGPRs: false
+  scratchRSrcReg:  '$private_rsrc_reg'
+  frameOffsetReg:  '$fp_reg'
+  stackPtrOffsetReg: '$sgpr32'
+  bytesInStackArgArea: 0
+  returnsVoid:     false
+  psInputAddr:     7
+  psInputEnable:   7
+  maxMemoryClusterDWords: 8
+  mode:
+    ieee:            false
+    dx10-clamp:      true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
+  highBitsOf32BitAddress: 0
+  occupancy:       16
+  vgprForAGPRCopy: ''
+  sgprForEXECCopy: '$sgpr105'
+  longBranchReservedReg: ''
+  hasInitWholeWave: false
+  dynamicVGPRBlockSize: 0
+  scratchReservedForDynamicVGPRs: 0
+  isWholeWaveFunction: false
+body:             |
+  bb.0:
+    successors: %bb.3(0x40000000), %bb.8(0x40000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+  
+    %27:vgpr_32 = COPY killed $vgpr3
+    %26:vgpr_32 = COPY killed $vgpr2
+    %25:vgpr_32 = COPY killed $vgpr1
+    %24:vgpr_32 = COPY killed $vgpr0
+    %32:vgpr_32 = V_AND_B32_e64 1, killed %24, implicit $exec
+    %33:sreg_32 = V_CMP_NE_U32_e64 1, killed %32, implicit $exec
+    %34:sreg_32 = S_MOV_B32 0
+    %1:sreg_32 = SI_IF %33, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.3
+  
+  bb.1:
+    successors: %bb.8(0x80000000)
+  
+    %4:sreg_32 = PHI %37, %bb.3, %90, %bb.9
+    %2:vreg_64 = PHI undef %35:vreg_64, %bb.3, %22, %bb.9
+    %3:vreg_64 = PHI %6, %bb.3, undef %39:vreg_64, %bb.9
+    SI_END_CF killed %7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %102:sreg_32 = S_AND_B32 killed %4, $exec_lo, implicit-def dead $scc
+    %101:sreg_32 = COPY killed %102
+    S_BRANCH %bb.8
+  
+  bb.2:
+    successors: %bb.6(0x80000000)
+  
+    %63:vgpr_32 = DS_READ_U16_gfx9 %25, 0, 0, implicit $exec :: (load (s16) from %ir.p, addrspace 3)
+    %64:vgpr_32 = DS_READ_U16_gfx9 %25, 2, 0, implicit $exec :: (load (s16) from %ir.p + 2, addrspace 3)
+    %65:vgpr_32 = DS_READ_U16_gfx9 %25, 4, 0, implicit $exec :: (load (s16) from %ir.p + 4, addrspace 3)
+    %66:vgpr_32 = DS_READ_U16_gfx9 %25, 6, 0, implicit $exec :: (load (s16) from %ir.p + 6, addrspace 3)
+    %68:vgpr_32 = V_LSHL_OR_B32_e64 killed %66, 16, killed %65, implicit $exec
+    %69:vgpr_32 = V_LSHL_OR_B32_e64 killed %64, 16, killed %63, implicit $exec
+    %88:vreg_64 = REG_SEQUENCE killed %69, %subreg.sub0, killed %68, %subreg.sub1
+    %5:vreg_64 = COPY killed %88
+    %95:sreg_32 = COPY $exec_lo
+    %98:sreg_32 = S_ANDN2_B32 killed %20, $exec_lo, implicit-def dead $scc
+    %99:sreg_32 = S_AND_B32 killed %33, $exec_lo, implicit-def dead $scc
+    %97:sreg_32 = S_OR_B32 killed %98, killed %99, implicit-def dead $scc
+    S_BRANCH %bb.6
+  
+  bb.3:
+    successors: %bb.9(0x40000000), %bb.1(0x40000000)
+  
+    %6:vreg_64 = DS_READ_B64_gfx9 %25, 8, 0, implicit $exec :: (load (s64) from %ir.gep2, addrspace 3)
+    %37:sreg_32 = S_MOV_B32 -1
+    %7:sreg_32 = SI_IF %33, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.9
+  
+  bb.4:
+    successors: %bb.5(0x40000000), %bb.10(0x40000000)
+  
+    %9:sreg_32 = PHI %14, %bb.6, %92, %bb.7
+    %8:vreg_64 = PHI %12, %bb.6, %17, %bb.7
+    SI_END_CF killed %16, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %10:sreg_32 = SI_IF killed %9, %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.5
+  
+  bb.5:
+    successors: %bb.10(0x80000000)
+  
+    %76:vreg_64 = DS_READ2_B32_gfx9 killed %25, 6, 7, 0, implicit $exec :: (load (s64) from %ir.gep3, align 4, addrspace 3)
+    %104:vgpr_32, %106:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %76.sub0, killed %26, 0, implicit $exec
+    %105:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %76.sub1, killed %27, killed %106, 0, implicit $exec
+    %11:vreg_64 = REG_SEQUENCE killed %104, %subreg.sub0, killed %105, %subreg.sub1
+    S_BRANCH %bb.10
+  
+  bb.6:
+    successors: %bb.7(0x40000000), %bb.4(0x40000000)
+  
+    %15:sreg_32 = PHI %20, %bb.8, %97, %bb.2
+    %14:sreg_32 = PHI %34, %bb.8, %95, %bb.2
+    %12:vreg_64 = PHI %18, %bb.8, undef %61:vreg_64, %bb.2
+    %13:vreg_64 = PHI %19, %bb.8, %5, %bb.2
+    SI_END_CF killed %21, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %16:sreg_32 = SI_IF killed %15, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.7
+  
+  bb.7:
+    successors: %bb.4(0x80000000)
+  
+    %112:vgpr_32, %114:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %13.sub0, %26, 0, implicit $exec
+    %113:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %13.sub1, %27, killed %114, 0, implicit $exec
+    %17:vreg_64 = REG_SEQUENCE killed %112, %subreg.sub0, killed %113, %subreg.sub1
+    %93:sreg_32 = S_ANDN2_B32 killed %14, $exec_lo, implicit-def dead $scc
+    %92:sreg_32 = COPY killed %93
+    S_BRANCH %bb.4
+  
+  bb.8:
+    successors: %bb.2(0x40000000), %bb.6(0x40000000)
+  
+    %20:sreg_32 = PHI %34, %bb.0, %101, %bb.1
+    %18:vreg_64 = PHI undef %29:vreg_64, %bb.0, %2, %bb.1
+    %19:vreg_64 = PHI undef %29:vreg_64, %bb.0, %3, %bb.1
+    %21:sreg_32 = SI_ELSE killed %1, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+  
+  bb.9:
+    successors: %bb.1(0x80000000)
+  
+    %41:vgpr_32 = DS_READ_U8_gfx9 %25, 32, 0, implicit $exec :: (load (s8) from %ir.gep4, addrspace 3)
+    %42:vgpr_32 = DS_READ_U8_gfx9 %25, 33, 0, implicit $exec :: (load (s8) from %ir.gep4 + 1, addrspace 3)
+    %43:vgpr_32 = DS_READ_U8_gfx9 %25, 34, 0, implicit $exec :: (load (s8) from %ir.gep4 + 2, addrspace 3)
+    %44:vgpr_32 = DS_READ_U8_gfx9 %25, 35, 0, implicit $exec :: (load (s8) from %ir.gep4 + 3, addrspace 3)
+    %45:vgpr_32 = DS_READ_U8_gfx9 %25, 36, 0, implicit $exec :: (load (s8) from %ir.gep4 + 4, addrspace 3)
+    %46:vgpr_32 = DS_READ_U8_gfx9 %25, 37, 0, implicit $exec :: (load (s8) from %ir.gep4 + 5, addrspace 3)
+    %47:vgpr_32 = DS_READ_U8_gfx9 %25, 38, 0, implicit $exec :: (load (s8) from %ir.gep4 + 6, addrspace 3)
+    %48:vgpr_32 = DS_READ_U8_gfx9 %25, 39, 0, implicit $exec :: (load (s8) from %ir.gep4 + 7, addrspace 3)
+    %50:vgpr_32 = V_LSHL_OR_B32_e64 killed %46, 8, killed %45, implicit $exec
+    %51:vgpr_32 = V_LSHL_OR_B32_e64 killed %48, 8, killed %47, implicit $exec
+    %53:vgpr_32 = V_LSHL_OR_B32_e64 killed %51, 16, killed %50, implicit $exec
+    %54:vgpr_32 = V_LSHL_OR_B32_e64 killed %42, 8, killed %41, implicit $exec
+    %55:vgpr_32 = V_LSHL_OR_B32_e64 killed %44, 8, killed %43, implicit $exec
+    %56:vgpr_32 = V_LSHL_OR_B32_e64 killed %55, 16, killed %54, implicit $exec
+    %120:vgpr_32, %122:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 killed %56, %26, 0, implicit $exec
+    %121:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %53, %27, killed %122, 0, implicit $exec
+    %22:vreg_64 = REG_SEQUENCE killed %120, %subreg.sub0, killed %121, %subreg.sub1
+    %90:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+    S_BRANCH %bb.1
+  
+  bb.10:
+    %23:vreg_64 = PHI %8, %bb.4, %11, %bb.5
+    SI_END_CF killed %10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %78:sreg_32_xm0 = V_READFIRSTLANE_B32 %23.sub0, implicit $exec
+    %80:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %23.sub1, implicit $exec
+    $sgpr0 = COPY killed %78
+    $sgpr1 = COPY killed %80
+    SI_RETURN_TO_EPILOG killed $sgpr0, killed $sgpr1
+...
+---
+
+
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-14blocks.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-14blocks.mir
new file mode 100644
index 0000000000000..bd461a1d7d3e0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-14blocks.mir
@@ -0,0 +1,1567 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+  #
+  #       bb.0.entry
+  #        /    |
+  #   bb.1.bb1  |
+  #        \    |
+  #       bb.2.bb2
+  #        /    |
+  #   bb.5.bb4  |
+  #        \    |
+  #      bb.3.Flow3
+  #        /    |
+  #   bb.4.bb3  |
+  #        \    |
+  #      bb.6.bb5
+  #        /    |
+  #   bb.12.bb7 |
+  #        \    |
+  #      bb.7.Flow2
+  #        /    |
+  #   bb.8.bb6  |
+  #    /     |  |
+  #bb.11.bb9 |  |
+  #    \     |  |
+  #  bb.9.Flow  |
+  #    /     |  |
+  #bb.10.bb8 |  |
+  #    \     |  |
+  # bb.13.Flow1 |
+  #       \     |
+  #      bb.14.exit
+  #
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test3 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %31:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %30:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %31[ 7 ]
+# CHECK: Instr: %29:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %31[ 6 ]
+# CHECK: Instr: %28:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %30[ 3 ]
+# CHECK: Vreg: %29[ 26 ]
+# CHECK: Vreg: %31[ 5 ]
+# CHECK: Instr: %27:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %29[ 25 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Instr: %118:vreg_64 = REG_SEQUENCE killed %27, %subreg.sub0, killed %28, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %29[ 24 ]
+# CHECK: Vreg: %31[ 3 ]
+# CHECK: Instr: %35:vgpr_32 = V_AND_B32_e64 1, killed %30, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %118[ 5 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %29[ 23 ]
+# CHECK: Vreg: %31[ 2 ]
+# CHECK: Instr: %36:sreg_32 = V_CMP_EQ_U32_e64 1, killed %35, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %118[ 4 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %29[ 22 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: Instr: %37:vgpr_32 = V_AND_B32_e64 1, killed %31, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %118[ 3 ]
+# CHECK: Vreg: %29[ 21 ]
+# CHECK: Vreg: %36[ 18 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %38:sreg_32 = V_CMP_EQ_U32_e64 1, killed %37, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %118[ 2 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %29[ 20 ]
+# CHECK: Vreg: %36[ 17 ]
+# CHECK: Instr: %40:sreg_32 = S_XOR_B32 %38, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %118[ 1 ]
+# CHECK: Vreg: %29[ 19 ]
+# CHECK: Vreg: %36[ 16 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Instr: %41:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 26 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %29[ 18 ]
+# CHECK: Vreg: %36[ 15 ]
+# CHECK: Vreg: %38[ 33 ]
+# CHECK: Instr: %43:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 25 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %29[ 17 ]
+# CHECK: Vreg: %36[ 14 ]
+# CHECK: Vreg: %38[ 32 ]
+# CHECK: Instr: %46:vgpr_32 = V_LSHL_OR_B32_e64 killed %43, 8, killed %41, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 24 ]
+# CHECK: Vreg: %118[ 1 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 16 ]
+# CHECK: Vreg: %36[ 13 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %38[ 31 ]
+# CHECK: Instr: %47:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %46[ 3 ]
+# CHECK: Vreg: %29[ 15 ]
+# CHECK: Vreg: %36[ 12 ]
+# CHECK: Vreg: %38[ 30 ]
+# CHECK: Instr: %49:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 22 ]
+# CHECK: Vreg: %47[ 1 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %46[ 2 ]
+# CHECK: Vreg: %29[ 14 ]
+# CHECK: Vreg: %36[ 11 ]
+# CHECK: Vreg: %38[ 29 ]
+# CHECK: Instr: %51:vgpr_32 = V_LSHL_OR_B32_e64 killed %49, 8, killed %47, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 21 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %118[ 2 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %29[ 13 ]
+# CHECK: Vreg: %36[ 10 ]
+# CHECK: Vreg: %38[ 28 ]
+# CHECK: Instr: %1:vgpr_32 = V_LSHL_OR_B32_e64 killed %51, 16, killed %46, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %118[ 1 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %29[ 12 ]
+# CHECK: Vreg: %36[ 9 ]
+# CHECK: Vreg: %38[ 27 ]
+# CHECK: Instr: %53:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 12, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 19 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %29[ 11 ]
+# CHECK: Vreg: %36[ 8 ]
+# CHECK: Vreg: %38[ 26 ]
+# CHECK: Instr: %55:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 13, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 18 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %53[ 1 ]
+# CHECK: Vreg: %29[ 10 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Vreg: %38[ 25 ]
+# CHECK: Instr: %57:vgpr_32 = V_LSHL_OR_B32_e64 killed %55, 8, killed %53, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 17 ]
+# CHECK: Vreg: %118[ 1 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %38[ 24 ]
+# CHECK: Instr: %58:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 14, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 16 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %29[ 8 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %57[ 3 ]
+# CHECK: Vreg: %38[ 23 ]
+# CHECK: Instr: %60:vgpr_32 = GLOBAL_LOAD_UBYTE killed %118, 15, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 15 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %58[ 1 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %29[ 7 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %57[ 2 ]
+# CHECK: Vreg: %38[ 22 ]
+# CHECK: Instr: %62:vgpr_32 = V_LSHL_OR_B32_e64 killed %60, 8, killed %58, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 14 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %57[ 1 ]
+# CHECK: Vreg: %38[ 21 ]
+# CHECK: Instr: %2:vgpr_32 = V_LSHL_OR_B32_e64 killed %62, 16, killed %57, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 13 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ 20 ]
+# CHECK: Instr: %3:vgpr_32 = V_ADD_U32_e64 100, %1, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 12 ]
+# CHECK: Vreg: %2[ 22 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %38[ 19 ]
+# CHECK: Instr: %4:sreg_32 = SI_IF %36, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 11 ]
+# CHECK: Vreg: %2[ 21 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %38[ 18 ]
+# CHECK: Instr: S_BRANCH %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %36[ 17 ]
+# CHECK: Vreg: %38[ 17 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %36[ 17 ]
+# CHECK: Vreg: %38[ 17 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %64:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %36[ 17 ]
+# CHECK: Vreg: %38[ 17 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %36[ 17 ]
+# CHECK: Vreg: %38[ 17 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %5:vgpr_32 = PHI %3, %bb.0, %64, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %36[ 17 ]
+# CHECK: Vreg: %38[ 17 ]
+# CHECK: Instr: SI_END_CF killed %4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %36[ 16 ]
+# CHECK: Vreg: %5[ 10 ]
+# CHECK: Vreg: %38[ 16 ]
+# CHECK: Instr: %66:vgpr_32 = DS_READ_U8_gfx9 %29, 0, 0, implicit $exec :: (load (s8) from %ir.p2, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 8 ]
+# CHECK: Vreg: %2[ 18 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 15 ]
+# CHECK: Vreg: %5[ 9 ]
+# CHECK: Vreg: %38[ 15 ]
+# CHECK: Instr: %67:vgpr_32 = DS_READ_U8_gfx9 %29, 1, 0, implicit $exec :: (load (s8) from %ir.p2 + 1, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 7 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %66[ 3 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 14 ]
+# CHECK: Vreg: %5[ 8 ]
+# CHECK: Vreg: %38[ 14 ]
+# CHECK: Instr: %68:vgpr_32 = DS_READ_U8_gfx9 %29, 2, 0, implicit $exec :: (load (s8) from %ir.p2 + 2, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %66[ 2 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 13 ]
+# CHECK: Vreg: %5[ 7 ]
+# CHECK: Vreg: %38[ 13 ]
+# CHECK: Instr: %69:vgpr_32 = DS_READ_U8_gfx9 %29, 3, 0, implicit $exec :: (load (s8) from %ir.p2 + 3, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %68[ 2 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 12 ]
+# CHECK: Vreg: %5[ 6 ]
+# CHECK: Vreg: %38[ 12 ]
+# CHECK: Instr: %71:vgpr_32 = V_LSHL_OR_B32_e64 killed %67, 8, killed %66, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %68[ 1 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %36[ 11 ]
+# CHECK: Vreg: %5[ 5 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %38[ 11 ]
+# CHECK: Instr: %72:vgpr_32 = V_LSHL_OR_B32_e64 killed %69, 8, killed %68, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %71[ 1 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %29[ 8 ]
+# CHECK: Vreg: %36[ 10 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %38[ 10 ]
+# CHECK: Instr: %6:vgpr_32 = V_LSHL_OR_B32_e64 killed %72, 16, killed %71, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %29[ 7 ]
+# CHECK: Vreg: %36[ 9 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Vreg: %38[ 9 ]
+# CHECK: Instr: %7:vgpr_32 = V_ADD_U32_e64 100, %6, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %36[ 8 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Vreg: %38[ 8 ]
+# CHECK: Instr: %8:sreg_32 = SI_IF killed %40, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %6[ 12 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Vreg: %38[ 7 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %6[ 11 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %6[ 11 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %9:vgpr_32 = PHI undef %65:vgpr_32, %bb.2, %12, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 13 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %6[ 11 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Instr: %119:vgpr_32 = PHI %5, %bb.2, undef %120:vgpr_32, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 13 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %6[ 11 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Instr: %10:sreg_32 = SI_ELSE killed %8, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 12 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %6[ 10 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %119[ 2 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 11 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %6[ 9 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %119[ 1 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 11 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %6[ 9 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %119[ 1 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %76:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 %1, killed %119, 1000, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 13 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %6[ 11 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Instr: %11:vgpr_32 = COPY killed %76.sub0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 12 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %6[ 10 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %76:sub0[ 0 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 11 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %6[ 9 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 11 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %6[ 9 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %12:vgpr_32 = V_ADD_U32_e64 %7, %1, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %6[ 12 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Vreg: %38[ 7 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 13 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %6[ 11 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 13 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %6[ 11 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %13:vgpr_32 = PHI %9, %bb.3, %11, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 11 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %6[ 9 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Instr: SI_END_CF killed %10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 10 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %6[ 8 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Instr: %14:vgpr_32 = DS_READ_B32_gfx9 killed %29, 12, 0, implicit $exec :: (load (s32) from %ir.gep2, align 8, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 9 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %6[ 7 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Instr: %15:vgpr_32 = V_ADD_U32_e64 %14, killed %13, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 8 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %6[ 6 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Instr: %79:sreg_32 = S_XOR_B32 %36, %38, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 7 ]
+# CHECK: Vreg: %14[ 4 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %6[ 5 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Instr: %83:sreg_32 = S_XOR_B32 killed %79, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 6 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %6[ 4 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Instr: %16:sreg_32 = SI_IF killed %83, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Vreg: %83[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: %17:vgpr_32 = PHI undef %78:vgpr_32, %bb.6, %24, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Instr: %121:vgpr_32 = PHI %2, %bb.6, undef %122:vgpr_32, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Instr: %123:vgpr_32 = PHI %15, %bb.6, undef %124:vgpr_32, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %121[ 6 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Instr: %18:sreg_32 = SI_ELSE killed %16, %bb.14, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %123[ 5 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %121[ 5 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %123[ 4 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %121[ 4 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %123[ 4 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %121[ 4 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: %109:sreg_32 = S_AND_B32 killed %36, killed %38, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 8 ]
+# CHECK: Vreg: %123[ 3 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %121[ 3 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Instr: %113:sreg_32 = S_XOR_B32 killed %109, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %7[ 7 ]
+# CHECK: Vreg: %123[ 2 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %121[ 2 ]
+# CHECK: Instr: %19:sreg_32 = SI_IF killed %113, %bb.9, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 6 ]
+# CHECK: Vreg: %123[ 1 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %121[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: --- MBB_9 ---
+# CHECK: Instr: %20:vgpr_32 = PHI undef %108:vgpr_32, %bb.8, %23, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: %125:vgpr_32 = PHI %121, %bb.8, undef %126:vgpr_32, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: %127:vgpr_32 = PHI %123, %bb.8, undef %128:vgpr_32, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %125[ 3 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: %21:sreg_32 = SI_ELSE killed %19, %bb.13, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %125[ 2 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %127[ 2 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %125[ 1 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %127[ 1 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %125[ 1 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %127[ 1 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: --- MBB_10 ---
+# CHECK: Instr: %22:vgpr_32 = V_ADD_U32_e64 killed %125, killed %127, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: --- MBB_11 ---
+# CHECK: Instr: %23:vgpr_32 = V_MUL_LO_U32_e64 killed %121, killed %123, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 6 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: --- MBB_12 ---
+# CHECK: Instr: %84:vgpr_32 = V_SUB_U32_e64 killed %14, killed %15, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 26 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %2[ 21 ]
+# CHECK: Vreg: %16[ 23 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %36[ 25 ]
+# CHECK: Vreg: %38[ 25 ]
+# CHECK: Instr: %85:vgpr_32 = V_MUL_LO_U32_e64 killed %84, killed %6, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 25 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %16[ 22 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %36[ 24 ]
+# CHECK: Vreg: %38[ 24 ]
+# CHECK: Instr: %86:vgpr_32 = V_CVT_F32_U32_e64 %1, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 24 ]
+# CHECK: Vreg: %85[ 8 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %16[ 21 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %36[ 23 ]
+# CHECK: Vreg: %38[ 23 ]
+# CHECK: Instr: %87:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %86, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 23 ]
+# CHECK: Vreg: %85[ 7 ]
+# CHECK: Vreg: %2[ 18 ]
+# CHECK: Vreg: %16[ 20 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %36[ 22 ]
+# CHECK: Vreg: %38[ 22 ]
+# CHECK: Instr: %89:vgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, 1333788670, 0, killed %87, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 22 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %16[ 19 ]
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %36[ 21 ]
+# CHECK: Vreg: %38[ 21 ]
+# CHECK: Instr: %90:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, killed %89, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 21 ]
+# CHECK: Vreg: %85[ 5 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %16[ 18 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %36[ 20 ]
+# CHECK: Vreg: %38[ 20 ]
+# CHECK: Instr: %92:vgpr_32 = V_SUB_U32_e64 0, %1, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %90[ 1 ]
+# CHECK: Vreg: %7[ 20 ]
+# CHECK: Vreg: %85[ 4 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %16[ 17 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %36[ 19 ]
+# CHECK: Vreg: %38[ 19 ]
+# CHECK: Instr: %93:vgpr_32 = V_MUL_LO_U32_e64 killed %92, %90, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %7[ 19 ]
+# CHECK: Vreg: %85[ 3 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %16[ 16 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %36[ 18 ]
+# CHECK: Vreg: %38[ 18 ]
+# CHECK: Instr: %94:vgpr_32 = V_MUL_HI_U32_e64 %90, killed %93, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %7[ 18 ]
+# CHECK: Vreg: %85[ 2 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %16[ 15 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %36[ 17 ]
+# CHECK: Vreg: %38[ 17 ]
+# CHECK: Instr: %95:vgpr_32 = V_ADD_U32_e64 killed %90, killed %94, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %7[ 17 ]
+# CHECK: Vreg: %85[ 1 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %16[ 14 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %36[ 16 ]
+# CHECK: Vreg: %38[ 16 ]
+# CHECK: Instr: %96:vgpr_32 = V_MUL_HI_U32_e64 %85, killed %95, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 16 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %16[ 13 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %36[ 15 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %38[ 15 ]
+# CHECK: Instr: %97:vgpr_32 = V_MUL_LO_U32_e64 %96, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 15 ]
+# CHECK: Vreg: %85[ 1 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %16[ 12 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %36[ 14 ]
+# CHECK: Vreg: %38[ 14 ]
+# CHECK: Instr: %98:vgpr_32 = V_SUB_U32_e64 killed %85, killed %97, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 14 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %16[ 11 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %36[ 13 ]
+# CHECK: Vreg: %38[ 13 ]
+# CHECK: Instr: %99:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 %98, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 13 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %16[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %36[ 12 ]
+# CHECK: Vreg: %38[ 12 ]
+# CHECK: Instr: %101:vgpr_32 = V_ADD_U32_e64 1, %96, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 12 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %99[ 1 ]
+# CHECK: Vreg: %16[ 9 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %98[ 2 ]
+# CHECK: Vreg: %36[ 11 ]
+# CHECK: Vreg: %38[ 11 ]
+# CHECK: Instr: %102:vgpr_32 = V_CNDMASK_B32_e64 0, killed %96, 0, killed %101, %99, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 11 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %16[ 8 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %36[ 10 ]
+# CHECK: Vreg: %38[ 10 ]
+# CHECK: Instr: %103:vgpr_32 = V_SUB_U32_e64 %98, %1, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 10 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %99[ 1 ]
+# CHECK: Vreg: %16[ 7 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %36[ 9 ]
+# CHECK: Vreg: %38[ 9 ]
+# CHECK: Vreg: %102[ 3 ]
+# CHECK: Instr: %104:vgpr_32 = V_CNDMASK_B32_e64 0, killed %98, 0, killed %103, killed %99, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 9 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %16[ 6 ]
+# CHECK: Vreg: %103[ 0 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %36[ 8 ]
+# CHECK: Vreg: %38[ 8 ]
+# CHECK: Vreg: %102[ 2 ]
+# CHECK: Instr: %105:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 killed %104, killed %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 8 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %16[ 5 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Vreg: %38[ 7 ]
+# CHECK: Vreg: %102[ 1 ]
+# CHECK: Instr: %106:vgpr_32 = V_ADD_U32_e64 1, %102, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 7 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %16[ 4 ]
+# CHECK: Vreg: %105[ 1 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: %107:vgpr_32 = V_CNDMASK_B32_e64 0, killed %102, 0, killed %106, killed %105, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 6 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %16[ 3 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: %24:vgpr_32 = V_ADD_U32_e64 killed %107, killed %2, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %16[ 2 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: --- MBB_13 ---
+# CHECK: Instr: %25:vgpr_32 = PHI %20, %bb.9, %22, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Instr: SI_END_CF killed %21, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: --- MBB_14 ---
+# CHECK: Instr: %26:vgpr_32 = PHI %17, %bb.7, %25, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: SI_END_CF killed %18, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Instr: %114:vgpr_32 = V_ADD_U32_e64 killed %7, killed %26, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Instr: %115:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %114, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %115
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test3(ptr addrspace(1) %p1, ptr addrspace(3) %p2, i1 %cond1, i1 %cond2) {
+  entry:
+     %ld1 = load i32, ptr addrspace(1) %p1, align 1
+     %gep1 = getelementptr inbounds i32, ptr addrspace(1) %p1, i64 3
+     %ld2 = load i32, ptr addrspace(1) %gep1, align 1
+     %add1 = add i32 %ld1, 100
+     br i1 %cond1, label %bb1, label %bb2
+  
+  bb1:
+    br label %bb2
+  
+  bb2:
+    %phi0 = phi i32 [ 100, %bb1 ], [ %add1, %entry ]
+    %ld3 = load i32, ptr addrspace(3) %p2, align 1
+    %add2 = add i32 %ld3, 100
+    br i1 %cond2, label %bb3, label %bb4
+  
+  bb3:
+    %mul1 = mul i32 %ld1, %phi0
+    %add3 = add i32 %mul1, 1000
+    br label %bb5
+  
+  bb4:
+    %add4 = add i32 %add2, %ld1
+    br label %bb5
+  
+  bb5:
+    %phi1 = phi i32 [ %add3, %bb3 ], [ %add4, %bb4]
+    %gep2 = getelementptr inbounds i32, ptr addrspace(3) %p2, i64 3
+    %ld4 = load i32, ptr addrspace(3) %gep2, align 8
+    %add5 = add i32 %ld4, %phi1
+    %xor = xor i1 %cond1, %cond2
+    br i1 %xor, label %bb6, label %bb7
+  
+  bb6:
+    %and = and i1 %cond1, %cond2
+    br i1 %and, label %bb8, label %bb9
+  
+  bb8:
+    %add6 = add i32 %ld2, %add5
+    br label %exit
+  
+  bb9:
+    %mul2 = mul i32 %ld2, %add5
+    br label %exit
+  
+  bb7:
+    %sub1 = sub i32 %ld4, %add5
+    %mul3 = mul i32 %sub1, %ld3
+    %div = udiv i32 %mul3, %ld1
+    %add7 = add i32 %div, %ld2
+    br label %exit
+  
+  exit:
+    %phi2 = phi i32 [ %add6, %bb8 ], [ %mul2, %bb9], [ %add7, %bb7 ]
+    %add8 = add i32 %add2, %phi2
+    ret i32 %add8
+  }
+  
+---
+name:            test3
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+noVRegs:         false
+hasFakeUses:     false
+callsEHReturn:   false
+callsUnwindInit: false
+hasEHContTarget: false
+hasEHScopes:     false
+hasEHFunclets:   false
+isOutlined:      false
+debugInstrRef:   true
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+  - { id: 0, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 1, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 2, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 3, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 4, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 5, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 6, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 7, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 8, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 9, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 10, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 11, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 12, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 13, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 14, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 15, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 16, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 17, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 18, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 19, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 20, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 21, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 22, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 23, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 24, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 25, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 26, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 27, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 28, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 29, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 30, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 31, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 32, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 33, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 34, class: sreg_64, preferred-register: '', flags: [  ] }
+  - { id: 35, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 36, class: sreg_32, preferred-register: '$vcc_lo', flags: [  ] }
+  - { id: 37, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 38, class: sreg_32, preferred-register: '$vcc_lo', flags: [  ] }
+  - { id: 39, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 40, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 41, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 42, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 43, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 44, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 45, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 46, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 47, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 48, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 49, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 50, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 51, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 52, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 53, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 54, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 55, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 56, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 57, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 58, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 59, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 60, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 61, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 62, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 63, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 64, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 65, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 66, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 67, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 68, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 69, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 70, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 71, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 72, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 73, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 74, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 75, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 76, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 77, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 78, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 79, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 80, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 81, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 82, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 83, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 84, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 85, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 86, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 87, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 88, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 89, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 90, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 91, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 92, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 93, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 94, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 95, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 96, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 97, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 98, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 99, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo', 
+      flags: [  ] }
+  - { id: 100, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 101, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 102, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 103, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 104, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 105, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo', 
+      flags: [  ] }
+  - { id: 106, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 107, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 108, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 109, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 110, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 111, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 112, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 113, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 114, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 115, class: sreg_32_xm0, preferred-register: '', flags: [  ] }
+  - { id: 116, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 117, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 118, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 119, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 120, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 121, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 122, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 123, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 124, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 125, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 126, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 127, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 128, class: vgpr_32, preferred-register: '', flags: [  ] }
+liveins:
+  - { reg: '$vgpr0', virtual-reg: '%27' }
+  - { reg: '$vgpr1', virtual-reg: '%28' }
+  - { reg: '$vgpr2', virtual-reg: '%29' }
+  - { reg: '$vgpr3', virtual-reg: '%30' }
+  - { reg: '$vgpr4', virtual-reg: '%31' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  functionContext: ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  isCalleeSavedInfoValid: false
+  localFrameSize:  0
+fixedStack:      []
+stack:           []
+entry_values:    []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo:
+  explicitKernArgSize: 0
+  maxKernArgAlign: 4
+  ldsSize:         0
+  gdsSize:         0
+  dynLDSAlign:     1
+  isEntryFunction: true
+  isChainFunction: false
+  noSignedZerosFPMath: false
+  memoryBound:     false
+  waveLimiter:     false
+  hasSpilledSGPRs: false
+  hasSpilledVGPRs: false
+  scratchRSrcReg:  '$private_rsrc_reg'
+  frameOffsetReg:  '$fp_reg'
+  stackPtrOffsetReg: '$sgpr32'
+  bytesInStackArgArea: 0
+  returnsVoid:     false
+  psInputAddr:     15
+  psInputEnable:   15
+  maxMemoryClusterDWords: 8
+  mode:
+    ieee:            false
+    dx10-clamp:      true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
+  highBitsOf32BitAddress: 0
+  occupancy:       16
+  vgprForAGPRCopy: ''
+  sgprForEXECCopy: '$sgpr105'
+  longBranchReservedReg: ''
+  hasInitWholeWave: false
+  dynamicVGPRBlockSize: 0
+  scratchReservedForDynamicVGPRs: 0
+  isWholeWaveFunction: false
+body:             |
+  bb.0:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  
+    %31:vgpr_32 = COPY killed $vgpr4
+    %30:vgpr_32 = COPY killed $vgpr3
+    %29:vgpr_32 = COPY killed $vgpr2
+    %28:vgpr_32 = COPY killed $vgpr1
+    %27:vgpr_32 = COPY killed $vgpr0
+    %118:vreg_64 = REG_SEQUENCE killed %27, %subreg.sub0, killed %28, %subreg.sub1
+    %35:vgpr_32 = V_AND_B32_e64 1, killed %30, implicit $exec
+    %36:sreg_32 = V_CMP_EQ_U32_e64 1, killed %35, implicit $exec
+    %37:vgpr_32 = V_AND_B32_e64 1, killed %31, implicit $exec
+    %38:sreg_32 = V_CMP_EQ_U32_e64 1, killed %37, implicit $exec
+    %40:sreg_32 = S_XOR_B32 %38, -1, implicit-def dead $scc
+    %41:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %43:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %46:vgpr_32 = V_LSHL_OR_B32_e64 killed %43, 8, killed %41, implicit $exec
+    %47:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %49:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %51:vgpr_32 = V_LSHL_OR_B32_e64 killed %49, 8, killed %47, implicit $exec
+    %1:vgpr_32 = V_LSHL_OR_B32_e64 killed %51, 16, killed %46, implicit $exec
+    %53:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 12, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+    %55:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 13, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+    %57:vgpr_32 = V_LSHL_OR_B32_e64 killed %55, 8, killed %53, implicit $exec
+    %58:vgpr_32 = GLOBAL_LOAD_UBYTE %118, 14, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+    %60:vgpr_32 = GLOBAL_LOAD_UBYTE killed %118, 15, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+    %62:vgpr_32 = V_LSHL_OR_B32_e64 killed %60, 8, killed %58, implicit $exec
+    %2:vgpr_32 = V_LSHL_OR_B32_e64 killed %62, 16, killed %57, implicit $exec
+    %3:vgpr_32 = V_ADD_U32_e64 100, %1, 0, implicit $exec
+    %4:sreg_32 = SI_IF %36, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.1
+  
+  bb.1:
+    successors: %bb.2(0x80000000)
+  
+    %64:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+  
+  bb.2:
+    successors: %bb.5(0x40000000), %bb.3(0x40000000)
+  
+    %5:vgpr_32 = PHI %3, %bb.0, %64, %bb.1
+    SI_END_CF killed %4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %66:vgpr_32 = DS_READ_U8_gfx9 %29, 0, 0, implicit $exec :: (load (s8) from %ir.p2, addrspace 3)
+    %67:vgpr_32 = DS_READ_U8_gfx9 %29, 1, 0, implicit $exec :: (load (s8) from %ir.p2 + 1, addrspace 3)
+    %68:vgpr_32 = DS_READ_U8_gfx9 %29, 2, 0, implicit $exec :: (load (s8) from %ir.p2 + 2, addrspace 3)
+    %69:vgpr_32 = DS_READ_U8_gfx9 %29, 3, 0, implicit $exec :: (load (s8) from %ir.p2 + 3, addrspace 3)
+    %71:vgpr_32 = V_LSHL_OR_B32_e64 killed %67, 8, killed %66, implicit $exec
+    %72:vgpr_32 = V_LSHL_OR_B32_e64 killed %69, 8, killed %68, implicit $exec
+    %6:vgpr_32 = V_LSHL_OR_B32_e64 killed %72, 16, killed %71, implicit $exec
+    %7:vgpr_32 = V_ADD_U32_e64 100, %6, 0, implicit $exec
+    %8:sreg_32 = SI_IF killed %40, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.5
+  
+  bb.3:
+    successors: %bb.4(0x40000000), %bb.6(0x40000000)
+  
+    %9:vgpr_32 = PHI undef %65:vgpr_32, %bb.2, %12, %bb.5
+    %119:vgpr_32 = PHI %5, %bb.2, undef %120:vgpr_32, %bb.5
+    %10:sreg_32 = SI_ELSE killed %8, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.4
+  
+  bb.4:
+    successors: %bb.6(0x80000000)
+  
+    %76:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 %1, killed %119, 1000, 0, implicit $exec
+    %11:vgpr_32 = COPY killed %76.sub0
+    S_BRANCH %bb.6
+  
+  bb.5:
+    successors: %bb.3(0x80000000)
+  
+    %12:vgpr_32 = V_ADD_U32_e64 %7, %1, 0, implicit $exec
+    S_BRANCH %bb.3
+  
+  bb.6:
+    successors: %bb.12(0x40000000), %bb.7(0x40000000)
+  
+    %13:vgpr_32 = PHI %9, %bb.3, %11, %bb.4
+    SI_END_CF killed %10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %14:vgpr_32 = DS_READ_B32_gfx9 killed %29, 12, 0, implicit $exec :: (load (s32) from %ir.gep2, align 8, addrspace 3)
+    %15:vgpr_32 = V_ADD_U32_e64 %14, killed %13, 0, implicit $exec
+    %79:sreg_32 = S_XOR_B32 %36, %38, implicit-def dead $scc
+    %83:sreg_32 = S_XOR_B32 killed %79, -1, implicit-def dead $scc
+    %16:sreg_32 = SI_IF killed %83, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.12
+  
+  bb.7:
+    successors: %bb.8(0x40000000), %bb.14(0x40000000)
+  
+    %17:vgpr_32 = PHI undef %78:vgpr_32, %bb.6, %24, %bb.12
+    %121:vgpr_32 = PHI %2, %bb.6, undef %122:vgpr_32, %bb.12
+    %123:vgpr_32 = PHI %15, %bb.6, undef %124:vgpr_32, %bb.12
+    %18:sreg_32 = SI_ELSE killed %16, %bb.14, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.8
+  
+  bb.8:
+    successors: %bb.11(0x40000000), %bb.9(0x40000000)
+  
+    %109:sreg_32 = S_AND_B32 killed %36, killed %38, implicit-def dead $scc
+    %113:sreg_32 = S_XOR_B32 killed %109, -1, implicit-def dead $scc
+    %19:sreg_32 = SI_IF killed %113, %bb.9, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.11
+  
+  bb.9:
+    successors: %bb.10(0x40000000), %bb.13(0x40000000)
+  
+    %20:vgpr_32 = PHI undef %108:vgpr_32, %bb.8, %23, %bb.11
+    %125:vgpr_32 = PHI %121, %bb.8, undef %126:vgpr_32, %bb.11
+    %127:vgpr_32 = PHI %123, %bb.8, undef %128:vgpr_32, %bb.11
+    %21:sreg_32 = SI_ELSE killed %19, %bb.13, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.10
+  
+  bb.10:
+    successors: %bb.13(0x80000000)
+  
+    %22:vgpr_32 = V_ADD_U32_e64 killed %125, killed %127, 0, implicit $exec
+    S_BRANCH %bb.13
+  
+  bb.11:
+    successors: %bb.9(0x80000000)
+  
+    %23:vgpr_32 = V_MUL_LO_U32_e64 killed %121, killed %123, implicit $exec
+    S_BRANCH %bb.9
+  
+  bb.12:
+    successors: %bb.7(0x80000000)
+  
+    %84:vgpr_32 = V_SUB_U32_e64 killed %14, killed %15, 0, implicit $exec
+    %85:vgpr_32 = V_MUL_LO_U32_e64 killed %84, killed %6, implicit $exec
+    %86:vgpr_32 = V_CVT_F32_U32_e64 %1, 0, 0, implicit $mode, implicit $exec
+    %87:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %86, 0, 0, implicit $mode, implicit $exec
+    %89:vgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, 1333788670, 0, killed %87, 0, 0, implicit $mode, implicit $exec
+    %90:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, killed %89, 0, 0, implicit $mode, implicit $exec
+    %92:vgpr_32 = V_SUB_U32_e64 0, %1, 0, implicit $exec
+    %93:vgpr_32 = V_MUL_LO_U32_e64 killed %92, %90, implicit $exec
+    %94:vgpr_32 = V_MUL_HI_U32_e64 %90, killed %93, implicit $exec
+    %95:vgpr_32 = V_ADD_U32_e64 killed %90, killed %94, 0, implicit $exec
+    %96:vgpr_32 = V_MUL_HI_U32_e64 %85, killed %95, implicit $exec
+    %97:vgpr_32 = V_MUL_LO_U32_e64 %96, %1, implicit $exec
+    %98:vgpr_32 = V_SUB_U32_e64 killed %85, killed %97, 0, implicit $exec
+    %99:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 %98, %1, implicit $exec
+    %101:vgpr_32 = V_ADD_U32_e64 1, %96, 0, implicit $exec
+    %102:vgpr_32 = V_CNDMASK_B32_e64 0, killed %96, 0, killed %101, %99, implicit $exec
+    %103:vgpr_32 = V_SUB_U32_e64 %98, %1, 0, implicit $exec
+    %104:vgpr_32 = V_CNDMASK_B32_e64 0, killed %98, 0, killed %103, killed %99, implicit $exec
+    %105:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 killed %104, killed %1, implicit $exec
+    %106:vgpr_32 = V_ADD_U32_e64 1, %102, 0, implicit $exec
+    %107:vgpr_32 = V_CNDMASK_B32_e64 0, killed %102, 0, killed %106, killed %105, implicit $exec
+    %24:vgpr_32 = V_ADD_U32_e64 killed %107, killed %2, 0, implicit $exec
+    S_BRANCH %bb.7
+  
+  bb.13:
+    successors: %bb.14(0x80000000)
+  
+    %25:vgpr_32 = PHI %20, %bb.9, %22, %bb.10
+    SI_END_CF killed %21, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+  
+  bb.14:
+    %26:vgpr_32 = PHI %17, %bb.7, %25, %bb.13
+    SI_END_CF killed %18, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %114:vgpr_32 = V_ADD_U32_e64 killed %7, killed %26, 0, implicit $exec
+    %115:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %114, implicit $exec
+    $sgpr0 = COPY killed %115
+    SI_RETURN_TO_EPILOG killed $sgpr0
+...
+---
+
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
new file mode 100644
index 0000000000000..0d6a1984c1c72
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
@@ -0,0 +1,1767 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#            bb.0.entry
+#                |
+#        bb.1.loop1.header<----+
+#         /      |             |
+#  bb.5.bb2      |             |
+#         \      |             |
+#         bb.2.Flow------------+
+#                |             |
+#         bb.3.Flow2           |
+#           /    |             |
+#    bb.4.bb1    |             |
+#           \    |             |
+#       bb.6.loop1.latch2------+
+#                |
+#            bb.7.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test8 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr8
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 39 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 38 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Instr: %9:vreg_64 = REG_SEQUENCE killed %4, %subreg.sub0, killed %3, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Instr: %10:vreg_64 = REG_SEQUENCE killed %6, %subreg.sub0, killed %5, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %9[ 22 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %11:vreg_64 = REG_SEQUENCE killed %8, %subreg.sub0, killed %7, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %9[ 21 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %10[ 19 ]
+# CHECK: Instr: %12:vgpr_32 = V_AND_B32_e64 1, killed %2, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 20 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %10[ 18 ]
+# CHECK: Instr: %13:sreg_32 = V_CMP_NE_U32_e64 1, killed %12, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %9[ 19 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %10[ 17 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %14:vgpr_32 = GLOBAL_LOAD_UBYTE %11, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %9[ 18 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %13[ 14 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %10[ 16 ]
+# CHECK: Instr: %15:vgpr_32 = GLOBAL_LOAD_UBYTE %11, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %9[ 17 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %13[ 13 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %10[ 15 ]
+# CHECK: Instr: %16:vgpr_32 = V_LSHL_OR_B32_e64 killed %15, 8, killed %14, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %9[ 16 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Instr: %17:vgpr_32 = GLOBAL_LOAD_UBYTE %11, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %9[ 15 ]
+# CHECK: Vreg: %16[ 3 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %13[ 11 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %10[ 13 ]
+# CHECK: Instr: %18:vgpr_32 = GLOBAL_LOAD_UBYTE %11, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %9[ 14 ]
+# CHECK: Vreg: %16[ 2 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Instr: %19:vgpr_32 = V_LSHL_OR_B32_e64 killed %18, 8, killed %17, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %9[ 13 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %11[ 21 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: %20:vgpr_32 = V_LSHL_OR_B32_e64 killed %19, 16, killed %16, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %9[ 12 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %11[ 20 ]
+# CHECK: Vreg: %13[ 8 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %10[ 10 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %21:vgpr_32 = V_ADD_U32_e64 500, %20, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %11[ 19 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Instr: %22:vgpr_32 = V_MOV_B32_e32 7, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %21[ 15 ]
+# CHECK: Vreg: %9[ 10 ]
+# CHECK: Vreg: %11[ 18 ]
+# CHECK: Vreg: %13[ 6 ]
+# CHECK: Vreg: %20[ 9 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Instr: %23:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %21[ 14 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %11[ 17 ]
+# CHECK: Vreg: %13[ 5 ]
+# CHECK: Vreg: %20[ 8 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %22[ 2 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Instr: %24:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %11[ 16 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %20[ 7 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Instr: %25:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %26:sreg_32 = PHI undef %27:sreg_32, %bb.0, %28, %bb.2, undef %29:sreg_32, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %30:sreg_32 = PHI undef %31:sreg_32, %bb.0, %32, %bb.2, undef %33:sreg_32, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %34:sreg_32 = PHI %24, %bb.0, %34, %bb.2, %35, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %36:sreg_32 = PHI %24, %bb.0, %37, %bb.2, %24, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %38:vgpr_32 = PHI %25, %bb.0, %39, %bb.2, %25, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Instr: %40:vgpr_32 = PHI %23, %bb.0, %41, %bb.2, %42, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %38[ 9 ]
+# CHECK: Instr: %43:vgpr_32 = PHI %22, %bb.0, %44, %bb.2, %45, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %40[ 8 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %38[ 9 ]
+# CHECK: Instr: %46:sreg_32 = S_OR_B32 killed %30, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %40[ 7 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %20[ 5 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %43[ LoopTag+21 ]
+# CHECK: Vreg: %38[ 8 ]
+# CHECK: Instr: %47:sreg_32 = S_OR_B32 killed %26, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %11[ 13 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %20[ 4 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %46[ 2 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %43[ LoopTag+20 ]
+# CHECK: Vreg: %38[ 7 ]
+# CHECK: Instr: %48:sreg_32 = SI_IF %13, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %47[ 1 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %11[ 12 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %20[ 3 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+19 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %28:sreg_32 = PHI %47, %bb.1, %49, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: Instr: %32:sreg_32 = PHI %46, %bb.1, %50, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: Instr: %51:vgpr_32 = PHI undef %52:vgpr_32, %bb.1, %53, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: Instr: %54:vgpr_32 = PHI undef %52:vgpr_32, %bb.1, %55, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %51[ 7 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: Instr: %56:vgpr_32 = PHI undef %52:vgpr_32, %bb.1, %57, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %51[ 7 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: Instr: %44:vgpr_32 = PHI undef %52:vgpr_32, %bb.1, %58, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %56[ 7 ]
+# CHECK: Vreg: %51[ 7 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: Instr: %41:vgpr_32 = PHI undef %52:vgpr_32, %bb.1, %59, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %56[ 7 ]
+# CHECK: Vreg: %44[ 4 ]
+# CHECK: Vreg: %51[ 7 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: Instr: %39:vgpr_32 = PHI undef %52:vgpr_32, %bb.1, %60, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %56[ 7 ]
+# CHECK: Vreg: %44[ 4 ]
+# CHECK: Vreg: %51[ 7 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %41[ 4 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: Instr: SI_END_CF killed %48, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %40[ 8 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %28[ 3 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %54[ 6 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %56[ 6 ]
+# CHECK: Vreg: %44[ 3 ]
+# CHECK: Vreg: %51[ 6 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %13[ 6 ]
+# CHECK: Vreg: %39[ 3 ]
+# CHECK: Vreg: %20[ 9 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %41[ 3 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+17 ]
+# CHECK: Vreg: %38[ LoopTag+19 ]
+# CHECK: Instr: %37:sreg_32 = SI_IF_BREAK %32, killed %36, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %40[ 7 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %28[ 2 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %54[ 5 ]
+# CHECK: Vreg: %11[ 9 ]
+# CHECK: Vreg: %56[ 5 ]
+# CHECK: Vreg: %44[ 2 ]
+# CHECK: Vreg: %51[ 5 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %13[ 5 ]
+# CHECK: Vreg: %39[ 2 ]
+# CHECK: Vreg: %20[ 8 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %41[ 2 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+16 ]
+# CHECK: Vreg: %38[ LoopTag+18 ]
+# CHECK: Instr: SI_LOOP %37, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %54[ 4 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %56[ 4 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 1 ]
+# CHECK: Vreg: %51[ 4 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %20[ 7 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %43[ LoopTag+15 ]
+# CHECK: Vreg: %38[ LoopTag+17 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %54[ 3 ]
+# CHECK: Vreg: %11[ 7 ]
+# CHECK: Vreg: %56[ 3 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %51[ 3 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %43[ LoopTag+14 ]
+# CHECK: Vreg: %38[ LoopTag+16 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %54[ 3 ]
+# CHECK: Vreg: %11[ 7 ]
+# CHECK: Vreg: %56[ 3 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %51[ 3 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %43[ LoopTag+14 ]
+# CHECK: Vreg: %38[ LoopTag+16 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: SI_END_CF killed %37, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %54[ 2 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %56[ 2 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %51[ 2 ]
+# CHECK: Vreg: %13[ 14 ]
+# CHECK: Vreg: %20[ 17 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %10[ 16 ]
+# CHECK: Vreg: %43[ LoopTag+13 ]
+# CHECK: Vreg: %38[ LoopTag+15 ]
+# CHECK: Instr: %61:sreg_32 = SI_IF killed %28, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %54[ 1 ]
+# CHECK: Vreg: %11[ 5 ]
+# CHECK: Vreg: %56[ 1 ]
+# CHECK: Vreg: %51[ 1 ]
+# CHECK: Vreg: %13[ 13 ]
+# CHECK: Vreg: %20[ 16 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %10[ 15 ]
+# CHECK: Vreg: %43[ LoopTag+12 ]
+# CHECK: Vreg: %38[ LoopTag+14 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %20[ 15 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %43[ LoopTag+11 ]
+# CHECK: Vreg: %38[ LoopTag+13 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %20[ 15 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %43[ LoopTag+11 ]
+# CHECK: Vreg: %38[ LoopTag+13 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: GLOBAL_STORE_DWORD %9, %21, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %61[ 4 ]
+# CHECK: Vreg: %11[ 7 ]
+# CHECK: Vreg: %13[ 15 ]
+# CHECK: Vreg: %20[ 18 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %10[ 17 ]
+# CHECK: Vreg: %43[ LoopTag+14 ]
+# CHECK: Vreg: %38[ LoopTag+16 ]
+# CHECK: Instr: %62:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %9[ 18 ]
+# CHECK: Vreg: %61[ 3 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %13[ 14 ]
+# CHECK: Vreg: %20[ 17 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %10[ 16 ]
+# CHECK: Vreg: %43[ LoopTag+13 ]
+# CHECK: Vreg: %38[ LoopTag+15 ]
+# CHECK: Instr: %63:vgpr_32 = V_MOV_B32_e32 1000, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %9[ 17 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %11[ 5 ]
+# CHECK: Vreg: %13[ 13 ]
+# CHECK: Vreg: %20[ 16 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %10[ 15 ]
+# CHECK: Vreg: %62[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+12 ]
+# CHECK: Vreg: %38[ LoopTag+14 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9[ 16 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %20[ 15 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+11 ]
+# CHECK: Vreg: %38[ LoopTag+13 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9[ 16 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %20[ 15 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+11 ]
+# CHECK: Vreg: %38[ LoopTag+13 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %57:vgpr_32 = GLOBAL_LOAD_DWORD %10, 0, 0, implicit $exec :: (load (s32) from %ir.p2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %21[ 21 ]
+# CHECK: Vreg: %47[ 11 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %11[ 24 ]
+# CHECK: Vreg: %13[ 20 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %46[ 8 ]
+# CHECK: Vreg: %34[ 17 ]
+# CHECK: Vreg: %48[ 14 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %36[ 15 ]
+# CHECK: Vreg: %43[ LoopTag+31 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Instr: %53:vgpr_32 = V_MUL_LO_U32_e64 %57, %20, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 20 ]
+# CHECK: Vreg: %47[ 10 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %11[ 23 ]
+# CHECK: Vreg: %13[ 19 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %46[ 7 ]
+# CHECK: Vreg: %34[ 16 ]
+# CHECK: Vreg: %48[ 13 ]
+# CHECK: Vreg: %10[ 21 ]
+# CHECK: Vreg: %36[ 14 ]
+# CHECK: Vreg: %43[ LoopTag+30 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %9, %53, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 19 ]
+# CHECK: Vreg: %47[ 9 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %11[ 22 ]
+# CHECK: Vreg: %13[ 18 ]
+# CHECK: Vreg: %20[ 21 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %46[ 6 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 15 ]
+# CHECK: Vreg: %48[ 12 ]
+# CHECK: Vreg: %10[ 20 ]
+# CHECK: Vreg: %36[ 13 ]
+# CHECK: Vreg: %43[ LoopTag+29 ]
+# CHECK: Vreg: %57[ 11 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Instr: %55:vgpr_32 = V_SUB_U32_e64 %53, %40, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 18 ]
+# CHECK: Vreg: %47[ 8 ]
+# CHECK: Vreg: %9[ 18 ]
+# CHECK: Vreg: %11[ 21 ]
+# CHECK: Vreg: %13[ 17 ]
+# CHECK: Vreg: %20[ 20 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %46[ 5 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %48[ 11 ]
+# CHECK: Vreg: %10[ 19 ]
+# CHECK: Vreg: %36[ 12 ]
+# CHECK: Vreg: %43[ LoopTag+28 ]
+# CHECK: Vreg: %57[ 10 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Instr: %60:vgpr_32 = V_ADD_U32_e64 1, %38, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %40[ 18 ]
+# CHECK: Vreg: %21[ 17 ]
+# CHECK: Vreg: %47[ 7 ]
+# CHECK: Vreg: %9[ 17 ]
+# CHECK: Vreg: %11[ 20 ]
+# CHECK: Vreg: %13[ 16 ]
+# CHECK: Vreg: %20[ 19 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %46[ 4 ]
+# CHECK: Vreg: %53[ 9 ]
+# CHECK: Vreg: %34[ 13 ]
+# CHECK: Vreg: %48[ 10 ]
+# CHECK: Vreg: %10[ 18 ]
+# CHECK: Vreg: %55[ 9 ]
+# CHECK: Vreg: %36[ 11 ]
+# CHECK: Vreg: %43[ LoopTag+27 ]
+# CHECK: Vreg: %57[ 9 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Instr: %64:sreg_32 = V_CMP_GE_U32_e64 %60, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %40[ 17 ]
+# CHECK: Vreg: %21[ 16 ]
+# CHECK: Vreg: %47[ 6 ]
+# CHECK: Vreg: %9[ 16 ]
+# CHECK: Vreg: %11[ 19 ]
+# CHECK: Vreg: %13[ 15 ]
+# CHECK: Vreg: %20[ 18 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %46[ 3 ]
+# CHECK: Vreg: %53[ 8 ]
+# CHECK: Vreg: %34[ 12 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %48[ 9 ]
+# CHECK: Vreg: %10[ 17 ]
+# CHECK: Vreg: %55[ 8 ]
+# CHECK: Vreg: %36[ 10 ]
+# CHECK: Vreg: %43[ LoopTag+26 ]
+# CHECK: Vreg: %57[ 8 ]
+# CHECK: Vreg: %38[ LoopTag+28 ]
+# CHECK: Instr: %59:vgpr_32 = V_MOV_B32_e32 52, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %64[ 3 ]
+# CHECK: Vreg: %40[ 16 ]
+# CHECK: Vreg: %21[ 15 ]
+# CHECK: Vreg: %47[ 5 ]
+# CHECK: Vreg: %9[ 15 ]
+# CHECK: Vreg: %11[ 18 ]
+# CHECK: Vreg: %13[ 14 ]
+# CHECK: Vreg: %20[ 17 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %46[ 2 ]
+# CHECK: Vreg: %53[ 7 ]
+# CHECK: Vreg: %34[ 11 ]
+# CHECK: Vreg: %60[ 7 ]
+# CHECK: Vreg: %48[ 8 ]
+# CHECK: Vreg: %10[ 16 ]
+# CHECK: Vreg: %55[ 7 ]
+# CHECK: Vreg: %36[ 9 ]
+# CHECK: Vreg: %43[ LoopTag+25 ]
+# CHECK: Vreg: %57[ 7 ]
+# CHECK: Vreg: %38[ LoopTag+27 ]
+# CHECK: Instr: %58:vgpr_32 = V_MOV_B32_e32 13, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %64[ 2 ]
+# CHECK: Vreg: %59[ 6 ]
+# CHECK: Vreg: %40[ 15 ]
+# CHECK: Vreg: %21[ 14 ]
+# CHECK: Vreg: %47[ 4 ]
+# CHECK: Vreg: %9[ 14 ]
+# CHECK: Vreg: %11[ 17 ]
+# CHECK: Vreg: %13[ 13 ]
+# CHECK: Vreg: %20[ 16 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %53[ 6 ]
+# CHECK: Vreg: %34[ 10 ]
+# CHECK: Vreg: %60[ 6 ]
+# CHECK: Vreg: %48[ 7 ]
+# CHECK: Vreg: %10[ 15 ]
+# CHECK: Vreg: %55[ 6 ]
+# CHECK: Vreg: %36[ 8 ]
+# CHECK: Vreg: %43[ LoopTag+24 ]
+# CHECK: Vreg: %57[ 6 ]
+# CHECK: Vreg: %38[ LoopTag+26 ]
+# CHECK: Instr: %65:sreg_32 = S_ANDN2_B32 killed %46, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %59[ 5 ]
+# CHECK: Vreg: %40[ 14 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %47[ 3 ]
+# CHECK: Vreg: %9[ 13 ]
+# CHECK: Vreg: %11[ 16 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %58[ 5 ]
+# CHECK: Vreg: %20[ 15 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %53[ 5 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %48[ 6 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %55[ 5 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Vreg: %43[ LoopTag+23 ]
+# CHECK: Vreg: %57[ 5 ]
+# CHECK: Vreg: %38[ LoopTag+25 ]
+# CHECK: Instr: %66:sreg_32 = S_AND_B32 killed %64, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %59[ 4 ]
+# CHECK: Vreg: %40[ 13 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %47[ 2 ]
+# CHECK: Vreg: %9[ 12 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %13[ 11 ]
+# CHECK: Vreg: %58[ 4 ]
+# CHECK: Vreg: %20[ 14 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %53[ 4 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %60[ 4 ]
+# CHECK: Vreg: %48[ 5 ]
+# CHECK: Vreg: %10[ 13 ]
+# CHECK: Vreg: %55[ 4 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %43[ LoopTag+22 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %38[ LoopTag+24 ]
+# CHECK: Instr: %50:sreg_32 = S_OR_B32 killed %65, killed %66, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %59[ 3 ]
+# CHECK: Vreg: %40[ 12 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %47[ 1 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %58[ 3 ]
+# CHECK: Vreg: %20[ 13 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %53[ 3 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %48[ 4 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Vreg: %55[ 3 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %43[ LoopTag+21 ]
+# CHECK: Vreg: %57[ 3 ]
+# CHECK: Vreg: %38[ LoopTag+23 ]
+# CHECK: Instr: %67:sreg_32 = S_ANDN2_B32 killed %47, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %59[ 2 ]
+# CHECK: Vreg: %40[ 11 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %9[ 10 ]
+# CHECK: Vreg: %11[ 13 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 12 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %53[ 2 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %60[ 2 ]
+# CHECK: Vreg: %48[ 3 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %55[ 2 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %43[ LoopTag+20 ]
+# CHECK: Vreg: %50[ 2 ]
+# CHECK: Vreg: %57[ 2 ]
+# CHECK: Vreg: %38[ LoopTag+22 ]
+# CHECK: Instr: %49:sreg_32 = COPY killed %67
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %59[ 1 ]
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %11[ 12 ]
+# CHECK: Vreg: %13[ 8 ]
+# CHECK: Vreg: %58[ 1 ]
+# CHECK: Vreg: %20[ 11 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %53[ 1 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %60[ 1 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %10[ 10 ]
+# CHECK: Vreg: %55[ 1 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+19 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %57[ 1 ]
+# CHECK: Vreg: %38[ LoopTag+21 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %68:vgpr_32 = PHI %56, %bb.3, %63, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9[ 16 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %20[ 15 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+11 ]
+# CHECK: Vreg: %38[ LoopTag+13 ]
+# CHECK: Instr: %69:vgpr_32 = PHI %54, %bb.3, %62, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9[ 16 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %68[ 3 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %20[ 15 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+11 ]
+# CHECK: Vreg: %38[ LoopTag+13 ]
+# CHECK: Instr: %70:vgpr_32 = PHI %51, %bb.3, %21, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9[ 16 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %68[ 3 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %20[ 15 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %43[ LoopTag+11 ]
+# CHECK: Vreg: %69[ LoopTag+12 ]
+# CHECK: Vreg: %38[ LoopTag+13 ]
+# CHECK: Instr: SI_END_CF killed %61, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 20 ]
+# CHECK: Vreg: %9[ 15 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %68[ 2 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %70[ LoopTag+12 ]
+# CHECK: Vreg: %13[ 11 ]
+# CHECK: Vreg: %20[ 14 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %10[ 13 ]
+# CHECK: Vreg: %43[ LoopTag+10 ]
+# CHECK: Vreg: %69[ LoopTag+11 ]
+# CHECK: Vreg: %38[ LoopTag+12 ]
+# CHECK: Instr: %42:vgpr_32 = V_ADD_U32_e64 1, killed %40, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 19 ]
+# CHECK: Vreg: %9[ 14 ]
+# CHECK: Vreg: %68[ 1 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %70[ LoopTag+11 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %20[ 13 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Vreg: %43[ LoopTag+9 ]
+# CHECK: Vreg: %69[ LoopTag+10 ]
+# CHECK: Vreg: %38[ LoopTag+11 ]
+# CHECK: Instr: %71:vgpr_32 = V_ADD_U32_e64 %68, %42, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %21[ 18 ]
+# CHECK: Vreg: %9[ 13 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %70[ LoopTag+10 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %20[ 12 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %43[ LoopTag+8 ]
+# CHECK: Vreg: %69[ LoopTag+9 ]
+# CHECK: Vreg: %38[ LoopTag+10 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %11, %71, 0, 0, implicit $exec :: (store (s32) into %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %21[ 17 ]
+# CHECK: Vreg: %9[ 12 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %68[ LoopTag+8 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %70[ LoopTag+9 ]
+# CHECK: Vreg: %13[ 8 ]
+# CHECK: Vreg: %20[ 11 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %10[ 10 ]
+# CHECK: Vreg: %43[ LoopTag+7 ]
+# CHECK: Vreg: %69[ LoopTag+8 ]
+# CHECK: Vreg: %38[ LoopTag+9 ]
+# CHECK: Instr: %72:sreg_32 = V_CMP_GE_U32_e64 %42, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+6 ]
+# CHECK: Vreg: %21[ 16 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %68[ LoopTag+7 ]
+# CHECK: Vreg: %11[ 19 ]
+# CHECK: Vreg: %70[ LoopTag+8 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %43[ LoopTag+6 ]
+# CHECK: Vreg: %69[ LoopTag+7 ]
+# CHECK: Vreg: %38[ LoopTag+8 ]
+# CHECK: Instr: %35:sreg_32 = SI_IF_BREAK killed %72, killed %34, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %71[ LoopTag+5 ]
+# CHECK: Vreg: %21[ 15 ]
+# CHECK: Vreg: %9[ 10 ]
+# CHECK: Vreg: %42[ 3 ]
+# CHECK: Vreg: %68[ LoopTag+6 ]
+# CHECK: Vreg: %11[ 18 ]
+# CHECK: Vreg: %70[ LoopTag+7 ]
+# CHECK: Vreg: %13[ 6 ]
+# CHECK: Vreg: %20[ 9 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %43[ LoopTag+5 ]
+# CHECK: Vreg: %69[ LoopTag+6 ]
+# CHECK: Vreg: %38[ LoopTag+7 ]
+# CHECK: Instr: %45:vgpr_32 = V_MOV_B32_e32 13, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %71[ LoopTag+4 ]
+# CHECK: Vreg: %21[ 14 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %68[ LoopTag+5 ]
+# CHECK: Vreg: %11[ 17 ]
+# CHECK: Vreg: %70[ LoopTag+6 ]
+# CHECK: Vreg: %13[ 5 ]
+# CHECK: Vreg: %20[ 8 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %43[ LoopTag+4 ]
+# CHECK: Vreg: %69[ LoopTag+5 ]
+# CHECK: Vreg: %38[ LoopTag+6 ]
+# CHECK: Instr: SI_LOOP %35, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %71[ LoopTag+3 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %68[ LoopTag+4 ]
+# CHECK: Vreg: %11[ 16 ]
+# CHECK: Vreg: %70[ LoopTag+5 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %20[ 7 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %43[ LoopTag+3 ]
+# CHECK: Vreg: %69[ LoopTag+4 ]
+# CHECK: Vreg: %38[ LoopTag+5 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+2 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %68[ LoopTag+3 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %70[ LoopTag+4 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %43[ LoopTag+2 ]
+# CHECK: Vreg: %69[ LoopTag+3 ]
+# CHECK: Vreg: %38[ LoopTag+4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+2 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %68[ LoopTag+3 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %70[ LoopTag+4 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %43[ LoopTag+2 ]
+# CHECK: Vreg: %69[ LoopTag+3 ]
+# CHECK: Vreg: %38[ LoopTag+4 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: SI_END_CF killed %35, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %71[ 1 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %68[ 2 ]
+# CHECK: Vreg: %70[ 3 ]
+# CHECK: Vreg: %43[ 1 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Instr: %73:vgpr_32 = V_ADD3_U32_e64 killed %71, killed %43, %71, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %68[ 1 ]
+# CHECK: Vreg: %70[ 2 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Instr: %74:vgpr_32 = V_ADD3_U32_e64 killed %73, killed %68, killed %69, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %70[ 1 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Instr: %75:vgpr_32 = V_ADD3_U32_e64 killed %74, killed %70, killed %38, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Instr: %76:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %75, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %75[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %76
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test8(ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, i1 %cond, i32 %TC1, i32 %TC2) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  %add1 = add i32 %ld1, 100
+  br label %1
+  1:
+  %phi.inc1 = phi i32 [ 0, %0 ], [ %inc1, %4 ], [ 0, %5 ]
+  %phi.inc2 = phi i32 [ 10, %0 ], [ 52, %4 ], [ %inc2, %5 ]
+  %phi1 = phi i32 [ 7, %0 ], [ 13, %4 ], [ 13, %5 ]
+  br i1 %cond, label %2, label %3
+  2:
+  %add2 = add i32 %ld1, 500
+  store i32 %add2, ptr addrspace(1) %p3
+  br label %5
+  3:
+  %ld2 = load i32, ptr addrspace(1) %p2, align 4
+  %mul = mul i32 %ld2, %ld1
+  store i32 %mul, ptr addrspace(1) %p3
+  br label %4
+  4:
+  %sub = sub i32 %mul, %phi.inc2
+  %inc1 = add i32 %phi.inc1, 1
+  %cond1 = icmp ult i32 %inc1, %TC1
+  br i1 %cond1, label %1, label %5
+  5:
+  %phi2 = phi i32 [ 1000, %2 ], [ %ld2, %4 ]
+  %phi3 = phi i32 [ 100, %2 ], [ %sub, %4 ]
+  %phi4 = phi i32 [ %add2, %2 ], [ %mul, %4 ]
+  %inc2 = add i32 %phi.inc2, 1
+  %add3 = add i32 %phi2, %inc2
+  store i32 %add3, ptr addrspace(1) %p1
+  %add4 = add i32 %add3, %phi1
+  %cond2 = icmp ult i32 %inc2, %TC2
+  br i1 %cond2, label %1, label %6
+  6:
+  %add5 = add i32 %add4, %add3
+  %add6 = add i32 %add5, %phi2
+  %add7 = add i32 %add6, %phi3
+  %add8 = add i32 %add7, %phi4
+  %add9 = add i32 %add8, %phi.inc1
+  ret i32 %add9
+  }
+...
+
+---
+name:            test8
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8
+  
+    %45:vgpr_32 = COPY killed $vgpr8
+    %44:vgpr_32 = COPY killed $vgpr7
+    %43:vgpr_32 = COPY killed $vgpr6
+    %42:vgpr_32 = COPY killed $vgpr5
+    %41:vgpr_32 = COPY killed $vgpr4
+    %40:vgpr_32 = COPY killed $vgpr3
+    %39:vgpr_32 = COPY killed $vgpr2
+    %38:vgpr_32 = COPY killed $vgpr1
+    %37:vgpr_32 = COPY killed $vgpr0
+    %92:vreg_64 = REG_SEQUENCE killed %41, %subreg.sub0, killed %42, %subreg.sub1
+    %91:vreg_64 = REG_SEQUENCE killed %39, %subreg.sub0, killed %40, %subreg.sub1
+    %90:vreg_64 = REG_SEQUENCE killed %37, %subreg.sub0, killed %38, %subreg.sub1
+    %55:vgpr_32 = V_AND_B32_e64 1, killed %43, implicit $exec
+    %56:sreg_32 = V_CMP_NE_U32_e64 1, killed %55, implicit $exec
+    %57:vgpr_32 = GLOBAL_LOAD_UBYTE %90, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %59:vgpr_32 = GLOBAL_LOAD_UBYTE %90, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %62:vgpr_32 = V_LSHL_OR_B32_e64 killed %59, 8, killed %57, implicit $exec
+    %63:vgpr_32 = GLOBAL_LOAD_UBYTE %90, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %65:vgpr_32 = GLOBAL_LOAD_UBYTE %90, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %67:vgpr_32 = V_LSHL_OR_B32_e64 killed %65, 8, killed %63, implicit $exec
+    %1:vgpr_32 = V_LSHL_OR_B32_e64 killed %67, 16, killed %62, implicit $exec
+    %2:vgpr_32 = V_ADD_U32_e64 500, %1, 0, implicit $exec
+    %51:vgpr_32 = V_MOV_B32_e32 7, implicit $exec
+    %50:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
+    %49:sreg_32 = S_MOV_B32 0
+    %93:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  
+  bb.1:
+    successors: %bb.5(0x40000000), %bb.2(0x40000000)
+  
+    %105:sreg_32 = PHI undef %101:sreg_32, %bb.0, %16, %bb.2, undef %102:sreg_32, %bb.6
+    %98:sreg_32 = PHI undef %94:sreg_32, %bb.0, %15, %bb.2, undef %95:sreg_32, %bb.6
+    %3:sreg_32 = PHI %49, %bb.0, %3, %bb.2, %29, %bb.6
+    %4:sreg_32 = PHI %49, %bb.0, %17, %bb.2, %49, %bb.6
+    %5:vgpr_32 = PHI %93, %bb.0, %14, %bb.2, %93, %bb.6
+    %6:vgpr_32 = PHI %50, %bb.0, %86, %bb.2, %27, %bb.6
+    %7:vgpr_32 = PHI %51, %bb.0, %88, %bb.2, %80, %bb.6
+    %96:sreg_32 = S_OR_B32 killed %98, $exec_lo, implicit-def dead $scc
+    %103:sreg_32 = S_OR_B32 killed %105, $exec_lo, implicit-def dead $scc
+    %8:sreg_32 = SI_IF %56, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.5
+  
+  bb.2:
+    successors: %bb.3(0x40000000), %bb.1(0x40000000)
+  
+    %16:sreg_32 = PHI %103, %bb.1, %104, %bb.5
+    %15:sreg_32 = PHI %96, %bb.1, %97, %bb.5
+    %9:vgpr_32 = PHI undef %70:vgpr_32, %bb.1, %20, %bb.5
+    %10:vgpr_32 = PHI undef %70:vgpr_32, %bb.1, %21, %bb.5
+    %11:vgpr_32 = PHI undef %70:vgpr_32, %bb.1, %19, %bb.5
+    %88:vgpr_32 = PHI undef %70:vgpr_32, %bb.1, %89, %bb.5
+    %86:vgpr_32 = PHI undef %70:vgpr_32, %bb.1, %87, %bb.5
+    %14:vgpr_32 = PHI undef %70:vgpr_32, %bb.1, %22, %bb.5
+    SI_END_CF killed %8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %17:sreg_32 = SI_IF_BREAK %15, killed %4, implicit-def dead $scc
+    SI_LOOP %17, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.3
+  
+  bb.3:
+    successors: %bb.4(0x40000000), %bb.6(0x40000000)
+  
+    SI_END_CF killed %17, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %18:sreg_32 = SI_IF killed %16, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.4
+  
+  bb.4:
+    successors: %bb.6(0x80000000)
+  
+    GLOBAL_STORE_DWORD %92, %2, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    %79:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+    %78:vgpr_32 = V_MOV_B32_e32 1000, implicit $exec
+    S_BRANCH %bb.6
+  
+  bb.5:
+    successors: %bb.2(0x80000000)
+  
+    %19:vgpr_32 = GLOBAL_LOAD_DWORD %91, 0, 0, implicit $exec :: (load (s32) from %ir.p2, addrspace 1)
+    %20:vgpr_32 = V_MUL_LO_U32_e64 %19, %1, implicit $exec
+    GLOBAL_STORE_DWORD %92, %20, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    %21:vgpr_32 = V_SUB_U32_e64 %20, %6, 0, implicit $exec
+    %22:vgpr_32 = V_ADD_U32_e64 1, %5, 0, implicit $exec
+    %77:sreg_32 = V_CMP_GE_U32_e64 %22, %44, implicit $exec
+    %87:vgpr_32 = V_MOV_B32_e32 52, implicit $exec
+    %89:vgpr_32 = V_MOV_B32_e32 13, implicit $exec
+    %99:sreg_32 = S_ANDN2_B32 killed %96, $exec_lo, implicit-def dead $scc
+    %100:sreg_32 = S_AND_B32 killed %77, $exec_lo, implicit-def dead $scc
+    %97:sreg_32 = S_OR_B32 killed %99, killed %100, implicit-def dead $scc
+    %106:sreg_32 = S_ANDN2_B32 killed %103, $exec_lo, implicit-def dead $scc
+    %104:sreg_32 = COPY killed %106
+    S_BRANCH %bb.2
+  
+  bb.6:
+    successors: %bb.7(0x04000000), %bb.1(0x7c000000)
+  
+    %24:vgpr_32 = PHI %11, %bb.3, %78, %bb.4
+    %25:vgpr_32 = PHI %10, %bb.3, %79, %bb.4
+    %26:vgpr_32 = PHI %9, %bb.3, %2, %bb.4
+    SI_END_CF killed %18, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %27:vgpr_32 = V_ADD_U32_e64 1, killed %6, 0, implicit $exec
+    %28:vgpr_32 = V_ADD_U32_e64 %24, %27, 0, implicit $exec
+    GLOBAL_STORE_DWORD %90, %28, 0, 0, implicit $exec :: (store (s32) into %ir.p1, addrspace 1)
+    %81:sreg_32 = V_CMP_GE_U32_e64 %27, %45, implicit $exec
+    %29:sreg_32 = SI_IF_BREAK killed %81, killed %3, implicit-def dead $scc
+    %80:vgpr_32 = V_MOV_B32_e32 13, implicit $exec
+    SI_LOOP %29, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.7
+  
+  bb.7:
+    SI_END_CF killed %29, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %82:vgpr_32 = V_ADD3_U32_e64 killed %28, killed %7, %28, implicit $exec
+    %83:vgpr_32 = V_ADD3_U32_e64 killed %82, killed %24, killed %25, implicit $exec
+    %84:vgpr_32 = V_ADD3_U32_e64 killed %83, killed %26, killed %5, implicit $exec
+    %85:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %84, implicit $exec
+    $sgpr0 = COPY killed %85
+    SI_RETURN_TO_EPILOG killed $sgpr0
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-b.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-b.mir
new file mode 100644
index 0000000000000..b3558b8410a83
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-b.mir
@@ -0,0 +1,2646 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#            bb.0.entry
+#           /         |
+#       bb.4.bb1      |
+#         /   |       |
+#  bb.5.bb2   |       |
+#         \   |       |
+#        bb.7.bb3     |
+#         |    \      |
+#         | bb.10.bb5 |
+#         |    /      |
+#        bb.8.Flow    |
+#         /   |       |
+#  bb.9.bb4   |       |
+#         \   |       |
+#        bb.11.bb6    |
+#            |        |
+#            bb.6.Flow2
+#             /       |
+# bb.1.loop.preheader |
+#          |          |
+#  +--->bb.3.loop     |
+#   +------+          |
+#          |          |
+#     bb.12.Flow1     |
+#            \        |
+#            bb.2.Flow3
+#                |
+#           bb.13.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test11 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr12
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %2[ 24 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %3[ 38 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %2[ 22 ]
+# CHECK: Vreg: %4[ 37 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %3[ 37 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %2[ 21 ]
+# CHECK: Vreg: %4[ 36 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %3[ 36 ]
+# CHECK: Vreg: %5[ 22 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %4[ 35 ]
+# CHECK: Vreg: %6[ 21 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %3[ 35 ]
+# CHECK: Vreg: %5[ 21 ]
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %4[ 34 ]
+# CHECK: Vreg: %6[ 20 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %3[ 34 ]
+# CHECK: Vreg: %5[ 20 ]
+# CHECK: Instr: %9:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %2[ 18 ]
+# CHECK: Vreg: %4[ 33 ]
+# CHECK: Vreg: %6[ 19 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: Vreg: %3[ 33 ]
+# CHECK: Vreg: %5[ 19 ]
+# CHECK: Instr: %10:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %6[ 18 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %3[ 32 ]
+# CHECK: Vreg: %5[ 18 ]
+# CHECK: Instr: %11:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %6[ 17 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %3[ 31 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %5[ 17 ]
+# CHECK: Instr: %12:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %4[ 30 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %6[ 16 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %3[ 30 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %5[ 16 ]
+# CHECK: Instr: %13:vreg_64 = REG_SEQUENCE killed %8, %subreg.sub0, killed %7, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %4[ 29 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %6[ 15 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %5[ 15 ]
+# CHECK: Vreg: %12[ 2 ]
+# CHECK: Instr: %14:vreg_64 = REG_SEQUENCE %10, %subreg.sub0, %9, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %4[ 28 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %6[ 14 ]
+# CHECK: Vreg: %13[ 13 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %3[ 28 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %5[ 14 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: %15:vreg_64 = REG_SEQUENCE killed %12, %subreg.sub0, killed %11, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %14[ 42 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %9[ 12 ]
+# CHECK: Vreg: %4[ 27 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %6[ 13 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %3[ 27 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Vreg: %5[ 13 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %16:vgpr_32 = V_AND_B32_e64 1, killed %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %14[ 41 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %4[ 26 ]
+# CHECK: Vreg: %6[ 12 ]
+# CHECK: Vreg: %13[ 11 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %3[ 26 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %5[ 12 ]
+# CHECK: Instr: %17:sreg_32 = V_CMP_NE_U32_e64 1, killed %16, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 40 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %9[ 10 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %4[ 25 ]
+# CHECK: Vreg: %6[ 11 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %3[ 25 ]
+# CHECK: Vreg: %10[ 10 ]
+# CHECK: Vreg: %5[ 11 ]
+# CHECK: Instr: %18:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 39 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %4[ 24 ]
+# CHECK: Vreg: %6[ 10 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 24 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %17[ 8 ]
+# CHECK: Vreg: %5[ 10 ]
+# CHECK: Instr: %19:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 38 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %4[ 23 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %6[ 9 ]
+# CHECK: Vreg: %13[ 8 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 23 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %17[ 7 ]
+# CHECK: Vreg: %5[ 9 ]
+# CHECK: Instr: %20:vgpr_32 = V_LSHL_OR_B32_e64 killed %19, 8, killed %18, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 37 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %4[ 22 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %6[ 8 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %3[ 22 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %17[ 6 ]
+# CHECK: Vreg: %5[ 8 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %21:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 36 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %4[ 21 ]
+# CHECK: Vreg: %6[ 7 ]
+# CHECK: Vreg: %13[ 6 ]
+# CHECK: Vreg: %20[ 3 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %17[ 5 ]
+# CHECK: Vreg: %5[ 7 ]
+# CHECK: Instr: %22:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 35 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %4[ 20 ]
+# CHECK: Vreg: %6[ 6 ]
+# CHECK: Vreg: %13[ 5 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %17[ 4 ]
+# CHECK: Vreg: %5[ 6 ]
+# CHECK: Instr: %23:vgpr_32 = V_LSHL_OR_B32_e64 killed %22, 8, killed %21, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 34 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 19 ]
+# CHECK: Vreg: %6[ 5 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %15:sub0[ 15 ]
+# CHECK: Vreg: %15:sub1[ 16 ]
+# CHECK: Vreg: %15[ 23 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 19 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Vreg: %5[ 5 ]
+# CHECK: Instr: %24:vgpr_32 = V_LSHL_OR_B32_e64 killed %23, 16, killed %20, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 33 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %4[ 18 ]
+# CHECK: Vreg: %6[ 4 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %15:sub0[ 14 ]
+# CHECK: Vreg: %15:sub1[ 15 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Instr: %25:vgpr_32 = V_ADD_U32_e64 100, %24, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 32 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %4[ 17 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %15:sub0[ 13 ]
+# CHECK: Vreg: %15:sub1[ 14 ]
+# CHECK: Vreg: %15[ 21 ]
+# CHECK: Vreg: %3[ 17 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Instr: %26:sreg_32 = SI_IF killed %17, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 31 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %4[ 16 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %15:sub0[ 12 ]
+# CHECK: Vreg: %15:sub1[ 13 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %3[ 16 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %24[ 1 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %14[ 30 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %4[ 15 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %15:sub0[ 11 ]
+# CHECK: Vreg: %15:sub1[ 12 ]
+# CHECK: Vreg: %15[ 19 ]
+# CHECK: Vreg: %3[ 15 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %14[ 30 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %4[ 15 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %15:sub0[ 11 ]
+# CHECK: Vreg: %15:sub1[ 12 ]
+# CHECK: Vreg: %15[ 19 ]
+# CHECK: Vreg: %3[ 15 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %27:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 23 ]
+# CHECK: Vreg: %59[ 17 ]
+# CHECK: Vreg: %61[ 18 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %37[ 24 ]
+# CHECK: Vreg: %48[ 5 ]
+# CHECK: Vreg: %50[ 6 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 22 ]
+# CHECK: Vreg: %59[ 16 ]
+# CHECK: Vreg: %61[ 17 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %48[ 4 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %33[ 22 ]
+# CHECK: Vreg: %59[ 16 ]
+# CHECK: Vreg: %61[ 17 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %48[ 4 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %28:vgpr_32 = PHI %29, %bb.6, %30, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Instr: %31:vgpr_32 = PHI %32, %bb.6, %33, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %28[ 3 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Instr: %34:vgpr_32 = PHI %35, %bb.6, %36, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %28[ 3 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %31[ 3 ]
+# CHECK: Instr: SI_END_CF killed %37, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %28[ 2 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %31[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %38:sreg_32 = PHI %27, %bb.1, %39, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+22 ]
+# CHECK: Vreg: %59[ 16 ]
+# CHECK: Vreg: %61[ 17 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+23 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %48[ 4 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Instr: %40:sreg_32 = PHI %27, %bb.1, %41, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+22 ]
+# CHECK: Vreg: %59[ 16 ]
+# CHECK: Vreg: %61[ 17 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+23 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %48[ 4 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %38[ 18 ]
+# CHECK: Instr: %30:vgpr_32 = PHI %42, %bb.1, %36, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+22 ]
+# CHECK: Vreg: %59[ 16 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %61[ 17 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+23 ]
+# CHECK: Vreg: %48[ 4 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %38[ 18 ]
+# CHECK: Instr: %43:sreg_32_xm0 = S_ASHR_I32 %40, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+21 ]
+# CHECK: Vreg: %59[ 15 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %61[ 16 ]
+# CHECK: Vreg: %30[ LoopTag+21 ]
+# CHECK: Vreg: %37[ LoopTag+22 ]
+# CHECK: Vreg: %48[ 3 ]
+# CHECK: Vreg: %50[ 4 ]
+# CHECK: Vreg: %38[ 17 ]
+# CHECK: Instr: %44:sreg_64 = REG_SEQUENCE %40, %subreg.sub0, killed %43, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+20 ]
+# CHECK: Vreg: %59[ 14 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %61[ 15 ]
+# CHECK: Vreg: %30[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+21 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %50[ 3 ]
+# CHECK: Vreg: %38[ 16 ]
+# CHECK: Instr: %45:sreg_64 = nsw S_LSHL_B64 killed %44, 3, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+19 ]
+# CHECK: Vreg: %59[ 13 ]
+# CHECK: Vreg: %40[ 11 ]
+# CHECK: Vreg: %61[ 14 ]
+# CHECK: Vreg: %30[ LoopTag+19 ]
+# CHECK: Vreg: %37[ LoopTag+20 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %50[ 2 ]
+# CHECK: Vreg: %38[ 15 ]
+# CHECK: Instr: %46:vgpr_32, %47:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %48, %45.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45:sub0[ 0 ]
+# CHECK: Vreg: %45:sub1[ 1 ]
+# CHECK: Vreg: %33[ LoopTag+18 ]
+# CHECK: Vreg: %59[ 12 ]
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %61[ 13 ]
+# CHECK: Vreg: %30[ LoopTag+18 ]
+# CHECK: Vreg: %37[ LoopTag+19 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %38[ 14 ]
+# CHECK: Instr: %49:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %45.sub1, %50, killed %47, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45:sub1[ 0 ]
+# CHECK: Vreg: %33[ LoopTag+17 ]
+# CHECK: Vreg: %59[ 11 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %61[ 12 ]
+# CHECK: Vreg: %30[ LoopTag+17 ]
+# CHECK: Vreg: %37[ LoopTag+18 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %48[ 19 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %38[ 13 ]
+# CHECK: Instr: %51:vreg_64 = REG_SEQUENCE killed %46, %subreg.sub0, killed %49, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+16 ]
+# CHECK: Vreg: %59[ 10 ]
+# CHECK: Vreg: %40[ 8 ]
+# CHECK: Vreg: %61[ 11 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %30[ LoopTag+16 ]
+# CHECK: Vreg: %37[ LoopTag+17 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %48[ 18 ]
+# CHECK: Vreg: %50[ 19 ]
+# CHECK: Vreg: %38[ 12 ]
+# CHECK: Instr: %52:vgpr_32 = GLOBAL_LOAD_UBYTE %51, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+15 ]
+# CHECK: Vreg: %59[ 9 ]
+# CHECK: Vreg: %40[ 7 ]
+# CHECK: Vreg: %61[ 10 ]
+# CHECK: Vreg: %30[ LoopTag+15 ]
+# CHECK: Vreg: %37[ LoopTag+16 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %48[ 17 ]
+# CHECK: Vreg: %50[ 18 ]
+# CHECK: Vreg: %38[ 11 ]
+# CHECK: Instr: %53:vgpr_32 = GLOBAL_LOAD_UBYTE %51, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %33[ LoopTag+14 ]
+# CHECK: Vreg: %59[ 8 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %61[ 9 ]
+# CHECK: Vreg: %30[ LoopTag+14 ]
+# CHECK: Vreg: %37[ LoopTag+15 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %48[ 16 ]
+# CHECK: Vreg: %50[ 17 ]
+# CHECK: Vreg: %38[ 10 ]
+# CHECK: Instr: %54:vgpr_32 = V_LSHL_OR_B32_e64 killed %53, 8, killed %52, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %33[ LoopTag+13 ]
+# CHECK: Vreg: %59[ 7 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %61[ 8 ]
+# CHECK: Vreg: %30[ LoopTag+13 ]
+# CHECK: Vreg: %37[ LoopTag+14 ]
+# CHECK: Vreg: %51[ 1 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %48[ 15 ]
+# CHECK: Vreg: %50[ 16 ]
+# CHECK: Vreg: %38[ 9 ]
+# CHECK: Instr: %55:vgpr_32 = GLOBAL_LOAD_UBYTE %51, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+12 ]
+# CHECK: Vreg: %59[ 6 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %54[ 3 ]
+# CHECK: Vreg: %61[ 7 ]
+# CHECK: Vreg: %30[ LoopTag+12 ]
+# CHECK: Vreg: %37[ LoopTag+13 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %48[ 14 ]
+# CHECK: Vreg: %50[ 15 ]
+# CHECK: Vreg: %38[ 8 ]
+# CHECK: Instr: %56:vgpr_32 = GLOBAL_LOAD_UBYTE killed %51, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+11 ]
+# CHECK: Vreg: %59[ 5 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %54[ 2 ]
+# CHECK: Vreg: %61[ 6 ]
+# CHECK: Vreg: %30[ LoopTag+11 ]
+# CHECK: Vreg: %37[ LoopTag+12 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %48[ 13 ]
+# CHECK: Vreg: %55[ 1 ]
+# CHECK: Vreg: %50[ 14 ]
+# CHECK: Vreg: %38[ 7 ]
+# CHECK: Instr: %57:vgpr_32 = V_LSHL_OR_B32_e64 killed %56, 8, killed %55, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+10 ]
+# CHECK: Vreg: %59[ 4 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %54[ 1 ]
+# CHECK: Vreg: %61[ 5 ]
+# CHECK: Vreg: %30[ LoopTag+10 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+11 ]
+# CHECK: Vreg: %48[ 12 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %50[ 13 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Instr: %58:vgpr_32 = V_LSHL_OR_B32_e64 killed %57, 16, killed %54, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+9 ]
+# CHECK: Vreg: %59[ 3 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %61[ 4 ]
+# CHECK: Vreg: %30[ LoopTag+9 ]
+# CHECK: Vreg: %37[ LoopTag+10 ]
+# CHECK: Vreg: %48[ 11 ]
+# CHECK: Vreg: %50[ 12 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Instr: %41:sreg_32 = S_ADD_I32 killed %40, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+8 ]
+# CHECK: Vreg: %59[ 2 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %61[ 3 ]
+# CHECK: Vreg: %30[ LoopTag+8 ]
+# CHECK: Vreg: %37[ LoopTag+9 ]
+# CHECK: Vreg: %58[ 1 ]
+# CHECK: Vreg: %48[ 10 ]
+# CHECK: Vreg: %50[ 11 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Instr: %36:vgpr_32 = V_ADD_U32_e64 %41, killed %58, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+7 ]
+# CHECK: Vreg: %59[ 1 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %30[ LoopTag+7 ]
+# CHECK: Vreg: %37[ LoopTag+8 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %48[ 9 ]
+# CHECK: Vreg: %50[ 10 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %59, %36, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+6 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %30[ LoopTag+6 ]
+# CHECK: Vreg: %37[ LoopTag+7 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %48[ 8 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %50[ 9 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Instr: %60:sreg_32 = V_CMP_GE_U32_e64 %41, %61, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+5 ]
+# CHECK: Vreg: %59[ 19 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %30[ LoopTag+5 ]
+# CHECK: Vreg: %37[ LoopTag+6 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %48[ 7 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %50[ 8 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Instr: %39:sreg_32 = SI_IF_BREAK killed %60, killed %38, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+4 ]
+# CHECK: Vreg: %59[ 18 ]
+# CHECK: Vreg: %61[ 19 ]
+# CHECK: Vreg: %30[ LoopTag+4 ]
+# CHECK: Vreg: %37[ LoopTag+5 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %41[ 2 ]
+# CHECK: Vreg: %48[ 6 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %50[ 7 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Instr: SI_LOOP %39, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+3 ]
+# CHECK: Vreg: %59[ 17 ]
+# CHECK: Vreg: %61[ 18 ]
+# CHECK: Vreg: %30[ LoopTag+3 ]
+# CHECK: Vreg: %37[ LoopTag+4 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %48[ 5 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %50[ 6 ]
+# CHECK: Instr: S_BRANCH %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ LoopTag+2 ]
+# CHECK: Vreg: %59[ 16 ]
+# CHECK: Vreg: %61[ 17 ]
+# CHECK: Vreg: %30[ LoopTag+2 ]
+# CHECK: Vreg: %37[ LoopTag+3 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %48[ 4 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %33[ LoopTag+2 ]
+# CHECK: Vreg: %59[ 16 ]
+# CHECK: Vreg: %61[ 17 ]
+# CHECK: Vreg: %30[ LoopTag+2 ]
+# CHECK: Vreg: %37[ LoopTag+3 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %48[ 4 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %62:vreg_64 = REG_SEQUENCE killed %6, %subreg.sub0, killed %5, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 30 ]
+# CHECK: Vreg: %14[ 29 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %4[ 14 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %15:sub0[ 10 ]
+# CHECK: Vreg: %15:sub1[ 11 ]
+# CHECK: Vreg: %15[ 18 ]
+# CHECK: Vreg: %3[ 14 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %24[ 1 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %63:vgpr_32 = V_MUL_LO_U32_e64 100, %24, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %14[ 28 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %4[ 13 ]
+# CHECK: Vreg: %25[ 26 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %15:sub0[ 9 ]
+# CHECK: Vreg: %15:sub1[ 10 ]
+# CHECK: Vreg: %15[ 17 ]
+# CHECK: Vreg: %3[ 13 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %62[ 6 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %13, %63, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 28 ]
+# CHECK: Vreg: %14[ 27 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %4[ 12 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 25 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %15:sub0[ 8 ]
+# CHECK: Vreg: %15:sub1[ 9 ]
+# CHECK: Vreg: %15[ 16 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %24[ 4 ]
+# CHECK: Instr: %64:sreg_32 = V_CMP_GE_U32_e64 %63, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 27 ]
+# CHECK: Vreg: %14[ 26 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 24 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %15:sub0[ 7 ]
+# CHECK: Vreg: %15:sub1[ 8 ]
+# CHECK: Vreg: %15[ 15 ]
+# CHECK: Vreg: %3[ 11 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %62[ 4 ]
+# CHECK: Vreg: %24[ 3 ]
+# CHECK: Instr: %65:sreg_32 = V_CMP_LT_U32_e64 %63, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 8 ]
+# CHECK: Vreg: %26[ 26 ]
+# CHECK: Vreg: %14[ 25 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %4[ 10 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 23 ]
+# CHECK: Vreg: %13[ 11 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %15:sub0[ 6 ]
+# CHECK: Vreg: %15:sub1[ 7 ]
+# CHECK: Vreg: %15[ 14 ]
+# CHECK: Vreg: %3[ 10 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %62[ 3 ]
+# CHECK: Vreg: %24[ 2 ]
+# CHECK: Instr: %66:sreg_32 = SI_IF killed %65, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %14[ 24 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 9 ]
+# CHECK: Vreg: %63[ 8 ]
+# CHECK: Vreg: %25[ 22 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %15:sub0[ 5 ]
+# CHECK: Vreg: %15:sub1[ 6 ]
+# CHECK: Vreg: %15[ 13 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %24[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 6 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %14[ 23 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %25[ 21 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %15:sub0[ 4 ]
+# CHECK: Vreg: %15:sub1[ 5 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %62[ 1 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ 6 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %14[ 23 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %25[ 21 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %15:sub0[ 4 ]
+# CHECK: Vreg: %15:sub1[ 5 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %62[ 1 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %67:vgpr_32 = GLOBAL_LOAD_UBYTE %62, 24, 0, implicit $exec :: (load (s8) from %ir.gep2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 15 ]
+# CHECK: Vreg: %26[ 33 ]
+# CHECK: Vreg: %14[ 32 ]
+# CHECK: Vreg: %66[ 10 ]
+# CHECK: Vreg: %9[ 12 ]
+# CHECK: Vreg: %4[ 17 ]
+# CHECK: Vreg: %63[ 16 ]
+# CHECK: Vreg: %25[ 30 ]
+# CHECK: Vreg: %13[ 8 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %15:sub0[ 13 ]
+# CHECK: Vreg: %15:sub1[ 14 ]
+# CHECK: Vreg: %15[ 21 ]
+# CHECK: Vreg: %3[ 17 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Instr: %68:vgpr_32 = GLOBAL_LOAD_UBYTE %62, 25, 0, implicit $exec :: (load (s8) from %ir.gep2 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 14 ]
+# CHECK: Vreg: %26[ 32 ]
+# CHECK: Vreg: %14[ 31 ]
+# CHECK: Vreg: %66[ 9 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %4[ 16 ]
+# CHECK: Vreg: %63[ 15 ]
+# CHECK: Vreg: %25[ 29 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %15:sub0[ 12 ]
+# CHECK: Vreg: %15:sub1[ 13 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %3[ 16 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %10[ 10 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Instr: %69:vgpr_32 = V_LSHL_OR_B32_e64 killed %68, 8, killed %67, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %26[ 31 ]
+# CHECK: Vreg: %14[ 30 ]
+# CHECK: Vreg: %66[ 8 ]
+# CHECK: Vreg: %9[ 10 ]
+# CHECK: Vreg: %4[ 15 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %63[ 14 ]
+# CHECK: Vreg: %25[ 28 ]
+# CHECK: Vreg: %13[ 6 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %15:sub0[ 11 ]
+# CHECK: Vreg: %15:sub1[ 12 ]
+# CHECK: Vreg: %15[ 19 ]
+# CHECK: Vreg: %3[ 15 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %62[ 1 ]
+# CHECK: Instr: %70:vgpr_32 = GLOBAL_LOAD_UBYTE %62, 26, 0, implicit $exec :: (load (s8) from %ir.gep2 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 12 ]
+# CHECK: Vreg: %26[ 30 ]
+# CHECK: Vreg: %14[ 29 ]
+# CHECK: Vreg: %66[ 7 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %4[ 14 ]
+# CHECK: Vreg: %63[ 13 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %13[ 5 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %15:sub0[ 10 ]
+# CHECK: Vreg: %15:sub1[ 11 ]
+# CHECK: Vreg: %15[ 18 ]
+# CHECK: Vreg: %3[ 14 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Instr: %71:vgpr_32 = GLOBAL_LOAD_UBYTE %62, 27, 0, implicit $exec :: (load (s8) from %ir.gep2 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 11 ]
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %14[ 28 ]
+# CHECK: Vreg: %66[ 6 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %4[ 13 ]
+# CHECK: Vreg: %63[ 12 ]
+# CHECK: Vreg: %25[ 26 ]
+# CHECK: Vreg: %70[ 1 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %15:sub0[ 9 ]
+# CHECK: Vreg: %15:sub1[ 10 ]
+# CHECK: Vreg: %15[ 17 ]
+# CHECK: Vreg: %3[ 13 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Instr: %72:vgpr_32 = V_LSHL_OR_B32_e64 killed %71, 8, killed %70, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 10 ]
+# CHECK: Vreg: %26[ 28 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %14[ 27 ]
+# CHECK: Vreg: %66[ 5 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %4[ 12 ]
+# CHECK: Vreg: %63[ 11 ]
+# CHECK: Vreg: %25[ 25 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %15:sub0[ 8 ]
+# CHECK: Vreg: %15:sub1[ 9 ]
+# CHECK: Vreg: %15[ 16 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %62[ 16 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Instr: %73:vgpr_32 = V_LSHL_OR_B32_e64 killed %72, 16, killed %69, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 9 ]
+# CHECK: Vreg: %26[ 27 ]
+# CHECK: Vreg: %14[ 26 ]
+# CHECK: Vreg: %66[ 4 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %63[ 10 ]
+# CHECK: Vreg: %25[ 24 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %15:sub0[ 7 ]
+# CHECK: Vreg: %15:sub1[ 8 ]
+# CHECK: Vreg: %15[ 15 ]
+# CHECK: Vreg: %3[ 11 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %62[ 15 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Instr: %74:vgpr_32 = V_MUL_LO_U32_e64 killed %73, killed %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 8 ]
+# CHECK: Vreg: %26[ 26 ]
+# CHECK: Vreg: %14[ 25 ]
+# CHECK: Vreg: %66[ 3 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %4[ 10 ]
+# CHECK: Vreg: %63[ 9 ]
+# CHECK: Vreg: %25[ 23 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %15:sub0[ 6 ]
+# CHECK: Vreg: %15:sub1[ 7 ]
+# CHECK: Vreg: %15[ 14 ]
+# CHECK: Vreg: %3[ 10 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %62[ 14 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %13, %74, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %14[ 24 ]
+# CHECK: Vreg: %66[ 2 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 9 ]
+# CHECK: Vreg: %63[ 8 ]
+# CHECK: Vreg: %25[ 22 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %15:sub0[ 5 ]
+# CHECK: Vreg: %15:sub1[ 6 ]
+# CHECK: Vreg: %15[ 13 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 6 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %14[ 23 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %25[ 21 ]
+# CHECK: Vreg: %15:sub0[ 4 ]
+# CHECK: Vreg: %15:sub1[ 5 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %62[ 12 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ 6 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %14[ 23 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %25[ 21 ]
+# CHECK: Vreg: %15:sub0[ 4 ]
+# CHECK: Vreg: %15:sub1[ 5 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %62[ 12 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %29:vgpr_32 = PHI undef %75:vgpr_32, %bb.0, %76, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Instr: %32:vgpr_32 = PHI undef %75:vgpr_32, %bb.0, %77, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %35:vgpr_32 = PHI undef %75:vgpr_32, %bb.0, %78, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %42:vgpr_32 = PHI %24, %bb.0, undef %79:vgpr_32, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %48:vgpr_32 = PHI %10, %bb.0, undef %80:vgpr_32, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %50:vgpr_32 = PHI %9, %bb.0, undef %81:vgpr_32, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %48[ 8 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Instr: %59:vreg_64 = PHI %13, %bb.0, undef %82:vreg_64, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %48[ 8 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %50[ 9 ]
+# CHECK: Instr: %61:vgpr_32 = PHI %2, %bb.0, undef %83:vgpr_32, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %59[ 20 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %48[ 8 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %50[ 9 ]
+# CHECK: Instr: %33:vgpr_32 = PHI %25, %bb.0, undef %84:vgpr_32, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %59[ 20 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %61[ 21 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %48[ 8 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %50[ 9 ]
+# CHECK: Instr: %37:sreg_32 = SI_ELSE killed %26, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %33[ 25 ]
+# CHECK: Vreg: %59[ 19 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %61[ 20 ]
+# CHECK: Vreg: %42[ 3 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %48[ 7 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %50[ 8 ]
+# CHECK: Instr: S_BRANCH %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 24 ]
+# CHECK: Vreg: %59[ 18 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %61[ 19 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %48[ 6 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %50[ 7 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %33[ 24 ]
+# CHECK: Vreg: %59[ 18 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %61[ 19 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %48[ 6 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %50[ 7 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: %85:vgpr_32 = PHI %24, %bb.4, %74, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 6 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %14[ 23 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %25[ 21 ]
+# CHECK: Vreg: %15:sub0[ 4 ]
+# CHECK: Vreg: %15:sub1[ 5 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %62[ 12 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: SI_END_CF killed %66, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 5 ]
+# CHECK: Vreg: %26[ 23 ]
+# CHECK: Vreg: %14[ 22 ]
+# CHECK: Vreg: %85[ 7 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %4[ 7 ]
+# CHECK: Vreg: %63[ 6 ]
+# CHECK: Vreg: %25[ 20 ]
+# CHECK: Vreg: %15:sub0[ 3 ]
+# CHECK: Vreg: %15:sub1[ 4 ]
+# CHECK: Vreg: %15[ 11 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %62[ 11 ]
+# CHECK: Instr: %86:vgpr_32, %87:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %10, 24, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 4 ]
+# CHECK: Vreg: %26[ 22 ]
+# CHECK: Vreg: %14[ 21 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %4[ 6 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %25[ 19 ]
+# CHECK: Vreg: %15:sub0[ 2 ]
+# CHECK: Vreg: %15:sub1[ 3 ]
+# CHECK: Vreg: %15[ 10 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %62[ 10 ]
+# CHECK: Instr: %88:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 0, %9, killed %87, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 3 ]
+# CHECK: Vreg: %26[ 21 ]
+# CHECK: Vreg: %14[ 20 ]
+# CHECK: Vreg: %85[ 5 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Vreg: %4[ 5 ]
+# CHECK: Vreg: %63[ 4 ]
+# CHECK: Vreg: %25[ 18 ]
+# CHECK: Vreg: %15:sub0[ 1 ]
+# CHECK: Vreg: %15:sub1[ 2 ]
+# CHECK: Vreg: %15[ 9 ]
+# CHECK: Vreg: %86[ 4 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %10[ 17 ]
+# CHECK: Vreg: %62[ 9 ]
+# CHECK: Instr: %89:vgpr_32, %90:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %15.sub0, 16, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 2 ]
+# CHECK: Vreg: %26[ 20 ]
+# CHECK: Vreg: %14[ 19 ]
+# CHECK: Vreg: %85[ 4 ]
+# CHECK: Vreg: %9[ 17 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %25[ 17 ]
+# CHECK: Vreg: %15:sub0[ 0 ]
+# CHECK: Vreg: %15:sub1[ 1 ]
+# CHECK: Vreg: %15[ 8 ]
+# CHECK: Vreg: %86[ 3 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %10[ 16 ]
+# CHECK: Vreg: %62[ 8 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Instr: %91:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 0, %15.sub1, killed %90, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %26[ 19 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %14[ 18 ]
+# CHECK: Vreg: %85[ 3 ]
+# CHECK: Vreg: %9[ 16 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %63[ 2 ]
+# CHECK: Vreg: %25[ 16 ]
+# CHECK: Vreg: %89[ 2 ]
+# CHECK: Vreg: %15:sub1[ 0 ]
+# CHECK: Vreg: %15:sub0[ 4 ]
+# CHECK: Vreg: %15[ 7 ]
+# CHECK: Vreg: %86[ 2 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Vreg: %10[ 15 ]
+# CHECK: Vreg: %62[ 7 ]
+# CHECK: Vreg: %88[ 2 ]
+# CHECK: Instr: %92:sreg_32 = SI_IF killed %64, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %26[ 18 ]
+# CHECK: Vreg: %14[ 17 ]
+# CHECK: Vreg: %85[ 2 ]
+# CHECK: Vreg: %9[ 15 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %25[ 15 ]
+# CHECK: Vreg: %89[ 1 ]
+# CHECK: Vreg: %91[ 1 ]
+# CHECK: Vreg: %15:sub0[ 3 ]
+# CHECK: Vreg: %15:sub1[ 4 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %86[ 1 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %62[ 6 ]
+# CHECK: Vreg: %88[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %14[ 16 ]
+# CHECK: Vreg: %85[ 1 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %9[ 14 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %15:sub0[ 2 ]
+# CHECK: Vreg: %15:sub1[ 3 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %10[ 13 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %14[ 16 ]
+# CHECK: Vreg: %85[ 1 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %9[ 14 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %15:sub0[ 2 ]
+# CHECK: Vreg: %15:sub1[ 3 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %10[ 13 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: %93:vreg_64 = PHI undef %94:vreg_64, %bb.7, %95, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: %96:vreg_64 = PHI undef %94:vreg_64, %bb.7, %97, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: %98:vgpr_32 = PHI undef %99:vgpr_32, %bb.7, %100, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: %101:vgpr_32 = PHI undef %99:vgpr_32, %bb.7, %102, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %98[ 3 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: %103:vgpr_32 = PHI %86, %bb.7, undef %104:vgpr_32, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %101[ 3 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %98[ 3 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Instr: %105:vgpr_32 = PHI %88, %bb.7, undef %106:vgpr_32, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %101[ 3 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %103[ 4 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %98[ 3 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Instr: %107:vgpr_32 = PHI %89, %bb.7, undef %108:vgpr_32, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %101[ 3 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %103[ 4 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %98[ 3 ]
+# CHECK: Vreg: %105[ 4 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Instr: %109:vgpr_32 = PHI %91, %bb.7, undef %110:vgpr_32, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %101[ 3 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %103[ 4 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %98[ 3 ]
+# CHECK: Vreg: %105[ 4 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %107[ 5 ]
+# CHECK: Instr: %111:vgpr_32 = PHI %63, %bb.7, undef %112:vgpr_32, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %109[ 5 ]
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %101[ 3 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %103[ 4 ]
+# CHECK: Vreg: %98[ 3 ]
+# CHECK: Vreg: %105[ 4 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %107[ 5 ]
+# CHECK: Instr: %113:vreg_64 = REG_SEQUENCE killed %4, %subreg.sub0, killed %3, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %109[ 4 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %85[ 5 ]
+# CHECK: Vreg: %111[ 5 ]
+# CHECK: Vreg: %92[ 1 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %101[ 2 ]
+# CHECK: Vreg: %25[ 13 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %103[ 3 ]
+# CHECK: Vreg: %98[ 2 ]
+# CHECK: Vreg: %105[ 3 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %93[ 2 ]
+# CHECK: Vreg: %62[ 4 ]
+# CHECK: Vreg: %107[ 4 ]
+# CHECK: Instr: %114:sreg_32 = SI_ELSE killed %92, %bb.11, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %109[ 3 ]
+# CHECK: Vreg: %26[ 15 ]
+# CHECK: Vreg: %85[ 4 ]
+# CHECK: Vreg: %111[ 4 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %113[ 7 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %25[ 12 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %103[ 2 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %105[ 2 ]
+# CHECK: Vreg: %93[ 1 ]
+# CHECK: Vreg: %62[ 3 ]
+# CHECK: Vreg: %107[ 3 ]
+# CHECK: Instr: S_BRANCH %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %109[ 2 ]
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %85[ 3 ]
+# CHECK: Vreg: %111[ 3 ]
+# CHECK: Vreg: %113[ 6 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %103[ 1 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %105[ 1 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %107[ 2 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %109[ 2 ]
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %85[ 3 ]
+# CHECK: Vreg: %111[ 3 ]
+# CHECK: Vreg: %113[ 6 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %103[ 1 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %105[ 1 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %107[ 2 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: --- MBB_9 ---
+# CHECK: Instr: %115:vreg_64 = REG_SEQUENCE killed %103, %subreg.sub0, killed %105, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %26[ 26 ]
+# CHECK: Vreg: %85[ 2 ]
+# CHECK: Vreg: %111[ 2 ]
+# CHECK: Vreg: %113[ 18 ]
+# CHECK: Vreg: %25[ 23 ]
+# CHECK: Vreg: %103[ 0 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %62[ 14 ]
+# CHECK: Vreg: %107[ 1 ]
+# CHECK: Vreg: %114[ 13 ]
+# CHECK: Instr: %116:vreg_64 = REG_SEQUENCE killed %107, %subreg.sub0, killed %109, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %85[ 1 ]
+# CHECK: Vreg: %111[ 1 ]
+# CHECK: Vreg: %113[ 17 ]
+# CHECK: Vreg: %25[ 22 ]
+# CHECK: Vreg: %115[ 2 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %114[ 12 ]
+# CHECK: Instr: %117:vgpr_32 = V_ADD_U32_e64 killed %111, %85, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %116[ 9 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %113[ 16 ]
+# CHECK: Vreg: %25[ 21 ]
+# CHECK: Vreg: %115[ 1 ]
+# CHECK: Vreg: %62[ 12 ]
+# CHECK: Vreg: %114[ 11 ]
+# CHECK: Instr: %118:vgpr_32 = GLOBAL_LOAD_UBYTE %115, 0, 0, implicit $exec :: (load (s8) from %ir.gep3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 23 ]
+# CHECK: Vreg: %116[ 8 ]
+# CHECK: Vreg: %85[ 14 ]
+# CHECK: Vreg: %113[ 15 ]
+# CHECK: Vreg: %25[ 20 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %117[ 7 ]
+# CHECK: Vreg: %62[ 11 ]
+# CHECK: Vreg: %114[ 10 ]
+# CHECK: Instr: %119:vgpr_32 = GLOBAL_LOAD_UBYTE %115, 1, 0, implicit $exec :: (load (s8) from %ir.gep3 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 22 ]
+# CHECK: Vreg: %116[ 7 ]
+# CHECK: Vreg: %85[ 13 ]
+# CHECK: Vreg: %118[ 1 ]
+# CHECK: Vreg: %113[ 14 ]
+# CHECK: Vreg: %25[ 19 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %117[ 6 ]
+# CHECK: Vreg: %62[ 10 ]
+# CHECK: Vreg: %114[ 9 ]
+# CHECK: Instr: %120:vgpr_32 = V_LSHL_OR_B32_e64 killed %119, 8, killed %118, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 21 ]
+# CHECK: Vreg: %116[ 6 ]
+# CHECK: Vreg: %85[ 12 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %113[ 13 ]
+# CHECK: Vreg: %25[ 18 ]
+# CHECK: Vreg: %115[ 1 ]
+# CHECK: Vreg: %117[ 5 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %62[ 9 ]
+# CHECK: Vreg: %114[ 8 ]
+# CHECK: Instr: %121:vgpr_32 = GLOBAL_LOAD_UBYTE %115, 2, 0, implicit $exec :: (load (s8) from %ir.gep3 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 20 ]
+# CHECK: Vreg: %116[ 5 ]
+# CHECK: Vreg: %85[ 11 ]
+# CHECK: Vreg: %113[ 12 ]
+# CHECK: Vreg: %120[ 3 ]
+# CHECK: Vreg: %25[ 17 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %117[ 4 ]
+# CHECK: Vreg: %62[ 8 ]
+# CHECK: Vreg: %114[ 7 ]
+# CHECK: Instr: %122:vgpr_32 = GLOBAL_LOAD_UBYTE %115, 3, 0, implicit $exec :: (load (s8) from %ir.gep3 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 19 ]
+# CHECK: Vreg: %116[ 4 ]
+# CHECK: Vreg: %85[ 10 ]
+# CHECK: Vreg: %113[ 11 ]
+# CHECK: Vreg: %120[ 2 ]
+# CHECK: Vreg: %25[ 16 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %117[ 3 ]
+# CHECK: Vreg: %62[ 7 ]
+# CHECK: Vreg: %114[ 6 ]
+# CHECK: Vreg: %121[ 1 ]
+# CHECK: Instr: %123:vgpr_32 = V_LSHL_OR_B32_e64 killed %122, 8, killed %121, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 18 ]
+# CHECK: Vreg: %116[ 3 ]
+# CHECK: Vreg: %85[ 9 ]
+# CHECK: Vreg: %113[ 10 ]
+# CHECK: Vreg: %120[ 1 ]
+# CHECK: Vreg: %25[ 15 ]
+# CHECK: Vreg: %115[ 4 ]
+# CHECK: Vreg: %122[ 0 ]
+# CHECK: Vreg: %117[ 2 ]
+# CHECK: Vreg: %62[ 6 ]
+# CHECK: Vreg: %114[ 5 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Instr: %124:vgpr_32 = V_LSHL_OR_B32_e64 killed %123, 16, killed %120, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %116[ 2 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %85[ 8 ]
+# CHECK: Vreg: %113[ 9 ]
+# CHECK: Vreg: %120[ 0 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %115[ 3 ]
+# CHECK: Vreg: %117[ 1 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %114[ 4 ]
+# CHECK: Instr: %125:vgpr_32 = V_SUB_U32_e64 killed %124, %117, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %85[ 7 ]
+# CHECK: Vreg: %113[ 8 ]
+# CHECK: Vreg: %25[ 13 ]
+# CHECK: Vreg: %115[ 2 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %62[ 4 ]
+# CHECK: Vreg: %114[ 3 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %116, %125, 0, 0, implicit $exec :: (store (s32) into %ir.gep4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 15 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %113[ 7 ]
+# CHECK: Vreg: %25[ 12 ]
+# CHECK: Vreg: %115[ 1 ]
+# CHECK: Vreg: %117[ 1 ]
+# CHECK: Vreg: %62[ 3 ]
+# CHECK: Vreg: %114[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %85[ 5 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %113[ 6 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %85[ 5 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %113[ 6 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: --- MBB_10 ---
+# CHECK: Instr: %102:vgpr_32 = V_MUL_LO_U32_e64 killed %63, %85, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 33 ]
+# CHECK: Vreg: %14[ 15 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %92[ 18 ]
+# CHECK: Vreg: %9[ 13 ]
+# CHECK: Vreg: %4[ 17 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 30 ]
+# CHECK: Vreg: %15:sub0[ 1 ]
+# CHECK: Vreg: %15:sub1[ 2 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %3[ 17 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Vreg: %62[ 21 ]
+# CHECK: Instr: %126:vgpr_32, %127:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %15.sub0, 8, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 32 ]
+# CHECK: Vreg: %14[ 14 ]
+# CHECK: Vreg: %85[ 21 ]
+# CHECK: Vreg: %92[ 17 ]
+# CHECK: Vreg: %9[ 12 ]
+# CHECK: Vreg: %4[ 16 ]
+# CHECK: Vreg: %25[ 29 ]
+# CHECK: Vreg: %15:sub0[ 0 ]
+# CHECK: Vreg: %15:sub1[ 1 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %3[ 16 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %62[ 20 ]
+# CHECK: Vreg: %102[ 10 ]
+# CHECK: Instr: %128:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 0, %15.sub1, killed %127, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 31 ]
+# CHECK: Vreg: %14[ 13 ]
+# CHECK: Vreg: %85[ 20 ]
+# CHECK: Vreg: %92[ 16 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %4[ 15 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %25[ 28 ]
+# CHECK: Vreg: %15:sub1[ 0 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %3[ 15 ]
+# CHECK: Vreg: %10[ 10 ]
+# CHECK: Vreg: %62[ 19 ]
+# CHECK: Vreg: %126[ 1 ]
+# CHECK: Vreg: %102[ 9 ]
+# CHECK: Instr: %97:vreg_64 = REG_SEQUENCE killed %126, %subreg.sub0, killed %128, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 0 ]
+# CHECK: Vreg: %26[ 30 ]
+# CHECK: Vreg: %14[ 12 ]
+# CHECK: Vreg: %85[ 19 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %9[ 10 ]
+# CHECK: Vreg: %4[ 14 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %3[ 14 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %62[ 18 ]
+# CHECK: Vreg: %126[ 0 ]
+# CHECK: Vreg: %102[ 8 ]
+# CHECK: Instr: %129:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 8, 0, implicit $exec :: (load (s8) from %ir.gep5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %97[ 12 ]
+# CHECK: Vreg: %14[ 11 ]
+# CHECK: Vreg: %85[ 18 ]
+# CHECK: Vreg: %92[ 14 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %4[ 13 ]
+# CHECK: Vreg: %25[ 26 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 13 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %62[ 17 ]
+# CHECK: Vreg: %102[ 7 ]
+# CHECK: Instr: %130:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 9, 0, implicit $exec :: (load (s8) from %ir.gep5 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 28 ]
+# CHECK: Vreg: %97[ 11 ]
+# CHECK: Vreg: %14[ 10 ]
+# CHECK: Vreg: %85[ 17 ]
+# CHECK: Vreg: %92[ 13 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %4[ 12 ]
+# CHECK: Vreg: %25[ 25 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %62[ 16 ]
+# CHECK: Vreg: %102[ 6 ]
+# CHECK: Instr: %131:vgpr_32 = V_LSHL_OR_B32_e64 killed %130, 8, killed %129, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 27 ]
+# CHECK: Vreg: %97[ 10 ]
+# CHECK: Vreg: %14[ 9 ]
+# CHECK: Vreg: %85[ 16 ]
+# CHECK: Vreg: %130[ 0 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %25[ 24 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %3[ 11 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %62[ 15 ]
+# CHECK: Vreg: %102[ 5 ]
+# CHECK: Instr: %132:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 10, 0, implicit $exec :: (load (s8) from %ir.gep5 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 26 ]
+# CHECK: Vreg: %97[ 9 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %85[ 15 ]
+# CHECK: Vreg: %92[ 11 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %4[ 10 ]
+# CHECK: Vreg: %25[ 23 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 10 ]
+# CHECK: Vreg: %131[ 3 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %62[ 14 ]
+# CHECK: Vreg: %102[ 4 ]
+# CHECK: Instr: %133:vgpr_32 = GLOBAL_LOAD_UBYTE killed %15, 11, 0, implicit $exec :: (load (s8) from %ir.gep5 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %97[ 8 ]
+# CHECK: Vreg: %14[ 7 ]
+# CHECK: Vreg: %85[ 14 ]
+# CHECK: Vreg: %92[ 10 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %4[ 9 ]
+# CHECK: Vreg: %132[ 1 ]
+# CHECK: Vreg: %25[ 22 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %131[ 2 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %102[ 3 ]
+# CHECK: Instr: %134:vgpr_32 = V_LSHL_OR_B32_e64 killed %133, 8, killed %132, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %97[ 7 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %85[ 13 ]
+# CHECK: Vreg: %92[ 9 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %132[ 0 ]
+# CHECK: Vreg: %25[ 21 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Vreg: %131[ 1 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %62[ 12 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %102[ 2 ]
+# CHECK: Instr: %135:vgpr_32 = V_LSHL_OR_B32_e64 killed %134, 16, killed %131, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 23 ]
+# CHECK: Vreg: %97[ 6 ]
+# CHECK: Vreg: %14[ 5 ]
+# CHECK: Vreg: %85[ 12 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 7 ]
+# CHECK: Vreg: %25[ 20 ]
+# CHECK: Vreg: %134[ 0 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %62[ 11 ]
+# CHECK: Vreg: %102[ 1 ]
+# CHECK: Instr: %100:vgpr_32 = V_SUB_U32_e64 killed %135, %102, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 22 ]
+# CHECK: Vreg: %135[ 0 ]
+# CHECK: Vreg: %97[ 5 ]
+# CHECK: Vreg: %14[ 4 ]
+# CHECK: Vreg: %85[ 11 ]
+# CHECK: Vreg: %92[ 7 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %4[ 6 ]
+# CHECK: Vreg: %25[ 19 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %62[ 10 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: %136:vgpr_32, %137:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 killed %10, 8, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 21 ]
+# CHECK: Vreg: %97[ 4 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %85[ 10 ]
+# CHECK: Vreg: %92[ 6 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %4[ 5 ]
+# CHECK: Vreg: %25[ 18 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %100[ 3 ]
+# CHECK: Vreg: %62[ 9 ]
+# CHECK: Vreg: %102[ 4 ]
+# CHECK: Instr: %138:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 0, killed %9, killed %137, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 20 ]
+# CHECK: Vreg: %97[ 3 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %85[ 9 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %137[ 0 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %25[ 17 ]
+# CHECK: Vreg: %136[ 1 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %100[ 2 ]
+# CHECK: Vreg: %62[ 8 ]
+# CHECK: Vreg: %102[ 3 ]
+# CHECK: Instr: %95:vreg_64 = REG_SEQUENCE killed %136, %subreg.sub0, killed %138, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 19 ]
+# CHECK: Vreg: %97[ 2 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %85[ 8 ]
+# CHECK: Vreg: %92[ 4 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %25[ 16 ]
+# CHECK: Vreg: %136[ 0 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Vreg: %138[ 0 ]
+# CHECK: Vreg: %100[ 1 ]
+# CHECK: Vreg: %62[ 7 ]
+# CHECK: Vreg: %102[ 2 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %14, %100, 8, 0, implicit $exec :: (store (s32) into %ir.gep6, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 18 ]
+# CHECK: Vreg: %97[ 1 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %85[ 7 ]
+# CHECK: Vreg: %92[ 3 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %25[ 15 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %62[ 6 ]
+# CHECK: Vreg: %95[ 1 ]
+# CHECK: Vreg: %102[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %85[ 6 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: --- MBB_11 ---
+# CHECK: Instr: %139:vgpr_32 = PHI %101, %bb.8, %117, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %85[ 5 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %113[ 6 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Instr: %76:vgpr_32 = PHI %98, %bb.8, %125, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %85[ 5 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %113[ 6 ]
+# CHECK: Vreg: %139[ 3 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Instr: %140:vreg_64 = PHI %96, %bb.8, %115, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %85[ 5 ]
+# CHECK: Vreg: %113[ 6 ]
+# CHECK: Vreg: %139[ 3 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Vreg: %76[ 11 ]
+# CHECK: Instr: %141:vreg_64 = PHI %93, %bb.8, %116, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %85[ 5 ]
+# CHECK: Vreg: %113[ 6 ]
+# CHECK: Vreg: %139[ 3 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Vreg: %76[ 11 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Instr: SI_END_CF killed %114, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 13 ]
+# CHECK: Vreg: %85[ 4 ]
+# CHECK: Vreg: %113[ 5 ]
+# CHECK: Vreg: %139[ 2 ]
+# CHECK: Vreg: %25[ 10 ]
+# CHECK: Vreg: %141[ 11 ]
+# CHECK: Vreg: %62[ 1 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %76[ 10 ]
+# CHECK: Vreg: %140[ 3 ]
+# CHECK: Instr: %142:vgpr_32 = GLOBAL_LOAD_DWORD killed %62, 16, 0, implicit $exec :: (load (s32) from %ir.gep7, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %85[ 3 ]
+# CHECK: Vreg: %113[ 4 ]
+# CHECK: Vreg: %139[ 1 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %141[ 10 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %76[ 9 ]
+# CHECK: Vreg: %140[ 2 ]
+# CHECK: Instr: %77:vgpr_32 = V_ADD_U32_e64 %142, killed %139, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %142[ 0 ]
+# CHECK: Vreg: %85[ 2 ]
+# CHECK: Vreg: %113[ 3 ]
+# CHECK: Vreg: %139[ 0 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %141[ 9 ]
+# CHECK: Vreg: %76[ 8 ]
+# CHECK: Vreg: %140[ 1 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %140, %77, 0, 0, implicit $exec :: (store (s32) into %ir.phi4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %85[ 1 ]
+# CHECK: Vreg: %113[ 2 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %141[ 8 ]
+# CHECK: Vreg: %76[ 7 ]
+# CHECK: Vreg: %140[ 0 ]
+# CHECK: Instr: %143:vgpr_32 = V_SUB_U32_e64 killed %142, killed %85, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %142[ 0 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %113[ 1 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %77[ 5 ]
+# CHECK: Vreg: %141[ 7 ]
+# CHECK: Vreg: %76[ 6 ]
+# CHECK: Instr: %144:vgpr_32 = GLOBAL_LOAD_USHORT %113, 24, 0, implicit $exec :: (load (s16) from %ir.gep8, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %77[ 4 ]
+# CHECK: Vreg: %141[ 6 ]
+# CHECK: Vreg: %143[ 4 ]
+# CHECK: Vreg: %76[ 5 ]
+# CHECK: Instr: %145:vgpr_32 = GLOBAL_LOAD_USHORT killed %113, 26, 0, implicit $exec :: (load (s16) from %ir.gep8 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 7 ]
+# CHECK: Vreg: %144[ 1 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %77[ 3 ]
+# CHECK: Vreg: %141[ 5 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %76[ 4 ]
+# CHECK: Instr: %146:vgpr_32 = V_LSHL_OR_B32_e64 killed %145, 16, killed %144, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %77[ 2 ]
+# CHECK: Vreg: %141[ 4 ]
+# CHECK: Vreg: %143[ 2 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %76[ 3 ]
+# CHECK: Instr: %147:vreg_64 = REG_SEQUENCE killed %146, %subreg.sub0, undef %148:vgpr_32, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %77[ 1 ]
+# CHECK: Vreg: %141[ 3 ]
+# CHECK: Vreg: %143[ 1 ]
+# CHECK: Vreg: %76[ 2 ]
+# CHECK: Instr: %149:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 killed %143, %77, killed %147, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %141[ 2 ]
+# CHECK: Vreg: %143[ 0 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: %78:vgpr_32 = V_ADD3_U32_e64 killed %149.sub0, %76, killed %25, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %149:sub0[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %77[ 2 ]
+# CHECK: Vreg: %141[ 1 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %141, %78, 0, 0, implicit $exec :: (store (s32) into %ir.phi5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %77[ 1 ]
+# CHECK: Vreg: %141[ 0 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: --- MBB_12 ---
+# CHECK: Instr: SI_END_CF killed %39, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: --- MBB_13 ---
+# CHECK: Instr: %150:vgpr_32 = V_ADD3_U32_e64 killed %34, killed %31, killed %28, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %151:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %150, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %150[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %151
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test11 (ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, ptr addrspace(1) %p4, ptr addrspace(1) %p5, i32 %TC, i32 %Val, i1 %cond1) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  %add1 = add i32 %ld1, 100
+  br i1 %cond1, label %1, label %2
+  1:
+  %phi.inc1 = phi i32 [ 0, %0 ], [ %inc1, %1 ]
+  %phi.add = phi i32 [ %ld1, %0 ], [ %add2, %1 ]
+  %sext = sext i32 %phi.inc1 to i64
+  %gep1 = getelementptr inbounds i64, ptr addrspace(1) %p2, i64 %sext
+  %ld2 = load i32, ptr addrspace(1) %gep1, align 1
+  %inc1 = add i32 %phi.inc1, 1
+  %add2 = add i32 %ld2, %inc1
+  store i32 %add2, ptr addrspace(1) %p3
+  %cond2 = icmp ult i32 %inc1, %TC
+  br i1 %cond2, label %1, label %8
+  2:
+  %mul1 = mul i32 %ld1, 100
+  store i32 %mul1, ptr addrspace(1) %p3
+  %cond3 = icmp ult i32 %mul1, %Val
+  br i1 %cond3, label %3, label %4
+  3:
+  %gep2 = getelementptr inbounds i64, ptr addrspace(1) %p4, i64 3
+  %ld3 = load i32, ptr addrspace(1) %gep2, align 1
+  %mul2 = mul i32 %ld3, %Val
+  store i32 %mul2, ptr addrspace(1) %p3
+  br label %4
+  4:
+  %phi1 = phi i32 [ %ld1, %2 ], [ %mul2, %3]
+  %sub1 = sub i32 %mul1, %phi1
+  %cond4 = icmp ult i32 %sub1, %Val
+  br i1 %cond3, label %5, label %6
+  5:
+  %add3 = add i32 %mul1, %phi1
+  %gep3 = getelementptr inbounds i64, ptr addrspace(1) %p2, i64 3
+  %ld4 = load i32, ptr addrspace(1) %gep3, align 1
+  %sub2 = sub i32 %ld4, %add3
+  %gep4 = getelementptr inbounds i64, ptr addrspace(1) %p1, i64 2
+  store i32 %sub2, ptr addrspace(1) %gep4
+  br label %7
+  6:
+  %mul3 = mul i32 %mul1, %phi1
+  %gep5 = getelementptr inbounds i64, ptr addrspace(1) %p1, i64 1
+  %ld5 = load i32, ptr addrspace(1) %gep5, align 1
+  %sub3 = sub i32 %ld5, %mul3
+  %gep6 = getelementptr inbounds i64, ptr addrspace(1) %p2, i64 1
+  store i32 %sub3, ptr addrspace(1) %gep6
+  br label %7
+  7:
+  %phi2 = phi i32 [ %add3, %5 ], [ %mul3, %6 ]
+  %phi3 = phi i32 [ %sub2, %5 ], [ %sub3, %6 ]
+  %phi4 = phi ptr addrspace(1) [ %gep3, %5 ], [ %gep5, %6]
+  %phi5 = phi ptr addrspace(1) [ %gep4, %5 ], [ %gep6, %6]
+  %gep7 = getelementptr inbounds i64, ptr addrspace(1) %p4, i64 2
+  %ld6 = load i32, ptr addrspace(1) %gep7, align 4
+  %add4 = add i32 %ld6, %phi2
+  store i32 %add4, ptr addrspace(1) %phi4
+  %sub4 = sub i32 %ld6, %phi1
+  %gep8 = getelementptr inbounds i64, ptr addrspace(1) %p5, i64 3
+  %ld7 = load i32, ptr addrspace(1) %gep8, align 2
+  %mul4 = mul i32 %sub4, %add4
+  %add5 = add i32 %ld7, %mul4
+  %add6 = add i32 %add5, %phi3
+  %add7 = add i32 %add6, %add1
+  store i32 %add7, ptr addrspace(1) %phi5
+  br label %8
+  8:
+  %phi6 = phi i32 [ %add2, %1 ], [ %add7, %7 ]
+  %phi7 = phi i32 [ %add1, %1 ], [ %add4, %7 ]
+  %phi8 = phi i32 [ %phi.add, %1 ], [ %phi3, %7 ]
+  %add8 = add i32 %phi6, %phi7
+  %add9 = add i32 %add8, %phi8
+  ret i32 %add9
+  }
+...
+
+---
+name:            test11
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.4(0x40000000), %bb.6(0x40000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12
+  
+    %57:vgpr_32 = COPY killed $vgpr12
+    %56:vgpr_32 = COPY killed $vgpr11
+    %55:vgpr_32 = COPY killed $vgpr10
+    %54:vgpr_32 = COPY killed $vgpr9
+    %53:vgpr_32 = COPY killed $vgpr8
+    %52:vgpr_32 = COPY killed $vgpr7
+    %51:vgpr_32 = COPY killed $vgpr6
+    %50:vgpr_32 = COPY killed $vgpr5
+    %49:vgpr_32 = COPY killed $vgpr4
+    %48:vgpr_32 = COPY killed $vgpr3
+    %47:vgpr_32 = COPY killed $vgpr2
+    %46:vgpr_32 = COPY killed $vgpr1
+    %45:vgpr_32 = COPY killed $vgpr0
+    %156:vreg_64 = REG_SEQUENCE killed %49, %subreg.sub0, killed %50, %subreg.sub1
+    %155:vreg_64 = REG_SEQUENCE %47, %subreg.sub0, %48, %subreg.sub1
+    %154:vreg_64 = REG_SEQUENCE killed %45, %subreg.sub0, killed %46, %subreg.sub1
+    %69:vgpr_32 = V_AND_B32_e64 1, killed %57, implicit $exec
+    %70:sreg_32 = V_CMP_NE_U32_e64 1, killed %69, implicit $exec
+    %71:vgpr_32 = GLOBAL_LOAD_UBYTE %154, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %73:vgpr_32 = GLOBAL_LOAD_UBYTE %154, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %76:vgpr_32 = V_LSHL_OR_B32_e64 killed %73, 8, killed %71, implicit $exec
+    %77:vgpr_32 = GLOBAL_LOAD_UBYTE %154, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %79:vgpr_32 = GLOBAL_LOAD_UBYTE %154, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %81:vgpr_32 = V_LSHL_OR_B32_e64 killed %79, 8, killed %77, implicit $exec
+    %0:vgpr_32 = V_LSHL_OR_B32_e64 killed %81, 16, killed %76, implicit $exec
+    %1:vgpr_32 = V_ADD_U32_e64 100, %0, 0, implicit $exec
+    %2:sreg_32 = SI_IF killed %70, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.4
+  
+  bb.1:
+    successors: %bb.3(0x80000000)
+  
+    %132:sreg_32 = S_MOV_B32 0
+    S_BRANCH %bb.3
+  
+  bb.2:
+    successors: %bb.13(0x80000000)
+  
+    %3:vgpr_32 = PHI %17, %bb.6, %8, %bb.12
+    %4:vgpr_32 = PHI %18, %bb.6, %184, %bb.12
+    %5:vgpr_32 = PHI %19, %bb.6, %11, %bb.12
+    SI_END_CF killed %20, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.13
+  
+  bb.3:
+    successors: %bb.12(0x04000000), %bb.3(0x7c000000)
+  
+    %6:sreg_32 = PHI %132, %bb.1, %12, %bb.3
+    %7:sreg_32 = PHI %132, %bb.1, %9, %bb.3
+    %8:vgpr_32 = PHI %174, %bb.1, %11, %bb.3
+    %133:sreg_32_xm0 = S_ASHR_I32 %7, 31, implicit-def dead $scc
+    %135:sreg_64 = REG_SEQUENCE %7, %subreg.sub0, killed %133, %subreg.sub1
+    %137:sreg_64 = nsw S_LSHL_B64 killed %135, 3, implicit-def dead $scc
+    %159:vgpr_32, %161:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %176, %137.sub0, 0, implicit $exec
+    %160:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %137.sub1, %178, killed %161, 0, implicit $exec
+    %138:vreg_64 = REG_SEQUENCE killed %159, %subreg.sub0, killed %160, %subreg.sub1
+    %139:vgpr_32 = GLOBAL_LOAD_UBYTE %138, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+    %140:vgpr_32 = GLOBAL_LOAD_UBYTE %138, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+    %142:vgpr_32 = V_LSHL_OR_B32_e64 killed %140, 8, killed %139, implicit $exec
+    %143:vgpr_32 = GLOBAL_LOAD_UBYTE %138, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+    %144:vgpr_32 = GLOBAL_LOAD_UBYTE killed %138, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+    %145:vgpr_32 = V_LSHL_OR_B32_e64 killed %144, 8, killed %143, implicit $exec
+    %147:vgpr_32 = V_LSHL_OR_B32_e64 killed %145, 16, killed %142, implicit $exec
+    %9:sreg_32 = S_ADD_I32 killed %7, 1, implicit-def dead $scc
+    %11:vgpr_32 = V_ADD_U32_e64 %9, killed %147, 0, implicit $exec
+    GLOBAL_STORE_DWORD %180, %11, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    %149:sreg_32 = V_CMP_GE_U32_e64 %9, %182, implicit $exec
+    %12:sreg_32 = SI_IF_BREAK killed %149, killed %6, implicit-def dead $scc
+    SI_LOOP %12, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.12
+  
+  bb.4:
+    successors: %bb.5(0x40000000), %bb.7(0x40000000)
+  
+    %157:vreg_64 = REG_SEQUENCE killed %51, %subreg.sub0, killed %52, %subreg.sub1
+    %13:vgpr_32 = V_MUL_LO_U32_e64 100, %0, implicit $exec
+    GLOBAL_STORE_DWORD %156, %13, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    %85:sreg_32 = V_CMP_GE_U32_e64 %13, %56, implicit $exec
+    %86:sreg_32 = V_CMP_LT_U32_e64 %13, %56, implicit $exec
+    %15:sreg_32 = SI_IF killed %86, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.5
+  
+  bb.5:
+    successors: %bb.7(0x80000000)
+  
+    %87:vgpr_32 = GLOBAL_LOAD_UBYTE %157, 24, 0, implicit $exec :: (load (s8) from %ir.gep2, addrspace 1)
+    %88:vgpr_32 = GLOBAL_LOAD_UBYTE %157, 25, 0, implicit $exec :: (load (s8) from %ir.gep2 + 1, addrspace 1)
+    %90:vgpr_32 = V_LSHL_OR_B32_e64 killed %88, 8, killed %87, implicit $exec
+    %91:vgpr_32 = GLOBAL_LOAD_UBYTE %157, 26, 0, implicit $exec :: (load (s8) from %ir.gep2 + 2, addrspace 1)
+    %92:vgpr_32 = GLOBAL_LOAD_UBYTE %157, 27, 0, implicit $exec :: (load (s8) from %ir.gep2 + 3, addrspace 1)
+    %93:vgpr_32 = V_LSHL_OR_B32_e64 killed %92, 8, killed %91, implicit $exec
+    %95:vgpr_32 = V_LSHL_OR_B32_e64 killed %93, 16, killed %90, implicit $exec
+    %16:vgpr_32 = V_MUL_LO_U32_e64 killed %95, killed %56, implicit $exec
+    GLOBAL_STORE_DWORD killed %156, %16, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    S_BRANCH %bb.7
+  
+  bb.6:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  
+    %17:vgpr_32 = PHI undef %63:vgpr_32, %bb.0, %37, %bb.11
+    %18:vgpr_32 = PHI undef %63:vgpr_32, %bb.0, %40, %bb.11
+    %19:vgpr_32 = PHI undef %63:vgpr_32, %bb.0, %41, %bb.11
+    %174:vgpr_32 = PHI %0, %bb.0, undef %175:vgpr_32, %bb.11
+    %176:vgpr_32 = PHI %47, %bb.0, undef %177:vgpr_32, %bb.11
+    %178:vgpr_32 = PHI %48, %bb.0, undef %179:vgpr_32, %bb.11
+    %180:vreg_64 = PHI %156, %bb.0, undef %181:vreg_64, %bb.11
+    %182:vgpr_32 = PHI %55, %bb.0, undef %183:vgpr_32, %bb.11
+    %184:vgpr_32 = PHI %1, %bb.0, undef %185:vgpr_32, %bb.11
+    %20:sreg_32 = SI_ELSE killed %2, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.1
+  
+  bb.7:
+    successors: %bb.10(0x40000000), %bb.8(0x40000000)
+  
+    %21:vgpr_32 = PHI %0, %bb.4, %16, %bb.5
+    SI_END_CF killed %15, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %162:vgpr_32, %164:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %47, 24, 0, implicit $exec
+    %163:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 0, %48, killed %164, 0, implicit $exec
+    %165:vgpr_32, %167:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %154.sub0, 16, 0, implicit $exec
+    %166:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 0, %154.sub1, killed %167, 0, implicit $exec
+    %24:sreg_32 = SI_IF killed %85, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.10
+  
+  bb.8:
+    successors: %bb.9(0x40000000), %bb.11(0x40000000)
+  
+    %25:vreg_64 = PHI undef %96:vreg_64, %bb.7, %35, %bb.10
+    %26:vreg_64 = PHI undef %96:vreg_64, %bb.7, %33, %bb.10
+    %27:vgpr_32 = PHI undef %97:vgpr_32, %bb.7, %34, %bb.10
+    %28:vgpr_32 = PHI undef %97:vgpr_32, %bb.7, %32, %bb.10
+    %186:vgpr_32 = PHI %162, %bb.7, undef %187:vgpr_32, %bb.10
+    %188:vgpr_32 = PHI %163, %bb.7, undef %189:vgpr_32, %bb.10
+    %190:vgpr_32 = PHI %165, %bb.7, undef %191:vgpr_32, %bb.10
+    %192:vgpr_32 = PHI %166, %bb.7, undef %193:vgpr_32, %bb.10
+    %194:vgpr_32 = PHI %13, %bb.7, undef %195:vgpr_32, %bb.10
+    %158:vreg_64 = REG_SEQUENCE killed %53, %subreg.sub0, killed %54, %subreg.sub1
+    %29:sreg_32 = SI_ELSE killed %24, %bb.11, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.9
+  
+  bb.9:
+    successors: %bb.11(0x80000000)
+  
+    %22:vreg_64 = REG_SEQUENCE killed %186, %subreg.sub0, killed %188, %subreg.sub1
+    %23:vreg_64 = REG_SEQUENCE killed %190, %subreg.sub0, killed %192, %subreg.sub1
+    %30:vgpr_32 = V_ADD_U32_e64 killed %194, %21, 0, implicit $exec
+    %111:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 0, 0, implicit $exec :: (load (s8) from %ir.gep3, addrspace 1)
+    %112:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 1, 0, implicit $exec :: (load (s8) from %ir.gep3 + 1, addrspace 1)
+    %114:vgpr_32 = V_LSHL_OR_B32_e64 killed %112, 8, killed %111, implicit $exec
+    %115:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 2, 0, implicit $exec :: (load (s8) from %ir.gep3 + 2, addrspace 1)
+    %116:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 3, 0, implicit $exec :: (load (s8) from %ir.gep3 + 3, addrspace 1)
+    %117:vgpr_32 = V_LSHL_OR_B32_e64 killed %116, 8, killed %115, implicit $exec
+    %119:vgpr_32 = V_LSHL_OR_B32_e64 killed %117, 16, killed %114, implicit $exec
+    %31:vgpr_32 = V_SUB_U32_e64 killed %119, %30, 0, implicit $exec
+    GLOBAL_STORE_DWORD %23, %31, 0, 0, implicit $exec :: (store (s32) into %ir.gep4, addrspace 1)
+    S_BRANCH %bb.11
+  
+  bb.10:
+    successors: %bb.8(0x80000000)
+  
+    %32:vgpr_32 = V_MUL_LO_U32_e64 killed %13, %21, implicit $exec
+    %168:vgpr_32, %170:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %154.sub0, 8, 0, implicit $exec
+    %169:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 0, %154.sub1, killed %170, 0, implicit $exec
+    %33:vreg_64 = REG_SEQUENCE killed %168, %subreg.sub0, killed %169, %subreg.sub1
+    %102:vgpr_32 = GLOBAL_LOAD_UBYTE %154, 8, 0, implicit $exec :: (load (s8) from %ir.gep5, addrspace 1)
+    %103:vgpr_32 = GLOBAL_LOAD_UBYTE %154, 9, 0, implicit $exec :: (load (s8) from %ir.gep5 + 1, addrspace 1)
+    %105:vgpr_32 = V_LSHL_OR_B32_e64 killed %103, 8, killed %102, implicit $exec
+    %106:vgpr_32 = GLOBAL_LOAD_UBYTE %154, 10, 0, implicit $exec :: (load (s8) from %ir.gep5 + 2, addrspace 1)
+    %107:vgpr_32 = GLOBAL_LOAD_UBYTE killed %154, 11, 0, implicit $exec :: (load (s8) from %ir.gep5 + 3, addrspace 1)
+    %108:vgpr_32 = V_LSHL_OR_B32_e64 killed %107, 8, killed %106, implicit $exec
+    %110:vgpr_32 = V_LSHL_OR_B32_e64 killed %108, 16, killed %105, implicit $exec
+    %34:vgpr_32 = V_SUB_U32_e64 killed %110, %32, 0, implicit $exec
+    %171:vgpr_32, %173:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 killed %47, 8, 0, implicit $exec
+    %172:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 0, killed %48, killed %173, 0, implicit $exec
+    %35:vreg_64 = REG_SEQUENCE killed %171, %subreg.sub0, killed %172, %subreg.sub1
+    GLOBAL_STORE_DWORD killed %155, %34, 8, 0, implicit $exec :: (store (s32) into %ir.gep6, addrspace 1)
+    S_BRANCH %bb.8
+  
+  bb.11:
+    successors: %bb.6(0x80000000)
+  
+    %36:vgpr_32 = PHI %28, %bb.8, %30, %bb.9
+    %37:vgpr_32 = PHI %27, %bb.8, %31, %bb.9
+    %38:vreg_64 = PHI %26, %bb.8, %22, %bb.9
+    %39:vreg_64 = PHI %25, %bb.8, %23, %bb.9
+    SI_END_CF killed %29, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %120:vgpr_32 = GLOBAL_LOAD_DWORD killed %157, 16, 0, implicit $exec :: (load (s32) from %ir.gep7, addrspace 1)
+    %40:vgpr_32 = V_ADD_U32_e64 %120, killed %36, 0, implicit $exec
+    GLOBAL_STORE_DWORD killed %38, %40, 0, 0, implicit $exec :: (store (s32) into %ir.phi4, addrspace 1)
+    %121:vgpr_32 = V_SUB_U32_e64 killed %120, killed %21, 0, implicit $exec
+    %122:vgpr_32 = GLOBAL_LOAD_USHORT %158, 24, 0, implicit $exec :: (load (s16) from %ir.gep8, addrspace 1)
+    %123:vgpr_32 = GLOBAL_LOAD_USHORT killed %158, 26, 0, implicit $exec :: (load (s16) from %ir.gep8 + 2, addrspace 1)
+    %125:vgpr_32 = V_LSHL_OR_B32_e64 killed %123, 16, killed %122, implicit $exec
+    %152:vreg_64 = REG_SEQUENCE killed %125, %subreg.sub0, undef %153:vgpr_32, %subreg.sub1
+    %129:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 killed %121, %40, killed %152, 0, implicit $exec
+    %41:vgpr_32 = V_ADD3_U32_e64 killed %129.sub0, %37, killed %1, implicit $exec
+    GLOBAL_STORE_DWORD killed %39, %41, 0, 0, implicit $exec :: (store (s32) into %ir.phi5, addrspace 1)
+    S_BRANCH %bb.6
+  
+  bb.12:
+    successors: %bb.2(0x80000000)
+  
+    SI_END_CF killed %12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+  
+  bb.13:
+    %150:vgpr_32 = V_ADD3_U32_e64 killed %5, killed %4, killed %3, implicit $exec
+    %151:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %150, implicit $exec
+    $sgpr0 = COPY killed %151
+    SI_RETURN_TO_EPILOG killed $sgpr0
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
new file mode 100644
index 0000000000000..99ed7ef607d0b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
@@ -0,0 +1,1021 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#       bb.0.entry
+#           |
+#    bb.1.loop.header<--+
+#       /   |           |
+#  bb.2.bb1 |           |
+#       \   |           |
+#      bb.5.Flow        |
+#       /   |           |
+#  bb.6.bb3 |           |
+#       \   |           |
+#      bb.3.Flow1       |
+#       /   |           |
+#  bb.4.bb2 |           |
+#       \   |           |
+#    bb.7.loop.latch----+
+#           |
+#       bb.8.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test5 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Instr: %7:vreg_64 = REG_SEQUENCE killed %2, %subreg.sub0, killed %1, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Instr: %8:vreg_64 = REG_SEQUENCE killed %4, %subreg.sub0, killed %3, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %7[ 27 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Instr: %9:vreg_64 = REG_SEQUENCE killed %6, %subreg.sub0, killed %5, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %7[ 26 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %8:sub0[ 16 ]
+# CHECK: Vreg: %8:sub1[ 17 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %10:vgpr_32 = GLOBAL_LOAD_UBYTE %9, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %7[ 25 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %8:sub0[ 15 ]
+# CHECK: Vreg: %8:sub1[ 16 ]
+# CHECK: Instr: %11:vgpr_32 = GLOBAL_LOAD_UBYTE %9, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %7[ 24 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %8:sub0[ 14 ]
+# CHECK: Vreg: %8:sub1[ 15 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Instr: %12:vgpr_32 = V_LSHL_OR_B32_e64 killed %11, 8, killed %10, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %7[ 23 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %13:vgpr_32 = GLOBAL_LOAD_UBYTE %9, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %7[ 22 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %8:sub0[ 12 ]
+# CHECK: Vreg: %8:sub1[ 13 ]
+# CHECK: Vreg: %12[ 3 ]
+# CHECK: Instr: %14:vgpr_32 = GLOBAL_LOAD_UBYTE killed %9, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %7[ 21 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %8:sub0[ 11 ]
+# CHECK: Vreg: %8:sub1[ 12 ]
+# CHECK: Vreg: %12[ 2 ]
+# CHECK: Instr: %15:vgpr_32 = V_LSHL_OR_B32_e64 killed %14, 8, killed %13, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %7[ 20 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %8:sub0[ 10 ]
+# CHECK: Vreg: %8:sub1[ 11 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: %16:vgpr_32 = V_LSHL_OR_B32_e64 killed %15, 16, killed %12, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %7[ 19 ]
+# CHECK: Vreg: %8:sub0[ 9 ]
+# CHECK: Vreg: %8:sub1[ 10 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %17:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %7[ 18 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %8:sub0[ 8 ]
+# CHECK: Vreg: %8:sub1[ 9 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %7[ 18 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %8:sub0[ 8 ]
+# CHECK: Vreg: %8:sub1[ 9 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %18:sreg_32 = PHI %17, %bb.0, %19, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %7[ LoopTag+18 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %8:sub0[ 8 ]
+# CHECK: Vreg: %8:sub1[ 9 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %20:vreg_64 = PHI undef %21:vreg_64, %bb.0, %22, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %7[ LoopTag+18 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %18[ 14 ]
+# CHECK: Vreg: %8:sub0[ 8 ]
+# CHECK: Vreg: %8:sub1[ 9 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %23:sreg_32 = PHI %17, %bb.0, %24, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %7[ LoopTag+18 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %18[ 14 ]
+# CHECK: Vreg: %20[ 4 ]
+# CHECK: Vreg: %8:sub0[ 8 ]
+# CHECK: Vreg: %8:sub1[ 9 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %25:vgpr_32 = PHI %16, %bb.0, %26, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %7[ LoopTag+18 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %18[ 14 ]
+# CHECK: Vreg: %20[ 4 ]
+# CHECK: Vreg: %8:sub0[ 8 ]
+# CHECK: Vreg: %8:sub1[ 9 ]
+# CHECK: Vreg: %17[ 4 ]
+# CHECK: Instr: %27:sreg_32 = V_CMP_GE_I32_e64 %23, %16, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %7[ LoopTag+17 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %18[ 13 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %20[ 3 ]
+# CHECK: Vreg: %8:sub0[ 7 ]
+# CHECK: Vreg: %8:sub1[ 8 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Instr: %28:sreg_32 = V_CMP_LT_I32_e64 %23, %16, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %7[ LoopTag+16 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %8:sub0[ 6 ]
+# CHECK: Vreg: %8:sub1[ 7 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Instr: %29:sreg_32 = SI_IF killed %28, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %7[ LoopTag+15 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %16[ 9 ]
+# CHECK: Vreg: %23[ 2 ]
+# CHECK: Vreg: %18[ 11 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %8:sub0[ 5 ]
+# CHECK: Vreg: %8:sub1[ 6 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %7[ LoopTag+14 ]
+# CHECK: Vreg: %16[ 8 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %8:sub0[ 4 ]
+# CHECK: Vreg: %8:sub1[ 5 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %7[ LoopTag+14 ]
+# CHECK: Vreg: %16[ 8 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %8:sub0[ 4 ]
+# CHECK: Vreg: %8:sub1[ 5 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %30:sreg_32_xm0 = S_ASHR_I32 %23, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %7[ LoopTag+26 ]
+# CHECK: Vreg: %16[ 7 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %18[ 22 ]
+# CHECK: Vreg: %25[ 16 ]
+# CHECK: Vreg: %27[ 9 ]
+# CHECK: Vreg: %8:sub0[ 3 ]
+# CHECK: Vreg: %8:sub1[ 4 ]
+# CHECK: Vreg: %29[ 13 ]
+# CHECK: Instr: %31:sreg_64 = REG_SEQUENCE %23, %subreg.sub0, killed %30, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %7[ LoopTag+25 ]
+# CHECK: Vreg: %16[ 6 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18[ 21 ]
+# CHECK: Vreg: %25[ 15 ]
+# CHECK: Vreg: %27[ 8 ]
+# CHECK: Vreg: %8:sub0[ 2 ]
+# CHECK: Vreg: %8:sub1[ 3 ]
+# CHECK: Vreg: %29[ 12 ]
+# CHECK: Instr: %32:sreg_64 = nsw S_LSHL_B64 killed %31, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %7[ LoopTag+24 ]
+# CHECK: Vreg: %16[ 5 ]
+# CHECK: Vreg: %23[ 18 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %8:sub0[ 1 ]
+# CHECK: Vreg: %8:sub1[ 2 ]
+# CHECK: Vreg: %29[ 11 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %33:vgpr_32, %34:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %8.sub0, %32.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %7[ LoopTag+23 ]
+# CHECK: Vreg: %16[ 4 ]
+# CHECK: Vreg: %23[ 17 ]
+# CHECK: Vreg: %18[ 19 ]
+# CHECK: Vreg: %25[ 13 ]
+# CHECK: Vreg: %32:sub0[ 0 ]
+# CHECK: Vreg: %32:sub1[ 1 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %8:sub0[ 0 ]
+# CHECK: Vreg: %8:sub1[ 1 ]
+# CHECK: Vreg: %29[ 10 ]
+# CHECK: Instr: %35:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %32.sub1, %8.sub1, killed %34, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %7[ LoopTag+22 ]
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %16[ 3 ]
+# CHECK: Vreg: %23[ 16 ]
+# CHECK: Vreg: %18[ 18 ]
+# CHECK: Vreg: %25[ 12 ]
+# CHECK: Vreg: %32:sub1[ 0 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %8:sub1[ 0 ]
+# CHECK: Vreg: %8:sub0[ 28 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Instr: %36:vreg_64 = REG_SEQUENCE killed %33, %subreg.sub0, killed %35, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %7[ LoopTag+21 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %16[ 2 ]
+# CHECK: Vreg: %23[ 15 ]
+# CHECK: Vreg: %18[ 17 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %27[ 4 ]
+# CHECK: Vreg: %8:sub0[ 27 ]
+# CHECK: Vreg: %8:sub1[ 28 ]
+# CHECK: Vreg: %29[ 8 ]
+# CHECK: Instr: %37:vgpr_32 = GLOBAL_LOAD_DWORD %36, 0, 0, implicit $exec :: (load (s32) from %ir.gep, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %7[ LoopTag+20 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %18[ 16 ]
+# CHECK: Vreg: %25[ 10 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %8:sub0[ 26 ]
+# CHECK: Vreg: %8:sub1[ 27 ]
+# CHECK: Vreg: %29[ 7 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Instr: %38:sreg_32 = V_CMP_LE_I32_e64 killed %37, %16, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %7[ LoopTag+19 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %23[ 13 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %18[ 15 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %8:sub0[ 25 ]
+# CHECK: Vreg: %8:sub1[ 26 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Instr: %39:sreg_32 = COPY $exec_lo
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %7[ LoopTag+18 ]
+# CHECK: Vreg: %23[ 12 ]
+# CHECK: Vreg: %18[ 14 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %8:sub0[ 24 ]
+# CHECK: Vreg: %8:sub1[ 25 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Instr: %40:sreg_32 = S_ANDN2_B32 killed %27, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %7[ LoopTag+17 ]
+# CHECK: Vreg: %23[ 11 ]
+# CHECK: Vreg: %18[ 13 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %39[ 3 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %8:sub0[ 23 ]
+# CHECK: Vreg: %8:sub1[ 24 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Instr: %41:sreg_32 = S_AND_B32 killed %38, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %7[ LoopTag+16 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %23[ 10 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %39[ 2 ]
+# CHECK: Vreg: %8:sub0[ 22 ]
+# CHECK: Vreg: %8:sub1[ 23 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Instr: %42:sreg_32 = S_OR_B32 killed %40, killed %41, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %7[ LoopTag+15 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %23[ 9 ]
+# CHECK: Vreg: %18[ 11 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %8:sub0[ 21 ]
+# CHECK: Vreg: %8:sub1[ 22 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %7[ LoopTag+14 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 8 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %8:sub0[ 20 ]
+# CHECK: Vreg: %8:sub1[ 21 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %7[ LoopTag+14 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 8 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %8:sub0[ 20 ]
+# CHECK: Vreg: %8:sub1[ 21 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %43:sreg_32 = PHI %44, %bb.5, %45, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %7[ LoopTag+11 ]
+# CHECK: Vreg: %23[ 5 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %8:sub0[ 17 ]
+# CHECK: Vreg: %8:sub1[ 18 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Instr: %46:vgpr_32 = PHI undef %47:vgpr_32, %bb.5, %48, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %7[ LoopTag+11 ]
+# CHECK: Vreg: %23[ 5 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %8:sub0[ 17 ]
+# CHECK: Vreg: %8:sub1[ 18 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Instr: SI_END_CF killed %49, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %7[ LoopTag+10 ]
+# CHECK: Vreg: %23[ 4 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %46[ 2 ]
+# CHECK: Vreg: %8:sub0[ 16 ]
+# CHECK: Vreg: %8:sub1[ 17 ]
+# CHECK: Vreg: %22[ 3 ]
+# CHECK: Vreg: %43[ 1 ]
+# CHECK: Instr: %50:sreg_32 = SI_IF killed %43, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %7[ LoopTag+9 ]
+# CHECK: Vreg: %23[ 3 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %8:sub0[ 15 ]
+# CHECK: Vreg: %8:sub1[ 16 ]
+# CHECK: Vreg: %22[ 2 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %7[ LoopTag+8 ]
+# CHECK: Vreg: %23[ 2 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %8:sub0[ 14 ]
+# CHECK: Vreg: %8:sub1[ 15 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %7[ LoopTag+8 ]
+# CHECK: Vreg: %23[ 2 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %8:sub0[ 14 ]
+# CHECK: Vreg: %8:sub1[ 15 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: GLOBAL_STORE_DWORD %22, killed %25, 0, 0, implicit $exec :: (store (s32) into %ir.gep, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %7[ LoopTag+10 ]
+# CHECK: Vreg: %23[ 4 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %8:sub0[ 16 ]
+# CHECK: Vreg: %8:sub1[ 17 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %50[ 3 ]
+# CHECK: Instr: %51:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %7[ LoopTag+9 ]
+# CHECK: Vreg: %23[ 3 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %8:sub0[ 15 ]
+# CHECK: Vreg: %8:sub1[ 16 ]
+# CHECK: Vreg: %22[ 7 ]
+# CHECK: Vreg: %50[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %7[ LoopTag+8 ]
+# CHECK: Vreg: %23[ 2 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %8:sub0[ 14 ]
+# CHECK: Vreg: %8:sub1[ 15 ]
+# CHECK: Vreg: %22[ 6 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %7[ LoopTag+8 ]
+# CHECK: Vreg: %23[ 2 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %8:sub0[ 14 ]
+# CHECK: Vreg: %8:sub1[ 15 ]
+# CHECK: Vreg: %22[ 6 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %52:sreg_32 = PHI %27, %bb.1, %42, %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %7[ LoopTag+14 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 8 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %8:sub0[ 20 ]
+# CHECK: Vreg: %8:sub1[ 21 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: %44:sreg_32 = PHI %17, %bb.1, %39, %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %7[ LoopTag+14 ]
+# CHECK: Vreg: %52[ 2 ]
+# CHECK: Vreg: %23[ 8 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %8:sub0[ 20 ]
+# CHECK: Vreg: %8:sub1[ 21 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: %22:vreg_64 = PHI %20, %bb.1, %36, %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %7[ LoopTag+14 ]
+# CHECK: Vreg: %52[ 2 ]
+# CHECK: Vreg: %23[ 8 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %44[ 3 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %8:sub0[ 20 ]
+# CHECK: Vreg: %8:sub1[ 21 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Instr: SI_END_CF killed %29, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %7[ LoopTag+13 ]
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %23[ 7 ]
+# CHECK: Vreg: %18[ 9 ]
+# CHECK: Vreg: %44[ 2 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %8:sub0[ 19 ]
+# CHECK: Vreg: %8:sub1[ 20 ]
+# CHECK: Vreg: %22[ 6 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Instr: %49:sreg_32 = SI_IF killed %52, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %7[ LoopTag+12 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %23[ 6 ]
+# CHECK: Vreg: %18[ 8 ]
+# CHECK: Vreg: %44[ 1 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %8:sub0[ 18 ]
+# CHECK: Vreg: %8:sub1[ 19 ]
+# CHECK: Vreg: %22[ 5 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %7[ LoopTag+11 ]
+# CHECK: Vreg: %23[ 5 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %8:sub0[ 17 ]
+# CHECK: Vreg: %8:sub1[ 18 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %7[ LoopTag+11 ]
+# CHECK: Vreg: %23[ 5 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %8:sub0[ 17 ]
+# CHECK: Vreg: %8:sub1[ 18 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %53:vgpr_32 = V_LSHRREV_B32_e64 31, %25, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %7[ LoopTag+16 ]
+# CHECK: Vreg: %23[ 10 ]
+# CHECK: Vreg: %49[ 6 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %44[ 3 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %8:sub0[ 22 ]
+# CHECK: Vreg: %8:sub1[ 23 ]
+# CHECK: Vreg: %22[ 9 ]
+# CHECK: Instr: %54:vgpr_32 = V_ADD_U32_e64 %25, killed %53, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %7[ LoopTag+15 ]
+# CHECK: Vreg: %23[ 9 ]
+# CHECK: Vreg: %49[ 5 ]
+# CHECK: Vreg: %18[ 11 ]
+# CHECK: Vreg: %44[ 2 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %8:sub0[ 21 ]
+# CHECK: Vreg: %8:sub1[ 22 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %22[ 8 ]
+# CHECK: Instr: %48:vgpr_32 = V_ASHRREV_I32_e64 1, killed %54, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %7[ LoopTag+14 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %23[ 8 ]
+# CHECK: Vreg: %49[ 4 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %44[ 1 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %8:sub0[ 20 ]
+# CHECK: Vreg: %8:sub1[ 21 ]
+# CHECK: Vreg: %22[ 7 ]
+# CHECK: Instr: %55:sreg_32 = S_ANDN2_B32 killed %44, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %7[ LoopTag+13 ]
+# CHECK: Vreg: %23[ 7 ]
+# CHECK: Vreg: %49[ 3 ]
+# CHECK: Vreg: %18[ 9 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %8:sub0[ 19 ]
+# CHECK: Vreg: %8:sub1[ 20 ]
+# CHECK: Vreg: %22[ 6 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Instr: %45:sreg_32 = COPY killed %55
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %7[ LoopTag+12 ]
+# CHECK: Vreg: %23[ 6 ]
+# CHECK: Vreg: %49[ 2 ]
+# CHECK: Vreg: %18[ 8 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %8:sub0[ 18 ]
+# CHECK: Vreg: %8:sub1[ 19 ]
+# CHECK: Vreg: %22[ 5 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %7[ LoopTag+11 ]
+# CHECK: Vreg: %23[ 5 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %8:sub0[ 17 ]
+# CHECK: Vreg: %8:sub1[ 18 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %7[ LoopTag+11 ]
+# CHECK: Vreg: %23[ 5 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %8:sub0[ 17 ]
+# CHECK: Vreg: %8:sub1[ 18 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: %26:vgpr_32 = PHI %46, %bb.3, %51, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %7[ LoopTag+8 ]
+# CHECK: Vreg: %23[ 2 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %8:sub0[ 14 ]
+# CHECK: Vreg: %8:sub1[ 15 ]
+# CHECK: Vreg: %22[ 6 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Instr: SI_END_CF killed %50, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %7[ LoopTag+7 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %22[ 5 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Instr: %24:sreg_32 = S_ADD_I32 killed %23, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %7[ LoopTag+6 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %8:sub0[ 12 ]
+# CHECK: Vreg: %8:sub1[ 13 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: Instr: %56:sreg_32 = V_CMP_GE_U32_e64 %24, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %7[ LoopTag+5 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %8:sub0[ 11 ]
+# CHECK: Vreg: %8:sub1[ 12 ]
+# CHECK: Vreg: %22[ 3 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %19:sreg_32 = SI_IF_BREAK killed %56, killed %18, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %7[ LoopTag+4 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %8:sub0[ 10 ]
+# CHECK: Vreg: %8:sub1[ 11 ]
+# CHECK: Vreg: %22[ 2 ]
+# CHECK: Vreg: %24[ 2 ]
+# CHECK: Instr: SI_LOOP %19, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %7[ LoopTag+3 ]
+# CHECK: Vreg: %8:sub0[ 9 ]
+# CHECK: Vreg: %8:sub1[ 10 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %24[ 1 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %7[ LoopTag+2 ]
+# CHECK: Vreg: %8:sub0[ 8 ]
+# CHECK: Vreg: %8:sub1[ 9 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %7[ LoopTag+2 ]
+# CHECK: Vreg: %8:sub0[ 8 ]
+# CHECK: Vreg: %8:sub1[ 9 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: SI_END_CF killed %19, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %7, killed %26, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Instr: S_ENDPGM 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps void @test5(ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, i32 %TC) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  br label %1
+  1:
+  %phi.inc = phi i32 [ 0, %0 ], [ %inc, %5 ]
+  %phi1 = phi i32 [ %ld1, %0 ], [ %phi2, %5 ]
+  %cond1 = icmp slt i32 %phi.inc, %ld1
+  br i1 %cond1, label %2, label %4
+  2:
+  %sext = sext i32 %phi.inc to i64
+  %gep = getelementptr inbounds i32, ptr addrspace(1) %p2, i64 %sext
+  %ld2 = load i32, ptr addrspace(1) %gep, align 4
+  %cond2 = icmp sgt i32 %ld2, %ld1
+  br i1 %cond2, label %3, label %4
+  3:
+  store i32 %phi1, ptr addrspace(1) %gep, align 4
+  br label %5
+  4:
+  %div = sdiv i32 %phi1, 2
+  br label %5
+  5:
+  %phi2 = phi i32 [ 1, %3 ], [ %div, %4 ]
+  %inc = add i32 %phi.inc, 1
+  %cond3 = icmp ult i32 %inc, %TC
+  br i1 %cond3, label %1, label %6
+  6:
+  store i32 %phi2, ptr addrspace(1) %p3, align 4
+  ret void
+  }
+...
+
+---
+name:            test5
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6
+  
+    %28:vgpr_32 = COPY killed $vgpr6
+    %27:vgpr_32 = COPY killed $vgpr5
+    %26:vgpr_32 = COPY killed $vgpr4
+    %25:vgpr_32 = COPY killed $vgpr3
+    %24:vgpr_32 = COPY killed $vgpr2
+    %23:vgpr_32 = COPY killed $vgpr1
+    %22:vgpr_32 = COPY killed $vgpr0
+    %67:vreg_64 = REG_SEQUENCE killed %26, %subreg.sub0, killed %27, %subreg.sub1
+    %66:vreg_64 = REG_SEQUENCE killed %24, %subreg.sub0, killed %25, %subreg.sub1
+    %65:vreg_64 = REG_SEQUENCE killed %22, %subreg.sub0, killed %23, %subreg.sub1
+    %36:vgpr_32 = GLOBAL_LOAD_UBYTE %65, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %38:vgpr_32 = GLOBAL_LOAD_UBYTE %65, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %41:vgpr_32 = V_LSHL_OR_B32_e64 killed %38, 8, killed %36, implicit $exec
+    %42:vgpr_32 = GLOBAL_LOAD_UBYTE %65, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %44:vgpr_32 = GLOBAL_LOAD_UBYTE killed %65, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %46:vgpr_32 = V_LSHL_OR_B32_e64 killed %44, 8, killed %42, implicit $exec
+    %0:vgpr_32 = V_LSHL_OR_B32_e64 killed %46, 16, killed %41, implicit $exec
+    %31:sreg_32 = S_MOV_B32 0
+  
+  bb.1:
+    successors: %bb.2(0x40000000), %bb.5(0x40000000)
+  
+    %1:sreg_32 = PHI %31, %bb.0, %19, %bb.7
+    %2:vreg_64 = PHI undef %32:vreg_64, %bb.0, %12, %bb.7
+    %3:sreg_32 = PHI %31, %bb.0, %18, %bb.7
+    %4:vgpr_32 = PHI %0, %bb.0, %17, %bb.7
+    %49:sreg_32 = V_CMP_GE_I32_e64 %3, %0, implicit $exec
+    %50:sreg_32 = V_CMP_LT_I32_e64 %3, %0, implicit $exec
+    %6:sreg_32 = SI_IF killed %50, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+  
+  bb.2:
+    successors: %bb.5(0x80000000)
+  
+    %53:sreg_32_xm0 = S_ASHR_I32 %3, 31, implicit-def dead $scc
+    %55:sreg_64 = REG_SEQUENCE %3, %subreg.sub0, killed %53, %subreg.sub1
+    %57:sreg_64 = nsw S_LSHL_B64 killed %55, 2, implicit-def dead $scc
+    %74:vgpr_32, %76:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %66.sub0, %57.sub0, 0, implicit $exec
+    %75:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %57.sub1, %66.sub1, killed %76, 0, implicit $exec
+    %7:vreg_64 = REG_SEQUENCE killed %74, %subreg.sub0, killed %75, %subreg.sub1
+    %58:vgpr_32 = GLOBAL_LOAD_DWORD %7, 0, 0, implicit $exec :: (load (s32) from %ir.gep, addrspace 1)
+    %59:sreg_32 = V_CMP_LE_I32_e64 killed %58, %0, implicit $exec
+    %70:sreg_32 = COPY $exec_lo
+    %72:sreg_32 = S_ANDN2_B32 killed %49, $exec_lo, implicit-def dead $scc
+    %73:sreg_32 = S_AND_B32 killed %59, $exec_lo, implicit-def dead $scc
+    %71:sreg_32 = S_OR_B32 killed %72, killed %73, implicit-def dead $scc
+    S_BRANCH %bb.5
+  
+  bb.3:
+    successors: %bb.4(0x40000000), %bb.7(0x40000000)
+  
+    %10:sreg_32 = PHI %13, %bb.5, %68, %bb.6
+    %9:vgpr_32 = PHI undef %60:vgpr_32, %bb.5, %16, %bb.6
+    SI_END_CF killed %15, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %11:sreg_32 = SI_IF killed %10, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.4
+  
+  bb.4:
+    successors: %bb.7(0x80000000)
+  
+    GLOBAL_STORE_DWORD %12, killed %4, 0, 0, implicit $exec :: (store (s32) into %ir.gep, addrspace 1)
+    %63:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    S_BRANCH %bb.7
+  
+  bb.5:
+    successors: %bb.6(0x40000000), %bb.3(0x40000000)
+  
+    %14:sreg_32 = PHI %49, %bb.1, %71, %bb.2
+    %13:sreg_32 = PHI %31, %bb.1, %70, %bb.2
+    %12:vreg_64 = PHI %2, %bb.1, %7, %bb.2
+    SI_END_CF killed %6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %15:sreg_32 = SI_IF killed %14, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.6
+  
+  bb.6:
+    successors: %bb.3(0x80000000)
+  
+    %61:vgpr_32 = V_LSHRREV_B32_e64 31, %4, implicit $exec
+    %62:vgpr_32 = V_ADD_U32_e64 %4, killed %61, 0, implicit $exec
+    %16:vgpr_32 = V_ASHRREV_I32_e64 1, killed %62, implicit $exec
+    %69:sreg_32 = S_ANDN2_B32 killed %13, $exec_lo, implicit-def dead $scc
+    %68:sreg_32 = COPY killed %69
+    S_BRANCH %bb.3
+  
+  bb.7:
+    successors: %bb.8(0x04000000), %bb.1(0x7c000000)
+  
+    %17:vgpr_32 = PHI %9, %bb.3, %63, %bb.4
+    SI_END_CF killed %11, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %18:sreg_32 = S_ADD_I32 killed %3, 1, implicit-def dead $scc
+    %64:sreg_32 = V_CMP_GE_U32_e64 %18, %28, implicit $exec
+    %19:sreg_32 = SI_IF_BREAK killed %64, killed %1, implicit-def dead $scc
+    SI_LOOP %19, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.8
+  
+  bb.8:
+    SI_END_CF killed %19, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    GLOBAL_STORE_DWORD killed %67, killed %17, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    S_ENDPGM 0
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
new file mode 100644
index 0000000000000..446d098f616a2
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
@@ -0,0 +1,6346 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#                     bb.0.entry
+#                         |
+#                 bb.1.loop1.header<-----------------------+
+#                         |                                |
+#                 bb.2.loop2.header<--------------------+  |
+#                      /    |                           |  |
+#     bb.3.loop4.preheader  |                           |  |
+#                /          |                           |  |
+#        bb.12.loop4<-+     |                           |  |
+#             +-------+     |                           |  |
+#             |             |                           |  |
+#        bb.13.Flow         |                           |  |
+#               \           |                           |  |
+#                bb.11.Flow14                           |  |
+#                  |       \                            |  |
+#                  |      bb.4.loop3.header.preheader   |  |
+#                  |                   |                |  |
+#                  |           bb.6.loop3.header<----+  |  |
+#                  |               /     |           |  |  |
+#                  |           bb.9.bb3  |           |  |  |
+#                  |               \     |           |  |  |
+#                  |             bb.7.Flow12         |  |  |
+#                  |               /       |         |  |  |
+#                  |             bb.8.bb2  |         |  |  |
+#                  |               \       |         |  |  |
+#                  |           bb.10.loop3.latch-----+  |  |
+#                  |               /                    |  |
+#                  |      bb.14.Flow13                  |  |
+#                  |       /                            |  |
+#                 bb.5.Flow15                           |  |
+#                     |                                 |  |
+#                 bb.15.bb4                             |  |
+#                  /   |                                |  |
+#           bb.16.bb5  |                                |  |
+#                  \   |                                |  |
+#            bb.17.loop2.latch--------------------------+  |
+#                     |                                    |
+#            bb.18.loop1.latch-----------------------------+
+#                     |
+#                bb.19.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test13 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr14
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 61 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 60 ]
+# CHECK: Vreg: %1[ 68 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 59 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %1[ 67 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %2[ 76 ]
+# CHECK: Vreg: %1[ 66 ]
+# CHECK: Vreg: %3[ 99 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 57 ]
+# CHECK: Vreg: %2[ 75 ]
+# CHECK: Vreg: %4[ 114 ]
+# CHECK: Vreg: %1[ 65 ]
+# CHECK: Vreg: %3[ 98 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 56 ]
+# CHECK: Vreg: %2[ 74 ]
+# CHECK: Vreg: %4[ 113 ]
+# CHECK: Vreg: %1[ 64 ]
+# CHECK: Vreg: %3[ 97 ]
+# CHECK: Vreg: %5[ 9 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 55 ]
+# CHECK: Vreg: %2[ 73 ]
+# CHECK: Vreg: %4[ 112 ]
+# CHECK: Vreg: %6[ 8 ]
+# CHECK: Vreg: %1[ 63 ]
+# CHECK: Vreg: %3[ 96 ]
+# CHECK: Vreg: %5[ 8 ]
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 54 ]
+# CHECK: Vreg: %7[ 8 ]
+# CHECK: Vreg: %2[ 72 ]
+# CHECK: Vreg: %4[ 111 ]
+# CHECK: Vreg: %6[ 7 ]
+# CHECK: Vreg: %1[ 62 ]
+# CHECK: Vreg: %3[ 95 ]
+# CHECK: Vreg: %5[ 7 ]
+# CHECK: Instr: %9:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 53 ]
+# CHECK: Vreg: %7[ 7 ]
+# CHECK: Vreg: %2[ 71 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %6[ 6 ]
+# CHECK: Vreg: %1[ 61 ]
+# CHECK: Vreg: %8[ 7 ]
+# CHECK: Vreg: %3[ 94 ]
+# CHECK: Vreg: %5[ 6 ]
+# CHECK: Instr: %10:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 52 ]
+# CHECK: Vreg: %7[ 6 ]
+# CHECK: Vreg: %2[ 70 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %6[ 5 ]
+# CHECK: Vreg: %1[ 60 ]
+# CHECK: Vreg: %8[ 6 ]
+# CHECK: Vreg: %3[ 93 ]
+# CHECK: Vreg: %5[ 5 ]
+# CHECK: Instr: %11:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 51 ]
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %2[ 69 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %4[ 108 ]
+# CHECK: Vreg: %6[ 4 ]
+# CHECK: Vreg: %1[ 59 ]
+# CHECK: Vreg: %8[ 5 ]
+# CHECK: Vreg: %3[ 92 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Instr: %12:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 50 ]
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %2[ 68 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: Vreg: %3[ 91 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Instr: %13:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 49 ]
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %2[ 67 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 106 ]
+# CHECK: Vreg: %11[ 5 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 57 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Vreg: %12[ 5 ]
+# CHECK: Instr: %14:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 48 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %2[ 66 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 105 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %13[ 5 ]
+# CHECK: Vreg: %1[ 56 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %3[ 89 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Vreg: %12[ 4 ]
+# CHECK: Instr: %15:vreg_64 = REG_SEQUENCE killed %6, %subreg.sub0, killed %5, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %14[ 4 ]
+# CHECK: Vreg: %2[ 65 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %4[ 104 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %1[ 55 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %3[ 88 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %12[ 3 ]
+# CHECK: Instr: %16:vreg_64 = REG_SEQUENCE killed %8, %subreg.sub0, killed %7, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %2[ 64 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %4[ 103 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %1[ 54 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %15[ 59 ]
+# CHECK: Vreg: %3[ 87 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %12[ 2 ]
+# CHECK: Instr: %17:vreg_64 = REG_SEQUENCE killed %10, %subreg.sub0, killed %9, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %2[ 63 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %16:sub0[ 96 ]
+# CHECK: Vreg: %16:sub1[ 97 ]
+# CHECK: Vreg: %16[ 103 ]
+# CHECK: Vreg: %4[ 102 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 53 ]
+# CHECK: Vreg: %15[ 58 ]
+# CHECK: Vreg: %3[ 86 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: %18:vreg_64 = REG_SEQUENCE killed %12, %subreg.sub0, killed %11, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 44 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %2[ 62 ]
+# CHECK: Vreg: %16:sub0[ 95 ]
+# CHECK: Vreg: %16:sub1[ 96 ]
+# CHECK: Vreg: %16[ 102 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 52 ]
+# CHECK: Vreg: %15[ 57 ]
+# CHECK: Vreg: %3[ 85 ]
+# CHECK: Vreg: %17:sub0[ 74 ]
+# CHECK: Vreg: %17:sub1[ 75 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %19:vreg_64 = REG_SEQUENCE killed %14, %subreg.sub0, killed %13, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %2[ 61 ]
+# CHECK: Vreg: %16:sub0[ 94 ]
+# CHECK: Vreg: %16:sub1[ 95 ]
+# CHECK: Vreg: %16[ 101 ]
+# CHECK: Vreg: %4[ 100 ]
+# CHECK: Vreg: %18:sub0[ 14 ]
+# CHECK: Vreg: %18:sub1[ 15 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %15[ 56 ]
+# CHECK: Vreg: %3[ 84 ]
+# CHECK: Vreg: %17:sub0[ 73 ]
+# CHECK: Vreg: %17:sub1[ 74 ]
+# CHECK: Instr: %20:vgpr_32 = GLOBAL_LOAD_UBYTE %19, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 42 ]
+# CHECK: Vreg: %2[ 60 ]
+# CHECK: Vreg: %16:sub0[ 93 ]
+# CHECK: Vreg: %16:sub1[ 94 ]
+# CHECK: Vreg: %16[ 100 ]
+# CHECK: Vreg: %4[ 99 ]
+# CHECK: Vreg: %18:sub0[ 13 ]
+# CHECK: Vreg: %18:sub1[ 14 ]
+# CHECK: Vreg: %1[ 50 ]
+# CHECK: Vreg: %15[ 55 ]
+# CHECK: Vreg: %3[ 83 ]
+# CHECK: Vreg: %17:sub0[ 72 ]
+# CHECK: Vreg: %17:sub1[ 73 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %21:vgpr_32 = GLOBAL_LOAD_UBYTE %19, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %2[ 59 ]
+# CHECK: Vreg: %16:sub0[ 92 ]
+# CHECK: Vreg: %16:sub1[ 93 ]
+# CHECK: Vreg: %16[ 99 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %18:sub0[ 12 ]
+# CHECK: Vreg: %18:sub1[ 13 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %1[ 49 ]
+# CHECK: Vreg: %15[ 54 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %17:sub0[ 71 ]
+# CHECK: Vreg: %17:sub1[ 72 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %22:vgpr_32 = V_LSHL_OR_B32_e64 killed %21, 8, killed %20, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 58 ]
+# CHECK: Vreg: %16:sub0[ 91 ]
+# CHECK: Vreg: %16:sub1[ 92 ]
+# CHECK: Vreg: %16[ 98 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %18:sub0[ 11 ]
+# CHECK: Vreg: %18:sub1[ 12 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 48 ]
+# CHECK: Vreg: %15[ 53 ]
+# CHECK: Vreg: %3[ 81 ]
+# CHECK: Vreg: %17:sub0[ 70 ]
+# CHECK: Vreg: %17:sub1[ 71 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: %23:vgpr_32 = GLOBAL_LOAD_UBYTE %19, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 39 ]
+# CHECK: Vreg: %2[ 57 ]
+# CHECK: Vreg: %16:sub0[ 90 ]
+# CHECK: Vreg: %16:sub1[ 91 ]
+# CHECK: Vreg: %16[ 97 ]
+# CHECK: Vreg: %4[ 96 ]
+# CHECK: Vreg: %18:sub0[ 10 ]
+# CHECK: Vreg: %18:sub1[ 11 ]
+# CHECK: Vreg: %1[ 47 ]
+# CHECK: Vreg: %15[ 52 ]
+# CHECK: Vreg: %22[ 3 ]
+# CHECK: Vreg: %3[ 80 ]
+# CHECK: Vreg: %17:sub0[ 69 ]
+# CHECK: Vreg: %17:sub1[ 70 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %24:vgpr_32 = GLOBAL_LOAD_UBYTE killed %19, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 38 ]
+# CHECK: Vreg: %2[ 56 ]
+# CHECK: Vreg: %16:sub0[ 89 ]
+# CHECK: Vreg: %16:sub1[ 90 ]
+# CHECK: Vreg: %16[ 96 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %4[ 95 ]
+# CHECK: Vreg: %18:sub0[ 9 ]
+# CHECK: Vreg: %18:sub1[ 10 ]
+# CHECK: Vreg: %1[ 46 ]
+# CHECK: Vreg: %15[ 51 ]
+# CHECK: Vreg: %22[ 2 ]
+# CHECK: Vreg: %3[ 79 ]
+# CHECK: Vreg: %17:sub0[ 68 ]
+# CHECK: Vreg: %17:sub1[ 69 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %25:vgpr_32 = V_LSHL_OR_B32_e64 killed %24, 8, killed %23, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %2[ 55 ]
+# CHECK: Vreg: %16:sub0[ 88 ]
+# CHECK: Vreg: %16:sub1[ 89 ]
+# CHECK: Vreg: %16[ 95 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %18:sub0[ 8 ]
+# CHECK: Vreg: %18:sub1[ 9 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %15[ 50 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %3[ 78 ]
+# CHECK: Vreg: %17:sub0[ 67 ]
+# CHECK: Vreg: %17:sub1[ 68 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %26:vgpr_32 = V_LSHL_OR_B32_e64 killed %25, 16, killed %22, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %2[ 54 ]
+# CHECK: Vreg: %16:sub0[ 87 ]
+# CHECK: Vreg: %16:sub1[ 88 ]
+# CHECK: Vreg: %16[ 94 ]
+# CHECK: Vreg: %4[ 93 ]
+# CHECK: Vreg: %18:sub0[ 7 ]
+# CHECK: Vreg: %18:sub1[ 8 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %15[ 49 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 77 ]
+# CHECK: Vreg: %17:sub0[ 66 ]
+# CHECK: Vreg: %17:sub1[ 67 ]
+# CHECK: Instr: %27:vgpr_32 = V_ADD_U32_e64 100, %26, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %2[ 53 ]
+# CHECK: Vreg: %16:sub0[ 86 ]
+# CHECK: Vreg: %16:sub1[ 87 ]
+# CHECK: Vreg: %16[ 93 ]
+# CHECK: Vreg: %4[ 92 ]
+# CHECK: Vreg: %18:sub0[ 6 ]
+# CHECK: Vreg: %18:sub1[ 7 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %15[ 48 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %17:sub0[ 65 ]
+# CHECK: Vreg: %17:sub1[ 66 ]
+# CHECK: Instr: %28:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %26[ 26 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %16:sub0[ 85 ]
+# CHECK: Vreg: %16:sub1[ 86 ]
+# CHECK: Vreg: %16[ 92 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %18:sub0[ 5 ]
+# CHECK: Vreg: %18:sub1[ 6 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %27[ 68 ]
+# CHECK: Vreg: %15[ 47 ]
+# CHECK: Vreg: %3[ 75 ]
+# CHECK: Vreg: %17:sub0[ 64 ]
+# CHECK: Vreg: %17:sub1[ 65 ]
+# CHECK: Instr: %29:sreg_32 = S_MOV_B32 2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %16:sub0[ 84 ]
+# CHECK: Vreg: %16:sub1[ 85 ]
+# CHECK: Vreg: %16[ 91 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %18:sub0[ 4 ]
+# CHECK: Vreg: %18:sub1[ 5 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %27[ 67 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %3[ 74 ]
+# CHECK: Vreg: %17:sub0[ 63 ]
+# CHECK: Vreg: %17:sub1[ 64 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %16:sub0[ 84 ]
+# CHECK: Vreg: %16:sub1[ 85 ]
+# CHECK: Vreg: %16[ 91 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %18:sub0[ 4 ]
+# CHECK: Vreg: %18:sub1[ 5 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %27[ 67 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %3[ 74 ]
+# CHECK: Vreg: %29[ 24 ]
+# CHECK: Vreg: %17:sub0[ 63 ]
+# CHECK: Vreg: %17:sub1[ 64 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %30:sreg_32 = PHI %28, %bb.0, %31, %bb.18
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %16:sub0[ 84 ]
+# CHECK: Vreg: %16:sub1[ 85 ]
+# CHECK: Vreg: %16[ 91 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %18:sub0[ 4 ]
+# CHECK: Vreg: %18:sub1[ 5 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %27[ 67 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %3[ 74 ]
+# CHECK: Vreg: %29[ 24 ]
+# CHECK: Vreg: %17:sub0[ 63 ]
+# CHECK: Vreg: %17:sub1[ 64 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %32:sreg_32 = PHI %28, %bb.0, %33, %bb.18
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %16:sub0[ 84 ]
+# CHECK: Vreg: %16:sub1[ 85 ]
+# CHECK: Vreg: %16[ 91 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %30[ 91 ]
+# CHECK: Vreg: %18:sub0[ 4 ]
+# CHECK: Vreg: %18:sub1[ 5 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %27[ 67 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %3[ 74 ]
+# CHECK: Vreg: %29[ 24 ]
+# CHECK: Vreg: %17:sub0[ 63 ]
+# CHECK: Vreg: %17:sub1[ 64 ]
+# CHECK: Instr: %34:sreg_32 = PHI %28, %bb.0, %35, %bb.18
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %16:sub0[ 84 ]
+# CHECK: Vreg: %16:sub1[ 85 ]
+# CHECK: Vreg: %16[ 91 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %30[ 91 ]
+# CHECK: Vreg: %18:sub0[ 4 ]
+# CHECK: Vreg: %18:sub1[ 5 ]
+# CHECK: Vreg: %32[ 40 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %27[ 67 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %3[ 74 ]
+# CHECK: Vreg: %29[ 24 ]
+# CHECK: Vreg: %17:sub0[ 63 ]
+# CHECK: Vreg: %17:sub1[ 64 ]
+# CHECK: Instr: %36:sreg_32_xm0 = S_ASHR_I32 %34, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %2[ 50 ]
+# CHECK: Vreg: %28[ 23 ]
+# CHECK: Vreg: %16:sub0[ 83 ]
+# CHECK: Vreg: %16:sub1[ 84 ]
+# CHECK: Vreg: %16[ 90 ]
+# CHECK: Vreg: %4[ 89 ]
+# CHECK: Vreg: %30[ 90 ]
+# CHECK: Vreg: %18:sub0[ 3 ]
+# CHECK: Vreg: %18:sub1[ 4 ]
+# CHECK: Vreg: %32[ 39 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %27[ 66 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 45 ]
+# CHECK: Vreg: %3[ 73 ]
+# CHECK: Vreg: %29[ 23 ]
+# CHECK: Vreg: %17:sub0[ 62 ]
+# CHECK: Vreg: %17:sub1[ 63 ]
+# CHECK: Instr: %37:sreg_64 = REG_SEQUENCE %34, %subreg.sub0, killed %36, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %26[ 23 ]
+# CHECK: Vreg: %2[ 49 ]
+# CHECK: Vreg: %28[ 22 ]
+# CHECK: Vreg: %16:sub0[ 82 ]
+# CHECK: Vreg: %16:sub1[ 83 ]
+# CHECK: Vreg: %16[ 89 ]
+# CHECK: Vreg: %4[ 88 ]
+# CHECK: Vreg: %30[ 89 ]
+# CHECK: Vreg: %18:sub0[ 2 ]
+# CHECK: Vreg: %18:sub1[ 3 ]
+# CHECK: Vreg: %32[ 38 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %27[ 65 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 44 ]
+# CHECK: Vreg: %3[ 72 ]
+# CHECK: Vreg: %29[ 22 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17:sub0[ 61 ]
+# CHECK: Vreg: %17:sub1[ 62 ]
+# CHECK: Instr: %38:sreg_64 = nsw S_LSHL_B64 killed %37, 3, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %26[ 22 ]
+# CHECK: Vreg: %2[ 48 ]
+# CHECK: Vreg: %28[ 21 ]
+# CHECK: Vreg: %16:sub0[ 81 ]
+# CHECK: Vreg: %16:sub1[ 82 ]
+# CHECK: Vreg: %16[ 88 ]
+# CHECK: Vreg: %4[ 87 ]
+# CHECK: Vreg: %30[ 88 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %18:sub0[ 1 ]
+# CHECK: Vreg: %18:sub1[ 2 ]
+# CHECK: Vreg: %32[ 37 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %27[ 64 ]
+# CHECK: Vreg: %34[ 11 ]
+# CHECK: Vreg: %15[ 43 ]
+# CHECK: Vreg: %3[ 71 ]
+# CHECK: Vreg: %29[ 21 ]
+# CHECK: Vreg: %17:sub0[ 60 ]
+# CHECK: Vreg: %17:sub1[ 61 ]
+# CHECK: Instr: %39:vgpr_32, %40:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %18.sub0, %38.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %26[ 21 ]
+# CHECK: Vreg: %2[ 47 ]
+# CHECK: Vreg: %28[ 20 ]
+# CHECK: Vreg: %16:sub0[ 80 ]
+# CHECK: Vreg: %16:sub1[ 81 ]
+# CHECK: Vreg: %16[ 87 ]
+# CHECK: Vreg: %4[ 86 ]
+# CHECK: Vreg: %30[ 87 ]
+# CHECK: Vreg: %18:sub0[ 0 ]
+# CHECK: Vreg: %18:sub1[ 1 ]
+# CHECK: Vreg: %32[ 36 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %27[ 63 ]
+# CHECK: Vreg: %34[ 10 ]
+# CHECK: Vreg: %15[ 42 ]
+# CHECK: Vreg: %3[ 70 ]
+# CHECK: Vreg: %29[ 20 ]
+# CHECK: Vreg: %17:sub0[ 59 ]
+# CHECK: Vreg: %17:sub1[ 60 ]
+# CHECK: Vreg: %38:sub0[ 0 ]
+# CHECK: Vreg: %38:sub1[ 1 ]
+# CHECK: Instr: %41:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %38.sub1, %18.sub1, killed %40, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %26[ 20 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %2[ 46 ]
+# CHECK: Vreg: %28[ 19 ]
+# CHECK: Vreg: %16:sub0[ 79 ]
+# CHECK: Vreg: %16:sub1[ 80 ]
+# CHECK: Vreg: %16[ 86 ]
+# CHECK: Vreg: %4[ 85 ]
+# CHECK: Vreg: %30[ 86 ]
+# CHECK: Vreg: %18:sub1[ 0 ]
+# CHECK: Vreg: %18:sub0[ 24 ]
+# CHECK: Vreg: %32[ 35 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %27[ 62 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 41 ]
+# CHECK: Vreg: %3[ 69 ]
+# CHECK: Vreg: %29[ 19 ]
+# CHECK: Vreg: %17:sub0[ 58 ]
+# CHECK: Vreg: %17:sub1[ 59 ]
+# CHECK: Vreg: %38:sub1[ 0 ]
+# CHECK: Instr: %42:vreg_64 = REG_SEQUENCE killed %39, %subreg.sub0, killed %41, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %26[ 19 ]
+# CHECK: Vreg: %2[ 45 ]
+# CHECK: Vreg: %28[ 18 ]
+# CHECK: Vreg: %16:sub0[ 78 ]
+# CHECK: Vreg: %16:sub1[ 79 ]
+# CHECK: Vreg: %16[ 85 ]
+# CHECK: Vreg: %4[ 84 ]
+# CHECK: Vreg: %30[ 85 ]
+# CHECK: Vreg: %18:sub0[ 23 ]
+# CHECK: Vreg: %18:sub1[ 24 ]
+# CHECK: Vreg: %32[ 34 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %27[ 61 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %15[ 40 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %3[ 68 ]
+# CHECK: Vreg: %29[ 18 ]
+# CHECK: Vreg: %17:sub0[ 57 ]
+# CHECK: Vreg: %17:sub1[ 58 ]
+# CHECK: Instr: %43:vgpr_32 = GLOBAL_LOAD_UBYTE %42, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %26[ 18 ]
+# CHECK: Vreg: %2[ 44 ]
+# CHECK: Vreg: %28[ 17 ]
+# CHECK: Vreg: %16:sub0[ 77 ]
+# CHECK: Vreg: %16:sub1[ 78 ]
+# CHECK: Vreg: %16[ 84 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 83 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %18:sub0[ 22 ]
+# CHECK: Vreg: %18:sub1[ 23 ]
+# CHECK: Vreg: %32[ 33 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %27[ 60 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %15[ 39 ]
+# CHECK: Vreg: %3[ 67 ]
+# CHECK: Vreg: %29[ 17 ]
+# CHECK: Vreg: %17:sub0[ 56 ]
+# CHECK: Vreg: %17:sub1[ 57 ]
+# CHECK: Instr: %44:vgpr_32 = GLOBAL_LOAD_UBYTE %42, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %2[ 43 ]
+# CHECK: Vreg: %28[ 16 ]
+# CHECK: Vreg: %16:sub0[ 76 ]
+# CHECK: Vreg: %16:sub1[ 77 ]
+# CHECK: Vreg: %16[ 83 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 82 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %18:sub0[ 21 ]
+# CHECK: Vreg: %18:sub1[ 22 ]
+# CHECK: Vreg: %32[ 32 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %27[ 59 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %15[ 38 ]
+# CHECK: Vreg: %3[ 66 ]
+# CHECK: Vreg: %29[ 16 ]
+# CHECK: Vreg: %17:sub0[ 55 ]
+# CHECK: Vreg: %17:sub1[ 56 ]
+# CHECK: Vreg: %43[ 1 ]
+# CHECK: Instr: %45:vgpr_32 = V_LSHL_OR_B32_e64 killed %44, 8, killed %43, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %2[ 42 ]
+# CHECK: Vreg: %28[ 15 ]
+# CHECK: Vreg: %16:sub0[ 75 ]
+# CHECK: Vreg: %16:sub1[ 76 ]
+# CHECK: Vreg: %16[ 82 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %4[ 81 ]
+# CHECK: Vreg: %30[ 82 ]
+# CHECK: Vreg: %18:sub0[ 20 ]
+# CHECK: Vreg: %18:sub1[ 21 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %32[ 31 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %27[ 58 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %15[ 37 ]
+# CHECK: Vreg: %3[ 65 ]
+# CHECK: Vreg: %29[ 15 ]
+# CHECK: Vreg: %17:sub0[ 54 ]
+# CHECK: Vreg: %17:sub1[ 55 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Instr: %46:vgpr_32 = GLOBAL_LOAD_UBYTE %42, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 15 ]
+# CHECK: Vreg: %2[ 41 ]
+# CHECK: Vreg: %28[ 14 ]
+# CHECK: Vreg: %16:sub0[ 74 ]
+# CHECK: Vreg: %16:sub1[ 75 ]
+# CHECK: Vreg: %16[ 81 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 80 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %18:sub0[ 19 ]
+# CHECK: Vreg: %18:sub1[ 20 ]
+# CHECK: Vreg: %32[ 30 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %27[ 57 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %3[ 64 ]
+# CHECK: Vreg: %29[ 14 ]
+# CHECK: Vreg: %17:sub0[ 53 ]
+# CHECK: Vreg: %17:sub1[ 54 ]
+# CHECK: Instr: %47:vgpr_32 = GLOBAL_LOAD_UBYTE killed %42, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %45[ 2 ]
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %2[ 40 ]
+# CHECK: Vreg: %28[ 13 ]
+# CHECK: Vreg: %16:sub0[ 73 ]
+# CHECK: Vreg: %16:sub1[ 74 ]
+# CHECK: Vreg: %16[ 80 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 79 ]
+# CHECK: Vreg: %30[ 80 ]
+# CHECK: Vreg: %18:sub0[ 18 ]
+# CHECK: Vreg: %18:sub1[ 19 ]
+# CHECK: Vreg: %32[ 29 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %27[ 56 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %15[ 35 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %29[ 13 ]
+# CHECK: Vreg: %17:sub0[ 52 ]
+# CHECK: Vreg: %17:sub1[ 53 ]
+# CHECK: Instr: %48:vgpr_32 = V_LSHL_OR_B32_e64 killed %47, 8, killed %46, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %26[ 13 ]
+# CHECK: Vreg: %2[ 39 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %28[ 12 ]
+# CHECK: Vreg: %16:sub0[ 72 ]
+# CHECK: Vreg: %16:sub1[ 73 ]
+# CHECK: Vreg: %16[ 79 ]
+# CHECK: Vreg: %4[ 78 ]
+# CHECK: Vreg: %30[ 79 ]
+# CHECK: Vreg: %18:sub0[ 17 ]
+# CHECK: Vreg: %18:sub1[ 18 ]
+# CHECK: Vreg: %32[ 28 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ 55 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %15[ 34 ]
+# CHECK: Vreg: %3[ 62 ]
+# CHECK: Vreg: %29[ 12 ]
+# CHECK: Vreg: %17:sub0[ 51 ]
+# CHECK: Vreg: %17:sub1[ 52 ]
+# CHECK: Instr: %49:vgpr_32 = V_LSHL_OR_B32_e64 killed %48, 16, killed %45, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %2[ 38 ]
+# CHECK: Vreg: %28[ 11 ]
+# CHECK: Vreg: %16:sub0[ 71 ]
+# CHECK: Vreg: %16:sub1[ 72 ]
+# CHECK: Vreg: %16[ 78 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 78 ]
+# CHECK: Vreg: %18:sub0[ 16 ]
+# CHECK: Vreg: %18:sub1[ 17 ]
+# CHECK: Vreg: %32[ 27 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %27[ 54 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 33 ]
+# CHECK: Vreg: %3[ 61 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %29[ 11 ]
+# CHECK: Vreg: %17:sub0[ 50 ]
+# CHECK: Vreg: %17:sub1[ 51 ]
+# CHECK: Instr: %50:sgpr_32 = S_CVT_F32_U32 %34, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %2[ 37 ]
+# CHECK: Vreg: %28[ 10 ]
+# CHECK: Vreg: %16:sub0[ 70 ]
+# CHECK: Vreg: %16:sub1[ 71 ]
+# CHECK: Vreg: %16[ 77 ]
+# CHECK: Vreg: %4[ 76 ]
+# CHECK: Vreg: %49[ 66 ]
+# CHECK: Vreg: %30[ 77 ]
+# CHECK: Vreg: %18:sub0[ 15 ]
+# CHECK: Vreg: %18:sub1[ 16 ]
+# CHECK: Vreg: %32[ 26 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %27[ 53 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 32 ]
+# CHECK: Vreg: %3[ 60 ]
+# CHECK: Vreg: %29[ 10 ]
+# CHECK: Vreg: %17:sub0[ 49 ]
+# CHECK: Vreg: %17:sub1[ 50 ]
+# CHECK: Instr: %51:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %50, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %2[ 36 ]
+# CHECK: Vreg: %28[ 9 ]
+# CHECK: Vreg: %16:sub0[ 69 ]
+# CHECK: Vreg: %16:sub1[ 70 ]
+# CHECK: Vreg: %16[ 76 ]
+# CHECK: Vreg: %4[ 75 ]
+# CHECK: Vreg: %49[ 65 ]
+# CHECK: Vreg: %30[ 76 ]
+# CHECK: Vreg: %18:sub0[ 14 ]
+# CHECK: Vreg: %18:sub1[ 15 ]
+# CHECK: Vreg: %32[ 25 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %27[ 52 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %15[ 31 ]
+# CHECK: Vreg: %3[ 59 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %17:sub0[ 48 ]
+# CHECK: Vreg: %17:sub1[ 49 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Instr: %52:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %51, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %28[ 8 ]
+# CHECK: Vreg: %16:sub0[ 68 ]
+# CHECK: Vreg: %16:sub1[ 69 ]
+# CHECK: Vreg: %16[ 75 ]
+# CHECK: Vreg: %4[ 74 ]
+# CHECK: Vreg: %49[ 64 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %18:sub0[ 13 ]
+# CHECK: Vreg: %18:sub1[ 14 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %32[ 24 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %27[ 51 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %15[ 30 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %29[ 8 ]
+# CHECK: Vreg: %17:sub0[ 47 ]
+# CHECK: Vreg: %17:sub1[ 48 ]
+# CHECK: Instr: %53:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %52, 1333788670, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %2[ 34 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %16:sub0[ 67 ]
+# CHECK: Vreg: %16:sub1[ 68 ]
+# CHECK: Vreg: %16[ 74 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %49[ 63 ]
+# CHECK: Vreg: %30[ 74 ]
+# CHECK: Vreg: %18:sub0[ 12 ]
+# CHECK: Vreg: %18:sub1[ 13 ]
+# CHECK: Vreg: %32[ 23 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %27[ 50 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %3[ 57 ]
+# CHECK: Vreg: %29[ 7 ]
+# CHECK: Vreg: %17:sub0[ 46 ]
+# CHECK: Vreg: %17:sub1[ 47 ]
+# CHECK: Instr: %54:sreg_32 = nofpexcept S_CVT_U32_F32 killed %53, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %26[ 7 ]
+# CHECK: Vreg: %2[ 33 ]
+# CHECK: Vreg: %28[ 6 ]
+# CHECK: Vreg: %16:sub0[ 66 ]
+# CHECK: Vreg: %16:sub1[ 67 ]
+# CHECK: Vreg: %16[ 73 ]
+# CHECK: Vreg: %4[ 72 ]
+# CHECK: Vreg: %49[ 62 ]
+# CHECK: Vreg: %30[ 73 ]
+# CHECK: Vreg: %18:sub0[ 11 ]
+# CHECK: Vreg: %18:sub1[ 12 ]
+# CHECK: Vreg: %32[ 22 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %27[ 49 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 28 ]
+# CHECK: Vreg: %3[ 56 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %17:sub0[ 45 ]
+# CHECK: Vreg: %17:sub1[ 46 ]
+# CHECK: Instr: %55:sreg_32 = S_SUB_I32 0, %34, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %28[ 5 ]
+# CHECK: Vreg: %54[ 1 ]
+# CHECK: Vreg: %16:sub0[ 65 ]
+# CHECK: Vreg: %16:sub1[ 66 ]
+# CHECK: Vreg: %16[ 72 ]
+# CHECK: Vreg: %4[ 71 ]
+# CHECK: Vreg: %49[ 61 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %18:sub0[ 10 ]
+# CHECK: Vreg: %18:sub1[ 11 ]
+# CHECK: Vreg: %32[ 21 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %27[ 48 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 27 ]
+# CHECK: Vreg: %3[ 55 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %17:sub0[ 44 ]
+# CHECK: Vreg: %17:sub1[ 45 ]
+# CHECK: Instr: %56:sreg_32 = S_MUL_I32 killed %55, %54
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %2[ 31 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %16:sub0[ 64 ]
+# CHECK: Vreg: %16:sub1[ 65 ]
+# CHECK: Vreg: %16[ 71 ]
+# CHECK: Vreg: %4[ 70 ]
+# CHECK: Vreg: %49[ 60 ]
+# CHECK: Vreg: %30[ 71 ]
+# CHECK: Vreg: %18:sub0[ 9 ]
+# CHECK: Vreg: %18:sub1[ 10 ]
+# CHECK: Vreg: %32[ 20 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %27[ 47 ]
+# CHECK: Vreg: %34[ 29 ]
+# CHECK: Vreg: %15[ 26 ]
+# CHECK: Vreg: %3[ 54 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %17:sub0[ 43 ]
+# CHECK: Vreg: %17:sub1[ 44 ]
+# CHECK: Instr: %57:sreg_32 = S_MUL_HI_U32 %54, killed %56
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %2[ 30 ]
+# CHECK: Vreg: %28[ 3 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %16:sub0[ 63 ]
+# CHECK: Vreg: %16:sub1[ 64 ]
+# CHECK: Vreg: %16[ 70 ]
+# CHECK: Vreg: %4[ 69 ]
+# CHECK: Vreg: %49[ 59 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %18:sub0[ 8 ]
+# CHECK: Vreg: %18:sub1[ 9 ]
+# CHECK: Vreg: %32[ 19 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %27[ 46 ]
+# CHECK: Vreg: %34[ 28 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %17:sub0[ 42 ]
+# CHECK: Vreg: %17:sub1[ 43 ]
+# CHECK: Instr: %58:sreg_32 = S_ADD_I32 killed %54, killed %57, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %28[ 2 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %16:sub0[ 62 ]
+# CHECK: Vreg: %16:sub1[ 63 ]
+# CHECK: Vreg: %16[ 69 ]
+# CHECK: Vreg: %4[ 68 ]
+# CHECK: Vreg: %49[ 58 ]
+# CHECK: Vreg: %30[ 69 ]
+# CHECK: Vreg: %18:sub0[ 7 ]
+# CHECK: Vreg: %18:sub1[ 8 ]
+# CHECK: Vreg: %32[ 18 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %27[ 45 ]
+# CHECK: Vreg: %34[ 27 ]
+# CHECK: Vreg: %15[ 24 ]
+# CHECK: Vreg: %3[ 52 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %17:sub0[ 41 ]
+# CHECK: Vreg: %17:sub1[ 42 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Instr: %59:sreg_64 = REG_SEQUENCE killed %58, %subreg.sub0, undef %28, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %2[ 28 ]
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %16:sub0[ 61 ]
+# CHECK: Vreg: %16:sub1[ 62 ]
+# CHECK: Vreg: %16[ 68 ]
+# CHECK: Vreg: %4[ 67 ]
+# CHECK: Vreg: %49[ 57 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %18:sub0[ 6 ]
+# CHECK: Vreg: %18:sub1[ 7 ]
+# CHECK: Vreg: %32[ 17 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %27[ 44 ]
+# CHECK: Vreg: %34[ 26 ]
+# CHECK: Vreg: %15[ 23 ]
+# CHECK: Vreg: %3[ 51 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17:sub0[ 40 ]
+# CHECK: Vreg: %17:sub1[ 41 ]
+# CHECK: Instr: %60:sreg_32 = S_MOV_B32 20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %59:sub0[ 47 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %16:sub0[ 60 ]
+# CHECK: Vreg: %16:sub1[ 61 ]
+# CHECK: Vreg: %16[ 67 ]
+# CHECK: Vreg: %4[ 66 ]
+# CHECK: Vreg: %49[ 56 ]
+# CHECK: Vreg: %30[ 67 ]
+# CHECK: Vreg: %18:sub0[ 5 ]
+# CHECK: Vreg: %18:sub1[ 6 ]
+# CHECK: Vreg: %32[ 16 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %27[ 43 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17:sub0[ 39 ]
+# CHECK: Vreg: %17:sub1[ 40 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %59:sub0[ 47 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %16:sub0[ 60 ]
+# CHECK: Vreg: %16:sub1[ 61 ]
+# CHECK: Vreg: %16[ 67 ]
+# CHECK: Vreg: %4[ 66 ]
+# CHECK: Vreg: %49[ 56 ]
+# CHECK: Vreg: %30[ 67 ]
+# CHECK: Vreg: %18:sub0[ 5 ]
+# CHECK: Vreg: %18:sub1[ 6 ]
+# CHECK: Vreg: %32[ 16 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %27[ 43 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17:sub0[ 39 ]
+# CHECK: Vreg: %17:sub1[ 40 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %61:sreg_32 = PHI %28, %bb.1, %62, %bb.17
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %59:sub0[ 47 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %16[ 67 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+60 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+61 ]
+# CHECK: Vreg: %4[ LoopTag+66 ]
+# CHECK: Vreg: %49[ LoopTag+56 ]
+# CHECK: Vreg: %30[ LoopTag+67 ]
+# CHECK: Vreg: %18:sub0[ 5 ]
+# CHECK: Vreg: %18:sub1[ 6 ]
+# CHECK: Vreg: %32[ 16 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %27[ 43 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17:sub0[ 39 ]
+# CHECK: Vreg: %17:sub1[ 40 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Instr: %63:sreg_32 = PHI %60, %bb.1, %64, %bb.17
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %59:sub0[ 47 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %16[ 67 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+60 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+61 ]
+# CHECK: Vreg: %61[ 51 ]
+# CHECK: Vreg: %4[ LoopTag+66 ]
+# CHECK: Vreg: %49[ LoopTag+56 ]
+# CHECK: Vreg: %30[ LoopTag+67 ]
+# CHECK: Vreg: %18:sub0[ 5 ]
+# CHECK: Vreg: %18:sub1[ 6 ]
+# CHECK: Vreg: %32[ 16 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %27[ 43 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17:sub0[ 39 ]
+# CHECK: Vreg: %17:sub1[ 40 ]
+# CHECK: Instr: %65:sreg_32 = PHI %29, %bb.1, %66, %bb.17
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %59:sub0[ 47 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %16[ 67 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+60 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+61 ]
+# CHECK: Vreg: %61[ 51 ]
+# CHECK: Vreg: %4[ LoopTag+66 ]
+# CHECK: Vreg: %49[ LoopTag+56 ]
+# CHECK: Vreg: %30[ LoopTag+67 ]
+# CHECK: Vreg: %18:sub0[ 5 ]
+# CHECK: Vreg: %18:sub1[ 6 ]
+# CHECK: Vreg: %63[ 16 ]
+# CHECK: Vreg: %32[ 16 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %27[ 43 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17:sub0[ 39 ]
+# CHECK: Vreg: %17:sub1[ 40 ]
+# CHECK: Instr: %67:vgpr_32 = V_MUL_LO_U32_e64 %26, %65, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %59:sub0[ 46 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %16[ 66 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %61[ 50 ]
+# CHECK: Vreg: %4[ LoopTag+65 ]
+# CHECK: Vreg: %49[ LoopTag+55 ]
+# CHECK: Vreg: %30[ LoopTag+66 ]
+# CHECK: Vreg: %18:sub0[ 4 ]
+# CHECK: Vreg: %18:sub1[ 5 ]
+# CHECK: Vreg: %63[ 15 ]
+# CHECK: Vreg: %32[ 15 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 42 ]
+# CHECK: Vreg: %34[ 24 ]
+# CHECK: Vreg: %15[ 21 ]
+# CHECK: Vreg: %3[ 49 ]
+# CHECK: Vreg: %29[ LoopTag+92 ]
+# CHECK: Vreg: %17:sub0[ 38 ]
+# CHECK: Vreg: %17:sub1[ 39 ]
+# CHECK: Instr: %68:sreg_32_xm0 = S_ASHR_I32 %65, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ 52 ]
+# CHECK: Vreg: %59:sub0[ 45 ]
+# CHECK: Vreg: %2[ 25 ]
+# CHECK: Vreg: %16[ 65 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %61[ 49 ]
+# CHECK: Vreg: %4[ LoopTag+64 ]
+# CHECK: Vreg: %49[ LoopTag+54 ]
+# CHECK: Vreg: %30[ LoopTag+65 ]
+# CHECK: Vreg: %18:sub0[ 3 ]
+# CHECK: Vreg: %18:sub1[ 4 ]
+# CHECK: Vreg: %63[ 14 ]
+# CHECK: Vreg: %32[ 14 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 41 ]
+# CHECK: Vreg: %34[ 23 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %3[ 48 ]
+# CHECK: Vreg: %67[ 6 ]
+# CHECK: Vreg: %29[ LoopTag+91 ]
+# CHECK: Vreg: %17:sub0[ 37 ]
+# CHECK: Vreg: %17:sub1[ 38 ]
+# CHECK: Instr: %69:sreg_64 = REG_SEQUENCE %65, %subreg.sub0, killed %68, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %26[ 51 ]
+# CHECK: Vreg: %59:sub0[ 44 ]
+# CHECK: Vreg: %2[ 24 ]
+# CHECK: Vreg: %16[ 64 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %61[ 48 ]
+# CHECK: Vreg: %4[ LoopTag+63 ]
+# CHECK: Vreg: %49[ LoopTag+53 ]
+# CHECK: Vreg: %30[ LoopTag+64 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %18:sub0[ 2 ]
+# CHECK: Vreg: %18:sub1[ 3 ]
+# CHECK: Vreg: %63[ 13 ]
+# CHECK: Vreg: %32[ 13 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 40 ]
+# CHECK: Vreg: %34[ 22 ]
+# CHECK: Vreg: %15[ 19 ]
+# CHECK: Vreg: %3[ 47 ]
+# CHECK: Vreg: %67[ 5 ]
+# CHECK: Vreg: %29[ LoopTag+90 ]
+# CHECK: Vreg: %17:sub0[ 36 ]
+# CHECK: Vreg: %17:sub1[ 37 ]
+# CHECK: Instr: %70:sreg_64 = nsw S_LSHL_B64 killed %69, 3, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %26[ 50 ]
+# CHECK: Vreg: %59:sub0[ 43 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %16[ 63 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+56 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+57 ]
+# CHECK: Vreg: %61[ 47 ]
+# CHECK: Vreg: %4[ LoopTag+62 ]
+# CHECK: Vreg: %49[ LoopTag+52 ]
+# CHECK: Vreg: %30[ LoopTag+63 ]
+# CHECK: Vreg: %18:sub0[ 1 ]
+# CHECK: Vreg: %18:sub1[ 2 ]
+# CHECK: Vreg: %63[ 12 ]
+# CHECK: Vreg: %32[ 12 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %27[ 39 ]
+# CHECK: Vreg: %34[ 21 ]
+# CHECK: Vreg: %15[ 18 ]
+# CHECK: Vreg: %3[ 46 ]
+# CHECK: Vreg: %67[ 4 ]
+# CHECK: Vreg: %29[ LoopTag+89 ]
+# CHECK: Vreg: %17:sub0[ 35 ]
+# CHECK: Vreg: %17:sub1[ 36 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Instr: %71:vgpr_32, %72:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %18.sub0, %70.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %26[ 49 ]
+# CHECK: Vreg: %59:sub0[ 42 ]
+# CHECK: Vreg: %2[ 22 ]
+# CHECK: Vreg: %16[ 62 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %61[ 46 ]
+# CHECK: Vreg: %4[ LoopTag+61 ]
+# CHECK: Vreg: %49[ LoopTag+51 ]
+# CHECK: Vreg: %30[ LoopTag+62 ]
+# CHECK: Vreg: %18:sub0[ 0 ]
+# CHECK: Vreg: %18:sub1[ 1 ]
+# CHECK: Vreg: %63[ 11 ]
+# CHECK: Vreg: %70:sub0[ 0 ]
+# CHECK: Vreg: %70:sub1[ 1 ]
+# CHECK: Vreg: %32[ 11 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %27[ 38 ]
+# CHECK: Vreg: %34[ 20 ]
+# CHECK: Vreg: %15[ 17 ]
+# CHECK: Vreg: %3[ 45 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %29[ LoopTag+88 ]
+# CHECK: Vreg: %17:sub0[ 34 ]
+# CHECK: Vreg: %17:sub1[ 35 ]
+# CHECK: Instr: %73:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %70.sub1, %18.sub1, killed %72, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %26[ 48 ]
+# CHECK: Vreg: %71[ 1 ]
+# CHECK: Vreg: %59:sub0[ 41 ]
+# CHECK: Vreg: %2[ 21 ]
+# CHECK: Vreg: %16[ 61 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+54 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+55 ]
+# CHECK: Vreg: %61[ 45 ]
+# CHECK: Vreg: %4[ LoopTag+60 ]
+# CHECK: Vreg: %49[ LoopTag+50 ]
+# CHECK: Vreg: %30[ LoopTag+61 ]
+# CHECK: Vreg: %18:sub1[ 0 ]
+# CHECK: Vreg: %18:sub0[ 52 ]
+# CHECK: Vreg: %63[ 10 ]
+# CHECK: Vreg: %70:sub1[ 0 ]
+# CHECK: Vreg: %32[ 10 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ 37 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 19 ]
+# CHECK: Vreg: %15[ 16 ]
+# CHECK: Vreg: %3[ 44 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+87 ]
+# CHECK: Vreg: %17:sub0[ 33 ]
+# CHECK: Vreg: %17:sub1[ 34 ]
+# CHECK: Instr: %74:vreg_64 = REG_SEQUENCE killed %71, %subreg.sub0, killed %73, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ 47 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %59:sub0[ 40 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %16[ 60 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %61[ 44 ]
+# CHECK: Vreg: %4[ LoopTag+59 ]
+# CHECK: Vreg: %49[ LoopTag+49 ]
+# CHECK: Vreg: %30[ LoopTag+60 ]
+# CHECK: Vreg: %18:sub0[ 51 ]
+# CHECK: Vreg: %18:sub1[ 52 ]
+# CHECK: Vreg: %63[ 9 ]
+# CHECK: Vreg: %32[ 9 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %27[ 36 ]
+# CHECK: Vreg: %34[ 18 ]
+# CHECK: Vreg: %15[ 15 ]
+# CHECK: Vreg: %3[ 43 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+86 ]
+# CHECK: Vreg: %17:sub0[ 32 ]
+# CHECK: Vreg: %17:sub1[ 33 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %74, %67, 0, 0, implicit $exec :: (store (s32) into %ir.gep2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %26[ 46 ]
+# CHECK: Vreg: %59:sub0[ 39 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %16[ 59 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+52 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+53 ]
+# CHECK: Vreg: %61[ 43 ]
+# CHECK: Vreg: %4[ LoopTag+58 ]
+# CHECK: Vreg: %49[ LoopTag+48 ]
+# CHECK: Vreg: %30[ LoopTag+59 ]
+# CHECK: Vreg: %18:sub0[ 50 ]
+# CHECK: Vreg: %18:sub1[ 51 ]
+# CHECK: Vreg: %63[ 8 ]
+# CHECK: Vreg: %32[ 8 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %27[ 35 ]
+# CHECK: Vreg: %34[ 17 ]
+# CHECK: Vreg: %15[ 14 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+85 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %17:sub0[ 31 ]
+# CHECK: Vreg: %17:sub1[ 32 ]
+# CHECK: Instr: %75:sreg_32 = V_CMP_GE_U32_e64 %67, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %26[ 45 ]
+# CHECK: Vreg: %59:sub0[ 38 ]
+# CHECK: Vreg: %2[ 18 ]
+# CHECK: Vreg: %16[ 58 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+51 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+52 ]
+# CHECK: Vreg: %61[ 42 ]
+# CHECK: Vreg: %4[ LoopTag+57 ]
+# CHECK: Vreg: %49[ LoopTag+47 ]
+# CHECK: Vreg: %30[ LoopTag+58 ]
+# CHECK: Vreg: %18:sub0[ 49 ]
+# CHECK: Vreg: %18:sub1[ 50 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %32[ 7 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %27[ 34 ]
+# CHECK: Vreg: %34[ 16 ]
+# CHECK: Vreg: %15[ 13 ]
+# CHECK: Vreg: %3[ 41 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+84 ]
+# CHECK: Vreg: %17:sub0[ 30 ]
+# CHECK: Vreg: %17:sub1[ 31 ]
+# CHECK: Instr: %76:sreg_32 = SI_IF killed %75, %bb.11, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %26[ 44 ]
+# CHECK: Vreg: %59:sub0[ 37 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %16[ 57 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+50 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+51 ]
+# CHECK: Vreg: %61[ 41 ]
+# CHECK: Vreg: %4[ LoopTag+56 ]
+# CHECK: Vreg: %49[ LoopTag+46 ]
+# CHECK: Vreg: %30[ LoopTag+57 ]
+# CHECK: Vreg: %75[ 0 ]
+# CHECK: Vreg: %18:sub0[ 48 ]
+# CHECK: Vreg: %18:sub1[ 49 ]
+# CHECK: Vreg: %63[ 6 ]
+# CHECK: Vreg: %32[ 6 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %27[ 33 ]
+# CHECK: Vreg: %34[ 15 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %3[ 40 ]
+# CHECK: Vreg: %67[ 34 ]
+# CHECK: Vreg: %29[ LoopTag+83 ]
+# CHECK: Vreg: %17:sub0[ 29 ]
+# CHECK: Vreg: %17:sub1[ 30 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ 43 ]
+# CHECK: Vreg: %59:sub0[ 36 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %16[ 56 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+50 ]
+# CHECK: Vreg: %61[ 40 ]
+# CHECK: Vreg: %4[ LoopTag+55 ]
+# CHECK: Vreg: %49[ LoopTag+45 ]
+# CHECK: Vreg: %30[ LoopTag+56 ]
+# CHECK: Vreg: %18:sub0[ 47 ]
+# CHECK: Vreg: %18:sub1[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %32[ 5 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %27[ 32 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %15[ 11 ]
+# CHECK: Vreg: %3[ 39 ]
+# CHECK: Vreg: %67[ 33 ]
+# CHECK: Vreg: %29[ LoopTag+82 ]
+# CHECK: Vreg: %17:sub0[ 28 ]
+# CHECK: Vreg: %17:sub1[ 29 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ 43 ]
+# CHECK: Vreg: %59:sub0[ 36 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %16[ 56 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+50 ]
+# CHECK: Vreg: %61[ 40 ]
+# CHECK: Vreg: %4[ LoopTag+55 ]
+# CHECK: Vreg: %49[ LoopTag+45 ]
+# CHECK: Vreg: %30[ LoopTag+56 ]
+# CHECK: Vreg: %18:sub0[ 47 ]
+# CHECK: Vreg: %18:sub1[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %32[ 5 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %27[ 32 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %15[ 11 ]
+# CHECK: Vreg: %3[ 39 ]
+# CHECK: Vreg: %67[ 33 ]
+# CHECK: Vreg: %29[ LoopTag+82 ]
+# CHECK: Vreg: %17:sub0[ 28 ]
+# CHECK: Vreg: %17:sub1[ 29 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %77:sreg_32 = S_MOV_B32 19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %26[ 55 ]
+# CHECK: Vreg: %59:sub0[ 48 ]
+# CHECK: Vreg: %2[ 28 ]
+# CHECK: Vreg: %16[ 68 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+61 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+62 ]
+# CHECK: Vreg: %61[ 52 ]
+# CHECK: Vreg: %4[ LoopTag+67 ]
+# CHECK: Vreg: %49[ LoopTag+57 ]
+# CHECK: Vreg: %30[ LoopTag+68 ]
+# CHECK: Vreg: %18:sub0[ 59 ]
+# CHECK: Vreg: %18:sub1[ 60 ]
+# CHECK: Vreg: %63[ 17 ]
+# CHECK: Vreg: %32[ 17 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %27[ 44 ]
+# CHECK: Vreg: %34[ 26 ]
+# CHECK: Vreg: %15[ 23 ]
+# CHECK: Vreg: %3[ 51 ]
+# CHECK: Vreg: %67[ 45 ]
+# CHECK: Vreg: %29[ LoopTag+94 ]
+# CHECK: Vreg: %17:sub0[ 40 ]
+# CHECK: Vreg: %17:sub1[ 41 ]
+# CHECK: Vreg: %76[ 13 ]
+# CHECK: Instr: %78:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %26[ 54 ]
+# CHECK: Vreg: %59:sub0[ 47 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %16[ 67 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+60 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+61 ]
+# CHECK: Vreg: %61[ 51 ]
+# CHECK: Vreg: %4[ LoopTag+66 ]
+# CHECK: Vreg: %49[ LoopTag+56 ]
+# CHECK: Vreg: %30[ LoopTag+67 ]
+# CHECK: Vreg: %18:sub0[ 58 ]
+# CHECK: Vreg: %18:sub1[ 59 ]
+# CHECK: Vreg: %63[ 16 ]
+# CHECK: Vreg: %32[ 16 ]
+# CHECK: Vreg: %77[ 1 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %27[ 43 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %67[ 44 ]
+# CHECK: Vreg: %29[ LoopTag+93 ]
+# CHECK: Vreg: %17:sub0[ 39 ]
+# CHECK: Vreg: %17:sub1[ 40 ]
+# CHECK: Vreg: %76[ 12 ]
+# CHECK: Instr: S_BRANCH %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %26[ 53 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %59:sub0[ 46 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %16[ 66 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %61[ 50 ]
+# CHECK: Vreg: %4[ LoopTag+65 ]
+# CHECK: Vreg: %49[ LoopTag+55 ]
+# CHECK: Vreg: %30[ LoopTag+66 ]
+# CHECK: Vreg: %18:sub0[ 57 ]
+# CHECK: Vreg: %18:sub1[ 58 ]
+# CHECK: Vreg: %63[ 15 ]
+# CHECK: Vreg: %32[ 15 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %27[ 42 ]
+# CHECK: Vreg: %34[ 24 ]
+# CHECK: Vreg: %15[ 21 ]
+# CHECK: Vreg: %3[ 49 ]
+# CHECK: Vreg: %67[ 43 ]
+# CHECK: Vreg: %29[ LoopTag+92 ]
+# CHECK: Vreg: %17:sub0[ 38 ]
+# CHECK: Vreg: %17:sub1[ 39 ]
+# CHECK: Vreg: %76[ 11 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %26[ 53 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %59:sub0[ 46 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %16[ 66 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %61[ 50 ]
+# CHECK: Vreg: %4[ LoopTag+65 ]
+# CHECK: Vreg: %49[ LoopTag+55 ]
+# CHECK: Vreg: %30[ LoopTag+66 ]
+# CHECK: Vreg: %18:sub0[ 57 ]
+# CHECK: Vreg: %18:sub1[ 58 ]
+# CHECK: Vreg: %63[ 15 ]
+# CHECK: Vreg: %32[ 15 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %27[ 42 ]
+# CHECK: Vreg: %34[ 24 ]
+# CHECK: Vreg: %15[ 21 ]
+# CHECK: Vreg: %3[ 49 ]
+# CHECK: Vreg: %67[ 43 ]
+# CHECK: Vreg: %29[ LoopTag+92 ]
+# CHECK: Vreg: %17:sub0[ 38 ]
+# CHECK: Vreg: %17:sub1[ 39 ]
+# CHECK: Vreg: %76[ 11 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %79:sreg_32 = S_MOV_B32 9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %26[ 61 ]
+# CHECK: Vreg: %59:sub0[ 54 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %16[ 74 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+67 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+68 ]
+# CHECK: Vreg: %61[ 58 ]
+# CHECK: Vreg: %87[ 21 ]
+# CHECK: Vreg: %4[ LoopTag+73 ]
+# CHECK: Vreg: %49[ LoopTag+63 ]
+# CHECK: Vreg: %30[ LoopTag+74 ]
+# CHECK: Vreg: %18:sub0[ 65 ]
+# CHECK: Vreg: %18:sub1[ 66 ]
+# CHECK: Vreg: %63[ 2 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %1[ 77 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %27[ 50 ]
+# CHECK: Vreg: %34[ 11 ]
+# CHECK: Vreg: %15[ 8 ]
+# CHECK: Vreg: %3[ 57 ]
+# CHECK: Vreg: %67[ 51 ]
+# CHECK: Vreg: %29[ LoopTag+100 ]
+# CHECK: Vreg: %17:sub0[ 46 ]
+# CHECK: Vreg: %17:sub1[ 47 ]
+# CHECK: Instr: %80:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %26[ 60 ]
+# CHECK: Vreg: %59:sub0[ 53 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %16[ 73 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+66 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+67 ]
+# CHECK: Vreg: %61[ 57 ]
+# CHECK: Vreg: %87[ 20 ]
+# CHECK: Vreg: %4[ LoopTag+72 ]
+# CHECK: Vreg: %49[ LoopTag+62 ]
+# CHECK: Vreg: %30[ LoopTag+73 ]
+# CHECK: Vreg: %18:sub0[ 64 ]
+# CHECK: Vreg: %18:sub1[ 65 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %1[ 76 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %27[ 49 ]
+# CHECK: Vreg: %34[ 10 ]
+# CHECK: Vreg: %15[ 7 ]
+# CHECK: Vreg: %79[ 1 ]
+# CHECK: Vreg: %3[ 56 ]
+# CHECK: Vreg: %67[ 50 ]
+# CHECK: Vreg: %29[ LoopTag+99 ]
+# CHECK: Vreg: %17:sub0[ 45 ]
+# CHECK: Vreg: %17:sub1[ 46 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ 59 ]
+# CHECK: Vreg: %59:sub0[ 52 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %16[ 72 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+65 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+66 ]
+# CHECK: Vreg: %61[ 56 ]
+# CHECK: Vreg: %87[ 19 ]
+# CHECK: Vreg: %4[ LoopTag+71 ]
+# CHECK: Vreg: %49[ LoopTag+61 ]
+# CHECK: Vreg: %30[ LoopTag+72 ]
+# CHECK: Vreg: %18:sub0[ 63 ]
+# CHECK: Vreg: %18:sub1[ 64 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %80[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 75 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ 48 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %3[ 55 ]
+# CHECK: Vreg: %67[ 49 ]
+# CHECK: Vreg: %29[ LoopTag+98 ]
+# CHECK: Vreg: %17:sub0[ 44 ]
+# CHECK: Vreg: %17:sub1[ 45 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ 59 ]
+# CHECK: Vreg: %59:sub0[ 52 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %16[ 72 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+65 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+66 ]
+# CHECK: Vreg: %61[ 56 ]
+# CHECK: Vreg: %87[ 19 ]
+# CHECK: Vreg: %4[ LoopTag+71 ]
+# CHECK: Vreg: %49[ LoopTag+61 ]
+# CHECK: Vreg: %30[ LoopTag+72 ]
+# CHECK: Vreg: %18:sub0[ 63 ]
+# CHECK: Vreg: %18:sub1[ 64 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %80[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 75 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ 48 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %3[ 55 ]
+# CHECK: Vreg: %67[ 49 ]
+# CHECK: Vreg: %29[ LoopTag+98 ]
+# CHECK: Vreg: %17:sub0[ 44 ]
+# CHECK: Vreg: %17:sub1[ 45 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %81:vgpr_32 = PHI %82, %bb.11, %83, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 49 ]
+# CHECK: Vreg: %26[ 41 ]
+# CHECK: Vreg: %59:sub0[ 34 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %2[ 67 ]
+# CHECK: Vreg: %16[ 54 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+48 ]
+# CHECK: Vreg: %61[ 38 ]
+# CHECK: Vreg: %87[ 1 ]
+# CHECK: Vreg: %4[ LoopTag+53 ]
+# CHECK: Vreg: %49[ LoopTag+43 ]
+# CHECK: Vreg: %30[ LoopTag+54 ]
+# CHECK: Vreg: %18:sub0[ 45 ]
+# CHECK: Vreg: %18:sub1[ 46 ]
+# CHECK: Vreg: %63[ 36 ]
+# CHECK: Vreg: %82[ 0 ]
+# CHECK: Vreg: %32[ 56 ]
+# CHECK: Vreg: %1[ 57 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ 30 ]
+# CHECK: Vreg: %34[ 35 ]
+# CHECK: Vreg: %15[ 62 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 37 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %29[ LoopTag+80 ]
+# CHECK: Vreg: %17:sub0[ 26 ]
+# CHECK: Vreg: %17:sub1[ 27 ]
+# CHECK: Vreg: %83[ 0 ]
+# CHECK: Instr: %84:vgpr_32 = PHI %85, %bb.11, %86, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 49 ]
+# CHECK: Vreg: %26[ 41 ]
+# CHECK: Vreg: %59:sub0[ 34 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %2[ 67 ]
+# CHECK: Vreg: %16[ 54 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+48 ]
+# CHECK: Vreg: %61[ 38 ]
+# CHECK: Vreg: %87[ 1 ]
+# CHECK: Vreg: %4[ LoopTag+53 ]
+# CHECK: Vreg: %49[ LoopTag+43 ]
+# CHECK: Vreg: %30[ LoopTag+54 ]
+# CHECK: Vreg: %18:sub0[ 45 ]
+# CHECK: Vreg: %18:sub1[ 46 ]
+# CHECK: Vreg: %63[ 36 ]
+# CHECK: Vreg: %32[ 56 ]
+# CHECK: Vreg: %1[ 57 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ 30 ]
+# CHECK: Vreg: %34[ 35 ]
+# CHECK: Vreg: %15[ 62 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 37 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %29[ LoopTag+80 ]
+# CHECK: Vreg: %17:sub0[ 26 ]
+# CHECK: Vreg: %17:sub1[ 27 ]
+# CHECK: Vreg: %81[ 30 ]
+# CHECK: Instr: SI_END_CF killed %87, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 48 ]
+# CHECK: Vreg: %26[ 40 ]
+# CHECK: Vreg: %59:sub0[ 33 ]
+# CHECK: Vreg: %2[ 66 ]
+# CHECK: Vreg: %16[ 53 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+47 ]
+# CHECK: Vreg: %61[ 37 ]
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Vreg: %4[ LoopTag+52 ]
+# CHECK: Vreg: %49[ LoopTag+42 ]
+# CHECK: Vreg: %30[ LoopTag+53 ]
+# CHECK: Vreg: %18:sub0[ 44 ]
+# CHECK: Vreg: %18:sub1[ 45 ]
+# CHECK: Vreg: %63[ 35 ]
+# CHECK: Vreg: %32[ 55 ]
+# CHECK: Vreg: %84[ 11 ]
+# CHECK: Vreg: %1[ 56 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ 29 ]
+# CHECK: Vreg: %34[ 34 ]
+# CHECK: Vreg: %15[ 61 ]
+# CHECK: Vreg: %3[ 36 ]
+# CHECK: Vreg: %67[ 30 ]
+# CHECK: Vreg: %29[ LoopTag+79 ]
+# CHECK: Vreg: %17:sub0[ 25 ]
+# CHECK: Vreg: %17:sub1[ 26 ]
+# CHECK: Vreg: %81[ 29 ]
+# CHECK: Instr: S_BRANCH %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %26[ 39 ]
+# CHECK: Vreg: %59:sub0[ 32 ]
+# CHECK: Vreg: %2[ 65 ]
+# CHECK: Vreg: %16[ 52 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+46 ]
+# CHECK: Vreg: %61[ 36 ]
+# CHECK: Vreg: %4[ LoopTag+51 ]
+# CHECK: Vreg: %49[ LoopTag+41 ]
+# CHECK: Vreg: %30[ LoopTag+52 ]
+# CHECK: Vreg: %18:sub0[ 43 ]
+# CHECK: Vreg: %18:sub1[ 44 ]
+# CHECK: Vreg: %63[ 34 ]
+# CHECK: Vreg: %32[ 54 ]
+# CHECK: Vreg: %84[ 10 ]
+# CHECK: Vreg: %1[ 55 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %27[ 28 ]
+# CHECK: Vreg: %34[ 33 ]
+# CHECK: Vreg: %15[ 60 ]
+# CHECK: Vreg: %3[ 35 ]
+# CHECK: Vreg: %67[ 29 ]
+# CHECK: Vreg: %29[ LoopTag+78 ]
+# CHECK: Vreg: %17:sub0[ 24 ]
+# CHECK: Vreg: %17:sub1[ 25 ]
+# CHECK: Vreg: %81[ 28 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %26[ 39 ]
+# CHECK: Vreg: %59:sub0[ 32 ]
+# CHECK: Vreg: %2[ 65 ]
+# CHECK: Vreg: %16[ 52 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+46 ]
+# CHECK: Vreg: %61[ 36 ]
+# CHECK: Vreg: %4[ LoopTag+51 ]
+# CHECK: Vreg: %49[ LoopTag+41 ]
+# CHECK: Vreg: %30[ LoopTag+52 ]
+# CHECK: Vreg: %18:sub0[ 43 ]
+# CHECK: Vreg: %18:sub1[ 44 ]
+# CHECK: Vreg: %63[ 34 ]
+# CHECK: Vreg: %32[ 54 ]
+# CHECK: Vreg: %84[ 10 ]
+# CHECK: Vreg: %1[ 55 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %27[ 28 ]
+# CHECK: Vreg: %34[ 33 ]
+# CHECK: Vreg: %15[ 60 ]
+# CHECK: Vreg: %3[ 35 ]
+# CHECK: Vreg: %67[ 29 ]
+# CHECK: Vreg: %29[ LoopTag+78 ]
+# CHECK: Vreg: %17:sub0[ 24 ]
+# CHECK: Vreg: %17:sub1[ 25 ]
+# CHECK: Vreg: %81[ 28 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %88:sreg_32 = PHI %80, %bb.4, %89, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ LoopTag+59 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+52 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %16[ LoopTag+72 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+65 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+66 ]
+# CHECK: Vreg: %61[ LoopTag+56 ]
+# CHECK: Vreg: %87[ LoopTag+19 ]
+# CHECK: Vreg: %4[ LoopTag*2+71 ]
+# CHECK: Vreg: %49[ LoopTag*2+61 ]
+# CHECK: Vreg: %30[ LoopTag*2+72 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+63 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+64 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %80[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+75 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ LoopTag+48 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+55 ]
+# CHECK: Vreg: %67[ LoopTag+49 ]
+# CHECK: Vreg: %29[ LoopTag*2+98 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+45 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Instr: %90:sreg_32 = PHI %63, %bb.4, %91, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ LoopTag+59 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+52 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %16[ LoopTag+72 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+65 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+66 ]
+# CHECK: Vreg: %61[ LoopTag+56 ]
+# CHECK: Vreg: %87[ LoopTag+19 ]
+# CHECK: Vreg: %4[ LoopTag*2+71 ]
+# CHECK: Vreg: %49[ LoopTag*2+61 ]
+# CHECK: Vreg: %30[ LoopTag*2+72 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+63 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+64 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+75 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ LoopTag+48 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+55 ]
+# CHECK: Vreg: %67[ LoopTag+49 ]
+# CHECK: Vreg: %29[ LoopTag*2+98 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 12 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Instr: %92:sreg_32 = PHI %32, %bb.4, %93, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ LoopTag+59 ]
+# CHECK: Vreg: %90[ 7 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+52 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %16[ LoopTag+72 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+65 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+66 ]
+# CHECK: Vreg: %61[ LoopTag+56 ]
+# CHECK: Vreg: %87[ LoopTag+19 ]
+# CHECK: Vreg: %4[ LoopTag*2+71 ]
+# CHECK: Vreg: %49[ LoopTag*2+61 ]
+# CHECK: Vreg: %30[ LoopTag*2+72 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+63 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+64 ]
+# CHECK: Vreg: %63[ LoopTag+54 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+75 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ LoopTag+48 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+55 ]
+# CHECK: Vreg: %67[ LoopTag+49 ]
+# CHECK: Vreg: %29[ LoopTag*2+98 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 12 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Instr: %94:sreg_32 = PHI %79, %bb.4, %95, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ LoopTag+59 ]
+# CHECK: Vreg: %90[ 7 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+52 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %16[ LoopTag+72 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+65 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+66 ]
+# CHECK: Vreg: %61[ LoopTag+56 ]
+# CHECK: Vreg: %87[ LoopTag+19 ]
+# CHECK: Vreg: %4[ LoopTag*2+71 ]
+# CHECK: Vreg: %49[ LoopTag*2+61 ]
+# CHECK: Vreg: %30[ LoopTag*2+72 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+63 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+64 ]
+# CHECK: Vreg: %63[ LoopTag+54 ]
+# CHECK: Vreg: %32[ LoopTag+74 ]
+# CHECK: Vreg: %1[ LoopTag+75 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ LoopTag+48 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+55 ]
+# CHECK: Vreg: %67[ LoopTag+49 ]
+# CHECK: Vreg: %29[ LoopTag*2+98 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 12 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Instr: %95:sreg_32 = S_ADD_I32 killed %94, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %26[ LoopTag+58 ]
+# CHECK: Vreg: %90[ 6 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+51 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %92[ 4 ]
+# CHECK: Vreg: %16[ LoopTag+71 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+64 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+65 ]
+# CHECK: Vreg: %61[ LoopTag+55 ]
+# CHECK: Vreg: %87[ LoopTag+18 ]
+# CHECK: Vreg: %4[ LoopTag*2+70 ]
+# CHECK: Vreg: %49[ LoopTag*2+60 ]
+# CHECK: Vreg: %30[ LoopTag*2+71 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+62 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+63 ]
+# CHECK: Vreg: %63[ LoopTag+53 ]
+# CHECK: Vreg: %32[ LoopTag+73 ]
+# CHECK: Vreg: %1[ LoopTag+74 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %27[ LoopTag+47 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %3[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+48 ]
+# CHECK: Vreg: %29[ LoopTag*2+97 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 11 ]
+# CHECK: Instr: %96:sreg_32 = V_CMP_GE_U32_e64 %95, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %26[ LoopTag+57 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+50 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %92[ 3 ]
+# CHECK: Vreg: %16[ LoopTag+70 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+63 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+64 ]
+# CHECK: Vreg: %61[ LoopTag+54 ]
+# CHECK: Vreg: %87[ LoopTag+17 ]
+# CHECK: Vreg: %4[ LoopTag*2+69 ]
+# CHECK: Vreg: %49[ LoopTag*2+59 ]
+# CHECK: Vreg: %30[ LoopTag*2+70 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+61 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+62 ]
+# CHECK: Vreg: %63[ LoopTag+52 ]
+# CHECK: Vreg: %32[ LoopTag+72 ]
+# CHECK: Vreg: %1[ LoopTag+73 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %27[ LoopTag+46 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %3[ LoopTag+53 ]
+# CHECK: Vreg: %67[ LoopTag+47 ]
+# CHECK: Vreg: %29[ LoopTag*2+96 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+43 ]
+# CHECK: Vreg: %88[ 10 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Instr: %97:sreg_32 = SI_IF killed %96, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %26[ LoopTag+56 ]
+# CHECK: Vreg: %90[ 4 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %16[ LoopTag+69 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+62 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+63 ]
+# CHECK: Vreg: %61[ LoopTag+53 ]
+# CHECK: Vreg: %87[ LoopTag+16 ]
+# CHECK: Vreg: %4[ LoopTag*2+68 ]
+# CHECK: Vreg: %49[ LoopTag*2+58 ]
+# CHECK: Vreg: %30[ LoopTag*2+69 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+60 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+61 ]
+# CHECK: Vreg: %63[ LoopTag+51 ]
+# CHECK: Vreg: %32[ LoopTag+71 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+72 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %27[ LoopTag+45 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %3[ LoopTag+52 ]
+# CHECK: Vreg: %67[ LoopTag+46 ]
+# CHECK: Vreg: %29[ LoopTag*2+95 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+42 ]
+# CHECK: Vreg: %88[ 9 ]
+# CHECK: Vreg: %95[ 5 ]
+# CHECK: Instr: S_BRANCH %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ LoopTag+55 ]
+# CHECK: Vreg: %90[ 3 ]
+# CHECK: Vreg: %97[ 1 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %92[ 1 ]
+# CHECK: Vreg: %16[ LoopTag+68 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+61 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+62 ]
+# CHECK: Vreg: %61[ LoopTag+52 ]
+# CHECK: Vreg: %87[ LoopTag+15 ]
+# CHECK: Vreg: %4[ LoopTag*2+67 ]
+# CHECK: Vreg: %49[ LoopTag*2+57 ]
+# CHECK: Vreg: %30[ LoopTag*2+68 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %63[ LoopTag+50 ]
+# CHECK: Vreg: %32[ LoopTag+70 ]
+# CHECK: Vreg: %1[ LoopTag+71 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %27[ LoopTag+44 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %3[ LoopTag+51 ]
+# CHECK: Vreg: %67[ LoopTag+45 ]
+# CHECK: Vreg: %29[ LoopTag*2+94 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 8 ]
+# CHECK: Vreg: %95[ 4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ LoopTag+55 ]
+# CHECK: Vreg: %90[ 3 ]
+# CHECK: Vreg: %97[ 1 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %92[ 1 ]
+# CHECK: Vreg: %16[ LoopTag+68 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+61 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+62 ]
+# CHECK: Vreg: %61[ LoopTag+52 ]
+# CHECK: Vreg: %87[ LoopTag+15 ]
+# CHECK: Vreg: %4[ LoopTag*2+67 ]
+# CHECK: Vreg: %49[ LoopTag*2+57 ]
+# CHECK: Vreg: %30[ LoopTag*2+68 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %63[ LoopTag+50 ]
+# CHECK: Vreg: %32[ LoopTag+70 ]
+# CHECK: Vreg: %1[ LoopTag+71 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %27[ LoopTag+44 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %3[ LoopTag+51 ]
+# CHECK: Vreg: %67[ LoopTag+45 ]
+# CHECK: Vreg: %29[ LoopTag*2+94 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 8 ]
+# CHECK: Vreg: %95[ 4 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: %98:sreg_32 = SI_ELSE killed %97, %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ LoopTag+54 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %92[ 4 ]
+# CHECK: Vreg: %16[ LoopTag+67 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+60 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+61 ]
+# CHECK: Vreg: %61[ LoopTag+51 ]
+# CHECK: Vreg: %87[ LoopTag+14 ]
+# CHECK: Vreg: %4[ LoopTag*2+66 ]
+# CHECK: Vreg: %49[ LoopTag*2+56 ]
+# CHECK: Vreg: %30[ LoopTag*2+67 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %63[ LoopTag+49 ]
+# CHECK: Vreg: %32[ LoopTag+69 ]
+# CHECK: Vreg: %1[ LoopTag+70 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %27[ LoopTag+43 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %3[ LoopTag+50 ]
+# CHECK: Vreg: %67[ LoopTag+44 ]
+# CHECK: Vreg: %29[ LoopTag*2+93 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+39 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+40 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %95[ 3 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %26[ LoopTag+53 ]
+# CHECK: Vreg: %90[ 1 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %92[ 3 ]
+# CHECK: Vreg: %16[ LoopTag+66 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+59 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+60 ]
+# CHECK: Vreg: %61[ LoopTag+50 ]
+# CHECK: Vreg: %87[ LoopTag+13 ]
+# CHECK: Vreg: %4[ LoopTag*2+65 ]
+# CHECK: Vreg: %49[ LoopTag*2+55 ]
+# CHECK: Vreg: %30[ LoopTag*2+66 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %63[ LoopTag+48 ]
+# CHECK: Vreg: %32[ LoopTag+68 ]
+# CHECK: Vreg: %1[ LoopTag+69 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %27[ LoopTag+42 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %3[ LoopTag+49 ]
+# CHECK: Vreg: %67[ LoopTag+43 ]
+# CHECK: Vreg: %29[ LoopTag*2+92 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %26[ LoopTag+53 ]
+# CHECK: Vreg: %90[ 1 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %92[ 3 ]
+# CHECK: Vreg: %16[ LoopTag+66 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+59 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+60 ]
+# CHECK: Vreg: %61[ LoopTag+50 ]
+# CHECK: Vreg: %87[ LoopTag+13 ]
+# CHECK: Vreg: %4[ LoopTag*2+65 ]
+# CHECK: Vreg: %49[ LoopTag*2+55 ]
+# CHECK: Vreg: %30[ LoopTag*2+66 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %63[ LoopTag+48 ]
+# CHECK: Vreg: %32[ LoopTag+68 ]
+# CHECK: Vreg: %1[ LoopTag+69 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %27[ LoopTag+42 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %3[ LoopTag+49 ]
+# CHECK: Vreg: %67[ LoopTag+43 ]
+# CHECK: Vreg: %29[ LoopTag*2+92 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: %99:vgpr_32 = COPY %90
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ LoopTag+55 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %16[ LoopTag+68 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+61 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+62 ]
+# CHECK: Vreg: %61[ LoopTag+52 ]
+# CHECK: Vreg: %87[ LoopTag+15 ]
+# CHECK: Vreg: %4[ LoopTag*2+67 ]
+# CHECK: Vreg: %49[ LoopTag*2+57 ]
+# CHECK: Vreg: %30[ LoopTag*2+68 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %63[ LoopTag+50 ]
+# CHECK: Vreg: %32[ LoopTag+70 ]
+# CHECK: Vreg: %1[ LoopTag+71 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %27[ LoopTag+44 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %98[ 3 ]
+# CHECK: Vreg: %3[ LoopTag+51 ]
+# CHECK: Vreg: %67[ LoopTag+45 ]
+# CHECK: Vreg: %29[ LoopTag*2+94 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 8 ]
+# CHECK: Vreg: %95[ 4 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %15, killed %99, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ LoopTag+54 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %92[ 4 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %16[ LoopTag+67 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+60 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+61 ]
+# CHECK: Vreg: %61[ LoopTag+51 ]
+# CHECK: Vreg: %87[ LoopTag+14 ]
+# CHECK: Vreg: %4[ LoopTag*2+66 ]
+# CHECK: Vreg: %49[ LoopTag*2+56 ]
+# CHECK: Vreg: %30[ LoopTag*2+67 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %63[ LoopTag+49 ]
+# CHECK: Vreg: %32[ LoopTag+69 ]
+# CHECK: Vreg: %1[ LoopTag+70 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %27[ LoopTag+43 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %98[ 2 ]
+# CHECK: Vreg: %3[ LoopTag+50 ]
+# CHECK: Vreg: %67[ LoopTag+44 ]
+# CHECK: Vreg: %29[ LoopTag*2+93 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+39 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+40 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %95[ 3 ]
+# CHECK: Instr: S_BRANCH %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %26[ LoopTag+53 ]
+# CHECK: Vreg: %90[ 4 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %92[ 3 ]
+# CHECK: Vreg: %16[ LoopTag+66 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+59 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+60 ]
+# CHECK: Vreg: %61[ LoopTag+50 ]
+# CHECK: Vreg: %87[ LoopTag+13 ]
+# CHECK: Vreg: %4[ LoopTag*2+65 ]
+# CHECK: Vreg: %49[ LoopTag*2+55 ]
+# CHECK: Vreg: %30[ LoopTag*2+66 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %63[ LoopTag+48 ]
+# CHECK: Vreg: %32[ LoopTag+68 ]
+# CHECK: Vreg: %1[ LoopTag+69 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %27[ LoopTag+42 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %15[ 16 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %3[ LoopTag+49 ]
+# CHECK: Vreg: %67[ LoopTag+43 ]
+# CHECK: Vreg: %29[ LoopTag*2+92 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %26[ LoopTag+53 ]
+# CHECK: Vreg: %90[ 4 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %92[ 3 ]
+# CHECK: Vreg: %16[ LoopTag+66 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+59 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+60 ]
+# CHECK: Vreg: %61[ LoopTag+50 ]
+# CHECK: Vreg: %87[ LoopTag+13 ]
+# CHECK: Vreg: %4[ LoopTag*2+65 ]
+# CHECK: Vreg: %49[ LoopTag*2+55 ]
+# CHECK: Vreg: %30[ LoopTag*2+66 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %63[ LoopTag+48 ]
+# CHECK: Vreg: %32[ LoopTag+68 ]
+# CHECK: Vreg: %1[ LoopTag+69 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %27[ LoopTag+42 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %15[ 16 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %3[ LoopTag+49 ]
+# CHECK: Vreg: %67[ LoopTag+43 ]
+# CHECK: Vreg: %29[ LoopTag*2+92 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: --- MBB_9 ---
+# CHECK: Instr: %100:vgpr_32 = COPY %92
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ LoopTag+57 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %97[ 3 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+50 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %16[ LoopTag+70 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+63 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+64 ]
+# CHECK: Vreg: %61[ LoopTag+54 ]
+# CHECK: Vreg: %87[ LoopTag+17 ]
+# CHECK: Vreg: %4[ LoopTag*2+69 ]
+# CHECK: Vreg: %49[ LoopTag*2+59 ]
+# CHECK: Vreg: %30[ LoopTag*2+70 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+61 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+62 ]
+# CHECK: Vreg: %63[ LoopTag+52 ]
+# CHECK: Vreg: %32[ LoopTag+72 ]
+# CHECK: Vreg: %1[ LoopTag+73 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %27[ LoopTag+46 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %3[ LoopTag+53 ]
+# CHECK: Vreg: %67[ LoopTag+47 ]
+# CHECK: Vreg: %29[ LoopTag*2+96 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+43 ]
+# CHECK: Vreg: %88[ 10 ]
+# CHECK: Vreg: %95[ 6 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %15, killed %100, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %26[ LoopTag+56 ]
+# CHECK: Vreg: %90[ 4 ]
+# CHECK: Vreg: %97[ 2 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %92[ 6 ]
+# CHECK: Vreg: %16[ LoopTag+69 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+62 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+63 ]
+# CHECK: Vreg: %61[ LoopTag+53 ]
+# CHECK: Vreg: %87[ LoopTag+16 ]
+# CHECK: Vreg: %4[ LoopTag*2+68 ]
+# CHECK: Vreg: %49[ LoopTag*2+58 ]
+# CHECK: Vreg: %30[ LoopTag*2+69 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+60 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+61 ]
+# CHECK: Vreg: %63[ LoopTag+51 ]
+# CHECK: Vreg: %32[ LoopTag+71 ]
+# CHECK: Vreg: %1[ LoopTag+72 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %27[ LoopTag+45 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+52 ]
+# CHECK: Vreg: %67[ LoopTag+46 ]
+# CHECK: Vreg: %29[ LoopTag*2+95 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+42 ]
+# CHECK: Vreg: %88[ 9 ]
+# CHECK: Vreg: %95[ 5 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ LoopTag+55 ]
+# CHECK: Vreg: %90[ 3 ]
+# CHECK: Vreg: %97[ 1 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %16[ LoopTag+68 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+61 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+62 ]
+# CHECK: Vreg: %61[ LoopTag+52 ]
+# CHECK: Vreg: %87[ LoopTag+15 ]
+# CHECK: Vreg: %4[ LoopTag*2+67 ]
+# CHECK: Vreg: %49[ LoopTag*2+57 ]
+# CHECK: Vreg: %30[ LoopTag*2+68 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %63[ LoopTag+50 ]
+# CHECK: Vreg: %32[ LoopTag+70 ]
+# CHECK: Vreg: %1[ LoopTag+71 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %27[ LoopTag+44 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %3[ LoopTag+51 ]
+# CHECK: Vreg: %67[ LoopTag+45 ]
+# CHECK: Vreg: %29[ LoopTag*2+94 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 8 ]
+# CHECK: Vreg: %95[ 4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ LoopTag+55 ]
+# CHECK: Vreg: %90[ 3 ]
+# CHECK: Vreg: %97[ 1 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %16[ LoopTag+68 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+61 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+62 ]
+# CHECK: Vreg: %61[ LoopTag+52 ]
+# CHECK: Vreg: %87[ LoopTag+15 ]
+# CHECK: Vreg: %4[ LoopTag*2+67 ]
+# CHECK: Vreg: %49[ LoopTag*2+57 ]
+# CHECK: Vreg: %30[ LoopTag*2+68 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %63[ LoopTag+50 ]
+# CHECK: Vreg: %32[ LoopTag+70 ]
+# CHECK: Vreg: %1[ LoopTag+71 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %27[ LoopTag+44 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %3[ LoopTag+51 ]
+# CHECK: Vreg: %67[ LoopTag+45 ]
+# CHECK: Vreg: %29[ LoopTag*2+94 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 8 ]
+# CHECK: Vreg: %95[ 4 ]
+# CHECK: --- MBB_10 ---
+# CHECK: Instr: SI_END_CF killed %98, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %26[ LoopTag+52 ]
+# CHECK: Vreg: %90[ 3 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %16[ LoopTag+65 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+58 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+59 ]
+# CHECK: Vreg: %61[ LoopTag+49 ]
+# CHECK: Vreg: %87[ LoopTag+12 ]
+# CHECK: Vreg: %4[ LoopTag*2+64 ]
+# CHECK: Vreg: %49[ LoopTag*2+54 ]
+# CHECK: Vreg: %30[ LoopTag*2+65 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+56 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+57 ]
+# CHECK: Vreg: %63[ LoopTag+47 ]
+# CHECK: Vreg: %32[ LoopTag+67 ]
+# CHECK: Vreg: %1[ LoopTag+68 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ LoopTag+41 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %15[ 15 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+48 ]
+# CHECK: Vreg: %67[ LoopTag+42 ]
+# CHECK: Vreg: %29[ LoopTag*2+91 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %88[ 5 ]
+# CHECK: Vreg: %95[ 1 ]
+# CHECK: Instr: %101:sreg_32 = S_ADD_I32 %95, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %26[ LoopTag+51 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %92[ 1 ]
+# CHECK: Vreg: %16[ LoopTag+64 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+57 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+58 ]
+# CHECK: Vreg: %61[ LoopTag+48 ]
+# CHECK: Vreg: %87[ LoopTag+11 ]
+# CHECK: Vreg: %4[ LoopTag*2+63 ]
+# CHECK: Vreg: %49[ LoopTag*2+53 ]
+# CHECK: Vreg: %30[ LoopTag*2+64 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %63[ LoopTag+46 ]
+# CHECK: Vreg: %32[ LoopTag+66 ]
+# CHECK: Vreg: %1[ LoopTag+67 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ LoopTag+40 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 14 ]
+# CHECK: Vreg: %3[ LoopTag+47 ]
+# CHECK: Vreg: %67[ LoopTag+41 ]
+# CHECK: Vreg: %29[ LoopTag*2+90 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+36 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+37 ]
+# CHECK: Vreg: %88[ 4 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Instr: %93:sreg_32 = S_ADD_I32 killed %92, %34, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %26[ LoopTag+50 ]
+# CHECK: Vreg: %90[ 1 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %16[ LoopTag+63 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+56 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+57 ]
+# CHECK: Vreg: %61[ LoopTag+47 ]
+# CHECK: Vreg: %87[ LoopTag+10 ]
+# CHECK: Vreg: %4[ LoopTag*2+62 ]
+# CHECK: Vreg: %49[ LoopTag*2+52 ]
+# CHECK: Vreg: %30[ LoopTag*2+63 ]
+# CHECK: Vreg: %101[ 2 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+54 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+55 ]
+# CHECK: Vreg: %63[ LoopTag+45 ]
+# CHECK: Vreg: %32[ LoopTag+65 ]
+# CHECK: Vreg: %1[ LoopTag+66 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %27[ LoopTag+39 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 13 ]
+# CHECK: Vreg: %3[ LoopTag+46 ]
+# CHECK: Vreg: %67[ LoopTag+40 ]
+# CHECK: Vreg: %29[ LoopTag*2+89 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+35 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+36 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %95[ 5 ]
+# CHECK: Instr: %91:sreg_32 = S_ADD_I32 killed %90, %65, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %26[ LoopTag+49 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %16[ LoopTag+62 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+55 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+56 ]
+# CHECK: Vreg: %61[ LoopTag+46 ]
+# CHECK: Vreg: %87[ LoopTag+9 ]
+# CHECK: Vreg: %4[ LoopTag*2+61 ]
+# CHECK: Vreg: %49[ LoopTag*2+51 ]
+# CHECK: Vreg: %30[ LoopTag*2+62 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %63[ LoopTag+44 ]
+# CHECK: Vreg: %32[ LoopTag+64 ]
+# CHECK: Vreg: %1[ LoopTag+65 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ LoopTag+38 ]
+# CHECK: Vreg: %34[ 15 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %3[ LoopTag+45 ]
+# CHECK: Vreg: %67[ LoopTag+39 ]
+# CHECK: Vreg: %29[ LoopTag*2+88 ]
+# CHECK: Vreg: %93[ 6 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+34 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+35 ]
+# CHECK: Vreg: %88[ 2 ]
+# CHECK: Vreg: %95[ 4 ]
+# CHECK: Instr: %102:sreg_32 = V_CMP_GE_U32_e64 %101, %2, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ LoopTag+48 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %16[ LoopTag+61 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+54 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+55 ]
+# CHECK: Vreg: %61[ LoopTag+45 ]
+# CHECK: Vreg: %87[ LoopTag+8 ]
+# CHECK: Vreg: %4[ LoopTag*2+60 ]
+# CHECK: Vreg: %49[ LoopTag*2+50 ]
+# CHECK: Vreg: %30[ LoopTag*2+61 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+52 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+53 ]
+# CHECK: Vreg: %63[ LoopTag+43 ]
+# CHECK: Vreg: %32[ LoopTag+63 ]
+# CHECK: Vreg: %1[ LoopTag+64 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %27[ LoopTag+37 ]
+# CHECK: Vreg: %91[ 5 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %15[ 11 ]
+# CHECK: Vreg: %3[ LoopTag+44 ]
+# CHECK: Vreg: %67[ LoopTag+38 ]
+# CHECK: Vreg: %29[ LoopTag*2+87 ]
+# CHECK: Vreg: %93[ 5 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+33 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+34 ]
+# CHECK: Vreg: %88[ 1 ]
+# CHECK: Vreg: %95[ 3 ]
+# CHECK: Instr: %89:sreg_32 = SI_IF_BREAK killed %102, killed %88, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %26[ LoopTag+47 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %16[ LoopTag+60 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+53 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+54 ]
+# CHECK: Vreg: %61[ LoopTag+44 ]
+# CHECK: Vreg: %87[ LoopTag+7 ]
+# CHECK: Vreg: %4[ LoopTag*2+59 ]
+# CHECK: Vreg: %49[ LoopTag*2+49 ]
+# CHECK: Vreg: %30[ LoopTag*2+60 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+51 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+52 ]
+# CHECK: Vreg: %63[ LoopTag+42 ]
+# CHECK: Vreg: %32[ LoopTag+62 ]
+# CHECK: Vreg: %1[ LoopTag+63 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %27[ LoopTag+36 ]
+# CHECK: Vreg: %91[ 4 ]
+# CHECK: Vreg: %34[ 13 ]
+# CHECK: Vreg: %15[ 10 ]
+# CHECK: Vreg: %3[ LoopTag+43 ]
+# CHECK: Vreg: %67[ LoopTag+37 ]
+# CHECK: Vreg: %29[ LoopTag*2+86 ]
+# CHECK: Vreg: %93[ 4 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+32 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+33 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: %83:vgpr_32 = COPY killed %101, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %26[ LoopTag+46 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+39 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %16[ LoopTag+59 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+52 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+53 ]
+# CHECK: Vreg: %61[ LoopTag+43 ]
+# CHECK: Vreg: %87[ LoopTag+6 ]
+# CHECK: Vreg: %4[ LoopTag*2+58 ]
+# CHECK: Vreg: %49[ LoopTag*2+48 ]
+# CHECK: Vreg: %30[ LoopTag*2+59 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+50 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+51 ]
+# CHECK: Vreg: %63[ LoopTag+41 ]
+# CHECK: Vreg: %89[ 2 ]
+# CHECK: Vreg: %32[ LoopTag+61 ]
+# CHECK: Vreg: %1[ LoopTag+62 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %27[ LoopTag+35 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %34[ 12 ]
+# CHECK: Vreg: %15[ 9 ]
+# CHECK: Vreg: %3[ LoopTag+42 ]
+# CHECK: Vreg: %67[ LoopTag+36 ]
+# CHECK: Vreg: %29[ LoopTag*2+85 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+31 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+32 ]
+# CHECK: Vreg: %95[ 1 ]
+# CHECK: Instr: %86:vgpr_32 = COPY %95, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %26[ LoopTag+45 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %16[ LoopTag+58 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+51 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+52 ]
+# CHECK: Vreg: %61[ LoopTag+42 ]
+# CHECK: Vreg: %87[ LoopTag+5 ]
+# CHECK: Vreg: %4[ LoopTag*2+57 ]
+# CHECK: Vreg: %49[ LoopTag*2+47 ]
+# CHECK: Vreg: %30[ LoopTag*2+58 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+50 ]
+# CHECK: Vreg: %63[ LoopTag+40 ]
+# CHECK: Vreg: %89[ 1 ]
+# CHECK: Vreg: %32[ LoopTag+60 ]
+# CHECK: Vreg: %1[ LoopTag+61 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %27[ LoopTag+34 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %34[ 11 ]
+# CHECK: Vreg: %15[ 8 ]
+# CHECK: Vreg: %3[ LoopTag+41 ]
+# CHECK: Vreg: %67[ LoopTag+35 ]
+# CHECK: Vreg: %29[ LoopTag*2+84 ]
+# CHECK: Vreg: %93[ 2 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+30 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+31 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %83[ LoopTag+4 ]
+# CHECK: Instr: SI_LOOP %89, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %26[ LoopTag+44 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %16[ LoopTag+57 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+50 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+51 ]
+# CHECK: Vreg: %61[ LoopTag+41 ]
+# CHECK: Vreg: %87[ LoopTag+4 ]
+# CHECK: Vreg: %4[ LoopTag*2+56 ]
+# CHECK: Vreg: %49[ LoopTag*2+46 ]
+# CHECK: Vreg: %30[ LoopTag*2+57 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+49 ]
+# CHECK: Vreg: %63[ LoopTag+39 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+59 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %27[ LoopTag+33 ]
+# CHECK: Vreg: %91[ 1 ]
+# CHECK: Vreg: %34[ 10 ]
+# CHECK: Vreg: %15[ 7 ]
+# CHECK: Vreg: %86[ LoopTag+3 ]
+# CHECK: Vreg: %3[ LoopTag+40 ]
+# CHECK: Vreg: %67[ LoopTag+34 ]
+# CHECK: Vreg: %29[ LoopTag*2+83 ]
+# CHECK: Vreg: %93[ 1 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+29 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+30 ]
+# CHECK: Vreg: %95[ 1 ]
+# CHECK: Vreg: %83[ LoopTag+3 ]
+# CHECK: Instr: S_BRANCH %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ LoopTag+43 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+36 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %16[ LoopTag+56 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+49 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+50 ]
+# CHECK: Vreg: %61[ LoopTag+40 ]
+# CHECK: Vreg: %87[ LoopTag+3 ]
+# CHECK: Vreg: %4[ LoopTag*2+55 ]
+# CHECK: Vreg: %49[ LoopTag*2+45 ]
+# CHECK: Vreg: %30[ LoopTag*2+56 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+48 ]
+# CHECK: Vreg: %63[ LoopTag+38 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+58 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ LoopTag+32 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %86[ LoopTag+2 ]
+# CHECK: Vreg: %3[ LoopTag+39 ]
+# CHECK: Vreg: %67[ LoopTag+33 ]
+# CHECK: Vreg: %29[ LoopTag*2+82 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+28 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+29 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %83[ LoopTag+2 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ LoopTag+43 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+36 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %16[ LoopTag+56 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+49 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+50 ]
+# CHECK: Vreg: %61[ LoopTag+40 ]
+# CHECK: Vreg: %87[ LoopTag+3 ]
+# CHECK: Vreg: %4[ LoopTag*2+55 ]
+# CHECK: Vreg: %49[ LoopTag*2+45 ]
+# CHECK: Vreg: %30[ LoopTag*2+56 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+48 ]
+# CHECK: Vreg: %63[ LoopTag+38 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+58 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ LoopTag+32 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %86[ LoopTag+2 ]
+# CHECK: Vreg: %3[ LoopTag+39 ]
+# CHECK: Vreg: %67[ LoopTag+33 ]
+# CHECK: Vreg: %29[ LoopTag*2+82 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+28 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+29 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %83[ LoopTag+2 ]
+# CHECK: --- MBB_11 ---
+# CHECK: Instr: %82:vgpr_32 = PHI undef %103:vgpr_32, %bb.2, %104, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ 43 ]
+# CHECK: Vreg: %59:sub0[ 36 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %16[ 56 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+50 ]
+# CHECK: Vreg: %61[ 40 ]
+# CHECK: Vreg: %4[ LoopTag+55 ]
+# CHECK: Vreg: %49[ LoopTag+45 ]
+# CHECK: Vreg: %30[ LoopTag+56 ]
+# CHECK: Vreg: %18:sub0[ 47 ]
+# CHECK: Vreg: %18:sub1[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %32[ 5 ]
+# CHECK: Vreg: %1[ 59 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %27[ 32 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %15[ 11 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %3[ 39 ]
+# CHECK: Vreg: %67[ 33 ]
+# CHECK: Vreg: %29[ LoopTag+82 ]
+# CHECK: Vreg: %17:sub0[ 28 ]
+# CHECK: Vreg: %17:sub1[ 29 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: Instr: %85:vgpr_32 = PHI undef %103:vgpr_32, %bb.2, %105, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ 43 ]
+# CHECK: Vreg: %59:sub0[ 36 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %16[ 56 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+50 ]
+# CHECK: Vreg: %61[ 40 ]
+# CHECK: Vreg: %4[ LoopTag+55 ]
+# CHECK: Vreg: %49[ LoopTag+45 ]
+# CHECK: Vreg: %30[ LoopTag+56 ]
+# CHECK: Vreg: %18:sub0[ 47 ]
+# CHECK: Vreg: %18:sub1[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %82[ 2 ]
+# CHECK: Vreg: %32[ 5 ]
+# CHECK: Vreg: %1[ 59 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %27[ 32 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %15[ 11 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %3[ 39 ]
+# CHECK: Vreg: %67[ 33 ]
+# CHECK: Vreg: %29[ LoopTag+82 ]
+# CHECK: Vreg: %17:sub0[ 28 ]
+# CHECK: Vreg: %17:sub1[ 29 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: Instr: %87:sreg_32 = SI_ELSE killed %76, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %26[ 42 ]
+# CHECK: Vreg: %59:sub0[ 35 ]
+# CHECK: Vreg: %85[ 1 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %16[ 55 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+49 ]
+# CHECK: Vreg: %61[ 39 ]
+# CHECK: Vreg: %4[ LoopTag+54 ]
+# CHECK: Vreg: %49[ LoopTag+44 ]
+# CHECK: Vreg: %30[ LoopTag+55 ]
+# CHECK: Vreg: %18:sub0[ 46 ]
+# CHECK: Vreg: %18:sub1[ 47 ]
+# CHECK: Vreg: %63[ 4 ]
+# CHECK: Vreg: %82[ 1 ]
+# CHECK: Vreg: %32[ 4 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %27[ 31 ]
+# CHECK: Vreg: %34[ 13 ]
+# CHECK: Vreg: %15[ 10 ]
+# CHECK: Vreg: %3[ 38 ]
+# CHECK: Vreg: %67[ 32 ]
+# CHECK: Vreg: %29[ LoopTag+81 ]
+# CHECK: Vreg: %17:sub0[ 27 ]
+# CHECK: Vreg: %17:sub1[ 28 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %26[ 41 ]
+# CHECK: Vreg: %59:sub0[ 34 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %16[ 54 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+48 ]
+# CHECK: Vreg: %61[ 38 ]
+# CHECK: Vreg: %87[ 1 ]
+# CHECK: Vreg: %4[ LoopTag+53 ]
+# CHECK: Vreg: %49[ LoopTag+43 ]
+# CHECK: Vreg: %30[ LoopTag+54 ]
+# CHECK: Vreg: %18:sub0[ 45 ]
+# CHECK: Vreg: %18:sub1[ 46 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %82[ 0 ]
+# CHECK: Vreg: %32[ 3 ]
+# CHECK: Vreg: %1[ 57 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ 30 ]
+# CHECK: Vreg: %34[ 12 ]
+# CHECK: Vreg: %15[ 9 ]
+# CHECK: Vreg: %3[ 37 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %29[ LoopTag+80 ]
+# CHECK: Vreg: %17:sub0[ 26 ]
+# CHECK: Vreg: %17:sub1[ 27 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %26[ 41 ]
+# CHECK: Vreg: %59:sub0[ 34 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %16[ 54 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+48 ]
+# CHECK: Vreg: %61[ 38 ]
+# CHECK: Vreg: %87[ 1 ]
+# CHECK: Vreg: %4[ LoopTag+53 ]
+# CHECK: Vreg: %49[ LoopTag+43 ]
+# CHECK: Vreg: %30[ LoopTag+54 ]
+# CHECK: Vreg: %18:sub0[ 45 ]
+# CHECK: Vreg: %18:sub1[ 46 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %82[ 0 ]
+# CHECK: Vreg: %32[ 3 ]
+# CHECK: Vreg: %1[ 57 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ 30 ]
+# CHECK: Vreg: %34[ 12 ]
+# CHECK: Vreg: %15[ 9 ]
+# CHECK: Vreg: %3[ 37 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %29[ LoopTag+80 ]
+# CHECK: Vreg: %17:sub0[ 26 ]
+# CHECK: Vreg: %17:sub1[ 27 ]
+# CHECK: --- MBB_12 ---
+# CHECK: Instr: %106:sreg_32 = PHI %78, %bb.3, %107, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+17 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %26[ LoopTag+53 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %2[ LoopTag+26 ]
+# CHECK: Vreg: %16[ LoopTag+66 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+59 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+60 ]
+# CHECK: Vreg: %61[ LoopTag+50 ]
+# CHECK: Vreg: %4[ LoopTag*2+65 ]
+# CHECK: Vreg: %49[ LoopTag*2+55 ]
+# CHECK: Vreg: %30[ LoopTag*2+66 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %32[ LoopTag+15 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+15 ]
+# CHECK: Vreg: %27[ LoopTag+42 ]
+# CHECK: Vreg: %34[ LoopTag+24 ]
+# CHECK: Vreg: %15[ LoopTag+21 ]
+# CHECK: Vreg: %3[ LoopTag+49 ]
+# CHECK: Vreg: %67[ LoopTag+43 ]
+# CHECK: Vreg: %29[ LoopTag*2+92 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+39 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %76[ LoopTag+11 ]
+# CHECK: Instr: %108:sreg_32 = PHI %77, %bb.3, %109, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+17 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %26[ LoopTag+53 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %2[ LoopTag+26 ]
+# CHECK: Vreg: %16[ LoopTag+66 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+59 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+60 ]
+# CHECK: Vreg: %61[ LoopTag+50 ]
+# CHECK: Vreg: %106[ 4 ]
+# CHECK: Vreg: %4[ LoopTag*2+65 ]
+# CHECK: Vreg: %49[ LoopTag*2+55 ]
+# CHECK: Vreg: %30[ LoopTag*2+66 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %32[ LoopTag+15 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+15 ]
+# CHECK: Vreg: %27[ LoopTag+42 ]
+# CHECK: Vreg: %34[ LoopTag+24 ]
+# CHECK: Vreg: %15[ LoopTag+21 ]
+# CHECK: Vreg: %3[ LoopTag+49 ]
+# CHECK: Vreg: %67[ LoopTag+43 ]
+# CHECK: Vreg: %29[ LoopTag*2+92 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+39 ]
+# CHECK: Vreg: %76[ LoopTag+11 ]
+# CHECK: Instr: %109:sreg_32 = nuw S_ADD_I32 %108, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+16 ]
+# CHECK: Vreg: %26[ LoopTag+52 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %2[ LoopTag+25 ]
+# CHECK: Vreg: %16[ LoopTag+65 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+58 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+59 ]
+# CHECK: Vreg: %61[ LoopTag+49 ]
+# CHECK: Vreg: %106[ 3 ]
+# CHECK: Vreg: %4[ LoopTag*2+64 ]
+# CHECK: Vreg: %49[ LoopTag*2+54 ]
+# CHECK: Vreg: %30[ LoopTag*2+65 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+56 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+57 ]
+# CHECK: Vreg: %63[ LoopTag+14 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+14 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %65[ LoopTag+14 ]
+# CHECK: Vreg: %27[ LoopTag+41 ]
+# CHECK: Vreg: %34[ LoopTag+23 ]
+# CHECK: Vreg: %15[ LoopTag+20 ]
+# CHECK: Vreg: %3[ LoopTag+48 ]
+# CHECK: Vreg: %67[ LoopTag+42 ]
+# CHECK: Vreg: %29[ LoopTag*2+91 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %76[ LoopTag+10 ]
+# CHECK: Instr: %110:sreg_32 = S_ADD_I32 killed %108, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %109[ 3 ]
+# CHECK: Vreg: %26[ LoopTag+51 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %2[ LoopTag+24 ]
+# CHECK: Vreg: %16[ LoopTag+64 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+57 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+58 ]
+# CHECK: Vreg: %61[ LoopTag+48 ]
+# CHECK: Vreg: %106[ 2 ]
+# CHECK: Vreg: %4[ LoopTag*2+63 ]
+# CHECK: Vreg: %49[ LoopTag*2+53 ]
+# CHECK: Vreg: %30[ LoopTag*2+64 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %63[ LoopTag+13 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+13 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %65[ LoopTag+13 ]
+# CHECK: Vreg: %27[ LoopTag+40 ]
+# CHECK: Vreg: %34[ LoopTag+22 ]
+# CHECK: Vreg: %15[ LoopTag+19 ]
+# CHECK: Vreg: %3[ LoopTag+47 ]
+# CHECK: Vreg: %67[ LoopTag+41 ]
+# CHECK: Vreg: %29[ LoopTag*2+90 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+36 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+37 ]
+# CHECK: Vreg: %76[ LoopTag+9 ]
+# CHECK: Instr: %111:sreg_32 = V_CMP_GE_U32_e64 %110, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+14 ]
+# CHECK: Vreg: %109[ 2 ]
+# CHECK: Vreg: %26[ LoopTag+50 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %2[ LoopTag+23 ]
+# CHECK: Vreg: %16[ LoopTag+63 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+56 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+57 ]
+# CHECK: Vreg: %61[ LoopTag+47 ]
+# CHECK: Vreg: %106[ 1 ]
+# CHECK: Vreg: %4[ LoopTag*2+62 ]
+# CHECK: Vreg: %49[ LoopTag*2+52 ]
+# CHECK: Vreg: %30[ LoopTag*2+63 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+54 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+55 ]
+# CHECK: Vreg: %63[ LoopTag+12 ]
+# CHECK: Vreg: %32[ LoopTag+12 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+12 ]
+# CHECK: Vreg: %27[ LoopTag+39 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %34[ LoopTag+21 ]
+# CHECK: Vreg: %15[ LoopTag+18 ]
+# CHECK: Vreg: %3[ LoopTag+46 ]
+# CHECK: Vreg: %67[ LoopTag+40 ]
+# CHECK: Vreg: %29[ LoopTag*2+89 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+35 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+36 ]
+# CHECK: Vreg: %76[ LoopTag+8 ]
+# CHECK: Instr: %107:sreg_32 = SI_IF_BREAK killed %111, killed %106, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+13 ]
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %26[ LoopTag+49 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %2[ LoopTag+22 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %16[ LoopTag+62 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+55 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+56 ]
+# CHECK: Vreg: %61[ LoopTag+46 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %4[ LoopTag*2+61 ]
+# CHECK: Vreg: %49[ LoopTag*2+51 ]
+# CHECK: Vreg: %30[ LoopTag*2+62 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %63[ LoopTag+11 ]
+# CHECK: Vreg: %32[ LoopTag+11 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %65[ LoopTag+11 ]
+# CHECK: Vreg: %27[ LoopTag+38 ]
+# CHECK: Vreg: %110[ 2 ]
+# CHECK: Vreg: %34[ LoopTag+20 ]
+# CHECK: Vreg: %15[ LoopTag+17 ]
+# CHECK: Vreg: %3[ LoopTag+45 ]
+# CHECK: Vreg: %67[ LoopTag+39 ]
+# CHECK: Vreg: %29[ LoopTag*2+88 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+34 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+35 ]
+# CHECK: Vreg: %76[ LoopTag+7 ]
+# CHECK: Instr: %105:vgpr_32 = COPY %109, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %26[ LoopTag+48 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %2[ LoopTag+21 ]
+# CHECK: Vreg: %16[ LoopTag+61 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+54 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+55 ]
+# CHECK: Vreg: %61[ LoopTag+45 ]
+# CHECK: Vreg: %4[ LoopTag*2+60 ]
+# CHECK: Vreg: %49[ LoopTag*2+50 ]
+# CHECK: Vreg: %30[ LoopTag*2+61 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+52 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+53 ]
+# CHECK: Vreg: %63[ LoopTag+10 ]
+# CHECK: Vreg: %32[ LoopTag+10 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %65[ LoopTag+10 ]
+# CHECK: Vreg: %27[ LoopTag+37 ]
+# CHECK: Vreg: %110[ 1 ]
+# CHECK: Vreg: %34[ LoopTag+19 ]
+# CHECK: Vreg: %15[ LoopTag+16 ]
+# CHECK: Vreg: %3[ LoopTag+44 ]
+# CHECK: Vreg: %67[ LoopTag+38 ]
+# CHECK: Vreg: %29[ LoopTag*2+87 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+33 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+34 ]
+# CHECK: Vreg: %107[ 2 ]
+# CHECK: Vreg: %76[ LoopTag+6 ]
+# CHECK: Instr: %104:vgpr_32 = COPY killed %110, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+11 ]
+# CHECK: Vreg: %109[ 2 ]
+# CHECK: Vreg: %26[ LoopTag+47 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %2[ LoopTag+20 ]
+# CHECK: Vreg: %16[ LoopTag+60 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+53 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+54 ]
+# CHECK: Vreg: %61[ LoopTag+44 ]
+# CHECK: Vreg: %4[ LoopTag*2+59 ]
+# CHECK: Vreg: %49[ LoopTag*2+49 ]
+# CHECK: Vreg: %30[ LoopTag*2+60 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+51 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+52 ]
+# CHECK: Vreg: %63[ LoopTag+9 ]
+# CHECK: Vreg: %32[ LoopTag+9 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %65[ LoopTag+9 ]
+# CHECK: Vreg: %27[ LoopTag+36 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %34[ LoopTag+18 ]
+# CHECK: Vreg: %15[ LoopTag+15 ]
+# CHECK: Vreg: %105[ LoopTag+4 ]
+# CHECK: Vreg: %3[ LoopTag+43 ]
+# CHECK: Vreg: %67[ LoopTag+37 ]
+# CHECK: Vreg: %29[ LoopTag*2+86 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+32 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+33 ]
+# CHECK: Vreg: %107[ 1 ]
+# CHECK: Vreg: %76[ LoopTag+5 ]
+# CHECK: Instr: SI_LOOP %107, %bb.12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %26[ LoopTag+46 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+39 ]
+# CHECK: Vreg: %104[ LoopTag+3 ]
+# CHECK: Vreg: %2[ LoopTag+19 ]
+# CHECK: Vreg: %16[ LoopTag+59 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+52 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+53 ]
+# CHECK: Vreg: %61[ LoopTag+43 ]
+# CHECK: Vreg: %4[ LoopTag*2+58 ]
+# CHECK: Vreg: %49[ LoopTag*2+48 ]
+# CHECK: Vreg: %30[ LoopTag*2+59 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+50 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+51 ]
+# CHECK: Vreg: %63[ LoopTag+8 ]
+# CHECK: Vreg: %32[ LoopTag+8 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %65[ LoopTag+8 ]
+# CHECK: Vreg: %27[ LoopTag+35 ]
+# CHECK: Vreg: %34[ LoopTag+17 ]
+# CHECK: Vreg: %15[ LoopTag+14 ]
+# CHECK: Vreg: %105[ LoopTag+3 ]
+# CHECK: Vreg: %3[ LoopTag+42 ]
+# CHECK: Vreg: %67[ LoopTag+36 ]
+# CHECK: Vreg: %29[ LoopTag*2+85 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+31 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+32 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %76[ LoopTag+4 ]
+# CHECK: Instr: S_BRANCH %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+9 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %26[ LoopTag+45 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %104[ LoopTag+2 ]
+# CHECK: Vreg: %2[ LoopTag+18 ]
+# CHECK: Vreg: %16[ LoopTag+58 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+51 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+52 ]
+# CHECK: Vreg: %61[ LoopTag+42 ]
+# CHECK: Vreg: %4[ LoopTag*2+57 ]
+# CHECK: Vreg: %49[ LoopTag*2+47 ]
+# CHECK: Vreg: %30[ LoopTag*2+58 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+50 ]
+# CHECK: Vreg: %63[ LoopTag+7 ]
+# CHECK: Vreg: %32[ LoopTag+7 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+7 ]
+# CHECK: Vreg: %27[ LoopTag+34 ]
+# CHECK: Vreg: %34[ LoopTag+16 ]
+# CHECK: Vreg: %15[ LoopTag+13 ]
+# CHECK: Vreg: %105[ LoopTag+2 ]
+# CHECK: Vreg: %3[ LoopTag+41 ]
+# CHECK: Vreg: %67[ LoopTag+35 ]
+# CHECK: Vreg: %29[ LoopTag*2+84 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+30 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+31 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %76[ LoopTag+3 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+9 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %26[ LoopTag+45 ]
+# CHECK: Vreg: %59:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %104[ LoopTag+2 ]
+# CHECK: Vreg: %2[ LoopTag+18 ]
+# CHECK: Vreg: %16[ LoopTag+58 ]
+# CHECK: Vreg: %16:sub0[ LoopTag*2+51 ]
+# CHECK: Vreg: %16:sub1[ LoopTag*2+52 ]
+# CHECK: Vreg: %61[ LoopTag+42 ]
+# CHECK: Vreg: %4[ LoopTag*2+57 ]
+# CHECK: Vreg: %49[ LoopTag*2+47 ]
+# CHECK: Vreg: %30[ LoopTag*2+58 ]
+# CHECK: Vreg: %18:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %18:sub1[ LoopTag+50 ]
+# CHECK: Vreg: %63[ LoopTag+7 ]
+# CHECK: Vreg: %32[ LoopTag+7 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+7 ]
+# CHECK: Vreg: %27[ LoopTag+34 ]
+# CHECK: Vreg: %34[ LoopTag+16 ]
+# CHECK: Vreg: %15[ LoopTag+13 ]
+# CHECK: Vreg: %105[ LoopTag+2 ]
+# CHECK: Vreg: %3[ LoopTag+41 ]
+# CHECK: Vreg: %67[ LoopTag+35 ]
+# CHECK: Vreg: %29[ LoopTag*2+84 ]
+# CHECK: Vreg: %17:sub0[ LoopTag+30 ]
+# CHECK: Vreg: %17:sub1[ LoopTag+31 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %76[ LoopTag+3 ]
+# CHECK: --- MBB_13 ---
+# CHECK: Instr: SI_END_CF killed %107, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %26[ 44 ]
+# CHECK: Vreg: %59:sub0[ 37 ]
+# CHECK: Vreg: %104[ 1 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %16[ 57 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+50 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+51 ]
+# CHECK: Vreg: %61[ 41 ]
+# CHECK: Vreg: %4[ LoopTag+56 ]
+# CHECK: Vreg: %49[ LoopTag+46 ]
+# CHECK: Vreg: %30[ LoopTag+57 ]
+# CHECK: Vreg: %18:sub0[ 48 ]
+# CHECK: Vreg: %18:sub1[ 49 ]
+# CHECK: Vreg: %63[ 6 ]
+# CHECK: Vreg: %32[ 6 ]
+# CHECK: Vreg: %1[ 60 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %27[ 33 ]
+# CHECK: Vreg: %34[ 15 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %105[ 1 ]
+# CHECK: Vreg: %3[ 40 ]
+# CHECK: Vreg: %67[ 34 ]
+# CHECK: Vreg: %29[ LoopTag+83 ]
+# CHECK: Vreg: %17:sub0[ 29 ]
+# CHECK: Vreg: %17:sub1[ 30 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %76[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ 43 ]
+# CHECK: Vreg: %59:sub0[ 36 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %16[ 56 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+50 ]
+# CHECK: Vreg: %61[ 40 ]
+# CHECK: Vreg: %4[ LoopTag+55 ]
+# CHECK: Vreg: %49[ LoopTag+45 ]
+# CHECK: Vreg: %30[ LoopTag+56 ]
+# CHECK: Vreg: %18:sub0[ 47 ]
+# CHECK: Vreg: %18:sub1[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %32[ 5 ]
+# CHECK: Vreg: %1[ 59 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %27[ 32 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %15[ 11 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %3[ 39 ]
+# CHECK: Vreg: %67[ 33 ]
+# CHECK: Vreg: %29[ LoopTag+82 ]
+# CHECK: Vreg: %17:sub0[ 28 ]
+# CHECK: Vreg: %17:sub1[ 29 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ 43 ]
+# CHECK: Vreg: %59:sub0[ 36 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %16[ 56 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+50 ]
+# CHECK: Vreg: %61[ 40 ]
+# CHECK: Vreg: %4[ LoopTag+55 ]
+# CHECK: Vreg: %49[ LoopTag+45 ]
+# CHECK: Vreg: %30[ LoopTag+56 ]
+# CHECK: Vreg: %18:sub0[ 47 ]
+# CHECK: Vreg: %18:sub1[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %32[ 5 ]
+# CHECK: Vreg: %1[ 59 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %27[ 32 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %15[ 11 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %3[ 39 ]
+# CHECK: Vreg: %67[ 33 ]
+# CHECK: Vreg: %29[ LoopTag+82 ]
+# CHECK: Vreg: %17:sub0[ 28 ]
+# CHECK: Vreg: %17:sub1[ 29 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: --- MBB_14 ---
+# CHECK: Instr: SI_END_CF killed %89, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 50 ]
+# CHECK: Vreg: %26[ 42 ]
+# CHECK: Vreg: %59:sub0[ 35 ]
+# CHECK: Vreg: %2[ 68 ]
+# CHECK: Vreg: %16[ 55 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+49 ]
+# CHECK: Vreg: %61[ 39 ]
+# CHECK: Vreg: %87[ 2 ]
+# CHECK: Vreg: %4[ LoopTag+54 ]
+# CHECK: Vreg: %49[ LoopTag+44 ]
+# CHECK: Vreg: %30[ LoopTag+55 ]
+# CHECK: Vreg: %18:sub0[ 46 ]
+# CHECK: Vreg: %18:sub1[ 47 ]
+# CHECK: Vreg: %63[ 37 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %32[ 57 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %27[ 31 ]
+# CHECK: Vreg: %34[ 36 ]
+# CHECK: Vreg: %15[ 63 ]
+# CHECK: Vreg: %86[ 1 ]
+# CHECK: Vreg: %3[ 38 ]
+# CHECK: Vreg: %67[ 32 ]
+# CHECK: Vreg: %29[ LoopTag+81 ]
+# CHECK: Vreg: %17:sub0[ 27 ]
+# CHECK: Vreg: %17:sub1[ 28 ]
+# CHECK: Vreg: %83[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 49 ]
+# CHECK: Vreg: %26[ 41 ]
+# CHECK: Vreg: %59:sub0[ 34 ]
+# CHECK: Vreg: %2[ 67 ]
+# CHECK: Vreg: %16[ 54 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+48 ]
+# CHECK: Vreg: %61[ 38 ]
+# CHECK: Vreg: %87[ 1 ]
+# CHECK: Vreg: %4[ LoopTag+53 ]
+# CHECK: Vreg: %49[ LoopTag+43 ]
+# CHECK: Vreg: %30[ LoopTag+54 ]
+# CHECK: Vreg: %18:sub0[ 45 ]
+# CHECK: Vreg: %18:sub1[ 46 ]
+# CHECK: Vreg: %63[ 36 ]
+# CHECK: Vreg: %32[ 56 ]
+# CHECK: Vreg: %1[ 57 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ 30 ]
+# CHECK: Vreg: %34[ 35 ]
+# CHECK: Vreg: %15[ 62 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 37 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %29[ LoopTag+80 ]
+# CHECK: Vreg: %17:sub0[ 26 ]
+# CHECK: Vreg: %17:sub1[ 27 ]
+# CHECK: Vreg: %83[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 49 ]
+# CHECK: Vreg: %26[ 41 ]
+# CHECK: Vreg: %59:sub0[ 34 ]
+# CHECK: Vreg: %2[ 67 ]
+# CHECK: Vreg: %16[ 54 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+48 ]
+# CHECK: Vreg: %61[ 38 ]
+# CHECK: Vreg: %87[ 1 ]
+# CHECK: Vreg: %4[ LoopTag+53 ]
+# CHECK: Vreg: %49[ LoopTag+43 ]
+# CHECK: Vreg: %30[ LoopTag+54 ]
+# CHECK: Vreg: %18:sub0[ 45 ]
+# CHECK: Vreg: %18:sub1[ 46 ]
+# CHECK: Vreg: %63[ 36 ]
+# CHECK: Vreg: %32[ 56 ]
+# CHECK: Vreg: %1[ 57 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ 30 ]
+# CHECK: Vreg: %34[ 35 ]
+# CHECK: Vreg: %15[ 62 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %3[ 37 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %29[ LoopTag+80 ]
+# CHECK: Vreg: %17:sub0[ 26 ]
+# CHECK: Vreg: %17:sub1[ 27 ]
+# CHECK: Vreg: %83[ 0 ]
+# CHECK: --- MBB_15 ---
+# CHECK: Instr: %112:sgpr_32 = S_CVT_F32_U32 %65, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %26[ 38 ]
+# CHECK: Vreg: %59:sub0[ 31 ]
+# CHECK: Vreg: %2[ 64 ]
+# CHECK: Vreg: %16[ 51 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+45 ]
+# CHECK: Vreg: %61[ 35 ]
+# CHECK: Vreg: %4[ LoopTag+50 ]
+# CHECK: Vreg: %49[ LoopTag+40 ]
+# CHECK: Vreg: %30[ LoopTag+51 ]
+# CHECK: Vreg: %18:sub0[ 42 ]
+# CHECK: Vreg: %18:sub1[ 43 ]
+# CHECK: Vreg: %63[ 33 ]
+# CHECK: Vreg: %32[ 53 ]
+# CHECK: Vreg: %84[ 9 ]
+# CHECK: Vreg: %1[ 54 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 27 ]
+# CHECK: Vreg: %34[ 32 ]
+# CHECK: Vreg: %15[ 59 ]
+# CHECK: Vreg: %3[ 34 ]
+# CHECK: Vreg: %29[ LoopTag+77 ]
+# CHECK: Vreg: %67[ 28 ]
+# CHECK: Vreg: %17:sub0[ 23 ]
+# CHECK: Vreg: %17:sub1[ 24 ]
+# CHECK: Vreg: %81[ 27 ]
+# CHECK: Instr: %113:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %112, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %26[ 37 ]
+# CHECK: Vreg: %59:sub0[ 30 ]
+# CHECK: Vreg: %2[ 63 ]
+# CHECK: Vreg: %16[ 50 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+44 ]
+# CHECK: Vreg: %61[ 34 ]
+# CHECK: Vreg: %4[ LoopTag+49 ]
+# CHECK: Vreg: %49[ LoopTag+39 ]
+# CHECK: Vreg: %30[ LoopTag+50 ]
+# CHECK: Vreg: %18:sub0[ 41 ]
+# CHECK: Vreg: %18:sub1[ 42 ]
+# CHECK: Vreg: %63[ 32 ]
+# CHECK: Vreg: %32[ 52 ]
+# CHECK: Vreg: %84[ 8 ]
+# CHECK: Vreg: %1[ 53 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %27[ 26 ]
+# CHECK: Vreg: %34[ 31 ]
+# CHECK: Vreg: %15[ 58 ]
+# CHECK: Vreg: %3[ 33 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+76 ]
+# CHECK: Vreg: %67[ 27 ]
+# CHECK: Vreg: %17:sub0[ 22 ]
+# CHECK: Vreg: %17:sub1[ 23 ]
+# CHECK: Vreg: %81[ 26 ]
+# CHECK: Instr: %114:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %113, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 44 ]
+# CHECK: Vreg: %26[ 36 ]
+# CHECK: Vreg: %59:sub0[ 29 ]
+# CHECK: Vreg: %2[ 62 ]
+# CHECK: Vreg: %16[ 49 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+43 ]
+# CHECK: Vreg: %61[ 33 ]
+# CHECK: Vreg: %4[ LoopTag+48 ]
+# CHECK: Vreg: %49[ LoopTag+38 ]
+# CHECK: Vreg: %30[ LoopTag+49 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %18:sub0[ 40 ]
+# CHECK: Vreg: %18:sub1[ 41 ]
+# CHECK: Vreg: %63[ 31 ]
+# CHECK: Vreg: %32[ 51 ]
+# CHECK: Vreg: %84[ 7 ]
+# CHECK: Vreg: %1[ 52 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ 25 ]
+# CHECK: Vreg: %34[ 30 ]
+# CHECK: Vreg: %15[ 57 ]
+# CHECK: Vreg: %3[ 32 ]
+# CHECK: Vreg: %29[ LoopTag+75 ]
+# CHECK: Vreg: %67[ 26 ]
+# CHECK: Vreg: %17:sub0[ 21 ]
+# CHECK: Vreg: %17:sub1[ 22 ]
+# CHECK: Vreg: %81[ 25 ]
+# CHECK: Instr: %115:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %114, 1333788670, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Vreg: %26[ 35 ]
+# CHECK: Vreg: %59:sub0[ 28 ]
+# CHECK: Vreg: %2[ 61 ]
+# CHECK: Vreg: %16[ 48 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+42 ]
+# CHECK: Vreg: %61[ 32 ]
+# CHECK: Vreg: %4[ LoopTag+47 ]
+# CHECK: Vreg: %49[ LoopTag+37 ]
+# CHECK: Vreg: %30[ LoopTag+48 ]
+# CHECK: Vreg: %18:sub0[ 39 ]
+# CHECK: Vreg: %18:sub1[ 40 ]
+# CHECK: Vreg: %63[ 30 ]
+# CHECK: Vreg: %32[ 50 ]
+# CHECK: Vreg: %84[ 6 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ 24 ]
+# CHECK: Vreg: %34[ 29 ]
+# CHECK: Vreg: %15[ 56 ]
+# CHECK: Vreg: %3[ 31 ]
+# CHECK: Vreg: %29[ LoopTag+74 ]
+# CHECK: Vreg: %67[ 25 ]
+# CHECK: Vreg: %17:sub0[ 20 ]
+# CHECK: Vreg: %17:sub1[ 21 ]
+# CHECK: Vreg: %81[ 24 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Instr: %116:sreg_32 = nofpexcept S_CVT_U32_F32 killed %115, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 42 ]
+# CHECK: Vreg: %26[ 34 ]
+# CHECK: Vreg: %59:sub0[ 27 ]
+# CHECK: Vreg: %2[ 60 ]
+# CHECK: Vreg: %16[ 47 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+41 ]
+# CHECK: Vreg: %61[ 31 ]
+# CHECK: Vreg: %4[ LoopTag+46 ]
+# CHECK: Vreg: %49[ LoopTag+36 ]
+# CHECK: Vreg: %30[ LoopTag+47 ]
+# CHECK: Vreg: %18:sub0[ 38 ]
+# CHECK: Vreg: %18:sub1[ 39 ]
+# CHECK: Vreg: %63[ 29 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %32[ 49 ]
+# CHECK: Vreg: %84[ 5 ]
+# CHECK: Vreg: %1[ 50 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %27[ 23 ]
+# CHECK: Vreg: %34[ 28 ]
+# CHECK: Vreg: %15[ 55 ]
+# CHECK: Vreg: %3[ 30 ]
+# CHECK: Vreg: %29[ LoopTag+73 ]
+# CHECK: Vreg: %67[ 24 ]
+# CHECK: Vreg: %17:sub0[ 19 ]
+# CHECK: Vreg: %17:sub1[ 20 ]
+# CHECK: Vreg: %81[ 23 ]
+# CHECK: Instr: %117:sreg_32 = S_SUB_I32 0, %65, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %26[ 33 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %59:sub0[ 26 ]
+# CHECK: Vreg: %2[ 59 ]
+# CHECK: Vreg: %16[ 46 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+39 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+40 ]
+# CHECK: Vreg: %61[ 30 ]
+# CHECK: Vreg: %4[ LoopTag+45 ]
+# CHECK: Vreg: %49[ LoopTag+35 ]
+# CHECK: Vreg: %30[ LoopTag+46 ]
+# CHECK: Vreg: %18:sub0[ 37 ]
+# CHECK: Vreg: %18:sub1[ 38 ]
+# CHECK: Vreg: %63[ 28 ]
+# CHECK: Vreg: %32[ 48 ]
+# CHECK: Vreg: %84[ 4 ]
+# CHECK: Vreg: %1[ 49 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 22 ]
+# CHECK: Vreg: %34[ 27 ]
+# CHECK: Vreg: %15[ 54 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %29[ LoopTag+72 ]
+# CHECK: Vreg: %67[ 23 ]
+# CHECK: Vreg: %17:sub0[ 18 ]
+# CHECK: Vreg: %17:sub1[ 19 ]
+# CHECK: Vreg: %81[ 22 ]
+# CHECK: Instr: %118:sreg_32 = S_MUL_I32 killed %117, %116
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %26[ 32 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %59:sub0[ 25 ]
+# CHECK: Vreg: %2[ 58 ]
+# CHECK: Vreg: %16[ 45 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+39 ]
+# CHECK: Vreg: %61[ 29 ]
+# CHECK: Vreg: %4[ LoopTag+44 ]
+# CHECK: Vreg: %49[ LoopTag+34 ]
+# CHECK: Vreg: %30[ LoopTag+45 ]
+# CHECK: Vreg: %18:sub0[ 36 ]
+# CHECK: Vreg: %18:sub1[ 37 ]
+# CHECK: Vreg: %63[ 27 ]
+# CHECK: Vreg: %32[ 47 ]
+# CHECK: Vreg: %84[ 3 ]
+# CHECK: Vreg: %1[ 48 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %27[ 21 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %34[ 26 ]
+# CHECK: Vreg: %15[ 53 ]
+# CHECK: Vreg: %3[ 28 ]
+# CHECK: Vreg: %29[ LoopTag+71 ]
+# CHECK: Vreg: %67[ 22 ]
+# CHECK: Vreg: %17:sub0[ 17 ]
+# CHECK: Vreg: %17:sub1[ 18 ]
+# CHECK: Vreg: %81[ 21 ]
+# CHECK: Instr: %119:sreg_32 = S_MUL_HI_U32 %116, killed %118
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 39 ]
+# CHECK: Vreg: %26[ 31 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %59:sub0[ 24 ]
+# CHECK: Vreg: %2[ 57 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %16[ 44 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %61[ 28 ]
+# CHECK: Vreg: %4[ LoopTag+43 ]
+# CHECK: Vreg: %49[ LoopTag+33 ]
+# CHECK: Vreg: %30[ LoopTag+44 ]
+# CHECK: Vreg: %18:sub0[ 35 ]
+# CHECK: Vreg: %18:sub1[ 36 ]
+# CHECK: Vreg: %63[ 26 ]
+# CHECK: Vreg: %32[ 46 ]
+# CHECK: Vreg: %84[ 2 ]
+# CHECK: Vreg: %1[ 47 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ 20 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %15[ 52 ]
+# CHECK: Vreg: %3[ 27 ]
+# CHECK: Vreg: %29[ LoopTag+70 ]
+# CHECK: Vreg: %67[ 21 ]
+# CHECK: Vreg: %17:sub0[ 16 ]
+# CHECK: Vreg: %17:sub1[ 17 ]
+# CHECK: Vreg: %81[ 20 ]
+# CHECK: Instr: %120:sreg_32 = S_ADD_I32 killed %116, killed %119, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 38 ]
+# CHECK: Vreg: %26[ 30 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %59:sub0[ 23 ]
+# CHECK: Vreg: %2[ 56 ]
+# CHECK: Vreg: %16[ 43 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+36 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+37 ]
+# CHECK: Vreg: %61[ 27 ]
+# CHECK: Vreg: %4[ LoopTag+42 ]
+# CHECK: Vreg: %49[ LoopTag+32 ]
+# CHECK: Vreg: %30[ LoopTag+43 ]
+# CHECK: Vreg: %18:sub0[ 34 ]
+# CHECK: Vreg: %18:sub1[ 35 ]
+# CHECK: Vreg: %63[ 25 ]
+# CHECK: Vreg: %32[ 45 ]
+# CHECK: Vreg: %84[ 1 ]
+# CHECK: Vreg: %1[ 46 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ 19 ]
+# CHECK: Vreg: %34[ 24 ]
+# CHECK: Vreg: %15[ 51 ]
+# CHECK: Vreg: %3[ 26 ]
+# CHECK: Vreg: %29[ LoopTag+69 ]
+# CHECK: Vreg: %67[ 20 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %17:sub0[ 15 ]
+# CHECK: Vreg: %17:sub1[ 16 ]
+# CHECK: Vreg: %81[ 19 ]
+# CHECK: Instr: %121:vgpr_32 = V_MUL_HI_U32_e64 %84, killed %120, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %59:sub0[ 22 ]
+# CHECK: Vreg: %2[ 55 ]
+# CHECK: Vreg: %16[ 42 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+35 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+36 ]
+# CHECK: Vreg: %61[ 26 ]
+# CHECK: Vreg: %4[ LoopTag+41 ]
+# CHECK: Vreg: %49[ LoopTag+31 ]
+# CHECK: Vreg: %30[ LoopTag+42 ]
+# CHECK: Vreg: %120[ 0 ]
+# CHECK: Vreg: %18:sub0[ 33 ]
+# CHECK: Vreg: %18:sub1[ 34 ]
+# CHECK: Vreg: %63[ 24 ]
+# CHECK: Vreg: %32[ 44 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %27[ 18 ]
+# CHECK: Vreg: %34[ 23 ]
+# CHECK: Vreg: %15[ 50 ]
+# CHECK: Vreg: %3[ 25 ]
+# CHECK: Vreg: %29[ LoopTag+68 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %17:sub0[ 14 ]
+# CHECK: Vreg: %17:sub1[ 15 ]
+# CHECK: Vreg: %81[ 18 ]
+# CHECK: Instr: %122:vgpr_32 = V_MUL_LO_U32_e64 %121, %65, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %26[ 28 ]
+# CHECK: Vreg: %59:sub0[ 21 ]
+# CHECK: Vreg: %2[ 54 ]
+# CHECK: Vreg: %16[ 41 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+34 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+35 ]
+# CHECK: Vreg: %61[ 25 ]
+# CHECK: Vreg: %4[ LoopTag+40 ]
+# CHECK: Vreg: %49[ LoopTag+30 ]
+# CHECK: Vreg: %30[ LoopTag+41 ]
+# CHECK: Vreg: %18:sub0[ 32 ]
+# CHECK: Vreg: %18:sub1[ 33 ]
+# CHECK: Vreg: %63[ 23 ]
+# CHECK: Vreg: %32[ 43 ]
+# CHECK: Vreg: %84[ 1 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 17 ]
+# CHECK: Vreg: %34[ 22 ]
+# CHECK: Vreg: %15[ 49 ]
+# CHECK: Vreg: %3[ 24 ]
+# CHECK: Vreg: %29[ LoopTag+67 ]
+# CHECK: Vreg: %67[ 18 ]
+# CHECK: Vreg: %17:sub0[ 13 ]
+# CHECK: Vreg: %17:sub1[ 14 ]
+# CHECK: Vreg: %81[ 17 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Instr: %123:vgpr_32 = V_SUB_U32_e64 %84, killed %122, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %26[ 27 ]
+# CHECK: Vreg: %59:sub0[ 20 ]
+# CHECK: Vreg: %2[ 53 ]
+# CHECK: Vreg: %16[ 40 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+33 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+34 ]
+# CHECK: Vreg: %61[ 24 ]
+# CHECK: Vreg: %4[ LoopTag+39 ]
+# CHECK: Vreg: %49[ LoopTag+29 ]
+# CHECK: Vreg: %30[ LoopTag+40 ]
+# CHECK: Vreg: %18:sub0[ 31 ]
+# CHECK: Vreg: %18:sub1[ 32 ]
+# CHECK: Vreg: %63[ 22 ]
+# CHECK: Vreg: %32[ 42 ]
+# CHECK: Vreg: %122[ 0 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %27[ 16 ]
+# CHECK: Vreg: %34[ 21 ]
+# CHECK: Vreg: %15[ 48 ]
+# CHECK: Vreg: %3[ 23 ]
+# CHECK: Vreg: %29[ LoopTag+66 ]
+# CHECK: Vreg: %67[ 17 ]
+# CHECK: Vreg: %17:sub0[ 12 ]
+# CHECK: Vreg: %17:sub1[ 13 ]
+# CHECK: Vreg: %81[ 16 ]
+# CHECK: Vreg: %121[ 2 ]
+# CHECK: Instr: %124:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %65, %123, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %26[ 26 ]
+# CHECK: Vreg: %59:sub0[ 19 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %16[ 39 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+32 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+33 ]
+# CHECK: Vreg: %61[ 23 ]
+# CHECK: Vreg: %4[ LoopTag+38 ]
+# CHECK: Vreg: %49[ LoopTag+28 ]
+# CHECK: Vreg: %30[ LoopTag+39 ]
+# CHECK: Vreg: %18:sub0[ 30 ]
+# CHECK: Vreg: %18:sub1[ 31 ]
+# CHECK: Vreg: %63[ 21 ]
+# CHECK: Vreg: %32[ 41 ]
+# CHECK: Vreg: %84[ 19 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 15 ]
+# CHECK: Vreg: %34[ 20 ]
+# CHECK: Vreg: %15[ 47 ]
+# CHECK: Vreg: %3[ 22 ]
+# CHECK: Vreg: %29[ LoopTag+65 ]
+# CHECK: Vreg: %67[ 16 ]
+# CHECK: Vreg: %17:sub0[ 11 ]
+# CHECK: Vreg: %17:sub1[ 12 ]
+# CHECK: Vreg: %81[ 15 ]
+# CHECK: Vreg: %121[ 1 ]
+# CHECK: Instr: %125:vgpr_32 = V_ADD_U32_e64 1, %121, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %59:sub0[ 18 ]
+# CHECK: Vreg: %123[ 2 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %16[ 38 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+31 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+32 ]
+# CHECK: Vreg: %61[ 22 ]
+# CHECK: Vreg: %4[ LoopTag+37 ]
+# CHECK: Vreg: %49[ LoopTag+27 ]
+# CHECK: Vreg: %30[ LoopTag+38 ]
+# CHECK: Vreg: %18:sub0[ 29 ]
+# CHECK: Vreg: %18:sub1[ 30 ]
+# CHECK: Vreg: %63[ 20 ]
+# CHECK: Vreg: %32[ 40 ]
+# CHECK: Vreg: %84[ 18 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ 14 ]
+# CHECK: Vreg: %34[ 19 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %124[ 1 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %29[ LoopTag+64 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %17:sub0[ 10 ]
+# CHECK: Vreg: %17:sub1[ 11 ]
+# CHECK: Vreg: %81[ 14 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Instr: %126:vgpr_32 = V_CNDMASK_B32_e64 0, killed %121, 0, killed %125, %124, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %59:sub0[ 17 ]
+# CHECK: Vreg: %123[ 1 ]
+# CHECK: Vreg: %2[ 50 ]
+# CHECK: Vreg: %16[ 37 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+30 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+31 ]
+# CHECK: Vreg: %61[ 21 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %4[ LoopTag+36 ]
+# CHECK: Vreg: %49[ LoopTag+26 ]
+# CHECK: Vreg: %30[ LoopTag+37 ]
+# CHECK: Vreg: %18:sub0[ 28 ]
+# CHECK: Vreg: %18:sub1[ 29 ]
+# CHECK: Vreg: %63[ 19 ]
+# CHECK: Vreg: %32[ 39 ]
+# CHECK: Vreg: %84[ 17 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %27[ 13 ]
+# CHECK: Vreg: %34[ 18 ]
+# CHECK: Vreg: %15[ 45 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %29[ LoopTag+63 ]
+# CHECK: Vreg: %67[ 14 ]
+# CHECK: Vreg: %17:sub0[ 9 ]
+# CHECK: Vreg: %17:sub1[ 10 ]
+# CHECK: Vreg: %81[ 13 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Instr: %127:vgpr_32 = V_SUBREV_U32_e64 %65, %123, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %26[ 23 ]
+# CHECK: Vreg: %59:sub0[ 16 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %2[ 49 ]
+# CHECK: Vreg: %16[ 36 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+29 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+30 ]
+# CHECK: Vreg: %61[ 20 ]
+# CHECK: Vreg: %4[ LoopTag+35 ]
+# CHECK: Vreg: %49[ LoopTag+25 ]
+# CHECK: Vreg: %30[ LoopTag+36 ]
+# CHECK: Vreg: %18:sub0[ 27 ]
+# CHECK: Vreg: %18:sub1[ 28 ]
+# CHECK: Vreg: %63[ 18 ]
+# CHECK: Vreg: %32[ 38 ]
+# CHECK: Vreg: %84[ 16 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 12 ]
+# CHECK: Vreg: %34[ 17 ]
+# CHECK: Vreg: %15[ 44 ]
+# CHECK: Vreg: %124[ 1 ]
+# CHECK: Vreg: %3[ 19 ]
+# CHECK: Vreg: %29[ LoopTag+62 ]
+# CHECK: Vreg: %67[ 13 ]
+# CHECK: Vreg: %17:sub0[ 8 ]
+# CHECK: Vreg: %17:sub1[ 9 ]
+# CHECK: Vreg: %81[ 12 ]
+# CHECK: Vreg: %126[ 3 ]
+# CHECK: Instr: %128:vgpr_32 = V_CNDMASK_B32_e64 0, killed %123, 0, killed %127, killed %124, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %26[ 22 ]
+# CHECK: Vreg: %59:sub0[ 15 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %2[ 48 ]
+# CHECK: Vreg: %16[ 35 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+28 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+29 ]
+# CHECK: Vreg: %61[ 19 ]
+# CHECK: Vreg: %4[ LoopTag+34 ]
+# CHECK: Vreg: %49[ LoopTag+24 ]
+# CHECK: Vreg: %30[ LoopTag+35 ]
+# CHECK: Vreg: %18:sub0[ 26 ]
+# CHECK: Vreg: %18:sub1[ 27 ]
+# CHECK: Vreg: %63[ 17 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %32[ 37 ]
+# CHECK: Vreg: %84[ 15 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %34[ 16 ]
+# CHECK: Vreg: %15[ 43 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %29[ LoopTag+61 ]
+# CHECK: Vreg: %67[ 12 ]
+# CHECK: Vreg: %17:sub0[ 7 ]
+# CHECK: Vreg: %17:sub1[ 8 ]
+# CHECK: Vreg: %81[ 11 ]
+# CHECK: Vreg: %126[ 2 ]
+# CHECK: Instr: %129:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %65, killed %128, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %128[ 0 ]
+# CHECK: Vreg: %26[ 21 ]
+# CHECK: Vreg: %59:sub0[ 14 ]
+# CHECK: Vreg: %2[ 47 ]
+# CHECK: Vreg: %16[ 34 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+27 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+28 ]
+# CHECK: Vreg: %61[ 18 ]
+# CHECK: Vreg: %4[ LoopTag+33 ]
+# CHECK: Vreg: %49[ LoopTag+23 ]
+# CHECK: Vreg: %30[ LoopTag+34 ]
+# CHECK: Vreg: %18:sub0[ 25 ]
+# CHECK: Vreg: %18:sub1[ 26 ]
+# CHECK: Vreg: %63[ 16 ]
+# CHECK: Vreg: %32[ 36 ]
+# CHECK: Vreg: %84[ 14 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 10 ]
+# CHECK: Vreg: %34[ 15 ]
+# CHECK: Vreg: %15[ 42 ]
+# CHECK: Vreg: %3[ 17 ]
+# CHECK: Vreg: %29[ LoopTag+60 ]
+# CHECK: Vreg: %67[ 11 ]
+# CHECK: Vreg: %17:sub0[ 6 ]
+# CHECK: Vreg: %17:sub1[ 7 ]
+# CHECK: Vreg: %81[ 10 ]
+# CHECK: Vreg: %126[ 1 ]
+# CHECK: Instr: %130:vgpr_32 = V_ADD_U32_e64 1, %126, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %26[ 20 ]
+# CHECK: Vreg: %59:sub0[ 13 ]
+# CHECK: Vreg: %2[ 46 ]
+# CHECK: Vreg: %16[ 33 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+26 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+27 ]
+# CHECK: Vreg: %61[ 17 ]
+# CHECK: Vreg: %4[ LoopTag+32 ]
+# CHECK: Vreg: %49[ LoopTag+22 ]
+# CHECK: Vreg: %30[ LoopTag+33 ]
+# CHECK: Vreg: %18:sub0[ 24 ]
+# CHECK: Vreg: %18:sub1[ 25 ]
+# CHECK: Vreg: %63[ 15 ]
+# CHECK: Vreg: %32[ 35 ]
+# CHECK: Vreg: %84[ 13 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %27[ 9 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %15[ 41 ]
+# CHECK: Vreg: %3[ 16 ]
+# CHECK: Vreg: %29[ LoopTag+59 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %17:sub0[ 5 ]
+# CHECK: Vreg: %17:sub1[ 6 ]
+# CHECK: Vreg: %81[ 9 ]
+# CHECK: Vreg: %126[ 0 ]
+# CHECK: Instr: %131:vgpr_32 = V_CNDMASK_B32_e64 0, killed %126, 0, killed %130, killed %129, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %26[ 19 ]
+# CHECK: Vreg: %59:sub0[ 12 ]
+# CHECK: Vreg: %2[ 45 ]
+# CHECK: Vreg: %130[ 0 ]
+# CHECK: Vreg: %16[ 32 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+25 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+26 ]
+# CHECK: Vreg: %61[ 16 ]
+# CHECK: Vreg: %4[ LoopTag+31 ]
+# CHECK: Vreg: %49[ LoopTag+21 ]
+# CHECK: Vreg: %30[ LoopTag+32 ]
+# CHECK: Vreg: %18:sub0[ 23 ]
+# CHECK: Vreg: %18:sub1[ 24 ]
+# CHECK: Vreg: %63[ 14 ]
+# CHECK: Vreg: %32[ 34 ]
+# CHECK: Vreg: %84[ 12 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %27[ 8 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %34[ 13 ]
+# CHECK: Vreg: %15[ 40 ]
+# CHECK: Vreg: %3[ 15 ]
+# CHECK: Vreg: %29[ LoopTag+58 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %17:sub0[ 4 ]
+# CHECK: Vreg: %17:sub1[ 5 ]
+# CHECK: Vreg: %81[ 8 ]
+# CHECK: Vreg: %126[ 0 ]
+# CHECK: Instr: %132:vgpr_32 = V_ASHRREV_I32_e64 31, %131, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %26[ 18 ]
+# CHECK: Vreg: %59:sub0[ 11 ]
+# CHECK: Vreg: %2[ 44 ]
+# CHECK: Vreg: %16[ 31 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+24 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+25 ]
+# CHECK: Vreg: %61[ 15 ]
+# CHECK: Vreg: %4[ LoopTag+30 ]
+# CHECK: Vreg: %49[ LoopTag+20 ]
+# CHECK: Vreg: %30[ LoopTag+31 ]
+# CHECK: Vreg: %18:sub0[ 22 ]
+# CHECK: Vreg: %18:sub1[ 23 ]
+# CHECK: Vreg: %63[ 13 ]
+# CHECK: Vreg: %32[ 33 ]
+# CHECK: Vreg: %84[ 11 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %34[ 12 ]
+# CHECK: Vreg: %15[ 39 ]
+# CHECK: Vreg: %3[ 14 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+57 ]
+# CHECK: Vreg: %67[ 8 ]
+# CHECK: Vreg: %17:sub0[ 3 ]
+# CHECK: Vreg: %17:sub1[ 4 ]
+# CHECK: Vreg: %81[ 7 ]
+# CHECK: Instr: %133:vreg_64 = REG_SEQUENCE %131, %subreg.sub0, killed %132, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %59:sub0[ 10 ]
+# CHECK: Vreg: %2[ 43 ]
+# CHECK: Vreg: %16[ 30 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+23 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+24 ]
+# CHECK: Vreg: %61[ 14 ]
+# CHECK: Vreg: %4[ LoopTag+29 ]
+# CHECK: Vreg: %49[ LoopTag+19 ]
+# CHECK: Vreg: %30[ LoopTag+30 ]
+# CHECK: Vreg: %132[ 0 ]
+# CHECK: Vreg: %18:sub0[ 21 ]
+# CHECK: Vreg: %18:sub1[ 22 ]
+# CHECK: Vreg: %63[ 12 ]
+# CHECK: Vreg: %32[ 32 ]
+# CHECK: Vreg: %84[ 10 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %34[ 11 ]
+# CHECK: Vreg: %15[ 38 ]
+# CHECK: Vreg: %3[ 13 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+56 ]
+# CHECK: Vreg: %67[ 7 ]
+# CHECK: Vreg: %17:sub0[ 2 ]
+# CHECK: Vreg: %17:sub1[ 3 ]
+# CHECK: Vreg: %81[ 6 ]
+# CHECK: Instr: %134:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %133, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %59:sub0[ 9 ]
+# CHECK: Vreg: %2[ 42 ]
+# CHECK: Vreg: %16[ 29 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+22 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+23 ]
+# CHECK: Vreg: %61[ 13 ]
+# CHECK: Vreg: %4[ LoopTag+28 ]
+# CHECK: Vreg: %49[ LoopTag+18 ]
+# CHECK: Vreg: %30[ LoopTag+29 ]
+# CHECK: Vreg: %18:sub0[ 20 ]
+# CHECK: Vreg: %18:sub1[ 21 ]
+# CHECK: Vreg: %63[ 11 ]
+# CHECK: Vreg: %32[ 31 ]
+# CHECK: Vreg: %84[ 9 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %34[ 10 ]
+# CHECK: Vreg: %15[ 37 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %131[ 8 ]
+# CHECK: Vreg: %29[ LoopTag+55 ]
+# CHECK: Vreg: %67[ 6 ]
+# CHECK: Vreg: %17:sub0[ 1 ]
+# CHECK: Vreg: %17:sub1[ 2 ]
+# CHECK: Vreg: %81[ 5 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Instr: %135:vgpr_32, %136:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %17.sub0, %134.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %26[ 15 ]
+# CHECK: Vreg: %59:sub0[ 8 ]
+# CHECK: Vreg: %2[ 41 ]
+# CHECK: Vreg: %16[ 28 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+21 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+22 ]
+# CHECK: Vreg: %61[ 12 ]
+# CHECK: Vreg: %4[ LoopTag+27 ]
+# CHECK: Vreg: %49[ LoopTag+17 ]
+# CHECK: Vreg: %30[ LoopTag+28 ]
+# CHECK: Vreg: %18:sub0[ 19 ]
+# CHECK: Vreg: %18:sub1[ 20 ]
+# CHECK: Vreg: %63[ 10 ]
+# CHECK: Vreg: %134:sub0[ 0 ]
+# CHECK: Vreg: %134:sub1[ 1 ]
+# CHECK: Vreg: %32[ 30 ]
+# CHECK: Vreg: %84[ 8 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %27[ 4 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %3[ 11 ]
+# CHECK: Vreg: %131[ 7 ]
+# CHECK: Vreg: %29[ LoopTag+54 ]
+# CHECK: Vreg: %67[ 5 ]
+# CHECK: Vreg: %17:sub0[ 0 ]
+# CHECK: Vreg: %17:sub1[ 1 ]
+# CHECK: Vreg: %81[ 4 ]
+# CHECK: Instr: %137:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %17.sub1, killed %134.sub1, killed %136, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %135[ 1 ]
+# CHECK: Vreg: %59:sub0[ 7 ]
+# CHECK: Vreg: %2[ 40 ]
+# CHECK: Vreg: %16[ 27 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+20 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+21 ]
+# CHECK: Vreg: %61[ 11 ]
+# CHECK: Vreg: %4[ LoopTag+26 ]
+# CHECK: Vreg: %49[ LoopTag+16 ]
+# CHECK: Vreg: %30[ LoopTag+27 ]
+# CHECK: Vreg: %18:sub0[ 18 ]
+# CHECK: Vreg: %18:sub1[ 19 ]
+# CHECK: Vreg: %63[ 9 ]
+# CHECK: Vreg: %134:sub1[ 0 ]
+# CHECK: Vreg: %32[ 29 ]
+# CHECK: Vreg: %84[ 7 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %136[ 0 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %15[ 35 ]
+# CHECK: Vreg: %3[ 10 ]
+# CHECK: Vreg: %131[ 6 ]
+# CHECK: Vreg: %29[ LoopTag+53 ]
+# CHECK: Vreg: %67[ 4 ]
+# CHECK: Vreg: %17:sub1[ 0 ]
+# CHECK: Vreg: %17:sub0[ 21 ]
+# CHECK: Vreg: %81[ 3 ]
+# CHECK: Instr: %138:vreg_64 = REG_SEQUENCE killed %135, %subreg.sub0, killed %137, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %26[ 13 ]
+# CHECK: Vreg: %135[ 0 ]
+# CHECK: Vreg: %59:sub0[ 6 ]
+# CHECK: Vreg: %2[ 39 ]
+# CHECK: Vreg: %137[ 0 ]
+# CHECK: Vreg: %16[ 26 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+19 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+20 ]
+# CHECK: Vreg: %61[ 10 ]
+# CHECK: Vreg: %4[ LoopTag+25 ]
+# CHECK: Vreg: %49[ LoopTag+15 ]
+# CHECK: Vreg: %30[ LoopTag+26 ]
+# CHECK: Vreg: %18:sub0[ 17 ]
+# CHECK: Vreg: %18:sub1[ 18 ]
+# CHECK: Vreg: %63[ 8 ]
+# CHECK: Vreg: %32[ 28 ]
+# CHECK: Vreg: %84[ 6 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %15[ 34 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %131[ 5 ]
+# CHECK: Vreg: %29[ LoopTag+52 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %17:sub0[ 20 ]
+# CHECK: Vreg: %17:sub1[ 21 ]
+# CHECK: Vreg: %81[ 2 ]
+# CHECK: Instr: %139:vgpr_32 = GLOBAL_LOAD_DWORD killed %138, 0, 0, implicit $exec :: (load (s32) from %ir.gep3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %59:sub0[ 5 ]
+# CHECK: Vreg: %2[ 38 ]
+# CHECK: Vreg: %16[ 25 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+18 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+19 ]
+# CHECK: Vreg: %61[ 9 ]
+# CHECK: Vreg: %4[ LoopTag+24 ]
+# CHECK: Vreg: %49[ LoopTag+14 ]
+# CHECK: Vreg: %30[ LoopTag+25 ]
+# CHECK: Vreg: %18:sub0[ 16 ]
+# CHECK: Vreg: %18:sub1[ 17 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %32[ 27 ]
+# CHECK: Vreg: %84[ 5 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %15[ 33 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Vreg: %131[ 4 ]
+# CHECK: Vreg: %29[ LoopTag+51 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %138[ 0 ]
+# CHECK: Vreg: %17:sub0[ 19 ]
+# CHECK: Vreg: %17:sub1[ 20 ]
+# CHECK: Vreg: %81[ 1 ]
+# CHECK: Instr: %140:vgpr_32 = V_ADD_U32_e64 killed %81, %27, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %59:sub0[ 4 ]
+# CHECK: Vreg: %2[ 37 ]
+# CHECK: Vreg: %16[ 24 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+17 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+18 ]
+# CHECK: Vreg: %61[ 8 ]
+# CHECK: Vreg: %4[ LoopTag+23 ]
+# CHECK: Vreg: %49[ LoopTag+13 ]
+# CHECK: Vreg: %30[ LoopTag+24 ]
+# CHECK: Vreg: %139[ 3 ]
+# CHECK: Vreg: %18:sub0[ 15 ]
+# CHECK: Vreg: %18:sub1[ 16 ]
+# CHECK: Vreg: %63[ 6 ]
+# CHECK: Vreg: %32[ 26 ]
+# CHECK: Vreg: %84[ 4 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %15[ 32 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Vreg: %131[ 3 ]
+# CHECK: Vreg: %29[ LoopTag+50 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %17:sub0[ 18 ]
+# CHECK: Vreg: %17:sub1[ 19 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Instr: %141:sreg_32 = V_CMP_LT_U32_e64 killed %140, killed %67, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %59:sub0[ 3 ]
+# CHECK: Vreg: %2[ 36 ]
+# CHECK: Vreg: %16[ 23 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+16 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+17 ]
+# CHECK: Vreg: %61[ 7 ]
+# CHECK: Vreg: %4[ LoopTag+22 ]
+# CHECK: Vreg: %49[ LoopTag+12 ]
+# CHECK: Vreg: %30[ LoopTag+23 ]
+# CHECK: Vreg: %139[ 2 ]
+# CHECK: Vreg: %18:sub0[ 14 ]
+# CHECK: Vreg: %18:sub1[ 15 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %32[ 25 ]
+# CHECK: Vreg: %84[ 3 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %27[ 52 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %15[ 31 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %131[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+49 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %17:sub0[ 17 ]
+# CHECK: Vreg: %17:sub1[ 18 ]
+# CHECK: Vreg: %140[ 0 ]
+# CHECK: Instr: %142:sreg_32 = SI_IF killed %141, %bb.17, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %59:sub0[ 2 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %16[ 22 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+15 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+16 ]
+# CHECK: Vreg: %61[ 6 ]
+# CHECK: Vreg: %4[ LoopTag+21 ]
+# CHECK: Vreg: %49[ LoopTag+11 ]
+# CHECK: Vreg: %30[ LoopTag+22 ]
+# CHECK: Vreg: %139[ 1 ]
+# CHECK: Vreg: %18:sub0[ 13 ]
+# CHECK: Vreg: %18:sub1[ 14 ]
+# CHECK: Vreg: %63[ 4 ]
+# CHECK: Vreg: %32[ 24 ]
+# CHECK: Vreg: %141[ 0 ]
+# CHECK: Vreg: %84[ 2 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ 51 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %15[ 30 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %131[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+48 ]
+# CHECK: Vreg: %17:sub0[ 16 ]
+# CHECK: Vreg: %17:sub1[ 17 ]
+# CHECK: Instr: S_BRANCH %bb.16
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %59:sub0[ 1 ]
+# CHECK: Vreg: %2[ 34 ]
+# CHECK: Vreg: %16[ 21 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+14 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+15 ]
+# CHECK: Vreg: %61[ 5 ]
+# CHECK: Vreg: %4[ LoopTag+20 ]
+# CHECK: Vreg: %49[ LoopTag+10 ]
+# CHECK: Vreg: %30[ LoopTag+21 ]
+# CHECK: Vreg: %139[ 0 ]
+# CHECK: Vreg: %18:sub0[ 12 ]
+# CHECK: Vreg: %18:sub1[ 13 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %32[ 23 ]
+# CHECK: Vreg: %84[ 1 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ 50 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+47 ]
+# CHECK: Vreg: %17:sub0[ 15 ]
+# CHECK: Vreg: %17:sub1[ 16 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %59:sub0[ 1 ]
+# CHECK: Vreg: %2[ 34 ]
+# CHECK: Vreg: %16[ 21 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+14 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+15 ]
+# CHECK: Vreg: %61[ 5 ]
+# CHECK: Vreg: %4[ LoopTag+20 ]
+# CHECK: Vreg: %49[ LoopTag+10 ]
+# CHECK: Vreg: %30[ LoopTag+21 ]
+# CHECK: Vreg: %139[ 0 ]
+# CHECK: Vreg: %18:sub0[ 12 ]
+# CHECK: Vreg: %18:sub1[ 13 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %32[ 23 ]
+# CHECK: Vreg: %84[ 1 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ 50 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+47 ]
+# CHECK: Vreg: %17:sub0[ 15 ]
+# CHECK: Vreg: %17:sub1[ 16 ]
+# CHECK: --- MBB_16 ---
+# CHECK: Instr: %143:vgpr_32 = V_MUL_HI_U32_e64 %84, %59.sub0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %26[ 28 ]
+# CHECK: Vreg: %142[ 21 ]
+# CHECK: Vreg: %59:sub0[ 0 ]
+# CHECK: Vreg: %2[ 54 ]
+# CHECK: Vreg: %16[ 20 ]
+# CHECK: Vreg: %61[ 25 ]
+# CHECK: Vreg: %4[ LoopTag+40 ]
+# CHECK: Vreg: %49[ LoopTag+30 ]
+# CHECK: Vreg: %30[ LoopTag+41 ]
+# CHECK: Vreg: %18:sub0[ 32 ]
+# CHECK: Vreg: %18:sub1[ 33 ]
+# CHECK: Vreg: %63[ 23 ]
+# CHECK: Vreg: %32[ 43 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %65[ 22 ]
+# CHECK: Vreg: %27[ 70 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 49 ]
+# CHECK: Vreg: %3[ 24 ]
+# CHECK: Vreg: %29[ LoopTag+67 ]
+# CHECK: Vreg: %17:sub0[ 14 ]
+# CHECK: Vreg: %17:sub1[ 15 ]
+# CHECK: Instr: %144:vgpr_32 = V_MUL_LO_U32_e64 %143, %34, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %26[ 27 ]
+# CHECK: Vreg: %142[ 20 ]
+# CHECK: Vreg: %59:sub0[ 73 ]
+# CHECK: Vreg: %2[ 53 ]
+# CHECK: Vreg: %16[ 19 ]
+# CHECK: Vreg: %61[ 24 ]
+# CHECK: Vreg: %4[ LoopTag+39 ]
+# CHECK: Vreg: %49[ LoopTag+29 ]
+# CHECK: Vreg: %30[ LoopTag+40 ]
+# CHECK: Vreg: %18:sub0[ 31 ]
+# CHECK: Vreg: %18:sub1[ 32 ]
+# CHECK: Vreg: %63[ 22 ]
+# CHECK: Vreg: %32[ 42 ]
+# CHECK: Vreg: %84[ 1 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %65[ 21 ]
+# CHECK: Vreg: %27[ 69 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 48 ]
+# CHECK: Vreg: %143[ 0 ]
+# CHECK: Vreg: %3[ 23 ]
+# CHECK: Vreg: %29[ LoopTag+66 ]
+# CHECK: Vreg: %17:sub0[ 13 ]
+# CHECK: Vreg: %17:sub1[ 14 ]
+# CHECK: Instr: %145:vgpr_32 = V_SUB_U32_e64 killed %84, killed %144, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %26[ 26 ]
+# CHECK: Vreg: %142[ 19 ]
+# CHECK: Vreg: %59:sub0[ 72 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %16[ 18 ]
+# CHECK: Vreg: %61[ 23 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %4[ LoopTag+38 ]
+# CHECK: Vreg: %49[ LoopTag+28 ]
+# CHECK: Vreg: %30[ LoopTag+39 ]
+# CHECK: Vreg: %18:sub0[ 30 ]
+# CHECK: Vreg: %18:sub1[ 31 ]
+# CHECK: Vreg: %63[ 21 ]
+# CHECK: Vreg: %32[ 41 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 20 ]
+# CHECK: Vreg: %27[ 68 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 47 ]
+# CHECK: Vreg: %143[ 2 ]
+# CHECK: Vreg: %3[ 22 ]
+# CHECK: Vreg: %29[ LoopTag+65 ]
+# CHECK: Vreg: %17:sub0[ 12 ]
+# CHECK: Vreg: %17:sub1[ 13 ]
+# CHECK: Instr: %146:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %34, %145, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %142[ 18 ]
+# CHECK: Vreg: %59:sub0[ 71 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %16[ 17 ]
+# CHECK: Vreg: %61[ 22 ]
+# CHECK: Vreg: %4[ LoopTag+37 ]
+# CHECK: Vreg: %49[ LoopTag+27 ]
+# CHECK: Vreg: %30[ LoopTag+38 ]
+# CHECK: Vreg: %18:sub0[ 29 ]
+# CHECK: Vreg: %18:sub1[ 30 ]
+# CHECK: Vreg: %63[ 20 ]
+# CHECK: Vreg: %32[ 40 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %65[ 19 ]
+# CHECK: Vreg: %27[ 67 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %143[ 1 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %29[ LoopTag+64 ]
+# CHECK: Vreg: %17:sub0[ 11 ]
+# CHECK: Vreg: %17:sub1[ 12 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Instr: %147:vgpr_32 = V_ADD_U32_e64 1, %143, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %142[ 17 ]
+# CHECK: Vreg: %59:sub0[ 70 ]
+# CHECK: Vreg: %2[ 50 ]
+# CHECK: Vreg: %16[ 16 ]
+# CHECK: Vreg: %61[ 21 ]
+# CHECK: Vreg: %4[ LoopTag+36 ]
+# CHECK: Vreg: %49[ LoopTag+26 ]
+# CHECK: Vreg: %30[ LoopTag+37 ]
+# CHECK: Vreg: %18:sub0[ 28 ]
+# CHECK: Vreg: %18:sub1[ 29 ]
+# CHECK: Vreg: %63[ 19 ]
+# CHECK: Vreg: %146[ 1 ]
+# CHECK: Vreg: %32[ 39 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %65[ 18 ]
+# CHECK: Vreg: %27[ 66 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %15[ 45 ]
+# CHECK: Vreg: %143[ 0 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %29[ LoopTag+63 ]
+# CHECK: Vreg: %17:sub0[ 10 ]
+# CHECK: Vreg: %17:sub1[ 11 ]
+# CHECK: Vreg: %145[ 2 ]
+# CHECK: Instr: %148:vgpr_32 = V_CNDMASK_B32_e64 0, killed %143, 0, killed %147, %146, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %26[ 23 ]
+# CHECK: Vreg: %142[ 16 ]
+# CHECK: Vreg: %59:sub0[ 69 ]
+# CHECK: Vreg: %2[ 49 ]
+# CHECK: Vreg: %16[ 15 ]
+# CHECK: Vreg: %61[ 20 ]
+# CHECK: Vreg: %4[ LoopTag+35 ]
+# CHECK: Vreg: %49[ LoopTag+25 ]
+# CHECK: Vreg: %30[ LoopTag+36 ]
+# CHECK: Vreg: %18:sub0[ 27 ]
+# CHECK: Vreg: %18:sub1[ 28 ]
+# CHECK: Vreg: %63[ 18 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %32[ 38 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %27[ 65 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 44 ]
+# CHECK: Vreg: %143[ 0 ]
+# CHECK: Vreg: %3[ 19 ]
+# CHECK: Vreg: %29[ LoopTag+62 ]
+# CHECK: Vreg: %17:sub0[ 9 ]
+# CHECK: Vreg: %17:sub1[ 10 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: %149:vgpr_32 = V_SUBREV_U32_e64 %34, %145, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %26[ 22 ]
+# CHECK: Vreg: %142[ 15 ]
+# CHECK: Vreg: %59:sub0[ 68 ]
+# CHECK: Vreg: %2[ 48 ]
+# CHECK: Vreg: %16[ 14 ]
+# CHECK: Vreg: %61[ 19 ]
+# CHECK: Vreg: %4[ LoopTag+34 ]
+# CHECK: Vreg: %49[ LoopTag+24 ]
+# CHECK: Vreg: %30[ LoopTag+35 ]
+# CHECK: Vreg: %18:sub0[ 26 ]
+# CHECK: Vreg: %18:sub1[ 27 ]
+# CHECK: Vreg: %63[ 17 ]
+# CHECK: Vreg: %146[ 1 ]
+# CHECK: Vreg: %32[ 37 ]
+# CHECK: Vreg: %148[ 3 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %27[ 64 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 43 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %29[ LoopTag+61 ]
+# CHECK: Vreg: %17:sub0[ 8 ]
+# CHECK: Vreg: %17:sub1[ 9 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Instr: %150:vgpr_32 = V_CNDMASK_B32_e64 0, killed %145, 0, killed %149, killed %146, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %26[ 21 ]
+# CHECK: Vreg: %142[ 14 ]
+# CHECK: Vreg: %59:sub0[ 67 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %2[ 47 ]
+# CHECK: Vreg: %16[ 13 ]
+# CHECK: Vreg: %61[ 18 ]
+# CHECK: Vreg: %4[ LoopTag+33 ]
+# CHECK: Vreg: %49[ LoopTag+23 ]
+# CHECK: Vreg: %30[ LoopTag+34 ]
+# CHECK: Vreg: %18:sub0[ 25 ]
+# CHECK: Vreg: %18:sub1[ 26 ]
+# CHECK: Vreg: %63[ 16 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %32[ 36 ]
+# CHECK: Vreg: %148[ 2 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %27[ 63 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 42 ]
+# CHECK: Vreg: %3[ 17 ]
+# CHECK: Vreg: %29[ LoopTag+60 ]
+# CHECK: Vreg: %17:sub0[ 7 ]
+# CHECK: Vreg: %17:sub1[ 8 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Instr: %151:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %34, killed %150, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %26[ 20 ]
+# CHECK: Vreg: %142[ 13 ]
+# CHECK: Vreg: %59:sub0[ 66 ]
+# CHECK: Vreg: %2[ 46 ]
+# CHECK: Vreg: %16[ 12 ]
+# CHECK: Vreg: %61[ 17 ]
+# CHECK: Vreg: %4[ LoopTag+32 ]
+# CHECK: Vreg: %49[ LoopTag+22 ]
+# CHECK: Vreg: %30[ LoopTag+33 ]
+# CHECK: Vreg: %18:sub0[ 24 ]
+# CHECK: Vreg: %18:sub1[ 25 ]
+# CHECK: Vreg: %63[ 15 ]
+# CHECK: Vreg: %32[ 35 ]
+# CHECK: Vreg: %148[ 1 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %27[ 62 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 41 ]
+# CHECK: Vreg: %150[ 0 ]
+# CHECK: Vreg: %3[ 16 ]
+# CHECK: Vreg: %29[ LoopTag+59 ]
+# CHECK: Vreg: %17:sub0[ 6 ]
+# CHECK: Vreg: %17:sub1[ 7 ]
+# CHECK: Instr: %152:vgpr_32 = V_ADD_U32_e64 1, %148, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %26[ 19 ]
+# CHECK: Vreg: %142[ 12 ]
+# CHECK: Vreg: %59:sub0[ 65 ]
+# CHECK: Vreg: %2[ 45 ]
+# CHECK: Vreg: %16[ 11 ]
+# CHECK: Vreg: %61[ 16 ]
+# CHECK: Vreg: %151[ 1 ]
+# CHECK: Vreg: %4[ LoopTag+31 ]
+# CHECK: Vreg: %49[ LoopTag+21 ]
+# CHECK: Vreg: %30[ LoopTag+32 ]
+# CHECK: Vreg: %18:sub0[ 23 ]
+# CHECK: Vreg: %18:sub1[ 24 ]
+# CHECK: Vreg: %63[ 14 ]
+# CHECK: Vreg: %32[ 34 ]
+# CHECK: Vreg: %148[ 0 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %27[ 61 ]
+# CHECK: Vreg: %34[ 43 ]
+# CHECK: Vreg: %15[ 40 ]
+# CHECK: Vreg: %3[ 15 ]
+# CHECK: Vreg: %29[ LoopTag+58 ]
+# CHECK: Vreg: %17:sub0[ 5 ]
+# CHECK: Vreg: %17:sub1[ 6 ]
+# CHECK: Instr: %153:vgpr_32 = V_CNDMASK_B32_e64 0, killed %148, 0, killed %152, killed %151, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %26[ 18 ]
+# CHECK: Vreg: %142[ 11 ]
+# CHECK: Vreg: %59:sub0[ 64 ]
+# CHECK: Vreg: %2[ 44 ]
+# CHECK: Vreg: %16[ 10 ]
+# CHECK: Vreg: %61[ 15 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %4[ LoopTag+30 ]
+# CHECK: Vreg: %49[ LoopTag+20 ]
+# CHECK: Vreg: %30[ LoopTag+31 ]
+# CHECK: Vreg: %18:sub0[ 22 ]
+# CHECK: Vreg: %18:sub1[ 23 ]
+# CHECK: Vreg: %63[ 13 ]
+# CHECK: Vreg: %32[ 33 ]
+# CHECK: Vreg: %148[ 0 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %27[ 60 ]
+# CHECK: Vreg: %34[ 42 ]
+# CHECK: Vreg: %15[ 39 ]
+# CHECK: Vreg: %3[ 14 ]
+# CHECK: Vreg: %29[ LoopTag+57 ]
+# CHECK: Vreg: %17:sub0[ 4 ]
+# CHECK: Vreg: %17:sub1[ 5 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Instr: %154:vgpr_32 = V_ASHRREV_I32_e64 31, %153, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %142[ 10 ]
+# CHECK: Vreg: %59:sub0[ 63 ]
+# CHECK: Vreg: %2[ 43 ]
+# CHECK: Vreg: %16[ 9 ]
+# CHECK: Vreg: %61[ 14 ]
+# CHECK: Vreg: %4[ LoopTag+29 ]
+# CHECK: Vreg: %49[ LoopTag+19 ]
+# CHECK: Vreg: %30[ LoopTag+30 ]
+# CHECK: Vreg: %18:sub0[ 21 ]
+# CHECK: Vreg: %18:sub1[ 22 ]
+# CHECK: Vreg: %63[ 12 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %32[ 32 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %27[ 59 ]
+# CHECK: Vreg: %34[ 41 ]
+# CHECK: Vreg: %15[ 38 ]
+# CHECK: Vreg: %3[ 13 ]
+# CHECK: Vreg: %29[ LoopTag+56 ]
+# CHECK: Vreg: %17:sub0[ 3 ]
+# CHECK: Vreg: %17:sub1[ 4 ]
+# CHECK: Instr: %155:vreg_64 = REG_SEQUENCE %153, %subreg.sub0, killed %154, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %154[ 0 ]
+# CHECK: Vreg: %142[ 9 ]
+# CHECK: Vreg: %59:sub0[ 62 ]
+# CHECK: Vreg: %2[ 42 ]
+# CHECK: Vreg: %16[ 8 ]
+# CHECK: Vreg: %61[ 13 ]
+# CHECK: Vreg: %4[ LoopTag+28 ]
+# CHECK: Vreg: %49[ LoopTag+18 ]
+# CHECK: Vreg: %30[ LoopTag+29 ]
+# CHECK: Vreg: %18:sub0[ 20 ]
+# CHECK: Vreg: %18:sub1[ 21 ]
+# CHECK: Vreg: %63[ 11 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %32[ 31 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %27[ 58 ]
+# CHECK: Vreg: %34[ 40 ]
+# CHECK: Vreg: %15[ 37 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %29[ LoopTag+55 ]
+# CHECK: Vreg: %17:sub0[ 2 ]
+# CHECK: Vreg: %17:sub1[ 3 ]
+# CHECK: Instr: %156:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %155, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %26[ 15 ]
+# CHECK: Vreg: %142[ 8 ]
+# CHECK: Vreg: %59:sub0[ 61 ]
+# CHECK: Vreg: %2[ 41 ]
+# CHECK: Vreg: %16[ 7 ]
+# CHECK: Vreg: %61[ 12 ]
+# CHECK: Vreg: %4[ LoopTag+27 ]
+# CHECK: Vreg: %49[ LoopTag+17 ]
+# CHECK: Vreg: %30[ LoopTag+28 ]
+# CHECK: Vreg: %18:sub0[ 19 ]
+# CHECK: Vreg: %18:sub1[ 20 ]
+# CHECK: Vreg: %63[ 10 ]
+# CHECK: Vreg: %153[ 7 ]
+# CHECK: Vreg: %32[ 30 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %27[ 57 ]
+# CHECK: Vreg: %155[ 0 ]
+# CHECK: Vreg: %34[ 39 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %3[ 11 ]
+# CHECK: Vreg: %29[ LoopTag+54 ]
+# CHECK: Vreg: %17:sub0[ 1 ]
+# CHECK: Vreg: %17:sub1[ 2 ]
+# CHECK: Instr: %157:vgpr_32, %158:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %17.sub0, %156.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %142[ 7 ]
+# CHECK: Vreg: %59:sub0[ 60 ]
+# CHECK: Vreg: %2[ 40 ]
+# CHECK: Vreg: %156:sub0[ 0 ]
+# CHECK: Vreg: %156:sub1[ 1 ]
+# CHECK: Vreg: %16[ 6 ]
+# CHECK: Vreg: %61[ 11 ]
+# CHECK: Vreg: %4[ LoopTag+26 ]
+# CHECK: Vreg: %49[ LoopTag+16 ]
+# CHECK: Vreg: %30[ LoopTag+27 ]
+# CHECK: Vreg: %18:sub0[ 18 ]
+# CHECK: Vreg: %18:sub1[ 19 ]
+# CHECK: Vreg: %63[ 9 ]
+# CHECK: Vreg: %153[ 6 ]
+# CHECK: Vreg: %32[ 29 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %27[ 56 ]
+# CHECK: Vreg: %34[ 38 ]
+# CHECK: Vreg: %15[ 35 ]
+# CHECK: Vreg: %3[ 10 ]
+# CHECK: Vreg: %29[ LoopTag+53 ]
+# CHECK: Vreg: %17:sub0[ 0 ]
+# CHECK: Vreg: %17:sub1[ 1 ]
+# CHECK: Instr: %159:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %17.sub1, killed %156.sub1, killed %158, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %26[ 13 ]
+# CHECK: Vreg: %142[ 6 ]
+# CHECK: Vreg: %59:sub0[ 59 ]
+# CHECK: Vreg: %2[ 39 ]
+# CHECK: Vreg: %156:sub1[ 0 ]
+# CHECK: Vreg: %16[ 5 ]
+# CHECK: Vreg: %61[ 10 ]
+# CHECK: Vreg: %4[ LoopTag+25 ]
+# CHECK: Vreg: %49[ LoopTag+15 ]
+# CHECK: Vreg: %30[ LoopTag+26 ]
+# CHECK: Vreg: %158[ 0 ]
+# CHECK: Vreg: %18:sub0[ 17 ]
+# CHECK: Vreg: %18:sub1[ 18 ]
+# CHECK: Vreg: %63[ 8 ]
+# CHECK: Vreg: %153[ 5 ]
+# CHECK: Vreg: %32[ 28 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %27[ 55 ]
+# CHECK: Vreg: %34[ 37 ]
+# CHECK: Vreg: %15[ 34 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %29[ LoopTag+52 ]
+# CHECK: Vreg: %157[ 1 ]
+# CHECK: Vreg: %17:sub1[ 0 ]
+# CHECK: Vreg: %17:sub0[ 51 ]
+# CHECK: Instr: %160:vreg_64 = REG_SEQUENCE killed %157, %subreg.sub0, killed %159, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %142[ 5 ]
+# CHECK: Vreg: %59:sub0[ 58 ]
+# CHECK: Vreg: %2[ 38 ]
+# CHECK: Vreg: %16[ 4 ]
+# CHECK: Vreg: %61[ 9 ]
+# CHECK: Vreg: %4[ LoopTag+24 ]
+# CHECK: Vreg: %49[ LoopTag+14 ]
+# CHECK: Vreg: %30[ LoopTag+25 ]
+# CHECK: Vreg: %18:sub0[ 16 ]
+# CHECK: Vreg: %18:sub1[ 17 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %153[ 4 ]
+# CHECK: Vreg: %32[ 27 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %27[ 54 ]
+# CHECK: Vreg: %34[ 36 ]
+# CHECK: Vreg: %15[ 33 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Vreg: %29[ LoopTag+51 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %17:sub0[ 50 ]
+# CHECK: Vreg: %17:sub1[ 51 ]
+# CHECK: Vreg: %159[ 0 ]
+# CHECK: Instr: %161:vgpr_32 = GLOBAL_LOAD_USHORT %160, 0, 0, implicit $exec :: (load (s16) from %ir.gep4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %142[ 4 ]
+# CHECK: Vreg: %59:sub0[ 57 ]
+# CHECK: Vreg: %2[ 37 ]
+# CHECK: Vreg: %16[ 3 ]
+# CHECK: Vreg: %61[ 8 ]
+# CHECK: Vreg: %4[ LoopTag+23 ]
+# CHECK: Vreg: %49[ LoopTag+13 ]
+# CHECK: Vreg: %30[ LoopTag+24 ]
+# CHECK: Vreg: %18:sub0[ 15 ]
+# CHECK: Vreg: %18:sub1[ 16 ]
+# CHECK: Vreg: %63[ 6 ]
+# CHECK: Vreg: %153[ 3 ]
+# CHECK: Vreg: %32[ 26 ]
+# CHECK: Vreg: %160[ 0 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %27[ 53 ]
+# CHECK: Vreg: %34[ 35 ]
+# CHECK: Vreg: %15[ 32 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Vreg: %29[ LoopTag+50 ]
+# CHECK: Vreg: %17:sub0[ 49 ]
+# CHECK: Vreg: %17:sub1[ 50 ]
+# CHECK: Instr: %162:vgpr_32 = GLOBAL_LOAD_USHORT killed %160, 2, 0, implicit $exec :: (load (s16) from %ir.gep4 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %161[ 1 ]
+# CHECK: Vreg: %142[ 3 ]
+# CHECK: Vreg: %59:sub0[ 56 ]
+# CHECK: Vreg: %2[ 36 ]
+# CHECK: Vreg: %16[ 2 ]
+# CHECK: Vreg: %61[ 7 ]
+# CHECK: Vreg: %4[ LoopTag+22 ]
+# CHECK: Vreg: %49[ LoopTag+12 ]
+# CHECK: Vreg: %30[ LoopTag+23 ]
+# CHECK: Vreg: %18:sub0[ 14 ]
+# CHECK: Vreg: %18:sub1[ 15 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %153[ 2 ]
+# CHECK: Vreg: %32[ 25 ]
+# CHECK: Vreg: %160[ 0 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %27[ 52 ]
+# CHECK: Vreg: %34[ 34 ]
+# CHECK: Vreg: %15[ 31 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %29[ LoopTag+49 ]
+# CHECK: Vreg: %17:sub0[ 48 ]
+# CHECK: Vreg: %17:sub1[ 49 ]
+# CHECK: Instr: %163:vgpr_32 = V_LSHL_OR_B32_e64 killed %162, 16, killed %161, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %142[ 2 ]
+# CHECK: Vreg: %59:sub0[ 55 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %61[ 6 ]
+# CHECK: Vreg: %4[ LoopTag+21 ]
+# CHECK: Vreg: %49[ LoopTag+11 ]
+# CHECK: Vreg: %30[ LoopTag+22 ]
+# CHECK: Vreg: %18:sub0[ 13 ]
+# CHECK: Vreg: %18:sub1[ 14 ]
+# CHECK: Vreg: %63[ 4 ]
+# CHECK: Vreg: %153[ 1 ]
+# CHECK: Vreg: %32[ 24 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %27[ 51 ]
+# CHECK: Vreg: %34[ 33 ]
+# CHECK: Vreg: %15[ 30 ]
+# CHECK: Vreg: %162[ 0 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %29[ LoopTag+48 ]
+# CHECK: Vreg: %17:sub0[ 47 ]
+# CHECK: Vreg: %17:sub1[ 48 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %16, %163, 0, 0, implicit $exec :: (store (s32) into %ir.p4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %59:sub0[ 54 ]
+# CHECK: Vreg: %2[ 34 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %61[ 5 ]
+# CHECK: Vreg: %4[ LoopTag+20 ]
+# CHECK: Vreg: %49[ LoopTag+10 ]
+# CHECK: Vreg: %30[ LoopTag+21 ]
+# CHECK: Vreg: %18:sub0[ 12 ]
+# CHECK: Vreg: %18:sub1[ 13 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %32[ 23 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ 50 ]
+# CHECK: Vreg: %34[ 32 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %29[ LoopTag+47 ]
+# CHECK: Vreg: %17:sub0[ 46 ]
+# CHECK: Vreg: %17:sub1[ 47 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %59:sub0[ 54 ]
+# CHECK: Vreg: %2[ 34 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %16[ 74 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+14 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+15 ]
+# CHECK: Vreg: %61[ 5 ]
+# CHECK: Vreg: %4[ LoopTag+20 ]
+# CHECK: Vreg: %49[ LoopTag+10 ]
+# CHECK: Vreg: %30[ LoopTag+21 ]
+# CHECK: Vreg: %18:sub0[ 12 ]
+# CHECK: Vreg: %18:sub1[ 13 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %32[ 23 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ 50 ]
+# CHECK: Vreg: %34[ 32 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %29[ LoopTag+47 ]
+# CHECK: Vreg: %17:sub0[ 46 ]
+# CHECK: Vreg: %17:sub1[ 47 ]
+# CHECK: --- MBB_17 ---
+# CHECK: Instr: %164:vgpr_32 = PHI %139, %bb.15, %163, %bb.16
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %59:sub0[ 54 ]
+# CHECK: Vreg: %2[ 34 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %16[ 74 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+14 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+15 ]
+# CHECK: Vreg: %61[ 5 ]
+# CHECK: Vreg: %4[ LoopTag+20 ]
+# CHECK: Vreg: %49[ LoopTag+10 ]
+# CHECK: Vreg: %30[ LoopTag+21 ]
+# CHECK: Vreg: %139[ 0 ]
+# CHECK: Vreg: %18:sub0[ 12 ]
+# CHECK: Vreg: %18:sub1[ 13 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %32[ 23 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ 50 ]
+# CHECK: Vreg: %34[ 32 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+47 ]
+# CHECK: Vreg: %17:sub0[ 46 ]
+# CHECK: Vreg: %17:sub1[ 47 ]
+# CHECK: Instr: %165:vgpr_32 = PHI %131, %bb.15, %153, %bb.16
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %59:sub0[ 54 ]
+# CHECK: Vreg: %2[ 34 ]
+# CHECK: Vreg: %16[ 74 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+14 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+15 ]
+# CHECK: Vreg: %61[ 5 ]
+# CHECK: Vreg: %4[ LoopTag+20 ]
+# CHECK: Vreg: %49[ LoopTag+10 ]
+# CHECK: Vreg: %30[ LoopTag+21 ]
+# CHECK: Vreg: %18:sub0[ 12 ]
+# CHECK: Vreg: %18:sub1[ 13 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %32[ 23 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %27[ 50 ]
+# CHECK: Vreg: %34[ 32 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+47 ]
+# CHECK: Vreg: %164[ LoopTag*2+25 ]
+# CHECK: Vreg: %17:sub0[ 46 ]
+# CHECK: Vreg: %17:sub1[ 47 ]
+# CHECK: Instr: SI_END_CF killed %142, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %26[ 7 ]
+# CHECK: Vreg: %142[ 0 ]
+# CHECK: Vreg: %59:sub0[ 53 ]
+# CHECK: Vreg: %2[ 33 ]
+# CHECK: Vreg: %16[ 73 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+13 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+14 ]
+# CHECK: Vreg: %61[ 4 ]
+# CHECK: Vreg: %4[ LoopTag+19 ]
+# CHECK: Vreg: %49[ LoopTag+9 ]
+# CHECK: Vreg: %30[ LoopTag+20 ]
+# CHECK: Vreg: %165[ LoopTag+10 ]
+# CHECK: Vreg: %18:sub0[ 11 ]
+# CHECK: Vreg: %18:sub1[ 12 ]
+# CHECK: Vreg: %63[ 2 ]
+# CHECK: Vreg: %32[ 22 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %27[ 49 ]
+# CHECK: Vreg: %34[ 31 ]
+# CHECK: Vreg: %15[ 28 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Vreg: %29[ LoopTag+46 ]
+# CHECK: Vreg: %164[ LoopTag*2+24 ]
+# CHECK: Vreg: %17:sub0[ 45 ]
+# CHECK: Vreg: %17:sub1[ 46 ]
+# CHECK: Instr: %66:sreg_32 = S_ADD_I32 killed %65, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %59:sub0[ 52 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %16[ 72 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+12 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+13 ]
+# CHECK: Vreg: %61[ 3 ]
+# CHECK: Vreg: %4[ LoopTag+18 ]
+# CHECK: Vreg: %49[ LoopTag+8 ]
+# CHECK: Vreg: %30[ LoopTag+19 ]
+# CHECK: Vreg: %165[ LoopTag+9 ]
+# CHECK: Vreg: %18:sub0[ 10 ]
+# CHECK: Vreg: %18:sub1[ 11 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %32[ 21 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 48 ]
+# CHECK: Vreg: %34[ 30 ]
+# CHECK: Vreg: %15[ 27 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+45 ]
+# CHECK: Vreg: %164[ LoopTag*2+23 ]
+# CHECK: Vreg: %17:sub0[ 44 ]
+# CHECK: Vreg: %17:sub1[ 45 ]
+# CHECK: Instr: %64:sreg_32 = S_ADD_I32 killed %63, 10, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %59:sub0[ 51 ]
+# CHECK: Vreg: %2[ 31 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %16[ 71 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+11 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+12 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %4[ LoopTag+17 ]
+# CHECK: Vreg: %49[ LoopTag+7 ]
+# CHECK: Vreg: %30[ LoopTag+18 ]
+# CHECK: Vreg: %165[ LoopTag+8 ]
+# CHECK: Vreg: %18:sub0[ 9 ]
+# CHECK: Vreg: %18:sub1[ 10 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %32[ 20 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %27[ 47 ]
+# CHECK: Vreg: %34[ 29 ]
+# CHECK: Vreg: %15[ 26 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+44 ]
+# CHECK: Vreg: %164[ LoopTag*2+22 ]
+# CHECK: Vreg: %17:sub0[ 43 ]
+# CHECK: Vreg: %17:sub1[ 44 ]
+# CHECK: Instr: %166:sreg_32 = V_CMP_GE_U32_e64 %66, %3, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %64[ 3 ]
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %59:sub0[ 50 ]
+# CHECK: Vreg: %2[ 30 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %16[ 70 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+10 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+11 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %4[ LoopTag+16 ]
+# CHECK: Vreg: %49[ LoopTag+6 ]
+# CHECK: Vreg: %30[ LoopTag+17 ]
+# CHECK: Vreg: %165[ LoopTag+7 ]
+# CHECK: Vreg: %18:sub0[ 8 ]
+# CHECK: Vreg: %18:sub1[ 9 ]
+# CHECK: Vreg: %32[ 19 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %27[ 46 ]
+# CHECK: Vreg: %34[ 28 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+43 ]
+# CHECK: Vreg: %164[ LoopTag*2+21 ]
+# CHECK: Vreg: %17:sub0[ 42 ]
+# CHECK: Vreg: %17:sub1[ 43 ]
+# CHECK: Instr: %62:sreg_32 = SI_IF_BREAK killed %166, killed %61, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %64[ 2 ]
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %59:sub0[ 49 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %66[ 2 ]
+# CHECK: Vreg: %16[ 69 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+9 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+10 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %4[ LoopTag+15 ]
+# CHECK: Vreg: %49[ LoopTag+5 ]
+# CHECK: Vreg: %30[ LoopTag+16 ]
+# CHECK: Vreg: %165[ LoopTag+6 ]
+# CHECK: Vreg: %18:sub0[ 7 ]
+# CHECK: Vreg: %18:sub1[ 8 ]
+# CHECK: Vreg: %32[ 18 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %27[ 45 ]
+# CHECK: Vreg: %34[ 27 ]
+# CHECK: Vreg: %15[ 24 ]
+# CHECK: Vreg: %3[ 52 ]
+# CHECK: Vreg: %29[ LoopTag+42 ]
+# CHECK: Vreg: %164[ LoopTag*2+20 ]
+# CHECK: Vreg: %17:sub0[ 41 ]
+# CHECK: Vreg: %17:sub1[ 42 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Instr: SI_LOOP %62, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %59:sub0[ 48 ]
+# CHECK: Vreg: %2[ 28 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %16[ 68 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+8 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+9 ]
+# CHECK: Vreg: %4[ LoopTag+14 ]
+# CHECK: Vreg: %49[ LoopTag+4 ]
+# CHECK: Vreg: %30[ LoopTag+15 ]
+# CHECK: Vreg: %165[ LoopTag+5 ]
+# CHECK: Vreg: %18:sub0[ 6 ]
+# CHECK: Vreg: %18:sub1[ 7 ]
+# CHECK: Vreg: %32[ 17 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %27[ 44 ]
+# CHECK: Vreg: %34[ 26 ]
+# CHECK: Vreg: %15[ 23 ]
+# CHECK: Vreg: %3[ 51 ]
+# CHECK: Vreg: %29[ LoopTag+41 ]
+# CHECK: Vreg: %164[ LoopTag*2+19 ]
+# CHECK: Vreg: %17:sub0[ 40 ]
+# CHECK: Vreg: %17:sub1[ 41 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.18
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %59:sub0[ 47 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %16[ 67 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+7 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+8 ]
+# CHECK: Vreg: %4[ LoopTag+13 ]
+# CHECK: Vreg: %49[ LoopTag+3 ]
+# CHECK: Vreg: %30[ LoopTag+14 ]
+# CHECK: Vreg: %165[ LoopTag+4 ]
+# CHECK: Vreg: %18:sub0[ 5 ]
+# CHECK: Vreg: %18:sub1[ 6 ]
+# CHECK: Vreg: %32[ 16 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %27[ 43 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %29[ LoopTag+40 ]
+# CHECK: Vreg: %164[ LoopTag*2+18 ]
+# CHECK: Vreg: %17:sub0[ 39 ]
+# CHECK: Vreg: %17:sub1[ 40 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %59:sub0[ 47 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %16[ 67 ]
+# CHECK: Vreg: %16:sub0[ LoopTag+7 ]
+# CHECK: Vreg: %16:sub1[ LoopTag+8 ]
+# CHECK: Vreg: %4[ LoopTag+13 ]
+# CHECK: Vreg: %49[ LoopTag+3 ]
+# CHECK: Vreg: %30[ LoopTag+14 ]
+# CHECK: Vreg: %165[ LoopTag+4 ]
+# CHECK: Vreg: %18:sub0[ 5 ]
+# CHECK: Vreg: %18:sub1[ 6 ]
+# CHECK: Vreg: %32[ 16 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %27[ 43 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %29[ LoopTag+40 ]
+# CHECK: Vreg: %164[ LoopTag*2+18 ]
+# CHECK: Vreg: %17:sub0[ 39 ]
+# CHECK: Vreg: %17:sub1[ 40 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: --- MBB_18 ---
+# CHECK: Instr: SI_END_CF killed %62, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 48 ]
+# CHECK: Vreg: %26[ 40 ]
+# CHECK: Vreg: %2[ 66 ]
+# CHECK: Vreg: %16:sub0[ 6 ]
+# CHECK: Vreg: %16:sub1[ 7 ]
+# CHECK: Vreg: %16[ 106 ]
+# CHECK: Vreg: %4[ 12 ]
+# CHECK: Vreg: %49[ 2 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %165[ 3 ]
+# CHECK: Vreg: %18:sub0[ 19 ]
+# CHECK: Vreg: %18:sub1[ 20 ]
+# CHECK: Vreg: %32[ 11 ]
+# CHECK: Vreg: %1[ 56 ]
+# CHECK: Vreg: %27[ 82 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 61 ]
+# CHECK: Vreg: %3[ 89 ]
+# CHECK: Vreg: %29[ 39 ]
+# CHECK: Vreg: %164[ LoopTag+17 ]
+# CHECK: Vreg: %17:sub0[ 78 ]
+# CHECK: Vreg: %17:sub1[ 79 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Instr: %35:sreg_32 = S_ADD_I32 killed %34, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %26[ 39 ]
+# CHECK: Vreg: %2[ 65 ]
+# CHECK: Vreg: %16:sub0[ 5 ]
+# CHECK: Vreg: %16:sub1[ 6 ]
+# CHECK: Vreg: %16[ 105 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %30[ 12 ]
+# CHECK: Vreg: %165[ 2 ]
+# CHECK: Vreg: %18:sub0[ 18 ]
+# CHECK: Vreg: %18:sub1[ 19 ]
+# CHECK: Vreg: %32[ 10 ]
+# CHECK: Vreg: %1[ 55 ]
+# CHECK: Vreg: %27[ 81 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 60 ]
+# CHECK: Vreg: %3[ 88 ]
+# CHECK: Vreg: %29[ 38 ]
+# CHECK: Vreg: %164[ LoopTag+16 ]
+# CHECK: Vreg: %17:sub0[ 77 ]
+# CHECK: Vreg: %17:sub1[ 78 ]
+# CHECK: Instr: %167:vgpr_32 = V_ADD_U32_e64 %35, %49, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %26[ 38 ]
+# CHECK: Vreg: %2[ 64 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %16:sub0[ 4 ]
+# CHECK: Vreg: %16:sub1[ 5 ]
+# CHECK: Vreg: %16[ 104 ]
+# CHECK: Vreg: %4[ 10 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %30[ 11 ]
+# CHECK: Vreg: %165[ 1 ]
+# CHECK: Vreg: %18:sub0[ 17 ]
+# CHECK: Vreg: %18:sub1[ 18 ]
+# CHECK: Vreg: %32[ 9 ]
+# CHECK: Vreg: %1[ 54 ]
+# CHECK: Vreg: %27[ 80 ]
+# CHECK: Vreg: %15[ 59 ]
+# CHECK: Vreg: %3[ 87 ]
+# CHECK: Vreg: %29[ 37 ]
+# CHECK: Vreg: %164[ LoopTag+15 ]
+# CHECK: Vreg: %17:sub0[ 76 ]
+# CHECK: Vreg: %17:sub1[ 77 ]
+# CHECK: Instr: %168:vgpr_32 = V_ASHRREV_I32_e64 31, %165, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %26[ 37 ]
+# CHECK: Vreg: %2[ 63 ]
+# CHECK: Vreg: %35[ 9 ]
+# CHECK: Vreg: %16:sub0[ 3 ]
+# CHECK: Vreg: %16:sub1[ 4 ]
+# CHECK: Vreg: %16[ 103 ]
+# CHECK: Vreg: %4[ 9 ]
+# CHECK: Vreg: %49[ LoopTag+14 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %165[ 0 ]
+# CHECK: Vreg: %18:sub0[ 16 ]
+# CHECK: Vreg: %18:sub1[ 17 ]
+# CHECK: Vreg: %32[ 8 ]
+# CHECK: Vreg: %167[ 6 ]
+# CHECK: Vreg: %1[ 53 ]
+# CHECK: Vreg: %27[ 79 ]
+# CHECK: Vreg: %15[ 58 ]
+# CHECK: Vreg: %3[ 86 ]
+# CHECK: Vreg: %29[ 36 ]
+# CHECK: Vreg: %164[ LoopTag+14 ]
+# CHECK: Vreg: %17:sub0[ 75 ]
+# CHECK: Vreg: %17:sub1[ 76 ]
+# CHECK: Instr: %169:vreg_64 = REG_SEQUENCE killed %165, %subreg.sub0, killed %168, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 44 ]
+# CHECK: Vreg: %26[ 36 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %2[ 62 ]
+# CHECK: Vreg: %35[ 8 ]
+# CHECK: Vreg: %16:sub0[ 2 ]
+# CHECK: Vreg: %16:sub1[ 3 ]
+# CHECK: Vreg: %16[ 102 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %49[ LoopTag+13 ]
+# CHECK: Vreg: %30[ 9 ]
+# CHECK: Vreg: %165[ 0 ]
+# CHECK: Vreg: %18:sub0[ 15 ]
+# CHECK: Vreg: %18:sub1[ 16 ]
+# CHECK: Vreg: %32[ 7 ]
+# CHECK: Vreg: %167[ 5 ]
+# CHECK: Vreg: %1[ 52 ]
+# CHECK: Vreg: %27[ 78 ]
+# CHECK: Vreg: %15[ 57 ]
+# CHECK: Vreg: %3[ 85 ]
+# CHECK: Vreg: %29[ 35 ]
+# CHECK: Vreg: %164[ LoopTag+13 ]
+# CHECK: Vreg: %17:sub0[ 74 ]
+# CHECK: Vreg: %17:sub1[ 75 ]
+# CHECK: Instr: %170:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %169, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Vreg: %26[ 35 ]
+# CHECK: Vreg: %2[ 61 ]
+# CHECK: Vreg: %35[ 7 ]
+# CHECK: Vreg: %16:sub0[ 1 ]
+# CHECK: Vreg: %16:sub1[ 2 ]
+# CHECK: Vreg: %16[ 101 ]
+# CHECK: Vreg: %4[ 7 ]
+# CHECK: Vreg: %49[ LoopTag+12 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %18:sub0[ 14 ]
+# CHECK: Vreg: %18:sub1[ 15 ]
+# CHECK: Vreg: %32[ 6 ]
+# CHECK: Vreg: %167[ 4 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %27[ 77 ]
+# CHECK: Vreg: %15[ 56 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ 84 ]
+# CHECK: Vreg: %29[ 34 ]
+# CHECK: Vreg: %164[ LoopTag+12 ]
+# CHECK: Vreg: %17:sub0[ 73 ]
+# CHECK: Vreg: %17:sub1[ 74 ]
+# CHECK: Instr: %171:vgpr_32, %172:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %16.sub0, %170.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 42 ]
+# CHECK: Vreg: %26[ 34 ]
+# CHECK: Vreg: %2[ 60 ]
+# CHECK: Vreg: %35[ 6 ]
+# CHECK: Vreg: %16:sub0[ 0 ]
+# CHECK: Vreg: %16:sub1[ 1 ]
+# CHECK: Vreg: %16[ 100 ]
+# CHECK: Vreg: %170:sub0[ 0 ]
+# CHECK: Vreg: %170:sub1[ 1 ]
+# CHECK: Vreg: %4[ 6 ]
+# CHECK: Vreg: %49[ LoopTag+11 ]
+# CHECK: Vreg: %30[ 7 ]
+# CHECK: Vreg: %18:sub0[ 13 ]
+# CHECK: Vreg: %18:sub1[ 14 ]
+# CHECK: Vreg: %32[ 5 ]
+# CHECK: Vreg: %167[ 3 ]
+# CHECK: Vreg: %1[ 50 ]
+# CHECK: Vreg: %27[ 76 ]
+# CHECK: Vreg: %15[ 55 ]
+# CHECK: Vreg: %3[ 83 ]
+# CHECK: Vreg: %29[ 33 ]
+# CHECK: Vreg: %164[ LoopTag+11 ]
+# CHECK: Vreg: %17:sub0[ 72 ]
+# CHECK: Vreg: %17:sub1[ 73 ]
+# CHECK: Instr: %173:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %16.sub1, killed %170.sub1, killed %172, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %26[ 33 ]
+# CHECK: Vreg: %2[ 59 ]
+# CHECK: Vreg: %35[ 5 ]
+# CHECK: Vreg: %16:sub1[ 0 ]
+# CHECK: Vreg: %16:sub0[ 92 ]
+# CHECK: Vreg: %16[ 99 ]
+# CHECK: Vreg: %170:sub1[ 0 ]
+# CHECK: Vreg: %4[ 5 ]
+# CHECK: Vreg: %49[ LoopTag+10 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %18:sub0[ 12 ]
+# CHECK: Vreg: %18:sub1[ 13 ]
+# CHECK: Vreg: %172[ 0 ]
+# CHECK: Vreg: %32[ 4 ]
+# CHECK: Vreg: %167[ 2 ]
+# CHECK: Vreg: %1[ 49 ]
+# CHECK: Vreg: %27[ 75 ]
+# CHECK: Vreg: %15[ 54 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %29[ 32 ]
+# CHECK: Vreg: %164[ LoopTag+10 ]
+# CHECK: Vreg: %17:sub0[ 71 ]
+# CHECK: Vreg: %17:sub1[ 72 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Instr: %174:vreg_64 = REG_SEQUENCE killed %171, %subreg.sub0, killed %173, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %173[ 0 ]
+# CHECK: Vreg: %26[ 32 ]
+# CHECK: Vreg: %2[ 58 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %16:sub0[ 91 ]
+# CHECK: Vreg: %16:sub1[ 92 ]
+# CHECK: Vreg: %16[ 98 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %49[ LoopTag+9 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %18:sub0[ 11 ]
+# CHECK: Vreg: %18:sub1[ 12 ]
+# CHECK: Vreg: %32[ 3 ]
+# CHECK: Vreg: %167[ 1 ]
+# CHECK: Vreg: %1[ 48 ]
+# CHECK: Vreg: %27[ 74 ]
+# CHECK: Vreg: %15[ 53 ]
+# CHECK: Vreg: %3[ 81 ]
+# CHECK: Vreg: %29[ 31 ]
+# CHECK: Vreg: %164[ LoopTag+9 ]
+# CHECK: Vreg: %17:sub0[ 70 ]
+# CHECK: Vreg: %17:sub1[ 71 ]
+# CHECK: Vreg: %171[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_SHORT_D16_HI %174, %167, 2, 0, implicit $exec :: (store (s16) into %ir.gep5 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 39 ]
+# CHECK: Vreg: %26[ 31 ]
+# CHECK: Vreg: %2[ 57 ]
+# CHECK: Vreg: %35[ 3 ]
+# CHECK: Vreg: %16:sub0[ 90 ]
+# CHECK: Vreg: %16:sub1[ 91 ]
+# CHECK: Vreg: %16[ 97 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %49[ LoopTag+8 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %18:sub0[ 10 ]
+# CHECK: Vreg: %18:sub1[ 11 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %1[ 47 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %27[ 73 ]
+# CHECK: Vreg: %15[ 52 ]
+# CHECK: Vreg: %3[ 80 ]
+# CHECK: Vreg: %29[ 30 ]
+# CHECK: Vreg: %164[ LoopTag+8 ]
+# CHECK: Vreg: %17:sub0[ 69 ]
+# CHECK: Vreg: %17:sub1[ 70 ]
+# CHECK: Instr: GLOBAL_STORE_SHORT killed %174, killed %167, 0, 0, implicit $exec :: (store (s16) into %ir.gep5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 38 ]
+# CHECK: Vreg: %26[ 30 ]
+# CHECK: Vreg: %2[ 56 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %16:sub0[ 89 ]
+# CHECK: Vreg: %16:sub1[ 90 ]
+# CHECK: Vreg: %16[ 96 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %49[ LoopTag+7 ]
+# CHECK: Vreg: %30[ 3 ]
+# CHECK: Vreg: %18:sub0[ 9 ]
+# CHECK: Vreg: %18:sub1[ 10 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %1[ 46 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %27[ 72 ]
+# CHECK: Vreg: %15[ 51 ]
+# CHECK: Vreg: %3[ 79 ]
+# CHECK: Vreg: %29[ 29 ]
+# CHECK: Vreg: %164[ LoopTag+7 ]
+# CHECK: Vreg: %17:sub0[ 68 ]
+# CHECK: Vreg: %17:sub1[ 69 ]
+# CHECK: Instr: %33:sreg_32 = S_ADD_I32 killed %32, 10, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %2[ 55 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %16:sub0[ 88 ]
+# CHECK: Vreg: %16:sub1[ 89 ]
+# CHECK: Vreg: %16[ 95 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %49[ LoopTag+6 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %18:sub0[ 8 ]
+# CHECK: Vreg: %18:sub1[ 9 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %27[ 71 ]
+# CHECK: Vreg: %15[ 50 ]
+# CHECK: Vreg: %3[ 78 ]
+# CHECK: Vreg: %29[ 28 ]
+# CHECK: Vreg: %164[ LoopTag+6 ]
+# CHECK: Vreg: %17:sub0[ 67 ]
+# CHECK: Vreg: %17:sub1[ 68 ]
+# CHECK: Instr: %175:sreg_32 = V_CMP_GE_U32_e64 %35, %4, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %26[ 28 ]
+# CHECK: Vreg: %33[ 3 ]
+# CHECK: Vreg: %2[ 54 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %16:sub0[ 87 ]
+# CHECK: Vreg: %16:sub1[ 88 ]
+# CHECK: Vreg: %16[ 94 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %49[ LoopTag+5 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %18:sub0[ 7 ]
+# CHECK: Vreg: %18:sub1[ 8 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %27[ 70 ]
+# CHECK: Vreg: %15[ 49 ]
+# CHECK: Vreg: %3[ 77 ]
+# CHECK: Vreg: %29[ 27 ]
+# CHECK: Vreg: %164[ LoopTag+5 ]
+# CHECK: Vreg: %17:sub0[ 66 ]
+# CHECK: Vreg: %17:sub1[ 67 ]
+# CHECK: Instr: %31:sreg_32 = SI_IF_BREAK killed %175, killed %30, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %26[ 27 ]
+# CHECK: Vreg: %33[ 2 ]
+# CHECK: Vreg: %2[ 53 ]
+# CHECK: Vreg: %175[ 0 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %16:sub0[ 86 ]
+# CHECK: Vreg: %16:sub1[ 87 ]
+# CHECK: Vreg: %16[ 93 ]
+# CHECK: Vreg: %4[ 92 ]
+# CHECK: Vreg: %49[ LoopTag+4 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18:sub0[ 6 ]
+# CHECK: Vreg: %18:sub1[ 7 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %27[ 69 ]
+# CHECK: Vreg: %15[ 48 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %29[ 26 ]
+# CHECK: Vreg: %164[ LoopTag+4 ]
+# CHECK: Vreg: %17:sub0[ 65 ]
+# CHECK: Vreg: %17:sub1[ 66 ]
+# CHECK: Instr: SI_LOOP %31, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %26[ 26 ]
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %16:sub0[ 85 ]
+# CHECK: Vreg: %16:sub1[ 86 ]
+# CHECK: Vreg: %16[ 92 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %49[ LoopTag+3 ]
+# CHECK: Vreg: %18:sub0[ 5 ]
+# CHECK: Vreg: %18:sub1[ 6 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %27[ 68 ]
+# CHECK: Vreg: %15[ 47 ]
+# CHECK: Vreg: %3[ 75 ]
+# CHECK: Vreg: %29[ 25 ]
+# CHECK: Vreg: %164[ LoopTag+3 ]
+# CHECK: Vreg: %17:sub0[ 64 ]
+# CHECK: Vreg: %17:sub1[ 65 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %16:sub0[ 84 ]
+# CHECK: Vreg: %16:sub1[ 85 ]
+# CHECK: Vreg: %16[ 91 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %49[ LoopTag+2 ]
+# CHECK: Vreg: %18:sub0[ 4 ]
+# CHECK: Vreg: %18:sub1[ 5 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %27[ 67 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %3[ 74 ]
+# CHECK: Vreg: %29[ 24 ]
+# CHECK: Vreg: %164[ LoopTag+2 ]
+# CHECK: Vreg: %17:sub0[ 63 ]
+# CHECK: Vreg: %17:sub1[ 64 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %16:sub0[ 84 ]
+# CHECK: Vreg: %16:sub1[ 85 ]
+# CHECK: Vreg: %16[ 91 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %49[ LoopTag+2 ]
+# CHECK: Vreg: %18:sub0[ 4 ]
+# CHECK: Vreg: %18:sub1[ 5 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %27[ 67 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %3[ 74 ]
+# CHECK: Vreg: %29[ 24 ]
+# CHECK: Vreg: %164[ LoopTag+2 ]
+# CHECK: Vreg: %17:sub0[ 63 ]
+# CHECK: Vreg: %17:sub1[ 64 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: --- MBB_19 ---
+# CHECK: Instr: SI_END_CF killed %31, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %164[ 1 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %176:vgpr_32 = V_ADD_U32_e64 killed %164, killed %49, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Instr: %177:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %176, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %176[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %177
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %177[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test13 (ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, ptr addrspace(1) %p4, ptr addrspace(1) %p5, i32 %TC1, i32 %TC2, i32 %TC3, i32 %TC4, i32 %Val) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  %add1 = add i32 %ld1, 100
+  br label %1
+  1:
+  %phi.inc1 = phi i32 [ 0, %0 ], [ %inc1, %12 ]
+  %sext1 = sext i32 %phi.inc1 to i64
+  %gep1 = getelementptr inbounds i64, ptr addrspace(1) %p2, i64 %sext1
+  %ld2 = load i32, ptr addrspace(1) %gep1, align 1
+  br label %2
+  2:
+  %phi.inc2 = phi i32 [ 2, %1 ], [ %inc2, %11 ]
+  br label %3
+  3:
+  %mul1 = mul i32 %ld1, %phi.inc2
+  %sext2 = sext i32 %phi.inc2 to i64
+  %gep2 = getelementptr inbounds i64, ptr addrspace(1) %p2, i64 %sext2
+  store i32 %mul1, ptr addrspace(1) %gep2
+  %cond1 = icmp ult i32 %mul1, %Val
+  br i1 %cond1, label %4, label %8
+  4:
+  %phi.inc3 = phi i32 [ 10, %3 ], [ %inc3, %7 ]
+  %cond2 = icmp ult i32 %phi.inc3, %Val
+  br i1 %cond2, label %5, label %6
+  5:
+  %mul2 = mul i32 %phi.inc2, %phi.inc3
+  store i32 %mul2, ptr addrspace(1) %p5
+  br label %7
+  6:
+  %mul3 = mul i32 %phi.inc1, %phi.inc3
+  store i32 %mul3, ptr addrspace(1) %p5
+  br label %7
+  7:
+  %mul4 = phi i32 [ %mul2, %5 ], [ %mul3, %6 ]
+  %inc3 = add i32 %phi.inc3, 1
+  %cond3 = icmp ult i32 %inc3, %TC3
+  br i1 %cond3, label %4, label %9
+  8:
+  %phi.inc4 = phi i32 [ 20, %3 ], [ %inc4, %8 ]
+  %inc4 = add i32 %phi.inc4, 1
+  %mul5 = mul i32 %phi.inc4, %inc4
+  %cond4 = icmp ult i32 %inc4, %TC4
+  br i1 %cond4, label %8, label %9
+  9:
+  %phi1 = phi i32 [ %phi.inc3, %7 ], [ %phi.inc4, %8 ]
+  %phi2 = phi i32 [ %inc3, %7 ], [ %inc4, %8 ]
+  %phi3 = phi i32 [ %mul4, %7 ], [ %mul5, %8 ]
+  %div1 = udiv i32 %phi1, %phi.inc2
+  %sext3 = sext i32 %div1 to i64
+  %gep3 = getelementptr inbounds i64, ptr addrspace(1) %p3, i64 %sext3
+  %ld3 = load i32, ptr addrspace(1) %gep3, align 4
+  %add2 = add i32 %phi2, %add1
+  %cond5 = icmp ult i32 %add2, %mul1
+  br i1 %cond5, label %10, label %11
+  10:
+  %div2 = udiv i32 %phi1, %phi.inc1
+  %sext4 = sext i32 %div2 to i64
+  %gep4 = getelementptr inbounds i64, ptr addrspace(1) %p3, i64 %sext4
+  %ld4 = load i32, ptr addrspace(1) %gep4, align 2
+  store i32 %ld4, ptr addrspace(1) %p4
+  br label %11
+  11:
+  %phi4 = phi i32 [ %ld3, %9 ], [ %ld4, %10 ]
+  %phi5 = phi i32 [ %div1, %9 ], [ %div2, %10 ]
+  %phi6 = phi i32 [ %phi3, %9 ], [ %ld4, %10 ]
+  %inc2 = add i32 %phi.inc2, 1
+  %cond6 = icmp ult i32 %inc2, %TC2
+  br i1 %cond6, label %2, label %12
+  12:
+  %inc1 = add i32 %phi.inc1, 1
+  %add3 = add i32 %ld2, %inc1
+  %sext5 = sext i32 %phi5 to i64
+  %gep5 = getelementptr inbounds i64, ptr addrspace(1) %p4, i64 %sext5
+  store i32 %add3, ptr addrspace(1) %gep5, align 2
+  %cond7 = icmp ult i32 %inc1, %TC1
+  br i1 %cond7, label %1, label %13
+  13:
+  %add4 = add i32 %phi4, %ld2
+  ret i32 %add4
+  }
+...
+
+---
+name:            test13
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14
+  
+    %73:vgpr_32 = COPY killed $vgpr14
+    %72:vgpr_32 = COPY killed $vgpr13
+    %71:vgpr_32 = COPY killed $vgpr12
+    %70:vgpr_32 = COPY killed $vgpr11
+    %69:vgpr_32 = COPY killed $vgpr10
+    %68:vgpr_32 = COPY killed $vgpr9
+    %67:vgpr_32 = COPY killed $vgpr8
+    %66:vgpr_32 = COPY killed $vgpr7
+    %65:vgpr_32 = COPY killed $vgpr6
+    %64:vgpr_32 = COPY killed $vgpr5
+    %63:vgpr_32 = COPY killed $vgpr4
+    %62:vgpr_32 = COPY killed $vgpr3
+    %61:vgpr_32 = COPY killed $vgpr2
+    %60:vgpr_32 = COPY killed $vgpr1
+    %59:vgpr_32 = COPY killed $vgpr0
+    %208:vreg_64 = REG_SEQUENCE killed %67, %subreg.sub0, killed %68, %subreg.sub1
+    %207:vreg_64 = REG_SEQUENCE killed %65, %subreg.sub0, killed %66, %subreg.sub1
+    %206:vreg_64 = REG_SEQUENCE killed %63, %subreg.sub0, killed %64, %subreg.sub1
+    %205:vreg_64 = REG_SEQUENCE killed %61, %subreg.sub0, killed %62, %subreg.sub1
+    %204:vreg_64 = REG_SEQUENCE killed %59, %subreg.sub0, killed %60, %subreg.sub1
+    %84:vgpr_32 = GLOBAL_LOAD_UBYTE %204, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %86:vgpr_32 = GLOBAL_LOAD_UBYTE %204, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %89:vgpr_32 = V_LSHL_OR_B32_e64 killed %86, 8, killed %84, implicit $exec
+    %90:vgpr_32 = GLOBAL_LOAD_UBYTE %204, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %92:vgpr_32 = GLOBAL_LOAD_UBYTE killed %204, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %94:vgpr_32 = V_LSHL_OR_B32_e64 killed %92, 8, killed %90, implicit $exec
+    %0:vgpr_32 = V_LSHL_OR_B32_e64 killed %94, 16, killed %89, implicit $exec
+    %1:vgpr_32 = V_ADD_U32_e64 100, %0, 0, implicit $exec
+    %78:sreg_32 = S_MOV_B32 0
+    %137:sreg_32 = S_MOV_B32 2
+  
+  bb.1:
+    successors: %bb.2(0x80000000)
+  
+    %2:sreg_32 = PHI %78, %bb.0, %55, %bb.18
+    %3:sreg_32 = PHI %78, %bb.0, %54, %bb.18
+    %4:sreg_32 = PHI %78, %bb.0, %53, %bb.18
+    %100:sreg_32_xm0 = S_ASHR_I32 %4, 31, implicit-def dead $scc
+    %102:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, killed %100, %subreg.sub1
+    %104:sreg_64 = nsw S_LSHL_B64 killed %102, 3, implicit-def dead $scc
+    %213:vgpr_32, %215:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %205.sub0, %104.sub0, 0, implicit $exec
+    %214:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %104.sub1, %205.sub1, killed %215, 0, implicit $exec
+    %105:vreg_64 = REG_SEQUENCE killed %213, %subreg.sub0, killed %214, %subreg.sub1
+    %106:vgpr_32 = GLOBAL_LOAD_UBYTE %105, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+    %107:vgpr_32 = GLOBAL_LOAD_UBYTE %105, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+    %109:vgpr_32 = V_LSHL_OR_B32_e64 killed %107, 8, killed %106, implicit $exec
+    %110:vgpr_32 = GLOBAL_LOAD_UBYTE %105, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+    %111:vgpr_32 = GLOBAL_LOAD_UBYTE killed %105, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+    %112:vgpr_32 = V_LSHL_OR_B32_e64 killed %111, 8, killed %110, implicit $exec
+    %5:vgpr_32 = V_LSHL_OR_B32_e64 killed %112, 16, killed %109, implicit $exec
+    %114:sgpr_32 = S_CVT_F32_U32 %4, implicit $mode
+    %115:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %114, 0, 0, implicit $mode, implicit $exec
+    %118:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %115, implicit $exec
+    %117:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %118, 1333788670, implicit $mode
+    %119:sreg_32 = nofpexcept S_CVT_U32_F32 killed %117, implicit $mode
+    %120:sreg_32 = S_SUB_I32 0, %4, implicit-def dead $scc
+    %121:sreg_32 = S_MUL_I32 killed %120, %119
+    %122:sreg_32 = S_MUL_HI_U32 %119, killed %121
+    %123:sreg_32 = S_ADD_I32 killed %119, killed %122, implicit-def dead $scc
+    %125:sreg_64 = REG_SEQUENCE killed %123, %subreg.sub0, undef %78, %subreg.sub1
+    %98:sreg_32 = S_MOV_B32 20
+  
+  bb.2:
+    successors: %bb.3(0x40000000), %bb.11(0x40000000)
+  
+    %7:sreg_32 = PHI %78, %bb.1, %49, %bb.17
+    %8:sreg_32 = PHI %98, %bb.1, %48, %bb.17
+    %9:sreg_32 = PHI %137, %bb.1, %47, %bb.17
+    %10:vgpr_32 = V_MUL_LO_U32_e64 %0, %9, implicit $exec
+    %127:sreg_32_xm0 = S_ASHR_I32 %9, 31, implicit-def dead $scc
+    %129:sreg_64 = REG_SEQUENCE %9, %subreg.sub0, killed %127, %subreg.sub1
+    %131:sreg_64 = nsw S_LSHL_B64 killed %129, 3, implicit-def dead $scc
+    %216:vgpr_32, %218:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %205.sub0, %131.sub0, 0, implicit $exec
+    %217:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %131.sub1, %205.sub1, killed %218, 0, implicit $exec
+    %132:vreg_64 = REG_SEQUENCE killed %216, %subreg.sub0, killed %217, %subreg.sub1
+    GLOBAL_STORE_DWORD killed %132, %10, 0, 0, implicit $exec :: (store (s32) into %ir.gep2, addrspace 1)
+    %133:sreg_32 = V_CMP_GE_U32_e64 %10, %73, implicit $exec
+    %11:sreg_32 = SI_IF killed %133, %bb.11, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.3
+  
+  bb.3:
+    successors: %bb.12(0x80000000)
+  
+    %135:sreg_32 = S_MOV_B32 19
+    %134:sreg_32 = S_MOV_B32 0
+    S_BRANCH %bb.12
+  
+  bb.4:
+    successors: %bb.6(0x80000000)
+  
+    %140:sreg_32 = S_MOV_B32 9
+    %139:sreg_32 = S_MOV_B32 0
+    S_BRANCH %bb.6
+  
+  bb.5:
+    successors: %bb.15(0x80000000)
+  
+    %12:vgpr_32 = PHI %25, %bb.11, %211, %bb.14
+    %13:vgpr_32 = PHI %26, %bb.11, %212, %bb.14
+    SI_END_CF killed %27, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.15
+  
+  bb.6:
+    successors: %bb.9(0x40000000), %bb.7(0x40000000)
+  
+    %14:sreg_32 = PHI %139, %bb.4, %24, %bb.10
+    %15:sreg_32 = PHI %8, %bb.4, %23, %bb.10
+    %16:sreg_32 = PHI %3, %bb.4, %22, %bb.10
+    %17:sreg_32 = PHI %140, %bb.4, %18, %bb.10
+    %18:sreg_32 = S_ADD_I32 killed %17, 1, implicit-def dead $scc
+    %142:sreg_32 = V_CMP_GE_U32_e64 %18, %73, implicit $exec
+    %19:sreg_32 = SI_IF killed %142, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.9
+  
+  bb.7:
+    successors: %bb.8(0x40000000), %bb.10(0x40000000)
+  
+    %20:sreg_32 = SI_ELSE killed %19, %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.8
+  
+  bb.8:
+    successors: %bb.10(0x80000000)
+  
+    %144:vgpr_32 = COPY %15
+    GLOBAL_STORE_DWORD %208, killed %144, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+    S_BRANCH %bb.10
+  
+  bb.9:
+    successors: %bb.7(0x80000000)
+  
+    %143:vgpr_32 = COPY %16
+    GLOBAL_STORE_DWORD %208, killed %143, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+    S_BRANCH %bb.7
+  
+  bb.10:
+    successors: %bb.14(0x04000000), %bb.6(0x7c000000)
+  
+    SI_END_CF killed %20, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %21:sreg_32 = S_ADD_I32 %18, 1, implicit-def dead $scc
+    %22:sreg_32 = S_ADD_I32 killed %16, %4, implicit-def dead $scc
+    %23:sreg_32 = S_ADD_I32 killed %15, %9, implicit-def dead $scc
+    %146:sreg_32 = V_CMP_GE_U32_e64 %21, %71, implicit $exec
+    %24:sreg_32 = SI_IF_BREAK killed %146, killed %14, implicit-def dead $scc
+    %211:vgpr_32 = COPY killed %21, implicit $exec
+    %212:vgpr_32 = COPY %18, implicit $exec
+    SI_LOOP %24, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.14
+  
+  bb.11:
+    successors: %bb.4(0x40000000), %bb.5(0x40000000)
+  
+    %25:vgpr_32 = PHI undef %126:vgpr_32, %bb.2, %210, %bb.13
+    %26:vgpr_32 = PHI undef %126:vgpr_32, %bb.2, %209, %bb.13
+    %27:sreg_32 = SI_ELSE killed %11, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.4
+  
+  bb.12:
+    successors: %bb.13(0x04000000), %bb.12(0x7c000000)
+  
+    %28:sreg_32 = PHI %134, %bb.3, %32, %bb.12
+    %29:sreg_32 = PHI %135, %bb.3, %30, %bb.12
+    %30:sreg_32 = nuw S_ADD_I32 %29, 1, implicit-def dead $scc
+    %31:sreg_32 = S_ADD_I32 killed %29, 2, implicit-def dead $scc
+    %138:sreg_32 = V_CMP_GE_U32_e64 %31, %72, implicit $exec
+    %32:sreg_32 = SI_IF_BREAK killed %138, killed %28, implicit-def dead $scc
+    %209:vgpr_32 = COPY %30, implicit $exec
+    %210:vgpr_32 = COPY killed %31, implicit $exec
+    SI_LOOP %32, %bb.12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.13
+  
+  bb.13:
+    successors: %bb.11(0x80000000)
+  
+    SI_END_CF killed %32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.11
+  
+  bb.14:
+    successors: %bb.5(0x80000000)
+  
+    SI_END_CF killed %24, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.5
+  
+  bb.15:
+    successors: %bb.16(0x40000000), %bb.17(0x40000000)
+  
+    %147:sgpr_32 = S_CVT_F32_U32 %9, implicit $mode
+    %148:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %147, 0, 0, implicit $mode, implicit $exec
+    %151:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %148, implicit $exec
+    %150:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %151, 1333788670, implicit $mode
+    %152:sreg_32 = nofpexcept S_CVT_U32_F32 killed %150, implicit $mode
+    %154:sreg_32 = S_SUB_I32 0, %9, implicit-def dead $scc
+    %155:sreg_32 = S_MUL_I32 killed %154, %152
+    %156:sreg_32 = S_MUL_HI_U32 %152, killed %155
+    %157:sreg_32 = S_ADD_I32 killed %152, killed %156, implicit-def dead $scc
+    %160:vgpr_32 = V_MUL_HI_U32_e64 %13, killed %157, implicit $exec
+    %161:vgpr_32 = V_MUL_LO_U32_e64 %160, %9, implicit $exec
+    %162:vgpr_32 = V_SUB_U32_e64 %13, killed %161, 0, implicit $exec
+    %163:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %9, %162, implicit $exec
+    %165:vgpr_32 = V_ADD_U32_e64 1, %160, 0, implicit $exec
+    %166:vgpr_32 = V_CNDMASK_B32_e64 0, killed %160, 0, killed %165, %163, implicit $exec
+    %167:vgpr_32 = V_SUBREV_U32_e64 %9, %162, 0, implicit $exec
+    %168:vgpr_32 = V_CNDMASK_B32_e64 0, killed %162, 0, killed %167, killed %163, implicit $exec
+    %169:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %9, killed %168, implicit $exec
+    %170:vgpr_32 = V_ADD_U32_e64 1, %166, 0, implicit $exec
+    %40:vgpr_32 = V_CNDMASK_B32_e64 0, killed %166, 0, killed %170, killed %169, implicit $exec
+    %171:vgpr_32 = V_ASHRREV_I32_e64 31, %40, implicit $exec
+    %173:vreg_64 = REG_SEQUENCE %40, %subreg.sub0, killed %171, %subreg.sub1
+    %175:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %173, implicit $exec
+    %219:vgpr_32, %221:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %206.sub0, %175.sub0, 0, implicit $exec
+    %220:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %206.sub1, killed %175.sub1, killed %221, 0, implicit $exec
+    %176:vreg_64 = REG_SEQUENCE killed %219, %subreg.sub0, killed %220, %subreg.sub1
+    %41:vgpr_32 = GLOBAL_LOAD_DWORD killed %176, 0, 0, implicit $exec :: (load (s32) from %ir.gep3, addrspace 1)
+    %177:vgpr_32 = V_ADD_U32_e64 killed %12, %1, 0, implicit $exec
+    %178:sreg_32 = V_CMP_LT_U32_e64 killed %177, killed %10, implicit $exec
+    %42:sreg_32 = SI_IF killed %178, %bb.17, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.16
+  
+  bb.16:
+    successors: %bb.17(0x80000000)
+  
+    %179:vgpr_32 = V_MUL_HI_U32_e64 %13, %125.sub0, implicit $exec
+    %180:vgpr_32 = V_MUL_LO_U32_e64 %179, %4, implicit $exec
+    %181:vgpr_32 = V_SUB_U32_e64 killed %13, killed %180, 0, implicit $exec
+    %182:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %4, %181, implicit $exec
+    %183:vgpr_32 = V_ADD_U32_e64 1, %179, 0, implicit $exec
+    %184:vgpr_32 = V_CNDMASK_B32_e64 0, killed %179, 0, killed %183, %182, implicit $exec
+    %185:vgpr_32 = V_SUBREV_U32_e64 %4, %181, 0, implicit $exec
+    %186:vgpr_32 = V_CNDMASK_B32_e64 0, killed %181, 0, killed %185, killed %182, implicit $exec
+    %187:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %4, killed %186, implicit $exec
+    %188:vgpr_32 = V_ADD_U32_e64 1, %184, 0, implicit $exec
+    %43:vgpr_32 = V_CNDMASK_B32_e64 0, killed %184, 0, killed %188, killed %187, implicit $exec
+    %189:vgpr_32 = V_ASHRREV_I32_e64 31, %43, implicit $exec
+    %190:vreg_64 = REG_SEQUENCE %43, %subreg.sub0, killed %189, %subreg.sub1
+    %191:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %190, implicit $exec
+    %222:vgpr_32, %224:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %206.sub0, %191.sub0, 0, implicit $exec
+    %223:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %206.sub1, killed %191.sub1, killed %224, 0, implicit $exec
+    %192:vreg_64 = REG_SEQUENCE killed %222, %subreg.sub0, killed %223, %subreg.sub1
+    %193:vgpr_32 = GLOBAL_LOAD_USHORT %192, 0, 0, implicit $exec :: (load (s16) from %ir.gep4, addrspace 1)
+    %194:vgpr_32 = GLOBAL_LOAD_USHORT killed %192, 2, 0, implicit $exec :: (load (s16) from %ir.gep4 + 2, addrspace 1)
+    %44:vgpr_32 = V_LSHL_OR_B32_e64 killed %194, 16, killed %193, implicit $exec
+    GLOBAL_STORE_DWORD %207, %44, 0, 0, implicit $exec :: (store (s32) into %ir.p4, addrspace 1)
+  
+  bb.17:
+    successors: %bb.18(0x04000000), %bb.2(0x7c000000)
+  
+    %45:vgpr_32 = PHI %41, %bb.15, %44, %bb.16
+    %46:vgpr_32 = PHI %40, %bb.15, %43, %bb.16
+    SI_END_CF killed %42, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %47:sreg_32 = S_ADD_I32 killed %9, 1, implicit-def dead $scc
+    %48:sreg_32 = S_ADD_I32 killed %8, 10, implicit-def dead $scc
+    %195:sreg_32 = V_CMP_GE_U32_e64 %47, %70, implicit $exec
+    %49:sreg_32 = SI_IF_BREAK killed %195, killed %7, implicit-def dead $scc
+    SI_LOOP %49, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.18
+  
+  bb.18:
+    successors: %bb.19(0x04000000), %bb.1(0x7c000000)
+  
+    SI_END_CF killed %49, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %53:sreg_32 = S_ADD_I32 killed %4, 1, implicit-def dead $scc
+    %196:vgpr_32 = V_ADD_U32_e64 %53, %5, 0, implicit $exec
+    %197:vgpr_32 = V_ASHRREV_I32_e64 31, %46, implicit $exec
+    %198:vreg_64 = REG_SEQUENCE killed %46, %subreg.sub0, killed %197, %subreg.sub1
+    %199:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %198, implicit $exec
+    %225:vgpr_32, %227:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %207.sub0, %199.sub0, 0, implicit $exec
+    %226:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %207.sub1, killed %199.sub1, killed %227, 0, implicit $exec
+    %200:vreg_64 = REG_SEQUENCE killed %225, %subreg.sub0, killed %226, %subreg.sub1
+    GLOBAL_STORE_SHORT_D16_HI %200, %196, 2, 0, implicit $exec :: (store (s16) into %ir.gep5 + 2, addrspace 1)
+    GLOBAL_STORE_SHORT killed %200, killed %196, 0, 0, implicit $exec :: (store (s16) into %ir.gep5, addrspace 1)
+    %54:sreg_32 = S_ADD_I32 killed %3, 10, implicit-def dead $scc
+    %201:sreg_32 = V_CMP_GE_U32_e64 %53, %69, implicit $exec
+    %55:sreg_32 = SI_IF_BREAK killed %201, killed %2, implicit-def dead $scc
+    SI_LOOP %55, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.19
+  
+  bb.19:
+    SI_END_CF killed %55, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %202:vgpr_32 = V_ADD_U32_e64 killed %45, killed %5, 0, implicit $exec
+    %203:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %202, implicit $exec
+    $sgpr0 = COPY killed %203
+    SI_RETURN_TO_EPILOG killed $sgpr0
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nesteed_loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nesteed_loops.mir
new file mode 100644
index 0000000000000..2f1f61453ecc3
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nesteed_loops.mir
@@ -0,0 +1,2008 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#             bb.0.entry
+#                 |
+#         bb.1.loop1.header<-----+
+#                 |              |
+#         bb.2.loop2.header<--+  |
+#               /    \        |  |
+#            bb.3   bb.6.bb2  |  |
+#               \    /        |  |
+#              bb.4.Flow      |  |
+#               /    |        |  |
+#  bb.5.loop2.latch1 |        |  |
+#               \    |        |  |
+#             bb.7.Flow1------+  |
+#                 |              |
+#          bb.8.loop1.latch------+
+#                 |
+#             bb.9.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test10 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 42 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 39 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 38 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Instr: %8:vreg_64 = REG_SEQUENCE killed %3, %subreg.sub0, killed %2, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Instr: %9:vreg_64 = REG_SEQUENCE killed %5, %subreg.sub0, killed %4, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %8[ 12 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %10:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, killed %6, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %9:sub0[ 26 ]
+# CHECK: Vreg: %9:sub1[ 27 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %8[ 11 ]
+# CHECK: Instr: %11:vgpr_32 = GLOBAL_LOAD_UBYTE %10, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %9:sub0[ 25 ]
+# CHECK: Vreg: %9:sub1[ 26 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %8[ 10 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %12:vgpr_32 = GLOBAL_LOAD_UBYTE %10, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %9:sub0[ 24 ]
+# CHECK: Vreg: %9:sub1[ 25 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %8[ 9 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %13:vgpr_32 = V_LSHL_OR_B32_e64 killed %12, 8, killed %11, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %9:sub0[ 23 ]
+# CHECK: Vreg: %9:sub1[ 24 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %8[ 8 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %14:vgpr_32 = GLOBAL_LOAD_UBYTE %10, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %9:sub0[ 22 ]
+# CHECK: Vreg: %9:sub1[ 23 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %8[ 7 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %15:vgpr_32 = GLOBAL_LOAD_UBYTE %10, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %9:sub0[ 21 ]
+# CHECK: Vreg: %9:sub1[ 22 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %8[ 6 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %16:vgpr_32 = V_LSHL_OR_B32_e64 killed %15, 8, killed %14, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %9:sub0[ 20 ]
+# CHECK: Vreg: %9:sub1[ 21 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %8[ 5 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %10:sub0[ 16 ]
+# CHECK: Vreg: %10:sub1[ 17 ]
+# CHECK: Instr: %17:vgpr_32 = V_LSHL_OR_B32_e64 killed %16, 16, killed %13, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %9:sub0[ 19 ]
+# CHECK: Vreg: %9:sub1[ 20 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: Vreg: %10:sub0[ 15 ]
+# CHECK: Vreg: %10:sub1[ 16 ]
+# CHECK: Instr: %18:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %19:sreg_32 = PHI %18, %bb.0, %20, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %21:sreg_32 = PHI %18, %bb.0, %22, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %19[ 21 ]
+# CHECK: Instr: %23:vgpr_32 = PHI %17, %bb.0, %24, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %19[ 21 ]
+# CHECK: Instr: %25:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %9:sub0[ 17 ]
+# CHECK: Vreg: %9:sub1[ 18 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %10:sub0[ 13 ]
+# CHECK: Vreg: %10:sub1[ 14 ]
+# CHECK: Vreg: %17[ LoopTag+25 ]
+# CHECK: Vreg: %19[ 20 ]
+# CHECK: Instr: %26:vgpr_32 = V_MUL_LO_U32_e64 100, %23, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %9:sub0[ 16 ]
+# CHECK: Vreg: %9:sub1[ 17 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %10:sub0[ 12 ]
+# CHECK: Vreg: %10:sub1[ 13 ]
+# CHECK: Vreg: %17[ LoopTag+24 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %8, %26, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %9:sub0[ 15 ]
+# CHECK: Vreg: %9:sub1[ 16 ]
+# CHECK: Vreg: %23[ LoopTag+23 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %10:sub0[ 11 ]
+# CHECK: Vreg: %10:sub1[ 12 ]
+# CHECK: Vreg: %17[ LoopTag+23 ]
+# CHECK: Vreg: %19[ 18 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %26[ LoopTag+24 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %9:sub0[ 15 ]
+# CHECK: Vreg: %9:sub1[ 16 ]
+# CHECK: Vreg: %23[ LoopTag+23 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %8[ 24 ]
+# CHECK: Vreg: %10:sub0[ 11 ]
+# CHECK: Vreg: %10:sub1[ 12 ]
+# CHECK: Vreg: %17[ LoopTag+23 ]
+# CHECK: Vreg: %19[ 18 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %27:sreg_32 = PHI %18, %bb.1, %28, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %26[ LoopTag*2+24 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 15 ]
+# CHECK: Vreg: %9:sub1[ 16 ]
+# CHECK: Vreg: %23[ LoopTag*2+23 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+17 ]
+# CHECK: Vreg: %8[ LoopTag+24 ]
+# CHECK: Vreg: %10:sub0[ 11 ]
+# CHECK: Vreg: %10:sub1[ 12 ]
+# CHECK: Vreg: %17[ LoopTag*2+23 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+18 ]
+# CHECK: Instr: %29:sreg_32 = PHI %18, %bb.1, %30, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %26[ LoopTag*2+24 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %9:sub0[ 15 ]
+# CHECK: Vreg: %9:sub1[ 16 ]
+# CHECK: Vreg: %23[ LoopTag*2+23 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+17 ]
+# CHECK: Vreg: %27[ 12 ]
+# CHECK: Vreg: %8[ LoopTag+24 ]
+# CHECK: Vreg: %10:sub0[ 11 ]
+# CHECK: Vreg: %10:sub1[ 12 ]
+# CHECK: Vreg: %17[ LoopTag*2+23 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+18 ]
+# CHECK: Instr: %24:vgpr_32 = PHI %25, %bb.1, %31, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %26[ LoopTag*2+24 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %9:sub0[ 15 ]
+# CHECK: Vreg: %9:sub1[ 16 ]
+# CHECK: Vreg: %23[ LoopTag*2+23 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+17 ]
+# CHECK: Vreg: %27[ 12 ]
+# CHECK: Vreg: %8[ LoopTag+24 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %10:sub0[ 11 ]
+# CHECK: Vreg: %10:sub1[ 12 ]
+# CHECK: Vreg: %17[ LoopTag*2+23 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+18 ]
+# CHECK: Instr: %32:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %26[ LoopTag*2+23 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %9:sub0[ 14 ]
+# CHECK: Vreg: %9:sub1[ 15 ]
+# CHECK: Vreg: %23[ LoopTag*2+22 ]
+# CHECK: Vreg: %1[ LoopTag+16 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %8[ LoopTag+23 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10:sub0[ 10 ]
+# CHECK: Vreg: %10:sub1[ 11 ]
+# CHECK: Vreg: %17[ LoopTag*2+22 ]
+# CHECK: Vreg: %24[ LoopTag+20 ]
+# CHECK: Vreg: %19[ LoopTag+17 ]
+# CHECK: Instr: %33:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %26[ LoopTag*2+22 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %9:sub0[ 13 ]
+# CHECK: Vreg: %9:sub1[ 14 ]
+# CHECK: Vreg: %23[ LoopTag*2+21 ]
+# CHECK: Vreg: %32[ 4 ]
+# CHECK: Vreg: %1[ LoopTag+15 ]
+# CHECK: Vreg: %27[ 10 ]
+# CHECK: Vreg: %8[ LoopTag+22 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10:sub0[ 9 ]
+# CHECK: Vreg: %10:sub1[ 10 ]
+# CHECK: Vreg: %17[ LoopTag*2+21 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %19[ LoopTag+16 ]
+# CHECK: Instr: S_CMP_GE_U32 %29, %21, implicit-def $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %26[ LoopTag*2+21 ]
+# CHECK: Vreg: %33[ 3 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9:sub0[ 12 ]
+# CHECK: Vreg: %9:sub1[ 13 ]
+# CHECK: Vreg: %23[ LoopTag*2+20 ]
+# CHECK: Vreg: %32[ 3 ]
+# CHECK: Vreg: %1[ LoopTag+14 ]
+# CHECK: Vreg: %27[ 9 ]
+# CHECK: Vreg: %8[ LoopTag+21 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10:sub0[ 8 ]
+# CHECK: Vreg: %10:sub1[ 9 ]
+# CHECK: Vreg: %17[ LoopTag*2+20 ]
+# CHECK: Vreg: %24[ LoopTag+18 ]
+# CHECK: Vreg: %19[ LoopTag+15 ]
+# CHECK: Instr: %34:sgpr_32 = V_READFIRSTLANE_B32 undef %35:vgpr_32, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %26[ LoopTag*2+20 ]
+# CHECK: Vreg: %33[ 2 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %9:sub0[ 11 ]
+# CHECK: Vreg: %9:sub1[ 12 ]
+# CHECK: Vreg: %23[ LoopTag*2+19 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+13 ]
+# CHECK: Vreg: %27[ 8 ]
+# CHECK: Vreg: %8[ LoopTag+20 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %10:sub0[ 7 ]
+# CHECK: Vreg: %10:sub1[ 8 ]
+# CHECK: Vreg: %17[ LoopTag*2+19 ]
+# CHECK: Vreg: %24[ LoopTag+17 ]
+# CHECK: Vreg: %19[ LoopTag+14 ]
+# CHECK: Instr: S_CBRANCH_SCC1 %bb.5, implicit killed $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %26[ LoopTag*2+19 ]
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %9:sub0[ 10 ]
+# CHECK: Vreg: %9:sub1[ 11 ]
+# CHECK: Vreg: %23[ LoopTag*2+18 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+12 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %8[ LoopTag+19 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10:sub0[ 6 ]
+# CHECK: Vreg: %10:sub1[ 7 ]
+# CHECK: Vreg: %17[ LoopTag*2+18 ]
+# CHECK: Vreg: %24[ LoopTag+16 ]
+# CHECK: Vreg: %19[ LoopTag+13 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %26[ LoopTag*2+18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %9:sub0[ 9 ]
+# CHECK: Vreg: %9:sub1[ 10 ]
+# CHECK: Vreg: %23[ LoopTag*2+17 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+11 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+18 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10:sub0[ 5 ]
+# CHECK: Vreg: %10:sub1[ 6 ]
+# CHECK: Vreg: %17[ LoopTag*2+17 ]
+# CHECK: Vreg: %24[ LoopTag+15 ]
+# CHECK: Vreg: %19[ LoopTag+12 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %26[ LoopTag*2+18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %9:sub0[ 9 ]
+# CHECK: Vreg: %9:sub1[ 10 ]
+# CHECK: Vreg: %23[ LoopTag*2+17 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+11 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+18 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10:sub0[ 5 ]
+# CHECK: Vreg: %10:sub1[ 6 ]
+# CHECK: Vreg: %17[ LoopTag*2+17 ]
+# CHECK: Vreg: %24[ LoopTag+15 ]
+# CHECK: Vreg: %19[ LoopTag+12 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %36:sreg_32 = PHI %32, %bb.2, %37, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %26[ LoopTag*2+18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %9:sub0[ 9 ]
+# CHECK: Vreg: %9:sub1[ 10 ]
+# CHECK: Vreg: %23[ LoopTag*2+17 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+11 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+18 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %10:sub0[ 19 ]
+# CHECK: Vreg: %10:sub1[ 20 ]
+# CHECK: Vreg: %17[ LoopTag*2+17 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %24[ LoopTag+15 ]
+# CHECK: Vreg: %19[ LoopTag+12 ]
+# CHECK: Instr: %38:vgpr_32 = PHI undef %35:vgpr_32, %bb.2, %39, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %26[ LoopTag*2+18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %9:sub0[ 9 ]
+# CHECK: Vreg: %9:sub1[ 10 ]
+# CHECK: Vreg: %23[ LoopTag*2+17 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+11 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+18 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %10:sub0[ 19 ]
+# CHECK: Vreg: %10:sub1[ 20 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %17[ LoopTag*2+17 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %24[ LoopTag+15 ]
+# CHECK: Vreg: %19[ LoopTag+12 ]
+# CHECK: Instr: %40:sreg_32 = PHI %34, %bb.2, %41, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %26[ LoopTag*2+18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %9:sub0[ 9 ]
+# CHECK: Vreg: %9:sub1[ 10 ]
+# CHECK: Vreg: %23[ LoopTag*2+17 ]
+# CHECK: Vreg: %1[ LoopTag+11 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+18 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %10:sub0[ 19 ]
+# CHECK: Vreg: %10:sub1[ 20 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %17[ LoopTag*2+17 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %24[ LoopTag+15 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Vreg: %19[ LoopTag+12 ]
+# CHECK: Instr: %42:sreg_32_xm0_xexec = PHI %33, %bb.2, %43, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %26[ LoopTag*2+18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %9:sub0[ 9 ]
+# CHECK: Vreg: %9:sub1[ 10 ]
+# CHECK: Vreg: %23[ LoopTag*2+17 ]
+# CHECK: Vreg: %1[ LoopTag+11 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+18 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %10:sub0[ 19 ]
+# CHECK: Vreg: %10:sub1[ 20 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %17[ LoopTag*2+17 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %24[ LoopTag+15 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Vreg: %19[ LoopTag+12 ]
+# CHECK: Instr: %44:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %42, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %26[ LoopTag*2+17 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %9:sub0[ 8 ]
+# CHECK: Vreg: %9:sub1[ 9 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+16 ]
+# CHECK: Vreg: %1[ LoopTag+10 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %8[ LoopTag+17 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %10:sub0[ 18 ]
+# CHECK: Vreg: %10:sub1[ 19 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %17[ LoopTag*2+16 ]
+# CHECK: Vreg: %24[ LoopTag+14 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Vreg: %19[ LoopTag+11 ]
+# CHECK: Instr: %45:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, killed %44, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %26[ LoopTag*2+16 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %9:sub0[ 7 ]
+# CHECK: Vreg: %9:sub1[ 8 ]
+# CHECK: Vreg: %23[ LoopTag*2+15 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+9 ]
+# CHECK: Vreg: %27[ 4 ]
+# CHECK: Vreg: %8[ LoopTag+16 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %10:sub0[ 17 ]
+# CHECK: Vreg: %10:sub1[ 18 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %17[ LoopTag*2+15 ]
+# CHECK: Vreg: %24[ LoopTag+13 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Vreg: %19[ LoopTag+10 ]
+# CHECK: Instr: $vcc_lo = S_AND_B32 $exec_lo, killed %45, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ LoopTag*2+15 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %9:sub0[ 6 ]
+# CHECK: Vreg: %9:sub1[ 7 ]
+# CHECK: Vreg: %23[ LoopTag*2+14 ]
+# CHECK: Vreg: %1[ LoopTag+8 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %8[ LoopTag+15 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %10:sub0[ 16 ]
+# CHECK: Vreg: %10:sub1[ 17 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ LoopTag*2+14 ]
+# CHECK: Vreg: %24[ LoopTag+12 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Vreg: %19[ LoopTag+9 ]
+# CHECK: Instr: S_CBRANCH_VCCNZ %bb.6, implicit killed $vcc_lo, implicit $vcc_lo
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %26[ LoopTag*2+14 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %23[ LoopTag*2+13 ]
+# CHECK: Vreg: %1[ LoopTag+7 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %8[ LoopTag+14 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10:sub0[ 15 ]
+# CHECK: Vreg: %10:sub1[ 16 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %17[ LoopTag*2+13 ]
+# CHECK: Vreg: %24[ LoopTag+11 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Vreg: %19[ LoopTag+8 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ LoopTag*2+13 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %9:sub0[ 4 ]
+# CHECK: Vreg: %9:sub1[ 5 ]
+# CHECK: Vreg: %23[ LoopTag*2+12 ]
+# CHECK: Vreg: %1[ LoopTag+6 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+13 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+12 ]
+# CHECK: Vreg: %24[ LoopTag+10 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+7 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ LoopTag*2+13 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %9:sub0[ 4 ]
+# CHECK: Vreg: %9:sub1[ 5 ]
+# CHECK: Vreg: %23[ LoopTag*2+12 ]
+# CHECK: Vreg: %1[ LoopTag+6 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+13 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+12 ]
+# CHECK: Vreg: %24[ LoopTag+10 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+7 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %46:sreg_32_xm0 = S_ASHR_I32 %29, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %26[ LoopTag*2+32 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %9:sub0[ 3 ]
+# CHECK: Vreg: %9:sub1[ 4 ]
+# CHECK: Vreg: %23[ LoopTag*2+31 ]
+# CHECK: Vreg: %1[ LoopTag+25 ]
+# CHECK: Vreg: %27[ 20 ]
+# CHECK: Vreg: %8[ LoopTag+32 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10:sub0[ 33 ]
+# CHECK: Vreg: %10:sub1[ 34 ]
+# CHECK: Vreg: %36[ 16 ]
+# CHECK: Vreg: %17[ LoopTag*2+31 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %19[ LoopTag+26 ]
+# CHECK: Instr: %47:sreg_64 = REG_SEQUENCE %29, %subreg.sub0, killed %46, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ LoopTag*2+31 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9:sub0[ 2 ]
+# CHECK: Vreg: %9:sub1[ 3 ]
+# CHECK: Vreg: %23[ LoopTag*2+30 ]
+# CHECK: Vreg: %1[ LoopTag+24 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ 19 ]
+# CHECK: Vreg: %8[ LoopTag+31 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10:sub0[ 32 ]
+# CHECK: Vreg: %10:sub1[ 33 ]
+# CHECK: Vreg: %36[ 15 ]
+# CHECK: Vreg: %17[ LoopTag*2+30 ]
+# CHECK: Vreg: %24[ LoopTag+28 ]
+# CHECK: Vreg: %19[ LoopTag+25 ]
+# CHECK: Instr: %48:sreg_64 = nsw S_LSHL_B64 killed %47, 3, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ LoopTag*2+30 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %9:sub0[ 1 ]
+# CHECK: Vreg: %9:sub1[ 2 ]
+# CHECK: Vreg: %23[ LoopTag*2+29 ]
+# CHECK: Vreg: %1[ LoopTag+23 ]
+# CHECK: Vreg: %27[ 18 ]
+# CHECK: Vreg: %8[ LoopTag+30 ]
+# CHECK: Vreg: %29[ 12 ]
+# CHECK: Vreg: %10:sub0[ 31 ]
+# CHECK: Vreg: %10:sub1[ 32 ]
+# CHECK: Vreg: %36[ 14 ]
+# CHECK: Vreg: %17[ LoopTag*2+29 ]
+# CHECK: Vreg: %24[ LoopTag+27 ]
+# CHECK: Vreg: %19[ LoopTag+24 ]
+# CHECK: Instr: %49:vgpr_32, %50:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %9.sub0, %48.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %26[ LoopTag*2+29 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %9:sub0[ 0 ]
+# CHECK: Vreg: %9:sub1[ 1 ]
+# CHECK: Vreg: %23[ LoopTag*2+28 ]
+# CHECK: Vreg: %1[ LoopTag+22 ]
+# CHECK: Vreg: %27[ 17 ]
+# CHECK: Vreg: %8[ LoopTag+29 ]
+# CHECK: Vreg: %48:sub0[ 0 ]
+# CHECK: Vreg: %48:sub1[ 1 ]
+# CHECK: Vreg: %29[ 11 ]
+# CHECK: Vreg: %10:sub0[ 30 ]
+# CHECK: Vreg: %10:sub1[ 31 ]
+# CHECK: Vreg: %36[ 13 ]
+# CHECK: Vreg: %17[ LoopTag*2+28 ]
+# CHECK: Vreg: %24[ LoopTag+26 ]
+# CHECK: Vreg: %19[ LoopTag+23 ]
+# CHECK: Instr: %51:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %48.sub1, %9.sub1, killed %50, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %26[ LoopTag*2+28 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %9:sub1[ 0 ]
+# CHECK: Vreg: %9:sub0[ 33 ]
+# CHECK: Vreg: %23[ LoopTag*2+27 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+21 ]
+# CHECK: Vreg: %27[ 16 ]
+# CHECK: Vreg: %8[ LoopTag+28 ]
+# CHECK: Vreg: %48:sub1[ 0 ]
+# CHECK: Vreg: %29[ 10 ]
+# CHECK: Vreg: %10:sub0[ 29 ]
+# CHECK: Vreg: %10:sub1[ 30 ]
+# CHECK: Vreg: %36[ 12 ]
+# CHECK: Vreg: %17[ LoopTag*2+27 ]
+# CHECK: Vreg: %24[ LoopTag+25 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+22 ]
+# CHECK: Instr: %52:vreg_64 = REG_SEQUENCE killed %49, %subreg.sub0, killed %51, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %26[ LoopTag*2+27 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %9:sub0[ 32 ]
+# CHECK: Vreg: %9:sub1[ 33 ]
+# CHECK: Vreg: %23[ LoopTag*2+26 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+20 ]
+# CHECK: Vreg: %27[ 15 ]
+# CHECK: Vreg: %8[ LoopTag+27 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %10:sub0[ 28 ]
+# CHECK: Vreg: %10:sub1[ 29 ]
+# CHECK: Vreg: %36[ 11 ]
+# CHECK: Vreg: %17[ LoopTag*2+26 ]
+# CHECK: Vreg: %24[ LoopTag+24 ]
+# CHECK: Vreg: %19[ LoopTag+21 ]
+# CHECK: Instr: %53:vgpr_32 = GLOBAL_LOAD_UBYTE %52, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %26[ LoopTag*2+26 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %9:sub0[ 31 ]
+# CHECK: Vreg: %9:sub1[ 32 ]
+# CHECK: Vreg: %23[ LoopTag*2+25 ]
+# CHECK: Vreg: %1[ LoopTag+19 ]
+# CHECK: Vreg: %27[ 14 ]
+# CHECK: Vreg: %8[ LoopTag+26 ]
+# CHECK: Vreg: %29[ 8 ]
+# CHECK: Vreg: %10:sub0[ 27 ]
+# CHECK: Vreg: %10:sub1[ 28 ]
+# CHECK: Vreg: %36[ 10 ]
+# CHECK: Vreg: %17[ LoopTag*2+25 ]
+# CHECK: Vreg: %24[ LoopTag+23 ]
+# CHECK: Vreg: %19[ LoopTag+20 ]
+# CHECK: Instr: %54:vgpr_32 = GLOBAL_LOAD_UBYTE %52, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %26[ LoopTag*2+25 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %9:sub0[ 30 ]
+# CHECK: Vreg: %9:sub1[ 31 ]
+# CHECK: Vreg: %23[ LoopTag*2+24 ]
+# CHECK: Vreg: %1[ LoopTag+18 ]
+# CHECK: Vreg: %27[ 13 ]
+# CHECK: Vreg: %8[ LoopTag+25 ]
+# CHECK: Vreg: %53[ 1 ]
+# CHECK: Vreg: %29[ 7 ]
+# CHECK: Vreg: %10:sub0[ 26 ]
+# CHECK: Vreg: %10:sub1[ 27 ]
+# CHECK: Vreg: %36[ 9 ]
+# CHECK: Vreg: %17[ LoopTag*2+24 ]
+# CHECK: Vreg: %24[ LoopTag+22 ]
+# CHECK: Vreg: %19[ LoopTag+19 ]
+# CHECK: Instr: %55:vgpr_32 = V_LSHL_OR_B32_e64 killed %54, 8, killed %53, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ LoopTag*2+24 ]
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %9:sub0[ 29 ]
+# CHECK: Vreg: %9:sub1[ 30 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+23 ]
+# CHECK: Vreg: %1[ LoopTag+17 ]
+# CHECK: Vreg: %27[ 12 ]
+# CHECK: Vreg: %8[ LoopTag+24 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %10:sub0[ 25 ]
+# CHECK: Vreg: %10:sub1[ 26 ]
+# CHECK: Vreg: %36[ 8 ]
+# CHECK: Vreg: %17[ LoopTag*2+23 ]
+# CHECK: Vreg: %24[ LoopTag+21 ]
+# CHECK: Vreg: %19[ LoopTag+18 ]
+# CHECK: Instr: %56:vgpr_32 = GLOBAL_LOAD_UBYTE %52, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %26[ LoopTag*2+23 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %9:sub0[ 28 ]
+# CHECK: Vreg: %9:sub1[ 29 ]
+# CHECK: Vreg: %23[ LoopTag*2+22 ]
+# CHECK: Vreg: %1[ LoopTag+16 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %8[ LoopTag+23 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %10:sub0[ 24 ]
+# CHECK: Vreg: %10:sub1[ 25 ]
+# CHECK: Vreg: %55[ 3 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Vreg: %17[ LoopTag*2+22 ]
+# CHECK: Vreg: %24[ LoopTag+20 ]
+# CHECK: Vreg: %19[ LoopTag+17 ]
+# CHECK: Instr: %57:vgpr_32 = GLOBAL_LOAD_UBYTE killed %52, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %26[ LoopTag*2+22 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %9:sub0[ 27 ]
+# CHECK: Vreg: %9:sub1[ 28 ]
+# CHECK: Vreg: %23[ LoopTag*2+21 ]
+# CHECK: Vreg: %56[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+15 ]
+# CHECK: Vreg: %27[ 10 ]
+# CHECK: Vreg: %8[ LoopTag+22 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %10:sub0[ 23 ]
+# CHECK: Vreg: %10:sub1[ 24 ]
+# CHECK: Vreg: %55[ 2 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %17[ LoopTag*2+21 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %19[ LoopTag+16 ]
+# CHECK: Instr: %58:vgpr_32 = V_LSHL_OR_B32_e64 killed %57, 8, killed %56, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %26[ LoopTag*2+21 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %9:sub0[ 26 ]
+# CHECK: Vreg: %9:sub1[ 27 ]
+# CHECK: Vreg: %23[ LoopTag*2+20 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+14 ]
+# CHECK: Vreg: %27[ 9 ]
+# CHECK: Vreg: %8[ LoopTag+21 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %10:sub0[ 22 ]
+# CHECK: Vreg: %10:sub1[ 23 ]
+# CHECK: Vreg: %55[ 1 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %17[ LoopTag*2+20 ]
+# CHECK: Vreg: %24[ LoopTag+18 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+15 ]
+# CHECK: Instr: %59:vgpr_32 = V_LSHL_OR_B32_e64 killed %58, 16, killed %55, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %26[ LoopTag*2+20 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %9:sub0[ 25 ]
+# CHECK: Vreg: %9:sub1[ 26 ]
+# CHECK: Vreg: %23[ LoopTag*2+19 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+13 ]
+# CHECK: Vreg: %27[ 8 ]
+# CHECK: Vreg: %8[ LoopTag+20 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10:sub0[ 21 ]
+# CHECK: Vreg: %10:sub1[ 22 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %17[ LoopTag*2+19 ]
+# CHECK: Vreg: %24[ LoopTag+17 ]
+# CHECK: Vreg: %19[ LoopTag+14 ]
+# CHECK: Instr: %60:vgpr_32 = V_ADD_U32_e64 %21, killed %59, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ LoopTag*2+19 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9:sub0[ 24 ]
+# CHECK: Vreg: %9:sub1[ 25 ]
+# CHECK: Vreg: %23[ LoopTag*2+18 ]
+# CHECK: Vreg: %1[ LoopTag+12 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %8[ LoopTag+19 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10:sub0[ 20 ]
+# CHECK: Vreg: %10:sub1[ 21 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %17[ LoopTag*2+18 ]
+# CHECK: Vreg: %24[ LoopTag+16 ]
+# CHECK: Vreg: %19[ LoopTag+13 ]
+# CHECK: Instr: %61:sreg_32 = S_ADD_I32 killed %29, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %26[ LoopTag*2+18 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %9:sub0[ 23 ]
+# CHECK: Vreg: %9:sub1[ 24 ]
+# CHECK: Vreg: %23[ LoopTag*2+17 ]
+# CHECK: Vreg: %1[ LoopTag+11 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+18 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10:sub0[ 19 ]
+# CHECK: Vreg: %10:sub1[ 20 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ LoopTag*2+17 ]
+# CHECK: Vreg: %24[ LoopTag+15 ]
+# CHECK: Vreg: %19[ LoopTag+12 ]
+# CHECK: Instr: %62:sreg_32 = V_CMP_GE_U32_e64 %61, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %26[ LoopTag*2+17 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %9:sub0[ 22 ]
+# CHECK: Vreg: %9:sub1[ 23 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+16 ]
+# CHECK: Vreg: %1[ LoopTag+10 ]
+# CHECK: Vreg: %27[ 5 ]
+# CHECK: Vreg: %8[ LoopTag+17 ]
+# CHECK: Vreg: %60[ 4 ]
+# CHECK: Vreg: %10:sub0[ 18 ]
+# CHECK: Vreg: %10:sub1[ 19 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %17[ LoopTag*2+16 ]
+# CHECK: Vreg: %24[ LoopTag+14 ]
+# CHECK: Vreg: %19[ LoopTag+11 ]
+# CHECK: Instr: %63:sreg_32 = S_ANDN2_B32 killed %36, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %26[ LoopTag*2+16 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %9:sub0[ 21 ]
+# CHECK: Vreg: %9:sub1[ 22 ]
+# CHECK: Vreg: %61[ 3 ]
+# CHECK: Vreg: %23[ LoopTag*2+15 ]
+# CHECK: Vreg: %1[ LoopTag+9 ]
+# CHECK: Vreg: %27[ 4 ]
+# CHECK: Vreg: %8[ LoopTag+16 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %10:sub0[ 17 ]
+# CHECK: Vreg: %10:sub1[ 18 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+15 ]
+# CHECK: Vreg: %62[ 1 ]
+# CHECK: Vreg: %24[ LoopTag+13 ]
+# CHECK: Vreg: %19[ LoopTag+10 ]
+# CHECK: Instr: %64:sreg_32 = S_AND_B32 killed %62, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %26[ LoopTag*2+15 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %9:sub0[ 20 ]
+# CHECK: Vreg: %9:sub1[ 21 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %23[ LoopTag*2+14 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+8 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %8[ LoopTag+15 ]
+# CHECK: Vreg: %60[ 2 ]
+# CHECK: Vreg: %10:sub0[ 16 ]
+# CHECK: Vreg: %10:sub1[ 17 ]
+# CHECK: Vreg: %17[ LoopTag*2+14 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %24[ LoopTag+12 ]
+# CHECK: Vreg: %19[ LoopTag+9 ]
+# CHECK: Instr: %65:sreg_32 = S_OR_B32 killed %63, killed %64, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %26[ LoopTag*2+14 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %9:sub0[ 19 ]
+# CHECK: Vreg: %9:sub1[ 20 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %23[ LoopTag*2+13 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+7 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %8[ LoopTag+14 ]
+# CHECK: Vreg: %60[ 1 ]
+# CHECK: Vreg: %10:sub0[ 15 ]
+# CHECK: Vreg: %10:sub1[ 16 ]
+# CHECK: Vreg: %17[ LoopTag*2+13 ]
+# CHECK: Vreg: %24[ LoopTag+11 ]
+# CHECK: Vreg: %19[ LoopTag+8 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %26[ LoopTag*2+13 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+12 ]
+# CHECK: Vreg: %1[ LoopTag+6 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+13 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ LoopTag*2+12 ]
+# CHECK: Vreg: %24[ LoopTag+10 ]
+# CHECK: Vreg: %19[ LoopTag+7 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %26[ LoopTag*2+13 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+12 ]
+# CHECK: Vreg: %1[ LoopTag+6 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+13 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ LoopTag*2+12 ]
+# CHECK: Vreg: %24[ LoopTag+10 ]
+# CHECK: Vreg: %19[ LoopTag+7 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %66:sreg_32 = S_SUB_I32 %29, %21, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %26[ LoopTag*2+37 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9:sub0[ 28 ]
+# CHECK: Vreg: %9:sub1[ 29 ]
+# CHECK: Vreg: %23[ LoopTag*2+36 ]
+# CHECK: Vreg: %1[ LoopTag+30 ]
+# CHECK: Vreg: %27[ 25 ]
+# CHECK: Vreg: %8[ LoopTag+37 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10:sub0[ 4 ]
+# CHECK: Vreg: %10:sub1[ 5 ]
+# CHECK: Vreg: %17[ LoopTag*2+36 ]
+# CHECK: Vreg: %24[ LoopTag+34 ]
+# CHECK: Vreg: %19[ LoopTag+31 ]
+# CHECK: Instr: %67:sreg_32_xm0 = S_ASHR_I32 %66, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %26[ LoopTag*2+36 ]
+# CHECK: Vreg: %21[ 29 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %9:sub0[ 27 ]
+# CHECK: Vreg: %9:sub1[ 28 ]
+# CHECK: Vreg: %23[ LoopTag*2+35 ]
+# CHECK: Vreg: %1[ LoopTag+29 ]
+# CHECK: Vreg: %27[ 24 ]
+# CHECK: Vreg: %8[ LoopTag+36 ]
+# CHECK: Vreg: %29[ 13 ]
+# CHECK: Vreg: %10:sub0[ 3 ]
+# CHECK: Vreg: %10:sub1[ 4 ]
+# CHECK: Vreg: %17[ LoopTag*2+35 ]
+# CHECK: Vreg: %24[ LoopTag+33 ]
+# CHECK: Vreg: %19[ LoopTag+30 ]
+# CHECK: Instr: %68:sreg_64 = REG_SEQUENCE killed %66, %subreg.sub0, killed %67, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %26[ LoopTag*2+35 ]
+# CHECK: Vreg: %21[ 28 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %9:sub0[ 26 ]
+# CHECK: Vreg: %9:sub1[ 27 ]
+# CHECK: Vreg: %23[ LoopTag*2+34 ]
+# CHECK: Vreg: %1[ LoopTag+28 ]
+# CHECK: Vreg: %27[ 23 ]
+# CHECK: Vreg: %8[ LoopTag+35 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %29[ 12 ]
+# CHECK: Vreg: %10:sub0[ 2 ]
+# CHECK: Vreg: %10:sub1[ 3 ]
+# CHECK: Vreg: %17[ LoopTag*2+34 ]
+# CHECK: Vreg: %24[ LoopTag+32 ]
+# CHECK: Vreg: %19[ LoopTag+29 ]
+# CHECK: Instr: %69:sreg_64 = nsw S_LSHL_B64 killed %68, 3, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %26[ LoopTag*2+34 ]
+# CHECK: Vreg: %21[ 27 ]
+# CHECK: Vreg: %9:sub0[ 25 ]
+# CHECK: Vreg: %9:sub1[ 26 ]
+# CHECK: Vreg: %23[ LoopTag*2+33 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+27 ]
+# CHECK: Vreg: %27[ 22 ]
+# CHECK: Vreg: %8[ LoopTag+34 ]
+# CHECK: Vreg: %29[ 11 ]
+# CHECK: Vreg: %10:sub0[ 1 ]
+# CHECK: Vreg: %10:sub1[ 2 ]
+# CHECK: Vreg: %17[ LoopTag*2+33 ]
+# CHECK: Vreg: %24[ LoopTag+31 ]
+# CHECK: Vreg: %19[ LoopTag+28 ]
+# CHECK: Instr: %70:vgpr_32, %71:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %10.sub0, %69.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %26[ LoopTag*2+33 ]
+# CHECK: Vreg: %21[ 26 ]
+# CHECK: Vreg: %9:sub0[ 24 ]
+# CHECK: Vreg: %9:sub1[ 25 ]
+# CHECK: Vreg: %23[ LoopTag*2+32 ]
+# CHECK: Vreg: %1[ LoopTag+26 ]
+# CHECK: Vreg: %27[ 21 ]
+# CHECK: Vreg: %8[ LoopTag+33 ]
+# CHECK: Vreg: %29[ 10 ]
+# CHECK: Vreg: %10:sub0[ 0 ]
+# CHECK: Vreg: %10:sub1[ 1 ]
+# CHECK: Vreg: %17[ LoopTag*2+32 ]
+# CHECK: Vreg: %24[ LoopTag+30 ]
+# CHECK: Vreg: %69:sub0[ 0 ]
+# CHECK: Vreg: %69:sub1[ 1 ]
+# CHECK: Vreg: %19[ LoopTag+27 ]
+# CHECK: Instr: %72:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %69.sub1, %10.sub1, killed %71, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %26[ LoopTag*2+32 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %21[ 25 ]
+# CHECK: Vreg: %9:sub0[ 23 ]
+# CHECK: Vreg: %9:sub1[ 24 ]
+# CHECK: Vreg: %23[ LoopTag*2+31 ]
+# CHECK: Vreg: %70[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+25 ]
+# CHECK: Vreg: %27[ 20 ]
+# CHECK: Vreg: %8[ LoopTag+32 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %10:sub1[ 0 ]
+# CHECK: Vreg: %10:sub0[ 33 ]
+# CHECK: Vreg: %17[ LoopTag*2+31 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %69:sub1[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+26 ]
+# CHECK: Instr: %73:vreg_64 = REG_SEQUENCE killed %70, %subreg.sub0, killed %72, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %26[ LoopTag*2+31 ]
+# CHECK: Vreg: %21[ 24 ]
+# CHECK: Vreg: %9:sub0[ 22 ]
+# CHECK: Vreg: %9:sub1[ 23 ]
+# CHECK: Vreg: %23[ LoopTag*2+30 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+24 ]
+# CHECK: Vreg: %27[ 19 ]
+# CHECK: Vreg: %8[ LoopTag+31 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %29[ 8 ]
+# CHECK: Vreg: %10:sub0[ 32 ]
+# CHECK: Vreg: %10:sub1[ 33 ]
+# CHECK: Vreg: %17[ LoopTag*2+30 ]
+# CHECK: Vreg: %24[ LoopTag+28 ]
+# CHECK: Vreg: %19[ LoopTag+25 ]
+# CHECK: Instr: %74:vgpr_32 = GLOBAL_LOAD_UBYTE %73, 0, 0, implicit $exec :: (load (s8) from %ir.gep2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %26[ LoopTag*2+30 ]
+# CHECK: Vreg: %21[ 23 ]
+# CHECK: Vreg: %9:sub0[ 21 ]
+# CHECK: Vreg: %9:sub1[ 22 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+29 ]
+# CHECK: Vreg: %1[ LoopTag+23 ]
+# CHECK: Vreg: %27[ 18 ]
+# CHECK: Vreg: %8[ LoopTag+30 ]
+# CHECK: Vreg: %29[ 7 ]
+# CHECK: Vreg: %10:sub0[ 31 ]
+# CHECK: Vreg: %10:sub1[ 32 ]
+# CHECK: Vreg: %17[ LoopTag*2+29 ]
+# CHECK: Vreg: %24[ LoopTag+27 ]
+# CHECK: Vreg: %19[ LoopTag+24 ]
+# CHECK: Instr: %75:vgpr_32 = GLOBAL_LOAD_UBYTE %73, 1, 0, implicit $exec :: (load (s8) from %ir.gep2 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %26[ LoopTag*2+29 ]
+# CHECK: Vreg: %21[ 22 ]
+# CHECK: Vreg: %9:sub0[ 20 ]
+# CHECK: Vreg: %9:sub1[ 21 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+28 ]
+# CHECK: Vreg: %1[ LoopTag+22 ]
+# CHECK: Vreg: %27[ 17 ]
+# CHECK: Vreg: %8[ LoopTag+29 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %10:sub0[ 30 ]
+# CHECK: Vreg: %10:sub1[ 31 ]
+# CHECK: Vreg: %74[ 1 ]
+# CHECK: Vreg: %17[ LoopTag*2+28 ]
+# CHECK: Vreg: %24[ LoopTag+26 ]
+# CHECK: Vreg: %19[ LoopTag+23 ]
+# CHECK: Instr: %76:vgpr_32 = V_LSHL_OR_B32_e64 killed %75, 8, killed %74, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ LoopTag*2+28 ]
+# CHECK: Vreg: %21[ 21 ]
+# CHECK: Vreg: %9:sub0[ 19 ]
+# CHECK: Vreg: %9:sub1[ 20 ]
+# CHECK: Vreg: %73[ 1 ]
+# CHECK: Vreg: %23[ LoopTag*2+27 ]
+# CHECK: Vreg: %75[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+21 ]
+# CHECK: Vreg: %27[ 16 ]
+# CHECK: Vreg: %8[ LoopTag+28 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %10:sub0[ 29 ]
+# CHECK: Vreg: %10:sub1[ 30 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+27 ]
+# CHECK: Vreg: %24[ LoopTag+25 ]
+# CHECK: Vreg: %19[ LoopTag+22 ]
+# CHECK: Instr: %77:vgpr_32 = GLOBAL_LOAD_UBYTE %73, 2, 0, implicit $exec :: (load (s8) from %ir.gep2 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %26[ LoopTag*2+27 ]
+# CHECK: Vreg: %21[ 20 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+26 ]
+# CHECK: Vreg: %1[ LoopTag+20 ]
+# CHECK: Vreg: %27[ 15 ]
+# CHECK: Vreg: %8[ LoopTag+27 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %10:sub0[ 28 ]
+# CHECK: Vreg: %10:sub1[ 29 ]
+# CHECK: Vreg: %17[ LoopTag*2+26 ]
+# CHECK: Vreg: %24[ LoopTag+24 ]
+# CHECK: Vreg: %76[ 3 ]
+# CHECK: Vreg: %19[ LoopTag+21 ]
+# CHECK: Instr: %78:vgpr_32 = GLOBAL_LOAD_UBYTE killed %73, 3, 0, implicit $exec :: (load (s8) from %ir.gep2 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %26[ LoopTag*2+26 ]
+# CHECK: Vreg: %21[ 19 ]
+# CHECK: Vreg: %9:sub0[ 17 ]
+# CHECK: Vreg: %9:sub1[ 18 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+25 ]
+# CHECK: Vreg: %77[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+19 ]
+# CHECK: Vreg: %27[ 14 ]
+# CHECK: Vreg: %8[ LoopTag+26 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %10:sub0[ 27 ]
+# CHECK: Vreg: %10:sub1[ 28 ]
+# CHECK: Vreg: %17[ LoopTag*2+25 ]
+# CHECK: Vreg: %24[ LoopTag+23 ]
+# CHECK: Vreg: %76[ 2 ]
+# CHECK: Vreg: %19[ LoopTag+20 ]
+# CHECK: Instr: %79:vgpr_32 = V_LSHL_OR_B32_e64 killed %78, 8, killed %77, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %26[ LoopTag*2+25 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %21[ 18 ]
+# CHECK: Vreg: %9:sub0[ 16 ]
+# CHECK: Vreg: %9:sub1[ 17 ]
+# CHECK: Vreg: %23[ LoopTag*2+24 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+18 ]
+# CHECK: Vreg: %27[ 13 ]
+# CHECK: Vreg: %8[ LoopTag+25 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10:sub0[ 26 ]
+# CHECK: Vreg: %10:sub1[ 27 ]
+# CHECK: Vreg: %17[ LoopTag*2+24 ]
+# CHECK: Vreg: %24[ LoopTag+22 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: Vreg: %19[ LoopTag+19 ]
+# CHECK: Instr: %80:vgpr_32 = V_LSHL_OR_B32_e64 killed %79, 16, killed %76, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %26[ LoopTag*2+24 ]
+# CHECK: Vreg: %21[ 17 ]
+# CHECK: Vreg: %9:sub0[ 15 ]
+# CHECK: Vreg: %9:sub1[ 16 ]
+# CHECK: Vreg: %23[ LoopTag*2+23 ]
+# CHECK: Vreg: %1[ LoopTag+17 ]
+# CHECK: Vreg: %27[ 12 ]
+# CHECK: Vreg: %8[ LoopTag+24 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10:sub0[ 25 ]
+# CHECK: Vreg: %10:sub1[ 26 ]
+# CHECK: Vreg: %17[ LoopTag*2+23 ]
+# CHECK: Vreg: %24[ LoopTag+21 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+18 ]
+# CHECK: Instr: %39:vgpr_32 = V_SUBREV_U32_e64 %29, killed %80, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %26[ LoopTag*2+23 ]
+# CHECK: Vreg: %21[ 16 ]
+# CHECK: Vreg: %9:sub0[ 14 ]
+# CHECK: Vreg: %9:sub1[ 15 ]
+# CHECK: Vreg: %80[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+22 ]
+# CHECK: Vreg: %1[ LoopTag+16 ]
+# CHECK: Vreg: %27[ 11 ]
+# CHECK: Vreg: %8[ LoopTag+23 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10:sub0[ 24 ]
+# CHECK: Vreg: %10:sub1[ 25 ]
+# CHECK: Vreg: %17[ LoopTag*2+22 ]
+# CHECK: Vreg: %24[ LoopTag+20 ]
+# CHECK: Vreg: %19[ LoopTag+17 ]
+# CHECK: Instr: %41:sreg_32 = S_ADD_I32 %29, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %26[ LoopTag*2+22 ]
+# CHECK: Vreg: %21[ 15 ]
+# CHECK: Vreg: %9:sub0[ 13 ]
+# CHECK: Vreg: %9:sub1[ 14 ]
+# CHECK: Vreg: %23[ LoopTag*2+21 ]
+# CHECK: Vreg: %39[ 4 ]
+# CHECK: Vreg: %1[ LoopTag+15 ]
+# CHECK: Vreg: %27[ 10 ]
+# CHECK: Vreg: %8[ LoopTag+22 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10:sub0[ 23 ]
+# CHECK: Vreg: %10:sub1[ 24 ]
+# CHECK: Vreg: %17[ LoopTag*2+21 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %19[ LoopTag+16 ]
+# CHECK: Instr: %81:sreg_32 = V_CMP_GE_U32_e64 %41, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %26[ LoopTag*2+21 ]
+# CHECK: Vreg: %21[ 14 ]
+# CHECK: Vreg: %9:sub0[ 12 ]
+# CHECK: Vreg: %9:sub1[ 13 ]
+# CHECK: Vreg: %23[ LoopTag*2+20 ]
+# CHECK: Vreg: %39[ 3 ]
+# CHECK: Vreg: %1[ LoopTag+14 ]
+# CHECK: Vreg: %27[ 9 ]
+# CHECK: Vreg: %8[ LoopTag+21 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %10:sub0[ 22 ]
+# CHECK: Vreg: %10:sub1[ 23 ]
+# CHECK: Vreg: %17[ LoopTag*2+20 ]
+# CHECK: Vreg: %24[ LoopTag+18 ]
+# CHECK: Vreg: %19[ LoopTag+15 ]
+# CHECK: Instr: %43:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %26[ LoopTag*2+20 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %9:sub0[ 11 ]
+# CHECK: Vreg: %9:sub1[ 12 ]
+# CHECK: Vreg: %23[ LoopTag*2+19 ]
+# CHECK: Vreg: %39[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+13 ]
+# CHECK: Vreg: %27[ 8 ]
+# CHECK: Vreg: %8[ LoopTag+20 ]
+# CHECK: Vreg: %41[ 2 ]
+# CHECK: Vreg: %29[ 8 ]
+# CHECK: Vreg: %10:sub0[ 21 ]
+# CHECK: Vreg: %10:sub1[ 22 ]
+# CHECK: Vreg: %17[ LoopTag*2+19 ]
+# CHECK: Vreg: %81[ 1 ]
+# CHECK: Vreg: %24[ LoopTag+17 ]
+# CHECK: Vreg: %19[ LoopTag+14 ]
+# CHECK: Instr: %37:sreg_32 = S_ORN2_B32 killed %81, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %26[ LoopTag*2+19 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %9:sub0[ 10 ]
+# CHECK: Vreg: %9:sub1[ 11 ]
+# CHECK: Vreg: %23[ LoopTag*2+18 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+12 ]
+# CHECK: Vreg: %27[ 7 ]
+# CHECK: Vreg: %8[ LoopTag+19 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %29[ 7 ]
+# CHECK: Vreg: %10:sub0[ 20 ]
+# CHECK: Vreg: %10:sub1[ 21 ]
+# CHECK: Vreg: %17[ LoopTag*2+18 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Vreg: %43[ 1 ]
+# CHECK: Vreg: %24[ LoopTag+16 ]
+# CHECK: Vreg: %19[ LoopTag+13 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %26[ LoopTag*2+18 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %9:sub0[ 9 ]
+# CHECK: Vreg: %9:sub1[ 10 ]
+# CHECK: Vreg: %23[ LoopTag*2+17 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+11 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+18 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %10:sub0[ 19 ]
+# CHECK: Vreg: %10:sub1[ 20 ]
+# CHECK: Vreg: %17[ LoopTag*2+17 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %24[ LoopTag+15 ]
+# CHECK: Vreg: %19[ LoopTag+12 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %26[ LoopTag*2+18 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %9:sub0[ 9 ]
+# CHECK: Vreg: %9:sub1[ 10 ]
+# CHECK: Vreg: %23[ LoopTag*2+17 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+11 ]
+# CHECK: Vreg: %27[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+18 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %10:sub0[ 19 ]
+# CHECK: Vreg: %10:sub1[ 20 ]
+# CHECK: Vreg: %17[ LoopTag*2+17 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %24[ LoopTag+15 ]
+# CHECK: Vreg: %19[ LoopTag+12 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %82:sreg_32 = PHI %36, %bb.3, %65, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %26[ LoopTag*2+13 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+12 ]
+# CHECK: Vreg: %1[ LoopTag+6 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+13 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+12 ]
+# CHECK: Vreg: %24[ LoopTag+10 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+7 ]
+# CHECK: Instr: %31:vgpr_32 = PHI %38, %bb.3, %60, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %26[ LoopTag*2+13 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+12 ]
+# CHECK: Vreg: %82[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+6 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+13 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ LoopTag*2+12 ]
+# CHECK: Vreg: %24[ LoopTag+10 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+7 ]
+# CHECK: Instr: %30:sreg_32 = PHI %40, %bb.3, %61, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %26[ LoopTag*2+13 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+12 ]
+# CHECK: Vreg: %82[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+6 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+13 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ LoopTag*2+12 ]
+# CHECK: Vreg: %24[ LoopTag+10 ]
+# CHECK: Vreg: %31[ 3 ]
+# CHECK: Vreg: %19[ LoopTag+7 ]
+# CHECK: Instr: %28:sreg_32 = SI_IF_BREAK killed %82, killed %27, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %26[ LoopTag*2+12 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %9:sub0[ 17 ]
+# CHECK: Vreg: %9:sub1[ 18 ]
+# CHECK: Vreg: %23[ LoopTag*2+11 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %82[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+5 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+12 ]
+# CHECK: Vreg: %10:sub0[ 13 ]
+# CHECK: Vreg: %10:sub1[ 14 ]
+# CHECK: Vreg: %17[ LoopTag*2+11 ]
+# CHECK: Vreg: %24[ LoopTag+9 ]
+# CHECK: Vreg: %31[ 2 ]
+# CHECK: Vreg: %19[ LoopTag+6 ]
+# CHECK: Instr: SI_LOOP %28, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %26[ LoopTag*2+11 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 16 ]
+# CHECK: Vreg: %9:sub1[ 17 ]
+# CHECK: Vreg: %23[ LoopTag*2+10 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+4 ]
+# CHECK: Vreg: %8[ LoopTag+11 ]
+# CHECK: Vreg: %10:sub0[ 12 ]
+# CHECK: Vreg: %10:sub1[ 13 ]
+# CHECK: Vreg: %17[ LoopTag*2+10 ]
+# CHECK: Vreg: %24[ LoopTag+8 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: Vreg: %19[ LoopTag+5 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %26[ LoopTag*2+10 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 15 ]
+# CHECK: Vreg: %9:sub1[ 16 ]
+# CHECK: Vreg: %23[ LoopTag*2+9 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+3 ]
+# CHECK: Vreg: %8[ LoopTag+10 ]
+# CHECK: Vreg: %10:sub0[ 11 ]
+# CHECK: Vreg: %10:sub1[ 12 ]
+# CHECK: Vreg: %17[ LoopTag*2+9 ]
+# CHECK: Vreg: %24[ LoopTag+7 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %26[ LoopTag*2+10 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 15 ]
+# CHECK: Vreg: %9:sub1[ 16 ]
+# CHECK: Vreg: %23[ LoopTag*2+9 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+3 ]
+# CHECK: Vreg: %8[ LoopTag+10 ]
+# CHECK: Vreg: %10:sub0[ 11 ]
+# CHECK: Vreg: %10:sub1[ 12 ]
+# CHECK: Vreg: %17[ LoopTag*2+9 ]
+# CHECK: Vreg: %24[ LoopTag+7 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+4 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: SI_END_CF killed %28, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %26[ LoopTag+9 ]
+# CHECK: Vreg: %19[ 3 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 24 ]
+# CHECK: Vreg: %9:sub1[ 25 ]
+# CHECK: Vreg: %23[ LoopTag+8 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %8[ 9 ]
+# CHECK: Vreg: %10:sub0[ 20 ]
+# CHECK: Vreg: %10:sub1[ 21 ]
+# CHECK: Vreg: %17[ LoopTag+8 ]
+# CHECK: Vreg: %24[ 6 ]
+# CHECK: Instr: %22:sreg_32 = S_ADD_I32 killed %21, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %26[ LoopTag+8 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9:sub0[ 23 ]
+# CHECK: Vreg: %9:sub1[ 24 ]
+# CHECK: Vreg: %23[ LoopTag+7 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %8[ 8 ]
+# CHECK: Vreg: %10:sub0[ 19 ]
+# CHECK: Vreg: %10:sub1[ 20 ]
+# CHECK: Vreg: %17[ LoopTag+7 ]
+# CHECK: Vreg: %24[ 5 ]
+# CHECK: Instr: %83:sreg_32 = V_CMP_GE_U32_e64 %22, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %26[ LoopTag+7 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Vreg: %9:sub0[ 22 ]
+# CHECK: Vreg: %9:sub1[ 23 ]
+# CHECK: Vreg: %23[ LoopTag+6 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %8[ 7 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10:sub0[ 18 ]
+# CHECK: Vreg: %10:sub1[ 19 ]
+# CHECK: Vreg: %17[ LoopTag+6 ]
+# CHECK: Vreg: %24[ 4 ]
+# CHECK: Instr: %20:sreg_32 = SI_IF_BREAK killed %83, killed %19, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %26[ LoopTag+6 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Vreg: %9:sub0[ 21 ]
+# CHECK: Vreg: %9:sub1[ 22 ]
+# CHECK: Vreg: %23[ LoopTag+5 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %8[ 6 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %10:sub0[ 17 ]
+# CHECK: Vreg: %10:sub1[ 18 ]
+# CHECK: Vreg: %17[ LoopTag+5 ]
+# CHECK: Vreg: %24[ 3 ]
+# CHECK: Vreg: %83[ 0 ]
+# CHECK: Instr: %84:vgpr_32 = COPY %22, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %26[ LoopTag+5 ]
+# CHECK: Vreg: %9:sub0[ 20 ]
+# CHECK: Vreg: %9:sub1[ 21 ]
+# CHECK: Vreg: %23[ LoopTag+4 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %8[ 5 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10:sub0[ 16 ]
+# CHECK: Vreg: %10:sub1[ 17 ]
+# CHECK: Vreg: %17[ LoopTag+4 ]
+# CHECK: Vreg: %24[ 2 ]
+# CHECK: Instr: SI_LOOP %20, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %26[ LoopTag+4 ]
+# CHECK: Vreg: %9:sub0[ 19 ]
+# CHECK: Vreg: %9:sub1[ 20 ]
+# CHECK: Vreg: %23[ LoopTag+3 ]
+# CHECK: Vreg: %84[ LoopTag+3 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %10:sub0[ 15 ]
+# CHECK: Vreg: %10:sub1[ 16 ]
+# CHECK: Vreg: %17[ LoopTag+3 ]
+# CHECK: Vreg: %24[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %26[ LoopTag+3 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %23[ LoopTag+2 ]
+# CHECK: Vreg: %84[ LoopTag+2 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ LoopTag+2 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %26[ LoopTag+3 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %23[ LoopTag+2 ]
+# CHECK: Vreg: %84[ LoopTag+2 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10:sub0[ 14 ]
+# CHECK: Vreg: %10:sub1[ 15 ]
+# CHECK: Vreg: %17[ LoopTag+2 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: SI_END_CF killed %20, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %84[ 1 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Instr: %85:vgpr_32 = V_ADD3_U32_e64 killed %23, killed %84, killed %17, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: %86:vgpr_32 = V_ADD3_U32_e64 killed %85, killed %26, 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Instr: %87:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %86, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %87
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test10(ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, i32 %TC1, i32 %TC2) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  %add1 = add i32 %ld1, 100
+  br label %1
+  1:
+  %phi.inc1 = phi i32 [ 0, %0 ], [ %inc1, %7 ]
+  %phi1 = phi i32 [ %ld1, %0 ], [ %phi2, %7 ]
+  br label %2
+  2:
+  %mul = mul i32 %phi1, 100
+  store i32 %mul, ptr addrspace(1) %p3
+  br label %3
+  3:
+  %phi.inc2 = phi i32 [ 0, %2 ], [ %inc2, %4 ], [ %inc3, %6 ]
+  %phi2 = phi i32 [ 100, %2 ], [ %add2, %4 ], [ %sub2, %6 ]
+  %cond1 = icmp ugt i32 %phi.inc1, %phi.inc2
+  br i1 %cond1, label %4, label %5
+  4:
+  %sext1 = sext i32 %phi.inc2 to i64
+  %gep1 = getelementptr inbounds i64, ptr addrspace(1) %p2, i64 %sext1
+  %ld2 = load i32, ptr addrspace(1) %gep1, align 1
+  %add2 = add i32 %ld2, %phi.inc1
+  %inc2 = add i32 %phi.inc2, 1
+  %cond2 = icmp ult i32 %inc2, %TC2
+  br i1 %cond2, label %3, label %7
+  5:
+  %sub1 = sub i32 %phi.inc2, %phi.inc1
+  %sext2 = sext i32 %sub1 to i64
+  %gep2 = getelementptr inbounds i64, ptr addrspace(1) %p1, i64 %sext2
+  %ld3 = load i32, ptr addrspace(1) %gep2, align 1
+  %sub2 = sub i32 %ld3, %phi.inc2
+  br label %6
+  6:
+  %inc3 = add i32 %phi.inc2, 2
+  %cond3 = icmp ult i32 %inc3, %TC2
+  br i1 %cond3, label %3, label %7
+  7:
+  %inc1 = add i32 %phi.inc1, 1
+  %add3 = add i32 %phi1, %inc1
+  %cond4 = icmp ult i32 %inc1, %TC1
+  br i1 %cond4, label %1, label %8
+  8:
+  %add4 = add i32 %add3, %add1
+  %add5 = add i32 %add4, %mul
+  ret i32 %add5
+  }
+...
+
+---
+name:            test10
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
+  
+    %37:vgpr_32 = COPY killed $vgpr7
+    %36:vgpr_32 = COPY killed $vgpr6
+    %35:vgpr_32 = COPY killed $vgpr5
+    %34:vgpr_32 = COPY killed $vgpr4
+    %33:vgpr_32 = COPY killed $vgpr3
+    %32:vgpr_32 = COPY killed $vgpr2
+    %31:vgpr_32 = COPY killed $vgpr1
+    %30:vgpr_32 = COPY killed $vgpr0
+    %106:vreg_64 = REG_SEQUENCE killed %34, %subreg.sub0, killed %35, %subreg.sub1
+    %105:vreg_64 = REG_SEQUENCE killed %32, %subreg.sub0, killed %33, %subreg.sub1
+    %104:vreg_64 = REG_SEQUENCE killed %30, %subreg.sub0, killed %31, %subreg.sub1
+    %45:vgpr_32 = GLOBAL_LOAD_UBYTE %104, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %47:vgpr_32 = GLOBAL_LOAD_UBYTE %104, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %50:vgpr_32 = V_LSHL_OR_B32_e64 killed %47, 8, killed %45, implicit $exec
+    %51:vgpr_32 = GLOBAL_LOAD_UBYTE %104, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %53:vgpr_32 = GLOBAL_LOAD_UBYTE %104, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %55:vgpr_32 = V_LSHL_OR_B32_e64 killed %53, 8, killed %51, implicit $exec
+    %0:vgpr_32 = V_LSHL_OR_B32_e64 killed %55, 16, killed %50, implicit $exec
+    %41:sreg_32 = S_MOV_B32 0
+  
+  bb.1:
+    successors: %bb.2(0x80000000)
+  
+    %1:sreg_32 = PHI %41, %bb.0, %25, %bb.7
+    %2:sreg_32 = PHI %41, %bb.0, %24, %bb.7
+    %3:vgpr_32 = PHI %0, %bb.0, %7, %bb.7
+    %58:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+    %4:vgpr_32 = V_MUL_LO_U32_e64 100, %3, implicit $exec
+    GLOBAL_STORE_DWORD %106, %4, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+  
+  bb.2:
+    successors: %bb.5(0x40000000), %bb.3(0x40000000)
+  
+    %5:sreg_32 = PHI %41, %bb.1, %21, %bb.6
+    %6:sreg_32 = PHI %41, %bb.1, %19, %bb.6
+    %7:vgpr_32 = PHI %58, %bb.1, %18, %bb.6
+    %61:sreg_32 = S_MOV_B32 -1
+    %60:sreg_32 = S_MOV_B32 -1
+    S_CMP_GE_U32 %6, %2, implicit-def $scc
+    %102:sgpr_32 = V_READFIRSTLANE_B32 undef %59:vgpr_32, implicit $exec
+    S_CBRANCH_SCC1 %bb.5, implicit killed $scc
+    S_BRANCH %bb.3
+  
+  bb.3:
+    successors: %bb.4(0x40000000), %bb.6(0x40000000)
+  
+    %10:sreg_32 = PHI %61, %bb.2, %108, %bb.5
+    %8:vgpr_32 = PHI undef %59:vgpr_32, %bb.2, %15, %bb.5
+    %9:sreg_32 = PHI %102, %bb.2, %16, %bb.5
+    %11:sreg_32_xm0_xexec = PHI %60, %bb.2, %62, %bb.5
+    %81:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %11, implicit $exec
+    %103:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, killed %81, implicit $exec
+    $vcc_lo = S_AND_B32 $exec_lo, killed %103, implicit-def dead $scc
+    S_CBRANCH_VCCNZ %bb.6, implicit killed $vcc_lo, implicit $vcc
+    S_BRANCH %bb.4
+  
+  bb.4:
+    successors: %bb.6(0x80000000)
+  
+    %84:sreg_32_xm0 = S_ASHR_I32 %6, 31, implicit-def dead $scc
+    %86:sreg_64 = REG_SEQUENCE %6, %subreg.sub0, killed %84, %subreg.sub1
+    %88:sreg_64 = nsw S_LSHL_B64 killed %86, 3, implicit-def dead $scc
+    %112:vgpr_32, %114:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %105.sub0, %88.sub0, 0, implicit $exec
+    %113:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %88.sub1, %105.sub1, killed %114, 0, implicit $exec
+    %89:vreg_64 = REG_SEQUENCE killed %112, %subreg.sub0, killed %113, %subreg.sub1
+    %90:vgpr_32 = GLOBAL_LOAD_UBYTE %89, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+    %91:vgpr_32 = GLOBAL_LOAD_UBYTE %89, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+    %92:vgpr_32 = V_LSHL_OR_B32_e64 killed %91, 8, killed %90, implicit $exec
+    %93:vgpr_32 = GLOBAL_LOAD_UBYTE %89, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+    %94:vgpr_32 = GLOBAL_LOAD_UBYTE killed %89, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+    %95:vgpr_32 = V_LSHL_OR_B32_e64 killed %94, 8, killed %93, implicit $exec
+    %96:vgpr_32 = V_LSHL_OR_B32_e64 killed %95, 16, killed %92, implicit $exec
+    %12:vgpr_32 = V_ADD_U32_e64 %2, killed %96, 0, implicit $exec
+    %13:sreg_32 = S_ADD_I32 killed %6, 1, implicit-def dead $scc
+    %97:sreg_32 = V_CMP_GE_U32_e64 %13, %37, implicit $exec
+    %110:sreg_32 = S_ANDN2_B32 killed %10, $exec_lo, implicit-def dead $scc
+    %111:sreg_32 = S_AND_B32 killed %97, $exec_lo, implicit-def dead $scc
+    %109:sreg_32 = S_OR_B32 killed %110, killed %111, implicit-def dead $scc
+    S_BRANCH %bb.6
+  
+  bb.5:
+    successors: %bb.3(0x80000000)
+  
+    %63:sreg_32 = S_SUB_I32 %6, %2, implicit-def dead $scc
+    %64:sreg_32_xm0 = S_ASHR_I32 %63, 31, implicit-def dead $scc
+    %66:sreg_64 = REG_SEQUENCE killed %63, %subreg.sub0, killed %64, %subreg.sub1
+    %68:sreg_64 = nsw S_LSHL_B64 killed %66, 3, implicit-def dead $scc
+    %115:vgpr_32, %117:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %104.sub0, %68.sub0, 0, implicit $exec
+    %116:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %68.sub1, %104.sub1, killed %117, 0, implicit $exec
+    %69:vreg_64 = REG_SEQUENCE killed %115, %subreg.sub0, killed %116, %subreg.sub1
+    %70:vgpr_32 = GLOBAL_LOAD_UBYTE %69, 0, 0, implicit $exec :: (load (s8) from %ir.gep2, addrspace 1)
+    %71:vgpr_32 = GLOBAL_LOAD_UBYTE %69, 1, 0, implicit $exec :: (load (s8) from %ir.gep2 + 1, addrspace 1)
+    %73:vgpr_32 = V_LSHL_OR_B32_e64 killed %71, 8, killed %70, implicit $exec
+    %74:vgpr_32 = GLOBAL_LOAD_UBYTE %69, 2, 0, implicit $exec :: (load (s8) from %ir.gep2 + 2, addrspace 1)
+    %75:vgpr_32 = GLOBAL_LOAD_UBYTE killed %69, 3, 0, implicit $exec :: (load (s8) from %ir.gep2 + 3, addrspace 1)
+    %76:vgpr_32 = V_LSHL_OR_B32_e64 killed %75, 8, killed %74, implicit $exec
+    %78:vgpr_32 = V_LSHL_OR_B32_e64 killed %76, 16, killed %73, implicit $exec
+    %15:vgpr_32 = V_SUBREV_U32_e64 %6, killed %78, 0, implicit $exec
+    %16:sreg_32 = S_ADD_I32 %6, 2, implicit-def dead $scc
+    %80:sreg_32 = V_CMP_GE_U32_e64 %16, %37, implicit $exec
+    %62:sreg_32 = S_MOV_B32 0
+    %108:sreg_32 = S_ORN2_B32 killed %80, $exec_lo, implicit-def dead $scc
+    S_BRANCH %bb.3
+  
+  bb.6:
+    successors: %bb.7(0x04000000), %bb.2(0x7c000000)
+  
+    %20:sreg_32 = PHI %10, %bb.3, %109, %bb.4
+    %18:vgpr_32 = PHI %8, %bb.3, %12, %bb.4
+    %19:sreg_32 = PHI %9, %bb.3, %13, %bb.4
+    %21:sreg_32 = SI_IF_BREAK killed %20, killed %5, implicit-def dead $scc
+    SI_LOOP %21, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.7
+  
+  bb.7:
+    successors: %bb.8(0x04000000), %bb.1(0x7c000000)
+  
+    SI_END_CF killed %21, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %24:sreg_32 = S_ADD_I32 killed %2, 1, implicit-def dead $scc
+    %98:sreg_32 = V_CMP_GE_U32_e64 %24, %36, implicit $exec
+    %25:sreg_32 = SI_IF_BREAK killed %98, killed %1, implicit-def dead $scc
+    %107:vgpr_32 = COPY %24, implicit $exec
+    SI_LOOP %25, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.8
+  
+  bb.8:
+    SI_END_CF killed %25, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %99:vgpr_32 = V_ADD3_U32_e64 killed %3, killed %107, killed %0, implicit $exec
+    %100:vgpr_32 = V_ADD3_U32_e64 killed %99, killed %4, 100, implicit $exec
+    %101:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %100, implicit $exec
+    $sgpr0 = COPY killed %101
+    SI_RETURN_TO_EPILOG killed $sgpr0
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
new file mode 100644
index 0000000000000..d28bae5a9cead
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
@@ -0,0 +1,6116 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#                     bb.0.entry
+#                         |
+#                 bb.1.loop1.header<---------------------+
+#                         |                              |
+#                 bb.2.loop2.header<------------------+  |
+#                         |                           |  |
+#                 bb.3.loop3.header<---------------+  |  |
+#                       |   \                      |  |  |
+#                       |  bb.8.bb2                |  |  |
+#                       |   /                      |  |  |
+#                     bb.4.Flow                    |  |  |
+#                      /   |                       |  |  |
+#                bb.5.bb1  |                       |  |  |
+#                    |     |                       |  |  |
+#         +----->bb7.loop4 |                       |  |  |
+#         +----------+     |                       |  |  |
+#                    |     |                       |  |  |
+#        bb.9.bb3.loopexit |                       |  |  |
+#                    \     |                       |  |  |
+#                   bb.6.Flow4                     |  |  |
+#                       |                          |  |  |
+#                   bb.10.bb3                      |  |  |
+#                    /  |                          |  |  |
+#            bb.11.bb4  |                          |  |  |
+#                    \  |                          |  |  |
+#               bb.12.loop3.latch------------------+  |  |
+#                       |                             |  |
+#               bb.13.loop2.latch---------------------+  |
+#                       |                                |
+#               bb.14.loop1.latch------------------------+
+#                       |
+#                  bb.15.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test14 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr16
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 76 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 75 ]
+# CHECK: Vreg: %1[ 88 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 74 ]
+# CHECK: Vreg: %2[ 105 ]
+# CHECK: Vreg: %1[ 87 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 73 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %1[ 86 ]
+# CHECK: Vreg: %3[ 110 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 72 ]
+# CHECK: Vreg: %2[ 103 ]
+# CHECK: Vreg: %4[ 124 ]
+# CHECK: Vreg: %1[ 85 ]
+# CHECK: Vreg: %3[ 109 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %2[ 102 ]
+# CHECK: Vreg: %4[ 123 ]
+# CHECK: Vreg: %1[ 84 ]
+# CHECK: Vreg: %3[ 108 ]
+# CHECK: Vreg: %5[ 11 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 70 ]
+# CHECK: Vreg: %2[ 101 ]
+# CHECK: Vreg: %4[ 122 ]
+# CHECK: Vreg: %6[ 10 ]
+# CHECK: Vreg: %1[ 83 ]
+# CHECK: Vreg: %3[ 107 ]
+# CHECK: Vreg: %5[ 10 ]
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 69 ]
+# CHECK: Vreg: %7[ 10 ]
+# CHECK: Vreg: %2[ 100 ]
+# CHECK: Vreg: %4[ 121 ]
+# CHECK: Vreg: %6[ 9 ]
+# CHECK: Vreg: %1[ 82 ]
+# CHECK: Vreg: %3[ 106 ]
+# CHECK: Vreg: %5[ 9 ]
+# CHECK: Instr: %9:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 68 ]
+# CHECK: Vreg: %7[ 9 ]
+# CHECK: Vreg: %2[ 99 ]
+# CHECK: Vreg: %4[ 120 ]
+# CHECK: Vreg: %6[ 8 ]
+# CHECK: Vreg: %1[ 81 ]
+# CHECK: Vreg: %8[ 9 ]
+# CHECK: Vreg: %3[ 105 ]
+# CHECK: Vreg: %5[ 8 ]
+# CHECK: Instr: %10:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 67 ]
+# CHECK: Vreg: %7[ 8 ]
+# CHECK: Vreg: %2[ 98 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %4[ 119 ]
+# CHECK: Vreg: %6[ 7 ]
+# CHECK: Vreg: %1[ 80 ]
+# CHECK: Vreg: %8[ 8 ]
+# CHECK: Vreg: %3[ 104 ]
+# CHECK: Vreg: %5[ 7 ]
+# CHECK: Instr: %11:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 66 ]
+# CHECK: Vreg: %7[ 7 ]
+# CHECK: Vreg: %2[ 97 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %6[ 6 ]
+# CHECK: Vreg: %1[ 79 ]
+# CHECK: Vreg: %8[ 7 ]
+# CHECK: Vreg: %3[ 103 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %5[ 6 ]
+# CHECK: Instr: %12:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 65 ]
+# CHECK: Vreg: %7[ 6 ]
+# CHECK: Vreg: %2[ 96 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %4[ 117 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %6[ 5 ]
+# CHECK: Vreg: %1[ 78 ]
+# CHECK: Vreg: %8[ 6 ]
+# CHECK: Vreg: %3[ 102 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %5[ 5 ]
+# CHECK: Instr: %13:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 64 ]
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %2[ 95 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %4[ 116 ]
+# CHECK: Vreg: %11[ 7 ]
+# CHECK: Vreg: %6[ 4 ]
+# CHECK: Vreg: %1[ 77 ]
+# CHECK: Vreg: %8[ 5 ]
+# CHECK: Vreg: %3[ 101 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Vreg: %12[ 7 ]
+# CHECK: Instr: %14:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 63 ]
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %2[ 94 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %4[ 115 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %1[ 76 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: Vreg: %3[ 100 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Vreg: %12[ 6 ]
+# CHECK: Instr: %15:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 62 ]
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %2[ 93 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 114 ]
+# CHECK: Vreg: %11[ 5 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %13[ 6 ]
+# CHECK: Vreg: %1[ 75 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %3[ 99 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Vreg: %12[ 5 ]
+# CHECK: Instr: %16:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 61 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %14[ 5 ]
+# CHECK: Vreg: %2[ 92 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 113 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %13[ 5 ]
+# CHECK: Vreg: %1[ 74 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %3[ 98 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Vreg: %12[ 4 ]
+# CHECK: Instr: %17:vreg_64 = REG_SEQUENCE killed %6, %subreg.sub0, killed %5, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 60 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %14[ 4 ]
+# CHECK: Vreg: %2[ 91 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %16[ 5 ]
+# CHECK: Vreg: %4[ 112 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %1[ 73 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %3[ 97 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %12[ 3 ]
+# CHECK: Instr: %18:vreg_64 = REG_SEQUENCE killed %8, %subreg.sub0, killed %7, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 59 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %16[ 4 ]
+# CHECK: Vreg: %4[ 111 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %1[ 72 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %3[ 96 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %17[ 28 ]
+# CHECK: Vreg: %12[ 2 ]
+# CHECK: Instr: %19:vreg_64 = REG_SEQUENCE killed %10, %subreg.sub0, killed %9, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %2[ 89 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %16[ 3 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %18[ 63 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 71 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %3[ 95 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %17[ 27 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: %20:vreg_64 = REG_SEQUENCE killed %12, %subreg.sub0, killed %11, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 57 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %2[ 88 ]
+# CHECK: Vreg: %16[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %18[ 62 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 70 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %3[ 94 ]
+# CHECK: Vreg: %17[ 26 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Vreg: %19:sub0[ 104 ]
+# CHECK: Vreg: %19:sub1[ 105 ]
+# CHECK: Instr: %21:vreg_64 = REG_SEQUENCE killed %14, %subreg.sub0, killed %13, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 56 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %2[ 87 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %4[ 108 ]
+# CHECK: Vreg: %18[ 61 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %20:sub0[ 77 ]
+# CHECK: Vreg: %20:sub1[ 78 ]
+# CHECK: Vreg: %1[ 69 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %3[ 93 ]
+# CHECK: Vreg: %17[ 25 ]
+# CHECK: Vreg: %19:sub0[ 103 ]
+# CHECK: Vreg: %19:sub1[ 104 ]
+# CHECK: Instr: %22:vreg_64 = REG_SEQUENCE killed %16, %subreg.sub0, killed %15, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 55 ]
+# CHECK: Vreg: %21:sub0[ 14 ]
+# CHECK: Vreg: %21:sub1[ 15 ]
+# CHECK: Vreg: %2[ 86 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %18[ 60 ]
+# CHECK: Vreg: %20:sub0[ 76 ]
+# CHECK: Vreg: %20:sub1[ 77 ]
+# CHECK: Vreg: %1[ 68 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 92 ]
+# CHECK: Vreg: %17[ 24 ]
+# CHECK: Vreg: %19:sub0[ 102 ]
+# CHECK: Vreg: %19:sub1[ 103 ]
+# CHECK: Instr: %23:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 54 ]
+# CHECK: Vreg: %21:sub0[ 13 ]
+# CHECK: Vreg: %21:sub1[ 14 ]
+# CHECK: Vreg: %2[ 85 ]
+# CHECK: Vreg: %4[ 106 ]
+# CHECK: Vreg: %18[ 59 ]
+# CHECK: Vreg: %20:sub0[ 75 ]
+# CHECK: Vreg: %20:sub1[ 76 ]
+# CHECK: Vreg: %1[ 67 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 91 ]
+# CHECK: Vreg: %17[ 23 ]
+# CHECK: Vreg: %19:sub0[ 101 ]
+# CHECK: Vreg: %19:sub1[ 102 ]
+# CHECK: Instr: %24:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 53 ]
+# CHECK: Vreg: %21:sub0[ 12 ]
+# CHECK: Vreg: %21:sub1[ 13 ]
+# CHECK: Vreg: %2[ 84 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %4[ 105 ]
+# CHECK: Vreg: %18[ 58 ]
+# CHECK: Vreg: %20:sub0[ 74 ]
+# CHECK: Vreg: %20:sub1[ 75 ]
+# CHECK: Vreg: %1[ 66 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %17[ 22 ]
+# CHECK: Vreg: %19:sub0[ 100 ]
+# CHECK: Vreg: %19:sub1[ 101 ]
+# CHECK: Instr: %25:vgpr_32 = V_LSHL_OR_B32_e64 killed %24, 8, killed %23, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 52 ]
+# CHECK: Vreg: %21:sub0[ 11 ]
+# CHECK: Vreg: %21:sub1[ 12 ]
+# CHECK: Vreg: %2[ 83 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %4[ 104 ]
+# CHECK: Vreg: %18[ 57 ]
+# CHECK: Vreg: %20:sub0[ 73 ]
+# CHECK: Vreg: %20:sub1[ 74 ]
+# CHECK: Vreg: %1[ 65 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %3[ 89 ]
+# CHECK: Vreg: %17[ 21 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %19:sub0[ 99 ]
+# CHECK: Vreg: %19:sub1[ 100 ]
+# CHECK: Instr: %26:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 51 ]
+# CHECK: Vreg: %21:sub0[ 10 ]
+# CHECK: Vreg: %21:sub1[ 11 ]
+# CHECK: Vreg: %2[ 82 ]
+# CHECK: Vreg: %4[ 103 ]
+# CHECK: Vreg: %18[ 56 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %20:sub0[ 72 ]
+# CHECK: Vreg: %20:sub1[ 73 ]
+# CHECK: Vreg: %1[ 64 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 88 ]
+# CHECK: Vreg: %17[ 20 ]
+# CHECK: Vreg: %19:sub0[ 98 ]
+# CHECK: Vreg: %19:sub1[ 99 ]
+# CHECK: Instr: %27:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 50 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %21:sub0[ 9 ]
+# CHECK: Vreg: %21:sub1[ 10 ]
+# CHECK: Vreg: %2[ 81 ]
+# CHECK: Vreg: %4[ 102 ]
+# CHECK: Vreg: %18[ 55 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %20:sub0[ 71 ]
+# CHECK: Vreg: %20:sub1[ 72 ]
+# CHECK: Vreg: %1[ 63 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 87 ]
+# CHECK: Vreg: %17[ 19 ]
+# CHECK: Vreg: %19:sub0[ 97 ]
+# CHECK: Vreg: %19:sub1[ 98 ]
+# CHECK: Instr: %28:vgpr_32 = V_LSHL_OR_B32_e64 killed %27, 8, killed %26, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 49 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %21:sub0[ 8 ]
+# CHECK: Vreg: %21:sub1[ 9 ]
+# CHECK: Vreg: %2[ 80 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %18[ 54 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %20:sub0[ 70 ]
+# CHECK: Vreg: %20:sub1[ 71 ]
+# CHECK: Vreg: %1[ 62 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %22[ 98 ]
+# CHECK: Vreg: %3[ 86 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %19:sub0[ 96 ]
+# CHECK: Vreg: %19:sub1[ 97 ]
+# CHECK: Instr: %29:vgpr_32 = V_LSHL_OR_B32_e64 killed %28, 16, killed %25, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 48 ]
+# CHECK: Vreg: %21:sub0[ 7 ]
+# CHECK: Vreg: %21:sub1[ 8 ]
+# CHECK: Vreg: %2[ 79 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %4[ 100 ]
+# CHECK: Vreg: %18[ 53 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %20:sub0[ 69 ]
+# CHECK: Vreg: %20:sub1[ 70 ]
+# CHECK: Vreg: %1[ 61 ]
+# CHECK: Vreg: %22[ 97 ]
+# CHECK: Vreg: %3[ 85 ]
+# CHECK: Vreg: %17[ 17 ]
+# CHECK: Vreg: %19:sub0[ 95 ]
+# CHECK: Vreg: %19:sub1[ 96 ]
+# CHECK: Instr: %30:vgpr_32 = V_ADD_U32_e64 100, %29, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %21:sub0[ 6 ]
+# CHECK: Vreg: %21:sub1[ 7 ]
+# CHECK: Vreg: %2[ 78 ]
+# CHECK: Vreg: %4[ 99 ]
+# CHECK: Vreg: %18[ 52 ]
+# CHECK: Vreg: %20:sub0[ 68 ]
+# CHECK: Vreg: %20:sub1[ 69 ]
+# CHECK: Vreg: %1[ 60 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 84 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 16 ]
+# CHECK: Vreg: %19:sub0[ 94 ]
+# CHECK: Vreg: %19:sub1[ 95 ]
+# CHECK: Instr: %31:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %21:sub0[ 5 ]
+# CHECK: Vreg: %21:sub1[ 6 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %30[ 71 ]
+# CHECK: Vreg: %18[ 51 ]
+# CHECK: Vreg: %20:sub0[ 67 ]
+# CHECK: Vreg: %20:sub1[ 68 ]
+# CHECK: Vreg: %1[ 59 ]
+# CHECK: Vreg: %22[ 95 ]
+# CHECK: Vreg: %3[ 83 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17[ 15 ]
+# CHECK: Vreg: %19:sub0[ 93 ]
+# CHECK: Vreg: %19:sub1[ 94 ]
+# CHECK: Instr: %32:sreg_32 = S_MOV_B32 2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %21:sub0[ 4 ]
+# CHECK: Vreg: %21:sub1[ 5 ]
+# CHECK: Vreg: %2[ 76 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %18[ 50 ]
+# CHECK: Vreg: %20:sub0[ 66 ]
+# CHECK: Vreg: %20:sub1[ 67 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %22[ 94 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 92 ]
+# CHECK: Vreg: %19:sub1[ 93 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %21:sub0[ 4 ]
+# CHECK: Vreg: %21:sub1[ 5 ]
+# CHECK: Vreg: %2[ 76 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %18[ 50 ]
+# CHECK: Vreg: %32[ 24 ]
+# CHECK: Vreg: %20:sub0[ 66 ]
+# CHECK: Vreg: %20:sub1[ 67 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %22[ 94 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 92 ]
+# CHECK: Vreg: %19:sub1[ 93 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %33:sreg_32 = PHI %31, %bb.0, %34, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %21:sub0[ 4 ]
+# CHECK: Vreg: %21:sub1[ 5 ]
+# CHECK: Vreg: %2[ 76 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %18[ 50 ]
+# CHECK: Vreg: %32[ 24 ]
+# CHECK: Vreg: %20:sub0[ 66 ]
+# CHECK: Vreg: %20:sub1[ 67 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22[ 94 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19:sub0[ 92 ]
+# CHECK: Vreg: %19:sub1[ 93 ]
+# CHECK: Instr: %35:sreg_32 = PHI %31, %bb.0, %36, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %33[ 98 ]
+# CHECK: Vreg: %21:sub0[ 4 ]
+# CHECK: Vreg: %21:sub1[ 5 ]
+# CHECK: Vreg: %2[ 76 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %18[ 50 ]
+# CHECK: Vreg: %32[ 24 ]
+# CHECK: Vreg: %20:sub0[ 66 ]
+# CHECK: Vreg: %20:sub1[ 67 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %22[ 94 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19:sub0[ 92 ]
+# CHECK: Vreg: %19:sub1[ 93 ]
+# CHECK: Instr: %37:vgpr_32 = PHI %29, %bb.0, %38, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %33[ 98 ]
+# CHECK: Vreg: %21:sub0[ 4 ]
+# CHECK: Vreg: %21:sub1[ 5 ]
+# CHECK: Vreg: %2[ 76 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %18[ 50 ]
+# CHECK: Vreg: %32[ 24 ]
+# CHECK: Vreg: %20:sub0[ 66 ]
+# CHECK: Vreg: %20:sub1[ 67 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %22[ 94 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %31[ 24 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19:sub0[ 92 ]
+# CHECK: Vreg: %19:sub1[ 93 ]
+# CHECK: Instr: %39:sreg_32_xm0 = S_ASHR_I32 %35, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 44 ]
+# CHECK: Vreg: %33[ 97 ]
+# CHECK: Vreg: %21:sub0[ 3 ]
+# CHECK: Vreg: %21:sub1[ 4 ]
+# CHECK: Vreg: %2[ 75 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %4[ 96 ]
+# CHECK: Vreg: %30[ 69 ]
+# CHECK: Vreg: %37[ 13 ]
+# CHECK: Vreg: %18[ 49 ]
+# CHECK: Vreg: %32[ 23 ]
+# CHECK: Vreg: %20:sub0[ 65 ]
+# CHECK: Vreg: %20:sub1[ 66 ]
+# CHECK: Vreg: %1[ 57 ]
+# CHECK: Vreg: %22[ 93 ]
+# CHECK: Vreg: %3[ 81 ]
+# CHECK: Vreg: %29[ 23 ]
+# CHECK: Vreg: %17[ 13 ]
+# CHECK: Vreg: %31[ 23 ]
+# CHECK: Vreg: %19:sub0[ 91 ]
+# CHECK: Vreg: %19:sub1[ 92 ]
+# CHECK: Instr: %40:sreg_64 = REG_SEQUENCE %35, %subreg.sub0, killed %39, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Vreg: %33[ 96 ]
+# CHECK: Vreg: %21:sub0[ 2 ]
+# CHECK: Vreg: %21:sub1[ 3 ]
+# CHECK: Vreg: %2[ 74 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %4[ 95 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 12 ]
+# CHECK: Vreg: %18[ 48 ]
+# CHECK: Vreg: %32[ 22 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20:sub0[ 64 ]
+# CHECK: Vreg: %20:sub1[ 65 ]
+# CHECK: Vreg: %1[ 56 ]
+# CHECK: Vreg: %22[ 92 ]
+# CHECK: Vreg: %3[ 80 ]
+# CHECK: Vreg: %29[ 22 ]
+# CHECK: Vreg: %17[ 12 ]
+# CHECK: Vreg: %31[ 22 ]
+# CHECK: Vreg: %19:sub0[ 90 ]
+# CHECK: Vreg: %19:sub1[ 91 ]
+# CHECK: Instr: %41:sreg_64 = nsw S_LSHL_B64 killed %40, 3, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 42 ]
+# CHECK: Vreg: %33[ 95 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21:sub0[ 1 ]
+# CHECK: Vreg: %21:sub1[ 2 ]
+# CHECK: Vreg: %2[ 73 ]
+# CHECK: Vreg: %35[ 12 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %30[ 67 ]
+# CHECK: Vreg: %37[ 11 ]
+# CHECK: Vreg: %18[ 47 ]
+# CHECK: Vreg: %32[ 21 ]
+# CHECK: Vreg: %20:sub0[ 63 ]
+# CHECK: Vreg: %20:sub1[ 64 ]
+# CHECK: Vreg: %1[ 55 ]
+# CHECK: Vreg: %22[ 91 ]
+# CHECK: Vreg: %3[ 79 ]
+# CHECK: Vreg: %29[ 21 ]
+# CHECK: Vreg: %17[ 11 ]
+# CHECK: Vreg: %31[ 21 ]
+# CHECK: Vreg: %19:sub0[ 89 ]
+# CHECK: Vreg: %19:sub1[ 90 ]
+# CHECK: Instr: %42:vgpr_32, %43:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %21.sub0, %41.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %33[ 94 ]
+# CHECK: Vreg: %21:sub0[ 0 ]
+# CHECK: Vreg: %21:sub1[ 1 ]
+# CHECK: Vreg: %2[ 72 ]
+# CHECK: Vreg: %35[ 11 ]
+# CHECK: Vreg: %4[ 93 ]
+# CHECK: Vreg: %30[ 66 ]
+# CHECK: Vreg: %37[ 10 ]
+# CHECK: Vreg: %18[ 46 ]
+# CHECK: Vreg: %32[ 20 ]
+# CHECK: Vreg: %20:sub0[ 62 ]
+# CHECK: Vreg: %20:sub1[ 63 ]
+# CHECK: Vreg: %1[ 54 ]
+# CHECK: Vreg: %41:sub0[ 0 ]
+# CHECK: Vreg: %41:sub1[ 1 ]
+# CHECK: Vreg: %22[ 90 ]
+# CHECK: Vreg: %3[ 78 ]
+# CHECK: Vreg: %29[ 20 ]
+# CHECK: Vreg: %17[ 10 ]
+# CHECK: Vreg: %31[ 20 ]
+# CHECK: Vreg: %19:sub0[ 88 ]
+# CHECK: Vreg: %19:sub1[ 89 ]
+# CHECK: Instr: %44:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %41.sub1, %21.sub1, killed %43, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %33[ 93 ]
+# CHECK: Vreg: %21:sub1[ 0 ]
+# CHECK: Vreg: %21:sub0[ 24 ]
+# CHECK: Vreg: %2[ 71 ]
+# CHECK: Vreg: %35[ 10 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %4[ 92 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 45 ]
+# CHECK: Vreg: %32[ 19 ]
+# CHECK: Vreg: %20:sub0[ 61 ]
+# CHECK: Vreg: %20:sub1[ 62 ]
+# CHECK: Vreg: %1[ 53 ]
+# CHECK: Vreg: %41:sub1[ 0 ]
+# CHECK: Vreg: %22[ 89 ]
+# CHECK: Vreg: %3[ 77 ]
+# CHECK: Vreg: %29[ 19 ]
+# CHECK: Vreg: %17[ 9 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ 19 ]
+# CHECK: Vreg: %19:sub0[ 87 ]
+# CHECK: Vreg: %19:sub1[ 88 ]
+# CHECK: Instr: %45:vreg_64 = REG_SEQUENCE killed %42, %subreg.sub0, killed %44, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 39 ]
+# CHECK: Vreg: %33[ 92 ]
+# CHECK: Vreg: %21:sub0[ 23 ]
+# CHECK: Vreg: %21:sub1[ 24 ]
+# CHECK: Vreg: %2[ 70 ]
+# CHECK: Vreg: %35[ 9 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 64 ]
+# CHECK: Vreg: %37[ 8 ]
+# CHECK: Vreg: %18[ 44 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %32[ 18 ]
+# CHECK: Vreg: %20:sub0[ 60 ]
+# CHECK: Vreg: %20:sub1[ 61 ]
+# CHECK: Vreg: %1[ 52 ]
+# CHECK: Vreg: %22[ 88 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %29[ 18 ]
+# CHECK: Vreg: %17[ 8 ]
+# CHECK: Vreg: %31[ 18 ]
+# CHECK: Vreg: %19:sub0[ 86 ]
+# CHECK: Vreg: %19:sub1[ 87 ]
+# CHECK: Instr: %46:vgpr_32 = GLOBAL_LOAD_UBYTE %45, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 38 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %33[ 91 ]
+# CHECK: Vreg: %21:sub0[ 22 ]
+# CHECK: Vreg: %21:sub1[ 23 ]
+# CHECK: Vreg: %2[ 69 ]
+# CHECK: Vreg: %35[ 8 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %30[ 63 ]
+# CHECK: Vreg: %37[ 7 ]
+# CHECK: Vreg: %18[ 43 ]
+# CHECK: Vreg: %32[ 17 ]
+# CHECK: Vreg: %20:sub0[ 59 ]
+# CHECK: Vreg: %20:sub1[ 60 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %22[ 87 ]
+# CHECK: Vreg: %3[ 75 ]
+# CHECK: Vreg: %29[ 17 ]
+# CHECK: Vreg: %17[ 7 ]
+# CHECK: Vreg: %31[ 17 ]
+# CHECK: Vreg: %19:sub0[ 85 ]
+# CHECK: Vreg: %19:sub1[ 86 ]
+# CHECK: Instr: %47:vgpr_32 = GLOBAL_LOAD_UBYTE %45, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %33[ 90 ]
+# CHECK: Vreg: %21:sub0[ 21 ]
+# CHECK: Vreg: %21:sub1[ 22 ]
+# CHECK: Vreg: %2[ 68 ]
+# CHECK: Vreg: %35[ 7 ]
+# CHECK: Vreg: %4[ 89 ]
+# CHECK: Vreg: %30[ 62 ]
+# CHECK: Vreg: %37[ 6 ]
+# CHECK: Vreg: %18[ 42 ]
+# CHECK: Vreg: %32[ 16 ]
+# CHECK: Vreg: %20:sub0[ 58 ]
+# CHECK: Vreg: %20:sub1[ 59 ]
+# CHECK: Vreg: %1[ 50 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %22[ 86 ]
+# CHECK: Vreg: %3[ 74 ]
+# CHECK: Vreg: %29[ 16 ]
+# CHECK: Vreg: %17[ 6 ]
+# CHECK: Vreg: %31[ 16 ]
+# CHECK: Vreg: %19:sub0[ 84 ]
+# CHECK: Vreg: %19:sub1[ 85 ]
+# CHECK: Instr: %48:vgpr_32 = V_LSHL_OR_B32_e64 killed %47, 8, killed %46, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %33[ 89 ]
+# CHECK: Vreg: %21:sub0[ 20 ]
+# CHECK: Vreg: %21:sub1[ 21 ]
+# CHECK: Vreg: %2[ 67 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %35[ 6 ]
+# CHECK: Vreg: %4[ 88 ]
+# CHECK: Vreg: %30[ 61 ]
+# CHECK: Vreg: %37[ 5 ]
+# CHECK: Vreg: %18[ 41 ]
+# CHECK: Vreg: %32[ 15 ]
+# CHECK: Vreg: %20:sub0[ 57 ]
+# CHECK: Vreg: %20:sub1[ 58 ]
+# CHECK: Vreg: %1[ 49 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %22[ 85 ]
+# CHECK: Vreg: %3[ 73 ]
+# CHECK: Vreg: %29[ 15 ]
+# CHECK: Vreg: %17[ 5 ]
+# CHECK: Vreg: %31[ 15 ]
+# CHECK: Vreg: %19:sub0[ 83 ]
+# CHECK: Vreg: %19:sub1[ 84 ]
+# CHECK: Instr: %49:vgpr_32 = GLOBAL_LOAD_UBYTE %45, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %33[ 88 ]
+# CHECK: Vreg: %21:sub0[ 19 ]
+# CHECK: Vreg: %21:sub1[ 20 ]
+# CHECK: Vreg: %2[ 66 ]
+# CHECK: Vreg: %35[ 5 ]
+# CHECK: Vreg: %4[ 87 ]
+# CHECK: Vreg: %30[ 60 ]
+# CHECK: Vreg: %37[ 4 ]
+# CHECK: Vreg: %18[ 40 ]
+# CHECK: Vreg: %32[ 14 ]
+# CHECK: Vreg: %20:sub0[ 56 ]
+# CHECK: Vreg: %20:sub1[ 57 ]
+# CHECK: Vreg: %1[ 48 ]
+# CHECK: Vreg: %22[ 84 ]
+# CHECK: Vreg: %3[ 72 ]
+# CHECK: Vreg: %48[ 3 ]
+# CHECK: Vreg: %29[ 14 ]
+# CHECK: Vreg: %17[ 4 ]
+# CHECK: Vreg: %31[ 14 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Instr: %50:vgpr_32 = GLOBAL_LOAD_UBYTE killed %45, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %33[ 87 ]
+# CHECK: Vreg: %21:sub0[ 18 ]
+# CHECK: Vreg: %21:sub1[ 19 ]
+# CHECK: Vreg: %2[ 65 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %4[ 86 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %30[ 59 ]
+# CHECK: Vreg: %37[ 3 ]
+# CHECK: Vreg: %18[ 39 ]
+# CHECK: Vreg: %32[ 13 ]
+# CHECK: Vreg: %20:sub0[ 55 ]
+# CHECK: Vreg: %20:sub1[ 56 ]
+# CHECK: Vreg: %1[ 47 ]
+# CHECK: Vreg: %22[ 83 ]
+# CHECK: Vreg: %3[ 71 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %29[ 13 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Vreg: %31[ 13 ]
+# CHECK: Vreg: %19:sub0[ 81 ]
+# CHECK: Vreg: %19:sub1[ 82 ]
+# CHECK: Instr: %51:vgpr_32 = V_LSHL_OR_B32_e64 killed %50, 8, killed %49, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %33[ 86 ]
+# CHECK: Vreg: %21:sub0[ 17 ]
+# CHECK: Vreg: %21:sub1[ 18 ]
+# CHECK: Vreg: %2[ 64 ]
+# CHECK: Vreg: %35[ 3 ]
+# CHECK: Vreg: %4[ 85 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %30[ 58 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %18[ 38 ]
+# CHECK: Vreg: %32[ 12 ]
+# CHECK: Vreg: %20:sub0[ 54 ]
+# CHECK: Vreg: %20:sub1[ 55 ]
+# CHECK: Vreg: %1[ 46 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 70 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %29[ 12 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %31[ 12 ]
+# CHECK: Vreg: %19:sub0[ 80 ]
+# CHECK: Vreg: %19:sub1[ 81 ]
+# CHECK: Instr: %52:vgpr_32 = V_LSHL_OR_B32_e64 killed %51, 16, killed %48, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %33[ 85 ]
+# CHECK: Vreg: %21:sub0[ 16 ]
+# CHECK: Vreg: %21:sub1[ 17 ]
+# CHECK: Vreg: %2[ 63 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %4[ 84 ]
+# CHECK: Vreg: %30[ 57 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %18[ 37 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %32[ 11 ]
+# CHECK: Vreg: %20:sub0[ 53 ]
+# CHECK: Vreg: %20:sub1[ 54 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %22[ 81 ]
+# CHECK: Vreg: %3[ 69 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %29[ 11 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %31[ 11 ]
+# CHECK: Vreg: %19:sub0[ 79 ]
+# CHECK: Vreg: %19:sub1[ 80 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %17, killed %37, 0, 0, implicit $exec :: (store (s32) into %ir.p6, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %52[ 74 ]
+# CHECK: Vreg: %33[ 84 ]
+# CHECK: Vreg: %21:sub0[ 15 ]
+# CHECK: Vreg: %21:sub1[ 16 ]
+# CHECK: Vreg: %2[ 62 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %4[ 83 ]
+# CHECK: Vreg: %30[ 56 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %18[ 36 ]
+# CHECK: Vreg: %32[ 10 ]
+# CHECK: Vreg: %20:sub0[ 52 ]
+# CHECK: Vreg: %20:sub1[ 53 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %22[ 80 ]
+# CHECK: Vreg: %3[ 68 ]
+# CHECK: Vreg: %29[ 10 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %31[ 10 ]
+# CHECK: Vreg: %19:sub0[ 78 ]
+# CHECK: Vreg: %19:sub1[ 79 ]
+# CHECK: Instr: %53:sgpr_32 = S_CVT_F32_U32 %35, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %52[ 73 ]
+# CHECK: Vreg: %33[ 83 ]
+# CHECK: Vreg: %21:sub0[ 14 ]
+# CHECK: Vreg: %21:sub1[ 15 ]
+# CHECK: Vreg: %2[ 61 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %4[ 82 ]
+# CHECK: Vreg: %30[ 55 ]
+# CHECK: Vreg: %18[ 35 ]
+# CHECK: Vreg: %32[ 9 ]
+# CHECK: Vreg: %20:sub0[ 51 ]
+# CHECK: Vreg: %20:sub1[ 52 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %22[ 79 ]
+# CHECK: Vreg: %3[ 67 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %17[ 99 ]
+# CHECK: Vreg: %31[ 9 ]
+# CHECK: Vreg: %19:sub0[ 77 ]
+# CHECK: Vreg: %19:sub1[ 78 ]
+# CHECK: Instr: %54:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %53, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %52[ 72 ]
+# CHECK: Vreg: %33[ 82 ]
+# CHECK: Vreg: %21:sub0[ 13 ]
+# CHECK: Vreg: %21:sub1[ 14 ]
+# CHECK: Vreg: %2[ 60 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %4[ 81 ]
+# CHECK: Vreg: %30[ 54 ]
+# CHECK: Vreg: %18[ 34 ]
+# CHECK: Vreg: %32[ 8 ]
+# CHECK: Vreg: %20:sub0[ 50 ]
+# CHECK: Vreg: %20:sub1[ 51 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %22[ 78 ]
+# CHECK: Vreg: %3[ 66 ]
+# CHECK: Vreg: %29[ 8 ]
+# CHECK: Vreg: %17[ 98 ]
+# CHECK: Vreg: %31[ 8 ]
+# CHECK: Vreg: %19:sub0[ 76 ]
+# CHECK: Vreg: %19:sub1[ 77 ]
+# CHECK: Instr: %55:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %54, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %52[ 71 ]
+# CHECK: Vreg: %33[ 81 ]
+# CHECK: Vreg: %21:sub0[ 12 ]
+# CHECK: Vreg: %21:sub1[ 13 ]
+# CHECK: Vreg: %2[ 59 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %35[ 3 ]
+# CHECK: Vreg: %4[ 80 ]
+# CHECK: Vreg: %30[ 53 ]
+# CHECK: Vreg: %18[ 33 ]
+# CHECK: Vreg: %32[ 7 ]
+# CHECK: Vreg: %20:sub0[ 49 ]
+# CHECK: Vreg: %20:sub1[ 50 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %22[ 77 ]
+# CHECK: Vreg: %3[ 65 ]
+# CHECK: Vreg: %29[ 7 ]
+# CHECK: Vreg: %17[ 97 ]
+# CHECK: Vreg: %31[ 7 ]
+# CHECK: Vreg: %19:sub0[ 75 ]
+# CHECK: Vreg: %19:sub1[ 76 ]
+# CHECK: Instr: %56:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %55, 1333788670, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %52[ 70 ]
+# CHECK: Vreg: %33[ 80 ]
+# CHECK: Vreg: %21:sub0[ 11 ]
+# CHECK: Vreg: %21:sub1[ 12 ]
+# CHECK: Vreg: %2[ 58 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %4[ 79 ]
+# CHECK: Vreg: %30[ 52 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %32[ 6 ]
+# CHECK: Vreg: %20:sub0[ 48 ]
+# CHECK: Vreg: %20:sub1[ 49 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %22[ 76 ]
+# CHECK: Vreg: %3[ 64 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %17[ 96 ]
+# CHECK: Vreg: %31[ 6 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: %57:sreg_32 = nofpexcept S_CVT_U32_F32 killed %56, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %52[ 69 ]
+# CHECK: Vreg: %33[ 79 ]
+# CHECK: Vreg: %21:sub0[ 10 ]
+# CHECK: Vreg: %21:sub1[ 11 ]
+# CHECK: Vreg: %2[ 57 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %4[ 78 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %18[ 31 ]
+# CHECK: Vreg: %32[ 5 ]
+# CHECK: Vreg: %20:sub0[ 47 ]
+# CHECK: Vreg: %20:sub1[ 48 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %22[ 75 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %17[ 95 ]
+# CHECK: Vreg: %31[ 5 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Instr: %58:sreg_32 = S_SUB_I32 0, %35, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %52[ 68 ]
+# CHECK: Vreg: %33[ 78 ]
+# CHECK: Vreg: %21:sub0[ 9 ]
+# CHECK: Vreg: %21:sub1[ 10 ]
+# CHECK: Vreg: %2[ 56 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 50 ]
+# CHECK: Vreg: %18[ 30 ]
+# CHECK: Vreg: %32[ 4 ]
+# CHECK: Vreg: %20:sub0[ 46 ]
+# CHECK: Vreg: %20:sub1[ 47 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %22[ 74 ]
+# CHECK: Vreg: %3[ 62 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %17[ 94 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %57[ 1 ]
+# CHECK: Vreg: %19:sub0[ 72 ]
+# CHECK: Vreg: %19:sub1[ 73 ]
+# CHECK: Instr: %59:sreg_32 = S_MUL_I32 killed %58, %57
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %52[ 67 ]
+# CHECK: Vreg: %33[ 77 ]
+# CHECK: Vreg: %21:sub0[ 8 ]
+# CHECK: Vreg: %21:sub1[ 9 ]
+# CHECK: Vreg: %2[ 55 ]
+# CHECK: Vreg: %35[ 27 ]
+# CHECK: Vreg: %4[ 76 ]
+# CHECK: Vreg: %30[ 49 ]
+# CHECK: Vreg: %18[ 29 ]
+# CHECK: Vreg: %32[ 3 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20:sub0[ 45 ]
+# CHECK: Vreg: %20:sub1[ 46 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %22[ 73 ]
+# CHECK: Vreg: %3[ 61 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %17[ 93 ]
+# CHECK: Vreg: %31[ 3 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Instr: %60:sreg_32 = S_MUL_HI_U32 %57, killed %59
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %52[ 66 ]
+# CHECK: Vreg: %33[ 76 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %21:sub0[ 7 ]
+# CHECK: Vreg: %21:sub1[ 8 ]
+# CHECK: Vreg: %2[ 54 ]
+# CHECK: Vreg: %35[ 26 ]
+# CHECK: Vreg: %4[ 75 ]
+# CHECK: Vreg: %30[ 48 ]
+# CHECK: Vreg: %18[ 28 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %20:sub0[ 44 ]
+# CHECK: Vreg: %20:sub1[ 45 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %22[ 72 ]
+# CHECK: Vreg: %3[ 60 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %17[ 92 ]
+# CHECK: Vreg: %31[ 2 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 70 ]
+# CHECK: Vreg: %19:sub1[ 71 ]
+# CHECK: Instr: %61:sreg_32 = S_ADD_I32 killed %57, killed %60, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %52[ 65 ]
+# CHECK: Vreg: %33[ 75 ]
+# CHECK: Vreg: %21:sub0[ 6 ]
+# CHECK: Vreg: %21:sub1[ 7 ]
+# CHECK: Vreg: %2[ 53 ]
+# CHECK: Vreg: %35[ 25 ]
+# CHECK: Vreg: %4[ 74 ]
+# CHECK: Vreg: %30[ 47 ]
+# CHECK: Vreg: %18[ 27 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %20:sub0[ 43 ]
+# CHECK: Vreg: %20:sub1[ 44 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22[ 71 ]
+# CHECK: Vreg: %3[ 59 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17[ 91 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 69 ]
+# CHECK: Vreg: %19:sub1[ 70 ]
+# CHECK: Instr: %62:sreg_64 = REG_SEQUENCE killed %61, %subreg.sub0, undef %31, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %52[ 64 ]
+# CHECK: Vreg: %33[ 74 ]
+# CHECK: Vreg: %21:sub0[ 5 ]
+# CHECK: Vreg: %21:sub1[ 6 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %35[ 24 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %30[ 46 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20:sub0[ 42 ]
+# CHECK: Vreg: %20:sub1[ 43 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %22[ 70 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 90 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 68 ]
+# CHECK: Vreg: %19:sub1[ 69 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %52[ 64 ]
+# CHECK: Vreg: %33[ 74 ]
+# CHECK: Vreg: %21:sub0[ 5 ]
+# CHECK: Vreg: %21:sub1[ 6 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %35[ 24 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %30[ 46 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20:sub0[ 42 ]
+# CHECK: Vreg: %20:sub1[ 43 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %22[ 70 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 90 ]
+# CHECK: Vreg: %62:sub0[ 50 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 68 ]
+# CHECK: Vreg: %19:sub1[ 69 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %63:sreg_32 = PHI %31, %bb.1, %64, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %52[ LoopTag+64 ]
+# CHECK: Vreg: %33[ LoopTag+74 ]
+# CHECK: Vreg: %21:sub0[ 5 ]
+# CHECK: Vreg: %21:sub1[ 6 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %35[ 24 ]
+# CHECK: Vreg: %4[ LoopTag+73 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %30[ 46 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20:sub0[ 42 ]
+# CHECK: Vreg: %20:sub1[ 43 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %22[ 70 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+90 ]
+# CHECK: Vreg: %62:sub0[ 50 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+68 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+69 ]
+# CHECK: Instr: %65:sreg_32 = PHI %32, %bb.1, %66, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %52[ LoopTag+64 ]
+# CHECK: Vreg: %33[ LoopTag+74 ]
+# CHECK: Vreg: %21:sub0[ 5 ]
+# CHECK: Vreg: %21:sub1[ 6 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %35[ 24 ]
+# CHECK: Vreg: %4[ LoopTag+73 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %30[ 46 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %63[ 59 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20:sub0[ 42 ]
+# CHECK: Vreg: %20:sub1[ 43 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %22[ 70 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+90 ]
+# CHECK: Vreg: %62:sub0[ 50 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+68 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+69 ]
+# CHECK: Instr: %67:vgpr_32 = PHI %29, %bb.1, %68, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %52[ LoopTag+64 ]
+# CHECK: Vreg: %33[ LoopTag+74 ]
+# CHECK: Vreg: %21:sub0[ 5 ]
+# CHECK: Vreg: %21:sub1[ 6 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %35[ 24 ]
+# CHECK: Vreg: %4[ LoopTag+73 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %30[ 46 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %63[ 59 ]
+# CHECK: Vreg: %32[ LoopTag+100 ]
+# CHECK: Vreg: %20:sub0[ 42 ]
+# CHECK: Vreg: %20:sub1[ 43 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %22[ 70 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+90 ]
+# CHECK: Vreg: %62:sub0[ 50 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+68 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+69 ]
+# CHECK: Instr: %69:vgpr_32 = V_MUL_LO_U32_e64 killed %67, %65, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %52[ LoopTag+63 ]
+# CHECK: Vreg: %33[ LoopTag+73 ]
+# CHECK: Vreg: %21:sub0[ 4 ]
+# CHECK: Vreg: %21:sub1[ 5 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %35[ 23 ]
+# CHECK: Vreg: %4[ LoopTag+72 ]
+# CHECK: Vreg: %30[ 45 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %63[ 58 ]
+# CHECK: Vreg: %32[ LoopTag+99 ]
+# CHECK: Vreg: %20:sub0[ 41 ]
+# CHECK: Vreg: %20:sub1[ 42 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 57 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+89 ]
+# CHECK: Vreg: %62:sub0[ 49 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+67 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+68 ]
+# CHECK: Instr: %70:sreg_32_xm0 = S_ASHR_I32 %65, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %52[ LoopTag+62 ]
+# CHECK: Vreg: %33[ LoopTag+72 ]
+# CHECK: Vreg: %21:sub0[ 3 ]
+# CHECK: Vreg: %21:sub1[ 4 ]
+# CHECK: Vreg: %2[ 50 ]
+# CHECK: Vreg: %35[ 22 ]
+# CHECK: Vreg: %4[ LoopTag+71 ]
+# CHECK: Vreg: %30[ 44 ]
+# CHECK: Vreg: %18[ 24 ]
+# CHECK: Vreg: %63[ 57 ]
+# CHECK: Vreg: %32[ LoopTag+98 ]
+# CHECK: Vreg: %20:sub0[ 40 ]
+# CHECK: Vreg: %20:sub1[ 41 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22[ 68 ]
+# CHECK: Vreg: %3[ 56 ]
+# CHECK: Vreg: %17[ LoopTag+88 ]
+# CHECK: Vreg: %62:sub0[ 48 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+66 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+67 ]
+# CHECK: Instr: %71:sreg_64 = REG_SEQUENCE %65, %subreg.sub0, killed %70, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %52[ LoopTag+61 ]
+# CHECK: Vreg: %33[ LoopTag+71 ]
+# CHECK: Vreg: %21:sub0[ 2 ]
+# CHECK: Vreg: %21:sub1[ 3 ]
+# CHECK: Vreg: %2[ 49 ]
+# CHECK: Vreg: %35[ 21 ]
+# CHECK: Vreg: %4[ LoopTag+70 ]
+# CHECK: Vreg: %30[ 43 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %63[ 56 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+97 ]
+# CHECK: Vreg: %20:sub0[ 39 ]
+# CHECK: Vreg: %20:sub1[ 40 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22[ 67 ]
+# CHECK: Vreg: %3[ 55 ]
+# CHECK: Vreg: %17[ LoopTag+87 ]
+# CHECK: Vreg: %62:sub0[ 47 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+65 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+66 ]
+# CHECK: Instr: %72:sreg_64 = nsw S_LSHL_B64 killed %71, 3, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %52[ LoopTag+60 ]
+# CHECK: Vreg: %33[ LoopTag+70 ]
+# CHECK: Vreg: %21:sub0[ 1 ]
+# CHECK: Vreg: %21:sub1[ 2 ]
+# CHECK: Vreg: %2[ 48 ]
+# CHECK: Vreg: %35[ 20 ]
+# CHECK: Vreg: %4[ LoopTag+69 ]
+# CHECK: Vreg: %30[ 42 ]
+# CHECK: Vreg: %18[ 22 ]
+# CHECK: Vreg: %63[ 55 ]
+# CHECK: Vreg: %32[ LoopTag+96 ]
+# CHECK: Vreg: %20:sub0[ 38 ]
+# CHECK: Vreg: %20:sub1[ 39 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %22[ 66 ]
+# CHECK: Vreg: %3[ 54 ]
+# CHECK: Vreg: %17[ LoopTag+86 ]
+# CHECK: Vreg: %62:sub0[ 46 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+64 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+65 ]
+# CHECK: Instr: %73:vgpr_32, %74:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %21.sub0, %72.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %52[ LoopTag+59 ]
+# CHECK: Vreg: %33[ LoopTag+69 ]
+# CHECK: Vreg: %21:sub0[ 0 ]
+# CHECK: Vreg: %21:sub1[ 1 ]
+# CHECK: Vreg: %2[ 47 ]
+# CHECK: Vreg: %35[ 19 ]
+# CHECK: Vreg: %4[ LoopTag+68 ]
+# CHECK: Vreg: %30[ 41 ]
+# CHECK: Vreg: %18[ 21 ]
+# CHECK: Vreg: %63[ 54 ]
+# CHECK: Vreg: %32[ LoopTag+95 ]
+# CHECK: Vreg: %20:sub0[ 37 ]
+# CHECK: Vreg: %20:sub1[ 38 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %72:sub0[ 0 ]
+# CHECK: Vreg: %72:sub1[ 1 ]
+# CHECK: Vreg: %22[ 65 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %17[ LoopTag+85 ]
+# CHECK: Vreg: %62:sub0[ 45 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+63 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+64 ]
+# CHECK: Instr: %75:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %72.sub1, %21.sub1, killed %74, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %52[ LoopTag+58 ]
+# CHECK: Vreg: %33[ LoopTag+68 ]
+# CHECK: Vreg: %21:sub1[ 0 ]
+# CHECK: Vreg: %21:sub0[ 60 ]
+# CHECK: Vreg: %2[ 46 ]
+# CHECK: Vreg: %73[ 1 ]
+# CHECK: Vreg: %35[ 18 ]
+# CHECK: Vreg: %4[ LoopTag+67 ]
+# CHECK: Vreg: %30[ 40 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ 53 ]
+# CHECK: Vreg: %32[ LoopTag+94 ]
+# CHECK: Vreg: %20:sub0[ 36 ]
+# CHECK: Vreg: %20:sub1[ 37 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %72:sub1[ 0 ]
+# CHECK: Vreg: %22[ 64 ]
+# CHECK: Vreg: %3[ 52 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+84 ]
+# CHECK: Vreg: %62:sub0[ 44 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+62 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+63 ]
+# CHECK: Instr: %76:vreg_64 = REG_SEQUENCE killed %73, %subreg.sub0, killed %75, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %52[ LoopTag+57 ]
+# CHECK: Vreg: %33[ LoopTag+67 ]
+# CHECK: Vreg: %21:sub0[ 59 ]
+# CHECK: Vreg: %21:sub1[ 60 ]
+# CHECK: Vreg: %2[ 45 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %35[ 17 ]
+# CHECK: Vreg: %4[ LoopTag+66 ]
+# CHECK: Vreg: %30[ 39 ]
+# CHECK: Vreg: %75[ 0 ]
+# CHECK: Vreg: %18[ 19 ]
+# CHECK: Vreg: %63[ 52 ]
+# CHECK: Vreg: %32[ LoopTag+93 ]
+# CHECK: Vreg: %20:sub0[ 35 ]
+# CHECK: Vreg: %20:sub1[ 36 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %22[ 63 ]
+# CHECK: Vreg: %3[ 51 ]
+# CHECK: Vreg: %17[ LoopTag+83 ]
+# CHECK: Vreg: %62:sub0[ 43 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+61 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+62 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %76, %69, 0, 0, implicit $exec :: (store (s32) into %ir.gep2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %52[ LoopTag+56 ]
+# CHECK: Vreg: %33[ LoopTag+66 ]
+# CHECK: Vreg: %21:sub0[ 58 ]
+# CHECK: Vreg: %21:sub1[ 59 ]
+# CHECK: Vreg: %2[ 44 ]
+# CHECK: Vreg: %35[ 16 ]
+# CHECK: Vreg: %4[ LoopTag+65 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %18[ 18 ]
+# CHECK: Vreg: %63[ 51 ]
+# CHECK: Vreg: %32[ LoopTag+92 ]
+# CHECK: Vreg: %20:sub0[ 34 ]
+# CHECK: Vreg: %20:sub1[ 35 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %22[ 62 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %17[ LoopTag+82 ]
+# CHECK: Vreg: %62:sub0[ 42 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+60 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+61 ]
+# CHECK: Instr: %77:sgpr_32 = S_CVT_F32_U32 %65, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %52[ LoopTag+55 ]
+# CHECK: Vreg: %33[ LoopTag+65 ]
+# CHECK: Vreg: %21:sub0[ 57 ]
+# CHECK: Vreg: %21:sub1[ 58 ]
+# CHECK: Vreg: %2[ 43 ]
+# CHECK: Vreg: %35[ 15 ]
+# CHECK: Vreg: %4[ LoopTag+64 ]
+# CHECK: Vreg: %30[ 37 ]
+# CHECK: Vreg: %18[ 17 ]
+# CHECK: Vreg: %63[ 50 ]
+# CHECK: Vreg: %32[ LoopTag+91 ]
+# CHECK: Vreg: %20:sub0[ 33 ]
+# CHECK: Vreg: %20:sub1[ 34 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22[ 61 ]
+# CHECK: Vreg: %3[ 49 ]
+# CHECK: Vreg: %17[ LoopTag+81 ]
+# CHECK: Vreg: %62:sub0[ 41 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+60 ]
+# CHECK: Instr: %78:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %77, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %52[ LoopTag+54 ]
+# CHECK: Vreg: %33[ LoopTag+64 ]
+# CHECK: Vreg: %21:sub0[ 56 ]
+# CHECK: Vreg: %21:sub1[ 57 ]
+# CHECK: Vreg: %2[ 42 ]
+# CHECK: Vreg: %35[ 14 ]
+# CHECK: Vreg: %4[ LoopTag+63 ]
+# CHECK: Vreg: %30[ 36 ]
+# CHECK: Vreg: %18[ 16 ]
+# CHECK: Vreg: %63[ 49 ]
+# CHECK: Vreg: %32[ LoopTag+90 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %20:sub0[ 32 ]
+# CHECK: Vreg: %20:sub1[ 33 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %22[ 60 ]
+# CHECK: Vreg: %3[ 48 ]
+# CHECK: Vreg: %17[ LoopTag+80 ]
+# CHECK: Vreg: %62:sub0[ 40 ]
+# CHECK: Vreg: %69[ 18 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+59 ]
+# CHECK: Instr: %79:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %78, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %52[ LoopTag+53 ]
+# CHECK: Vreg: %33[ LoopTag+63 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %21:sub0[ 55 ]
+# CHECK: Vreg: %21:sub1[ 56 ]
+# CHECK: Vreg: %2[ 41 ]
+# CHECK: Vreg: %35[ 13 ]
+# CHECK: Vreg: %4[ LoopTag+62 ]
+# CHECK: Vreg: %30[ 35 ]
+# CHECK: Vreg: %18[ 15 ]
+# CHECK: Vreg: %63[ 48 ]
+# CHECK: Vreg: %32[ LoopTag+89 ]
+# CHECK: Vreg: %20:sub0[ 31 ]
+# CHECK: Vreg: %20:sub1[ 32 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %22[ 59 ]
+# CHECK: Vreg: %3[ 47 ]
+# CHECK: Vreg: %17[ LoopTag+79 ]
+# CHECK: Vreg: %62:sub0[ 39 ]
+# CHECK: Vreg: %69[ 17 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+58 ]
+# CHECK: Instr: %80:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %79, 1333788670, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %52[ LoopTag+52 ]
+# CHECK: Vreg: %33[ LoopTag+62 ]
+# CHECK: Vreg: %21:sub0[ 54 ]
+# CHECK: Vreg: %21:sub1[ 55 ]
+# CHECK: Vreg: %2[ 40 ]
+# CHECK: Vreg: %35[ 12 ]
+# CHECK: Vreg: %4[ LoopTag+61 ]
+# CHECK: Vreg: %30[ 34 ]
+# CHECK: Vreg: %18[ 14 ]
+# CHECK: Vreg: %63[ 47 ]
+# CHECK: Vreg: %32[ LoopTag+88 ]
+# CHECK: Vreg: %20:sub0[ 30 ]
+# CHECK: Vreg: %20:sub1[ 31 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %22[ 58 ]
+# CHECK: Vreg: %3[ 46 ]
+# CHECK: Vreg: %17[ LoopTag+78 ]
+# CHECK: Vreg: %62:sub0[ 38 ]
+# CHECK: Vreg: %69[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+56 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+57 ]
+# CHECK: Instr: %81:sreg_32 = nofpexcept S_CVT_U32_F32 killed %80, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %52[ LoopTag+51 ]
+# CHECK: Vreg: %33[ LoopTag+61 ]
+# CHECK: Vreg: %21:sub0[ 53 ]
+# CHECK: Vreg: %21:sub1[ 54 ]
+# CHECK: Vreg: %2[ 39 ]
+# CHECK: Vreg: %35[ 11 ]
+# CHECK: Vreg: %80[ 0 ]
+# CHECK: Vreg: %4[ LoopTag+60 ]
+# CHECK: Vreg: %30[ 33 ]
+# CHECK: Vreg: %18[ 13 ]
+# CHECK: Vreg: %63[ 46 ]
+# CHECK: Vreg: %32[ LoopTag+87 ]
+# CHECK: Vreg: %20:sub0[ 29 ]
+# CHECK: Vreg: %20:sub1[ 30 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %22[ 57 ]
+# CHECK: Vreg: %3[ 45 ]
+# CHECK: Vreg: %17[ LoopTag+77 ]
+# CHECK: Vreg: %62:sub0[ 37 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+56 ]
+# CHECK: Instr: %82:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %52[ LoopTag+50 ]
+# CHECK: Vreg: %33[ LoopTag+60 ]
+# CHECK: Vreg: %21:sub0[ 52 ]
+# CHECK: Vreg: %21:sub1[ 53 ]
+# CHECK: Vreg: %2[ 38 ]
+# CHECK: Vreg: %35[ 10 ]
+# CHECK: Vreg: %4[ LoopTag+59 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %63[ 45 ]
+# CHECK: Vreg: %32[ LoopTag+86 ]
+# CHECK: Vreg: %20:sub0[ 28 ]
+# CHECK: Vreg: %20:sub1[ 29 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %22[ 56 ]
+# CHECK: Vreg: %3[ 44 ]
+# CHECK: Vreg: %17[ LoopTag+76 ]
+# CHECK: Vreg: %62:sub0[ 36 ]
+# CHECK: Vreg: %81[ 2 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+54 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+55 ]
+# CHECK: Instr: %83:sreg_32 = S_SUB_I32 0, %65, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %52[ LoopTag+49 ]
+# CHECK: Vreg: %33[ LoopTag+59 ]
+# CHECK: Vreg: %21:sub0[ 51 ]
+# CHECK: Vreg: %21:sub1[ 52 ]
+# CHECK: Vreg: %2[ 37 ]
+# CHECK: Vreg: %35[ 9 ]
+# CHECK: Vreg: %4[ LoopTag+58 ]
+# CHECK: Vreg: %30[ 31 ]
+# CHECK: Vreg: %18[ 11 ]
+# CHECK: Vreg: %63[ 44 ]
+# CHECK: Vreg: %82[ 5 ]
+# CHECK: Vreg: %32[ LoopTag+85 ]
+# CHECK: Vreg: %20:sub0[ 27 ]
+# CHECK: Vreg: %20:sub1[ 28 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22[ 55 ]
+# CHECK: Vreg: %3[ 43 ]
+# CHECK: Vreg: %17[ LoopTag+75 ]
+# CHECK: Vreg: %62:sub0[ 35 ]
+# CHECK: Vreg: %81[ 1 ]
+# CHECK: Vreg: %69[ 13 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+54 ]
+# CHECK: Instr: %84:sreg_32 = S_MUL_I32 killed %83, %81
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %83[ 0 ]
+# CHECK: Vreg: %52[ LoopTag+48 ]
+# CHECK: Vreg: %33[ LoopTag+58 ]
+# CHECK: Vreg: %21:sub0[ 50 ]
+# CHECK: Vreg: %21:sub1[ 51 ]
+# CHECK: Vreg: %2[ 36 ]
+# CHECK: Vreg: %35[ 8 ]
+# CHECK: Vreg: %4[ LoopTag+57 ]
+# CHECK: Vreg: %30[ 30 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %63[ 43 ]
+# CHECK: Vreg: %82[ 4 ]
+# CHECK: Vreg: %32[ LoopTag+84 ]
+# CHECK: Vreg: %20:sub0[ 26 ]
+# CHECK: Vreg: %20:sub1[ 27 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %22[ 54 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %17[ LoopTag+74 ]
+# CHECK: Vreg: %62:sub0[ 34 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+52 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+53 ]
+# CHECK: Instr: %85:sreg_32 = S_MUL_HI_U32 %81, killed %84
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %52[ LoopTag+47 ]
+# CHECK: Vreg: %33[ LoopTag+57 ]
+# CHECK: Vreg: %21:sub0[ 49 ]
+# CHECK: Vreg: %21:sub1[ 50 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %35[ 7 ]
+# CHECK: Vreg: %4[ LoopTag+56 ]
+# CHECK: Vreg: %30[ 29 ]
+# CHECK: Vreg: %18[ 9 ]
+# CHECK: Vreg: %63[ 42 ]
+# CHECK: Vreg: %82[ 3 ]
+# CHECK: Vreg: %32[ LoopTag+83 ]
+# CHECK: Vreg: %20:sub0[ 25 ]
+# CHECK: Vreg: %20:sub1[ 26 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %22[ 53 ]
+# CHECK: Vreg: %3[ 41 ]
+# CHECK: Vreg: %17[ LoopTag+73 ]
+# CHECK: Vreg: %62:sub0[ 33 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Vreg: %69[ 11 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+51 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+52 ]
+# CHECK: Instr: %86:sreg_32 = S_ADD_I32 killed %81, killed %85, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %52[ LoopTag+46 ]
+# CHECK: Vreg: %33[ LoopTag+56 ]
+# CHECK: Vreg: %21:sub0[ 48 ]
+# CHECK: Vreg: %21:sub1[ 49 ]
+# CHECK: Vreg: %2[ 34 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %35[ 6 ]
+# CHECK: Vreg: %4[ LoopTag+55 ]
+# CHECK: Vreg: %30[ 28 ]
+# CHECK: Vreg: %18[ 8 ]
+# CHECK: Vreg: %63[ 41 ]
+# CHECK: Vreg: %82[ 2 ]
+# CHECK: Vreg: %32[ LoopTag+82 ]
+# CHECK: Vreg: %20:sub0[ 24 ]
+# CHECK: Vreg: %20:sub1[ 25 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %22[ 52 ]
+# CHECK: Vreg: %3[ 40 ]
+# CHECK: Vreg: %17[ LoopTag+72 ]
+# CHECK: Vreg: %62:sub0[ 32 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+50 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+51 ]
+# CHECK: Instr: %87:sreg_64 = REG_SEQUENCE killed %86, %subreg.sub0, undef %31, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %52[ LoopTag+45 ]
+# CHECK: Vreg: %33[ LoopTag+55 ]
+# CHECK: Vreg: %21:sub0[ 47 ]
+# CHECK: Vreg: %21:sub1[ 48 ]
+# CHECK: Vreg: %2[ 33 ]
+# CHECK: Vreg: %35[ 5 ]
+# CHECK: Vreg: %4[ LoopTag+54 ]
+# CHECK: Vreg: %30[ 27 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %63[ 40 ]
+# CHECK: Vreg: %82[ 1 ]
+# CHECK: Vreg: %32[ LoopTag+81 ]
+# CHECK: Vreg: %20:sub0[ 23 ]
+# CHECK: Vreg: %20:sub1[ 24 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %22[ 51 ]
+# CHECK: Vreg: %3[ 39 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+71 ]
+# CHECK: Vreg: %62:sub0[ 31 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+50 ]
+# CHECK: Instr: %88:sreg_32 = S_MOV_B32 10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %52[ LoopTag+44 ]
+# CHECK: Vreg: %33[ LoopTag+54 ]
+# CHECK: Vreg: %21:sub0[ 46 ]
+# CHECK: Vreg: %21:sub1[ 47 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %87:sub0[ 8 ]
+# CHECK: Vreg: %4[ LoopTag+53 ]
+# CHECK: Vreg: %30[ 26 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %63[ 39 ]
+# CHECK: Vreg: %82[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+80 ]
+# CHECK: Vreg: %20:sub0[ 22 ]
+# CHECK: Vreg: %20:sub1[ 23 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %22[ 50 ]
+# CHECK: Vreg: %3[ 38 ]
+# CHECK: Vreg: %17[ LoopTag+70 ]
+# CHECK: Vreg: %62:sub0[ 30 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+49 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %52[ LoopTag+44 ]
+# CHECK: Vreg: %33[ LoopTag+54 ]
+# CHECK: Vreg: %21:sub0[ 46 ]
+# CHECK: Vreg: %21:sub1[ 47 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %87:sub0[ 8 ]
+# CHECK: Vreg: %4[ LoopTag+53 ]
+# CHECK: Vreg: %30[ 26 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %63[ 39 ]
+# CHECK: Vreg: %82[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+80 ]
+# CHECK: Vreg: %20:sub0[ 22 ]
+# CHECK: Vreg: %20:sub1[ 23 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %22[ 50 ]
+# CHECK: Vreg: %3[ 38 ]
+# CHECK: Vreg: %17[ LoopTag+70 ]
+# CHECK: Vreg: %62:sub0[ 30 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+49 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %89:sreg_32 = PHI %82, %bb.2, %90, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+44 ]
+# CHECK: Vreg: %33[ LoopTag*2+54 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+47 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %87:sub0[ 8 ]
+# CHECK: Vreg: %4[ LoopTag*2+53 ]
+# CHECK: Vreg: %30[ 26 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %63[ LoopTag+39 ]
+# CHECK: Vreg: %82[ 0 ]
+# CHECK: Vreg: %32[ LoopTag*2+80 ]
+# CHECK: Vreg: %20:sub0[ 22 ]
+# CHECK: Vreg: %20:sub1[ 23 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %22[ 50 ]
+# CHECK: Vreg: %3[ LoopTag+38 ]
+# CHECK: Vreg: %17[ LoopTag*2+70 ]
+# CHECK: Vreg: %62:sub0[ 30 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+48 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+49 ]
+# CHECK: Instr: %91:sreg_32 = PHI %88, %bb.2, %92, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %52[ LoopTag*2+44 ]
+# CHECK: Vreg: %33[ LoopTag*2+54 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+47 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %87:sub0[ 8 ]
+# CHECK: Vreg: %4[ LoopTag*2+53 ]
+# CHECK: Vreg: %30[ 26 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %63[ LoopTag+39 ]
+# CHECK: Vreg: %89[ 33 ]
+# CHECK: Vreg: %32[ LoopTag*2+80 ]
+# CHECK: Vreg: %20:sub0[ 22 ]
+# CHECK: Vreg: %20:sub1[ 23 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %22[ 50 ]
+# CHECK: Vreg: %3[ LoopTag+38 ]
+# CHECK: Vreg: %17[ LoopTag*2+70 ]
+# CHECK: Vreg: %62:sub0[ 30 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+48 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+49 ]
+# CHECK: Instr: %93:sreg_32 = V_CMP_GE_U32_e64 %91, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+43 ]
+# CHECK: Vreg: %33[ LoopTag*2+53 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+46 ]
+# CHECK: Vreg: %2[ 31 ]
+# CHECK: Vreg: %35[ 3 ]
+# CHECK: Vreg: %87:sub0[ 7 ]
+# CHECK: Vreg: %4[ LoopTag*2+52 ]
+# CHECK: Vreg: %30[ 25 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %63[ LoopTag+38 ]
+# CHECK: Vreg: %89[ 32 ]
+# CHECK: Vreg: %32[ LoopTag*2+79 ]
+# CHECK: Vreg: %20:sub0[ 21 ]
+# CHECK: Vreg: %20:sub1[ 22 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %22[ 49 ]
+# CHECK: Vreg: %3[ LoopTag+37 ]
+# CHECK: Vreg: %17[ LoopTag*2+69 ]
+# CHECK: Vreg: %62:sub0[ 29 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+47 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+48 ]
+# CHECK: Instr: %94:sreg_32 = SI_IF killed %93, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %52[ LoopTag*2+42 ]
+# CHECK: Vreg: %33[ LoopTag*2+52 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+45 ]
+# CHECK: Vreg: %2[ 30 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %87:sub0[ 6 ]
+# CHECK: Vreg: %4[ LoopTag*2+51 ]
+# CHECK: Vreg: %30[ 24 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %63[ LoopTag+37 ]
+# CHECK: Vreg: %89[ 31 ]
+# CHECK: Vreg: %32[ LoopTag*2+78 ]
+# CHECK: Vreg: %20:sub0[ 20 ]
+# CHECK: Vreg: %20:sub1[ 21 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %22[ 48 ]
+# CHECK: Vreg: %3[ LoopTag+36 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+68 ]
+# CHECK: Vreg: %62:sub0[ 28 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+46 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+47 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %52[ LoopTag*2+41 ]
+# CHECK: Vreg: %33[ LoopTag*2+51 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+44 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %87:sub0[ 5 ]
+# CHECK: Vreg: %4[ LoopTag*2+50 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %94[ 1 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %63[ LoopTag+36 ]
+# CHECK: Vreg: %89[ 30 ]
+# CHECK: Vreg: %32[ LoopTag*2+77 ]
+# CHECK: Vreg: %20:sub0[ 19 ]
+# CHECK: Vreg: %20:sub1[ 20 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %91[ 1 ]
+# CHECK: Vreg: %22[ 47 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %17[ LoopTag*2+67 ]
+# CHECK: Vreg: %62:sub0[ 27 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+45 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+46 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %52[ LoopTag*2+41 ]
+# CHECK: Vreg: %33[ LoopTag*2+51 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+44 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %87:sub0[ 5 ]
+# CHECK: Vreg: %4[ LoopTag*2+50 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %94[ 1 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %63[ LoopTag+36 ]
+# CHECK: Vreg: %89[ 30 ]
+# CHECK: Vreg: %32[ LoopTag*2+77 ]
+# CHECK: Vreg: %20:sub0[ 19 ]
+# CHECK: Vreg: %20:sub1[ 20 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %91[ 1 ]
+# CHECK: Vreg: %22[ 47 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %17[ LoopTag*2+67 ]
+# CHECK: Vreg: %62:sub0[ 27 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+45 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+46 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %95:vgpr_32 = PHI undef %96:vgpr_32, %bb.3, %69, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %52[ LoopTag*2+41 ]
+# CHECK: Vreg: %33[ LoopTag*2+51 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+44 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %35[ 28 ]
+# CHECK: Vreg: %87:sub0[ 5 ]
+# CHECK: Vreg: %4[ LoopTag*2+50 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %94[ 1 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %63[ LoopTag+36 ]
+# CHECK: Vreg: %89[ 30 ]
+# CHECK: Vreg: %32[ LoopTag*2+77 ]
+# CHECK: Vreg: %20:sub0[ 19 ]
+# CHECK: Vreg: %20:sub1[ 20 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %22[ 47 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+67 ]
+# CHECK: Vreg: %62:sub0[ 27 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+45 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+46 ]
+# CHECK: Instr: %97:vgpr_32 = PHI undef %96:vgpr_32, %bb.3, %98, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %52[ LoopTag*2+41 ]
+# CHECK: Vreg: %33[ LoopTag*2+51 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+44 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %35[ 28 ]
+# CHECK: Vreg: %87:sub0[ 5 ]
+# CHECK: Vreg: %4[ LoopTag*2+50 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %94[ 1 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %63[ LoopTag+36 ]
+# CHECK: Vreg: %89[ 30 ]
+# CHECK: Vreg: %32[ LoopTag*2+77 ]
+# CHECK: Vreg: %20:sub0[ 19 ]
+# CHECK: Vreg: %20:sub1[ 20 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %22[ 47 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+67 ]
+# CHECK: Vreg: %62:sub0[ 27 ]
+# CHECK: Vreg: %69[ 24 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+45 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+46 ]
+# CHECK: Instr: %99:vgpr_32 = PHI undef %96:vgpr_32, %bb.3, %100, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %52[ LoopTag*2+41 ]
+# CHECK: Vreg: %33[ LoopTag*2+51 ]
+# CHECK: Vreg: %97[ 2 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+44 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %35[ 28 ]
+# CHECK: Vreg: %87:sub0[ 5 ]
+# CHECK: Vreg: %4[ LoopTag*2+50 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %94[ 1 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %63[ LoopTag+36 ]
+# CHECK: Vreg: %89[ 30 ]
+# CHECK: Vreg: %32[ LoopTag*2+77 ]
+# CHECK: Vreg: %20:sub0[ 19 ]
+# CHECK: Vreg: %20:sub1[ 20 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %22[ 47 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+67 ]
+# CHECK: Vreg: %62:sub0[ 27 ]
+# CHECK: Vreg: %69[ 24 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+45 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+46 ]
+# CHECK: Instr: %101:sreg_32 = SI_ELSE killed %94, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %52[ LoopTag*2+40 ]
+# CHECK: Vreg: %33[ LoopTag*2+50 ]
+# CHECK: Vreg: %97[ 1 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+43 ]
+# CHECK: Vreg: %2[ 28 ]
+# CHECK: Vreg: %35[ 27 ]
+# CHECK: Vreg: %99[ 1 ]
+# CHECK: Vreg: %87:sub0[ 4 ]
+# CHECK: Vreg: %4[ LoopTag*2+49 ]
+# CHECK: Vreg: %30[ 22 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %63[ LoopTag+35 ]
+# CHECK: Vreg: %89[ 29 ]
+# CHECK: Vreg: %32[ LoopTag*2+76 ]
+# CHECK: Vreg: %20:sub0[ 18 ]
+# CHECK: Vreg: %20:sub1[ 19 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %22[ 46 ]
+# CHECK: Vreg: %3[ LoopTag+34 ]
+# CHECK: Vreg: %17[ LoopTag*2+66 ]
+# CHECK: Vreg: %62:sub0[ 26 ]
+# CHECK: Vreg: %69[ 23 ]
+# CHECK: Vreg: %95[ 1 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+44 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+45 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %52[ LoopTag*2+39 ]
+# CHECK: Vreg: %33[ LoopTag*2+49 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+42 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %35[ 26 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %87:sub0[ 3 ]
+# CHECK: Vreg: %4[ LoopTag*2+48 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %63[ LoopTag+34 ]
+# CHECK: Vreg: %89[ 28 ]
+# CHECK: Vreg: %32[ LoopTag*2+75 ]
+# CHECK: Vreg: %20:sub0[ 17 ]
+# CHECK: Vreg: %20:sub1[ 18 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %91[ 1 ]
+# CHECK: Vreg: %22[ 45 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %17[ LoopTag*2+65 ]
+# CHECK: Vreg: %62:sub0[ 25 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+43 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+44 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %52[ LoopTag*2+39 ]
+# CHECK: Vreg: %33[ LoopTag*2+49 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+42 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %35[ 26 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %87:sub0[ 3 ]
+# CHECK: Vreg: %4[ LoopTag*2+48 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %63[ LoopTag+34 ]
+# CHECK: Vreg: %89[ 28 ]
+# CHECK: Vreg: %32[ LoopTag*2+75 ]
+# CHECK: Vreg: %20:sub0[ 17 ]
+# CHECK: Vreg: %20:sub1[ 18 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %91[ 1 ]
+# CHECK: Vreg: %22[ 45 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %17[ LoopTag*2+65 ]
+# CHECK: Vreg: %62:sub0[ 25 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+43 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+44 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %102:sreg_32 = S_MUL_I32 %65, %91
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 48 ]
+# CHECK: Vreg: %52[ LoopTag*2+56 ]
+# CHECK: Vreg: %33[ LoopTag*2+66 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %2[ 44 ]
+# CHECK: Vreg: %35[ 43 ]
+# CHECK: Vreg: %87:sub0[ 20 ]
+# CHECK: Vreg: %4[ LoopTag*2+65 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %101[ 18 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %63[ LoopTag+51 ]
+# CHECK: Vreg: %89[ 45 ]
+# CHECK: Vreg: %32[ LoopTag*2+92 ]
+# CHECK: Vreg: %20:sub0[ 34 ]
+# CHECK: Vreg: %20:sub1[ 35 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %22[ 62 ]
+# CHECK: Vreg: %3[ LoopTag+50 ]
+# CHECK: Vreg: %17[ LoopTag*2+82 ]
+# CHECK: Vreg: %62:sub0[ 42 ]
+# CHECK: Vreg: %69[ 39 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+60 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+61 ]
+# CHECK: Instr: %103:vgpr_32 = COPY %102
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %52[ LoopTag*2+55 ]
+# CHECK: Vreg: %33[ LoopTag*2+65 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %2[ 43 ]
+# CHECK: Vreg: %35[ 42 ]
+# CHECK: Vreg: %87:sub0[ 19 ]
+# CHECK: Vreg: %4[ LoopTag*2+64 ]
+# CHECK: Vreg: %30[ 37 ]
+# CHECK: Vreg: %101[ 17 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %63[ LoopTag+50 ]
+# CHECK: Vreg: %89[ 44 ]
+# CHECK: Vreg: %32[ LoopTag*2+91 ]
+# CHECK: Vreg: %20:sub0[ 33 ]
+# CHECK: Vreg: %20:sub1[ 34 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %65[ 20 ]
+# CHECK: Vreg: %91[ 42 ]
+# CHECK: Vreg: %22[ 61 ]
+# CHECK: Vreg: %3[ LoopTag+49 ]
+# CHECK: Vreg: %17[ LoopTag*2+81 ]
+# CHECK: Vreg: %62:sub0[ 41 ]
+# CHECK: Vreg: %69[ 38 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+59 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+60 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %18, killed %103, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %52[ LoopTag*2+54 ]
+# CHECK: Vreg: %33[ LoopTag*2+64 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+56 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+57 ]
+# CHECK: Vreg: %2[ 42 ]
+# CHECK: Vreg: %35[ 41 ]
+# CHECK: Vreg: %87:sub0[ 18 ]
+# CHECK: Vreg: %4[ LoopTag*2+63 ]
+# CHECK: Vreg: %30[ 36 ]
+# CHECK: Vreg: %101[ 16 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %63[ LoopTag+49 ]
+# CHECK: Vreg: %89[ 43 ]
+# CHECK: Vreg: %32[ LoopTag*2+90 ]
+# CHECK: Vreg: %103[ 0 ]
+# CHECK: Vreg: %20:sub0[ 32 ]
+# CHECK: Vreg: %20:sub1[ 33 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %65[ 19 ]
+# CHECK: Vreg: %91[ 41 ]
+# CHECK: Vreg: %22[ 60 ]
+# CHECK: Vreg: %3[ LoopTag+48 ]
+# CHECK: Vreg: %17[ LoopTag*2+80 ]
+# CHECK: Vreg: %62:sub0[ 40 ]
+# CHECK: Vreg: %69[ 37 ]
+# CHECK: Vreg: %102[ 14 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+58 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+59 ]
+# CHECK: Instr: %104:sreg_32 = S_MOV_B32 19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %52[ LoopTag*2+53 ]
+# CHECK: Vreg: %33[ LoopTag*2+63 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %2[ 41 ]
+# CHECK: Vreg: %35[ 40 ]
+# CHECK: Vreg: %87:sub0[ 17 ]
+# CHECK: Vreg: %4[ LoopTag*2+62 ]
+# CHECK: Vreg: %30[ 35 ]
+# CHECK: Vreg: %101[ 15 ]
+# CHECK: Vreg: %18[ 50 ]
+# CHECK: Vreg: %63[ LoopTag+48 ]
+# CHECK: Vreg: %89[ 42 ]
+# CHECK: Vreg: %32[ LoopTag*2+89 ]
+# CHECK: Vreg: %20:sub0[ 31 ]
+# CHECK: Vreg: %20:sub1[ 32 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %65[ 18 ]
+# CHECK: Vreg: %91[ 40 ]
+# CHECK: Vreg: %22[ 59 ]
+# CHECK: Vreg: %3[ LoopTag+47 ]
+# CHECK: Vreg: %17[ LoopTag*2+79 ]
+# CHECK: Vreg: %62:sub0[ 39 ]
+# CHECK: Vreg: %69[ 36 ]
+# CHECK: Vreg: %102[ 13 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+57 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+58 ]
+# CHECK: Instr: %105:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 44 ]
+# CHECK: Vreg: %52[ LoopTag*2+52 ]
+# CHECK: Vreg: %33[ LoopTag*2+62 ]
+# CHECK: Vreg: %104[ 1 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+54 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+55 ]
+# CHECK: Vreg: %2[ 40 ]
+# CHECK: Vreg: %35[ 39 ]
+# CHECK: Vreg: %87:sub0[ 16 ]
+# CHECK: Vreg: %4[ LoopTag*2+61 ]
+# CHECK: Vreg: %30[ 34 ]
+# CHECK: Vreg: %101[ 14 ]
+# CHECK: Vreg: %18[ 49 ]
+# CHECK: Vreg: %63[ LoopTag+47 ]
+# CHECK: Vreg: %89[ 41 ]
+# CHECK: Vreg: %32[ LoopTag*2+88 ]
+# CHECK: Vreg: %20:sub0[ 30 ]
+# CHECK: Vreg: %20:sub1[ 31 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %91[ 39 ]
+# CHECK: Vreg: %22[ 58 ]
+# CHECK: Vreg: %3[ LoopTag+46 ]
+# CHECK: Vreg: %17[ LoopTag*2+78 ]
+# CHECK: Vreg: %62:sub0[ 38 ]
+# CHECK: Vreg: %69[ 35 ]
+# CHECK: Vreg: %102[ 12 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+56 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+57 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Vreg: %52[ LoopTag*2+51 ]
+# CHECK: Vreg: %33[ LoopTag*2+61 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %2[ 39 ]
+# CHECK: Vreg: %35[ 38 ]
+# CHECK: Vreg: %87:sub0[ 15 ]
+# CHECK: Vreg: %4[ LoopTag*2+60 ]
+# CHECK: Vreg: %30[ 33 ]
+# CHECK: Vreg: %101[ 13 ]
+# CHECK: Vreg: %18[ 48 ]
+# CHECK: Vreg: %63[ LoopTag+46 ]
+# CHECK: Vreg: %89[ 40 ]
+# CHECK: Vreg: %32[ LoopTag*2+87 ]
+# CHECK: Vreg: %20:sub0[ 29 ]
+# CHECK: Vreg: %20:sub1[ 30 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %91[ 38 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %22[ 57 ]
+# CHECK: Vreg: %3[ LoopTag+45 ]
+# CHECK: Vreg: %17[ LoopTag*2+77 ]
+# CHECK: Vreg: %62:sub0[ 37 ]
+# CHECK: Vreg: %69[ 34 ]
+# CHECK: Vreg: %102[ 11 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+55 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+56 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Vreg: %52[ LoopTag*2+51 ]
+# CHECK: Vreg: %33[ LoopTag*2+61 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %2[ 39 ]
+# CHECK: Vreg: %35[ 38 ]
+# CHECK: Vreg: %87:sub0[ 15 ]
+# CHECK: Vreg: %4[ LoopTag*2+60 ]
+# CHECK: Vreg: %30[ 33 ]
+# CHECK: Vreg: %101[ 13 ]
+# CHECK: Vreg: %18[ 48 ]
+# CHECK: Vreg: %63[ LoopTag+46 ]
+# CHECK: Vreg: %89[ 40 ]
+# CHECK: Vreg: %32[ LoopTag*2+87 ]
+# CHECK: Vreg: %20:sub0[ 29 ]
+# CHECK: Vreg: %20:sub1[ 30 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %91[ 38 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %22[ 57 ]
+# CHECK: Vreg: %3[ LoopTag+45 ]
+# CHECK: Vreg: %17[ LoopTag*2+77 ]
+# CHECK: Vreg: %62:sub0[ 37 ]
+# CHECK: Vreg: %69[ 34 ]
+# CHECK: Vreg: %102[ 11 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+55 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+56 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %38:vgpr_32 = PHI %95, %bb.4, %106, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %52[ LoopTag*2+39 ]
+# CHECK: Vreg: %33[ LoopTag*2+49 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+42 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %35[ 26 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %87:sub0[ 3 ]
+# CHECK: Vreg: %4[ LoopTag*2+48 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %18[ 36 ]
+# CHECK: Vreg: %63[ LoopTag+34 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %89[ 28 ]
+# CHECK: Vreg: %32[ LoopTag*2+75 ]
+# CHECK: Vreg: %20:sub0[ 17 ]
+# CHECK: Vreg: %20:sub1[ 18 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %91[ 26 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %22[ 45 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %17[ LoopTag*2+65 ]
+# CHECK: Vreg: %62:sub0[ 25 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+43 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+44 ]
+# CHECK: Instr: %107:vgpr_32 = PHI %97, %bb.4, %108, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %52[ LoopTag*2+39 ]
+# CHECK: Vreg: %33[ LoopTag*2+49 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+42 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %35[ 26 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %87:sub0[ 3 ]
+# CHECK: Vreg: %4[ LoopTag*2+48 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %18[ 36 ]
+# CHECK: Vreg: %63[ LoopTag+34 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %89[ 28 ]
+# CHECK: Vreg: %32[ LoopTag*2+75 ]
+# CHECK: Vreg: %20:sub0[ 17 ]
+# CHECK: Vreg: %20:sub1[ 18 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %91[ 26 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %22[ 45 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %17[ LoopTag*2+65 ]
+# CHECK: Vreg: %62:sub0[ 25 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %38[ LoopTag*2+51 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+43 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+44 ]
+# CHECK: Instr: %109:vgpr_32 = PHI %99, %bb.4, %110, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %52[ LoopTag*2+39 ]
+# CHECK: Vreg: %33[ LoopTag*2+49 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+42 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %35[ 26 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %87:sub0[ 3 ]
+# CHECK: Vreg: %4[ LoopTag*2+48 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %18[ 36 ]
+# CHECK: Vreg: %63[ LoopTag+34 ]
+# CHECK: Vreg: %89[ 28 ]
+# CHECK: Vreg: %32[ LoopTag*2+75 ]
+# CHECK: Vreg: %20:sub0[ 17 ]
+# CHECK: Vreg: %20:sub1[ 18 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %91[ 26 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %22[ 45 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %17[ LoopTag*2+65 ]
+# CHECK: Vreg: %62:sub0[ 25 ]
+# CHECK: Vreg: %107[ 21 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %38[ LoopTag*2+51 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+43 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+44 ]
+# CHECK: Instr: SI_END_CF killed %101, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %109[ 2 ]
+# CHECK: Vreg: %52[ LoopTag*2+38 ]
+# CHECK: Vreg: %33[ LoopTag*2+48 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+41 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %35[ 25 ]
+# CHECK: Vreg: %87:sub0[ 2 ]
+# CHECK: Vreg: %4[ LoopTag*2+47 ]
+# CHECK: Vreg: %30[ 20 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %18[ 35 ]
+# CHECK: Vreg: %63[ LoopTag+33 ]
+# CHECK: Vreg: %89[ 27 ]
+# CHECK: Vreg: %32[ LoopTag*2+74 ]
+# CHECK: Vreg: %20:sub0[ 16 ]
+# CHECK: Vreg: %20:sub1[ 17 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %91[ 25 ]
+# CHECK: Vreg: %22[ 44 ]
+# CHECK: Vreg: %3[ LoopTag+32 ]
+# CHECK: Vreg: %17[ LoopTag*2+64 ]
+# CHECK: Vreg: %62:sub0[ 24 ]
+# CHECK: Vreg: %107[ 20 ]
+# CHECK: Vreg: %69[ 21 ]
+# CHECK: Vreg: %38[ LoopTag*2+50 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+42 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+43 ]
+# CHECK: Instr: S_BRANCH %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %52[ LoopTag*2+37 ]
+# CHECK: Vreg: %33[ LoopTag*2+47 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+39 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+40 ]
+# CHECK: Vreg: %2[ 25 ]
+# CHECK: Vreg: %35[ 24 ]
+# CHECK: Vreg: %87:sub0[ 1 ]
+# CHECK: Vreg: %4[ LoopTag*2+46 ]
+# CHECK: Vreg: %30[ 19 ]
+# CHECK: Vreg: %18[ 34 ]
+# CHECK: Vreg: %63[ LoopTag+32 ]
+# CHECK: Vreg: %89[ 26 ]
+# CHECK: Vreg: %32[ LoopTag*2+73 ]
+# CHECK: Vreg: %20:sub0[ 15 ]
+# CHECK: Vreg: %20:sub1[ 16 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %91[ 24 ]
+# CHECK: Vreg: %22[ 43 ]
+# CHECK: Vreg: %3[ LoopTag+31 ]
+# CHECK: Vreg: %17[ LoopTag*2+63 ]
+# CHECK: Vreg: %62:sub0[ 23 ]
+# CHECK: Vreg: %107[ 19 ]
+# CHECK: Vreg: %69[ 20 ]
+# CHECK: Vreg: %38[ LoopTag*2+49 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+41 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+42 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %52[ LoopTag*2+37 ]
+# CHECK: Vreg: %33[ LoopTag*2+47 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+39 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+40 ]
+# CHECK: Vreg: %2[ 25 ]
+# CHECK: Vreg: %35[ 24 ]
+# CHECK: Vreg: %87:sub0[ 1 ]
+# CHECK: Vreg: %4[ LoopTag*2+46 ]
+# CHECK: Vreg: %30[ 19 ]
+# CHECK: Vreg: %18[ 34 ]
+# CHECK: Vreg: %63[ LoopTag+32 ]
+# CHECK: Vreg: %89[ 26 ]
+# CHECK: Vreg: %32[ LoopTag*2+73 ]
+# CHECK: Vreg: %20:sub0[ 15 ]
+# CHECK: Vreg: %20:sub1[ 16 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %91[ 24 ]
+# CHECK: Vreg: %22[ 43 ]
+# CHECK: Vreg: %3[ LoopTag+31 ]
+# CHECK: Vreg: %17[ LoopTag*2+63 ]
+# CHECK: Vreg: %62:sub0[ 23 ]
+# CHECK: Vreg: %107[ 19 ]
+# CHECK: Vreg: %69[ 20 ]
+# CHECK: Vreg: %38[ LoopTag*2+49 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+41 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+42 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: %111:sreg_32 = PHI %105, %bb.5, %112, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+43 ]
+# CHECK: Vreg: %52[ LoopTag*3+51 ]
+# CHECK: Vreg: %33[ LoopTag*3+61 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+53 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+54 ]
+# CHECK: Vreg: %2[ LoopTag+39 ]
+# CHECK: Vreg: %35[ LoopTag+38 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+15 ]
+# CHECK: Vreg: %4[ LoopTag*3+60 ]
+# CHECK: Vreg: %30[ LoopTag+33 ]
+# CHECK: Vreg: %101[ LoopTag+13 ]
+# CHECK: Vreg: %18[ LoopTag+48 ]
+# CHECK: Vreg: %63[ LoopTag*2+46 ]
+# CHECK: Vreg: %89[ LoopTag+40 ]
+# CHECK: Vreg: %32[ LoopTag*3+87 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+29 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+30 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+16 ]
+# CHECK: Vreg: %91[ LoopTag+38 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %22[ LoopTag+57 ]
+# CHECK: Vreg: %3[ LoopTag*2+45 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*3+77 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %69[ LoopTag+34 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %102[ LoopTag+11 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+55 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+56 ]
+# CHECK: Instr: %113:sreg_32 = PHI %104, %bb.5, %114, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+43 ]
+# CHECK: Vreg: %52[ LoopTag*3+51 ]
+# CHECK: Vreg: %33[ LoopTag*3+61 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+53 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+54 ]
+# CHECK: Vreg: %2[ LoopTag+39 ]
+# CHECK: Vreg: %111[ 4 ]
+# CHECK: Vreg: %35[ LoopTag+38 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+15 ]
+# CHECK: Vreg: %4[ LoopTag*3+60 ]
+# CHECK: Vreg: %30[ LoopTag+33 ]
+# CHECK: Vreg: %101[ LoopTag+13 ]
+# CHECK: Vreg: %18[ LoopTag+48 ]
+# CHECK: Vreg: %63[ LoopTag*2+46 ]
+# CHECK: Vreg: %89[ LoopTag+40 ]
+# CHECK: Vreg: %32[ LoopTag*3+87 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+29 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+30 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+16 ]
+# CHECK: Vreg: %91[ LoopTag+38 ]
+# CHECK: Vreg: %22[ LoopTag+57 ]
+# CHECK: Vreg: %3[ LoopTag*2+45 ]
+# CHECK: Vreg: %17[ LoopTag*3+77 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %69[ LoopTag+34 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %102[ LoopTag+11 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+55 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+56 ]
+# CHECK: Instr: %114:sreg_32 = nuw S_ADD_I32 %113, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+42 ]
+# CHECK: Vreg: %52[ LoopTag*3+50 ]
+# CHECK: Vreg: %33[ LoopTag*3+60 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+52 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+53 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %111[ 3 ]
+# CHECK: Vreg: %35[ LoopTag+37 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+14 ]
+# CHECK: Vreg: %4[ LoopTag*3+59 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %30[ LoopTag+32 ]
+# CHECK: Vreg: %101[ LoopTag+12 ]
+# CHECK: Vreg: %18[ LoopTag+47 ]
+# CHECK: Vreg: %63[ LoopTag*2+45 ]
+# CHECK: Vreg: %89[ LoopTag+39 ]
+# CHECK: Vreg: %32[ LoopTag*3+86 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+28 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+29 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %65[ LoopTag+15 ]
+# CHECK: Vreg: %91[ LoopTag+37 ]
+# CHECK: Vreg: %22[ LoopTag+56 ]
+# CHECK: Vreg: %3[ LoopTag*2+44 ]
+# CHECK: Vreg: %17[ LoopTag*3+76 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+36 ]
+# CHECK: Vreg: %69[ LoopTag+33 ]
+# CHECK: Vreg: %102[ LoopTag+10 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+54 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+55 ]
+# CHECK: Instr: %115:sreg_32 = S_ADD_I32 killed %113, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+41 ]
+# CHECK: Vreg: %52[ LoopTag*3+49 ]
+# CHECK: Vreg: %33[ LoopTag*3+59 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+51 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+52 ]
+# CHECK: Vreg: %2[ LoopTag+37 ]
+# CHECK: Vreg: %111[ 2 ]
+# CHECK: Vreg: %35[ LoopTag+36 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+13 ]
+# CHECK: Vreg: %4[ LoopTag*3+58 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %30[ LoopTag+31 ]
+# CHECK: Vreg: %101[ LoopTag+11 ]
+# CHECK: Vreg: %18[ LoopTag+46 ]
+# CHECK: Vreg: %63[ LoopTag*2+44 ]
+# CHECK: Vreg: %89[ LoopTag+38 ]
+# CHECK: Vreg: %32[ LoopTag*3+85 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+27 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+28 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %65[ LoopTag+14 ]
+# CHECK: Vreg: %91[ LoopTag+36 ]
+# CHECK: Vreg: %22[ LoopTag+55 ]
+# CHECK: Vreg: %3[ LoopTag*2+43 ]
+# CHECK: Vreg: %17[ LoopTag*3+75 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+35 ]
+# CHECK: Vreg: %69[ LoopTag+32 ]
+# CHECK: Vreg: %114[ 3 ]
+# CHECK: Vreg: %102[ LoopTag+9 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+53 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+54 ]
+# CHECK: Instr: %116:sreg_32 = V_CMP_GE_U32_e64 %115, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+40 ]
+# CHECK: Vreg: %52[ LoopTag*3+48 ]
+# CHECK: Vreg: %33[ LoopTag*3+58 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+50 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+51 ]
+# CHECK: Vreg: %2[ LoopTag+36 ]
+# CHECK: Vreg: %111[ 1 ]
+# CHECK: Vreg: %35[ LoopTag+35 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+12 ]
+# CHECK: Vreg: %4[ LoopTag*3+57 ]
+# CHECK: Vreg: %30[ LoopTag+30 ]
+# CHECK: Vreg: %101[ LoopTag+10 ]
+# CHECK: Vreg: %18[ LoopTag+45 ]
+# CHECK: Vreg: %63[ LoopTag*2+43 ]
+# CHECK: Vreg: %89[ LoopTag+37 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %32[ LoopTag*3+84 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+26 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+27 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+13 ]
+# CHECK: Vreg: %91[ LoopTag+35 ]
+# CHECK: Vreg: %22[ LoopTag+54 ]
+# CHECK: Vreg: %3[ LoopTag*2+42 ]
+# CHECK: Vreg: %17[ LoopTag*3+74 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+34 ]
+# CHECK: Vreg: %69[ LoopTag+31 ]
+# CHECK: Vreg: %114[ 2 ]
+# CHECK: Vreg: %102[ LoopTag+8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+52 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+53 ]
+# CHECK: Instr: %112:sreg_32 = SI_IF_BREAK killed %116, killed %111, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+39 ]
+# CHECK: Vreg: %52[ LoopTag*3+47 ]
+# CHECK: Vreg: %33[ LoopTag*3+57 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+49 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+50 ]
+# CHECK: Vreg: %2[ LoopTag+35 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %35[ LoopTag+34 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+11 ]
+# CHECK: Vreg: %4[ LoopTag*3+56 ]
+# CHECK: Vreg: %30[ LoopTag+29 ]
+# CHECK: Vreg: %101[ LoopTag+9 ]
+# CHECK: Vreg: %18[ LoopTag+44 ]
+# CHECK: Vreg: %63[ LoopTag*2+42 ]
+# CHECK: Vreg: %89[ LoopTag+36 ]
+# CHECK: Vreg: %115[ 2 ]
+# CHECK: Vreg: %32[ LoopTag*3+83 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+25 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+26 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %65[ LoopTag+12 ]
+# CHECK: Vreg: %91[ LoopTag+34 ]
+# CHECK: Vreg: %22[ LoopTag+53 ]
+# CHECK: Vreg: %3[ LoopTag*2+41 ]
+# CHECK: Vreg: %17[ LoopTag*3+73 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+33 ]
+# CHECK: Vreg: %69[ LoopTag+30 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Vreg: %102[ LoopTag+7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+51 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+52 ]
+# CHECK: Instr: %110:vgpr_32 = COPY %114, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+38 ]
+# CHECK: Vreg: %52[ LoopTag*3+46 ]
+# CHECK: Vreg: %33[ LoopTag*3+56 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+48 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+49 ]
+# CHECK: Vreg: %2[ LoopTag+34 ]
+# CHECK: Vreg: %35[ LoopTag+33 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+10 ]
+# CHECK: Vreg: %4[ LoopTag*3+55 ]
+# CHECK: Vreg: %30[ LoopTag+28 ]
+# CHECK: Vreg: %101[ LoopTag+8 ]
+# CHECK: Vreg: %18[ LoopTag+43 ]
+# CHECK: Vreg: %63[ LoopTag*2+41 ]
+# CHECK: Vreg: %89[ LoopTag+35 ]
+# CHECK: Vreg: %115[ 1 ]
+# CHECK: Vreg: %32[ LoopTag*3+82 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+24 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+25 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %65[ LoopTag+11 ]
+# CHECK: Vreg: %91[ LoopTag+33 ]
+# CHECK: Vreg: %22[ LoopTag+52 ]
+# CHECK: Vreg: %3[ LoopTag*2+40 ]
+# CHECK: Vreg: %112[ 2 ]
+# CHECK: Vreg: %17[ LoopTag*3+72 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+32 ]
+# CHECK: Vreg: %69[ LoopTag+29 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %102[ LoopTag+6 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+50 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+51 ]
+# CHECK: Instr: %117:vgpr_32 = COPY killed %115, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+37 ]
+# CHECK: Vreg: %52[ LoopTag*3+45 ]
+# CHECK: Vreg: %33[ LoopTag*3+55 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+47 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+48 ]
+# CHECK: Vreg: %2[ LoopTag+33 ]
+# CHECK: Vreg: %35[ LoopTag+32 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+9 ]
+# CHECK: Vreg: %4[ LoopTag*3+54 ]
+# CHECK: Vreg: %30[ LoopTag+27 ]
+# CHECK: Vreg: %101[ LoopTag+7 ]
+# CHECK: Vreg: %18[ LoopTag+42 ]
+# CHECK: Vreg: %63[ LoopTag*2+40 ]
+# CHECK: Vreg: %89[ LoopTag+34 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %32[ LoopTag*3+81 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+23 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+24 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %65[ LoopTag+10 ]
+# CHECK: Vreg: %91[ LoopTag+32 ]
+# CHECK: Vreg: %110[ LoopTag+4 ]
+# CHECK: Vreg: %22[ LoopTag+51 ]
+# CHECK: Vreg: %3[ LoopTag*2+39 ]
+# CHECK: Vreg: %112[ 1 ]
+# CHECK: Vreg: %17[ LoopTag*3+71 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+31 ]
+# CHECK: Vreg: %69[ LoopTag+28 ]
+# CHECK: Vreg: %114[ 2 ]
+# CHECK: Vreg: %102[ LoopTag+5 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+49 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+50 ]
+# CHECK: Instr: SI_LOOP %112, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+36 ]
+# CHECK: Vreg: %52[ LoopTag*3+44 ]
+# CHECK: Vreg: %33[ LoopTag*3+54 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+46 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+47 ]
+# CHECK: Vreg: %2[ LoopTag+32 ]
+# CHECK: Vreg: %35[ LoopTag+31 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+8 ]
+# CHECK: Vreg: %4[ LoopTag*3+53 ]
+# CHECK: Vreg: %30[ LoopTag+26 ]
+# CHECK: Vreg: %101[ LoopTag+6 ]
+# CHECK: Vreg: %18[ LoopTag+41 ]
+# CHECK: Vreg: %63[ LoopTag*2+39 ]
+# CHECK: Vreg: %89[ LoopTag+33 ]
+# CHECK: Vreg: %32[ LoopTag*3+80 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+22 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+23 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %65[ LoopTag+9 ]
+# CHECK: Vreg: %91[ LoopTag+31 ]
+# CHECK: Vreg: %110[ LoopTag+3 ]
+# CHECK: Vreg: %117[ LoopTag+3 ]
+# CHECK: Vreg: %22[ LoopTag+50 ]
+# CHECK: Vreg: %3[ LoopTag*2+38 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*3+70 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+30 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Vreg: %102[ LoopTag+4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+48 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+49 ]
+# CHECK: Instr: S_BRANCH %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+35 ]
+# CHECK: Vreg: %52[ LoopTag*3+43 ]
+# CHECK: Vreg: %33[ LoopTag*3+53 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+45 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+46 ]
+# CHECK: Vreg: %2[ LoopTag+31 ]
+# CHECK: Vreg: %35[ LoopTag+30 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+7 ]
+# CHECK: Vreg: %4[ LoopTag*3+52 ]
+# CHECK: Vreg: %30[ LoopTag+25 ]
+# CHECK: Vreg: %101[ LoopTag+5 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag*2+38 ]
+# CHECK: Vreg: %89[ LoopTag+32 ]
+# CHECK: Vreg: %32[ LoopTag*3+79 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+21 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+22 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+8 ]
+# CHECK: Vreg: %91[ LoopTag+30 ]
+# CHECK: Vreg: %110[ LoopTag+2 ]
+# CHECK: Vreg: %117[ LoopTag+2 ]
+# CHECK: Vreg: %22[ LoopTag+49 ]
+# CHECK: Vreg: %3[ LoopTag*2+37 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*3+69 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+29 ]
+# CHECK: Vreg: %69[ LoopTag+26 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %102[ LoopTag+3 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+47 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+48 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+35 ]
+# CHECK: Vreg: %52[ LoopTag*3+43 ]
+# CHECK: Vreg: %33[ LoopTag*3+53 ]
+# CHECK: Vreg: %21:sub0[ LoopTag*2+45 ]
+# CHECK: Vreg: %21:sub1[ LoopTag*2+46 ]
+# CHECK: Vreg: %2[ LoopTag+31 ]
+# CHECK: Vreg: %35[ LoopTag+30 ]
+# CHECK: Vreg: %87:sub0[ LoopTag+7 ]
+# CHECK: Vreg: %4[ LoopTag*3+52 ]
+# CHECK: Vreg: %30[ LoopTag+25 ]
+# CHECK: Vreg: %101[ LoopTag+5 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag*2+38 ]
+# CHECK: Vreg: %89[ LoopTag+32 ]
+# CHECK: Vreg: %32[ LoopTag*3+79 ]
+# CHECK: Vreg: %20:sub0[ LoopTag+21 ]
+# CHECK: Vreg: %20:sub1[ LoopTag+22 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+8 ]
+# CHECK: Vreg: %91[ LoopTag+30 ]
+# CHECK: Vreg: %110[ LoopTag+2 ]
+# CHECK: Vreg: %117[ LoopTag+2 ]
+# CHECK: Vreg: %22[ LoopTag+49 ]
+# CHECK: Vreg: %3[ LoopTag*2+37 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*3+69 ]
+# CHECK: Vreg: %62:sub0[ LoopTag+29 ]
+# CHECK: Vreg: %69[ LoopTag+26 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %102[ LoopTag+3 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*3+47 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*3+48 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: %118:sreg_32 = S_MUL_I32 %35, %91
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %52[ LoopTag*2+45 ]
+# CHECK: Vreg: %33[ LoopTag*2+55 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+48 ]
+# CHECK: Vreg: %2[ 33 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %87:sub0[ 9 ]
+# CHECK: Vreg: %4[ LoopTag*2+54 ]
+# CHECK: Vreg: %30[ 27 ]
+# CHECK: Vreg: %94[ 5 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %63[ LoopTag+40 ]
+# CHECK: Vreg: %89[ 34 ]
+# CHECK: Vreg: %32[ LoopTag*2+81 ]
+# CHECK: Vreg: %20:sub0[ 23 ]
+# CHECK: Vreg: %20:sub1[ 24 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %22[ 51 ]
+# CHECK: Vreg: %3[ LoopTag+39 ]
+# CHECK: Vreg: %17[ LoopTag*2+71 ]
+# CHECK: Vreg: %62:sub0[ 31 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+49 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+50 ]
+# CHECK: Instr: %98:vgpr_32 = COPY killed %118
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %52[ LoopTag*2+44 ]
+# CHECK: Vreg: %33[ LoopTag*2+54 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+47 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %35[ 31 ]
+# CHECK: Vreg: %87:sub0[ 8 ]
+# CHECK: Vreg: %4[ LoopTag*2+53 ]
+# CHECK: Vreg: %30[ 26 ]
+# CHECK: Vreg: %94[ 4 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %63[ LoopTag+39 ]
+# CHECK: Vreg: %89[ 33 ]
+# CHECK: Vreg: %32[ LoopTag*2+80 ]
+# CHECK: Vreg: %20:sub0[ 22 ]
+# CHECK: Vreg: %20:sub1[ 23 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %22[ 50 ]
+# CHECK: Vreg: %3[ LoopTag+38 ]
+# CHECK: Vreg: %17[ LoopTag*2+70 ]
+# CHECK: Vreg: %62:sub0[ 30 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+48 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+49 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %18, %98, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %52[ LoopTag*2+43 ]
+# CHECK: Vreg: %33[ LoopTag*2+53 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+46 ]
+# CHECK: Vreg: %2[ 31 ]
+# CHECK: Vreg: %35[ 30 ]
+# CHECK: Vreg: %87:sub0[ 7 ]
+# CHECK: Vreg: %4[ LoopTag*2+52 ]
+# CHECK: Vreg: %30[ 25 ]
+# CHECK: Vreg: %94[ 3 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %63[ LoopTag+38 ]
+# CHECK: Vreg: %89[ 32 ]
+# CHECK: Vreg: %32[ LoopTag*2+79 ]
+# CHECK: Vreg: %20:sub0[ 21 ]
+# CHECK: Vreg: %20:sub1[ 22 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %91[ 1 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %22[ 49 ]
+# CHECK: Vreg: %3[ LoopTag+37 ]
+# CHECK: Vreg: %17[ LoopTag*2+69 ]
+# CHECK: Vreg: %62:sub0[ 29 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+47 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+48 ]
+# CHECK: Instr: %100:vgpr_32 = COPY %91, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %52[ LoopTag*2+42 ]
+# CHECK: Vreg: %33[ LoopTag*2+52 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+45 ]
+# CHECK: Vreg: %2[ 30 ]
+# CHECK: Vreg: %35[ 29 ]
+# CHECK: Vreg: %87:sub0[ 6 ]
+# CHECK: Vreg: %4[ LoopTag*2+51 ]
+# CHECK: Vreg: %30[ 24 ]
+# CHECK: Vreg: %94[ 2 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %63[ LoopTag+37 ]
+# CHECK: Vreg: %89[ 31 ]
+# CHECK: Vreg: %32[ LoopTag*2+78 ]
+# CHECK: Vreg: %20:sub0[ 20 ]
+# CHECK: Vreg: %20:sub1[ 21 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %22[ 48 ]
+# CHECK: Vreg: %3[ LoopTag+36 ]
+# CHECK: Vreg: %17[ LoopTag*2+68 ]
+# CHECK: Vreg: %62:sub0[ 28 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+46 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+47 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %52[ LoopTag*2+41 ]
+# CHECK: Vreg: %33[ LoopTag*2+51 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+44 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %35[ 28 ]
+# CHECK: Vreg: %87:sub0[ 5 ]
+# CHECK: Vreg: %4[ LoopTag*2+50 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %94[ 1 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %63[ LoopTag+36 ]
+# CHECK: Vreg: %89[ 30 ]
+# CHECK: Vreg: %32[ LoopTag*2+77 ]
+# CHECK: Vreg: %20:sub0[ 19 ]
+# CHECK: Vreg: %20:sub1[ 20 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %22[ 47 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+67 ]
+# CHECK: Vreg: %62:sub0[ 27 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+45 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+46 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %52[ LoopTag*2+41 ]
+# CHECK: Vreg: %33[ LoopTag*2+51 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+44 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %35[ 28 ]
+# CHECK: Vreg: %87:sub0[ 5 ]
+# CHECK: Vreg: %4[ LoopTag*2+50 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %94[ 1 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %63[ LoopTag+36 ]
+# CHECK: Vreg: %89[ 30 ]
+# CHECK: Vreg: %32[ LoopTag*2+77 ]
+# CHECK: Vreg: %20:sub0[ 19 ]
+# CHECK: Vreg: %20:sub1[ 20 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %22[ 47 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+67 ]
+# CHECK: Vreg: %62:sub0[ 27 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+45 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+46 ]
+# CHECK: --- MBB_9 ---
+# CHECK: Instr: SI_END_CF killed %112, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %52[ LoopTag*2+42 ]
+# CHECK: Vreg: %33[ LoopTag*2+52 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+45 ]
+# CHECK: Vreg: %2[ 30 ]
+# CHECK: Vreg: %35[ 29 ]
+# CHECK: Vreg: %87:sub0[ 6 ]
+# CHECK: Vreg: %4[ LoopTag*2+51 ]
+# CHECK: Vreg: %30[ 24 ]
+# CHECK: Vreg: %101[ 4 ]
+# CHECK: Vreg: %18[ 39 ]
+# CHECK: Vreg: %63[ LoopTag+37 ]
+# CHECK: Vreg: %89[ 31 ]
+# CHECK: Vreg: %32[ LoopTag*2+78 ]
+# CHECK: Vreg: %20:sub0[ 20 ]
+# CHECK: Vreg: %20:sub1[ 21 ]
+# CHECK: Vreg: %1[ 47 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %91[ 29 ]
+# CHECK: Vreg: %110[ 1 ]
+# CHECK: Vreg: %117[ 1 ]
+# CHECK: Vreg: %22[ 48 ]
+# CHECK: Vreg: %3[ LoopTag+36 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+68 ]
+# CHECK: Vreg: %62:sub0[ 28 ]
+# CHECK: Vreg: %69[ 25 ]
+# CHECK: Vreg: %102[ 2 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+46 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+47 ]
+# CHECK: Instr: %106:vgpr_32 = V_MUL_LO_U32_e64 %110, killed %117, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %52[ LoopTag*2+41 ]
+# CHECK: Vreg: %33[ LoopTag*2+51 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+44 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %35[ 28 ]
+# CHECK: Vreg: %87:sub0[ 5 ]
+# CHECK: Vreg: %4[ LoopTag*2+50 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %101[ 3 ]
+# CHECK: Vreg: %18[ 38 ]
+# CHECK: Vreg: %63[ LoopTag+36 ]
+# CHECK: Vreg: %89[ 30 ]
+# CHECK: Vreg: %32[ LoopTag*2+77 ]
+# CHECK: Vreg: %20:sub0[ 19 ]
+# CHECK: Vreg: %20:sub1[ 20 ]
+# CHECK: Vreg: %1[ 46 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %91[ 28 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %22[ 47 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %17[ LoopTag*2+67 ]
+# CHECK: Vreg: %62:sub0[ 27 ]
+# CHECK: Vreg: %69[ 24 ]
+# CHECK: Vreg: %102[ 1 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+45 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+46 ]
+# CHECK: Instr: %108:vgpr_32 = COPY killed %102, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %52[ LoopTag*2+40 ]
+# CHECK: Vreg: %33[ LoopTag*2+50 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+43 ]
+# CHECK: Vreg: %2[ 28 ]
+# CHECK: Vreg: %35[ 27 ]
+# CHECK: Vreg: %106[ 1 ]
+# CHECK: Vreg: %87:sub0[ 4 ]
+# CHECK: Vreg: %4[ LoopTag*2+49 ]
+# CHECK: Vreg: %30[ 22 ]
+# CHECK: Vreg: %101[ 2 ]
+# CHECK: Vreg: %18[ 37 ]
+# CHECK: Vreg: %63[ LoopTag+35 ]
+# CHECK: Vreg: %89[ 29 ]
+# CHECK: Vreg: %32[ LoopTag*2+76 ]
+# CHECK: Vreg: %20:sub0[ 18 ]
+# CHECK: Vreg: %20:sub1[ 19 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %91[ 27 ]
+# CHECK: Vreg: %110[ 1 ]
+# CHECK: Vreg: %22[ 46 ]
+# CHECK: Vreg: %3[ LoopTag+34 ]
+# CHECK: Vreg: %17[ LoopTag*2+66 ]
+# CHECK: Vreg: %62:sub0[ 26 ]
+# CHECK: Vreg: %69[ 23 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+44 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+45 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %52[ LoopTag*2+39 ]
+# CHECK: Vreg: %33[ LoopTag*2+49 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+42 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %35[ 26 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %87:sub0[ 3 ]
+# CHECK: Vreg: %4[ LoopTag*2+48 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %18[ 36 ]
+# CHECK: Vreg: %63[ LoopTag+34 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %89[ 28 ]
+# CHECK: Vreg: %32[ LoopTag*2+75 ]
+# CHECK: Vreg: %20:sub0[ 17 ]
+# CHECK: Vreg: %20:sub1[ 18 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %91[ 26 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %22[ 45 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %17[ LoopTag*2+65 ]
+# CHECK: Vreg: %62:sub0[ 25 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+43 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+44 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %52[ LoopTag*2+39 ]
+# CHECK: Vreg: %33[ LoopTag*2+49 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+42 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %35[ 26 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %87:sub0[ 3 ]
+# CHECK: Vreg: %4[ LoopTag*2+48 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %18[ 36 ]
+# CHECK: Vreg: %63[ LoopTag+34 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %89[ 28 ]
+# CHECK: Vreg: %32[ LoopTag*2+75 ]
+# CHECK: Vreg: %20:sub0[ 17 ]
+# CHECK: Vreg: %20:sub1[ 18 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %91[ 26 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %22[ 45 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %17[ LoopTag*2+65 ]
+# CHECK: Vreg: %62:sub0[ 25 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+43 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+44 ]
+# CHECK: --- MBB_10 ---
+# CHECK: Instr: %119:vgpr_32 = V_MUL_HI_U32_e64 %109, %87.sub0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+36 ]
+# CHECK: Vreg: %33[ LoopTag*2+46 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+39 ]
+# CHECK: Vreg: %2[ 24 ]
+# CHECK: Vreg: %35[ 23 ]
+# CHECK: Vreg: %87:sub0[ 0 ]
+# CHECK: Vreg: %4[ LoopTag*2+45 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %18[ 33 ]
+# CHECK: Vreg: %63[ LoopTag+31 ]
+# CHECK: Vreg: %89[ 25 ]
+# CHECK: Vreg: %32[ LoopTag*2+72 ]
+# CHECK: Vreg: %20:sub0[ 14 ]
+# CHECK: Vreg: %20:sub1[ 15 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %91[ 23 ]
+# CHECK: Vreg: %22[ 42 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %17[ LoopTag*2+62 ]
+# CHECK: Vreg: %62:sub0[ 22 ]
+# CHECK: Vreg: %107[ 18 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %38[ LoopTag*2+48 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+40 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+41 ]
+# CHECK: Instr: %120:vgpr_32 = V_MUL_LO_U32_e64 %119, %65, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %52[ LoopTag*2+35 ]
+# CHECK: Vreg: %33[ LoopTag*2+45 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %35[ 22 ]
+# CHECK: Vreg: %87:sub0[ 34 ]
+# CHECK: Vreg: %4[ LoopTag*2+44 ]
+# CHECK: Vreg: %30[ 17 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %63[ LoopTag+30 ]
+# CHECK: Vreg: %89[ 24 ]
+# CHECK: Vreg: %32[ LoopTag*2+71 ]
+# CHECK: Vreg: %20:sub0[ 13 ]
+# CHECK: Vreg: %20:sub1[ 14 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %91[ 22 ]
+# CHECK: Vreg: %22[ 41 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+61 ]
+# CHECK: Vreg: %62:sub0[ 21 ]
+# CHECK: Vreg: %107[ 17 ]
+# CHECK: Vreg: %69[ 18 ]
+# CHECK: Vreg: %38[ LoopTag*2+47 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+39 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+40 ]
+# CHECK: Instr: %121:vgpr_32 = V_SUB_U32_e64 %109, killed %120, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+34 ]
+# CHECK: Vreg: %33[ LoopTag*2+44 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+36 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+37 ]
+# CHECK: Vreg: %2[ 22 ]
+# CHECK: Vreg: %35[ 21 ]
+# CHECK: Vreg: %87:sub0[ 33 ]
+# CHECK: Vreg: %4[ LoopTag*2+43 ]
+# CHECK: Vreg: %30[ 16 ]
+# CHECK: Vreg: %120[ 0 ]
+# CHECK: Vreg: %18[ 31 ]
+# CHECK: Vreg: %63[ LoopTag+29 ]
+# CHECK: Vreg: %89[ 23 ]
+# CHECK: Vreg: %32[ LoopTag*2+70 ]
+# CHECK: Vreg: %20:sub0[ 12 ]
+# CHECK: Vreg: %20:sub1[ 13 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %91[ 21 ]
+# CHECK: Vreg: %22[ 40 ]
+# CHECK: Vreg: %3[ LoopTag+28 ]
+# CHECK: Vreg: %119[ 2 ]
+# CHECK: Vreg: %17[ LoopTag*2+60 ]
+# CHECK: Vreg: %62:sub0[ 20 ]
+# CHECK: Vreg: %107[ 16 ]
+# CHECK: Vreg: %69[ 17 ]
+# CHECK: Vreg: %38[ LoopTag*2+46 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+38 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+39 ]
+# CHECK: Instr: %122:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %65, %121, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %109[ 19 ]
+# CHECK: Vreg: %52[ LoopTag*2+33 ]
+# CHECK: Vreg: %33[ LoopTag*2+43 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+35 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+36 ]
+# CHECK: Vreg: %2[ 21 ]
+# CHECK: Vreg: %35[ 20 ]
+# CHECK: Vreg: %87:sub0[ 32 ]
+# CHECK: Vreg: %4[ LoopTag*2+42 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %18[ 30 ]
+# CHECK: Vreg: %63[ LoopTag+28 ]
+# CHECK: Vreg: %89[ 22 ]
+# CHECK: Vreg: %32[ LoopTag*2+69 ]
+# CHECK: Vreg: %20:sub0[ 11 ]
+# CHECK: Vreg: %20:sub1[ 12 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %91[ 20 ]
+# CHECK: Vreg: %22[ 39 ]
+# CHECK: Vreg: %3[ LoopTag+27 ]
+# CHECK: Vreg: %119[ 1 ]
+# CHECK: Vreg: %17[ LoopTag*2+59 ]
+# CHECK: Vreg: %62:sub0[ 19 ]
+# CHECK: Vreg: %107[ 15 ]
+# CHECK: Vreg: %69[ 16 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %38[ LoopTag*2+45 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+37 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+38 ]
+# CHECK: Instr: %123:vgpr_32 = V_ADD_U32_e64 1, %119, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %109[ 18 ]
+# CHECK: Vreg: %52[ LoopTag*2+32 ]
+# CHECK: Vreg: %33[ LoopTag*2+42 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+34 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+35 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %35[ 19 ]
+# CHECK: Vreg: %87:sub0[ 31 ]
+# CHECK: Vreg: %4[ LoopTag*2+41 ]
+# CHECK: Vreg: %30[ 14 ]
+# CHECK: Vreg: %18[ 29 ]
+# CHECK: Vreg: %63[ LoopTag+27 ]
+# CHECK: Vreg: %89[ 21 ]
+# CHECK: Vreg: %32[ LoopTag*2+68 ]
+# CHECK: Vreg: %122[ 1 ]
+# CHECK: Vreg: %20:sub0[ 10 ]
+# CHECK: Vreg: %20:sub1[ 11 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %91[ 19 ]
+# CHECK: Vreg: %22[ 38 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+58 ]
+# CHECK: Vreg: %62:sub0[ 18 ]
+# CHECK: Vreg: %107[ 14 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %121[ 2 ]
+# CHECK: Vreg: %38[ LoopTag*2+44 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+36 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+37 ]
+# CHECK: Instr: %124:vgpr_32 = V_CNDMASK_B32_e64 0, killed %119, 0, killed %123, %122, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %109[ 17 ]
+# CHECK: Vreg: %52[ LoopTag*2+31 ]
+# CHECK: Vreg: %33[ LoopTag*2+41 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+33 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+34 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %35[ 18 ]
+# CHECK: Vreg: %87:sub0[ 30 ]
+# CHECK: Vreg: %4[ LoopTag*2+40 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %18[ 28 ]
+# CHECK: Vreg: %63[ LoopTag+26 ]
+# CHECK: Vreg: %89[ 20 ]
+# CHECK: Vreg: %32[ LoopTag*2+67 ]
+# CHECK: Vreg: %122[ 0 ]
+# CHECK: Vreg: %20:sub0[ 9 ]
+# CHECK: Vreg: %20:sub1[ 10 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %91[ 18 ]
+# CHECK: Vreg: %22[ 37 ]
+# CHECK: Vreg: %3[ LoopTag+25 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+57 ]
+# CHECK: Vreg: %62:sub0[ 17 ]
+# CHECK: Vreg: %107[ 13 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %121[ 1 ]
+# CHECK: Vreg: %38[ LoopTag*2+43 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+35 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+36 ]
+# CHECK: Instr: %125:vgpr_32 = V_SUBREV_U32_e64 %65, %121, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %109[ 16 ]
+# CHECK: Vreg: %52[ LoopTag*2+30 ]
+# CHECK: Vreg: %33[ LoopTag*2+40 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+32 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+33 ]
+# CHECK: Vreg: %2[ 18 ]
+# CHECK: Vreg: %35[ 17 ]
+# CHECK: Vreg: %87:sub0[ 29 ]
+# CHECK: Vreg: %4[ LoopTag*2+39 ]
+# CHECK: Vreg: %30[ 12 ]
+# CHECK: Vreg: %18[ 27 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %89[ 19 ]
+# CHECK: Vreg: %32[ LoopTag*2+66 ]
+# CHECK: Vreg: %122[ 1 ]
+# CHECK: Vreg: %20:sub0[ 8 ]
+# CHECK: Vreg: %20:sub1[ 9 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %91[ 17 ]
+# CHECK: Vreg: %124[ 3 ]
+# CHECK: Vreg: %22[ 36 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %17[ LoopTag*2+56 ]
+# CHECK: Vreg: %62:sub0[ 16 ]
+# CHECK: Vreg: %107[ 12 ]
+# CHECK: Vreg: %69[ 13 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %38[ LoopTag*2+42 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+34 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+35 ]
+# CHECK: Instr: %126:vgpr_32 = V_CNDMASK_B32_e64 0, killed %121, 0, killed %125, killed %122, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %109[ 15 ]
+# CHECK: Vreg: %52[ LoopTag*2+29 ]
+# CHECK: Vreg: %33[ LoopTag*2+39 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+31 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+32 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %35[ 16 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %87:sub0[ 28 ]
+# CHECK: Vreg: %4[ LoopTag*2+38 ]
+# CHECK: Vreg: %30[ 11 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %63[ LoopTag+24 ]
+# CHECK: Vreg: %89[ 18 ]
+# CHECK: Vreg: %32[ LoopTag*2+65 ]
+# CHECK: Vreg: %122[ 0 ]
+# CHECK: Vreg: %20:sub0[ 7 ]
+# CHECK: Vreg: %20:sub1[ 8 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %91[ 16 ]
+# CHECK: Vreg: %124[ 2 ]
+# CHECK: Vreg: %22[ 35 ]
+# CHECK: Vreg: %3[ LoopTag+23 ]
+# CHECK: Vreg: %17[ LoopTag*2+55 ]
+# CHECK: Vreg: %62:sub0[ 15 ]
+# CHECK: Vreg: %107[ 11 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %38[ LoopTag*2+41 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+33 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+34 ]
+# CHECK: Instr: %127:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %65, killed %126, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %109[ 14 ]
+# CHECK: Vreg: %52[ LoopTag*2+28 ]
+# CHECK: Vreg: %33[ LoopTag*2+38 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+30 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+31 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %35[ 15 ]
+# CHECK: Vreg: %87:sub0[ 27 ]
+# CHECK: Vreg: %4[ LoopTag*2+37 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %63[ LoopTag+23 ]
+# CHECK: Vreg: %89[ 17 ]
+# CHECK: Vreg: %32[ LoopTag*2+64 ]
+# CHECK: Vreg: %20:sub0[ 6 ]
+# CHECK: Vreg: %20:sub1[ 7 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %91[ 15 ]
+# CHECK: Vreg: %124[ 1 ]
+# CHECK: Vreg: %22[ 34 ]
+# CHECK: Vreg: %3[ LoopTag+22 ]
+# CHECK: Vreg: %17[ LoopTag*2+54 ]
+# CHECK: Vreg: %62:sub0[ 14 ]
+# CHECK: Vreg: %107[ 10 ]
+# CHECK: Vreg: %69[ 11 ]
+# CHECK: Vreg: %126[ 0 ]
+# CHECK: Vreg: %38[ LoopTag*2+40 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+32 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+33 ]
+# CHECK: Instr: %128:vgpr_32 = V_ADD_U32_e64 1, %124, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %109[ 13 ]
+# CHECK: Vreg: %52[ LoopTag*2+27 ]
+# CHECK: Vreg: %33[ LoopTag*2+37 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+29 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+30 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %35[ 14 ]
+# CHECK: Vreg: %87:sub0[ 26 ]
+# CHECK: Vreg: %4[ LoopTag*2+36 ]
+# CHECK: Vreg: %30[ 9 ]
+# CHECK: Vreg: %18[ 24 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %127[ 1 ]
+# CHECK: Vreg: %89[ 16 ]
+# CHECK: Vreg: %32[ LoopTag*2+63 ]
+# CHECK: Vreg: %20:sub0[ 5 ]
+# CHECK: Vreg: %20:sub1[ 6 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %65[ 24 ]
+# CHECK: Vreg: %91[ 14 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %22[ 33 ]
+# CHECK: Vreg: %3[ LoopTag+21 ]
+# CHECK: Vreg: %17[ LoopTag*2+53 ]
+# CHECK: Vreg: %62:sub0[ 13 ]
+# CHECK: Vreg: %107[ 9 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %38[ LoopTag*2+39 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+31 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+32 ]
+# CHECK: Instr: %129:vgpr_32 = V_CNDMASK_B32_e64 0, killed %124, 0, killed %128, killed %127, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %109[ 12 ]
+# CHECK: Vreg: %128[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+26 ]
+# CHECK: Vreg: %33[ LoopTag*2+36 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+28 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+29 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %35[ 13 ]
+# CHECK: Vreg: %87:sub0[ 25 ]
+# CHECK: Vreg: %4[ LoopTag*2+35 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %89[ 15 ]
+# CHECK: Vreg: %32[ LoopTag*2+62 ]
+# CHECK: Vreg: %20:sub0[ 4 ]
+# CHECK: Vreg: %20:sub1[ 5 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %65[ 23 ]
+# CHECK: Vreg: %91[ 13 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %22[ 32 ]
+# CHECK: Vreg: %3[ LoopTag+20 ]
+# CHECK: Vreg: %17[ LoopTag*2+52 ]
+# CHECK: Vreg: %62:sub0[ 12 ]
+# CHECK: Vreg: %107[ 8 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %38[ LoopTag*2+38 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+30 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+31 ]
+# CHECK: Instr: %130:vgpr_32 = V_ASHRREV_I32_e64 31, %129, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %109[ 11 ]
+# CHECK: Vreg: %52[ LoopTag*2+25 ]
+# CHECK: Vreg: %33[ LoopTag*2+35 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+27 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+28 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %35[ 12 ]
+# CHECK: Vreg: %87:sub0[ 24 ]
+# CHECK: Vreg: %4[ LoopTag*2+34 ]
+# CHECK: Vreg: %30[ 7 ]
+# CHECK: Vreg: %18[ 22 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %89[ 14 ]
+# CHECK: Vreg: %32[ LoopTag*2+61 ]
+# CHECK: Vreg: %20:sub0[ 3 ]
+# CHECK: Vreg: %20:sub1[ 4 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %65[ 22 ]
+# CHECK: Vreg: %91[ 12 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %22[ 31 ]
+# CHECK: Vreg: %3[ LoopTag+19 ]
+# CHECK: Vreg: %17[ LoopTag*2+51 ]
+# CHECK: Vreg: %62:sub0[ 11 ]
+# CHECK: Vreg: %107[ 7 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %38[ LoopTag*2+37 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+29 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+30 ]
+# CHECK: Instr: %131:vreg_64 = REG_SEQUENCE %129, %subreg.sub0, killed %130, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %109[ 10 ]
+# CHECK: Vreg: %52[ LoopTag*2+24 ]
+# CHECK: Vreg: %33[ LoopTag*2+34 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+26 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+27 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %130[ 0 ]
+# CHECK: Vreg: %35[ 11 ]
+# CHECK: Vreg: %87:sub0[ 23 ]
+# CHECK: Vreg: %4[ LoopTag*2+33 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %18[ 21 ]
+# CHECK: Vreg: %63[ LoopTag+19 ]
+# CHECK: Vreg: %89[ 13 ]
+# CHECK: Vreg: %32[ LoopTag*2+60 ]
+# CHECK: Vreg: %20:sub0[ 2 ]
+# CHECK: Vreg: %20:sub1[ 3 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %65[ 21 ]
+# CHECK: Vreg: %91[ 11 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %22[ 30 ]
+# CHECK: Vreg: %3[ LoopTag+18 ]
+# CHECK: Vreg: %17[ LoopTag*2+50 ]
+# CHECK: Vreg: %62:sub0[ 10 ]
+# CHECK: Vreg: %107[ 6 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %38[ LoopTag*2+36 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+28 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+29 ]
+# CHECK: Instr: %132:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %131, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %109[ 9 ]
+# CHECK: Vreg: %52[ LoopTag*2+23 ]
+# CHECK: Vreg: %33[ LoopTag*2+33 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+25 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+26 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %35[ 10 ]
+# CHECK: Vreg: %87:sub0[ 22 ]
+# CHECK: Vreg: %4[ LoopTag*2+32 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ LoopTag+18 ]
+# CHECK: Vreg: %89[ 12 ]
+# CHECK: Vreg: %32[ LoopTag*2+59 ]
+# CHECK: Vreg: %20:sub0[ 1 ]
+# CHECK: Vreg: %20:sub1[ 2 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %65[ 20 ]
+# CHECK: Vreg: %91[ 10 ]
+# CHECK: Vreg: %129[ 8 ]
+# CHECK: Vreg: %22[ 29 ]
+# CHECK: Vreg: %3[ LoopTag+17 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+49 ]
+# CHECK: Vreg: %62:sub0[ 9 ]
+# CHECK: Vreg: %107[ 5 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %38[ LoopTag*2+35 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+27 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+28 ]
+# CHECK: Instr: %133:vgpr_32, %134:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %20.sub0, %132.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %109[ 8 ]
+# CHECK: Vreg: %52[ LoopTag*2+22 ]
+# CHECK: Vreg: %33[ LoopTag*2+32 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+24 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+25 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %35[ 9 ]
+# CHECK: Vreg: %87:sub0[ 21 ]
+# CHECK: Vreg: %4[ LoopTag*2+31 ]
+# CHECK: Vreg: %132:sub0[ 0 ]
+# CHECK: Vreg: %132:sub1[ 1 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %18[ 19 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %89[ 11 ]
+# CHECK: Vreg: %32[ LoopTag*2+58 ]
+# CHECK: Vreg: %20:sub0[ 0 ]
+# CHECK: Vreg: %20:sub1[ 1 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %65[ 19 ]
+# CHECK: Vreg: %91[ 9 ]
+# CHECK: Vreg: %129[ 7 ]
+# CHECK: Vreg: %22[ 28 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %17[ LoopTag*2+48 ]
+# CHECK: Vreg: %62:sub0[ 8 ]
+# CHECK: Vreg: %107[ 4 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %38[ LoopTag*2+34 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+26 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+27 ]
+# CHECK: Instr: %135:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %20.sub1, killed %132.sub1, killed %134, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %109[ 7 ]
+# CHECK: Vreg: %52[ LoopTag*2+21 ]
+# CHECK: Vreg: %33[ LoopTag*2+31 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+23 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+24 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %35[ 8 ]
+# CHECK: Vreg: %87:sub0[ 20 ]
+# CHECK: Vreg: %4[ LoopTag*2+30 ]
+# CHECK: Vreg: %132:sub1[ 0 ]
+# CHECK: Vreg: %30[ 3 ]
+# CHECK: Vreg: %18[ 18 ]
+# CHECK: Vreg: %63[ LoopTag+16 ]
+# CHECK: Vreg: %89[ 10 ]
+# CHECK: Vreg: %134[ 0 ]
+# CHECK: Vreg: %32[ LoopTag*2+57 ]
+# CHECK: Vreg: %20:sub1[ 0 ]
+# CHECK: Vreg: %20:sub0[ 21 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %65[ 18 ]
+# CHECK: Vreg: %91[ 8 ]
+# CHECK: Vreg: %129[ 6 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %3[ LoopTag+15 ]
+# CHECK: Vreg: %17[ LoopTag*2+47 ]
+# CHECK: Vreg: %62:sub0[ 7 ]
+# CHECK: Vreg: %107[ 3 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %133[ 1 ]
+# CHECK: Vreg: %38[ LoopTag*2+33 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+25 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+26 ]
+# CHECK: Instr: %136:vreg_64 = REG_SEQUENCE killed %133, %subreg.sub0, killed %135, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %109[ 6 ]
+# CHECK: Vreg: %135[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+20 ]
+# CHECK: Vreg: %33[ LoopTag*2+30 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+22 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+23 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %35[ 7 ]
+# CHECK: Vreg: %87:sub0[ 19 ]
+# CHECK: Vreg: %4[ LoopTag*2+29 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %18[ 17 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %89[ 9 ]
+# CHECK: Vreg: %32[ LoopTag*2+56 ]
+# CHECK: Vreg: %20:sub0[ 20 ]
+# CHECK: Vreg: %20:sub1[ 21 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %91[ 7 ]
+# CHECK: Vreg: %129[ 5 ]
+# CHECK: Vreg: %22[ 26 ]
+# CHECK: Vreg: %3[ LoopTag+14 ]
+# CHECK: Vreg: %17[ LoopTag*2+46 ]
+# CHECK: Vreg: %62:sub0[ 6 ]
+# CHECK: Vreg: %107[ 2 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %38[ LoopTag*2+32 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+24 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+25 ]
+# CHECK: Instr: %137:vgpr_32 = GLOBAL_LOAD_DWORD killed %136, 0, 0, implicit $exec :: (load (s32) from %ir.gep3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %109[ 5 ]
+# CHECK: Vreg: %52[ LoopTag*2+19 ]
+# CHECK: Vreg: %33[ LoopTag*2+29 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+21 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+22 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %35[ 6 ]
+# CHECK: Vreg: %87:sub0[ 18 ]
+# CHECK: Vreg: %4[ LoopTag*2+28 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %18[ 16 ]
+# CHECK: Vreg: %63[ LoopTag+14 ]
+# CHECK: Vreg: %89[ 8 ]
+# CHECK: Vreg: %32[ LoopTag*2+55 ]
+# CHECK: Vreg: %20:sub0[ 19 ]
+# CHECK: Vreg: %20:sub1[ 20 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %91[ 6 ]
+# CHECK: Vreg: %129[ 4 ]
+# CHECK: Vreg: %136[ 0 ]
+# CHECK: Vreg: %22[ 25 ]
+# CHECK: Vreg: %3[ LoopTag+13 ]
+# CHECK: Vreg: %17[ LoopTag*2+45 ]
+# CHECK: Vreg: %62:sub0[ 5 ]
+# CHECK: Vreg: %107[ 1 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %38[ LoopTag*2+31 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+23 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+24 ]
+# CHECK: Instr: %138:vgpr_32 = V_ADD_U32_e64 %107, %30, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %109[ 4 ]
+# CHECK: Vreg: %52[ LoopTag*2+18 ]
+# CHECK: Vreg: %33[ LoopTag*2+28 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+20 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+21 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %137[ 3 ]
+# CHECK: Vreg: %35[ 5 ]
+# CHECK: Vreg: %87:sub0[ 17 ]
+# CHECK: Vreg: %4[ LoopTag*2+27 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18[ 15 ]
+# CHECK: Vreg: %63[ LoopTag+13 ]
+# CHECK: Vreg: %89[ 7 ]
+# CHECK: Vreg: %32[ LoopTag*2+54 ]
+# CHECK: Vreg: %20:sub0[ 18 ]
+# CHECK: Vreg: %20:sub1[ 19 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %91[ 5 ]
+# CHECK: Vreg: %129[ 3 ]
+# CHECK: Vreg: %22[ 24 ]
+# CHECK: Vreg: %3[ LoopTag+12 ]
+# CHECK: Vreg: %17[ LoopTag*2+44 ]
+# CHECK: Vreg: %62:sub0[ 4 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %38[ LoopTag*2+30 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+22 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+23 ]
+# CHECK: Instr: %139:sreg_32 = V_CMP_LT_U32_e64 killed %138, %69, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %109[ 3 ]
+# CHECK: Vreg: %52[ LoopTag*2+17 ]
+# CHECK: Vreg: %33[ LoopTag*2+27 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+19 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+20 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %137[ 2 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %87:sub0[ 16 ]
+# CHECK: Vreg: %4[ LoopTag*2+26 ]
+# CHECK: Vreg: %30[ 34 ]
+# CHECK: Vreg: %18[ 14 ]
+# CHECK: Vreg: %63[ LoopTag+12 ]
+# CHECK: Vreg: %89[ 6 ]
+# CHECK: Vreg: %32[ LoopTag*2+53 ]
+# CHECK: Vreg: %20:sub0[ 17 ]
+# CHECK: Vreg: %20:sub1[ 18 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %91[ 4 ]
+# CHECK: Vreg: %129[ 2 ]
+# CHECK: Vreg: %22[ 23 ]
+# CHECK: Vreg: %3[ LoopTag+11 ]
+# CHECK: Vreg: %138[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+43 ]
+# CHECK: Vreg: %62:sub0[ 3 ]
+# CHECK: Vreg: %107[ 2 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %38[ LoopTag*2+29 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+21 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+22 ]
+# CHECK: Instr: %140:sreg_32 = SI_IF killed %139, %bb.12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %109[ 2 ]
+# CHECK: Vreg: %52[ LoopTag*2+16 ]
+# CHECK: Vreg: %33[ LoopTag*2+26 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+18 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+19 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %137[ 1 ]
+# CHECK: Vreg: %35[ 3 ]
+# CHECK: Vreg: %87:sub0[ 15 ]
+# CHECK: Vreg: %4[ LoopTag*2+25 ]
+# CHECK: Vreg: %30[ 33 ]
+# CHECK: Vreg: %139[ 0 ]
+# CHECK: Vreg: %18[ 13 ]
+# CHECK: Vreg: %63[ LoopTag+11 ]
+# CHECK: Vreg: %89[ 5 ]
+# CHECK: Vreg: %32[ LoopTag*2+52 ]
+# CHECK: Vreg: %20:sub0[ 16 ]
+# CHECK: Vreg: %20:sub1[ 17 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %22[ 22 ]
+# CHECK: Vreg: %3[ LoopTag+10 ]
+# CHECK: Vreg: %17[ LoopTag*2+42 ]
+# CHECK: Vreg: %62:sub0[ 2 ]
+# CHECK: Vreg: %107[ 1 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %38[ LoopTag*2+28 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+20 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+21 ]
+# CHECK: Instr: S_BRANCH %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %52[ LoopTag*2+15 ]
+# CHECK: Vreg: %33[ LoopTag*2+25 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+17 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+18 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %137[ 0 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %87:sub0[ 14 ]
+# CHECK: Vreg: %4[ LoopTag*2+24 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+10 ]
+# CHECK: Vreg: %89[ 4 ]
+# CHECK: Vreg: %32[ LoopTag*2+51 ]
+# CHECK: Vreg: %20:sub0[ 15 ]
+# CHECK: Vreg: %20:sub1[ 16 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %22[ 21 ]
+# CHECK: Vreg: %3[ LoopTag+9 ]
+# CHECK: Vreg: %17[ LoopTag*2+41 ]
+# CHECK: Vreg: %62:sub0[ 1 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %69[ 21 ]
+# CHECK: Vreg: %140[ 1 ]
+# CHECK: Vreg: %38[ LoopTag*2+27 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+19 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+20 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %52[ LoopTag*2+15 ]
+# CHECK: Vreg: %33[ LoopTag*2+25 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+17 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+18 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %137[ 0 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %87:sub0[ 14 ]
+# CHECK: Vreg: %4[ LoopTag*2+24 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+10 ]
+# CHECK: Vreg: %89[ 4 ]
+# CHECK: Vreg: %32[ LoopTag*2+51 ]
+# CHECK: Vreg: %20:sub0[ 15 ]
+# CHECK: Vreg: %20:sub1[ 16 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %22[ 21 ]
+# CHECK: Vreg: %3[ LoopTag+9 ]
+# CHECK: Vreg: %17[ LoopTag*2+41 ]
+# CHECK: Vreg: %62:sub0[ 1 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %69[ 21 ]
+# CHECK: Vreg: %140[ 1 ]
+# CHECK: Vreg: %38[ LoopTag*2+27 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+19 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+20 ]
+# CHECK: --- MBB_11 ---
+# CHECK: Instr: %141:vgpr_32 = V_MUL_HI_U32_e64 %109, %62.sub0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+35 ]
+# CHECK: Vreg: %33[ LoopTag*2+45 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %87:sub0[ 34 ]
+# CHECK: Vreg: %4[ LoopTag*2+44 ]
+# CHECK: Vreg: %30[ 52 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %63[ LoopTag+30 ]
+# CHECK: Vreg: %89[ 24 ]
+# CHECK: Vreg: %32[ LoopTag*2+71 ]
+# CHECK: Vreg: %20:sub0[ 14 ]
+# CHECK: Vreg: %20:sub1[ 15 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %65[ 32 ]
+# CHECK: Vreg: %91[ 22 ]
+# CHECK: Vreg: %22[ 20 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %17[ LoopTag*2+61 ]
+# CHECK: Vreg: %62:sub0[ 0 ]
+# CHECK: Vreg: %69[ 20 ]
+# CHECK: Vreg: %140[ 21 ]
+# CHECK: Vreg: %38[ LoopTag*2+47 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+39 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+40 ]
+# CHECK: Instr: %142:vgpr_32 = V_MUL_LO_U32_e64 %141, %35, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %52[ LoopTag*2+34 ]
+# CHECK: Vreg: %33[ LoopTag*2+44 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+36 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+37 ]
+# CHECK: Vreg: %2[ 22 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %87:sub0[ 33 ]
+# CHECK: Vreg: %4[ LoopTag*2+43 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %18[ 31 ]
+# CHECK: Vreg: %63[ LoopTag+29 ]
+# CHECK: Vreg: %89[ 23 ]
+# CHECK: Vreg: %32[ LoopTag*2+70 ]
+# CHECK: Vreg: %141[ 0 ]
+# CHECK: Vreg: %20:sub0[ 13 ]
+# CHECK: Vreg: %20:sub1[ 14 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 31 ]
+# CHECK: Vreg: %91[ 21 ]
+# CHECK: Vreg: %22[ 19 ]
+# CHECK: Vreg: %3[ LoopTag+28 ]
+# CHECK: Vreg: %17[ LoopTag*2+60 ]
+# CHECK: Vreg: %62:sub0[ 55 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %140[ 20 ]
+# CHECK: Vreg: %38[ LoopTag*2+46 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+38 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+39 ]
+# CHECK: Instr: %143:vgpr_32 = V_SUB_U32_e64 killed %109, killed %142, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+33 ]
+# CHECK: Vreg: %33[ LoopTag*2+43 ]
+# CHECK: Vreg: %142[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+35 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+36 ]
+# CHECK: Vreg: %2[ 21 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %87:sub0[ 32 ]
+# CHECK: Vreg: %4[ LoopTag*2+42 ]
+# CHECK: Vreg: %30[ 50 ]
+# CHECK: Vreg: %18[ 30 ]
+# CHECK: Vreg: %63[ LoopTag+28 ]
+# CHECK: Vreg: %89[ 22 ]
+# CHECK: Vreg: %32[ LoopTag*2+69 ]
+# CHECK: Vreg: %141[ 2 ]
+# CHECK: Vreg: %20:sub0[ 12 ]
+# CHECK: Vreg: %20:sub1[ 13 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %65[ 30 ]
+# CHECK: Vreg: %91[ 20 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %3[ LoopTag+27 ]
+# CHECK: Vreg: %17[ LoopTag*2+59 ]
+# CHECK: Vreg: %62:sub0[ 54 ]
+# CHECK: Vreg: %69[ 18 ]
+# CHECK: Vreg: %140[ 19 ]
+# CHECK: Vreg: %38[ LoopTag*2+45 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+37 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+38 ]
+# CHECK: Instr: %144:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %35, %143, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %52[ LoopTag*2+32 ]
+# CHECK: Vreg: %33[ LoopTag*2+42 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+34 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+35 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %87:sub0[ 31 ]
+# CHECK: Vreg: %4[ LoopTag*2+41 ]
+# CHECK: Vreg: %30[ 49 ]
+# CHECK: Vreg: %18[ 29 ]
+# CHECK: Vreg: %63[ LoopTag+27 ]
+# CHECK: Vreg: %89[ 21 ]
+# CHECK: Vreg: %32[ LoopTag*2+68 ]
+# CHECK: Vreg: %141[ 1 ]
+# CHECK: Vreg: %20:sub0[ 11 ]
+# CHECK: Vreg: %20:sub1[ 12 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %65[ 29 ]
+# CHECK: Vreg: %91[ 19 ]
+# CHECK: Vreg: %143[ 0 ]
+# CHECK: Vreg: %22[ 17 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %17[ LoopTag*2+58 ]
+# CHECK: Vreg: %62:sub0[ 53 ]
+# CHECK: Vreg: %69[ 17 ]
+# CHECK: Vreg: %140[ 18 ]
+# CHECK: Vreg: %38[ LoopTag*2+44 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+36 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+37 ]
+# CHECK: Instr: %145:vgpr_32 = V_ADD_U32_e64 1, %141, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %52[ LoopTag*2+31 ]
+# CHECK: Vreg: %33[ LoopTag*2+41 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+33 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+34 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %144[ 1 ]
+# CHECK: Vreg: %87:sub0[ 30 ]
+# CHECK: Vreg: %4[ LoopTag*2+40 ]
+# CHECK: Vreg: %30[ 48 ]
+# CHECK: Vreg: %18[ 28 ]
+# CHECK: Vreg: %63[ LoopTag+26 ]
+# CHECK: Vreg: %89[ 20 ]
+# CHECK: Vreg: %32[ LoopTag*2+67 ]
+# CHECK: Vreg: %141[ 0 ]
+# CHECK: Vreg: %20:sub0[ 10 ]
+# CHECK: Vreg: %20:sub1[ 11 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %65[ 28 ]
+# CHECK: Vreg: %91[ 18 ]
+# CHECK: Vreg: %143[ 2 ]
+# CHECK: Vreg: %22[ 16 ]
+# CHECK: Vreg: %3[ LoopTag+25 ]
+# CHECK: Vreg: %17[ LoopTag*2+57 ]
+# CHECK: Vreg: %62:sub0[ 52 ]
+# CHECK: Vreg: %69[ 16 ]
+# CHECK: Vreg: %140[ 17 ]
+# CHECK: Vreg: %38[ LoopTag*2+43 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+35 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+36 ]
+# CHECK: Instr: %146:vgpr_32 = V_CNDMASK_B32_e64 0, killed %141, 0, killed %145, %144, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %52[ LoopTag*2+30 ]
+# CHECK: Vreg: %33[ LoopTag*2+40 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+32 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+33 ]
+# CHECK: Vreg: %2[ 18 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %87:sub0[ 29 ]
+# CHECK: Vreg: %4[ LoopTag*2+39 ]
+# CHECK: Vreg: %30[ 47 ]
+# CHECK: Vreg: %18[ 27 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %89[ 19 ]
+# CHECK: Vreg: %32[ LoopTag*2+66 ]
+# CHECK: Vreg: %141[ 0 ]
+# CHECK: Vreg: %20:sub0[ 9 ]
+# CHECK: Vreg: %20:sub1[ 10 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %65[ 27 ]
+# CHECK: Vreg: %91[ 17 ]
+# CHECK: Vreg: %143[ 1 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %17[ LoopTag*2+56 ]
+# CHECK: Vreg: %62:sub0[ 51 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %140[ 16 ]
+# CHECK: Vreg: %38[ LoopTag*2+42 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+34 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+35 ]
+# CHECK: Instr: %147:vgpr_32 = V_SUBREV_U32_e64 %35, %143, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %52[ LoopTag*2+29 ]
+# CHECK: Vreg: %33[ LoopTag*2+39 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+31 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+32 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %144[ 1 ]
+# CHECK: Vreg: %87:sub0[ 28 ]
+# CHECK: Vreg: %4[ LoopTag*2+38 ]
+# CHECK: Vreg: %30[ 46 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %63[ LoopTag+24 ]
+# CHECK: Vreg: %89[ 18 ]
+# CHECK: Vreg: %32[ LoopTag*2+65 ]
+# CHECK: Vreg: %20:sub0[ 8 ]
+# CHECK: Vreg: %20:sub1[ 9 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %65[ 26 ]
+# CHECK: Vreg: %91[ 16 ]
+# CHECK: Vreg: %146[ 3 ]
+# CHECK: Vreg: %143[ 0 ]
+# CHECK: Vreg: %22[ 14 ]
+# CHECK: Vreg: %3[ LoopTag+23 ]
+# CHECK: Vreg: %17[ LoopTag*2+55 ]
+# CHECK: Vreg: %62:sub0[ 50 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %140[ 15 ]
+# CHECK: Vreg: %38[ LoopTag*2+41 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+33 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+34 ]
+# CHECK: Instr: %148:vgpr_32 = V_CNDMASK_B32_e64 0, killed %143, 0, killed %147, killed %144, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+28 ]
+# CHECK: Vreg: %33[ LoopTag*2+38 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+30 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+31 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %87:sub0[ 27 ]
+# CHECK: Vreg: %4[ LoopTag*2+37 ]
+# CHECK: Vreg: %30[ 45 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %63[ LoopTag+23 ]
+# CHECK: Vreg: %89[ 17 ]
+# CHECK: Vreg: %32[ LoopTag*2+64 ]
+# CHECK: Vreg: %20:sub0[ 7 ]
+# CHECK: Vreg: %20:sub1[ 8 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %65[ 25 ]
+# CHECK: Vreg: %91[ 15 ]
+# CHECK: Vreg: %146[ 2 ]
+# CHECK: Vreg: %143[ 0 ]
+# CHECK: Vreg: %22[ 13 ]
+# CHECK: Vreg: %3[ LoopTag+22 ]
+# CHECK: Vreg: %17[ LoopTag*2+54 ]
+# CHECK: Vreg: %62:sub0[ 49 ]
+# CHECK: Vreg: %69[ 13 ]
+# CHECK: Vreg: %140[ 14 ]
+# CHECK: Vreg: %38[ LoopTag*2+40 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+32 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+33 ]
+# CHECK: Instr: %149:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %35, killed %148, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %52[ LoopTag*2+27 ]
+# CHECK: Vreg: %33[ LoopTag*2+37 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+29 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+30 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %87:sub0[ 26 ]
+# CHECK: Vreg: %4[ LoopTag*2+36 ]
+# CHECK: Vreg: %30[ 44 ]
+# CHECK: Vreg: %18[ 24 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %89[ 16 ]
+# CHECK: Vreg: %32[ LoopTag*2+63 ]
+# CHECK: Vreg: %20:sub0[ 6 ]
+# CHECK: Vreg: %20:sub1[ 7 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %65[ 24 ]
+# CHECK: Vreg: %91[ 14 ]
+# CHECK: Vreg: %146[ 1 ]
+# CHECK: Vreg: %148[ 0 ]
+# CHECK: Vreg: %22[ 12 ]
+# CHECK: Vreg: %3[ LoopTag+21 ]
+# CHECK: Vreg: %17[ LoopTag*2+53 ]
+# CHECK: Vreg: %62:sub0[ 48 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %140[ 13 ]
+# CHECK: Vreg: %38[ LoopTag*2+39 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+31 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+32 ]
+# CHECK: Instr: %150:vgpr_32 = V_ADD_U32_e64 1, %146, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %52[ LoopTag*2+26 ]
+# CHECK: Vreg: %33[ LoopTag*2+36 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+28 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+29 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %149[ 1 ]
+# CHECK: Vreg: %35[ 21 ]
+# CHECK: Vreg: %87:sub0[ 25 ]
+# CHECK: Vreg: %4[ LoopTag*2+35 ]
+# CHECK: Vreg: %30[ 43 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %89[ 15 ]
+# CHECK: Vreg: %32[ LoopTag*2+62 ]
+# CHECK: Vreg: %20:sub0[ 5 ]
+# CHECK: Vreg: %20:sub1[ 6 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %65[ 23 ]
+# CHECK: Vreg: %91[ 13 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %22[ 11 ]
+# CHECK: Vreg: %3[ LoopTag+20 ]
+# CHECK: Vreg: %17[ LoopTag*2+52 ]
+# CHECK: Vreg: %62:sub0[ 47 ]
+# CHECK: Vreg: %69[ 11 ]
+# CHECK: Vreg: %140[ 12 ]
+# CHECK: Vreg: %38[ LoopTag*2+38 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+30 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+31 ]
+# CHECK: Instr: %151:vgpr_32 = V_CNDMASK_B32_e64 0, killed %146, 0, killed %150, killed %149, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %52[ LoopTag*2+25 ]
+# CHECK: Vreg: %33[ LoopTag*2+35 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+27 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+28 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %35[ 20 ]
+# CHECK: Vreg: %87:sub0[ 24 ]
+# CHECK: Vreg: %4[ LoopTag*2+34 ]
+# CHECK: Vreg: %30[ 42 ]
+# CHECK: Vreg: %18[ 22 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %89[ 14 ]
+# CHECK: Vreg: %32[ LoopTag*2+61 ]
+# CHECK: Vreg: %20:sub0[ 4 ]
+# CHECK: Vreg: %20:sub1[ 5 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %65[ 22 ]
+# CHECK: Vreg: %91[ 12 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %22[ 10 ]
+# CHECK: Vreg: %3[ LoopTag+19 ]
+# CHECK: Vreg: %150[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+51 ]
+# CHECK: Vreg: %62:sub0[ 46 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %140[ 11 ]
+# CHECK: Vreg: %38[ LoopTag*2+37 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+29 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+30 ]
+# CHECK: Instr: %152:vgpr_32 = V_ASHRREV_I32_e64 31, %151, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %52[ LoopTag*2+24 ]
+# CHECK: Vreg: %33[ LoopTag*2+34 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+26 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+27 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %35[ 19 ]
+# CHECK: Vreg: %87:sub0[ 23 ]
+# CHECK: Vreg: %4[ LoopTag*2+33 ]
+# CHECK: Vreg: %30[ 41 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ 21 ]
+# CHECK: Vreg: %63[ LoopTag+19 ]
+# CHECK: Vreg: %89[ 13 ]
+# CHECK: Vreg: %32[ LoopTag*2+60 ]
+# CHECK: Vreg: %20:sub0[ 3 ]
+# CHECK: Vreg: %20:sub1[ 4 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %65[ 21 ]
+# CHECK: Vreg: %91[ 11 ]
+# CHECK: Vreg: %22[ 9 ]
+# CHECK: Vreg: %3[ LoopTag+18 ]
+# CHECK: Vreg: %17[ LoopTag*2+50 ]
+# CHECK: Vreg: %62:sub0[ 45 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %140[ 10 ]
+# CHECK: Vreg: %38[ LoopTag*2+36 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+28 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+29 ]
+# CHECK: Instr: %153:vreg_64 = REG_SEQUENCE %151, %subreg.sub0, killed %152, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %52[ LoopTag*2+23 ]
+# CHECK: Vreg: %33[ LoopTag*2+33 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+25 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+26 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %35[ 18 ]
+# CHECK: Vreg: %87:sub0[ 22 ]
+# CHECK: Vreg: %4[ LoopTag*2+32 ]
+# CHECK: Vreg: %30[ 40 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ LoopTag+18 ]
+# CHECK: Vreg: %89[ 12 ]
+# CHECK: Vreg: %32[ LoopTag*2+59 ]
+# CHECK: Vreg: %20:sub0[ 2 ]
+# CHECK: Vreg: %20:sub1[ 3 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %65[ 20 ]
+# CHECK: Vreg: %91[ 10 ]
+# CHECK: Vreg: %22[ 8 ]
+# CHECK: Vreg: %3[ LoopTag+17 ]
+# CHECK: Vreg: %17[ LoopTag*2+49 ]
+# CHECK: Vreg: %62:sub0[ 44 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %38[ LoopTag*2+35 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+27 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+28 ]
+# CHECK: Instr: %154:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %153, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %52[ LoopTag*2+22 ]
+# CHECK: Vreg: %33[ LoopTag*2+32 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+24 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+25 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %35[ 17 ]
+# CHECK: Vreg: %87:sub0[ 21 ]
+# CHECK: Vreg: %4[ LoopTag*2+31 ]
+# CHECK: Vreg: %30[ 39 ]
+# CHECK: Vreg: %151[ 7 ]
+# CHECK: Vreg: %18[ 19 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %89[ 11 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %32[ LoopTag*2+58 ]
+# CHECK: Vreg: %20:sub0[ 1 ]
+# CHECK: Vreg: %20:sub1[ 2 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %65[ 19 ]
+# CHECK: Vreg: %91[ 9 ]
+# CHECK: Vreg: %22[ 7 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %17[ LoopTag*2+48 ]
+# CHECK: Vreg: %62:sub0[ 43 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %140[ 8 ]
+# CHECK: Vreg: %38[ LoopTag*2+34 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+26 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+27 ]
+# CHECK: Instr: %155:vgpr_32, %156:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %20.sub0, %154.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %154:sub0[ 0 ]
+# CHECK: Vreg: %154:sub1[ 1 ]
+# CHECK: Vreg: %52[ LoopTag*2+21 ]
+# CHECK: Vreg: %33[ LoopTag*2+31 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+23 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+24 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %35[ 16 ]
+# CHECK: Vreg: %87:sub0[ 20 ]
+# CHECK: Vreg: %4[ LoopTag*2+30 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %151[ 6 ]
+# CHECK: Vreg: %18[ 18 ]
+# CHECK: Vreg: %63[ LoopTag+16 ]
+# CHECK: Vreg: %89[ 10 ]
+# CHECK: Vreg: %32[ LoopTag*2+57 ]
+# CHECK: Vreg: %20:sub0[ 0 ]
+# CHECK: Vreg: %20:sub1[ 1 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %65[ 18 ]
+# CHECK: Vreg: %91[ 8 ]
+# CHECK: Vreg: %22[ 6 ]
+# CHECK: Vreg: %3[ LoopTag+15 ]
+# CHECK: Vreg: %17[ LoopTag*2+47 ]
+# CHECK: Vreg: %62:sub0[ 42 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %140[ 7 ]
+# CHECK: Vreg: %38[ LoopTag*2+33 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+25 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+26 ]
+# CHECK: Instr: %157:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %20.sub1, killed %154.sub1, killed %156, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %154:sub1[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+20 ]
+# CHECK: Vreg: %33[ LoopTag*2+30 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+22 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+23 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %156[ 0 ]
+# CHECK: Vreg: %35[ 15 ]
+# CHECK: Vreg: %87:sub0[ 19 ]
+# CHECK: Vreg: %4[ LoopTag*2+29 ]
+# CHECK: Vreg: %30[ 37 ]
+# CHECK: Vreg: %151[ 5 ]
+# CHECK: Vreg: %18[ 17 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %89[ 9 ]
+# CHECK: Vreg: %32[ LoopTag*2+56 ]
+# CHECK: Vreg: %20:sub1[ 0 ]
+# CHECK: Vreg: %20:sub0[ 33 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %91[ 7 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %22[ 5 ]
+# CHECK: Vreg: %3[ LoopTag+14 ]
+# CHECK: Vreg: %17[ LoopTag*2+46 ]
+# CHECK: Vreg: %62:sub0[ 41 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %38[ LoopTag*2+32 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+24 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+25 ]
+# CHECK: Instr: %158:vreg_64 = REG_SEQUENCE killed %155, %subreg.sub0, killed %157, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %52[ LoopTag*2+19 ]
+# CHECK: Vreg: %33[ LoopTag*2+29 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+21 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+22 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %35[ 14 ]
+# CHECK: Vreg: %87:sub0[ 18 ]
+# CHECK: Vreg: %4[ LoopTag*2+28 ]
+# CHECK: Vreg: %30[ 36 ]
+# CHECK: Vreg: %151[ 4 ]
+# CHECK: Vreg: %18[ 16 ]
+# CHECK: Vreg: %63[ LoopTag+14 ]
+# CHECK: Vreg: %89[ 8 ]
+# CHECK: Vreg: %32[ LoopTag*2+55 ]
+# CHECK: Vreg: %20:sub0[ 32 ]
+# CHECK: Vreg: %20:sub1[ 33 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %91[ 6 ]
+# CHECK: Vreg: %155[ 0 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: Vreg: %3[ LoopTag+13 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+45 ]
+# CHECK: Vreg: %62:sub0[ 40 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %140[ 5 ]
+# CHECK: Vreg: %38[ LoopTag*2+31 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+23 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+24 ]
+# CHECK: Instr: %159:vgpr_32 = GLOBAL_LOAD_USHORT %158, 0, 0, implicit $exec :: (load (s16) from %ir.gep4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %52[ LoopTag*2+18 ]
+# CHECK: Vreg: %33[ LoopTag*2+28 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+20 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+21 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %35[ 13 ]
+# CHECK: Vreg: %87:sub0[ 17 ]
+# CHECK: Vreg: %4[ LoopTag*2+27 ]
+# CHECK: Vreg: %30[ 35 ]
+# CHECK: Vreg: %158[ 0 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ 15 ]
+# CHECK: Vreg: %63[ LoopTag+13 ]
+# CHECK: Vreg: %89[ 7 ]
+# CHECK: Vreg: %32[ LoopTag*2+54 ]
+# CHECK: Vreg: %20:sub0[ 31 ]
+# CHECK: Vreg: %20:sub1[ 32 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %91[ 5 ]
+# CHECK: Vreg: %22[ 3 ]
+# CHECK: Vreg: %3[ LoopTag+12 ]
+# CHECK: Vreg: %17[ LoopTag*2+44 ]
+# CHECK: Vreg: %62:sub0[ 39 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %38[ LoopTag*2+30 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+22 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+23 ]
+# CHECK: Instr: %160:vgpr_32 = GLOBAL_LOAD_USHORT killed %158, 2, 0, implicit $exec :: (load (s16) from %ir.gep4 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %52[ LoopTag*2+17 ]
+# CHECK: Vreg: %33[ LoopTag*2+27 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+19 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+20 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %35[ 12 ]
+# CHECK: Vreg: %87:sub0[ 16 ]
+# CHECK: Vreg: %4[ LoopTag*2+26 ]
+# CHECK: Vreg: %30[ 34 ]
+# CHECK: Vreg: %158[ 0 ]
+# CHECK: Vreg: %151[ 2 ]
+# CHECK: Vreg: %18[ 14 ]
+# CHECK: Vreg: %63[ LoopTag+12 ]
+# CHECK: Vreg: %89[ 6 ]
+# CHECK: Vreg: %32[ LoopTag*2+53 ]
+# CHECK: Vreg: %20:sub0[ 30 ]
+# CHECK: Vreg: %20:sub1[ 31 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %91[ 4 ]
+# CHECK: Vreg: %22[ 2 ]
+# CHECK: Vreg: %3[ LoopTag+11 ]
+# CHECK: Vreg: %17[ LoopTag*2+43 ]
+# CHECK: Vreg: %62:sub0[ 38 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %159[ 1 ]
+# CHECK: Vreg: %140[ 3 ]
+# CHECK: Vreg: %38[ LoopTag*2+29 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+21 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+22 ]
+# CHECK: Instr: %161:vgpr_32 = V_LSHL_OR_B32_e64 killed %160, 16, killed %159, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %52[ LoopTag*2+16 ]
+# CHECK: Vreg: %33[ LoopTag*2+26 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+18 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+19 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %35[ 11 ]
+# CHECK: Vreg: %87:sub0[ 15 ]
+# CHECK: Vreg: %4[ LoopTag*2+25 ]
+# CHECK: Vreg: %30[ 33 ]
+# CHECK: Vreg: %151[ 1 ]
+# CHECK: Vreg: %18[ 13 ]
+# CHECK: Vreg: %63[ LoopTag+11 ]
+# CHECK: Vreg: %89[ 5 ]
+# CHECK: Vreg: %32[ LoopTag*2+52 ]
+# CHECK: Vreg: %160[ 0 ]
+# CHECK: Vreg: %20:sub0[ 29 ]
+# CHECK: Vreg: %20:sub1[ 30 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %3[ LoopTag+10 ]
+# CHECK: Vreg: %17[ LoopTag*2+42 ]
+# CHECK: Vreg: %62:sub0[ 37 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %159[ 0 ]
+# CHECK: Vreg: %140[ 2 ]
+# CHECK: Vreg: %38[ LoopTag*2+28 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+20 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+21 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %22, %161, 0, 0, implicit $exec :: (store (s32) into %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %52[ LoopTag*2+15 ]
+# CHECK: Vreg: %33[ LoopTag*2+25 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+17 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+18 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %35[ 10 ]
+# CHECK: Vreg: %87:sub0[ 14 ]
+# CHECK: Vreg: %4[ LoopTag*2+24 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+10 ]
+# CHECK: Vreg: %89[ 4 ]
+# CHECK: Vreg: %32[ LoopTag*2+51 ]
+# CHECK: Vreg: %20:sub0[ 28 ]
+# CHECK: Vreg: %20:sub1[ 29 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+9 ]
+# CHECK: Vreg: %17[ LoopTag*2+41 ]
+# CHECK: Vreg: %62:sub0[ 36 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %140[ 1 ]
+# CHECK: Vreg: %38[ LoopTag*2+27 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+19 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+20 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %52[ LoopTag*2+15 ]
+# CHECK: Vreg: %33[ LoopTag*2+25 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+17 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+18 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %35[ 10 ]
+# CHECK: Vreg: %87:sub0[ 14 ]
+# CHECK: Vreg: %4[ LoopTag*2+24 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+10 ]
+# CHECK: Vreg: %89[ 4 ]
+# CHECK: Vreg: %32[ LoopTag*2+51 ]
+# CHECK: Vreg: %20:sub0[ 28 ]
+# CHECK: Vreg: %20:sub1[ 29 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %22[ 56 ]
+# CHECK: Vreg: %3[ LoopTag+9 ]
+# CHECK: Vreg: %17[ LoopTag*2+41 ]
+# CHECK: Vreg: %62:sub0[ 36 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %140[ 1 ]
+# CHECK: Vreg: %38[ LoopTag*2+27 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+19 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+20 ]
+# CHECK: --- MBB_12 ---
+# CHECK: Instr: %68:vgpr_32 = PHI %107, %bb.10, %69, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %52[ LoopTag*2+15 ]
+# CHECK: Vreg: %33[ LoopTag*2+25 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+17 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+18 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %137[ 0 ]
+# CHECK: Vreg: %35[ 10 ]
+# CHECK: Vreg: %87:sub0[ 14 ]
+# CHECK: Vreg: %4[ LoopTag*2+24 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+10 ]
+# CHECK: Vreg: %89[ 4 ]
+# CHECK: Vreg: %32[ LoopTag*2+51 ]
+# CHECK: Vreg: %20:sub0[ 28 ]
+# CHECK: Vreg: %20:sub1[ 29 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %22[ 56 ]
+# CHECK: Vreg: %3[ LoopTag+9 ]
+# CHECK: Vreg: %17[ LoopTag*2+41 ]
+# CHECK: Vreg: %62:sub0[ 36 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %140[ 1 ]
+# CHECK: Vreg: %38[ LoopTag*2+27 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+19 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+20 ]
+# CHECK: Instr: %162:vgpr_32 = PHI %137, %bb.10, %161, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %52[ LoopTag*2+15 ]
+# CHECK: Vreg: %33[ LoopTag*2+25 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+17 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+18 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %137[ 0 ]
+# CHECK: Vreg: %35[ 10 ]
+# CHECK: Vreg: %87:sub0[ 14 ]
+# CHECK: Vreg: %4[ LoopTag*2+24 ]
+# CHECK: Vreg: %68[ LoopTag+12 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+10 ]
+# CHECK: Vreg: %89[ 4 ]
+# CHECK: Vreg: %32[ LoopTag*2+51 ]
+# CHECK: Vreg: %20:sub0[ 28 ]
+# CHECK: Vreg: %20:sub1[ 29 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %22[ 56 ]
+# CHECK: Vreg: %3[ LoopTag+9 ]
+# CHECK: Vreg: %17[ LoopTag*2+41 ]
+# CHECK: Vreg: %62:sub0[ 36 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %140[ 1 ]
+# CHECK: Vreg: %38[ LoopTag*2+27 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+19 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+20 ]
+# CHECK: Instr: %163:vgpr_32 = PHI %129, %bb.10, %151, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %52[ LoopTag*2+15 ]
+# CHECK: Vreg: %33[ LoopTag*2+25 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+17 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+18 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %35[ 10 ]
+# CHECK: Vreg: %87:sub0[ 14 ]
+# CHECK: Vreg: %4[ LoopTag*2+24 ]
+# CHECK: Vreg: %68[ LoopTag+12 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+10 ]
+# CHECK: Vreg: %89[ 4 ]
+# CHECK: Vreg: %32[ LoopTag*2+51 ]
+# CHECK: Vreg: %20:sub0[ 28 ]
+# CHECK: Vreg: %20:sub1[ 29 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %162[ LoopTag*3+29 ]
+# CHECK: Vreg: %22[ 56 ]
+# CHECK: Vreg: %3[ LoopTag+9 ]
+# CHECK: Vreg: %17[ LoopTag*2+41 ]
+# CHECK: Vreg: %62:sub0[ 36 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %140[ 1 ]
+# CHECK: Vreg: %38[ LoopTag*2+27 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+19 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+20 ]
+# CHECK: Instr: SI_END_CF killed %140, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %52[ LoopTag*2+14 ]
+# CHECK: Vreg: %33[ LoopTag*2+24 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+16 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+17 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %163[ LoopTag*2+15 ]
+# CHECK: Vreg: %35[ 9 ]
+# CHECK: Vreg: %87:sub0[ 13 ]
+# CHECK: Vreg: %4[ LoopTag*2+23 ]
+# CHECK: Vreg: %68[ LoopTag+11 ]
+# CHECK: Vreg: %30[ 31 ]
+# CHECK: Vreg: %18[ 11 ]
+# CHECK: Vreg: %63[ LoopTag+9 ]
+# CHECK: Vreg: %89[ 3 ]
+# CHECK: Vreg: %32[ LoopTag*2+50 ]
+# CHECK: Vreg: %20:sub0[ 27 ]
+# CHECK: Vreg: %20:sub1[ 28 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %91[ 1 ]
+# CHECK: Vreg: %162[ LoopTag*3+28 ]
+# CHECK: Vreg: %22[ 55 ]
+# CHECK: Vreg: %3[ LoopTag+8 ]
+# CHECK: Vreg: %17[ LoopTag*2+40 ]
+# CHECK: Vreg: %62:sub0[ 35 ]
+# CHECK: Vreg: %69[ 13 ]
+# CHECK: Vreg: %140[ 0 ]
+# CHECK: Vreg: %38[ LoopTag*2+26 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+18 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+19 ]
+# CHECK: Instr: %92:sreg_32 = S_ADD_I32 killed %91, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %52[ LoopTag*2+13 ]
+# CHECK: Vreg: %33[ LoopTag*2+23 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+15 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+16 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %163[ LoopTag*2+14 ]
+# CHECK: Vreg: %35[ 8 ]
+# CHECK: Vreg: %87:sub0[ 12 ]
+# CHECK: Vreg: %4[ LoopTag*2+22 ]
+# CHECK: Vreg: %68[ LoopTag+10 ]
+# CHECK: Vreg: %30[ 30 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %63[ LoopTag+8 ]
+# CHECK: Vreg: %89[ 2 ]
+# CHECK: Vreg: %32[ LoopTag*2+49 ]
+# CHECK: Vreg: %20:sub0[ 26 ]
+# CHECK: Vreg: %20:sub1[ 27 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %162[ LoopTag*3+27 ]
+# CHECK: Vreg: %22[ 54 ]
+# CHECK: Vreg: %3[ LoopTag+7 ]
+# CHECK: Vreg: %17[ LoopTag*2+39 ]
+# CHECK: Vreg: %62:sub0[ 34 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %38[ LoopTag*2+25 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+17 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+18 ]
+# CHECK: Instr: %164:sreg_32 = V_CMP_GE_U32_e64 %92, %2, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %52[ LoopTag*2+12 ]
+# CHECK: Vreg: %33[ LoopTag*2+22 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+14 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+15 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %163[ LoopTag*2+13 ]
+# CHECK: Vreg: %35[ 7 ]
+# CHECK: Vreg: %87:sub0[ 11 ]
+# CHECK: Vreg: %4[ LoopTag*2+21 ]
+# CHECK: Vreg: %68[ LoopTag+9 ]
+# CHECK: Vreg: %30[ 29 ]
+# CHECK: Vreg: %18[ 9 ]
+# CHECK: Vreg: %63[ LoopTag+7 ]
+# CHECK: Vreg: %89[ 1 ]
+# CHECK: Vreg: %32[ LoopTag*2+48 ]
+# CHECK: Vreg: %20:sub0[ 25 ]
+# CHECK: Vreg: %20:sub1[ 26 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %162[ LoopTag*3+26 ]
+# CHECK: Vreg: %22[ 53 ]
+# CHECK: Vreg: %3[ LoopTag+6 ]
+# CHECK: Vreg: %17[ LoopTag*2+38 ]
+# CHECK: Vreg: %62:sub0[ 33 ]
+# CHECK: Vreg: %69[ 11 ]
+# CHECK: Vreg: %38[ LoopTag*2+24 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+16 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+17 ]
+# CHECK: Instr: %90:sreg_32 = SI_IF_BREAK killed %164, killed %89, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %52[ LoopTag*2+11 ]
+# CHECK: Vreg: %33[ LoopTag*2+21 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+13 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+14 ]
+# CHECK: Vreg: %2[ 34 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %163[ LoopTag*2+12 ]
+# CHECK: Vreg: %35[ 6 ]
+# CHECK: Vreg: %87:sub0[ 10 ]
+# CHECK: Vreg: %4[ LoopTag*2+20 ]
+# CHECK: Vreg: %68[ LoopTag+8 ]
+# CHECK: Vreg: %30[ 28 ]
+# CHECK: Vreg: %18[ 8 ]
+# CHECK: Vreg: %63[ LoopTag+6 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %32[ LoopTag*2+47 ]
+# CHECK: Vreg: %20:sub0[ 24 ]
+# CHECK: Vreg: %20:sub1[ 25 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %162[ LoopTag*3+25 ]
+# CHECK: Vreg: %22[ 52 ]
+# CHECK: Vreg: %3[ LoopTag+5 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %17[ LoopTag*2+37 ]
+# CHECK: Vreg: %62:sub0[ 32 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %38[ LoopTag*2+23 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+15 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+16 ]
+# CHECK: Instr: SI_LOOP %90, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+10 ]
+# CHECK: Vreg: %33[ LoopTag*2+20 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+12 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+13 ]
+# CHECK: Vreg: %2[ 33 ]
+# CHECK: Vreg: %92[ 1 ]
+# CHECK: Vreg: %163[ LoopTag*2+11 ]
+# CHECK: Vreg: %35[ 5 ]
+# CHECK: Vreg: %87:sub0[ 9 ]
+# CHECK: Vreg: %4[ LoopTag*2+19 ]
+# CHECK: Vreg: %68[ LoopTag+7 ]
+# CHECK: Vreg: %30[ 27 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %63[ LoopTag+5 ]
+# CHECK: Vreg: %32[ LoopTag*2+46 ]
+# CHECK: Vreg: %20:sub0[ 23 ]
+# CHECK: Vreg: %20:sub1[ 24 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %162[ LoopTag*3+24 ]
+# CHECK: Vreg: %22[ 51 ]
+# CHECK: Vreg: %3[ LoopTag+4 ]
+# CHECK: Vreg: %17[ LoopTag*2+36 ]
+# CHECK: Vreg: %62:sub0[ 31 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %38[ LoopTag*2+22 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+14 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+15 ]
+# CHECK: Instr: S_BRANCH %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+9 ]
+# CHECK: Vreg: %33[ LoopTag*2+19 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+11 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+12 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %163[ LoopTag*2+10 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %87:sub0[ 8 ]
+# CHECK: Vreg: %4[ LoopTag*2+18 ]
+# CHECK: Vreg: %68[ LoopTag+6 ]
+# CHECK: Vreg: %30[ 26 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %63[ LoopTag+4 ]
+# CHECK: Vreg: %32[ LoopTag*2+45 ]
+# CHECK: Vreg: %20:sub0[ 22 ]
+# CHECK: Vreg: %20:sub1[ 23 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %162[ LoopTag*3+23 ]
+# CHECK: Vreg: %22[ 50 ]
+# CHECK: Vreg: %3[ LoopTag+3 ]
+# CHECK: Vreg: %17[ LoopTag*2+35 ]
+# CHECK: Vreg: %62:sub0[ 30 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %38[ LoopTag*2+21 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+13 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+14 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %52[ LoopTag*2+9 ]
+# CHECK: Vreg: %33[ LoopTag*2+19 ]
+# CHECK: Vreg: %21:sub0[ LoopTag+11 ]
+# CHECK: Vreg: %21:sub1[ LoopTag+12 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %163[ LoopTag*2+10 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %87:sub0[ 8 ]
+# CHECK: Vreg: %4[ LoopTag*2+18 ]
+# CHECK: Vreg: %68[ LoopTag+6 ]
+# CHECK: Vreg: %30[ 26 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %63[ LoopTag+4 ]
+# CHECK: Vreg: %32[ LoopTag*2+45 ]
+# CHECK: Vreg: %20:sub0[ 22 ]
+# CHECK: Vreg: %20:sub1[ 23 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %162[ LoopTag*3+23 ]
+# CHECK: Vreg: %22[ 50 ]
+# CHECK: Vreg: %3[ LoopTag+3 ]
+# CHECK: Vreg: %17[ LoopTag*2+35 ]
+# CHECK: Vreg: %62:sub0[ 30 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %38[ LoopTag*2+21 ]
+# CHECK: Vreg: %19:sub0[ LoopTag*2+13 ]
+# CHECK: Vreg: %19:sub1[ LoopTag*2+14 ]
+# CHECK: --- MBB_13 ---
+# CHECK: Instr: SI_END_CF killed %90, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %52[ LoopTag+8 ]
+# CHECK: Vreg: %33[ LoopTag+18 ]
+# CHECK: Vreg: %21:sub0[ 10 ]
+# CHECK: Vreg: %21:sub1[ 11 ]
+# CHECK: Vreg: %2[ 57 ]
+# CHECK: Vreg: %163[ LoopTag+9 ]
+# CHECK: Vreg: %35[ 29 ]
+# CHECK: Vreg: %4[ LoopTag+17 ]
+# CHECK: Vreg: %68[ 5 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %18[ 31 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %32[ LoopTag+44 ]
+# CHECK: Vreg: %20:sub0[ 47 ]
+# CHECK: Vreg: %20:sub1[ 48 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %162[ LoopTag*2+22 ]
+# CHECK: Vreg: %22[ 75 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %17[ LoopTag+34 ]
+# CHECK: Vreg: %62:sub0[ 55 ]
+# CHECK: Vreg: %38[ LoopTag+20 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+12 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+13 ]
+# CHECK: Instr: %66:sreg_32 = S_ADD_I32 killed %65, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %52[ LoopTag+7 ]
+# CHECK: Vreg: %33[ LoopTag+17 ]
+# CHECK: Vreg: %21:sub0[ 9 ]
+# CHECK: Vreg: %21:sub1[ 10 ]
+# CHECK: Vreg: %2[ 56 ]
+# CHECK: Vreg: %163[ LoopTag+8 ]
+# CHECK: Vreg: %35[ 28 ]
+# CHECK: Vreg: %4[ LoopTag+16 ]
+# CHECK: Vreg: %68[ 4 ]
+# CHECK: Vreg: %30[ 50 ]
+# CHECK: Vreg: %18[ 30 ]
+# CHECK: Vreg: %63[ 2 ]
+# CHECK: Vreg: %32[ LoopTag+43 ]
+# CHECK: Vreg: %20:sub0[ 46 ]
+# CHECK: Vreg: %20:sub1[ 47 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %162[ LoopTag*2+21 ]
+# CHECK: Vreg: %22[ 74 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+33 ]
+# CHECK: Vreg: %62:sub0[ 54 ]
+# CHECK: Vreg: %38[ LoopTag+19 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+11 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+12 ]
+# CHECK: Instr: %165:sreg_32 = V_CMP_GE_U32_e64 %66, %3, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %52[ LoopTag+6 ]
+# CHECK: Vreg: %33[ LoopTag+16 ]
+# CHECK: Vreg: %21:sub0[ 8 ]
+# CHECK: Vreg: %21:sub1[ 9 ]
+# CHECK: Vreg: %2[ 55 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %163[ LoopTag+7 ]
+# CHECK: Vreg: %35[ 27 ]
+# CHECK: Vreg: %4[ LoopTag+15 ]
+# CHECK: Vreg: %68[ 3 ]
+# CHECK: Vreg: %30[ 49 ]
+# CHECK: Vreg: %18[ 29 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %32[ LoopTag+42 ]
+# CHECK: Vreg: %20:sub0[ 45 ]
+# CHECK: Vreg: %20:sub1[ 46 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %162[ LoopTag*2+20 ]
+# CHECK: Vreg: %22[ 73 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+32 ]
+# CHECK: Vreg: %62:sub0[ 53 ]
+# CHECK: Vreg: %38[ LoopTag+18 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+10 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+11 ]
+# CHECK: Instr: %64:sreg_32 = SI_IF_BREAK killed %165, killed %63, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %52[ LoopTag+5 ]
+# CHECK: Vreg: %33[ LoopTag+15 ]
+# CHECK: Vreg: %21:sub0[ 7 ]
+# CHECK: Vreg: %21:sub1[ 8 ]
+# CHECK: Vreg: %2[ 54 ]
+# CHECK: Vreg: %66[ 2 ]
+# CHECK: Vreg: %163[ LoopTag+6 ]
+# CHECK: Vreg: %35[ 26 ]
+# CHECK: Vreg: %4[ LoopTag+14 ]
+# CHECK: Vreg: %68[ 2 ]
+# CHECK: Vreg: %30[ 48 ]
+# CHECK: Vreg: %165[ 0 ]
+# CHECK: Vreg: %18[ 28 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+41 ]
+# CHECK: Vreg: %20:sub0[ 44 ]
+# CHECK: Vreg: %20:sub1[ 45 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %162[ LoopTag*2+19 ]
+# CHECK: Vreg: %22[ 72 ]
+# CHECK: Vreg: %3[ 60 ]
+# CHECK: Vreg: %17[ LoopTag+31 ]
+# CHECK: Vreg: %62:sub0[ 52 ]
+# CHECK: Vreg: %38[ LoopTag+17 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+9 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+10 ]
+# CHECK: Instr: SI_LOOP %64, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %52[ LoopTag+4 ]
+# CHECK: Vreg: %33[ LoopTag+14 ]
+# CHECK: Vreg: %21:sub0[ 6 ]
+# CHECK: Vreg: %21:sub1[ 7 ]
+# CHECK: Vreg: %2[ 53 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %163[ LoopTag+5 ]
+# CHECK: Vreg: %35[ 25 ]
+# CHECK: Vreg: %4[ LoopTag+13 ]
+# CHECK: Vreg: %68[ 1 ]
+# CHECK: Vreg: %30[ 47 ]
+# CHECK: Vreg: %18[ 27 ]
+# CHECK: Vreg: %32[ LoopTag+40 ]
+# CHECK: Vreg: %20:sub0[ 43 ]
+# CHECK: Vreg: %20:sub1[ 44 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %162[ LoopTag*2+18 ]
+# CHECK: Vreg: %22[ 71 ]
+# CHECK: Vreg: %3[ 59 ]
+# CHECK: Vreg: %17[ LoopTag+30 ]
+# CHECK: Vreg: %62:sub0[ 51 ]
+# CHECK: Vreg: %38[ LoopTag+16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+8 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+9 ]
+# CHECK: Instr: S_BRANCH %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %52[ LoopTag+3 ]
+# CHECK: Vreg: %33[ LoopTag+13 ]
+# CHECK: Vreg: %21:sub0[ 5 ]
+# CHECK: Vreg: %21:sub1[ 6 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %163[ LoopTag+4 ]
+# CHECK: Vreg: %35[ 24 ]
+# CHECK: Vreg: %4[ LoopTag+12 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %30[ 46 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %32[ LoopTag+39 ]
+# CHECK: Vreg: %20:sub0[ 42 ]
+# CHECK: Vreg: %20:sub1[ 43 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %162[ LoopTag*2+17 ]
+# CHECK: Vreg: %22[ 70 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %17[ LoopTag+29 ]
+# CHECK: Vreg: %62:sub0[ 50 ]
+# CHECK: Vreg: %38[ LoopTag+15 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+7 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+8 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %52[ LoopTag+3 ]
+# CHECK: Vreg: %33[ LoopTag+13 ]
+# CHECK: Vreg: %21:sub0[ 5 ]
+# CHECK: Vreg: %21:sub1[ 6 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %163[ LoopTag+4 ]
+# CHECK: Vreg: %35[ 24 ]
+# CHECK: Vreg: %4[ LoopTag+12 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %30[ 46 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %32[ LoopTag+39 ]
+# CHECK: Vreg: %20:sub0[ 42 ]
+# CHECK: Vreg: %20:sub1[ 43 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %162[ LoopTag*2+17 ]
+# CHECK: Vreg: %22[ 70 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %17[ LoopTag+29 ]
+# CHECK: Vreg: %62:sub0[ 50 ]
+# CHECK: Vreg: %38[ LoopTag+15 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+7 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+8 ]
+# CHECK: --- MBB_14 ---
+# CHECK: Instr: SI_END_CF killed %64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 59 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %52[ 2 ]
+# CHECK: Vreg: %33[ 12 ]
+# CHECK: Vreg: %21:sub0[ 18 ]
+# CHECK: Vreg: %21:sub1[ 19 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %163[ 3 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %18[ 64 ]
+# CHECK: Vreg: %32[ 38 ]
+# CHECK: Vreg: %20:sub0[ 80 ]
+# CHECK: Vreg: %20:sub1[ 81 ]
+# CHECK: Vreg: %1[ 72 ]
+# CHECK: Vreg: %162[ LoopTag+16 ]
+# CHECK: Vreg: %22[ 108 ]
+# CHECK: Vreg: %3[ 96 ]
+# CHECK: Vreg: %17[ 28 ]
+# CHECK: Vreg: %38[ 14 ]
+# CHECK: Vreg: %19:sub0[ 6 ]
+# CHECK: Vreg: %19:sub1[ 7 ]
+# CHECK: Instr: %36:sreg_32 = S_ADD_I32 killed %35, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %33[ 11 ]
+# CHECK: Vreg: %21:sub0[ 17 ]
+# CHECK: Vreg: %21:sub1[ 18 ]
+# CHECK: Vreg: %2[ 89 ]
+# CHECK: Vreg: %163[ 2 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %4[ 10 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %18[ 63 ]
+# CHECK: Vreg: %32[ 37 ]
+# CHECK: Vreg: %20:sub0[ 79 ]
+# CHECK: Vreg: %20:sub1[ 80 ]
+# CHECK: Vreg: %1[ 71 ]
+# CHECK: Vreg: %162[ LoopTag+15 ]
+# CHECK: Vreg: %22[ 107 ]
+# CHECK: Vreg: %3[ 95 ]
+# CHECK: Vreg: %17[ 27 ]
+# CHECK: Vreg: %38[ 13 ]
+# CHECK: Vreg: %19:sub0[ 5 ]
+# CHECK: Vreg: %19:sub1[ 6 ]
+# CHECK: Instr: %166:vgpr_32 = V_ADD_U32_e64 %36, %52, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 57 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %33[ 10 ]
+# CHECK: Vreg: %21:sub0[ 16 ]
+# CHECK: Vreg: %21:sub1[ 17 ]
+# CHECK: Vreg: %2[ 88 ]
+# CHECK: Vreg: %163[ 1 ]
+# CHECK: Vreg: %4[ 9 ]
+# CHECK: Vreg: %30[ 82 ]
+# CHECK: Vreg: %18[ 62 ]
+# CHECK: Vreg: %32[ 36 ]
+# CHECK: Vreg: %20:sub0[ 78 ]
+# CHECK: Vreg: %20:sub1[ 79 ]
+# CHECK: Vreg: %1[ 70 ]
+# CHECK: Vreg: %162[ LoopTag+14 ]
+# CHECK: Vreg: %22[ 106 ]
+# CHECK: Vreg: %3[ 94 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 26 ]
+# CHECK: Vreg: %38[ 12 ]
+# CHECK: Vreg: %19:sub0[ 4 ]
+# CHECK: Vreg: %19:sub1[ 5 ]
+# CHECK: Instr: %167:vgpr_32 = V_ASHRREV_I32_e64 31, %163, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 56 ]
+# CHECK: Vreg: %52[ LoopTag+13 ]
+# CHECK: Vreg: %33[ 9 ]
+# CHECK: Vreg: %166[ 6 ]
+# CHECK: Vreg: %21:sub0[ 15 ]
+# CHECK: Vreg: %21:sub1[ 16 ]
+# CHECK: Vreg: %2[ 87 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %18[ 61 ]
+# CHECK: Vreg: %32[ 35 ]
+# CHECK: Vreg: %20:sub0[ 77 ]
+# CHECK: Vreg: %20:sub1[ 78 ]
+# CHECK: Vreg: %1[ 69 ]
+# CHECK: Vreg: %162[ LoopTag+13 ]
+# CHECK: Vreg: %22[ 105 ]
+# CHECK: Vreg: %3[ 93 ]
+# CHECK: Vreg: %36[ 8 ]
+# CHECK: Vreg: %17[ 25 ]
+# CHECK: Vreg: %38[ 11 ]
+# CHECK: Vreg: %19:sub0[ 3 ]
+# CHECK: Vreg: %19:sub1[ 4 ]
+# CHECK: Instr: %168:vreg_64 = REG_SEQUENCE killed %163, %subreg.sub0, killed %167, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 55 ]
+# CHECK: Vreg: %52[ LoopTag+12 ]
+# CHECK: Vreg: %33[ 8 ]
+# CHECK: Vreg: %166[ 5 ]
+# CHECK: Vreg: %21:sub0[ 14 ]
+# CHECK: Vreg: %21:sub1[ 15 ]
+# CHECK: Vreg: %2[ 86 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %4[ 7 ]
+# CHECK: Vreg: %30[ 80 ]
+# CHECK: Vreg: %18[ 60 ]
+# CHECK: Vreg: %32[ 34 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20:sub0[ 76 ]
+# CHECK: Vreg: %20:sub1[ 77 ]
+# CHECK: Vreg: %1[ 68 ]
+# CHECK: Vreg: %162[ LoopTag+12 ]
+# CHECK: Vreg: %22[ 104 ]
+# CHECK: Vreg: %3[ 92 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Vreg: %17[ 24 ]
+# CHECK: Vreg: %38[ 10 ]
+# CHECK: Vreg: %19:sub0[ 2 ]
+# CHECK: Vreg: %19:sub1[ 3 ]
+# CHECK: Instr: %169:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %168, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 54 ]
+# CHECK: Vreg: %52[ LoopTag+11 ]
+# CHECK: Vreg: %33[ 7 ]
+# CHECK: Vreg: %166[ 4 ]
+# CHECK: Vreg: %21:sub0[ 13 ]
+# CHECK: Vreg: %21:sub1[ 14 ]
+# CHECK: Vreg: %2[ 85 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %4[ 6 ]
+# CHECK: Vreg: %30[ 79 ]
+# CHECK: Vreg: %18[ 59 ]
+# CHECK: Vreg: %32[ 33 ]
+# CHECK: Vreg: %20:sub0[ 75 ]
+# CHECK: Vreg: %20:sub1[ 76 ]
+# CHECK: Vreg: %1[ 67 ]
+# CHECK: Vreg: %162[ LoopTag+11 ]
+# CHECK: Vreg: %22[ 103 ]
+# CHECK: Vreg: %3[ 91 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %17[ 23 ]
+# CHECK: Vreg: %38[ 9 ]
+# CHECK: Vreg: %19:sub0[ 1 ]
+# CHECK: Vreg: %19:sub1[ 2 ]
+# CHECK: Instr: %170:vgpr_32, %171:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %19.sub0, %169.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 53 ]
+# CHECK: Vreg: %52[ LoopTag+10 ]
+# CHECK: Vreg: %33[ 6 ]
+# CHECK: Vreg: %166[ 3 ]
+# CHECK: Vreg: %21:sub0[ 12 ]
+# CHECK: Vreg: %21:sub1[ 13 ]
+# CHECK: Vreg: %2[ 84 ]
+# CHECK: Vreg: %4[ 5 ]
+# CHECK: Vreg: %30[ 78 ]
+# CHECK: Vreg: %18[ 58 ]
+# CHECK: Vreg: %32[ 32 ]
+# CHECK: Vreg: %20:sub0[ 74 ]
+# CHECK: Vreg: %20:sub1[ 75 ]
+# CHECK: Vreg: %1[ 66 ]
+# CHECK: Vreg: %162[ LoopTag+10 ]
+# CHECK: Vreg: %169:sub0[ 0 ]
+# CHECK: Vreg: %169:sub1[ 1 ]
+# CHECK: Vreg: %22[ 102 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %17[ 22 ]
+# CHECK: Vreg: %38[ 8 ]
+# CHECK: Vreg: %19:sub0[ 0 ]
+# CHECK: Vreg: %19:sub1[ 1 ]
+# CHECK: Instr: %172:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %19.sub1, killed %169.sub1, killed %171, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 52 ]
+# CHECK: Vreg: %52[ LoopTag+9 ]
+# CHECK: Vreg: %33[ 5 ]
+# CHECK: Vreg: %166[ 2 ]
+# CHECK: Vreg: %21:sub0[ 11 ]
+# CHECK: Vreg: %21:sub1[ 12 ]
+# CHECK: Vreg: %2[ 83 ]
+# CHECK: Vreg: %170[ 1 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %30[ 77 ]
+# CHECK: Vreg: %18[ 57 ]
+# CHECK: Vreg: %32[ 31 ]
+# CHECK: Vreg: %20:sub0[ 73 ]
+# CHECK: Vreg: %20:sub1[ 74 ]
+# CHECK: Vreg: %1[ 65 ]
+# CHECK: Vreg: %162[ LoopTag+9 ]
+# CHECK: Vreg: %169:sub1[ 0 ]
+# CHECK: Vreg: %22[ 101 ]
+# CHECK: Vreg: %3[ 89 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %17[ 21 ]
+# CHECK: Vreg: %171[ 0 ]
+# CHECK: Vreg: %38[ 7 ]
+# CHECK: Vreg: %19:sub1[ 0 ]
+# CHECK: Vreg: %19:sub0[ 99 ]
+# CHECK: Instr: %173:vreg_64 = REG_SEQUENCE killed %170, %subreg.sub0, killed %172, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 51 ]
+# CHECK: Vreg: %52[ LoopTag+8 ]
+# CHECK: Vreg: %33[ 4 ]
+# CHECK: Vreg: %166[ 1 ]
+# CHECK: Vreg: %21:sub0[ 10 ]
+# CHECK: Vreg: %21:sub1[ 11 ]
+# CHECK: Vreg: %2[ 82 ]
+# CHECK: Vreg: %170[ 0 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %30[ 76 ]
+# CHECK: Vreg: %18[ 56 ]
+# CHECK: Vreg: %172[ 0 ]
+# CHECK: Vreg: %32[ 30 ]
+# CHECK: Vreg: %20:sub0[ 72 ]
+# CHECK: Vreg: %20:sub1[ 73 ]
+# CHECK: Vreg: %1[ 64 ]
+# CHECK: Vreg: %162[ LoopTag+8 ]
+# CHECK: Vreg: %22[ 100 ]
+# CHECK: Vreg: %3[ 88 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %17[ 20 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Vreg: %19:sub0[ 98 ]
+# CHECK: Vreg: %19:sub1[ 99 ]
+# CHECK: Instr: GLOBAL_STORE_SHORT_D16_HI %173, %166, 2, 0, implicit $exec :: (store (s16) into %ir.gep5 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 50 ]
+# CHECK: Vreg: %173[ 0 ]
+# CHECK: Vreg: %52[ LoopTag+7 ]
+# CHECK: Vreg: %33[ 3 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Vreg: %21:sub0[ 9 ]
+# CHECK: Vreg: %21:sub1[ 10 ]
+# CHECK: Vreg: %2[ 81 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %18[ 55 ]
+# CHECK: Vreg: %32[ 29 ]
+# CHECK: Vreg: %20:sub0[ 71 ]
+# CHECK: Vreg: %20:sub1[ 72 ]
+# CHECK: Vreg: %1[ 63 ]
+# CHECK: Vreg: %162[ LoopTag+7 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %3[ 87 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 19 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Vreg: %19:sub0[ 97 ]
+# CHECK: Vreg: %19:sub1[ 98 ]
+# CHECK: Instr: GLOBAL_STORE_SHORT killed %173, killed %166, 0, 0, implicit $exec :: (store (s16) into %ir.gep5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 49 ]
+# CHECK: Vreg: %173[ 0 ]
+# CHECK: Vreg: %52[ LoopTag+6 ]
+# CHECK: Vreg: %33[ 2 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Vreg: %21:sub0[ 8 ]
+# CHECK: Vreg: %21:sub1[ 9 ]
+# CHECK: Vreg: %2[ 80 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %30[ 74 ]
+# CHECK: Vreg: %18[ 54 ]
+# CHECK: Vreg: %32[ 28 ]
+# CHECK: Vreg: %20:sub0[ 70 ]
+# CHECK: Vreg: %20:sub1[ 71 ]
+# CHECK: Vreg: %1[ 62 ]
+# CHECK: Vreg: %162[ LoopTag+6 ]
+# CHECK: Vreg: %22[ 98 ]
+# CHECK: Vreg: %3[ 86 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Vreg: %19:sub0[ 96 ]
+# CHECK: Vreg: %19:sub1[ 97 ]
+# CHECK: Instr: %174:sreg_32 = V_CMP_GE_U32_e64 %36, %4, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 48 ]
+# CHECK: Vreg: %52[ LoopTag+5 ]
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %21:sub0[ 7 ]
+# CHECK: Vreg: %21:sub1[ 8 ]
+# CHECK: Vreg: %2[ 79 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %30[ 73 ]
+# CHECK: Vreg: %18[ 53 ]
+# CHECK: Vreg: %32[ 27 ]
+# CHECK: Vreg: %20:sub0[ 69 ]
+# CHECK: Vreg: %20:sub1[ 70 ]
+# CHECK: Vreg: %1[ 61 ]
+# CHECK: Vreg: %162[ LoopTag+5 ]
+# CHECK: Vreg: %22[ 97 ]
+# CHECK: Vreg: %3[ 85 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 17 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Vreg: %19:sub0[ 95 ]
+# CHECK: Vreg: %19:sub1[ 96 ]
+# CHECK: Instr: %34:sreg_32 = SI_IF_BREAK killed %174, killed %33, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %52[ LoopTag+4 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21:sub0[ 6 ]
+# CHECK: Vreg: %21:sub1[ 7 ]
+# CHECK: Vreg: %2[ 78 ]
+# CHECK: Vreg: %4[ 99 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %18[ 52 ]
+# CHECK: Vreg: %32[ 26 ]
+# CHECK: Vreg: %20:sub0[ 68 ]
+# CHECK: Vreg: %20:sub1[ 69 ]
+# CHECK: Vreg: %1[ 60 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %162[ LoopTag+4 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 84 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 16 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Vreg: %19:sub0[ 94 ]
+# CHECK: Vreg: %19:sub1[ 95 ]
+# CHECK: Instr: SI_LOOP %34, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %52[ LoopTag+3 ]
+# CHECK: Vreg: %21:sub0[ 5 ]
+# CHECK: Vreg: %21:sub1[ 6 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %30[ 71 ]
+# CHECK: Vreg: %18[ 51 ]
+# CHECK: Vreg: %32[ 25 ]
+# CHECK: Vreg: %20:sub0[ 67 ]
+# CHECK: Vreg: %20:sub1[ 68 ]
+# CHECK: Vreg: %1[ 59 ]
+# CHECK: Vreg: %162[ LoopTag+3 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22[ 95 ]
+# CHECK: Vreg: %3[ 83 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %17[ 15 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Vreg: %19:sub0[ 93 ]
+# CHECK: Vreg: %19:sub1[ 94 ]
+# CHECK: Instr: S_BRANCH %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %52[ LoopTag+2 ]
+# CHECK: Vreg: %21:sub0[ 4 ]
+# CHECK: Vreg: %21:sub1[ 5 ]
+# CHECK: Vreg: %2[ 76 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %18[ 50 ]
+# CHECK: Vreg: %32[ 24 ]
+# CHECK: Vreg: %20:sub0[ 66 ]
+# CHECK: Vreg: %20:sub1[ 67 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %162[ LoopTag+2 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22[ 94 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19:sub0[ 92 ]
+# CHECK: Vreg: %19:sub1[ 93 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %52[ LoopTag+2 ]
+# CHECK: Vreg: %21:sub0[ 4 ]
+# CHECK: Vreg: %21:sub1[ 5 ]
+# CHECK: Vreg: %2[ 76 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %18[ 50 ]
+# CHECK: Vreg: %32[ 24 ]
+# CHECK: Vreg: %20:sub0[ 66 ]
+# CHECK: Vreg: %20:sub1[ 67 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %162[ LoopTag+2 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22[ 94 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19:sub0[ 92 ]
+# CHECK: Vreg: %19:sub1[ 93 ]
+# CHECK: --- MBB_15 ---
+# CHECK: Instr: SI_END_CF killed %34, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %162[ 1 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Instr: %175:vgpr_32 = V_ADD_U32_e64 killed %162, killed %52, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %162[ 0 ]
+# CHECK: Instr: %176:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %175, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %175[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %176
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %176[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test14 (ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, ptr addrspace(1) %p4, ptr addrspace(1) %p5, ptr addrspace(1) %p6, i32 %TC1, i32 %TC2, i32 %TC3, i32 %TC4, i32 %Val) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  %add1 = add i32 %ld1, 100
+  br label %1
+  1:
+  %phi.inc1 = phi i32 [ 0, %0 ], [ %inc1, %11 ]
+  %phi.div = phi i32 [ %ld1, %0 ], [ %phi3, %11 ]
+  %sext1 = sext i32 %phi.inc1 to i64
+  %gep1 = getelementptr inbounds i64, ptr addrspace(1) %p2, i64 %sext1
+  %ld2 = load i32, ptr addrspace(1) %gep1, align 1
+  store i32 %phi.div, ptr addrspace(1) %p6
+  br label %2
+  2:
+  %phi.inc2 = phi i32 [ 2, %1 ], [ %inc2, %10 ]
+  %phi.mul = phi i32 [ %ld1, %1 ], [ %mul4, %10 ]
+  %mul1 = mul i32 %phi.mul, %phi.inc2
+  %sext2 = sext i32 %phi.inc2 to i64
+  %gep2 = getelementptr inbounds i64, ptr addrspace(1) %p2, i64 %sext2
+  store i32 %mul1, ptr addrspace(1) %gep2
+  %cond1 = icmp ult i32 %mul1, %Val
+  br label %3
+  3:
+  %phi.inc3 = phi i32 [ 10, %2 ], [ %inc3, %9 ]
+  %cond2 = icmp ult i32 %phi.inc3, %Val
+  br i1 %cond2, label %4, label %6
+  4:
+  %mul2 = mul i32 %phi.inc2, %phi.inc3
+  store i32 %mul2, ptr addrspace(1) %p5
+  br label %5
+  5:
+  %phi.inc4 = phi i32 [ 20, %4 ], [ %inc4, %5 ]
+  %inc4 = add i32 %phi.inc4, 1
+  %mul5 = mul i32 %phi.inc4, %inc4
+  %cond4 = icmp ult i32 %inc4, %TC4
+  br i1 %cond4, label %5, label %7
+  6:
+  %mul3 = mul i32 %phi.inc1, %phi.inc3
+  store i32 %mul3, ptr addrspace(1) %p5
+  br label %7
+  7:
+  %phi1 = phi i32 [ %phi.inc4, %5 ], [ %phi.inc3, %6 ]
+  %phi2 = phi i32 [ %mul2, %5 ], [ %mul3, %6 ]
+  %phi3 = phi i32 [ %mul5, %5 ], [ %mul1, %6]
+  %div1 = udiv i32 %phi1, %phi.inc2
+  %sext3 = sext i32 %div1 to i64
+  %gep3 = getelementptr inbounds i64, ptr addrspace(1) %p3, i64 %sext3
+  %ld3 = load i32, ptr addrspace(1) %gep3, align 4
+  %add2 = add i32 %phi2, %add1
+  %cond5 = icmp ult i32 %add2, %mul1
+  br i1 %cond5, label %8, label %9
+  8:
+  %div2 = udiv i32 %phi1, %phi.inc1
+  %sext4 = sext i32 %div2 to i64
+  %gep4 = getelementptr inbounds i64, ptr addrspace(1) %p3, i64 %sext4
+  %ld4 = load i32, ptr addrspace(1) %gep4, align 2
+  store i32 %ld4, ptr addrspace(1) %p1
+  br label %9
+  9:
+  %mul4 = phi i32 [ %phi2, %7 ], [ %mul1, %8 ]
+  %phi4 = phi i32 [ %ld3, %7 ], [ %ld4, %8 ]
+  %phi5 = phi i32 [ %div1, %7 ], [ %div2, %8 ]
+  %phi6 = phi i32 [ %phi3, %7 ], [ %ld4, %8 ]
+  %inc3 = add i32 %phi.inc3, 1
+  %cond3 = icmp ult i32 %inc3, %TC3
+  br i1 %cond3, label %3, label %10
+  10:
+  %inc2 = add i32 %phi.inc2, 1
+  %cond6 = icmp ult i32 %inc2, %TC2
+  br i1 %cond6, label %2, label %11
+  11:
+  %inc1 = add i32 %phi.inc1, 1
+  %add3 = add i32 %ld2, %inc1
+  %sext5 = sext i32 %phi5 to i64
+  %gep5 = getelementptr inbounds i64, ptr addrspace(1) %p4, i64 %sext5
+  store i32 %add3, ptr addrspace(1) %gep5, align 2
+  %cond7 = icmp ult i32 %inc1, %TC1
+  br i1 %cond7, label %1, label %12
+  12:
+  %add4 = add i32 %phi4, %ld2
+  ret i32 %add4
+  }
+...
+
+---
+name:            test14
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16
+  
+    %76:vgpr_32 = COPY killed $vgpr16
+    %75:vgpr_32 = COPY killed $vgpr15
+    %74:vgpr_32 = COPY killed $vgpr14
+    %73:vgpr_32 = COPY killed $vgpr13
+    %72:vgpr_32 = COPY killed $vgpr12
+    %71:vgpr_32 = COPY killed $vgpr11
+    %70:vgpr_32 = COPY killed $vgpr10
+    %69:vgpr_32 = COPY killed $vgpr9
+    %68:vgpr_32 = COPY killed $vgpr8
+    %67:vgpr_32 = COPY killed $vgpr7
+    %66:vgpr_32 = COPY killed $vgpr6
+    %65:vgpr_32 = COPY killed $vgpr5
+    %64:vgpr_32 = COPY killed $vgpr4
+    %63:vgpr_32 = COPY killed $vgpr3
+    %62:vgpr_32 = COPY killed $vgpr2
+    %61:vgpr_32 = COPY killed $vgpr1
+    %60:vgpr_32 = COPY killed $vgpr0
+    %215:vreg_64 = REG_SEQUENCE killed %70, %subreg.sub0, killed %71, %subreg.sub1
+    %214:vreg_64 = REG_SEQUENCE killed %68, %subreg.sub0, killed %69, %subreg.sub1
+    %213:vreg_64 = REG_SEQUENCE killed %66, %subreg.sub0, killed %67, %subreg.sub1
+    %212:vreg_64 = REG_SEQUENCE killed %64, %subreg.sub0, killed %65, %subreg.sub1
+    %211:vreg_64 = REG_SEQUENCE killed %62, %subreg.sub0, killed %63, %subreg.sub1
+    %210:vreg_64 = REG_SEQUENCE killed %60, %subreg.sub0, killed %61, %subreg.sub1
+    %90:vgpr_32 = GLOBAL_LOAD_UBYTE %210, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %92:vgpr_32 = GLOBAL_LOAD_UBYTE %210, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %95:vgpr_32 = V_LSHL_OR_B32_e64 killed %92, 8, killed %90, implicit $exec
+    %96:vgpr_32 = GLOBAL_LOAD_UBYTE %210, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %98:vgpr_32 = GLOBAL_LOAD_UBYTE %210, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %100:vgpr_32 = V_LSHL_OR_B32_e64 killed %98, 8, killed %96, implicit $exec
+    %0:vgpr_32 = V_LSHL_OR_B32_e64 killed %100, 16, killed %95, implicit $exec
+    %1:vgpr_32 = V_ADD_U32_e64 100, %0, 0, implicit $exec
+    %83:sreg_32 = S_MOV_B32 0
+    %158:sreg_32 = S_MOV_B32 2
+  
+  bb.1:
+    successors: %bb.2(0x80000000)
+  
+    %2:sreg_32 = PHI %83, %bb.0, %56, %bb.14
+    %3:sreg_32 = PHI %83, %bb.0, %55, %bb.14
+    %4:vgpr_32 = PHI %0, %bb.0, %20, %bb.14
+    %105:sreg_32_xm0 = S_ASHR_I32 %3, 31, implicit-def dead $scc
+    %107:sreg_64 = REG_SEQUENCE %3, %subreg.sub0, killed %105, %subreg.sub1
+    %109:sreg_64 = nsw S_LSHL_B64 killed %107, 3, implicit-def dead $scc
+    %219:vgpr_32, %221:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %211.sub0, %109.sub0, 0, implicit $exec
+    %220:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %109.sub1, %211.sub1, killed %221, 0, implicit $exec
+    %110:vreg_64 = REG_SEQUENCE killed %219, %subreg.sub0, killed %220, %subreg.sub1
+    %111:vgpr_32 = GLOBAL_LOAD_UBYTE %110, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+    %112:vgpr_32 = GLOBAL_LOAD_UBYTE %110, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+    %114:vgpr_32 = V_LSHL_OR_B32_e64 killed %112, 8, killed %111, implicit $exec
+    %115:vgpr_32 = GLOBAL_LOAD_UBYTE %110, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+    %116:vgpr_32 = GLOBAL_LOAD_UBYTE killed %110, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+    %117:vgpr_32 = V_LSHL_OR_B32_e64 killed %116, 8, killed %115, implicit $exec
+    %5:vgpr_32 = V_LSHL_OR_B32_e64 killed %117, 16, killed %114, implicit $exec
+    GLOBAL_STORE_DWORD %215, killed %4, 0, 0, implicit $exec :: (store (s32) into %ir.p6, addrspace 1)
+    %119:sgpr_32 = S_CVT_F32_U32 %3, implicit $mode
+    %120:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %119, 0, 0, implicit $mode, implicit $exec
+    %123:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %120, implicit $exec
+    %122:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %123, 1333788670, implicit $mode
+    %124:sreg_32 = nofpexcept S_CVT_U32_F32 killed %122, implicit $mode
+    %125:sreg_32 = S_SUB_I32 0, %3, implicit-def dead $scc
+    %126:sreg_32 = S_MUL_I32 killed %125, %124
+    %127:sreg_32 = S_MUL_HI_U32 %124, killed %126
+    %128:sreg_32 = S_ADD_I32 killed %124, killed %127, implicit-def dead $scc
+    %130:sreg_64 = REG_SEQUENCE killed %128, %subreg.sub0, undef %83, %subreg.sub1
+  
+  bb.2:
+    successors: %bb.3(0x80000000)
+  
+    %7:sreg_32 = PHI %83, %bb.1, %50, %bb.13
+    %8:sreg_32 = PHI %158, %bb.1, %49, %bb.13
+    %9:vgpr_32 = PHI %0, %bb.1, %39, %bb.13
+    %10:vgpr_32 = V_MUL_LO_U32_e64 killed %9, %8, implicit $exec
+    %133:sreg_32_xm0 = S_ASHR_I32 %8, 31, implicit-def dead $scc
+    %135:sreg_64 = REG_SEQUENCE %8, %subreg.sub0, killed %133, %subreg.sub1
+    %137:sreg_64 = nsw S_LSHL_B64 killed %135, 3, implicit-def dead $scc
+    %222:vgpr_32, %224:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %211.sub0, %137.sub0, 0, implicit $exec
+    %223:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %137.sub1, %211.sub1, killed %224, 0, implicit $exec
+    %138:vreg_64 = REG_SEQUENCE killed %222, %subreg.sub0, killed %223, %subreg.sub1
+    GLOBAL_STORE_DWORD killed %138, %10, 0, 0, implicit $exec :: (store (s32) into %ir.gep2, addrspace 1)
+    %139:sgpr_32 = S_CVT_F32_U32 %8, implicit $mode
+    %140:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %139, 0, 0, implicit $mode, implicit $exec
+    %143:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %140, implicit $exec
+    %142:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %143, 1333788670, implicit $mode
+    %144:sreg_32 = nofpexcept S_CVT_U32_F32 killed %142, implicit $mode
+    %131:sreg_32 = S_MOV_B32 0
+    %145:sreg_32 = S_SUB_I32 0, %8, implicit-def dead $scc
+    %146:sreg_32 = S_MUL_I32 killed %145, %144
+    %147:sreg_32 = S_MUL_HI_U32 %144, killed %146
+    %148:sreg_32 = S_ADD_I32 killed %144, killed %147, implicit-def dead $scc
+    %150:sreg_64 = REG_SEQUENCE killed %148, %subreg.sub0, undef %83, %subreg.sub1
+    %132:sreg_32 = S_MOV_B32 10
+  
+  bb.3:
+    successors: %bb.8(0x40000000), %bb.4(0x40000000)
+  
+    %12:sreg_32 = PHI %131, %bb.2, %43, %bb.12
+    %13:sreg_32 = PHI %132, %bb.2, %42, %bb.12
+    %152:sreg_32 = V_CMP_GE_U32_e64 %13, %76, implicit $exec
+    %14:sreg_32 = SI_IF killed %152, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.8
+  
+  bb.4:
+    successors: %bb.5(0x40000000), %bb.6(0x40000000)
+  
+    %15:vgpr_32 = PHI undef %151:vgpr_32, %bb.3, %10, %bb.8
+    %209:vgpr_32 = PHI undef %151:vgpr_32, %bb.3, %153, %bb.8
+    %207:vgpr_32 = PHI undef %151:vgpr_32, %bb.3, %208, %bb.8
+    %18:sreg_32 = SI_ELSE killed %14, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.5
+  
+  bb.5:
+    successors: %bb.7(0x80000000)
+  
+    %19:sreg_32 = S_MUL_I32 %8, %13
+    %156:vgpr_32 = COPY %19
+    GLOBAL_STORE_DWORD %214, killed %156, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+    %155:sreg_32 = S_MOV_B32 19
+    %154:sreg_32 = S_MOV_B32 0
+    S_BRANCH %bb.7
+  
+  bb.6:
+    successors: %bb.10(0x80000000)
+  
+    %20:vgpr_32 = PHI %15, %bb.4, %32, %bb.9
+    %21:vgpr_32 = PHI %209, %bb.4, %216, %bb.9
+    %22:vgpr_32 = PHI %207, %bb.4, %217, %bb.9
+    SI_END_CF killed %18, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.10
+  
+  bb.7:
+    successors: %bb.9(0x04000000), %bb.7(0x7c000000)
+  
+    %23:sreg_32 = PHI %154, %bb.5, %27, %bb.7
+    %24:sreg_32 = PHI %155, %bb.5, %25, %bb.7
+    %25:sreg_32 = nuw S_ADD_I32 %24, 1, implicit-def dead $scc
+    %26:sreg_32 = S_ADD_I32 killed %24, 2, implicit-def dead $scc
+    %159:sreg_32 = V_CMP_GE_U32_e64 %26, %75, implicit $exec
+    %27:sreg_32 = SI_IF_BREAK killed %159, killed %23, implicit-def dead $scc
+    %217:vgpr_32 = COPY %25, implicit $exec
+    %218:vgpr_32 = COPY killed %26, implicit $exec
+    SI_LOOP %27, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.9
+  
+  bb.8:
+    successors: %bb.4(0x80000000)
+  
+    %28:sreg_32 = S_MUL_I32 %3, %13
+    %153:vgpr_32 = COPY killed %28
+    GLOBAL_STORE_DWORD %214, %153, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+    %208:vgpr_32 = COPY %13, implicit $exec
+    S_BRANCH %bb.4
+  
+  bb.9:
+    successors: %bb.6(0x80000000)
+  
+    SI_END_CF killed %27, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %32:vgpr_32 = V_MUL_LO_U32_e64 %217, killed %218, implicit $exec
+    %216:vgpr_32 = COPY killed %19, implicit $exec
+    S_BRANCH %bb.6
+  
+  bb.10:
+    successors: %bb.11(0x40000000), %bb.12(0x40000000)
+  
+    %163:vgpr_32 = V_MUL_HI_U32_e64 %22, %150.sub0, implicit $exec
+    %164:vgpr_32 = V_MUL_LO_U32_e64 %163, %8, implicit $exec
+    %165:vgpr_32 = V_SUB_U32_e64 %22, killed %164, 0, implicit $exec
+    %166:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %8, %165, implicit $exec
+    %168:vgpr_32 = V_ADD_U32_e64 1, %163, 0, implicit $exec
+    %169:vgpr_32 = V_CNDMASK_B32_e64 0, killed %163, 0, killed %168, %166, implicit $exec
+    %170:vgpr_32 = V_SUBREV_U32_e64 %8, %165, 0, implicit $exec
+    %171:vgpr_32 = V_CNDMASK_B32_e64 0, killed %165, 0, killed %170, killed %166, implicit $exec
+    %172:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %8, killed %171, implicit $exec
+    %173:vgpr_32 = V_ADD_U32_e64 1, %169, 0, implicit $exec
+    %34:vgpr_32 = V_CNDMASK_B32_e64 0, killed %169, 0, killed %173, killed %172, implicit $exec
+    %174:vgpr_32 = V_ASHRREV_I32_e64 31, %34, implicit $exec
+    %176:vreg_64 = REG_SEQUENCE %34, %subreg.sub0, killed %174, %subreg.sub1
+    %177:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %176, implicit $exec
+    %225:vgpr_32, %227:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %212.sub0, %177.sub0, 0, implicit $exec
+    %226:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %212.sub1, killed %177.sub1, killed %227, 0, implicit $exec
+    %178:vreg_64 = REG_SEQUENCE killed %225, %subreg.sub0, killed %226, %subreg.sub1
+    %35:vgpr_32 = GLOBAL_LOAD_DWORD killed %178, 0, 0, implicit $exec :: (load (s32) from %ir.gep3, addrspace 1)
+    %179:vgpr_32 = V_ADD_U32_e64 %21, %1, 0, implicit $exec
+    %180:sreg_32 = V_CMP_LT_U32_e64 killed %179, %10, implicit $exec
+    %36:sreg_32 = SI_IF killed %180, %bb.12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.11
+  
+  bb.11:
+    successors: %bb.12(0x80000000)
+  
+    %181:vgpr_32 = V_MUL_HI_U32_e64 %22, %130.sub0, implicit $exec
+    %182:vgpr_32 = V_MUL_LO_U32_e64 %181, %3, implicit $exec
+    %183:vgpr_32 = V_SUB_U32_e64 killed %22, killed %182, 0, implicit $exec
+    %184:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %3, %183, implicit $exec
+    %185:vgpr_32 = V_ADD_U32_e64 1, %181, 0, implicit $exec
+    %186:vgpr_32 = V_CNDMASK_B32_e64 0, killed %181, 0, killed %185, %184, implicit $exec
+    %187:vgpr_32 = V_SUBREV_U32_e64 %3, %183, 0, implicit $exec
+    %188:vgpr_32 = V_CNDMASK_B32_e64 0, killed %183, 0, killed %187, killed %184, implicit $exec
+    %189:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %3, killed %188, implicit $exec
+    %190:vgpr_32 = V_ADD_U32_e64 1, %186, 0, implicit $exec
+    %37:vgpr_32 = V_CNDMASK_B32_e64 0, killed %186, 0, killed %190, killed %189, implicit $exec
+    %191:vgpr_32 = V_ASHRREV_I32_e64 31, %37, implicit $exec
+    %192:vreg_64 = REG_SEQUENCE %37, %subreg.sub0, killed %191, %subreg.sub1
+    %193:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %192, implicit $exec
+    %228:vgpr_32, %230:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %212.sub0, %193.sub0, 0, implicit $exec
+    %229:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %212.sub1, killed %193.sub1, killed %230, 0, implicit $exec
+    %194:vreg_64 = REG_SEQUENCE killed %228, %subreg.sub0, killed %229, %subreg.sub1
+    %195:vgpr_32 = GLOBAL_LOAD_USHORT %194, 0, 0, implicit $exec :: (load (s16) from %ir.gep4, addrspace 1)
+    %196:vgpr_32 = GLOBAL_LOAD_USHORT killed %194, 2, 0, implicit $exec :: (load (s16) from %ir.gep4 + 2, addrspace 1)
+    %38:vgpr_32 = V_LSHL_OR_B32_e64 killed %196, 16, killed %195, implicit $exec
+    GLOBAL_STORE_DWORD %210, %38, 0, 0, implicit $exec :: (store (s32) into %ir.p1, addrspace 1)
+  
+  bb.12:
+    successors: %bb.13(0x04000000), %bb.3(0x7c000000)
+  
+    %39:vgpr_32 = PHI %21, %bb.10, %10, %bb.11
+    %40:vgpr_32 = PHI %35, %bb.10, %38, %bb.11
+    %41:vgpr_32 = PHI %34, %bb.10, %37, %bb.11
+    SI_END_CF killed %36, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %42:sreg_32 = S_ADD_I32 killed %13, 1, implicit-def dead $scc
+    %197:sreg_32 = V_CMP_GE_U32_e64 %42, %74, implicit $exec
+    %43:sreg_32 = SI_IF_BREAK killed %197, killed %12, implicit-def dead $scc
+    SI_LOOP %43, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.13
+  
+  bb.13:
+    successors: %bb.14(0x04000000), %bb.2(0x7c000000)
+  
+    SI_END_CF killed %43, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %49:sreg_32 = S_ADD_I32 killed %8, 1, implicit-def dead $scc
+    %198:sreg_32 = V_CMP_GE_U32_e64 %49, %73, implicit $exec
+    %50:sreg_32 = SI_IF_BREAK killed %198, killed %7, implicit-def dead $scc
+    SI_LOOP %50, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.14
+  
+  bb.14:
+    successors: %bb.15(0x04000000), %bb.1(0x7c000000)
+  
+    SI_END_CF killed %50, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %55:sreg_32 = S_ADD_I32 killed %3, 1, implicit-def dead $scc
+    %199:vgpr_32 = V_ADD_U32_e64 %55, %5, 0, implicit $exec
+    %200:vgpr_32 = V_ASHRREV_I32_e64 31, %41, implicit $exec
+    %201:vreg_64 = REG_SEQUENCE killed %41, %subreg.sub0, killed %200, %subreg.sub1
+    %202:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %201, implicit $exec
+    %231:vgpr_32, %233:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %213.sub0, %202.sub0, 0, implicit $exec
+    %232:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %213.sub1, killed %202.sub1, killed %233, 0, implicit $exec
+    %203:vreg_64 = REG_SEQUENCE killed %231, %subreg.sub0, killed %232, %subreg.sub1
+    GLOBAL_STORE_SHORT_D16_HI %203, %199, 2, 0, implicit $exec :: (store (s16) into %ir.gep5 + 2, addrspace 1)
+    GLOBAL_STORE_SHORT killed %203, killed %199, 0, 0, implicit $exec :: (store (s16) into %ir.gep5, addrspace 1)
+    %204:sreg_32 = V_CMP_GE_U32_e64 %55, %72, implicit $exec
+    %56:sreg_32 = SI_IF_BREAK killed %204, killed %2, implicit-def dead $scc
+    SI_LOOP %56, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.15
+  
+  bb.15:
+    SI_END_CF killed %56, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %205:vgpr_32 = V_ADD_U32_e64 killed %40, killed %5, 0, implicit $exec
+    %206:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %205, implicit $exec
+    $sgpr0 = COPY killed %206
+    SI_RETURN_TO_EPILOG killed $sgpr0
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/multi_exit_loop_followed_by_simple_loop.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/multi_exit_loop_followed_by_simple_loop.mir
new file mode 100644
index 0000000000000..9507b7dc52669
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/multi_exit_loop_followed_by_simple_loop.mir
@@ -0,0 +1,1380 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#           bb.0.entry
+#               |
+#       bb.1.loop1.header<---+
+#          /        |        |
+#bb.4.loop1.latch2  |        |
+#          \        |        |
+#           bb.2.Flow        |
+#           /       |        |
+#bb.3.loop1.latch1  |        |
+#           \       |        |
+#           bb.5.Flow1-------+
+#               |
+#            bb.6.bb
+#               |
+#           bb.7.loop2<------+
+#               |            |
+#               +------------+
+#               |
+#           bb.8.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test7 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr9
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 38 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %2[ 28 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %4[ 5 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %2[ 25 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %6[ 4 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %2[ 24 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Instr: %9:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Instr: %10:vreg_64 = REG_SEQUENCE killed %5, %subreg.sub0, killed %4, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %2[ 22 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %11:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, killed %6, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %2[ 21 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %10[ 25 ]
+# CHECK: Instr: %12:vreg_64 = REG_SEQUENCE killed %9, %subreg.sub0, killed %8, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %11[ 16 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %10[ 24 ]
+# CHECK: Instr: %13:vgpr_32 = V_AND_B32_e64 1, killed %3, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %10[ 23 ]
+# CHECK: Vreg: %12[ 2 ]
+# CHECK: Instr: %14:sreg_32 = V_CMP_NE_U32_e64 1, killed %13, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %2[ 18 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %10[ 22 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: %15:vgpr_32 = GLOBAL_LOAD_UBYTE %12, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %14[ 11 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %11[ 13 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %10[ 21 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %16:vgpr_32 = GLOBAL_LOAD_UBYTE %12, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %14[ 10 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %11[ 12 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %10[ 20 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %17:vgpr_32 = V_LSHL_OR_B32_e64 killed %16, 8, killed %15, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 22 ]
+# CHECK: Vreg: %14[ 9 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %10[ 19 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: %18:vgpr_32 = GLOBAL_LOAD_UBYTE %12, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 21 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %10[ 18 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %19:vgpr_32 = GLOBAL_LOAD_UBYTE killed %12, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 20 ]
+# CHECK: Vreg: %14[ 7 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %11[ 9 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %10[ 17 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %20:vgpr_32 = V_LSHL_OR_B32_e64 killed %19, 8, killed %18, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 19 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %10[ 16 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %21:vgpr_32 = V_LSHL_OR_B32_e64 killed %20, 16, killed %17, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 18 ]
+# CHECK: Vreg: %14[ 5 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %11[ 7 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %10[ 15 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: %22:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %14[ 4 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Instr: %23:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %11[ 5 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %10[ 13 ]
+# CHECK: Instr: %24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %25:sreg_32 = PHI %23, %bb.0, %26, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+12 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %27:vgpr_32 = PHI %24, %bb.0, %28, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+12 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %29:vgpr_32 = PHI %22, %bb.0, %30, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+12 ]
+# CHECK: Instr: %31:vgpr_32 = PHI %21, %bb.0, %32, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %10[ LoopTag+12 ]
+# CHECK: Instr: %33:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+14 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %10[ LoopTag+11 ]
+# CHECK: Vreg: %31[ LoopTag+10 ]
+# CHECK: Instr: %34:sreg_32 = SI_IF %14, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+13 ]
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10[ LoopTag+10 ]
+# CHECK: Vreg: %31[ LoopTag+9 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %35:sreg_32 = PHI %33, %bb.1, %36, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Instr: %37:vgpr_32 = PHI undef %38:vgpr_32, %bb.1, %39, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Instr: %40:vgpr_32 = PHI undef %38:vgpr_32, %bb.1, %41, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Instr: %42:vgpr_32 = PHI undef %38:vgpr_32, %bb.1, %43, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Instr: %44:vgpr_32 = PHI undef %38:vgpr_32, %bb.1, %45, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Instr: %46:vgpr_32 = PHI %29, %bb.1, undef %47:vgpr_32, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %44[ 2 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Instr: %48:vgpr_32 = PHI %27, %bb.1, undef %49:vgpr_32, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %44[ 2 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %46[ 3 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Instr: %50:sreg_32 = SI_ELSE killed %34, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+11 ]
+# CHECK: Vreg: %14[ 7 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %11[ 9 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %44[ 1 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %46[ 2 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %48[ 3 ]
+# CHECK: Vreg: %10[ LoopTag+8 ]
+# CHECK: Vreg: %31[ LoopTag+7 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %10[ LoopTag+7 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %10[ LoopTag+7 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %51:vgpr_32 = V_SUB_U32_e64 %21, killed %46, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+17 ]
+# CHECK: Vreg: %14[ 13 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %10[ LoopTag+14 ]
+# CHECK: Vreg: %50[ 8 ]
+# CHECK: Vreg: %31[ LoopTag+13 ]
+# CHECK: Instr: %52:vgpr_32 = V_ADD_U32_e64 1, killed %48, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+16 ]
+# CHECK: Vreg: %14[ 12 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %35[ 3 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %51[ 6 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+13 ]
+# CHECK: Vreg: %50[ 7 ]
+# CHECK: Vreg: %31[ LoopTag+12 ]
+# CHECK: Instr: %53:sreg_32 = V_CMP_GE_U32_e64 %52, %2, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 11 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %11[ 13 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %51[ 5 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %10[ LoopTag+12 ]
+# CHECK: Vreg: %50[ 6 ]
+# CHECK: Vreg: %31[ LoopTag+11 ]
+# CHECK: Instr: %54:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+14 ]
+# CHECK: Vreg: %52[ 4 ]
+# CHECK: Vreg: %14[ 10 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %11[ 12 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %51[ 4 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %53[ 2 ]
+# CHECK: Vreg: %10[ LoopTag+11 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %31[ LoopTag+10 ]
+# CHECK: Instr: %55:sreg_32 = S_ANDN2_B32 killed %35, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+13 ]
+# CHECK: Vreg: %52[ 3 ]
+# CHECK: Vreg: %14[ 9 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %54[ 3 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %51[ 3 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %53[ 1 ]
+# CHECK: Vreg: %10[ LoopTag+10 ]
+# CHECK: Vreg: %50[ 4 ]
+# CHECK: Vreg: %31[ LoopTag+9 ]
+# CHECK: Instr: %56:sreg_32 = S_AND_B32 killed %53, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %52[ 2 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %54[ 2 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %51[ 2 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %55[ 1 ]
+# CHECK: Vreg: %50[ 3 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Instr: %57:sreg_32 = S_OR_B32 killed %55, killed %56, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+11 ]
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %14[ 7 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %54[ 1 ]
+# CHECK: Vreg: %11[ 9 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %51[ 1 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %10[ LoopTag+8 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %50[ 2 ]
+# CHECK: Vreg: %31[ LoopTag+7 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %10[ LoopTag+7 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %10[ LoopTag+7 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %43:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, implicit $exec :: (load (s32) from %ir.p2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+18 ]
+# CHECK: Vreg: %14[ 14 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %25[ 10 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10[ LoopTag+15 ]
+# CHECK: Vreg: %31[ LoopTag+14 ]
+# CHECK: Instr: %39:vgpr_32 = V_ADD_U32_e64 1, killed %29, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+17 ]
+# CHECK: Vreg: %14[ 13 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+14 ]
+# CHECK: Vreg: %43[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+13 ]
+# CHECK: Instr: %45:vgpr_32 = V_ADD_U32_e64 %43, %39, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+16 ]
+# CHECK: Vreg: %14[ 12 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %10[ LoopTag+13 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+12 ]
+# CHECK: Instr: %58:sreg_32 = V_CMP_GE_U32_e64 %39, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %14[ 11 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %11[ 13 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %10[ LoopTag+12 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %31[ LoopTag+11 ]
+# CHECK: Instr: %41:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+14 ]
+# CHECK: Vreg: %45[ 2 ]
+# CHECK: Vreg: %14[ 10 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %11[ 12 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %58[ 1 ]
+# CHECK: Vreg: %39[ 2 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %10[ LoopTag+11 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %31[ LoopTag+10 ]
+# CHECK: Instr: %36:sreg_32 = S_ORN2_B32 killed %58, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+13 ]
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %14[ 9 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %10[ LoopTag+10 ]
+# CHECK: Vreg: %43[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+9 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %10[ LoopTag+9 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %59:sreg_32 = PHI %35, %bb.2, %57, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %10[ LoopTag+7 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Instr: %30:vgpr_32 = PHI %37, %bb.2, %54, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %59[ 2 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %10[ LoopTag+7 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: Instr: %28:vgpr_32 = PHI %40, %bb.2, %52, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %59[ 2 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %10[ LoopTag+7 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: Instr: %60:vgpr_32 = PHI %42, %bb.2, %21, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %59[ 2 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %10[ LoopTag+7 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: Instr: %32:vgpr_32 = PHI %44, %bb.2, %51, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %59[ 2 ]
+# CHECK: Vreg: %21[ LoopTag+18 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %10[ LoopTag+7 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: Instr: SI_END_CF killed %50, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+9 ]
+# CHECK: Vreg: %14[ 5 ]
+# CHECK: Vreg: %59[ 1 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %28[ 3 ]
+# CHECK: Vreg: %30[ 3 ]
+# CHECK: Vreg: %11[ 7 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %32[ 3 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %60[ LoopTag+16 ]
+# CHECK: Vreg: %10[ LoopTag+6 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+5 ]
+# CHECK: Instr: %26:sreg_32 = SI_IF_BREAK killed %59, killed %25, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+8 ]
+# CHECK: Vreg: %14[ 4 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %21[ LoopTag+16 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %28[ 2 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %10[ LoopTag+5 ]
+# CHECK: Vreg: %31[ LoopTag+4 ]
+# CHECK: Instr: SI_LOOP %26, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+7 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %21[ LoopTag+15 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %11[ 5 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %10[ LoopTag+4 ]
+# CHECK: Vreg: %31[ LoopTag+3 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+6 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %21[ LoopTag+14 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %60[ LoopTag+13 ]
+# CHECK: Vreg: %10[ LoopTag+3 ]
+# CHECK: Vreg: %31[ LoopTag+2 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+6 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %21[ LoopTag+14 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %60[ LoopTag+13 ]
+# CHECK: Vreg: %10[ LoopTag+3 ]
+# CHECK: Vreg: %31[ LoopTag+2 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: SI_END_CF killed %26, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %60[ 12 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: Instr: %61:vgpr_32 = V_MUL_LO_U32_e64 %32, %31, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %60[ 11 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %10, %61, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %60[ 10 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %62:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %61[ 9 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %60[ 9 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %61[ 9 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %60[ 9 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: %63:sreg_32 = PHI %62, %bb.6, %64, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %21[ LoopTag+10 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+9 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %60[ LoopTag+9 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %65:sreg_32 = PHI %62, %bb.6, %66, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %21[ LoopTag+10 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+9 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %60[ LoopTag+9 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %67:vgpr_32 = PHI %32, %bb.6, %31, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %21[ LoopTag+10 ]
+# CHECK: Vreg: %61[ LoopTag+9 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %60[ LoopTag+9 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %66:sreg_32 = S_ADD_I32 killed %65, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %21[ LoopTag+9 ]
+# CHECK: Vreg: %61[ LoopTag+8 ]
+# CHECK: Vreg: %63[ 2 ]
+# CHECK: Vreg: %32[ LoopTag+7 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %60[ LoopTag+8 ]
+# CHECK: Vreg: %67[ LoopTag+7 ]
+# CHECK: Vreg: %31[ 5 ]
+# CHECK: Instr: %68:sreg_32 = V_CMP_GE_U32_e64 %66, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %21[ LoopTag+8 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+7 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %32[ LoopTag+6 ]
+# CHECK: Vreg: %60[ LoopTag+7 ]
+# CHECK: Vreg: %67[ LoopTag+6 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Instr: %64:sreg_32 = SI_IF_BREAK killed %68, killed %63, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %21[ LoopTag+7 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %61[ LoopTag+6 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+5 ]
+# CHECK: Vreg: %60[ LoopTag+6 ]
+# CHECK: Vreg: %67[ LoopTag+5 ]
+# CHECK: Vreg: %31[ 3 ]
+# CHECK: Instr: %69:vgpr_32 = COPY %66, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %21[ LoopTag+6 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+5 ]
+# CHECK: Vreg: %32[ LoopTag+4 ]
+# CHECK: Vreg: %60[ LoopTag+5 ]
+# CHECK: Vreg: %67[ LoopTag+4 ]
+# CHECK: Vreg: %31[ 2 ]
+# CHECK: Instr: SI_LOOP %64, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %21[ LoopTag+5 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %61[ LoopTag+4 ]
+# CHECK: Vreg: %32[ LoopTag+3 ]
+# CHECK: Vreg: %60[ LoopTag+4 ]
+# CHECK: Vreg: %67[ LoopTag+3 ]
+# CHECK: Vreg: %69[ LoopTag+3 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %21[ LoopTag+4 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+3 ]
+# CHECK: Vreg: %32[ LoopTag+2 ]
+# CHECK: Vreg: %60[ LoopTag+3 ]
+# CHECK: Vreg: %67[ LoopTag+2 ]
+# CHECK: Vreg: %69[ LoopTag+2 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %21[ LoopTag+4 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+3 ]
+# CHECK: Vreg: %32[ LoopTag+2 ]
+# CHECK: Vreg: %60[ LoopTag+3 ]
+# CHECK: Vreg: %67[ LoopTag+2 ]
+# CHECK: Vreg: %69[ LoopTag+2 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: SI_END_CF killed %64, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %60[ 2 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Instr: %70:vgpr_32 = V_ADD3_U32_e64 killed %67, killed %69, killed %32, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %60[ 1 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Instr: %71:vgpr_32 = V_ADD3_U32_e64 killed %70, killed %61, killed %60, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Instr: %72:vgpr_32 = V_ADD3_U32_e64 killed %21, killed %71, 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Instr: %73:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %72, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %73
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test7(ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, i1 %cond, i32 %TC1, i32 %TC2, i32 %TC3) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  %add1 = add i32 %ld1, 100
+  br label %1
+  1:
+  %phi.inc1 = phi i32 [ 0, %0 ], [ %inc1, %2 ], [ 0, %3 ]
+  %phi.inc2 = phi i32 [ 10, %0 ], [ 0, %2 ], [ %inc2, %3 ]
+  %phi1 = phi i32 [ %ld1, %0 ], [ %sub, %2 ], [ %add2, %3 ]
+  br i1 %cond, label %2, label %3
+  2:
+  %sub = sub i32 %ld1, %phi.inc2
+  %inc1 = add i32 %phi.inc1, 1
+  %cond1 = icmp ult i32 %inc1, %TC1
+  br i1 %cond1, label %1, label %4
+  3:
+  %ld2 = load i32, ptr addrspace(1) %p2, align 4
+  %inc2 = add i32 %phi.inc2, 1
+  %add2 = add i32 %ld2, %inc2
+  %cond2 = icmp ult i32 %inc2, %TC2
+  br i1 %cond2, label %1, label %4
+  4:
+  %phi2 = phi i32 [ %sub, %2 ], [ %add2, %3 ]
+  %ld3 = phi i32 [ %ld1, %2 ], [ %ld2, %3 ]
+  %mul = mul i32 %phi2, %phi1
+  store i32 %mul, ptr addrspace(1) %p3
+  br label %5
+  5:
+  %phi.inc3 = phi i32 [ 0, %4 ], [ %inc3, %5 ]
+  %phi3 = phi i32 [ %phi2, %4 ], [ %phi1, %5 ]
+  %inc3 = add i32 %phi.inc3, 2
+  %add3 = add i32 %phi3, %inc3
+  %cond3 = icmp ult i32 %inc3, %TC3
+  br i1 %cond3, label %5, label %6
+  6:
+  %add4 = add i32 %add3, %phi2
+  %add5 = add i32 %add4, %mul
+  %add6 = add i32 %add5, %ld3
+  %add7 = add i32 %add6, %add1
+  ret i32 %add7
+  }
+...
+
+---
+name:            test7
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9
+  
+    %48:vgpr_32 = COPY killed $vgpr9
+    %47:vgpr_32 = COPY killed $vgpr8
+    %46:vgpr_32 = COPY killed $vgpr7
+    %45:vgpr_32 = COPY killed $vgpr6
+    %44:vgpr_32 = COPY killed $vgpr5
+    %43:vgpr_32 = COPY killed $vgpr4
+    %42:vgpr_32 = COPY killed $vgpr3
+    %41:vgpr_32 = COPY killed $vgpr2
+    %40:vgpr_32 = COPY killed $vgpr1
+    %39:vgpr_32 = COPY killed $vgpr0
+    %87:vreg_64 = REG_SEQUENCE killed %43, %subreg.sub0, killed %44, %subreg.sub1
+    %86:vreg_64 = REG_SEQUENCE killed %41, %subreg.sub0, killed %42, %subreg.sub1
+    %85:vreg_64 = REG_SEQUENCE killed %39, %subreg.sub0, killed %40, %subreg.sub1
+    %56:vgpr_32 = V_AND_B32_e64 1, killed %45, implicit $exec
+    %57:sreg_32 = V_CMP_NE_U32_e64 1, killed %56, implicit $exec
+    %58:vgpr_32 = GLOBAL_LOAD_UBYTE %85, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %60:vgpr_32 = GLOBAL_LOAD_UBYTE %85, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %63:vgpr_32 = V_LSHL_OR_B32_e64 killed %60, 8, killed %58, implicit $exec
+    %64:vgpr_32 = GLOBAL_LOAD_UBYTE %85, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %66:vgpr_32 = GLOBAL_LOAD_UBYTE killed %85, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %68:vgpr_32 = V_LSHL_OR_B32_e64 killed %66, 8, killed %64, implicit $exec
+    %1:vgpr_32 = V_LSHL_OR_B32_e64 killed %68, 16, killed %63, implicit $exec
+    %52:vgpr_32 = V_MOV_B32_e32 10, implicit $exec
+    %51:sreg_32 = S_MOV_B32 0
+    %88:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  
+  bb.1:
+    successors: %bb.4(0x40000000), %bb.2(0x40000000)
+  
+    %2:sreg_32 = PHI %51, %bb.0, %25, %bb.5
+    %3:vgpr_32 = PHI %88, %bb.0, %21, %bb.5
+    %4:vgpr_32 = PHI %52, %bb.0, %20, %bb.5
+    %5:vgpr_32 = PHI %1, %bb.0, %23, %bb.5
+    %72:sreg_32 = S_MOV_B32 -1
+    %6:sreg_32 = SI_IF %57, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.4
+  
+  bb.2:
+    successors: %bb.3(0x40000000), %bb.5(0x40000000)
+  
+    %11:sreg_32 = PHI %72, %bb.1, %90, %bb.4
+    %7:vgpr_32 = PHI undef %70:vgpr_32, %bb.1, %17, %bb.4
+    %83:vgpr_32 = PHI undef %70:vgpr_32, %bb.1, %84, %bb.4
+    %9:vgpr_32 = PHI undef %70:vgpr_32, %bb.1, %16, %bb.4
+    %10:vgpr_32 = PHI undef %70:vgpr_32, %bb.1, %18, %bb.4
+    %94:vgpr_32 = PHI %4, %bb.1, undef %95:vgpr_32, %bb.4
+    %96:vgpr_32 = PHI %3, %bb.1, undef %97:vgpr_32, %bb.4
+    %12:sreg_32 = SI_ELSE killed %6, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.3
+  
+  bb.3:
+    successors: %bb.5(0x80000000)
+  
+    %13:vgpr_32 = V_SUB_U32_e64 %1, killed %94, 0, implicit $exec
+    %14:vgpr_32 = V_ADD_U32_e64 1, killed %96, 0, implicit $exec
+    %76:sreg_32 = V_CMP_GE_U32_e64 %14, %46, implicit $exec
+    %75:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %92:sreg_32 = S_ANDN2_B32 killed %11, $exec_lo, implicit-def dead $scc
+    %93:sreg_32 = S_AND_B32 killed %76, $exec_lo, implicit-def dead $scc
+    %91:sreg_32 = S_OR_B32 killed %92, killed %93, implicit-def dead $scc
+    S_BRANCH %bb.5
+  
+  bb.4:
+    successors: %bb.2(0x80000000)
+  
+    %16:vgpr_32 = GLOBAL_LOAD_DWORD %86, 0, 0, implicit $exec :: (load (s32) from %ir.p2, addrspace 1)
+    %17:vgpr_32 = V_ADD_U32_e64 1, killed %4, 0, implicit $exec
+    %18:vgpr_32 = V_ADD_U32_e64 %16, %17, 0, implicit $exec
+    %74:sreg_32 = V_CMP_GE_U32_e64 %17, %47, implicit $exec
+    %84:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %90:sreg_32 = S_ORN2_B32 killed %74, $exec_lo, implicit-def dead $scc
+    S_BRANCH %bb.2
+  
+  bb.5:
+    successors: %bb.6(0x04000000), %bb.1(0x7c000000)
+  
+    %24:sreg_32 = PHI %11, %bb.2, %91, %bb.3
+    %20:vgpr_32 = PHI %7, %bb.2, %75, %bb.3
+    %21:vgpr_32 = PHI %83, %bb.2, %14, %bb.3
+    %22:vgpr_32 = PHI %9, %bb.2, %1, %bb.3
+    %23:vgpr_32 = PHI %10, %bb.2, %13, %bb.3
+    SI_END_CF killed %12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %25:sreg_32 = SI_IF_BREAK killed %24, killed %2, implicit-def dead $scc
+    SI_LOOP %25, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.6
+  
+  bb.6:
+    successors: %bb.7(0x80000000)
+  
+    SI_END_CF killed %25, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %30:vgpr_32 = V_MUL_LO_U32_e64 %23, %5, implicit $exec
+    GLOBAL_STORE_DWORD killed %87, %30, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    %77:sreg_32 = S_MOV_B32 0
+  
+  bb.7:
+    successors: %bb.8(0x04000000), %bb.7(0x7c000000)
+  
+    %31:sreg_32 = PHI %77, %bb.6, %35, %bb.7
+    %32:sreg_32 = PHI %77, %bb.6, %34, %bb.7
+    %33:vgpr_32 = PHI %23, %bb.6, %5, %bb.7
+    %34:sreg_32 = S_ADD_I32 killed %32, 2, implicit-def dead $scc
+    %78:sreg_32 = V_CMP_GE_U32_e64 %34, %48, implicit $exec
+    %35:sreg_32 = SI_IF_BREAK killed %78, killed %31, implicit-def dead $scc
+    %89:vgpr_32 = COPY %34, implicit $exec
+    SI_LOOP %35, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.8
+  
+  bb.8:
+    SI_END_CF killed %35, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %79:vgpr_32 = V_ADD3_U32_e64 killed %33, killed %89, killed %23, implicit $exec
+    %80:vgpr_32 = V_ADD3_U32_e64 killed %79, killed %30, killed %22, implicit $exec
+    %81:vgpr_32 = V_ADD3_U32_e64 killed %1, killed %80, 100, implicit $exec
+    %82:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %81, implicit $exec
+    $sgpr0 = COPY killed %82
+    SI_RETURN_TO_EPILOG killed $sgpr0
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
new file mode 100644
index 0000000000000..3e2b6e8a8167a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
@@ -0,0 +1,3948 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#              bb.0.entry
+#                  |
+#          bb.1.loop1.header<-+
+#            /           |    |
+# bb.2.loop2.preheader   |    |
+#           |            |    |
+#    bb.4.loop2.header   |    |
+#       |          |     |    |
+# +---->bb.5.bb1   |     |    |
+# |     |      |   |     |    |
+# | bb.7.loop2 |   |     |    |
+# |   .latch   |   |     |    |
+# |      \     |   |     |    |
+# |  bb.17.Flow11  |     |    |
+# |         \      |     |    |
+# +--------bb.6.Flow10   |    |
+#              |         |    |
+#        bb.18.loop.exit |    |
+#           .guard8  |   |    |
+#             /      |   |    |
+# bb.8.loop1.latch   |   |    |
+#             \      |   |    |
+#          bb.14.Flow13  |    |
+#               \        |    |
+#               bb.3.Flow12---+
+#                    |
+#         bb.15.loop.exit.guard
+#                    |      |
+#bb.16.loop.exit.guard7     |
+#          |        |       |
+# bb.11.side.exit   |       |
+#            \      |       |
+#            bb.12.Flow     |
+#                     \     |
+#                   bb.9.Flow9
+#                    /   |
+#      bb.10.side.exit1  |
+#                    \   |
+#                 bb.13.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test12 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr10
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %2[ 22 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %3[ 65 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %2[ 21 ]
+# CHECK: Vreg: %4[ 54 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %3[ 64 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %5[ 5 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %4[ 52 ]
+# CHECK: Vreg: %6[ 4 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %3[ 62 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %2[ 18 ]
+# CHECK: Vreg: %4[ 51 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %3[ 61 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Instr: %9:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %4[ 50 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %3[ 60 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Instr: %10:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 49 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %3[ 59 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Instr: %11:vreg_64 = REG_SEQUENCE killed %6, %subreg.sub0, killed %5, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %4[ 48 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %12:vreg_64 = REG_SEQUENCE killed %8, %subreg.sub0, killed %7, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %4[ 47 ]
+# CHECK: Vreg: %11[ 42 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %3[ 57 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Instr: %13:vreg_64 = REG_SEQUENCE killed %10, %subreg.sub0, killed %9, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %4[ 46 ]
+# CHECK: Vreg: %11[ 41 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %3[ 56 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %12:sub0[ 18 ]
+# CHECK: Vreg: %12:sub1[ 19 ]
+# CHECK: Instr: %14:vgpr_32 = V_AND_B32_e64 1, killed %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %4[ 45 ]
+# CHECK: Vreg: %11[ 40 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %3[ 55 ]
+# CHECK: Vreg: %12:sub0[ 17 ]
+# CHECK: Vreg: %12:sub1[ 18 ]
+# CHECK: Instr: %15:sreg_32 = V_CMP_EQ_U32_e64 1, killed %14, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %11[ 39 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %3[ 54 ]
+# CHECK: Vreg: %12:sub0[ 16 ]
+# CHECK: Vreg: %12:sub1[ 17 ]
+# CHECK: Instr: %16:vgpr_32 = V_AND_B32_e64 1, killed %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %11[ 38 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: Instr: %17:sreg_32 = V_CMP_EQ_U32_e64 1, killed %16, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %4[ 42 ]
+# CHECK: Vreg: %11[ 37 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %15[ 35 ]
+# CHECK: Vreg: %3[ 52 ]
+# CHECK: Vreg: %12:sub0[ 14 ]
+# CHECK: Vreg: %12:sub1[ 15 ]
+# CHECK: Instr: %18:vgpr_32 = GLOBAL_LOAD_UBYTE %13, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %11[ 36 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %15[ 34 ]
+# CHECK: Vreg: %3[ 51 ]
+# CHECK: Vreg: %17[ 27 ]
+# CHECK: Vreg: %12:sub0[ 13 ]
+# CHECK: Vreg: %12:sub1[ 14 ]
+# CHECK: Instr: %19:vgpr_32 = GLOBAL_LOAD_UBYTE %13, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %4[ 40 ]
+# CHECK: Vreg: %11[ 35 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %15[ 33 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %17[ 26 ]
+# CHECK: Vreg: %12:sub0[ 12 ]
+# CHECK: Vreg: %12:sub1[ 13 ]
+# CHECK: Instr: %20:vgpr_32 = V_LSHL_OR_B32_e64 killed %19, 8, killed %18, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %11[ 34 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %15[ 32 ]
+# CHECK: Vreg: %3[ 49 ]
+# CHECK: Vreg: %17[ 25 ]
+# CHECK: Vreg: %12:sub0[ 11 ]
+# CHECK: Vreg: %12:sub1[ 12 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %21:vgpr_32 = GLOBAL_LOAD_UBYTE %13, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %4[ 38 ]
+# CHECK: Vreg: %11[ 33 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %20[ 3 ]
+# CHECK: Vreg: %15[ 31 ]
+# CHECK: Vreg: %3[ 48 ]
+# CHECK: Vreg: %17[ 24 ]
+# CHECK: Vreg: %12:sub0[ 10 ]
+# CHECK: Vreg: %12:sub1[ 11 ]
+# CHECK: Instr: %22:vgpr_32 = GLOBAL_LOAD_UBYTE killed %13, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %4[ 37 ]
+# CHECK: Vreg: %11[ 32 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %15[ 30 ]
+# CHECK: Vreg: %3[ 47 ]
+# CHECK: Vreg: %17[ 23 ]
+# CHECK: Vreg: %12:sub0[ 9 ]
+# CHECK: Vreg: %12:sub1[ 10 ]
+# CHECK: Instr: %23:vgpr_32 = V_LSHL_OR_B32_e64 killed %22, 8, killed %21, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %4[ 36 ]
+# CHECK: Vreg: %11[ 31 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 46 ]
+# CHECK: Vreg: %17[ 22 ]
+# CHECK: Vreg: %12:sub0[ 8 ]
+# CHECK: Vreg: %12:sub1[ 9 ]
+# CHECK: Instr: %24:vgpr_32 = V_LSHL_OR_B32_e64 killed %23, 16, killed %20, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %4[ 35 ]
+# CHECK: Vreg: %11[ 30 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %15[ 28 ]
+# CHECK: Vreg: %3[ 45 ]
+# CHECK: Vreg: %17[ 21 ]
+# CHECK: Vreg: %12:sub0[ 7 ]
+# CHECK: Vreg: %12:sub1[ 8 ]
+# CHECK: Instr: %25:vgpr_32 = V_MUL_LO_U32_e64 100, %24, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %4[ 34 ]
+# CHECK: Vreg: %11[ 29 ]
+# CHECK: Vreg: %15[ 27 ]
+# CHECK: Vreg: %3[ 44 ]
+# CHECK: Vreg: %17[ 20 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %12:sub0[ 6 ]
+# CHECK: Vreg: %12:sub1[ 7 ]
+# CHECK: Instr: %26:sreg_32 = V_CMP_LT_U32_e64 %25, killed %2, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %4[ 33 ]
+# CHECK: Vreg: %11[ 28 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %15[ 26 ]
+# CHECK: Vreg: %3[ 43 ]
+# CHECK: Vreg: %17[ 19 ]
+# CHECK: Vreg: %24[ 39 ]
+# CHECK: Vreg: %12:sub0[ 5 ]
+# CHECK: Vreg: %12:sub1[ 6 ]
+# CHECK: Instr: %27:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %24[ 38 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %24[ 38 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %28:sreg_32 = PHI undef %29:sreg_32, %bb.0, %30, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %24[ LoopTag+38 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: Instr: %31:sreg_32 = PHI undef %32:sreg_32, %bb.0, %33, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %28[ 26 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %24[ LoopTag+38 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: Instr: %34:sreg_32 = PHI undef %35:sreg_32, %bb.0, %36, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %28[ 26 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %24[ LoopTag+38 ]
+# CHECK: Vreg: %31[ 23 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: Instr: %37:sreg_32 = PHI undef %38:sreg_32, %bb.0, %39, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %28[ 26 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 17 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %24[ LoopTag+38 ]
+# CHECK: Vreg: %31[ 23 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: Instr: %40:sreg_32 = PHI undef %41:sreg_32, %bb.0, %42, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %28[ 26 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %37[ 16 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 17 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %24[ LoopTag+38 ]
+# CHECK: Vreg: %31[ 23 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: Instr: %43:sreg_32 = PHI %27, %bb.0, %44, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %40[ 14 ]
+# CHECK: Vreg: %28[ 26 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %37[ 16 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 17 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %24[ LoopTag+38 ]
+# CHECK: Vreg: %31[ 23 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: Instr: %45:sreg_32 = PHI %27, %bb.0, %46, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %40[ 14 ]
+# CHECK: Vreg: %28[ 26 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %37[ 16 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %34[ 17 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %43[ 21 ]
+# CHECK: Vreg: %24[ LoopTag+38 ]
+# CHECK: Vreg: %31[ 23 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: Instr: %47:sreg_32_xm0 = S_ASHR_I32 %45, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 28 ]
+# CHECK: Vreg: %40[ 13 ]
+# CHECK: Vreg: %28[ 25 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %11[ 26 ]
+# CHECK: Vreg: %37[ 15 ]
+# CHECK: Vreg: %25[ 26 ]
+# CHECK: Vreg: %34[ 16 ]
+# CHECK: Vreg: %15[ 24 ]
+# CHECK: Vreg: %3[ 41 ]
+# CHECK: Vreg: %17[ 17 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %24[ LoopTag+37 ]
+# CHECK: Vreg: %31[ 22 ]
+# CHECK: Vreg: %12:sub0[ 3 ]
+# CHECK: Vreg: %12:sub1[ 4 ]
+# CHECK: Instr: %48:sreg_64 = REG_SEQUENCE %45, %subreg.sub0, killed %47, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 27 ]
+# CHECK: Vreg: %40[ 12 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %28[ 24 ]
+# CHECK: Vreg: %4[ 30 ]
+# CHECK: Vreg: %11[ 25 ]
+# CHECK: Vreg: %37[ 14 ]
+# CHECK: Vreg: %25[ 25 ]
+# CHECK: Vreg: %34[ 15 ]
+# CHECK: Vreg: %15[ 23 ]
+# CHECK: Vreg: %3[ 40 ]
+# CHECK: Vreg: %17[ 16 ]
+# CHECK: Vreg: %43[ 19 ]
+# CHECK: Vreg: %24[ LoopTag+36 ]
+# CHECK: Vreg: %31[ 21 ]
+# CHECK: Vreg: %12:sub0[ 2 ]
+# CHECK: Vreg: %12:sub1[ 3 ]
+# CHECK: Instr: %49:sreg_64 = nsw S_LSHL_B64 killed %48, 3, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 19 ]
+# CHECK: Vreg: %26[ 26 ]
+# CHECK: Vreg: %40[ 11 ]
+# CHECK: Vreg: %28[ 23 ]
+# CHECK: Vreg: %4[ 29 ]
+# CHECK: Vreg: %11[ 24 ]
+# CHECK: Vreg: %37[ 13 ]
+# CHECK: Vreg: %25[ 24 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %3[ 39 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %17[ 15 ]
+# CHECK: Vreg: %43[ 18 ]
+# CHECK: Vreg: %24[ LoopTag+35 ]
+# CHECK: Vreg: %31[ 20 ]
+# CHECK: Vreg: %12:sub0[ 1 ]
+# CHECK: Vreg: %12:sub1[ 2 ]
+# CHECK: Instr: %50:vgpr_32, %51:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %12.sub0, %49.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 18 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %28[ 22 ]
+# CHECK: Vreg: %4[ 28 ]
+# CHECK: Vreg: %49:sub0[ 0 ]
+# CHECK: Vreg: %49:sub1[ 1 ]
+# CHECK: Vreg: %11[ 23 ]
+# CHECK: Vreg: %37[ 12 ]
+# CHECK: Vreg: %25[ 23 ]
+# CHECK: Vreg: %34[ 13 ]
+# CHECK: Vreg: %15[ 21 ]
+# CHECK: Vreg: %3[ 38 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %24[ LoopTag+34 ]
+# CHECK: Vreg: %31[ 19 ]
+# CHECK: Vreg: %12:sub0[ 0 ]
+# CHECK: Vreg: %12:sub1[ 1 ]
+# CHECK: Instr: %52:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %49.sub1, %12.sub1, killed %51, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 17 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %28[ 21 ]
+# CHECK: Vreg: %4[ 27 ]
+# CHECK: Vreg: %49:sub1[ 0 ]
+# CHECK: Vreg: %11[ 22 ]
+# CHECK: Vreg: %37[ 11 ]
+# CHECK: Vreg: %25[ 22 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %34[ 12 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %3[ 37 ]
+# CHECK: Vreg: %17[ 13 ]
+# CHECK: Vreg: %43[ 16 ]
+# CHECK: Vreg: %24[ LoopTag+33 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ 18 ]
+# CHECK: Vreg: %12:sub1[ 0 ]
+# CHECK: Vreg: %12:sub0[ 29 ]
+# CHECK: Instr: %53:vreg_64 = REG_SEQUENCE killed %50, %subreg.sub0, killed %52, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 16 ]
+# CHECK: Vreg: %26[ 23 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %40[ 8 ]
+# CHECK: Vreg: %28[ 20 ]
+# CHECK: Vreg: %4[ 26 ]
+# CHECK: Vreg: %11[ 21 ]
+# CHECK: Vreg: %37[ 10 ]
+# CHECK: Vreg: %25[ 21 ]
+# CHECK: Vreg: %34[ 11 ]
+# CHECK: Vreg: %15[ 19 ]
+# CHECK: Vreg: %3[ 36 ]
+# CHECK: Vreg: %17[ 12 ]
+# CHECK: Vreg: %43[ 15 ]
+# CHECK: Vreg: %24[ LoopTag+32 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %31[ 17 ]
+# CHECK: Vreg: %12:sub0[ 28 ]
+# CHECK: Vreg: %12:sub1[ 29 ]
+# CHECK: Instr: %54:vgpr_32 = GLOBAL_LOAD_UBYTE %53, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 15 ]
+# CHECK: Vreg: %26[ 22 ]
+# CHECK: Vreg: %40[ 7 ]
+# CHECK: Vreg: %28[ 19 ]
+# CHECK: Vreg: %4[ 25 ]
+# CHECK: Vreg: %11[ 20 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %25[ 20 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 10 ]
+# CHECK: Vreg: %15[ 18 ]
+# CHECK: Vreg: %3[ 35 ]
+# CHECK: Vreg: %17[ 11 ]
+# CHECK: Vreg: %43[ 14 ]
+# CHECK: Vreg: %24[ LoopTag+31 ]
+# CHECK: Vreg: %31[ 16 ]
+# CHECK: Vreg: %12:sub0[ 27 ]
+# CHECK: Vreg: %12:sub1[ 28 ]
+# CHECK: Instr: %55:vgpr_32 = GLOBAL_LOAD_UBYTE %53, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 14 ]
+# CHECK: Vreg: %26[ 21 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %28[ 18 ]
+# CHECK: Vreg: %54[ 1 ]
+# CHECK: Vreg: %4[ 24 ]
+# CHECK: Vreg: %11[ 19 ]
+# CHECK: Vreg: %37[ 8 ]
+# CHECK: Vreg: %25[ 19 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %15[ 17 ]
+# CHECK: Vreg: %3[ 34 ]
+# CHECK: Vreg: %17[ 10 ]
+# CHECK: Vreg: %43[ 13 ]
+# CHECK: Vreg: %24[ LoopTag+30 ]
+# CHECK: Vreg: %31[ 15 ]
+# CHECK: Vreg: %12:sub0[ 26 ]
+# CHECK: Vreg: %12:sub1[ 27 ]
+# CHECK: Instr: %56:vgpr_32 = V_LSHL_OR_B32_e64 killed %55, 8, killed %54, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 13 ]
+# CHECK: Vreg: %26[ 20 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %28[ 17 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %4[ 23 ]
+# CHECK: Vreg: %11[ 18 ]
+# CHECK: Vreg: %37[ 7 ]
+# CHECK: Vreg: %25[ 18 ]
+# CHECK: Vreg: %53[ 1 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %15[ 16 ]
+# CHECK: Vreg: %3[ 33 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %17[ 9 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %31[ 14 ]
+# CHECK: Vreg: %12:sub0[ 25 ]
+# CHECK: Vreg: %12:sub1[ 26 ]
+# CHECK: Instr: %57:vgpr_32 = GLOBAL_LOAD_UBYTE %53, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 12 ]
+# CHECK: Vreg: %26[ 19 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %28[ 16 ]
+# CHECK: Vreg: %4[ 22 ]
+# CHECK: Vreg: %11[ 17 ]
+# CHECK: Vreg: %56[ 3 ]
+# CHECK: Vreg: %37[ 6 ]
+# CHECK: Vreg: %25[ 17 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %15[ 15 ]
+# CHECK: Vreg: %3[ 32 ]
+# CHECK: Vreg: %17[ 8 ]
+# CHECK: Vreg: %43[ 11 ]
+# CHECK: Vreg: %24[ LoopTag+28 ]
+# CHECK: Vreg: %31[ 13 ]
+# CHECK: Vreg: %12:sub0[ 24 ]
+# CHECK: Vreg: %12:sub1[ 25 ]
+# CHECK: Instr: %58:vgpr_32 = GLOBAL_LOAD_UBYTE killed %53, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 11 ]
+# CHECK: Vreg: %26[ 18 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %28[ 15 ]
+# CHECK: Vreg: %4[ 21 ]
+# CHECK: Vreg: %11[ 16 ]
+# CHECK: Vreg: %56[ 2 ]
+# CHECK: Vreg: %37[ 5 ]
+# CHECK: Vreg: %25[ 16 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %15[ 14 ]
+# CHECK: Vreg: %3[ 31 ]
+# CHECK: Vreg: %17[ 7 ]
+# CHECK: Vreg: %43[ 10 ]
+# CHECK: Vreg: %24[ LoopTag+27 ]
+# CHECK: Vreg: %31[ 12 ]
+# CHECK: Vreg: %12:sub0[ 23 ]
+# CHECK: Vreg: %12:sub1[ 24 ]
+# CHECK: Vreg: %57[ 1 ]
+# CHECK: Instr: %59:vgpr_32 = V_LSHL_OR_B32_e64 killed %58, 8, killed %57, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 10 ]
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %28[ 14 ]
+# CHECK: Vreg: %4[ 20 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %56[ 1 ]
+# CHECK: Vreg: %37[ 4 ]
+# CHECK: Vreg: %25[ 15 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %15[ 13 ]
+# CHECK: Vreg: %3[ 30 ]
+# CHECK: Vreg: %17[ 6 ]
+# CHECK: Vreg: %43[ 9 ]
+# CHECK: Vreg: %24[ LoopTag+26 ]
+# CHECK: Vreg: %31[ 11 ]
+# CHECK: Vreg: %12:sub0[ 22 ]
+# CHECK: Vreg: %12:sub1[ 23 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Instr: %60:vgpr_32 = V_LSHL_OR_B32_e64 killed %59, 16, killed %56, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 9 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %28[ 13 ]
+# CHECK: Vreg: %4[ 19 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %37[ 3 ]
+# CHECK: Vreg: %25[ 14 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %17[ 5 ]
+# CHECK: Vreg: %43[ 8 ]
+# CHECK: Vreg: %24[ LoopTag+25 ]
+# CHECK: Vreg: %31[ 10 ]
+# CHECK: Vreg: %12:sub0[ 21 ]
+# CHECK: Vreg: %12:sub1[ 22 ]
+# CHECK: Instr: %61:sreg_32 = S_ANDN2_B32 killed %40, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 8 ]
+# CHECK: Vreg: %26[ 15 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %28[ 12 ]
+# CHECK: Vreg: %4[ 18 ]
+# CHECK: Vreg: %11[ 13 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %25[ 13 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %15[ 11 ]
+# CHECK: Vreg: %60[ 26 ]
+# CHECK: Vreg: %3[ 28 ]
+# CHECK: Vreg: %17[ 4 ]
+# CHECK: Vreg: %43[ 7 ]
+# CHECK: Vreg: %24[ LoopTag+24 ]
+# CHECK: Vreg: %31[ 9 ]
+# CHECK: Vreg: %12:sub0[ 20 ]
+# CHECK: Vreg: %12:sub1[ 21 ]
+# CHECK: Instr: %62:sreg_32 = COPY %61
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 7 ]
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %28[ 11 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %4[ 17 ]
+# CHECK: Vreg: %11[ 12 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %25[ 12 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %15[ 10 ]
+# CHECK: Vreg: %60[ 25 ]
+# CHECK: Vreg: %3[ 27 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Vreg: %43[ 6 ]
+# CHECK: Vreg: %24[ LoopTag+23 ]
+# CHECK: Vreg: %31[ 8 ]
+# CHECK: Vreg: %12:sub0[ 19 ]
+# CHECK: Vreg: %12:sub1[ 20 ]
+# CHECK: Instr: %63:sreg_32 = S_OR_B32 killed %37, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 6 ]
+# CHECK: Vreg: %26[ 13 ]
+# CHECK: Vreg: %28[ 10 ]
+# CHECK: Vreg: %61[ 24 ]
+# CHECK: Vreg: %4[ 16 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 9 ]
+# CHECK: Vreg: %60[ 24 ]
+# CHECK: Vreg: %3[ 26 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %62[ 3 ]
+# CHECK: Vreg: %43[ 5 ]
+# CHECK: Vreg: %24[ LoopTag+22 ]
+# CHECK: Vreg: %31[ 7 ]
+# CHECK: Vreg: %12:sub0[ 18 ]
+# CHECK: Vreg: %12:sub1[ 19 ]
+# CHECK: Instr: %64:sreg_32 = S_OR_B32 killed %34, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 5 ]
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %28[ 9 ]
+# CHECK: Vreg: %61[ 23 ]
+# CHECK: Vreg: %4[ 15 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %63[ 2 ]
+# CHECK: Vreg: %25[ 10 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 8 ]
+# CHECK: Vreg: %60[ 23 ]
+# CHECK: Vreg: %3[ 25 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %43[ 4 ]
+# CHECK: Vreg: %24[ LoopTag+21 ]
+# CHECK: Vreg: %31[ 6 ]
+# CHECK: Vreg: %12:sub0[ 17 ]
+# CHECK: Vreg: %12:sub1[ 18 ]
+# CHECK: Instr: %65:sreg_32 = SI_IF %17, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %45[ 4 ]
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %28[ 8 ]
+# CHECK: Vreg: %61[ 22 ]
+# CHECK: Vreg: %4[ 14 ]
+# CHECK: Vreg: %11[ 9 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %15[ 7 ]
+# CHECK: Vreg: %60[ 22 ]
+# CHECK: Vreg: %3[ 24 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %62[ 1 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %24[ LoopTag+20 ]
+# CHECK: Vreg: %31[ 5 ]
+# CHECK: Vreg: %12:sub0[ 16 ]
+# CHECK: Vreg: %12:sub1[ 17 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %61[ 21 ]
+# CHECK: Vreg: %4[ 13 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %60[ 21 ]
+# CHECK: Vreg: %3[ 23 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %61[ 21 ]
+# CHECK: Vreg: %4[ 13 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %60[ 21 ]
+# CHECK: Vreg: %3[ 23 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %66:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 25 ]
+# CHECK: Vreg: %45[ 19 ]
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %28[ 35 ]
+# CHECK: Vreg: %61[ 20 ]
+# CHECK: Vreg: %4[ 12 ]
+# CHECK: Vreg: %11[ 7 ]
+# CHECK: Vreg: %63[ 23 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %65[ 29 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %60[ 20 ]
+# CHECK: Vreg: %3[ 22 ]
+# CHECK: Vreg: %17[ 57 ]
+# CHECK: Vreg: %43[ 30 ]
+# CHECK: Vreg: %24[ LoopTag+47 ]
+# CHECK: Vreg: %31[ 32 ]
+# CHECK: Vreg: %12:sub0[ 43 ]
+# CHECK: Vreg: %12:sub1[ 44 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 24 ]
+# CHECK: Vreg: %45[ 18 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %28[ 34 ]
+# CHECK: Vreg: %61[ 19 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %63[ 22 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %65[ 28 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %60[ 19 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %17[ 56 ]
+# CHECK: Vreg: %43[ 29 ]
+# CHECK: Vreg: %24[ LoopTag+46 ]
+# CHECK: Vreg: %31[ 31 ]
+# CHECK: Vreg: %12:sub0[ 42 ]
+# CHECK: Vreg: %12:sub1[ 43 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ 24 ]
+# CHECK: Vreg: %45[ 18 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %28[ 34 ]
+# CHECK: Vreg: %61[ 19 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %63[ 22 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %65[ 28 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %60[ 19 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %17[ 56 ]
+# CHECK: Vreg: %43[ 29 ]
+# CHECK: Vreg: %24[ LoopTag+46 ]
+# CHECK: Vreg: %31[ 31 ]
+# CHECK: Vreg: %12:sub0[ 42 ]
+# CHECK: Vreg: %12:sub1[ 43 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %36:sreg_32 = PHI %64, %bb.1, %67, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 40 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %11[ 38 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 38 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Instr: %39:sreg_32 = PHI %63, %bb.1, %68, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 40 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %11[ 38 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 38 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Instr: %42:sreg_32 = PHI %62, %bb.1, %69, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 40 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %11[ 38 ]
+# CHECK: Vreg: %25[ 38 ]
+# CHECK: Vreg: %39[ 8 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Instr: %46:sreg_32 = PHI undef %70:sreg_32, %bb.1, %71, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 40 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %42[ 5 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %11[ 38 ]
+# CHECK: Vreg: %25[ 38 ]
+# CHECK: Vreg: %39[ 8 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Instr: %72:vgpr_32 = PHI undef %73:vgpr_32, %bb.1, %74, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 40 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %42[ 5 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %11[ 38 ]
+# CHECK: Vreg: %25[ 38 ]
+# CHECK: Vreg: %39[ 8 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %46[ 11 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Instr: %75:vgpr_32 = PHI undef %73:vgpr_32, %bb.1, %76, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 40 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %42[ 5 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %11[ 38 ]
+# CHECK: Vreg: %25[ 38 ]
+# CHECK: Vreg: %39[ 8 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %46[ 11 ]
+# CHECK: Vreg: %72[ LoopTag+18 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Instr: SI_END_CF killed %65, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 2 ]
+# CHECK: Vreg: %26[ 39 ]
+# CHECK: Vreg: %28[ 6 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %4[ 42 ]
+# CHECK: Vreg: %11[ 37 ]
+# CHECK: Vreg: %75[ LoopTag+16 ]
+# CHECK: Vreg: %25[ 37 ]
+# CHECK: Vreg: %39[ 7 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %46[ 10 ]
+# CHECK: Vreg: %72[ LoopTag+17 ]
+# CHECK: Vreg: %15[ 35 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %3[ 52 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %17[ 28 ]
+# CHECK: Vreg: %43[ 1 ]
+# CHECK: Vreg: %24[ LoopTag+18 ]
+# CHECK: Vreg: %31[ 3 ]
+# CHECK: Vreg: %12:sub0[ 14 ]
+# CHECK: Vreg: %12:sub1[ 15 ]
+# CHECK: Instr: %44:sreg_32 = SI_IF_BREAK %36, killed %43, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %26[ 38 ]
+# CHECK: Vreg: %28[ 5 ]
+# CHECK: Vreg: %42[ 3 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %11[ 36 ]
+# CHECK: Vreg: %75[ LoopTag+15 ]
+# CHECK: Vreg: %25[ 36 ]
+# CHECK: Vreg: %39[ 6 ]
+# CHECK: Vreg: %46[ 9 ]
+# CHECK: Vreg: %72[ LoopTag+16 ]
+# CHECK: Vreg: %15[ 34 ]
+# CHECK: Vreg: %60[ LoopTag+16 ]
+# CHECK: Vreg: %3[ 51 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 27 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %24[ LoopTag+17 ]
+# CHECK: Vreg: %31[ 2 ]
+# CHECK: Vreg: %12:sub0[ 13 ]
+# CHECK: Vreg: %12:sub1[ 14 ]
+# CHECK: Instr: %77:vgpr_32 = COPY killed %45, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 37 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %4[ 40 ]
+# CHECK: Vreg: %11[ 35 ]
+# CHECK: Vreg: %75[ LoopTag+14 ]
+# CHECK: Vreg: %44[ 7 ]
+# CHECK: Vreg: %25[ 35 ]
+# CHECK: Vreg: %39[ 5 ]
+# CHECK: Vreg: %46[ 8 ]
+# CHECK: Vreg: %72[ LoopTag+15 ]
+# CHECK: Vreg: %15[ 33 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %36[ 8 ]
+# CHECK: Vreg: %17[ 26 ]
+# CHECK: Vreg: %24[ LoopTag+16 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: Vreg: %12:sub0[ 12 ]
+# CHECK: Vreg: %12:sub1[ 13 ]
+# CHECK: Instr: %78:sreg_32 = S_ANDN2_B32 killed %31, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 36 ]
+# CHECK: Vreg: %28[ 3 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %11[ 34 ]
+# CHECK: Vreg: %75[ LoopTag+13 ]
+# CHECK: Vreg: %44[ 6 ]
+# CHECK: Vreg: %25[ 34 ]
+# CHECK: Vreg: %77[ LoopTag+14 ]
+# CHECK: Vreg: %39[ 4 ]
+# CHECK: Vreg: %46[ 7 ]
+# CHECK: Vreg: %72[ LoopTag+14 ]
+# CHECK: Vreg: %15[ 32 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %3[ 49 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Vreg: %17[ 25 ]
+# CHECK: Vreg: %24[ LoopTag+15 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %12:sub0[ 11 ]
+# CHECK: Vreg: %12:sub1[ 12 ]
+# CHECK: Instr: %79:sreg_32 = S_AND_B32 %42, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 35 ]
+# CHECK: Vreg: %78[ 1 ]
+# CHECK: Vreg: %28[ 2 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 38 ]
+# CHECK: Vreg: %11[ 33 ]
+# CHECK: Vreg: %75[ LoopTag+12 ]
+# CHECK: Vreg: %44[ 5 ]
+# CHECK: Vreg: %25[ 33 ]
+# CHECK: Vreg: %77[ LoopTag+13 ]
+# CHECK: Vreg: %39[ 3 ]
+# CHECK: Vreg: %46[ 6 ]
+# CHECK: Vreg: %72[ LoopTag+13 ]
+# CHECK: Vreg: %15[ 31 ]
+# CHECK: Vreg: %60[ LoopTag+13 ]
+# CHECK: Vreg: %3[ 48 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %17[ 24 ]
+# CHECK: Vreg: %24[ LoopTag+14 ]
+# CHECK: Vreg: %12:sub0[ 10 ]
+# CHECK: Vreg: %12:sub1[ 11 ]
+# CHECK: Instr: %33:sreg_32 = S_OR_B32 killed %78, killed %79, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 34 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %42[ 5 ]
+# CHECK: Vreg: %4[ 37 ]
+# CHECK: Vreg: %11[ 32 ]
+# CHECK: Vreg: %75[ LoopTag+11 ]
+# CHECK: Vreg: %44[ 4 ]
+# CHECK: Vreg: %25[ 32 ]
+# CHECK: Vreg: %77[ LoopTag+12 ]
+# CHECK: Vreg: %39[ 2 ]
+# CHECK: Vreg: %46[ 5 ]
+# CHECK: Vreg: %72[ LoopTag+12 ]
+# CHECK: Vreg: %15[ 30 ]
+# CHECK: Vreg: %60[ LoopTag+12 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %3[ 47 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %17[ 23 ]
+# CHECK: Vreg: %24[ LoopTag+13 ]
+# CHECK: Vreg: %12:sub0[ 9 ]
+# CHECK: Vreg: %12:sub1[ 10 ]
+# CHECK: Instr: %80:sreg_32 = S_ANDN2_B32 killed %28, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 33 ]
+# CHECK: Vreg: %33[ 4 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %4[ 36 ]
+# CHECK: Vreg: %11[ 31 ]
+# CHECK: Vreg: %75[ LoopTag+10 ]
+# CHECK: Vreg: %44[ 3 ]
+# CHECK: Vreg: %25[ 31 ]
+# CHECK: Vreg: %77[ LoopTag+11 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %46[ 4 ]
+# CHECK: Vreg: %72[ LoopTag+11 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %60[ LoopTag+11 ]
+# CHECK: Vreg: %3[ 46 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %17[ 22 ]
+# CHECK: Vreg: %24[ LoopTag+12 ]
+# CHECK: Vreg: %12:sub0[ 8 ]
+# CHECK: Vreg: %12:sub1[ 9 ]
+# CHECK: Instr: %81:sreg_32 = S_AND_B32 %39, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 32 ]
+# CHECK: Vreg: %33[ 3 ]
+# CHECK: Vreg: %80[ 1 ]
+# CHECK: Vreg: %42[ 3 ]
+# CHECK: Vreg: %4[ 35 ]
+# CHECK: Vreg: %11[ 30 ]
+# CHECK: Vreg: %75[ LoopTag+9 ]
+# CHECK: Vreg: %44[ 2 ]
+# CHECK: Vreg: %25[ 30 ]
+# CHECK: Vreg: %77[ LoopTag+10 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %46[ 3 ]
+# CHECK: Vreg: %72[ LoopTag+10 ]
+# CHECK: Vreg: %15[ 28 ]
+# CHECK: Vreg: %60[ LoopTag+10 ]
+# CHECK: Vreg: %3[ 45 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %17[ 21 ]
+# CHECK: Vreg: %24[ LoopTag+11 ]
+# CHECK: Vreg: %12:sub0[ 7 ]
+# CHECK: Vreg: %12:sub1[ 8 ]
+# CHECK: Instr: %30:sreg_32 = S_OR_B32 killed %80, killed %81, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 31 ]
+# CHECK: Vreg: %33[ 2 ]
+# CHECK: Vreg: %80[ 0 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %4[ 34 ]
+# CHECK: Vreg: %11[ 29 ]
+# CHECK: Vreg: %75[ LoopTag+8 ]
+# CHECK: Vreg: %44[ 1 ]
+# CHECK: Vreg: %25[ 29 ]
+# CHECK: Vreg: %77[ LoopTag+9 ]
+# CHECK: Vreg: %39[ 2 ]
+# CHECK: Vreg: %46[ 2 ]
+# CHECK: Vreg: %72[ LoopTag+9 ]
+# CHECK: Vreg: %15[ 27 ]
+# CHECK: Vreg: %60[ LoopTag+9 ]
+# CHECK: Vreg: %3[ 44 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 20 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Vreg: %24[ LoopTag+10 ]
+# CHECK: Vreg: %12:sub0[ 6 ]
+# CHECK: Vreg: %12:sub1[ 7 ]
+# CHECK: Instr: SI_LOOP %44, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 30 ]
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %4[ 33 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %11[ 28 ]
+# CHECK: Vreg: %75[ LoopTag+7 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 28 ]
+# CHECK: Vreg: %77[ LoopTag+8 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %72[ LoopTag+8 ]
+# CHECK: Vreg: %15[ 26 ]
+# CHECK: Vreg: %60[ LoopTag+8 ]
+# CHECK: Vreg: %3[ 43 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %17[ 19 ]
+# CHECK: Vreg: %24[ LoopTag+9 ]
+# CHECK: Vreg: %12:sub0[ 5 ]
+# CHECK: Vreg: %12:sub1[ 6 ]
+# CHECK: Instr: S_BRANCH %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %75[ LoopTag+6 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %77[ LoopTag+7 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %72[ LoopTag+7 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %60[ LoopTag+7 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %24[ LoopTag+8 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %26[ 29 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %11[ 27 ]
+# CHECK: Vreg: %75[ LoopTag+6 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 27 ]
+# CHECK: Vreg: %77[ LoopTag+7 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %72[ LoopTag+7 ]
+# CHECK: Vreg: %15[ 25 ]
+# CHECK: Vreg: %60[ LoopTag+7 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %24[ LoopTag+8 ]
+# CHECK: Vreg: %12:sub0[ 4 ]
+# CHECK: Vreg: %12:sub1[ 5 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %82:sreg_32 = PHI undef %83:sreg_32, %bb.2, %84, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+24 ]
+# CHECK: Vreg: %45[ LoopTag+18 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+34 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+19 ]
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %60[ LoopTag+19 ]
+# CHECK: Vreg: %3[ LoopTag+21 ]
+# CHECK: Vreg: %17[ LoopTag+56 ]
+# CHECK: Vreg: %43[ LoopTag+29 ]
+# CHECK: Vreg: %24[ LoopTag*2+46 ]
+# CHECK: Vreg: %31[ LoopTag+31 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+43 ]
+# CHECK: Instr: %85:sreg_32 = PHI undef %86:sreg_32, %bb.2, %87, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+24 ]
+# CHECK: Vreg: %45[ LoopTag+18 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+34 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+19 ]
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %82[ 9 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %60[ LoopTag+19 ]
+# CHECK: Vreg: %3[ LoopTag+21 ]
+# CHECK: Vreg: %17[ LoopTag+56 ]
+# CHECK: Vreg: %43[ LoopTag+29 ]
+# CHECK: Vreg: %24[ LoopTag*2+46 ]
+# CHECK: Vreg: %31[ LoopTag+31 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+43 ]
+# CHECK: Instr: %88:sreg_32 = PHI undef %89:sreg_32, %bb.2, %90, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+24 ]
+# CHECK: Vreg: %45[ LoopTag+18 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %85[ 3 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+34 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+19 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %82[ 9 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %60[ LoopTag+19 ]
+# CHECK: Vreg: %3[ LoopTag+21 ]
+# CHECK: Vreg: %17[ LoopTag+56 ]
+# CHECK: Vreg: %43[ LoopTag+29 ]
+# CHECK: Vreg: %24[ LoopTag*2+46 ]
+# CHECK: Vreg: %31[ LoopTag+31 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+43 ]
+# CHECK: Instr: %91:sreg_32 = PHI %66, %bb.2, %92, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+24 ]
+# CHECK: Vreg: %45[ LoopTag+18 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %85[ 3 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+34 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+19 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %82[ 9 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %60[ LoopTag+19 ]
+# CHECK: Vreg: %3[ LoopTag+21 ]
+# CHECK: Vreg: %17[ LoopTag+56 ]
+# CHECK: Vreg: %43[ LoopTag+29 ]
+# CHECK: Vreg: %24[ LoopTag*2+46 ]
+# CHECK: Vreg: %88[ 2 ]
+# CHECK: Vreg: %31[ LoopTag+31 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+43 ]
+# CHECK: Instr: %93:sreg_32 = PHI %66, %bb.2, %94, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+24 ]
+# CHECK: Vreg: %45[ LoopTag+18 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %85[ 3 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+34 ]
+# CHECK: Vreg: %61[ LoopTag+19 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %82[ 9 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %91[ 8 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %60[ LoopTag+19 ]
+# CHECK: Vreg: %3[ LoopTag+21 ]
+# CHECK: Vreg: %17[ LoopTag+56 ]
+# CHECK: Vreg: %43[ LoopTag+29 ]
+# CHECK: Vreg: %24[ LoopTag*2+46 ]
+# CHECK: Vreg: %88[ 2 ]
+# CHECK: Vreg: %31[ LoopTag+31 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+43 ]
+# CHECK: Instr: %95:vgpr_32 = COPY %93, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+23 ]
+# CHECK: Vreg: %45[ LoopTag+17 ]
+# CHECK: Vreg: %26[ 7 ]
+# CHECK: Vreg: %85[ 2 ]
+# CHECK: Vreg: %28[ LoopTag+33 ]
+# CHECK: Vreg: %61[ LoopTag+18 ]
+# CHECK: Vreg: %4[ 10 ]
+# CHECK: Vreg: %11[ 5 ]
+# CHECK: Vreg: %82[ 8 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %91[ 7 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %3[ LoopTag+20 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+55 ]
+# CHECK: Vreg: %43[ LoopTag+28 ]
+# CHECK: Vreg: %24[ LoopTag*2+45 ]
+# CHECK: Vreg: %88[ 1 ]
+# CHECK: Vreg: %31[ LoopTag+30 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+42 ]
+# CHECK: Instr: %96:sreg_32 = S_OR_B32 killed %88, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+22 ]
+# CHECK: Vreg: %45[ LoopTag+16 ]
+# CHECK: Vreg: %26[ 6 ]
+# CHECK: Vreg: %85[ 1 ]
+# CHECK: Vreg: %28[ LoopTag+32 ]
+# CHECK: Vreg: %61[ LoopTag+17 ]
+# CHECK: Vreg: %4[ 9 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %82[ 7 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %65[ LoopTag+26 ]
+# CHECK: Vreg: %91[ 6 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %3[ LoopTag+19 ]
+# CHECK: Vreg: %93[ 8 ]
+# CHECK: Vreg: %17[ LoopTag+54 ]
+# CHECK: Vreg: %43[ LoopTag+27 ]
+# CHECK: Vreg: %24[ LoopTag*2+44 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+29 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+41 ]
+# CHECK: Vreg: %95[ 3 ]
+# CHECK: Instr: %97:sreg_32 = S_OR_B32 killed %85, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+21 ]
+# CHECK: Vreg: %45[ LoopTag+15 ]
+# CHECK: Vreg: %26[ 5 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+31 ]
+# CHECK: Vreg: %61[ LoopTag+16 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %82[ 6 ]
+# CHECK: Vreg: %63[ LoopTag+19 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %65[ LoopTag+25 ]
+# CHECK: Vreg: %91[ 5 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %60[ LoopTag+16 ]
+# CHECK: Vreg: %3[ LoopTag+18 ]
+# CHECK: Vreg: %93[ 7 ]
+# CHECK: Vreg: %17[ LoopTag+53 ]
+# CHECK: Vreg: %43[ LoopTag+26 ]
+# CHECK: Vreg: %24[ LoopTag*2+43 ]
+# CHECK: Vreg: %31[ LoopTag+28 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+39 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+40 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: Instr: %98:sreg_32 = SI_IF %15, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+20 ]
+# CHECK: Vreg: %45[ LoopTag+14 ]
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %97[ 1 ]
+# CHECK: Vreg: %28[ LoopTag+30 ]
+# CHECK: Vreg: %61[ LoopTag+15 ]
+# CHECK: Vreg: %4[ 7 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %82[ 5 ]
+# CHECK: Vreg: %63[ LoopTag+18 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %91[ 4 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %3[ LoopTag+17 ]
+# CHECK: Vreg: %93[ 6 ]
+# CHECK: Vreg: %17[ LoopTag+52 ]
+# CHECK: Vreg: %43[ LoopTag+25 ]
+# CHECK: Vreg: %24[ LoopTag*2+42 ]
+# CHECK: Vreg: %31[ LoopTag+27 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+39 ]
+# CHECK: Vreg: %95[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+19 ]
+# CHECK: Vreg: %45[ LoopTag+13 ]
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+29 ]
+# CHECK: Vreg: %61[ LoopTag+14 ]
+# CHECK: Vreg: %4[ 6 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %82[ 4 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+23 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %93[ 5 ]
+# CHECK: Vreg: %17[ LoopTag+51 ]
+# CHECK: Vreg: %43[ LoopTag+24 ]
+# CHECK: Vreg: %24[ LoopTag*2+41 ]
+# CHECK: Vreg: %31[ LoopTag+26 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ LoopTag+19 ]
+# CHECK: Vreg: %45[ LoopTag+13 ]
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+29 ]
+# CHECK: Vreg: %61[ LoopTag+14 ]
+# CHECK: Vreg: %4[ 6 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %82[ 4 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+23 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %93[ 5 ]
+# CHECK: Vreg: %17[ LoopTag+51 ]
+# CHECK: Vreg: %43[ LoopTag+24 ]
+# CHECK: Vreg: %24[ LoopTag*2+41 ]
+# CHECK: Vreg: %31[ LoopTag+26 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: GLOBAL_STORE_DWORD %11, %25, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+30 ]
+# CHECK: Vreg: %45[ LoopTag+24 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %97[ 8 ]
+# CHECK: Vreg: %28[ LoopTag+40 ]
+# CHECK: Vreg: %61[ LoopTag+25 ]
+# CHECK: Vreg: %4[ 5 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %82[ 15 ]
+# CHECK: Vreg: %63[ LoopTag+28 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %96[ 5 ]
+# CHECK: Vreg: %65[ LoopTag+34 ]
+# CHECK: Vreg: %91[ 14 ]
+# CHECK: Vreg: %98[ 12 ]
+# CHECK: Vreg: %15[ 23 ]
+# CHECK: Vreg: %60[ LoopTag+25 ]
+# CHECK: Vreg: %3[ LoopTag+27 ]
+# CHECK: Vreg: %93[ 4 ]
+# CHECK: Vreg: %17[ LoopTag+62 ]
+# CHECK: Vreg: %43[ LoopTag+35 ]
+# CHECK: Vreg: %24[ LoopTag*2+52 ]
+# CHECK: Vreg: %31[ LoopTag+37 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+49 ]
+# CHECK: Instr: %99:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+29 ]
+# CHECK: Vreg: %45[ LoopTag+23 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %97[ 7 ]
+# CHECK: Vreg: %28[ LoopTag+39 ]
+# CHECK: Vreg: %61[ LoopTag+24 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %11[ 24 ]
+# CHECK: Vreg: %82[ 14 ]
+# CHECK: Vreg: %63[ LoopTag+27 ]
+# CHECK: Vreg: %25[ 10 ]
+# CHECK: Vreg: %96[ 4 ]
+# CHECK: Vreg: %65[ LoopTag+33 ]
+# CHECK: Vreg: %91[ 13 ]
+# CHECK: Vreg: %98[ 11 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %60[ LoopTag+24 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %17[ LoopTag+61 ]
+# CHECK: Vreg: %43[ LoopTag+34 ]
+# CHECK: Vreg: %24[ LoopTag*2+51 ]
+# CHECK: Vreg: %31[ LoopTag+36 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+48 ]
+# CHECK: Instr: %100:sreg_32 = SI_IF %26, %bb.17, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+28 ]
+# CHECK: Vreg: %45[ LoopTag+22 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %97[ 6 ]
+# CHECK: Vreg: %28[ LoopTag+38 ]
+# CHECK: Vreg: %99[ 1 ]
+# CHECK: Vreg: %61[ LoopTag+23 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %11[ 23 ]
+# CHECK: Vreg: %82[ 13 ]
+# CHECK: Vreg: %63[ LoopTag+26 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+32 ]
+# CHECK: Vreg: %91[ 12 ]
+# CHECK: Vreg: %98[ 10 ]
+# CHECK: Vreg: %15[ 21 ]
+# CHECK: Vreg: %60[ LoopTag+23 ]
+# CHECK: Vreg: %3[ LoopTag+25 ]
+# CHECK: Vreg: %93[ 2 ]
+# CHECK: Vreg: %17[ LoopTag+60 ]
+# CHECK: Vreg: %43[ LoopTag+33 ]
+# CHECK: Vreg: %24[ LoopTag*2+50 ]
+# CHECK: Vreg: %31[ LoopTag+35 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+47 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+27 ]
+# CHECK: Vreg: %45[ LoopTag+21 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %97[ 5 ]
+# CHECK: Vreg: %28[ LoopTag+37 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+22 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %11[ 22 ]
+# CHECK: Vreg: %82[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %65[ LoopTag+31 ]
+# CHECK: Vreg: %91[ 11 ]
+# CHECK: Vreg: %98[ 9 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %93[ 1 ]
+# CHECK: Vreg: %100[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+59 ]
+# CHECK: Vreg: %43[ LoopTag+32 ]
+# CHECK: Vreg: %24[ LoopTag*2+49 ]
+# CHECK: Vreg: %31[ LoopTag+34 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+46 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ LoopTag+27 ]
+# CHECK: Vreg: %45[ LoopTag+21 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %97[ 5 ]
+# CHECK: Vreg: %28[ LoopTag+37 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+22 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %11[ 22 ]
+# CHECK: Vreg: %82[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %65[ LoopTag+31 ]
+# CHECK: Vreg: %91[ 11 ]
+# CHECK: Vreg: %98[ 9 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %93[ 1 ]
+# CHECK: Vreg: %100[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+59 ]
+# CHECK: Vreg: %43[ LoopTag+32 ]
+# CHECK: Vreg: %24[ LoopTag*2+49 ]
+# CHECK: Vreg: %31[ LoopTag+34 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+46 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %87:sreg_32 = PHI %97, %bb.4, %101, %bb.17
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+19 ]
+# CHECK: Vreg: %45[ LoopTag+13 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+29 ]
+# CHECK: Vreg: %61[ LoopTag+14 ]
+# CHECK: Vreg: %4[ 19 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %82[ 4 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+23 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %17[ LoopTag+51 ]
+# CHECK: Vreg: %43[ LoopTag+24 ]
+# CHECK: Vreg: %24[ LoopTag*2+41 ]
+# CHECK: Vreg: %31[ LoopTag+26 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: %90:sreg_32 = PHI %96, %bb.4, %102, %bb.17
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+19 ]
+# CHECK: Vreg: %45[ LoopTag+13 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+29 ]
+# CHECK: Vreg: %61[ LoopTag+14 ]
+# CHECK: Vreg: %87[ 3 ]
+# CHECK: Vreg: %4[ 19 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %82[ 4 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+23 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %17[ LoopTag+51 ]
+# CHECK: Vreg: %43[ LoopTag+24 ]
+# CHECK: Vreg: %24[ LoopTag*2+41 ]
+# CHECK: Vreg: %31[ LoopTag+26 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Instr: %94:sreg_32 = PHI undef %103:sreg_32, %bb.4, %104, %bb.17
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+19 ]
+# CHECK: Vreg: %45[ LoopTag+13 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+29 ]
+# CHECK: Vreg: %61[ LoopTag+14 ]
+# CHECK: Vreg: %87[ 3 ]
+# CHECK: Vreg: %4[ 19 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %82[ 4 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+23 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %17[ LoopTag+51 ]
+# CHECK: Vreg: %43[ LoopTag+24 ]
+# CHECK: Vreg: %24[ LoopTag*2+41 ]
+# CHECK: Vreg: %31[ LoopTag+26 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Instr: %74:vgpr_32 = PHI %95, %bb.4, %25, %bb.17
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+19 ]
+# CHECK: Vreg: %45[ LoopTag+13 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %28[ LoopTag+29 ]
+# CHECK: Vreg: %61[ LoopTag+14 ]
+# CHECK: Vreg: %87[ 3 ]
+# CHECK: Vreg: %4[ 19 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %82[ 4 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+23 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %17[ LoopTag+51 ]
+# CHECK: Vreg: %43[ LoopTag+24 ]
+# CHECK: Vreg: %24[ LoopTag*2+41 ]
+# CHECK: Vreg: %31[ LoopTag+26 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Instr: SI_END_CF killed %98, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+18 ]
+# CHECK: Vreg: %45[ LoopTag+12 ]
+# CHECK: Vreg: %26[ 15 ]
+# CHECK: Vreg: %90[ 1 ]
+# CHECK: Vreg: %28[ LoopTag+28 ]
+# CHECK: Vreg: %61[ LoopTag+13 ]
+# CHECK: Vreg: %87[ 2 ]
+# CHECK: Vreg: %4[ 18 ]
+# CHECK: Vreg: %94[ 7 ]
+# CHECK: Vreg: %11[ 13 ]
+# CHECK: Vreg: %82[ 3 ]
+# CHECK: Vreg: %63[ LoopTag+16 ]
+# CHECK: Vreg: %25[ 13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %15[ 11 ]
+# CHECK: Vreg: %60[ LoopTag+13 ]
+# CHECK: Vreg: %3[ LoopTag+15 ]
+# CHECK: Vreg: %74[ LoopTag+21 ]
+# CHECK: Vreg: %17[ LoopTag+50 ]
+# CHECK: Vreg: %43[ LoopTag+23 ]
+# CHECK: Vreg: %24[ LoopTag*2+40 ]
+# CHECK: Vreg: %31[ LoopTag+25 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+36 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+37 ]
+# CHECK: Instr: %105:sreg_32 = S_XOR_B32 %90, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+17 ]
+# CHECK: Vreg: %45[ LoopTag+11 ]
+# CHECK: Vreg: %26[ 14 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+27 ]
+# CHECK: Vreg: %61[ LoopTag+12 ]
+# CHECK: Vreg: %87[ 1 ]
+# CHECK: Vreg: %4[ 17 ]
+# CHECK: Vreg: %94[ 6 ]
+# CHECK: Vreg: %11[ 12 ]
+# CHECK: Vreg: %82[ 2 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %25[ 12 ]
+# CHECK: Vreg: %65[ LoopTag+21 ]
+# CHECK: Vreg: %91[ 1 ]
+# CHECK: Vreg: %15[ 10 ]
+# CHECK: Vreg: %60[ LoopTag+12 ]
+# CHECK: Vreg: %3[ LoopTag+14 ]
+# CHECK: Vreg: %74[ LoopTag+20 ]
+# CHECK: Vreg: %17[ LoopTag+49 ]
+# CHECK: Vreg: %43[ LoopTag+22 ]
+# CHECK: Vreg: %24[ LoopTag*2+39 ]
+# CHECK: Vreg: %31[ LoopTag+24 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+35 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+36 ]
+# CHECK: Instr: %92:sreg_32 = SI_IF_BREAK %87, killed %91, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+16 ]
+# CHECK: Vreg: %45[ LoopTag+10 ]
+# CHECK: Vreg: %26[ 13 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %28[ LoopTag+26 ]
+# CHECK: Vreg: %61[ LoopTag+11 ]
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Vreg: %4[ 16 ]
+# CHECK: Vreg: %94[ 5 ]
+# CHECK: Vreg: %11[ 11 ]
+# CHECK: Vreg: %82[ 1 ]
+# CHECK: Vreg: %63[ LoopTag+14 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %65[ LoopTag+20 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %15[ 9 ]
+# CHECK: Vreg: %60[ LoopTag+11 ]
+# CHECK: Vreg: %105[ 2 ]
+# CHECK: Vreg: %3[ LoopTag+13 ]
+# CHECK: Vreg: %74[ LoopTag+19 ]
+# CHECK: Vreg: %17[ LoopTag+48 ]
+# CHECK: Vreg: %43[ LoopTag+21 ]
+# CHECK: Vreg: %24[ LoopTag*2+38 ]
+# CHECK: Vreg: %31[ LoopTag+23 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+34 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+35 ]
+# CHECK: Instr: %106:sreg_32 = S_ANDN2_B32 killed %82, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+15 ]
+# CHECK: Vreg: %45[ LoopTag+9 ]
+# CHECK: Vreg: %26[ 12 ]
+# CHECK: Vreg: %90[ 4 ]
+# CHECK: Vreg: %28[ LoopTag+25 ]
+# CHECK: Vreg: %92[ 3 ]
+# CHECK: Vreg: %61[ LoopTag+10 ]
+# CHECK: Vreg: %87[ 4 ]
+# CHECK: Vreg: %4[ 15 ]
+# CHECK: Vreg: %94[ 4 ]
+# CHECK: Vreg: %11[ 10 ]
+# CHECK: Vreg: %82[ 0 ]
+# CHECK: Vreg: %63[ LoopTag+13 ]
+# CHECK: Vreg: %25[ 10 ]
+# CHECK: Vreg: %65[ LoopTag+19 ]
+# CHECK: Vreg: %15[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+10 ]
+# CHECK: Vreg: %105[ 1 ]
+# CHECK: Vreg: %3[ LoopTag+12 ]
+# CHECK: Vreg: %74[ LoopTag+18 ]
+# CHECK: Vreg: %17[ LoopTag+47 ]
+# CHECK: Vreg: %43[ LoopTag+20 ]
+# CHECK: Vreg: %24[ LoopTag*2+37 ]
+# CHECK: Vreg: %31[ LoopTag+22 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+33 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+34 ]
+# CHECK: Instr: %107:sreg_32 = S_AND_B32 killed %105, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+14 ]
+# CHECK: Vreg: %45[ LoopTag+8 ]
+# CHECK: Vreg: %26[ 11 ]
+# CHECK: Vreg: %90[ 3 ]
+# CHECK: Vreg: %28[ LoopTag+24 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %61[ LoopTag+9 ]
+# CHECK: Vreg: %106[ 1 ]
+# CHECK: Vreg: %87[ 3 ]
+# CHECK: Vreg: %4[ 14 ]
+# CHECK: Vreg: %94[ 3 ]
+# CHECK: Vreg: %11[ 9 ]
+# CHECK: Vreg: %63[ LoopTag+12 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %65[ LoopTag+18 ]
+# CHECK: Vreg: %15[ 7 ]
+# CHECK: Vreg: %60[ LoopTag+9 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+11 ]
+# CHECK: Vreg: %74[ LoopTag+17 ]
+# CHECK: Vreg: %17[ LoopTag+46 ]
+# CHECK: Vreg: %43[ LoopTag+19 ]
+# CHECK: Vreg: %24[ LoopTag*2+36 ]
+# CHECK: Vreg: %31[ LoopTag+21 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+32 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+33 ]
+# CHECK: Instr: %84:sreg_32 = S_OR_B32 killed %106, killed %107, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+13 ]
+# CHECK: Vreg: %45[ LoopTag+7 ]
+# CHECK: Vreg: %26[ 10 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %28[ LoopTag+23 ]
+# CHECK: Vreg: %92[ 1 ]
+# CHECK: Vreg: %61[ LoopTag+8 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %87[ 2 ]
+# CHECK: Vreg: %4[ 13 ]
+# CHECK: Vreg: %94[ 2 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %63[ LoopTag+11 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %65[ LoopTag+17 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %60[ LoopTag+8 ]
+# CHECK: Vreg: %3[ LoopTag+10 ]
+# CHECK: Vreg: %74[ LoopTag+16 ]
+# CHECK: Vreg: %17[ LoopTag+45 ]
+# CHECK: Vreg: %43[ LoopTag+18 ]
+# CHECK: Vreg: %24[ LoopTag*2+35 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+20 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+31 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+32 ]
+# CHECK: Instr: SI_LOOP %92, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+12 ]
+# CHECK: Vreg: %45[ LoopTag+6 ]
+# CHECK: Vreg: %26[ 9 ]
+# CHECK: Vreg: %90[ 1 ]
+# CHECK: Vreg: %28[ LoopTag+22 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+7 ]
+# CHECK: Vreg: %87[ 1 ]
+# CHECK: Vreg: %4[ 12 ]
+# CHECK: Vreg: %94[ 1 ]
+# CHECK: Vreg: %11[ 7 ]
+# CHECK: Vreg: %63[ LoopTag+10 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %84[ 1 ]
+# CHECK: Vreg: %65[ LoopTag+16 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+7 ]
+# CHECK: Vreg: %3[ LoopTag+9 ]
+# CHECK: Vreg: %74[ LoopTag+15 ]
+# CHECK: Vreg: %17[ LoopTag+44 ]
+# CHECK: Vreg: %43[ LoopTag+17 ]
+# CHECK: Vreg: %24[ LoopTag*2+34 ]
+# CHECK: Vreg: %31[ LoopTag+19 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+30 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+31 ]
+# CHECK: Instr: S_BRANCH %bb.18
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+11 ]
+# CHECK: Vreg: %45[ LoopTag+5 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+21 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+6 ]
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %63[ LoopTag+9 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+15 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %60[ LoopTag+6 ]
+# CHECK: Vreg: %3[ LoopTag+8 ]
+# CHECK: Vreg: %74[ LoopTag+14 ]
+# CHECK: Vreg: %17[ LoopTag+43 ]
+# CHECK: Vreg: %43[ LoopTag+16 ]
+# CHECK: Vreg: %24[ LoopTag*2+33 ]
+# CHECK: Vreg: %31[ LoopTag+18 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+29 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+30 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ LoopTag+11 ]
+# CHECK: Vreg: %45[ LoopTag+5 ]
+# CHECK: Vreg: %26[ 8 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+21 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+6 ]
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %63[ LoopTag+9 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+15 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %60[ LoopTag+6 ]
+# CHECK: Vreg: %3[ LoopTag+8 ]
+# CHECK: Vreg: %74[ LoopTag+14 ]
+# CHECK: Vreg: %17[ LoopTag+43 ]
+# CHECK: Vreg: %43[ LoopTag+16 ]
+# CHECK: Vreg: %24[ LoopTag*2+33 ]
+# CHECK: Vreg: %31[ LoopTag+18 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+29 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+30 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: %108:sreg_32 = S_ADD_I32 killed %93, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+31 ]
+# CHECK: Vreg: %45[ LoopTag+25 ]
+# CHECK: Vreg: %26[ 28 ]
+# CHECK: Vreg: %97[ 9 ]
+# CHECK: Vreg: %28[ LoopTag+41 ]
+# CHECK: Vreg: %61[ LoopTag+26 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %11[ 26 ]
+# CHECK: Vreg: %82[ 16 ]
+# CHECK: Vreg: %63[ LoopTag+29 ]
+# CHECK: Vreg: %25[ 12 ]
+# CHECK: Vreg: %96[ 6 ]
+# CHECK: Vreg: %65[ LoopTag+35 ]
+# CHECK: Vreg: %91[ 15 ]
+# CHECK: Vreg: %98[ 13 ]
+# CHECK: Vreg: %15[ 24 ]
+# CHECK: Vreg: %60[ LoopTag+26 ]
+# CHECK: Vreg: %3[ LoopTag+28 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %100[ 5 ]
+# CHECK: Vreg: %17[ LoopTag+63 ]
+# CHECK: Vreg: %43[ LoopTag+36 ]
+# CHECK: Vreg: %24[ LoopTag*2+53 ]
+# CHECK: Vreg: %31[ LoopTag+38 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+50 ]
+# CHECK: Instr: %109:sreg_32 = V_CMP_GE_U32_e64 %108, %4, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+30 ]
+# CHECK: Vreg: %45[ LoopTag+24 ]
+# CHECK: Vreg: %26[ 27 ]
+# CHECK: Vreg: %97[ 8 ]
+# CHECK: Vreg: %28[ LoopTag+40 ]
+# CHECK: Vreg: %61[ LoopTag+25 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %11[ 25 ]
+# CHECK: Vreg: %82[ 15 ]
+# CHECK: Vreg: %63[ LoopTag+28 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %25[ 11 ]
+# CHECK: Vreg: %96[ 5 ]
+# CHECK: Vreg: %65[ LoopTag+34 ]
+# CHECK: Vreg: %91[ 14 ]
+# CHECK: Vreg: %98[ 12 ]
+# CHECK: Vreg: %15[ 23 ]
+# CHECK: Vreg: %60[ LoopTag+25 ]
+# CHECK: Vreg: %3[ LoopTag+27 ]
+# CHECK: Vreg: %100[ 4 ]
+# CHECK: Vreg: %17[ LoopTag+62 ]
+# CHECK: Vreg: %43[ LoopTag+35 ]
+# CHECK: Vreg: %24[ LoopTag*2+52 ]
+# CHECK: Vreg: %31[ LoopTag+37 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+49 ]
+# CHECK: Instr: %110:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+29 ]
+# CHECK: Vreg: %45[ LoopTag+23 ]
+# CHECK: Vreg: %26[ 26 ]
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %97[ 7 ]
+# CHECK: Vreg: %28[ LoopTag+39 ]
+# CHECK: Vreg: %61[ LoopTag+24 ]
+# CHECK: Vreg: %4[ 29 ]
+# CHECK: Vreg: %11[ 24 ]
+# CHECK: Vreg: %82[ 14 ]
+# CHECK: Vreg: %63[ LoopTag+27 ]
+# CHECK: Vreg: %108[ 2 ]
+# CHECK: Vreg: %25[ 10 ]
+# CHECK: Vreg: %96[ 4 ]
+# CHECK: Vreg: %65[ LoopTag+33 ]
+# CHECK: Vreg: %91[ 13 ]
+# CHECK: Vreg: %98[ 11 ]
+# CHECK: Vreg: %15[ 22 ]
+# CHECK: Vreg: %60[ LoopTag+24 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %100[ 3 ]
+# CHECK: Vreg: %17[ LoopTag+61 ]
+# CHECK: Vreg: %43[ LoopTag+34 ]
+# CHECK: Vreg: %24[ LoopTag*2+51 ]
+# CHECK: Vreg: %31[ LoopTag+36 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+48 ]
+# CHECK: Instr: %111:sreg_32 = S_ORN2_B32 killed %109, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+28 ]
+# CHECK: Vreg: %45[ LoopTag+22 ]
+# CHECK: Vreg: %26[ 25 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %97[ 6 ]
+# CHECK: Vreg: %28[ LoopTag+38 ]
+# CHECK: Vreg: %61[ LoopTag+23 ]
+# CHECK: Vreg: %4[ 28 ]
+# CHECK: Vreg: %11[ 23 ]
+# CHECK: Vreg: %82[ 13 ]
+# CHECK: Vreg: %63[ LoopTag+26 ]
+# CHECK: Vreg: %108[ 1 ]
+# CHECK: Vreg: %25[ 9 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+32 ]
+# CHECK: Vreg: %110[ 1 ]
+# CHECK: Vreg: %91[ 12 ]
+# CHECK: Vreg: %98[ 10 ]
+# CHECK: Vreg: %15[ 21 ]
+# CHECK: Vreg: %60[ LoopTag+23 ]
+# CHECK: Vreg: %3[ LoopTag+25 ]
+# CHECK: Vreg: %100[ 2 ]
+# CHECK: Vreg: %17[ LoopTag+60 ]
+# CHECK: Vreg: %43[ LoopTag+33 ]
+# CHECK: Vreg: %24[ LoopTag*2+50 ]
+# CHECK: Vreg: %31[ LoopTag+35 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+47 ]
+# CHECK: Instr: S_BRANCH %bb.17
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+27 ]
+# CHECK: Vreg: %45[ LoopTag+21 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %97[ 5 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+37 ]
+# CHECK: Vreg: %61[ LoopTag+22 ]
+# CHECK: Vreg: %4[ 27 ]
+# CHECK: Vreg: %11[ 22 ]
+# CHECK: Vreg: %82[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %65[ LoopTag+31 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %91[ 11 ]
+# CHECK: Vreg: %98[ 9 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %100[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+59 ]
+# CHECK: Vreg: %43[ LoopTag+32 ]
+# CHECK: Vreg: %24[ LoopTag*2+49 ]
+# CHECK: Vreg: %31[ LoopTag+34 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+46 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ LoopTag+27 ]
+# CHECK: Vreg: %45[ LoopTag+21 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %97[ 5 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+37 ]
+# CHECK: Vreg: %61[ LoopTag+22 ]
+# CHECK: Vreg: %4[ 27 ]
+# CHECK: Vreg: %11[ 22 ]
+# CHECK: Vreg: %82[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %65[ LoopTag+31 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %91[ 11 ]
+# CHECK: Vreg: %98[ 9 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %100[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+59 ]
+# CHECK: Vreg: %43[ LoopTag+32 ]
+# CHECK: Vreg: %24[ LoopTag*2+49 ]
+# CHECK: Vreg: %31[ LoopTag+34 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+46 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: %112:sreg_32 = S_ADD_I32 %45, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %26[ 56 ]
+# CHECK: Vreg: %28[ 23 ]
+# CHECK: Vreg: %61[ 8 ]
+# CHECK: Vreg: %4[ 59 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %63[ 11 ]
+# CHECK: Vreg: %25[ 54 ]
+# CHECK: Vreg: %134[ 7 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %15[ 52 ]
+# CHECK: Vreg: %60[ 1 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Vreg: %74[ 16 ]
+# CHECK: Vreg: %17[ 45 ]
+# CHECK: Vreg: %43[ 18 ]
+# CHECK: Vreg: %24[ LoopTag+35 ]
+# CHECK: Vreg: %31[ 20 ]
+# CHECK: Vreg: %12:sub0[ 31 ]
+# CHECK: Vreg: %12:sub1[ 32 ]
+# CHECK: Instr: %113:vgpr_32 = V_ADD_U32_e64 %112, %60, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 12 ]
+# CHECK: Vreg: %45[ 18 ]
+# CHECK: Vreg: %26[ 55 ]
+# CHECK: Vreg: %28[ 22 ]
+# CHECK: Vreg: %61[ 7 ]
+# CHECK: Vreg: %4[ 58 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %63[ 10 ]
+# CHECK: Vreg: %25[ 53 ]
+# CHECK: Vreg: %134[ 6 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %15[ 51 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %74[ 15 ]
+# CHECK: Vreg: %17[ 44 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %24[ LoopTag+34 ]
+# CHECK: Vreg: %31[ 19 ]
+# CHECK: Vreg: %12:sub0[ 30 ]
+# CHECK: Vreg: %12:sub1[ 31 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %11, %113, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 11 ]
+# CHECK: Vreg: %45[ 17 ]
+# CHECK: Vreg: %26[ 54 ]
+# CHECK: Vreg: %28[ 21 ]
+# CHECK: Vreg: %61[ 6 ]
+# CHECK: Vreg: %4[ 57 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %63[ 9 ]
+# CHECK: Vreg: %25[ 52 ]
+# CHECK: Vreg: %134[ 5 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %15[ 50 ]
+# CHECK: Vreg: %60[ LoopTag+32 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %112[ 1 ]
+# CHECK: Vreg: %74[ 14 ]
+# CHECK: Vreg: %17[ 43 ]
+# CHECK: Vreg: %43[ 16 ]
+# CHECK: Vreg: %24[ LoopTag+33 ]
+# CHECK: Vreg: %31[ 18 ]
+# CHECK: Vreg: %12:sub0[ 29 ]
+# CHECK: Vreg: %12:sub1[ 30 ]
+# CHECK: Instr: %114:sreg_32 = V_CMP_GE_U32_e64 %112, %3, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 10 ]
+# CHECK: Vreg: %45[ 16 ]
+# CHECK: Vreg: %26[ 53 ]
+# CHECK: Vreg: %28[ 20 ]
+# CHECK: Vreg: %61[ 5 ]
+# CHECK: Vreg: %4[ 56 ]
+# CHECK: Vreg: %113[ 3 ]
+# CHECK: Vreg: %11[ 51 ]
+# CHECK: Vreg: %63[ 8 ]
+# CHECK: Vreg: %25[ 51 ]
+# CHECK: Vreg: %134[ 4 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %15[ 49 ]
+# CHECK: Vreg: %60[ LoopTag+31 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %17[ 42 ]
+# CHECK: Vreg: %43[ 15 ]
+# CHECK: Vreg: %24[ LoopTag+32 ]
+# CHECK: Vreg: %31[ 17 ]
+# CHECK: Vreg: %12:sub0[ 28 ]
+# CHECK: Vreg: %12:sub1[ 29 ]
+# CHECK: Instr: %115:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 9 ]
+# CHECK: Vreg: %45[ 15 ]
+# CHECK: Vreg: %26[ 52 ]
+# CHECK: Vreg: %28[ 19 ]
+# CHECK: Vreg: %61[ 4 ]
+# CHECK: Vreg: %4[ 55 ]
+# CHECK: Vreg: %113[ 2 ]
+# CHECK: Vreg: %11[ 50 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %25[ 50 ]
+# CHECK: Vreg: %134[ 3 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %15[ 48 ]
+# CHECK: Vreg: %60[ LoopTag+30 ]
+# CHECK: Vreg: %3[ 65 ]
+# CHECK: Vreg: %112[ 2 ]
+# CHECK: Vreg: %74[ 12 ]
+# CHECK: Vreg: %17[ 41 ]
+# CHECK: Vreg: %43[ 14 ]
+# CHECK: Vreg: %24[ LoopTag+31 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Vreg: %31[ 16 ]
+# CHECK: Vreg: %12:sub0[ 27 ]
+# CHECK: Vreg: %12:sub1[ 28 ]
+# CHECK: Instr: %116:sreg_32 = S_ORN2_B32 killed %114, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 8 ]
+# CHECK: Vreg: %45[ 14 ]
+# CHECK: Vreg: %26[ 51 ]
+# CHECK: Vreg: %28[ 18 ]
+# CHECK: Vreg: %61[ 3 ]
+# CHECK: Vreg: %4[ 54 ]
+# CHECK: Vreg: %113[ 1 ]
+# CHECK: Vreg: %11[ 49 ]
+# CHECK: Vreg: %63[ 6 ]
+# CHECK: Vreg: %25[ 49 ]
+# CHECK: Vreg: %134[ 2 ]
+# CHECK: Vreg: %115[ 1 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %15[ 47 ]
+# CHECK: Vreg: %60[ LoopTag+29 ]
+# CHECK: Vreg: %3[ 64 ]
+# CHECK: Vreg: %112[ 1 ]
+# CHECK: Vreg: %74[ 11 ]
+# CHECK: Vreg: %17[ 40 ]
+# CHECK: Vreg: %43[ 13 ]
+# CHECK: Vreg: %24[ LoopTag+30 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %31[ 15 ]
+# CHECK: Vreg: %12:sub0[ 26 ]
+# CHECK: Vreg: %12:sub1[ 27 ]
+# CHECK: Instr: S_BRANCH %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %45[ 13 ]
+# CHECK: Vreg: %26[ 50 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %28[ 17 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %11[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %25[ 48 ]
+# CHECK: Vreg: %134[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %60[ LoopTag+28 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %74[ 10 ]
+# CHECK: Vreg: %17[ 39 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %31[ 14 ]
+# CHECK: Vreg: %12:sub0[ 25 ]
+# CHECK: Vreg: %12:sub1[ 26 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %45[ 13 ]
+# CHECK: Vreg: %26[ 50 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %28[ 17 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %11[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %25[ 48 ]
+# CHECK: Vreg: %134[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %60[ LoopTag+28 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %74[ 10 ]
+# CHECK: Vreg: %17[ 39 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %31[ 14 ]
+# CHECK: Vreg: %12:sub0[ 25 ]
+# CHECK: Vreg: %12:sub1[ 26 ]
+# CHECK: --- MBB_9 ---
+# CHECK: Instr: %117:vgpr_32 = PHI undef %118:vgpr_32, %bb.15, %119, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %123[ 1 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %77[ 3 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %24[ 4 ]
+# CHECK: Instr: %120:vreg_64 = PHI %11, %bb.15, undef %121:vreg_64, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %123[ 1 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %77[ 3 ]
+# CHECK: Vreg: %117[ 2 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %24[ 4 ]
+# CHECK: Instr: %122:sreg_32 = SI_ELSE killed %123, %bb.13, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %120[ 3 ]
+# CHECK: Vreg: %77[ 2 ]
+# CHECK: Vreg: %117[ 1 ]
+# CHECK: Vreg: %60[ 2 ]
+# CHECK: Vreg: %24[ 3 ]
+# CHECK: Instr: S_BRANCH %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %120[ 2 ]
+# CHECK: Vreg: %77[ 1 ]
+# CHECK: Vreg: %122[ 1 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %60[ 1 ]
+# CHECK: Vreg: %24[ 2 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %120[ 2 ]
+# CHECK: Vreg: %77[ 1 ]
+# CHECK: Vreg: %122[ 1 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %60[ 1 ]
+# CHECK: Vreg: %24[ 2 ]
+# CHECK: --- MBB_10 ---
+# CHECK: Instr: %124:vgpr_32 = V_MUL_LO_U32_e64 killed %60, killed %77, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %120[ 1 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %122[ 3 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %24[ 4 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %120, %124, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %120[ 0 ]
+# CHECK: Vreg: %122[ 2 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %24[ 3 ]
+# CHECK: Instr: S_BRANCH %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %122[ 1 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %24[ 2 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %122[ 1 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %24[ 2 ]
+# CHECK: --- MBB_11 ---
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %11, %72, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %123[ 3 ]
+# CHECK: Vreg: %125[ 1 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %77[ 5 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %24[ 6 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %123[ 3 ]
+# CHECK: Vreg: %125[ 1 ]
+# CHECK: Vreg: %77[ 5 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %24[ 6 ]
+# CHECK: --- MBB_12 ---
+# CHECK: Instr: %119:vgpr_32 = PHI %75, %bb.16, %72, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %123[ 3 ]
+# CHECK: Vreg: %125[ 1 ]
+# CHECK: Vreg: %75[ 0 ]
+# CHECK: Vreg: %77[ 5 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %24[ 6 ]
+# CHECK: Instr: SI_END_CF killed %125, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %123[ 2 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %77[ 4 ]
+# CHECK: Vreg: %60[ 4 ]
+# CHECK: Vreg: %119[ 1 ]
+# CHECK: Vreg: %24[ 5 ]
+# CHECK: Instr: S_BRANCH %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %123[ 1 ]
+# CHECK: Vreg: %77[ 3 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %24[ 4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %123[ 1 ]
+# CHECK: Vreg: %77[ 3 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %24[ 4 ]
+# CHECK: --- MBB_13 ---
+# CHECK: Instr: %126:vgpr_32 = PHI %117, %bb.9, %124, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %122[ 1 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %24[ 2 ]
+# CHECK: Instr: SI_END_CF killed %122, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %122[ 0 ]
+# CHECK: Vreg: %126[ 1 ]
+# CHECK: Vreg: %24[ 1 ]
+# CHECK: Instr: %127:vgpr_32 = V_ADD3_U32_e64 killed %24, killed %126, 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %126[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Instr: %128:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %127, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %128
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: --- MBB_14 ---
+# CHECK: Instr: %129:sreg_32 = PHI %130, %bb.18, %116, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %45[ 13 ]
+# CHECK: Vreg: %26[ 50 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %130[ 0 ]
+# CHECK: Vreg: %28[ 17 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %11[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %25[ 48 ]
+# CHECK: Vreg: %134[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %60[ LoopTag+28 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %74[ 10 ]
+# CHECK: Vreg: %17[ 39 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %31[ 14 ]
+# CHECK: Vreg: %12:sub0[ 25 ]
+# CHECK: Vreg: %12:sub1[ 26 ]
+# CHECK: Instr: %131:sreg_32 = PHI %130, %bb.18, %115, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %45[ 13 ]
+# CHECK: Vreg: %26[ 50 ]
+# CHECK: Vreg: %130[ 0 ]
+# CHECK: Vreg: %28[ 17 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %11[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %25[ 48 ]
+# CHECK: Vreg: %134[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %129[ 8 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %60[ LoopTag+28 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %74[ 10 ]
+# CHECK: Vreg: %17[ 39 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %31[ 14 ]
+# CHECK: Vreg: %12:sub0[ 25 ]
+# CHECK: Vreg: %12:sub1[ 26 ]
+# CHECK: Instr: %71:sreg_32 = PHI undef %132:sreg_32, %bb.18, %112, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %45[ 13 ]
+# CHECK: Vreg: %26[ 50 ]
+# CHECK: Vreg: %28[ 17 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %11[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %25[ 48 ]
+# CHECK: Vreg: %134[ 1 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %129[ 8 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %60[ LoopTag+28 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %131[ 3 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %74[ 10 ]
+# CHECK: Vreg: %17[ 39 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %31[ 14 ]
+# CHECK: Vreg: %12:sub0[ 25 ]
+# CHECK: Vreg: %12:sub1[ 26 ]
+# CHECK: Instr: %76:vgpr_32 = PHI undef %133:vgpr_32, %bb.18, %113, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %45[ 13 ]
+# CHECK: Vreg: %26[ 50 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %28[ 17 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %11[ 48 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %25[ 48 ]
+# CHECK: Vreg: %134[ 1 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %129[ 8 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %60[ LoopTag+28 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %131[ 3 ]
+# CHECK: Vreg: %74[ 10 ]
+# CHECK: Vreg: %17[ 39 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %31[ 14 ]
+# CHECK: Vreg: %12:sub0[ 25 ]
+# CHECK: Vreg: %12:sub1[ 26 ]
+# CHECK: Instr: SI_END_CF killed %134, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 6 ]
+# CHECK: Vreg: %45[ 12 ]
+# CHECK: Vreg: %26[ 49 ]
+# CHECK: Vreg: %71[ 9 ]
+# CHECK: Vreg: %28[ 16 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %4[ 52 ]
+# CHECK: Vreg: %11[ 47 ]
+# CHECK: Vreg: %63[ 4 ]
+# CHECK: Vreg: %25[ 47 ]
+# CHECK: Vreg: %134[ 0 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %129[ 7 ]
+# CHECK: Vreg: %15[ 45 ]
+# CHECK: Vreg: %60[ LoopTag+27 ]
+# CHECK: Vreg: %3[ 62 ]
+# CHECK: Vreg: %131[ 2 ]
+# CHECK: Vreg: %74[ 9 ]
+# CHECK: Vreg: %17[ 38 ]
+# CHECK: Vreg: %43[ 11 ]
+# CHECK: Vreg: %24[ LoopTag+28 ]
+# CHECK: Vreg: %31[ 13 ]
+# CHECK: Vreg: %12:sub0[ 24 ]
+# CHECK: Vreg: %12:sub1[ 25 ]
+# CHECK: Vreg: %76[ 9 ]
+# CHECK: Instr: %135:sreg_32 = S_ANDN2_B32 killed %61, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 5 ]
+# CHECK: Vreg: %45[ 11 ]
+# CHECK: Vreg: %26[ 48 ]
+# CHECK: Vreg: %71[ 8 ]
+# CHECK: Vreg: %28[ 15 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %4[ 51 ]
+# CHECK: Vreg: %11[ 46 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %25[ 46 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %129[ 6 ]
+# CHECK: Vreg: %15[ 44 ]
+# CHECK: Vreg: %60[ LoopTag+26 ]
+# CHECK: Vreg: %3[ 61 ]
+# CHECK: Vreg: %131[ 1 ]
+# CHECK: Vreg: %74[ 8 ]
+# CHECK: Vreg: %17[ 37 ]
+# CHECK: Vreg: %43[ 10 ]
+# CHECK: Vreg: %24[ LoopTag+27 ]
+# CHECK: Vreg: %31[ 12 ]
+# CHECK: Vreg: %12:sub0[ 23 ]
+# CHECK: Vreg: %12:sub1[ 24 ]
+# CHECK: Vreg: %76[ 8 ]
+# CHECK: Instr: %136:sreg_32 = S_AND_B32 killed %131, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 4 ]
+# CHECK: Vreg: %45[ 10 ]
+# CHECK: Vreg: %26[ 47 ]
+# CHECK: Vreg: %71[ 7 ]
+# CHECK: Vreg: %135[ 1 ]
+# CHECK: Vreg: %28[ 14 ]
+# CHECK: Vreg: %4[ 50 ]
+# CHECK: Vreg: %11[ 45 ]
+# CHECK: Vreg: %63[ 2 ]
+# CHECK: Vreg: %25[ 45 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %129[ 5 ]
+# CHECK: Vreg: %15[ 43 ]
+# CHECK: Vreg: %60[ LoopTag+25 ]
+# CHECK: Vreg: %3[ 60 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %74[ 7 ]
+# CHECK: Vreg: %17[ 36 ]
+# CHECK: Vreg: %43[ 9 ]
+# CHECK: Vreg: %24[ LoopTag+26 ]
+# CHECK: Vreg: %31[ 11 ]
+# CHECK: Vreg: %12:sub0[ 22 ]
+# CHECK: Vreg: %12:sub1[ 23 ]
+# CHECK: Vreg: %76[ 7 ]
+# CHECK: Instr: %69:sreg_32 = S_OR_B32 killed %135, killed %136, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 3 ]
+# CHECK: Vreg: %45[ 9 ]
+# CHECK: Vreg: %26[ 46 ]
+# CHECK: Vreg: %71[ 6 ]
+# CHECK: Vreg: %135[ 0 ]
+# CHECK: Vreg: %28[ 13 ]
+# CHECK: Vreg: %4[ 49 ]
+# CHECK: Vreg: %11[ 44 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %25[ 44 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %129[ 4 ]
+# CHECK: Vreg: %136[ 0 ]
+# CHECK: Vreg: %15[ 42 ]
+# CHECK: Vreg: %60[ LoopTag+24 ]
+# CHECK: Vreg: %3[ 59 ]
+# CHECK: Vreg: %74[ 6 ]
+# CHECK: Vreg: %17[ 35 ]
+# CHECK: Vreg: %43[ 8 ]
+# CHECK: Vreg: %24[ LoopTag+25 ]
+# CHECK: Vreg: %31[ 10 ]
+# CHECK: Vreg: %12:sub0[ 21 ]
+# CHECK: Vreg: %12:sub1[ 22 ]
+# CHECK: Vreg: %76[ 6 ]
+# CHECK: Instr: %137:sreg_32 = S_ANDN2_B32 killed %63, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 2 ]
+# CHECK: Vreg: %45[ 8 ]
+# CHECK: Vreg: %26[ 45 ]
+# CHECK: Vreg: %71[ 5 ]
+# CHECK: Vreg: %28[ 12 ]
+# CHECK: Vreg: %4[ 48 ]
+# CHECK: Vreg: %11[ 43 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %25[ 43 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %129[ 3 ]
+# CHECK: Vreg: %15[ 41 ]
+# CHECK: Vreg: %60[ LoopTag+23 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %74[ 5 ]
+# CHECK: Vreg: %17[ 34 ]
+# CHECK: Vreg: %43[ 7 ]
+# CHECK: Vreg: %24[ LoopTag+24 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %31[ 9 ]
+# CHECK: Vreg: %12:sub0[ 20 ]
+# CHECK: Vreg: %12:sub1[ 21 ]
+# CHECK: Vreg: %76[ 5 ]
+# CHECK: Instr: %68:sreg_32 = COPY killed %137
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %45[ 7 ]
+# CHECK: Vreg: %26[ 44 ]
+# CHECK: Vreg: %71[ 4 ]
+# CHECK: Vreg: %28[ 11 ]
+# CHECK: Vreg: %137[ 0 ]
+# CHECK: Vreg: %4[ 47 ]
+# CHECK: Vreg: %11[ 42 ]
+# CHECK: Vreg: %25[ 42 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %129[ 2 ]
+# CHECK: Vreg: %15[ 40 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %3[ 57 ]
+# CHECK: Vreg: %74[ 4 ]
+# CHECK: Vreg: %17[ 33 ]
+# CHECK: Vreg: %43[ 6 ]
+# CHECK: Vreg: %24[ LoopTag+23 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %31[ 8 ]
+# CHECK: Vreg: %12:sub0[ 19 ]
+# CHECK: Vreg: %12:sub1[ 20 ]
+# CHECK: Vreg: %76[ 4 ]
+# CHECK: Instr: %138:sreg_32 = S_ANDN2_B32 killed %64, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %45[ 6 ]
+# CHECK: Vreg: %26[ 43 ]
+# CHECK: Vreg: %71[ 3 ]
+# CHECK: Vreg: %28[ 10 ]
+# CHECK: Vreg: %4[ 46 ]
+# CHECK: Vreg: %68[ 3 ]
+# CHECK: Vreg: %11[ 41 ]
+# CHECK: Vreg: %25[ 41 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %15[ 39 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %3[ 56 ]
+# CHECK: Vreg: %74[ 3 ]
+# CHECK: Vreg: %17[ 32 ]
+# CHECK: Vreg: %43[ 5 ]
+# CHECK: Vreg: %24[ LoopTag+22 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %31[ 7 ]
+# CHECK: Vreg: %12:sub0[ 18 ]
+# CHECK: Vreg: %12:sub1[ 19 ]
+# CHECK: Vreg: %76[ 3 ]
+# CHECK: Instr: %139:sreg_32 = S_AND_B32 killed %129, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 5 ]
+# CHECK: Vreg: %26[ 42 ]
+# CHECK: Vreg: %71[ 2 ]
+# CHECK: Vreg: %28[ 9 ]
+# CHECK: Vreg: %4[ 45 ]
+# CHECK: Vreg: %68[ 2 ]
+# CHECK: Vreg: %11[ 40 ]
+# CHECK: Vreg: %25[ 40 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %15[ 38 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %3[ 55 ]
+# CHECK: Vreg: %74[ 2 ]
+# CHECK: Vreg: %138[ 1 ]
+# CHECK: Vreg: %17[ 31 ]
+# CHECK: Vreg: %43[ 4 ]
+# CHECK: Vreg: %24[ LoopTag+21 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %31[ 6 ]
+# CHECK: Vreg: %12:sub0[ 17 ]
+# CHECK: Vreg: %12:sub1[ 18 ]
+# CHECK: Vreg: %76[ 2 ]
+# CHECK: Instr: %67:sreg_32 = S_OR_B32 killed %138, killed %139, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 4 ]
+# CHECK: Vreg: %26[ 41 ]
+# CHECK: Vreg: %71[ 1 ]
+# CHECK: Vreg: %28[ 8 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %68[ 1 ]
+# CHECK: Vreg: %11[ 39 ]
+# CHECK: Vreg: %139[ 0 ]
+# CHECK: Vreg: %25[ 39 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %15[ 37 ]
+# CHECK: Vreg: %60[ LoopTag+19 ]
+# CHECK: Vreg: %3[ 54 ]
+# CHECK: Vreg: %74[ 1 ]
+# CHECK: Vreg: %138[ 0 ]
+# CHECK: Vreg: %17[ 30 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %24[ LoopTag+20 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %31[ 5 ]
+# CHECK: Vreg: %12:sub0[ 16 ]
+# CHECK: Vreg: %12:sub1[ 17 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 40 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %11[ 38 ]
+# CHECK: Vreg: %25[ 38 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 40 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %11[ 38 ]
+# CHECK: Vreg: %25[ 38 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %24[ LoopTag+19 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %12:sub0[ 15 ]
+# CHECK: Vreg: %12:sub1[ 16 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: --- MBB_15 ---
+# CHECK: Instr: SI_END_CF killed %44, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 4 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %75[ 5 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %77[ 6 ]
+# CHECK: Vreg: %72[ 6 ]
+# CHECK: Vreg: %60[ 6 ]
+# CHECK: Vreg: %24[ 7 ]
+# CHECK: Instr: %140:sreg_32 = S_XOR_B32 killed %30, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 3 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %75[ 4 ]
+# CHECK: Vreg: %77[ 5 ]
+# CHECK: Vreg: %72[ 5 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %24[ 6 ]
+# CHECK: Instr: %123:sreg_32 = SI_IF killed %140, %bb.9, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 2 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %75[ 3 ]
+# CHECK: Vreg: %77[ 4 ]
+# CHECK: Vreg: %72[ 4 ]
+# CHECK: Vreg: %60[ 4 ]
+# CHECK: Vreg: %24[ 5 ]
+# CHECK: Vreg: %140[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.16
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %123[ 1 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %75[ 2 ]
+# CHECK: Vreg: %77[ 3 ]
+# CHECK: Vreg: %72[ 3 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %24[ 4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %123[ 1 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %75[ 2 ]
+# CHECK: Vreg: %77[ 3 ]
+# CHECK: Vreg: %72[ 3 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %24[ 4 ]
+# CHECK: --- MBB_16 ---
+# CHECK: Instr: %125:sreg_32 = SI_IF killed %33, %bb.12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %123[ 4 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %75[ 1 ]
+# CHECK: Vreg: %77[ 6 ]
+# CHECK: Vreg: %72[ 2 ]
+# CHECK: Vreg: %60[ 6 ]
+# CHECK: Vreg: %24[ 7 ]
+# CHECK: Instr: S_BRANCH %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %123[ 3 ]
+# CHECK: Vreg: %125[ 1 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %75[ 0 ]
+# CHECK: Vreg: %77[ 5 ]
+# CHECK: Vreg: %72[ 1 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %24[ 6 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %123[ 3 ]
+# CHECK: Vreg: %125[ 1 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %75[ 0 ]
+# CHECK: Vreg: %77[ 5 ]
+# CHECK: Vreg: %72[ 1 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %24[ 6 ]
+# CHECK: --- MBB_17 ---
+# CHECK: Instr: %141:sreg_32 = PHI %99, %bb.5, %111, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+27 ]
+# CHECK: Vreg: %45[ LoopTag+21 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %97[ 5 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+37 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+22 ]
+# CHECK: Vreg: %4[ 27 ]
+# CHECK: Vreg: %11[ 22 ]
+# CHECK: Vreg: %82[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %65[ LoopTag+31 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %91[ 11 ]
+# CHECK: Vreg: %98[ 9 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %100[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+59 ]
+# CHECK: Vreg: %43[ LoopTag+32 ]
+# CHECK: Vreg: %24[ LoopTag*2+49 ]
+# CHECK: Vreg: %31[ LoopTag+34 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+46 ]
+# CHECK: Instr: %142:sreg_32 = PHI %99, %bb.5, %110, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+27 ]
+# CHECK: Vreg: %45[ LoopTag+21 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %97[ 5 ]
+# CHECK: Vreg: %28[ LoopTag+37 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+22 ]
+# CHECK: Vreg: %4[ 27 ]
+# CHECK: Vreg: %11[ 22 ]
+# CHECK: Vreg: %82[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %141[ 6 ]
+# CHECK: Vreg: %65[ LoopTag+31 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %91[ 11 ]
+# CHECK: Vreg: %98[ 9 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %100[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+59 ]
+# CHECK: Vreg: %43[ LoopTag+32 ]
+# CHECK: Vreg: %24[ LoopTag*2+49 ]
+# CHECK: Vreg: %31[ LoopTag+34 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+46 ]
+# CHECK: Instr: %104:sreg_32 = PHI undef %143:sreg_32, %bb.5, %108, %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+27 ]
+# CHECK: Vreg: %45[ LoopTag+21 ]
+# CHECK: Vreg: %26[ 24 ]
+# CHECK: Vreg: %97[ 5 ]
+# CHECK: Vreg: %142[ 3 ]
+# CHECK: Vreg: %28[ LoopTag+37 ]
+# CHECK: Vreg: %61[ LoopTag+22 ]
+# CHECK: Vreg: %4[ 27 ]
+# CHECK: Vreg: %11[ 22 ]
+# CHECK: Vreg: %82[ 12 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %141[ 6 ]
+# CHECK: Vreg: %65[ LoopTag+31 ]
+# CHECK: Vreg: %91[ 11 ]
+# CHECK: Vreg: %98[ 9 ]
+# CHECK: Vreg: %15[ 20 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %100[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+59 ]
+# CHECK: Vreg: %43[ LoopTag+32 ]
+# CHECK: Vreg: %24[ LoopTag*2+49 ]
+# CHECK: Vreg: %31[ LoopTag+34 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+46 ]
+# CHECK: Instr: SI_END_CF killed %100, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+26 ]
+# CHECK: Vreg: %45[ LoopTag+20 ]
+# CHECK: Vreg: %26[ 23 ]
+# CHECK: Vreg: %97[ 4 ]
+# CHECK: Vreg: %142[ 2 ]
+# CHECK: Vreg: %104[ 7 ]
+# CHECK: Vreg: %28[ LoopTag+36 ]
+# CHECK: Vreg: %61[ LoopTag+21 ]
+# CHECK: Vreg: %4[ 26 ]
+# CHECK: Vreg: %11[ 21 ]
+# CHECK: Vreg: %82[ 11 ]
+# CHECK: Vreg: %63[ LoopTag+24 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %141[ 5 ]
+# CHECK: Vreg: %65[ LoopTag+30 ]
+# CHECK: Vreg: %91[ 10 ]
+# CHECK: Vreg: %98[ 8 ]
+# CHECK: Vreg: %15[ 19 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %3[ LoopTag+23 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+58 ]
+# CHECK: Vreg: %43[ LoopTag+31 ]
+# CHECK: Vreg: %24[ LoopTag*2+48 ]
+# CHECK: Vreg: %31[ LoopTag+33 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+44 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+45 ]
+# CHECK: Instr: %144:sreg_32 = S_ANDN2_B32 killed %96, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+25 ]
+# CHECK: Vreg: %45[ LoopTag+19 ]
+# CHECK: Vreg: %26[ 22 ]
+# CHECK: Vreg: %97[ 3 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %28[ LoopTag+35 ]
+# CHECK: Vreg: %61[ LoopTag+20 ]
+# CHECK: Vreg: %4[ 25 ]
+# CHECK: Vreg: %11[ 20 ]
+# CHECK: Vreg: %82[ 10 ]
+# CHECK: Vreg: %63[ LoopTag+23 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %141[ 4 ]
+# CHECK: Vreg: %65[ LoopTag+29 ]
+# CHECK: Vreg: %91[ 9 ]
+# CHECK: Vreg: %98[ 7 ]
+# CHECK: Vreg: %15[ 18 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %3[ LoopTag+22 ]
+# CHECK: Vreg: %17[ LoopTag+57 ]
+# CHECK: Vreg: %43[ LoopTag+30 ]
+# CHECK: Vreg: %24[ LoopTag*2+47 ]
+# CHECK: Vreg: %31[ LoopTag+32 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+43 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+44 ]
+# CHECK: Instr: %145:sreg_32 = S_AND_B32 killed %142, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+24 ]
+# CHECK: Vreg: %45[ LoopTag+18 ]
+# CHECK: Vreg: %26[ 21 ]
+# CHECK: Vreg: %97[ 2 ]
+# CHECK: Vreg: %142[ 0 ]
+# CHECK: Vreg: %104[ 5 ]
+# CHECK: Vreg: %28[ LoopTag+34 ]
+# CHECK: Vreg: %144[ 1 ]
+# CHECK: Vreg: %61[ LoopTag+19 ]
+# CHECK: Vreg: %4[ 24 ]
+# CHECK: Vreg: %11[ 19 ]
+# CHECK: Vreg: %82[ 9 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %141[ 3 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %91[ 8 ]
+# CHECK: Vreg: %98[ 6 ]
+# CHECK: Vreg: %15[ 17 ]
+# CHECK: Vreg: %60[ LoopTag+19 ]
+# CHECK: Vreg: %3[ LoopTag+21 ]
+# CHECK: Vreg: %17[ LoopTag+56 ]
+# CHECK: Vreg: %43[ LoopTag+29 ]
+# CHECK: Vreg: %24[ LoopTag*2+46 ]
+# CHECK: Vreg: %31[ LoopTag+31 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+42 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+43 ]
+# CHECK: Instr: %102:sreg_32 = S_OR_B32 killed %144, killed %145, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+23 ]
+# CHECK: Vreg: %45[ LoopTag+17 ]
+# CHECK: Vreg: %26[ 20 ]
+# CHECK: Vreg: %97[ 1 ]
+# CHECK: Vreg: %104[ 4 ]
+# CHECK: Vreg: %28[ LoopTag+33 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %61[ LoopTag+18 ]
+# CHECK: Vreg: %4[ 23 ]
+# CHECK: Vreg: %11[ 18 ]
+# CHECK: Vreg: %82[ 8 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %141[ 2 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %91[ 7 ]
+# CHECK: Vreg: %98[ 5 ]
+# CHECK: Vreg: %15[ 16 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %3[ LoopTag+20 ]
+# CHECK: Vreg: %17[ LoopTag+55 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+28 ]
+# CHECK: Vreg: %24[ LoopTag*2+45 ]
+# CHECK: Vreg: %31[ LoopTag+30 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+41 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+42 ]
+# CHECK: Instr: %146:sreg_32 = S_ANDN2_B32 killed %97, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+22 ]
+# CHECK: Vreg: %45[ LoopTag+16 ]
+# CHECK: Vreg: %26[ 19 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %104[ 3 ]
+# CHECK: Vreg: %28[ LoopTag+32 ]
+# CHECK: Vreg: %61[ LoopTag+17 ]
+# CHECK: Vreg: %4[ 22 ]
+# CHECK: Vreg: %11[ 17 ]
+# CHECK: Vreg: %82[ 7 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %141[ 1 ]
+# CHECK: Vreg: %65[ LoopTag+26 ]
+# CHECK: Vreg: %91[ 6 ]
+# CHECK: Vreg: %98[ 4 ]
+# CHECK: Vreg: %15[ 15 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %3[ LoopTag+19 ]
+# CHECK: Vreg: %17[ LoopTag+54 ]
+# CHECK: Vreg: %43[ LoopTag+27 ]
+# CHECK: Vreg: %24[ LoopTag*2+44 ]
+# CHECK: Vreg: %31[ LoopTag+29 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+40 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+41 ]
+# CHECK: Vreg: %102[ 3 ]
+# CHECK: Instr: %147:sreg_32 = S_AND_B32 killed %141, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+21 ]
+# CHECK: Vreg: %45[ LoopTag+15 ]
+# CHECK: Vreg: %26[ 18 ]
+# CHECK: Vreg: %104[ 2 ]
+# CHECK: Vreg: %28[ LoopTag+31 ]
+# CHECK: Vreg: %61[ LoopTag+16 ]
+# CHECK: Vreg: %4[ 21 ]
+# CHECK: Vreg: %11[ 16 ]
+# CHECK: Vreg: %82[ 6 ]
+# CHECK: Vreg: %63[ LoopTag+19 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %146[ 1 ]
+# CHECK: Vreg: %141[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+25 ]
+# CHECK: Vreg: %91[ 5 ]
+# CHECK: Vreg: %98[ 3 ]
+# CHECK: Vreg: %15[ 14 ]
+# CHECK: Vreg: %60[ LoopTag+16 ]
+# CHECK: Vreg: %3[ LoopTag+18 ]
+# CHECK: Vreg: %17[ LoopTag+53 ]
+# CHECK: Vreg: %43[ LoopTag+26 ]
+# CHECK: Vreg: %24[ LoopTag*2+43 ]
+# CHECK: Vreg: %31[ LoopTag+28 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+39 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+40 ]
+# CHECK: Vreg: %102[ 2 ]
+# CHECK: Instr: %101:sreg_32 = S_OR_B32 killed %146, killed %147, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+20 ]
+# CHECK: Vreg: %45[ LoopTag+14 ]
+# CHECK: Vreg: %26[ 17 ]
+# CHECK: Vreg: %104[ 1 ]
+# CHECK: Vreg: %28[ LoopTag+30 ]
+# CHECK: Vreg: %61[ LoopTag+15 ]
+# CHECK: Vreg: %4[ 20 ]
+# CHECK: Vreg: %11[ 15 ]
+# CHECK: Vreg: %82[ 5 ]
+# CHECK: Vreg: %63[ LoopTag+18 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %91[ 4 ]
+# CHECK: Vreg: %98[ 2 ]
+# CHECK: Vreg: %15[ 13 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %3[ LoopTag+17 ]
+# CHECK: Vreg: %17[ LoopTag+52 ]
+# CHECK: Vreg: %43[ LoopTag+25 ]
+# CHECK: Vreg: %24[ LoopTag*2+42 ]
+# CHECK: Vreg: %31[ LoopTag+27 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+38 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+39 ]
+# CHECK: Vreg: %102[ 1 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ LoopTag+19 ]
+# CHECK: Vreg: %45[ LoopTag+13 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+29 ]
+# CHECK: Vreg: %61[ LoopTag+14 ]
+# CHECK: Vreg: %4[ 19 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %82[ 4 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+23 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %17[ LoopTag+51 ]
+# CHECK: Vreg: %43[ LoopTag+24 ]
+# CHECK: Vreg: %24[ LoopTag*2+41 ]
+# CHECK: Vreg: %31[ LoopTag+26 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ LoopTag+19 ]
+# CHECK: Vreg: %45[ LoopTag+13 ]
+# CHECK: Vreg: %26[ 16 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %28[ LoopTag+29 ]
+# CHECK: Vreg: %61[ LoopTag+14 ]
+# CHECK: Vreg: %4[ 19 ]
+# CHECK: Vreg: %11[ 14 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %82[ 4 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %65[ LoopTag+23 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %15[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %17[ LoopTag+51 ]
+# CHECK: Vreg: %43[ LoopTag+24 ]
+# CHECK: Vreg: %24[ LoopTag*2+41 ]
+# CHECK: Vreg: %31[ LoopTag+26 ]
+# CHECK: Vreg: %12:sub0[ LoopTag+37 ]
+# CHECK: Vreg: %12:sub1[ LoopTag+38 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: --- MBB_18 ---
+# CHECK: Instr: SI_END_CF killed %92, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 10 ]
+# CHECK: Vreg: %45[ 4 ]
+# CHECK: Vreg: %26[ 53 ]
+# CHECK: Vreg: %28[ 20 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %61[ 5 ]
+# CHECK: Vreg: %4[ 56 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %63[ 8 ]
+# CHECK: Vreg: %25[ 51 ]
+# CHECK: Vreg: %84[ 2 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %15[ 49 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %17[ 42 ]
+# CHECK: Vreg: %43[ 15 ]
+# CHECK: Vreg: %24[ LoopTag+32 ]
+# CHECK: Vreg: %31[ 17 ]
+# CHECK: Vreg: %12:sub0[ 28 ]
+# CHECK: Vreg: %12:sub1[ 29 ]
+# CHECK: Instr: %130:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 9 ]
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %26[ 52 ]
+# CHECK: Vreg: %28[ 19 ]
+# CHECK: Vreg: %61[ 4 ]
+# CHECK: Vreg: %4[ 55 ]
+# CHECK: Vreg: %11[ 5 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %25[ 50 ]
+# CHECK: Vreg: %84[ 1 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %15[ 48 ]
+# CHECK: Vreg: %60[ 4 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %74[ 12 ]
+# CHECK: Vreg: %17[ 41 ]
+# CHECK: Vreg: %43[ 14 ]
+# CHECK: Vreg: %24[ LoopTag+31 ]
+# CHECK: Vreg: %31[ 16 ]
+# CHECK: Vreg: %12:sub0[ 27 ]
+# CHECK: Vreg: %12:sub1[ 28 ]
+# CHECK: Instr: %134:sreg_32 = SI_IF killed %84, %bb.14, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 8 ]
+# CHECK: Vreg: %45[ 2 ]
+# CHECK: Vreg: %26[ 51 ]
+# CHECK: Vreg: %130[ 1 ]
+# CHECK: Vreg: %28[ 18 ]
+# CHECK: Vreg: %61[ 3 ]
+# CHECK: Vreg: %4[ 54 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %63[ 6 ]
+# CHECK: Vreg: %25[ 49 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %15[ 47 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %74[ 11 ]
+# CHECK: Vreg: %17[ 40 ]
+# CHECK: Vreg: %43[ 13 ]
+# CHECK: Vreg: %24[ LoopTag+30 ]
+# CHECK: Vreg: %31[ 15 ]
+# CHECK: Vreg: %12:sub0[ 26 ]
+# CHECK: Vreg: %12:sub1[ 27 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %26[ 50 ]
+# CHECK: Vreg: %130[ 0 ]
+# CHECK: Vreg: %28[ 17 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %25[ 48 ]
+# CHECK: Vreg: %134[ 1 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %60[ 2 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %74[ 10 ]
+# CHECK: Vreg: %17[ 39 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %31[ 14 ]
+# CHECK: Vreg: %12:sub0[ 25 ]
+# CHECK: Vreg: %12:sub1[ 26 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %26[ 50 ]
+# CHECK: Vreg: %130[ 0 ]
+# CHECK: Vreg: %28[ 17 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %25[ 48 ]
+# CHECK: Vreg: %134[ 1 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %15[ 46 ]
+# CHECK: Vreg: %60[ 2 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %74[ 10 ]
+# CHECK: Vreg: %17[ 39 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %24[ LoopTag+29 ]
+# CHECK: Vreg: %31[ 14 ]
+# CHECK: Vreg: %12:sub0[ 25 ]
+# CHECK: Vreg: %12:sub1[ 26 ]
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test12 (ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, i32 %TC1, i32 %TC2, i32 %Val, i1 %cond1, i1 %cond2) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  %add1 = add i32 %ld1, 100
+  br label %1
+  1:
+  %phi.inc1 = phi i32 [ 0, %0 ], [ %inc1, %5 ]
+  %sext = sext i32 %phi.inc1 to i64
+  %gep1 = getelementptr inbounds i64, ptr addrspace(1) %p2, i64 %sext
+  %ld2 = load i32, ptr addrspace(1) %gep1, align 1
+  br i1 %cond1, label %2, label %6
+  2:
+  %phi.inc2 = phi i32 [ 0, %1 ], [ %inc2, %4 ]
+  br i1 %cond2, label %3, label %7
+  3:
+  %mul1 = mul i32 %ld1, 100
+  store i32 %mul1, ptr addrspace(1) %p3
+  %cond3 = icmp ult i32 %mul1, %Val
+  br i1 %cond3, label %4, label %7
+  4:
+  %inc2 = add i32 %phi.inc2, 1
+  %cond4 = icmp ult i32 %inc2, %TC1
+  br i1 %cond4, label %2, label %5
+  5:
+  %inc1 = add i32 %phi.inc1, 1
+  %add2 = add i32 %ld2, %inc1
+  store i32 %add2, ptr addrspace(1) %p3
+  %cond5 = icmp ult i32 %inc1, %TC2
+  br i1 %cond5, label %1, label %8
+  6:
+  %mul2 = mul i32 %ld2, %phi.inc1
+  store i32 %mul2, ptr addrspace(1) %p3
+  br label %8
+  7:
+  %phi1 = phi i32 [ %phi.inc2, %2 ], [ %mul1, %3 ]
+  store i32 %phi1, ptr addrspace(1) %p3
+  br label %8
+  8:
+  %phi2 = phi i32 [ %add2, %5 ], [ %mul2, %6 ], [ %phi1, %7 ]
+  %add3 = add i32 %phi2, %add1
+  ret i32 %add3
+  }
+...
+
+---
+name:            test12
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10
+  
+    %64:vgpr_32 = COPY killed $vgpr10
+    %63:vgpr_32 = COPY killed $vgpr9
+    %62:vgpr_32 = COPY killed $vgpr8
+    %61:vgpr_32 = COPY killed $vgpr7
+    %60:vgpr_32 = COPY killed $vgpr6
+    %59:vgpr_32 = COPY killed $vgpr5
+    %58:vgpr_32 = COPY killed $vgpr4
+    %57:vgpr_32 = COPY killed $vgpr3
+    %56:vgpr_32 = COPY killed $vgpr2
+    %55:vgpr_32 = COPY killed $vgpr1
+    %54:vgpr_32 = COPY killed $vgpr0
+    %151:vreg_64 = REG_SEQUENCE killed %58, %subreg.sub0, killed %59, %subreg.sub1
+    %150:vreg_64 = REG_SEQUENCE killed %56, %subreg.sub0, killed %57, %subreg.sub1
+    %149:vreg_64 = REG_SEQUENCE killed %54, %subreg.sub0, killed %55, %subreg.sub1
+    %73:vgpr_32 = V_AND_B32_e64 1, killed %64, implicit $exec
+    %74:sreg_32 = V_CMP_EQ_U32_e64 1, killed %73, implicit $exec
+    %75:vgpr_32 = V_AND_B32_e64 1, killed %63, implicit $exec
+    %76:sreg_32 = V_CMP_EQ_U32_e64 1, killed %75, implicit $exec
+    %77:vgpr_32 = GLOBAL_LOAD_UBYTE %149, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %79:vgpr_32 = GLOBAL_LOAD_UBYTE %149, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %82:vgpr_32 = V_LSHL_OR_B32_e64 killed %79, 8, killed %77, implicit $exec
+    %83:vgpr_32 = GLOBAL_LOAD_UBYTE %149, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %85:vgpr_32 = GLOBAL_LOAD_UBYTE killed %149, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %87:vgpr_32 = V_LSHL_OR_B32_e64 killed %85, 8, killed %83, implicit $exec
+    %0:vgpr_32 = V_LSHL_OR_B32_e64 killed %87, 16, killed %82, implicit $exec
+    %1:vgpr_32 = V_MUL_LO_U32_e64 100, %0, implicit $exec
+    %90:sreg_32 = V_CMP_LT_U32_e64 %1, killed %62, implicit $exec
+    %69:sreg_32 = S_MOV_B32 0
+  
+  bb.1:
+    successors: %bb.2(0x40000000), %bb.3(0x40000000)
+  
+    %191:sreg_32 = PHI undef %190:sreg_32, %bb.0, %39, %bb.3
+    %187:sreg_32 = PHI undef %186:sreg_32, %bb.0, %38, %bb.3
+    %169:sreg_32 = PHI undef %166:sreg_32, %bb.0, %12, %bb.3
+    %164:sreg_32 = PHI undef %161:sreg_32, %bb.0, %9, %bb.3
+    %157:sreg_32 = PHI undef %154:sreg_32, %bb.0, %8, %bb.3
+    %3:sreg_32 = PHI %69, %bb.0, %13, %bb.3
+    %4:sreg_32 = PHI %69, %bb.0, %7, %bb.3
+    %95:sreg_32_xm0 = S_ASHR_I32 %4, 31, implicit-def dead $scc
+    %97:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, killed %95, %subreg.sub1
+    %99:sreg_64 = nsw S_LSHL_B64 killed %97, 3, implicit-def dead $scc
+    %200:vgpr_32, %202:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %150.sub0, %99.sub0, 0, implicit $exec
+    %201:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %99.sub1, %150.sub1, killed %202, 0, implicit $exec
+    %100:vreg_64 = REG_SEQUENCE killed %200, %subreg.sub0, killed %201, %subreg.sub1
+    %101:vgpr_32 = GLOBAL_LOAD_UBYTE %100, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+    %102:vgpr_32 = GLOBAL_LOAD_UBYTE %100, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+    %104:vgpr_32 = V_LSHL_OR_B32_e64 killed %102, 8, killed %101, implicit $exec
+    %105:vgpr_32 = GLOBAL_LOAD_UBYTE %100, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+    %106:vgpr_32 = GLOBAL_LOAD_UBYTE killed %100, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+    %107:vgpr_32 = V_LSHL_OR_B32_e64 killed %106, 8, killed %105, implicit $exec
+    %5:vgpr_32 = V_LSHL_OR_B32_e64 killed %107, 16, killed %104, implicit $exec
+    %158:sreg_32 = S_ANDN2_B32 killed %157, $exec_lo, implicit-def dead $scc
+    %155:sreg_32 = COPY %158
+    %162:sreg_32 = S_OR_B32 killed %164, $exec_lo, implicit-def dead $scc
+    %167:sreg_32 = S_OR_B32 killed %169, $exec_lo, implicit-def dead $scc
+    %6:sreg_32 = SI_IF %76, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+  
+  bb.2:
+    successors: %bb.4(0x80000000)
+  
+    %112:sreg_32 = S_MOV_B32 0
+    S_BRANCH %bb.4
+  
+  bb.3:
+    successors: %bb.15(0x04000000), %bb.1(0x7c000000)
+  
+    %12:sreg_32 = PHI %167, %bb.1, %168, %bb.14
+    %9:sreg_32 = PHI %162, %bb.1, %163, %bb.14
+    %8:sreg_32 = PHI %155, %bb.1, %156, %bb.14
+    %7:sreg_32 = PHI undef %91:sreg_32, %bb.1, %34, %bb.14
+    %10:vgpr_32 = PHI undef %94:vgpr_32, %bb.1, %20, %bb.14
+    %11:vgpr_32 = PHI undef %94:vgpr_32, %bb.1, %36, %bb.14
+    SI_END_CF killed %6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %13:sreg_32 = SI_IF_BREAK %12, killed %3, implicit-def dead $scc
+    %153:vgpr_32 = COPY killed %4, implicit $exec
+    %188:sreg_32 = S_ANDN2_B32 killed %187, $exec_lo, implicit-def dead $scc
+    %189:sreg_32 = S_AND_B32 %8, $exec_lo, implicit-def dead $scc
+    %38:sreg_32 = S_OR_B32 killed %188, killed %189, implicit-def dead $scc
+    %192:sreg_32 = S_ANDN2_B32 killed %191, $exec_lo, implicit-def dead $scc
+    %193:sreg_32 = S_AND_B32 %9, $exec_lo, implicit-def dead $scc
+    %39:sreg_32 = S_OR_B32 killed %192, killed %193, implicit-def dead $scc
+    SI_LOOP %13, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.15
+  
+  bb.4:
+    successors: %bb.5(0x40000000), %bb.6(0x40000000)
+  
+    %197:sreg_32 = PHI undef %196:sreg_32, %bb.2, %51, %bb.6
+    %181:sreg_32 = PHI undef %178:sreg_32, %bb.2, %21, %bb.6
+    %175:sreg_32 = PHI undef %172:sreg_32, %bb.2, %19, %bb.6
+    %14:sreg_32 = PHI %112, %bb.2, %23, %bb.6
+    %15:sreg_32 = PHI %112, %bb.2, %18, %bb.6
+    %152:vgpr_32 = COPY %15, implicit $exec
+    %173:sreg_32 = S_OR_B32 killed %175, $exec_lo, implicit-def dead $scc
+    %179:sreg_32 = S_OR_B32 killed %181, $exec_lo, implicit-def dead $scc
+    %16:sreg_32 = SI_IF %74, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.5
+  
+  bb.5:
+    successors: %bb.7(0x40000000), %bb.17(0x40000000)
+  
+    GLOBAL_STORE_DWORD %151, %1, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    %119:sreg_32 = S_MOV_B32 -1
+    %17:sreg_32 = SI_IF %90, %bb.17, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.7
+  
+  bb.6:
+    successors: %bb.18(0x04000000), %bb.4(0x7c000000)
+  
+    %21:sreg_32 = PHI %179, %bb.4, %180, %bb.17
+    %19:sreg_32 = PHI %173, %bb.4, %174, %bb.17
+    %18:sreg_32 = PHI undef %113:sreg_32, %bb.4, %47, %bb.17
+    %20:vgpr_32 = PHI %152, %bb.4, %1, %bb.17
+    SI_END_CF killed %16, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %126:sreg_32 = S_XOR_B32 %19, -1, implicit-def dead $scc
+    %23:sreg_32 = SI_IF_BREAK %21, killed %14, implicit-def dead $scc
+    %198:sreg_32 = S_ANDN2_B32 killed %197, $exec_lo, implicit-def dead $scc
+    %199:sreg_32 = S_AND_B32 killed %126, $exec_lo, implicit-def dead $scc
+    %51:sreg_32 = S_OR_B32 killed %198, killed %199, implicit-def dead $scc
+    SI_LOOP %23, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.18
+  
+  bb.7:
+    successors: %bb.17(0x80000000)
+  
+    %24:sreg_32 = S_ADD_I32 killed %15, 1, implicit-def dead $scc
+    %123:sreg_32 = V_CMP_GE_U32_e64 %24, %60, implicit $exec
+    %194:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+    %195:sreg_32 = S_ORN2_B32 killed %123, $exec_lo, implicit-def dead $scc
+    S_BRANCH %bb.17
+  
+  bb.8:
+    successors: %bb.14(0x80000000)
+  
+    %26:sreg_32 = S_ADD_I32 %4, 1, implicit-def dead $scc
+    %27:vgpr_32 = V_ADD_U32_e64 %26, %5, 0, implicit $exec
+    GLOBAL_STORE_DWORD %151, %27, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    %136:sreg_32 = V_CMP_GE_U32_e64 %26, %61, implicit $exec
+    %184:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+    %185:sreg_32 = S_ORN2_B32 killed %136, $exec_lo, implicit-def dead $scc
+    S_BRANCH %bb.14
+  
+  bb.9:
+    successors: %bb.10(0x40000000), %bb.13(0x40000000)
+  
+    %29:vgpr_32 = PHI undef %141:vgpr_32, %bb.15, %32, %bb.12
+    %203:vreg_64 = PHI %151, %bb.15, undef %204:vreg_64, %bb.12
+    %30:sreg_32 = SI_ELSE killed %45, %bb.13, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.10
+  
+  bb.10:
+    successors: %bb.13(0x80000000)
+  
+    %31:vgpr_32 = V_MUL_LO_U32_e64 killed %5, killed %153, implicit $exec
+    GLOBAL_STORE_DWORD killed %203, %31, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    S_BRANCH %bb.13
+  
+  bb.11:
+    successors: %bb.12(0x80000000)
+  
+    GLOBAL_STORE_DWORD killed %151, %10, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+  
+  bb.12:
+    successors: %bb.9(0x80000000)
+  
+    %32:vgpr_32 = PHI %11, %bb.16, %10, %bb.11
+    SI_END_CF killed %46, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.9
+  
+  bb.13:
+    %33:vgpr_32 = PHI %29, %bb.9, %31, %bb.10
+    SI_END_CF killed %30, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %147:vgpr_32 = V_ADD3_U32_e64 killed %0, killed %33, 100, implicit $exec
+    %148:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %147, implicit $exec
+    $sgpr0 = COPY killed %148
+    SI_RETURN_TO_EPILOG killed $sgpr0
+  
+  bb.14:
+    successors: %bb.3(0x80000000)
+  
+    %37:sreg_32 = PHI %132, %bb.18, %185, %bb.8
+    %35:sreg_32 = PHI %132, %bb.18, %184, %bb.8
+    %34:sreg_32 = PHI undef %129:sreg_32, %bb.18, %26, %bb.8
+    %36:vgpr_32 = PHI undef %131:vgpr_32, %bb.18, %27, %bb.8
+    SI_END_CF killed %53, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %159:sreg_32 = S_ANDN2_B32 killed %158, $exec_lo, implicit-def dead $scc
+    %160:sreg_32 = S_AND_B32 killed %35, $exec_lo, implicit-def dead $scc
+    %156:sreg_32 = S_OR_B32 killed %159, killed %160, implicit-def dead $scc
+    %165:sreg_32 = S_ANDN2_B32 killed %162, $exec_lo, implicit-def dead $scc
+    %163:sreg_32 = COPY killed %165
+    %170:sreg_32 = S_ANDN2_B32 killed %167, $exec_lo, implicit-def dead $scc
+    %171:sreg_32 = S_AND_B32 killed %37, $exec_lo, implicit-def dead $scc
+    %168:sreg_32 = S_OR_B32 killed %170, killed %171, implicit-def dead $scc
+    S_BRANCH %bb.3
+  
+  bb.15:
+    successors: %bb.16(0x40000000), %bb.9(0x40000000)
+  
+    SI_END_CF killed %13, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %143:sreg_32 = S_XOR_B32 killed %39, -1, implicit-def dead $scc
+    %45:sreg_32 = SI_IF killed %143, %bb.9, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.16
+  
+  bb.16:
+    successors: %bb.11(0x40000000), %bb.12(0x40000000)
+  
+    %46:sreg_32 = SI_IF killed %38, %bb.12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.11
+  
+  bb.17:
+    successors: %bb.6(0x80000000)
+  
+    %49:sreg_32 = PHI %119, %bb.5, %195, %bb.7
+    %48:sreg_32 = PHI %119, %bb.5, %194, %bb.7
+    %47:sreg_32 = PHI undef %117:sreg_32, %bb.5, %24, %bb.7
+    SI_END_CF killed %17, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %176:sreg_32 = S_ANDN2_B32 killed %173, $exec_lo, implicit-def dead $scc
+    %177:sreg_32 = S_AND_B32 killed %48, $exec_lo, implicit-def dead $scc
+    %174:sreg_32 = S_OR_B32 killed %176, killed %177, implicit-def dead $scc
+    %182:sreg_32 = S_ANDN2_B32 killed %179, $exec_lo, implicit-def dead $scc
+    %183:sreg_32 = S_AND_B32 killed %49, $exec_lo, implicit-def dead $scc
+    %180:sreg_32 = S_OR_B32 killed %182, killed %183, implicit-def dead $scc
+    S_BRANCH %bb.6
+  
+  bb.18:
+    successors: %bb.8(0x40000000), %bb.14(0x40000000)
+  
+    SI_END_CF killed %23, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %132:sreg_32 = S_MOV_B32 -1
+    %53:sreg_32 = SI_IF killed %51, %bb.14, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.8
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-b.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-b.mir
new file mode 100644
index 0000000000000..400d777c6497f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-b.mir
@@ -0,0 +1,24320 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#                                       bb.0.entry
+#                                           |
+#                                       bb.1.loop1.header<----+
+#                                           |        |        |
+#                       bb.2.loop2.header.preheader  |        |
+#                                           |        |        |
+#            +------------------->bb.4.loop2.header  |        |
+#            |                         /      |      |        |
+#            |                    bb.7.bb1    |      |        |
+#            |                     /    |     |      |        |
+#            |       bb.9.loop2.latch2  |     |      |        |
+#            |                     \    |     |      |        |
+#            |                  bb.5.Flow28   |      |        |
+#            |                         \      |      |        |
+#            |                       bb.8.Flow27     |        |
+#            |                         /      |      |        |
+#            |            bb.6.loop2.latch1   |      |        |
+#            |                         \      |      |        |
+#            +-----------------------bb.37.Flow29    |        |
+#                                         |          |        |
+#                           bb.38.loop.exit.guard23  |        |
+#                                   /     |          |        |
+#                             bb.14.bb3   |          |        |
+#                                   \     |          |        |
+#                                 bb.10.Flow31       |        |
+#                                     |     |        |        |
+#                     bb.11.loop2.side.exit |        |        |
+#                            /        |     |        |        |
+#                     bb.13.bb2       |     |        |        |
+#                            \        |     |        |        |
+#                           bb.15.Flow33    |        |        |
+#                                \          |        |        |
+#                                bb.12.Flow32        |        |
+#                                     |     |        |        |
+#                                 bb.16.bb4 |        |        |
+#                                  /     |  |        |        |
+#                            bb.18.bb5   |  |        |        |
+#                             /     |    |  |        |        |
+#              bb.24.loop1.latch3   |    |  |        |        |
+#                             \     |    |  |        |        |
+#                         bb.21.Flow36   |  |        |        |
+#                                   |    |  |        |        |
+#                              bb.23.Flow35 |        |        |
+#                                /       |  |        |        |
+#                  bb.22.loop1.latch2    |  |        |        |
+#                                \       |  |        |        |
+#                              bb.19.Flow37 |        |        |
+#                                   \       |        |        |
+#                                 bb.17.Flow34       |        |
+#                                   /       |        |        |
+#                     bb.20.loop1.latch1    |        |        |
+#                                   \       |        |        |
+#                                 bb.33.Flow38       |        |
+#                                          \         |        |
+#                                           bb.3.Flow30-------+
+#                                               |
+#                                     bb.34.loop.exit.guard
+#                                        /               |
+#                            bb.35.loop.exit.guard21     |
+#                                      /        |        |
+#                      bb.36.loop.exit.guard22  |        |
+#                                /    |         |        |
+#            bb.29.loop1.side.exit3   |         |        |
+#                                \    |         |        |
+#                              bb.30.Flow       |        |
+#                                       \       |        |
+#                                      bb.27.Flow24      |
+#                                       /       |        |
+#                      bb.28.loop1.side.exit2   |        |
+#                                       \       |        |
+#                                      bb.31.Flow25	 |
+#                                               \        |
+#                                              bb.25.Flow26
+#                                               /      |
+#                             bb.26.loop1.sode.exit1   |
+#                                               \      |
+#                                              bb.32.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test15 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr17
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr16
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 93 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %1[ 127 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 91 ]
+# CHECK: Vreg: %2[ 110 ]
+# CHECK: Vreg: %1[ 126 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 90 ]
+# CHECK: Vreg: %2[ 109 ]
+# CHECK: Vreg: %1[ 125 ]
+# CHECK: Vreg: %3[ 95 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 89 ]
+# CHECK: Vreg: %2[ 108 ]
+# CHECK: Vreg: %4[ 95 ]
+# CHECK: Vreg: %1[ 124 ]
+# CHECK: Vreg: %3[ 94 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %3[ 93 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 87 ]
+# CHECK: Vreg: %2[ 106 ]
+# CHECK: Vreg: %4[ 93 ]
+# CHECK: Vreg: %6[ 11 ]
+# CHECK: Vreg: %1[ 122 ]
+# CHECK: Vreg: %3[ 92 ]
+# CHECK: Vreg: %5[ 91 ]
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 86 ]
+# CHECK: Vreg: %7[ 10 ]
+# CHECK: Vreg: %2[ 105 ]
+# CHECK: Vreg: %4[ 92 ]
+# CHECK: Vreg: %6[ 10 ]
+# CHECK: Vreg: %1[ 121 ]
+# CHECK: Vreg: %3[ 91 ]
+# CHECK: Vreg: %5[ 90 ]
+# CHECK: Instr: %9:vgpr_32 = COPY killed $vgpr8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %7[ 9 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %6[ 9 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %8[ 10 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Instr: %10:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 84 ]
+# CHECK: Vreg: %7[ 8 ]
+# CHECK: Vreg: %2[ 103 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %6[ 8 ]
+# CHECK: Vreg: %1[ 119 ]
+# CHECK: Vreg: %8[ 9 ]
+# CHECK: Vreg: %3[ 89 ]
+# CHECK: Vreg: %5[ 88 ]
+# CHECK: Instr: %11:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 83 ]
+# CHECK: Vreg: %7[ 7 ]
+# CHECK: Vreg: %2[ 102 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %4[ 89 ]
+# CHECK: Vreg: %6[ 7 ]
+# CHECK: Vreg: %1[ 118 ]
+# CHECK: Vreg: %8[ 8 ]
+# CHECK: Vreg: %3[ 88 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %5[ 87 ]
+# CHECK: Instr: %12:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 82 ]
+# CHECK: Vreg: %7[ 6 ]
+# CHECK: Vreg: %2[ 101 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %4[ 88 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %6[ 6 ]
+# CHECK: Vreg: %1[ 117 ]
+# CHECK: Vreg: %8[ 7 ]
+# CHECK: Vreg: %3[ 87 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %5[ 86 ]
+# CHECK: Instr: %13:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 81 ]
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %2[ 100 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %4[ 87 ]
+# CHECK: Vreg: %11[ 7 ]
+# CHECK: Vreg: %6[ 5 ]
+# CHECK: Vreg: %1[ 116 ]
+# CHECK: Vreg: %8[ 6 ]
+# CHECK: Vreg: %3[ 86 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %5[ 85 ]
+# CHECK: Vreg: %12[ 8 ]
+# CHECK: Instr: %14:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 80 ]
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %2[ 99 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %4[ 86 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %6[ 4 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %1[ 115 ]
+# CHECK: Vreg: %8[ 5 ]
+# CHECK: Vreg: %3[ 85 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %5[ 84 ]
+# CHECK: Vreg: %12[ 7 ]
+# CHECK: Instr: %15:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 79 ]
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %14[ 7 ]
+# CHECK: Vreg: %2[ 98 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 85 ]
+# CHECK: Vreg: %11[ 5 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %13[ 6 ]
+# CHECK: Vreg: %1[ 114 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: Vreg: %3[ 84 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %5[ 83 ]
+# CHECK: Vreg: %12[ 6 ]
+# CHECK: Instr: %16:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 78 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %2[ 97 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 84 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %13[ 5 ]
+# CHECK: Vreg: %1[ 113 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %3[ 83 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %5[ 82 ]
+# CHECK: Vreg: %12[ 5 ]
+# CHECK: Instr: %17:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 77 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %14[ 5 ]
+# CHECK: Vreg: %2[ 96 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %16[ 6 ]
+# CHECK: Vreg: %4[ 83 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %1[ 112 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %5[ 81 ]
+# CHECK: Vreg: %12[ 4 ]
+# CHECK: Instr: %18:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, killed %6, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 76 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %14[ 4 ]
+# CHECK: Vreg: %2[ 95 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %16[ 5 ]
+# CHECK: Vreg: %4[ 82 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %1[ 111 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %3[ 81 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %17[ 5 ]
+# CHECK: Vreg: %5[ 80 ]
+# CHECK: Vreg: %12[ 3 ]
+# CHECK: Instr: %19:vreg_64 = REG_SEQUENCE killed %9, %subreg.sub0, killed %8, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 75 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %2[ 94 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %16[ 4 ]
+# CHECK: Vreg: %4[ 81 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %18[ 91 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 110 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %3[ 80 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %17[ 4 ]
+# CHECK: Vreg: %5[ 79 ]
+# CHECK: Vreg: %12[ 2 ]
+# CHECK: Instr: %20:vreg_64 = REG_SEQUENCE killed %11, %subreg.sub0, killed %10, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 74 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %2[ 93 ]
+# CHECK: Vreg: %16[ 3 ]
+# CHECK: Vreg: %4[ 80 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %18[ 90 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 109 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %3[ 79 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Vreg: %5[ 78 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Vreg: %19:sub0[ 44 ]
+# CHECK: Vreg: %19:sub1[ 45 ]
+# CHECK: Vreg: %19[ 57 ]
+# CHECK: Instr: %21:vreg_64 = REG_SEQUENCE killed %13, %subreg.sub0, killed %12, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 73 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %2[ 92 ]
+# CHECK: Vreg: %16[ 2 ]
+# CHECK: Vreg: %4[ 79 ]
+# CHECK: Vreg: %18[ 89 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %20[ 67 ]
+# CHECK: Vreg: %1[ 108 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %3[ 78 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %5[ 77 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Vreg: %19:sub0[ 43 ]
+# CHECK: Vreg: %19:sub1[ 44 ]
+# CHECK: Vreg: %19[ 56 ]
+# CHECK: Instr: %22:vreg_64 = REG_SEQUENCE killed %15, %subreg.sub0, killed %14, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 72 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %21[ 70 ]
+# CHECK: Vreg: %2[ 91 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %4[ 78 ]
+# CHECK: Vreg: %18[ 88 ]
+# CHECK: Vreg: %20[ 66 ]
+# CHECK: Vreg: %1[ 107 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 77 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %5[ 76 ]
+# CHECK: Vreg: %19:sub0[ 42 ]
+# CHECK: Vreg: %19:sub1[ 43 ]
+# CHECK: Vreg: %19[ 55 ]
+# CHECK: Instr: %23:vreg_64 = REG_SEQUENCE killed %17, %subreg.sub0, killed %16, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %24:vgpr_32 = GLOBAL_LOAD_UBYTE %23, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 70 ]
+# CHECK: Vreg: %21[ 68 ]
+# CHECK: Vreg: %2[ 89 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %4[ 76 ]
+# CHECK: Vreg: %18[ 86 ]
+# CHECK: Vreg: %20[ 64 ]
+# CHECK: Vreg: %1[ 105 ]
+# CHECK: Vreg: %22:sub0[ 16 ]
+# CHECK: Vreg: %22:sub1[ 17 ]
+# CHECK: Vreg: %22[ 81 ]
+# CHECK: Vreg: %3[ 75 ]
+# CHECK: Vreg: %5[ 74 ]
+# CHECK: Vreg: %19:sub0[ 40 ]
+# CHECK: Vreg: %19:sub1[ 41 ]
+# CHECK: Vreg: %19[ 53 ]
+# CHECK: Instr: %25:vgpr_32 = GLOBAL_LOAD_UBYTE %23, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 69 ]
+# CHECK: Vreg: %21[ 67 ]
+# CHECK: Vreg: %2[ 88 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %4[ 75 ]
+# CHECK: Vreg: %18[ 85 ]
+# CHECK: Vreg: %20[ 63 ]
+# CHECK: Vreg: %1[ 104 ]
+# CHECK: Vreg: %22:sub0[ 15 ]
+# CHECK: Vreg: %22:sub1[ 16 ]
+# CHECK: Vreg: %22[ 80 ]
+# CHECK: Vreg: %3[ 74 ]
+# CHECK: Vreg: %24[ 1 ]
+# CHECK: Vreg: %5[ 73 ]
+# CHECK: Vreg: %19:sub0[ 39 ]
+# CHECK: Vreg: %19:sub1[ 40 ]
+# CHECK: Vreg: %19[ 52 ]
+# CHECK: Instr: %26:vgpr_32 = V_LSHL_OR_B32_e64 killed %25, 8, killed %24, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 68 ]
+# CHECK: Vreg: %21[ 66 ]
+# CHECK: Vreg: %2[ 87 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %4[ 74 ]
+# CHECK: Vreg: %18[ 84 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %20[ 62 ]
+# CHECK: Vreg: %1[ 103 ]
+# CHECK: Vreg: %22:sub0[ 14 ]
+# CHECK: Vreg: %22:sub1[ 15 ]
+# CHECK: Vreg: %22[ 79 ]
+# CHECK: Vreg: %3[ 73 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %5[ 72 ]
+# CHECK: Vreg: %19:sub0[ 38 ]
+# CHECK: Vreg: %19:sub1[ 39 ]
+# CHECK: Vreg: %19[ 51 ]
+# CHECK: Instr: %27:vgpr_32 = GLOBAL_LOAD_UBYTE %23, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 67 ]
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %21[ 65 ]
+# CHECK: Vreg: %2[ 86 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %18[ 83 ]
+# CHECK: Vreg: %20[ 61 ]
+# CHECK: Vreg: %1[ 102 ]
+# CHECK: Vreg: %22:sub0[ 13 ]
+# CHECK: Vreg: %22:sub1[ 14 ]
+# CHECK: Vreg: %22[ 78 ]
+# CHECK: Vreg: %3[ 72 ]
+# CHECK: Vreg: %5[ 71 ]
+# CHECK: Vreg: %19:sub0[ 37 ]
+# CHECK: Vreg: %19:sub1[ 38 ]
+# CHECK: Vreg: %19[ 50 ]
+# CHECK: Instr: %28:vgpr_32 = GLOBAL_LOAD_UBYTE %23, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 66 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %21[ 64 ]
+# CHECK: Vreg: %2[ 85 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %4[ 72 ]
+# CHECK: Vreg: %18[ 82 ]
+# CHECK: Vreg: %20[ 60 ]
+# CHECK: Vreg: %1[ 101 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %22:sub0[ 12 ]
+# CHECK: Vreg: %22:sub1[ 13 ]
+# CHECK: Vreg: %22[ 77 ]
+# CHECK: Vreg: %3[ 71 ]
+# CHECK: Vreg: %5[ 70 ]
+# CHECK: Vreg: %19:sub0[ 36 ]
+# CHECK: Vreg: %19:sub1[ 37 ]
+# CHECK: Vreg: %19[ 49 ]
+# CHECK: Instr: %29:vgpr_32 = V_LSHL_OR_B32_e64 killed %28, 8, killed %27, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 65 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %21[ 63 ]
+# CHECK: Vreg: %2[ 84 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %23[ 21 ]
+# CHECK: Vreg: %4[ 71 ]
+# CHECK: Vreg: %18[ 81 ]
+# CHECK: Vreg: %20[ 59 ]
+# CHECK: Vreg: %1[ 100 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %22:sub0[ 11 ]
+# CHECK: Vreg: %22:sub1[ 12 ]
+# CHECK: Vreg: %22[ 76 ]
+# CHECK: Vreg: %3[ 70 ]
+# CHECK: Vreg: %5[ 69 ]
+# CHECK: Vreg: %19:sub0[ 35 ]
+# CHECK: Vreg: %19:sub1[ 36 ]
+# CHECK: Vreg: %19[ 48 ]
+# CHECK: Instr: %30:vgpr_32 = V_LSHL_OR_B32_e64 killed %29, 16, killed %26, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 64 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %21[ 62 ]
+# CHECK: Vreg: %2[ 83 ]
+# CHECK: Vreg: %23[ 20 ]
+# CHECK: Vreg: %4[ 70 ]
+# CHECK: Vreg: %18[ 80 ]
+# CHECK: Vreg: %20[ 58 ]
+# CHECK: Vreg: %1[ 99 ]
+# CHECK: Vreg: %22:sub0[ 10 ]
+# CHECK: Vreg: %22:sub1[ 11 ]
+# CHECK: Vreg: %22[ 75 ]
+# CHECK: Vreg: %3[ 69 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %5[ 68 ]
+# CHECK: Vreg: %19:sub0[ 34 ]
+# CHECK: Vreg: %19:sub1[ 35 ]
+# CHECK: Vreg: %19[ 47 ]
+# CHECK: Instr: %31:vgpr_32 = V_MOV_B32_e32 500, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 63 ]
+# CHECK: Vreg: %21[ 61 ]
+# CHECK: Vreg: %2[ 82 ]
+# CHECK: Vreg: %23[ 19 ]
+# CHECK: Vreg: %4[ 69 ]
+# CHECK: Vreg: %30[ 43 ]
+# CHECK: Vreg: %18[ 79 ]
+# CHECK: Vreg: %20[ 57 ]
+# CHECK: Vreg: %1[ 98 ]
+# CHECK: Vreg: %22:sub0[ 9 ]
+# CHECK: Vreg: %22:sub1[ 10 ]
+# CHECK: Vreg: %22[ 74 ]
+# CHECK: Vreg: %3[ 68 ]
+# CHECK: Vreg: %5[ 67 ]
+# CHECK: Vreg: %19:sub0[ 33 ]
+# CHECK: Vreg: %19:sub1[ 34 ]
+# CHECK: Vreg: %19[ 46 ]
+# CHECK: Instr: %32:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 62 ]
+# CHECK: Vreg: %21[ 60 ]
+# CHECK: Vreg: %2[ 81 ]
+# CHECK: Vreg: %23[ 18 ]
+# CHECK: Vreg: %4[ 68 ]
+# CHECK: Vreg: %30[ 42 ]
+# CHECK: Vreg: %18[ 78 ]
+# CHECK: Vreg: %20[ 56 ]
+# CHECK: Vreg: %1[ 97 ]
+# CHECK: Vreg: %22:sub0[ 8 ]
+# CHECK: Vreg: %22:sub1[ 9 ]
+# CHECK: Vreg: %22[ 73 ]
+# CHECK: Vreg: %3[ 67 ]
+# CHECK: Vreg: %5[ 66 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Vreg: %19:sub0[ 32 ]
+# CHECK: Vreg: %19:sub1[ 33 ]
+# CHECK: Vreg: %19[ 45 ]
+# CHECK: Instr: %33:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 61 ]
+# CHECK: Vreg: %21[ 59 ]
+# CHECK: Vreg: %2[ 80 ]
+# CHECK: Vreg: %23[ 17 ]
+# CHECK: Vreg: %4[ 67 ]
+# CHECK: Vreg: %30[ 41 ]
+# CHECK: Vreg: %18[ 77 ]
+# CHECK: Vreg: %32[ 3 ]
+# CHECK: Vreg: %20[ 55 ]
+# CHECK: Vreg: %1[ 96 ]
+# CHECK: Vreg: %22:sub0[ 7 ]
+# CHECK: Vreg: %22:sub1[ 8 ]
+# CHECK: Vreg: %22[ 72 ]
+# CHECK: Vreg: %3[ 66 ]
+# CHECK: Vreg: %5[ 65 ]
+# CHECK: Vreg: %31[ 3 ]
+# CHECK: Vreg: %19:sub0[ 31 ]
+# CHECK: Vreg: %19:sub1[ 32 ]
+# CHECK: Vreg: %19[ 44 ]
+# CHECK: Instr: %34:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 60 ]
+# CHECK: Vreg: %33[ 2 ]
+# CHECK: Vreg: %21[ 58 ]
+# CHECK: Vreg: %2[ 79 ]
+# CHECK: Vreg: %23[ 16 ]
+# CHECK: Vreg: %4[ 66 ]
+# CHECK: Vreg: %30[ 40 ]
+# CHECK: Vreg: %18[ 76 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %20[ 54 ]
+# CHECK: Vreg: %1[ 95 ]
+# CHECK: Vreg: %22:sub0[ 6 ]
+# CHECK: Vreg: %22:sub1[ 7 ]
+# CHECK: Vreg: %22[ 71 ]
+# CHECK: Vreg: %3[ 65 ]
+# CHECK: Vreg: %5[ 64 ]
+# CHECK: Vreg: %31[ 2 ]
+# CHECK: Vreg: %19:sub0[ 30 ]
+# CHECK: Vreg: %19:sub1[ 31 ]
+# CHECK: Vreg: %19[ 43 ]
+# CHECK: Instr: %35:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 59 ]
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %21[ 57 ]
+# CHECK: Vreg: %2[ 78 ]
+# CHECK: Vreg: %23[ 15 ]
+# CHECK: Vreg: %4[ 65 ]
+# CHECK: Vreg: %30[ 39 ]
+# CHECK: Vreg: %18[ 75 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %20[ 53 ]
+# CHECK: Vreg: %1[ 94 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %22:sub0[ 5 ]
+# CHECK: Vreg: %22:sub1[ 6 ]
+# CHECK: Vreg: %22[ 70 ]
+# CHECK: Vreg: %3[ 64 ]
+# CHECK: Vreg: %5[ 63 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: Vreg: %19:sub0[ 29 ]
+# CHECK: Vreg: %19:sub1[ 30 ]
+# CHECK: Vreg: %19[ 42 ]
+# CHECK: Instr: %36:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %37:sreg_32 = PHI undef %38:sreg_32, %bb.0, %39, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %40:sreg_32 = PHI undef %41:sreg_32, %bb.0, %42, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %43:sreg_32 = PHI undef %44:sreg_32, %bb.0, %45, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %46:sreg_32 = PHI undef %47:sreg_32, %bb.0, %48, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %49:sreg_32 = PHI undef %50:sreg_32, %bb.0, %51, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %52:sreg_32 = PHI undef %53:sreg_32, %bb.0, %54, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %49[ 20 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %55:sreg_32 = PHI undef %56:sreg_32, %bb.0, %57, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %52[ 18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %49[ 20 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %58:sreg_32 = PHI %35, %bb.0, %59, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %52[ 18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %49[ 20 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %55[ 16 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %60:vgpr_32 = PHI undef %61:vgpr_32, %bb.0, %62, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %52[ 18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %49[ 20 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %55[ 16 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %63:vgpr_32 = PHI undef %61:vgpr_32, %bb.0, %64, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %52[ 18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %49[ 20 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %60[ 23 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %55[ 16 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %65:vgpr_32 = PHI %36, %bb.0, %66, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %52[ 18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %49[ 20 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %63[ 23 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %60[ 23 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %55[ 16 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %67:vgpr_32 = PHI %34, %bb.0, %68, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %52[ 18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %49[ 20 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %63[ 23 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %60[ 23 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %55[ 16 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %69:vgpr_32 = PHI %33, %bb.0, %70, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %52[ 18 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %49[ 20 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %63[ 23 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %60[ 23 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %55[ 16 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %71:vgpr_32 = PHI %32, %bb.0, %72, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %52[ 18 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %49[ 20 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %63[ 23 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %60[ 23 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %55[ 16 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %69[ 23 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %73:vgpr_32 = PHI %31, %bb.0, %74, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %71[ 23 ]
+# CHECK: Vreg: %52[ 18 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %49[ 20 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %63[ 23 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %46[ 21 ]
+# CHECK: Vreg: %60[ 23 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %55[ 16 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %69[ 23 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Instr: %75:vgpr_32 = V_ASHRREV_I32_e64 31, %65, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 57 ]
+# CHECK: Vreg: %71[ 22 ]
+# CHECK: Vreg: %52[ 17 ]
+# CHECK: Vreg: %40[ 28 ]
+# CHECK: Vreg: %21[ 55 ]
+# CHECK: Vreg: %2[ 76 ]
+# CHECK: Vreg: %73[ 22 ]
+# CHECK: Vreg: %23[ 13 ]
+# CHECK: Vreg: %4[ 63 ]
+# CHECK: Vreg: %49[ 19 ]
+# CHECK: Vreg: %30[ 37 ]
+# CHECK: Vreg: %37[ 31 ]
+# CHECK: Vreg: %18[ 73 ]
+# CHECK: Vreg: %63[ 22 ]
+# CHECK: Vreg: %58[ 24 ]
+# CHECK: Vreg: %20[ 51 ]
+# CHECK: Vreg: %1[ 92 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %46[ 20 ]
+# CHECK: Vreg: %60[ 22 ]
+# CHECK: Vreg: %22:sub0[ 3 ]
+# CHECK: Vreg: %22:sub1[ 4 ]
+# CHECK: Vreg: %22[ 68 ]
+# CHECK: Vreg: %67[ 14 ]
+# CHECK: Vreg: %3[ 62 ]
+# CHECK: Vreg: %55[ 15 ]
+# CHECK: Vreg: %43[ 25 ]
+# CHECK: Vreg: %5[ 61 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %19:sub0[ 27 ]
+# CHECK: Vreg: %19:sub1[ 28 ]
+# CHECK: Vreg: %19[ 40 ]
+# CHECK: Instr: %76:vreg_64 = REG_SEQUENCE %65, %subreg.sub0, killed %75, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 56 ]
+# CHECK: Vreg: %71[ 21 ]
+# CHECK: Vreg: %52[ 16 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 54 ]
+# CHECK: Vreg: %2[ 75 ]
+# CHECK: Vreg: %73[ 21 ]
+# CHECK: Vreg: %23[ 12 ]
+# CHECK: Vreg: %4[ 62 ]
+# CHECK: Vreg: %49[ 18 ]
+# CHECK: Vreg: %30[ 36 ]
+# CHECK: Vreg: %75[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 72 ]
+# CHECK: Vreg: %63[ 21 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 50 ]
+# CHECK: Vreg: %1[ 91 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %46[ 19 ]
+# CHECK: Vreg: %60[ 21 ]
+# CHECK: Vreg: %22:sub0[ 2 ]
+# CHECK: Vreg: %22:sub1[ 3 ]
+# CHECK: Vreg: %22[ 67 ]
+# CHECK: Vreg: %67[ 13 ]
+# CHECK: Vreg: %3[ 61 ]
+# CHECK: Vreg: %55[ 14 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 60 ]
+# CHECK: Vreg: %69[ 21 ]
+# CHECK: Vreg: %19:sub0[ 26 ]
+# CHECK: Vreg: %19:sub1[ 27 ]
+# CHECK: Vreg: %19[ 39 ]
+# CHECK: Instr: %77:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %76, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 55 ]
+# CHECK: Vreg: %71[ 20 ]
+# CHECK: Vreg: %52[ 15 ]
+# CHECK: Vreg: %40[ 26 ]
+# CHECK: Vreg: %21[ 53 ]
+# CHECK: Vreg: %2[ 74 ]
+# CHECK: Vreg: %73[ 20 ]
+# CHECK: Vreg: %23[ 11 ]
+# CHECK: Vreg: %4[ 61 ]
+# CHECK: Vreg: %49[ 17 ]
+# CHECK: Vreg: %30[ 35 ]
+# CHECK: Vreg: %37[ 29 ]
+# CHECK: Vreg: %18[ 71 ]
+# CHECK: Vreg: %63[ 20 ]
+# CHECK: Vreg: %58[ 22 ]
+# CHECK: Vreg: %20[ 49 ]
+# CHECK: Vreg: %1[ 90 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %46[ 18 ]
+# CHECK: Vreg: %60[ 20 ]
+# CHECK: Vreg: %22:sub0[ 1 ]
+# CHECK: Vreg: %22:sub1[ 2 ]
+# CHECK: Vreg: %22[ 66 ]
+# CHECK: Vreg: %67[ 12 ]
+# CHECK: Vreg: %3[ 60 ]
+# CHECK: Vreg: %55[ 13 ]
+# CHECK: Vreg: %43[ 23 ]
+# CHECK: Vreg: %5[ 59 ]
+# CHECK: Vreg: %69[ 20 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Vreg: %19:sub0[ 25 ]
+# CHECK: Vreg: %19:sub1[ 26 ]
+# CHECK: Vreg: %19[ 38 ]
+# CHECK: Instr: %78:vgpr_32, %79:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %22.sub0, %77.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 54 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %52[ 14 ]
+# CHECK: Vreg: %40[ 25 ]
+# CHECK: Vreg: %21[ 52 ]
+# CHECK: Vreg: %2[ 73 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %23[ 10 ]
+# CHECK: Vreg: %4[ 60 ]
+# CHECK: Vreg: %49[ 16 ]
+# CHECK: Vreg: %30[ 34 ]
+# CHECK: Vreg: %37[ 28 ]
+# CHECK: Vreg: %18[ 70 ]
+# CHECK: Vreg: %63[ 19 ]
+# CHECK: Vreg: %77:sub0[ 0 ]
+# CHECK: Vreg: %77:sub1[ 1 ]
+# CHECK: Vreg: %58[ 21 ]
+# CHECK: Vreg: %20[ 48 ]
+# CHECK: Vreg: %1[ 89 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %46[ 17 ]
+# CHECK: Vreg: %60[ 19 ]
+# CHECK: Vreg: %22:sub0[ 0 ]
+# CHECK: Vreg: %22:sub1[ 1 ]
+# CHECK: Vreg: %22[ 65 ]
+# CHECK: Vreg: %67[ 11 ]
+# CHECK: Vreg: %3[ 59 ]
+# CHECK: Vreg: %55[ 12 ]
+# CHECK: Vreg: %43[ 22 ]
+# CHECK: Vreg: %5[ 58 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %19:sub0[ 24 ]
+# CHECK: Vreg: %19:sub1[ 25 ]
+# CHECK: Vreg: %19[ 37 ]
+# CHECK: Instr: %80:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %22.sub1, killed %77.sub1, killed %79, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 53 ]
+# CHECK: Vreg: %71[ 18 ]
+# CHECK: Vreg: %52[ 13 ]
+# CHECK: Vreg: %78[ 1 ]
+# CHECK: Vreg: %40[ 24 ]
+# CHECK: Vreg: %21[ 51 ]
+# CHECK: Vreg: %2[ 72 ]
+# CHECK: Vreg: %73[ 18 ]
+# CHECK: Vreg: %23[ 9 ]
+# CHECK: Vreg: %4[ 59 ]
+# CHECK: Vreg: %49[ 15 ]
+# CHECK: Vreg: %30[ 33 ]
+# CHECK: Vreg: %37[ 27 ]
+# CHECK: Vreg: %18[ 69 ]
+# CHECK: Vreg: %63[ 18 ]
+# CHECK: Vreg: %77:sub1[ 0 ]
+# CHECK: Vreg: %58[ 20 ]
+# CHECK: Vreg: %20[ 47 ]
+# CHECK: Vreg: %1[ 88 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %46[ 16 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %60[ 18 ]
+# CHECK: Vreg: %22:sub1[ 0 ]
+# CHECK: Vreg: %22:sub0[ 35 ]
+# CHECK: Vreg: %22[ 64 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %3[ 58 ]
+# CHECK: Vreg: %55[ 11 ]
+# CHECK: Vreg: %43[ 21 ]
+# CHECK: Vreg: %5[ 57 ]
+# CHECK: Vreg: %69[ 18 ]
+# CHECK: Vreg: %19:sub0[ 23 ]
+# CHECK: Vreg: %19:sub1[ 24 ]
+# CHECK: Vreg: %19[ 36 ]
+# CHECK: Instr: %81:vreg_64 = REG_SEQUENCE killed %78, %subreg.sub0, killed %80, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 52 ]
+# CHECK: Vreg: %71[ 17 ]
+# CHECK: Vreg: %52[ 12 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %21[ 50 ]
+# CHECK: Vreg: %2[ 71 ]
+# CHECK: Vreg: %73[ 17 ]
+# CHECK: Vreg: %80[ 0 ]
+# CHECK: Vreg: %23[ 8 ]
+# CHECK: Vreg: %4[ 58 ]
+# CHECK: Vreg: %49[ 14 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %18[ 68 ]
+# CHECK: Vreg: %63[ 17 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 46 ]
+# CHECK: Vreg: %1[ 87 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %46[ 15 ]
+# CHECK: Vreg: %60[ 17 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 63 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %3[ 57 ]
+# CHECK: Vreg: %55[ 10 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 56 ]
+# CHECK: Vreg: %69[ 17 ]
+# CHECK: Vreg: %19:sub0[ 22 ]
+# CHECK: Vreg: %19:sub1[ 23 ]
+# CHECK: Vreg: %19[ 35 ]
+# CHECK: Instr: %82:vgpr_32 = GLOBAL_LOAD_UBYTE %81, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 51 ]
+# CHECK: Vreg: %71[ 16 ]
+# CHECK: Vreg: %52[ 11 ]
+# CHECK: Vreg: %40[ 22 ]
+# CHECK: Vreg: %21[ 49 ]
+# CHECK: Vreg: %2[ 70 ]
+# CHECK: Vreg: %73[ 16 ]
+# CHECK: Vreg: %23[ 7 ]
+# CHECK: Vreg: %4[ 57 ]
+# CHECK: Vreg: %49[ 13 ]
+# CHECK: Vreg: %30[ 31 ]
+# CHECK: Vreg: %37[ 25 ]
+# CHECK: Vreg: %18[ 67 ]
+# CHECK: Vreg: %63[ 16 ]
+# CHECK: Vreg: %58[ 18 ]
+# CHECK: Vreg: %20[ 45 ]
+# CHECK: Vreg: %1[ 86 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %46[ 14 ]
+# CHECK: Vreg: %60[ 16 ]
+# CHECK: Vreg: %22:sub0[ 33 ]
+# CHECK: Vreg: %22:sub1[ 34 ]
+# CHECK: Vreg: %22[ 62 ]
+# CHECK: Vreg: %67[ 8 ]
+# CHECK: Vreg: %3[ 56 ]
+# CHECK: Vreg: %55[ 9 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Vreg: %43[ 19 ]
+# CHECK: Vreg: %5[ 55 ]
+# CHECK: Vreg: %69[ 16 ]
+# CHECK: Vreg: %19:sub0[ 21 ]
+# CHECK: Vreg: %19:sub1[ 22 ]
+# CHECK: Vreg: %19[ 34 ]
+# CHECK: Instr: %83:vgpr_32 = GLOBAL_LOAD_UBYTE %81, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 50 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %52[ 10 ]
+# CHECK: Vreg: %40[ 21 ]
+# CHECK: Vreg: %21[ 48 ]
+# CHECK: Vreg: %2[ 69 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %23[ 6 ]
+# CHECK: Vreg: %4[ 56 ]
+# CHECK: Vreg: %49[ 12 ]
+# CHECK: Vreg: %30[ 30 ]
+# CHECK: Vreg: %37[ 24 ]
+# CHECK: Vreg: %18[ 66 ]
+# CHECK: Vreg: %63[ 15 ]
+# CHECK: Vreg: %82[ 1 ]
+# CHECK: Vreg: %58[ 17 ]
+# CHECK: Vreg: %20[ 44 ]
+# CHECK: Vreg: %1[ 85 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %46[ 13 ]
+# CHECK: Vreg: %60[ 15 ]
+# CHECK: Vreg: %22:sub0[ 32 ]
+# CHECK: Vreg: %22:sub1[ 33 ]
+# CHECK: Vreg: %22[ 61 ]
+# CHECK: Vreg: %67[ 7 ]
+# CHECK: Vreg: %3[ 55 ]
+# CHECK: Vreg: %55[ 8 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Vreg: %43[ 18 ]
+# CHECK: Vreg: %5[ 54 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %19:sub0[ 20 ]
+# CHECK: Vreg: %19:sub1[ 21 ]
+# CHECK: Vreg: %19[ 33 ]
+# CHECK: Instr: %84:vgpr_32 = V_LSHL_OR_B32_e64 killed %83, 8, killed %82, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 49 ]
+# CHECK: Vreg: %83[ 0 ]
+# CHECK: Vreg: %71[ 14 ]
+# CHECK: Vreg: %52[ 9 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 47 ]
+# CHECK: Vreg: %2[ 68 ]
+# CHECK: Vreg: %73[ 14 ]
+# CHECK: Vreg: %23[ 5 ]
+# CHECK: Vreg: %4[ 55 ]
+# CHECK: Vreg: %49[ 11 ]
+# CHECK: Vreg: %30[ 29 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 65 ]
+# CHECK: Vreg: %63[ 14 ]
+# CHECK: Vreg: %82[ 0 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 43 ]
+# CHECK: Vreg: %1[ 84 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %46[ 12 ]
+# CHECK: Vreg: %60[ 14 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 60 ]
+# CHECK: Vreg: %67[ 6 ]
+# CHECK: Vreg: %3[ 54 ]
+# CHECK: Vreg: %55[ 7 ]
+# CHECK: Vreg: %81[ 1 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %5[ 53 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %19:sub0[ 19 ]
+# CHECK: Vreg: %19:sub1[ 20 ]
+# CHECK: Vreg: %19[ 32 ]
+# CHECK: Instr: %85:vgpr_32 = GLOBAL_LOAD_UBYTE %81, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 48 ]
+# CHECK: Vreg: %71[ 13 ]
+# CHECK: Vreg: %52[ 8 ]
+# CHECK: Vreg: %40[ 19 ]
+# CHECK: Vreg: %21[ 46 ]
+# CHECK: Vreg: %2[ 67 ]
+# CHECK: Vreg: %73[ 13 ]
+# CHECK: Vreg: %23[ 4 ]
+# CHECK: Vreg: %4[ 54 ]
+# CHECK: Vreg: %49[ 10 ]
+# CHECK: Vreg: %30[ 28 ]
+# CHECK: Vreg: %37[ 22 ]
+# CHECK: Vreg: %18[ 64 ]
+# CHECK: Vreg: %63[ 13 ]
+# CHECK: Vreg: %58[ 15 ]
+# CHECK: Vreg: %20[ 42 ]
+# CHECK: Vreg: %1[ 83 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %84[ 3 ]
+# CHECK: Vreg: %46[ 11 ]
+# CHECK: Vreg: %60[ 13 ]
+# CHECK: Vreg: %22:sub0[ 30 ]
+# CHECK: Vreg: %22:sub1[ 31 ]
+# CHECK: Vreg: %22[ 59 ]
+# CHECK: Vreg: %67[ 5 ]
+# CHECK: Vreg: %3[ 53 ]
+# CHECK: Vreg: %55[ 6 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Vreg: %43[ 16 ]
+# CHECK: Vreg: %5[ 52 ]
+# CHECK: Vreg: %69[ 13 ]
+# CHECK: Vreg: %19:sub0[ 18 ]
+# CHECK: Vreg: %19:sub1[ 19 ]
+# CHECK: Vreg: %19[ 31 ]
+# CHECK: Instr: %86:vgpr_32 = GLOBAL_LOAD_UBYTE killed %81, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %71[ 12 ]
+# CHECK: Vreg: %52[ 7 ]
+# CHECK: Vreg: %40[ 18 ]
+# CHECK: Vreg: %21[ 45 ]
+# CHECK: Vreg: %2[ 66 ]
+# CHECK: Vreg: %85[ 1 ]
+# CHECK: Vreg: %73[ 12 ]
+# CHECK: Vreg: %23[ 3 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %49[ 9 ]
+# CHECK: Vreg: %30[ 27 ]
+# CHECK: Vreg: %37[ 21 ]
+# CHECK: Vreg: %18[ 63 ]
+# CHECK: Vreg: %63[ 12 ]
+# CHECK: Vreg: %58[ 14 ]
+# CHECK: Vreg: %20[ 41 ]
+# CHECK: Vreg: %1[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %84[ 2 ]
+# CHECK: Vreg: %46[ 10 ]
+# CHECK: Vreg: %60[ 12 ]
+# CHECK: Vreg: %22:sub0[ 29 ]
+# CHECK: Vreg: %22:sub1[ 30 ]
+# CHECK: Vreg: %22[ 58 ]
+# CHECK: Vreg: %67[ 4 ]
+# CHECK: Vreg: %3[ 52 ]
+# CHECK: Vreg: %55[ 5 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Vreg: %43[ 15 ]
+# CHECK: Vreg: %5[ 51 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %19:sub0[ 17 ]
+# CHECK: Vreg: %19:sub1[ 18 ]
+# CHECK: Vreg: %19[ 30 ]
+# CHECK: Instr: %87:vgpr_32 = V_LSHL_OR_B32_e64 killed %86, 8, killed %85, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %71[ 11 ]
+# CHECK: Vreg: %52[ 6 ]
+# CHECK: Vreg: %40[ 17 ]
+# CHECK: Vreg: %21[ 44 ]
+# CHECK: Vreg: %2[ 65 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %73[ 11 ]
+# CHECK: Vreg: %23[ 2 ]
+# CHECK: Vreg: %4[ 52 ]
+# CHECK: Vreg: %49[ 8 ]
+# CHECK: Vreg: %30[ 26 ]
+# CHECK: Vreg: %37[ 20 ]
+# CHECK: Vreg: %18[ 62 ]
+# CHECK: Vreg: %63[ 11 ]
+# CHECK: Vreg: %58[ 13 ]
+# CHECK: Vreg: %20[ 40 ]
+# CHECK: Vreg: %1[ 81 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %84[ 1 ]
+# CHECK: Vreg: %46[ 9 ]
+# CHECK: Vreg: %60[ 11 ]
+# CHECK: Vreg: %22:sub0[ 28 ]
+# CHECK: Vreg: %22:sub1[ 29 ]
+# CHECK: Vreg: %22[ 57 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %3[ 51 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %55[ 4 ]
+# CHECK: Vreg: %43[ 14 ]
+# CHECK: Vreg: %5[ 50 ]
+# CHECK: Vreg: %69[ 11 ]
+# CHECK: Vreg: %19:sub0[ 16 ]
+# CHECK: Vreg: %19:sub1[ 17 ]
+# CHECK: Vreg: %19[ 29 ]
+# CHECK: Instr: %88:vgpr_32 = V_LSHL_OR_B32_e64 killed %87, 16, killed %84, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %52[ 5 ]
+# CHECK: Vreg: %40[ 16 ]
+# CHECK: Vreg: %21[ 43 ]
+# CHECK: Vreg: %2[ 64 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %4[ 51 ]
+# CHECK: Vreg: %49[ 7 ]
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Vreg: %30[ 25 ]
+# CHECK: Vreg: %37[ 19 ]
+# CHECK: Vreg: %18[ 61 ]
+# CHECK: Vreg: %63[ 10 ]
+# CHECK: Vreg: %58[ 12 ]
+# CHECK: Vreg: %20[ 39 ]
+# CHECK: Vreg: %1[ 80 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %46[ 8 ]
+# CHECK: Vreg: %60[ 10 ]
+# CHECK: Vreg: %22:sub0[ 27 ]
+# CHECK: Vreg: %22:sub1[ 28 ]
+# CHECK: Vreg: %22[ 56 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %3[ 50 ]
+# CHECK: Vreg: %55[ 3 ]
+# CHECK: Vreg: %43[ 13 ]
+# CHECK: Vreg: %5[ 49 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %19:sub0[ 15 ]
+# CHECK: Vreg: %19:sub1[ 16 ]
+# CHECK: Vreg: %19[ 28 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %23, %88, 0, 0, implicit $exec :: (store (s32) into %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 44 ]
+# CHECK: Vreg: %71[ 9 ]
+# CHECK: Vreg: %52[ 4 ]
+# CHECK: Vreg: %40[ 15 ]
+# CHECK: Vreg: %21[ 42 ]
+# CHECK: Vreg: %2[ 63 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %4[ 50 ]
+# CHECK: Vreg: %49[ 6 ]
+# CHECK: Vreg: %30[ 24 ]
+# CHECK: Vreg: %37[ 18 ]
+# CHECK: Vreg: %18[ 60 ]
+# CHECK: Vreg: %63[ 9 ]
+# CHECK: Vreg: %58[ 11 ]
+# CHECK: Vreg: %20[ 38 ]
+# CHECK: Vreg: %1[ 79 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %46[ 7 ]
+# CHECK: Vreg: %60[ 9 ]
+# CHECK: Vreg: %22:sub0[ 26 ]
+# CHECK: Vreg: %22:sub1[ 27 ]
+# CHECK: Vreg: %22[ 55 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %3[ 49 ]
+# CHECK: Vreg: %55[ 2 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %5[ 48 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %19:sub0[ 14 ]
+# CHECK: Vreg: %19:sub1[ 15 ]
+# CHECK: Vreg: %19[ 27 ]
+# CHECK: Instr: %89:sreg_32 = V_CMP_LT_U32_e64 %65, %67, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Vreg: %71[ 8 ]
+# CHECK: Vreg: %52[ 3 ]
+# CHECK: Vreg: %40[ 14 ]
+# CHECK: Vreg: %21[ 41 ]
+# CHECK: Vreg: %2[ 62 ]
+# CHECK: Vreg: %73[ 8 ]
+# CHECK: Vreg: %23[ 35 ]
+# CHECK: Vreg: %4[ 49 ]
+# CHECK: Vreg: %49[ 5 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %37[ 17 ]
+# CHECK: Vreg: %18[ 59 ]
+# CHECK: Vreg: %63[ 8 ]
+# CHECK: Vreg: %58[ 10 ]
+# CHECK: Vreg: %20[ 37 ]
+# CHECK: Vreg: %1[ 78 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %46[ 6 ]
+# CHECK: Vreg: %60[ 8 ]
+# CHECK: Vreg: %22:sub0[ 25 ]
+# CHECK: Vreg: %22:sub1[ 26 ]
+# CHECK: Vreg: %22[ 54 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 48 ]
+# CHECK: Vreg: %55[ 1 ]
+# CHECK: Vreg: %43[ 11 ]
+# CHECK: Vreg: %88[ 25 ]
+# CHECK: Vreg: %5[ 47 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %19:sub0[ 13 ]
+# CHECK: Vreg: %19:sub1[ 14 ]
+# CHECK: Vreg: %19[ 26 ]
+# CHECK: Instr: %90:sreg_32 = S_ANDN2_B32 killed %55, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 42 ]
+# CHECK: Vreg: %71[ 7 ]
+# CHECK: Vreg: %52[ 2 ]
+# CHECK: Vreg: %40[ 13 ]
+# CHECK: Vreg: %21[ 40 ]
+# CHECK: Vreg: %2[ 61 ]
+# CHECK: Vreg: %73[ 7 ]
+# CHECK: Vreg: %23[ 34 ]
+# CHECK: Vreg: %4[ 48 ]
+# CHECK: Vreg: %49[ 4 ]
+# CHECK: Vreg: %30[ 22 ]
+# CHECK: Vreg: %37[ 16 ]
+# CHECK: Vreg: %18[ 58 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %89[ 6 ]
+# CHECK: Vreg: %58[ 9 ]
+# CHECK: Vreg: %20[ 36 ]
+# CHECK: Vreg: %1[ 77 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %46[ 5 ]
+# CHECK: Vreg: %60[ 7 ]
+# CHECK: Vreg: %22:sub0[ 24 ]
+# CHECK: Vreg: %22:sub1[ 25 ]
+# CHECK: Vreg: %22[ 53 ]
+# CHECK: Vreg: %67[ 7 ]
+# CHECK: Vreg: %3[ 47 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %43[ 10 ]
+# CHECK: Vreg: %88[ 24 ]
+# CHECK: Vreg: %5[ 46 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %19:sub0[ 12 ]
+# CHECK: Vreg: %19:sub1[ 13 ]
+# CHECK: Vreg: %19[ 25 ]
+# CHECK: Instr: %91:sreg_32 = COPY %90
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %71[ 6 ]
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %40[ 12 ]
+# CHECK: Vreg: %21[ 39 ]
+# CHECK: Vreg: %2[ 60 ]
+# CHECK: Vreg: %73[ 6 ]
+# CHECK: Vreg: %23[ 33 ]
+# CHECK: Vreg: %4[ 47 ]
+# CHECK: Vreg: %49[ 3 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %37[ 15 ]
+# CHECK: Vreg: %18[ 57 ]
+# CHECK: Vreg: %63[ 6 ]
+# CHECK: Vreg: %89[ 5 ]
+# CHECK: Vreg: %58[ 8 ]
+# CHECK: Vreg: %20[ 35 ]
+# CHECK: Vreg: %1[ 76 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %46[ 4 ]
+# CHECK: Vreg: %60[ 6 ]
+# CHECK: Vreg: %22:sub0[ 23 ]
+# CHECK: Vreg: %22:sub1[ 24 ]
+# CHECK: Vreg: %22[ 52 ]
+# CHECK: Vreg: %67[ 6 ]
+# CHECK: Vreg: %3[ 46 ]
+# CHECK: Vreg: %43[ 9 ]
+# CHECK: Vreg: %88[ 23 ]
+# CHECK: Vreg: %5[ 45 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %19:sub0[ 11 ]
+# CHECK: Vreg: %19:sub1[ 12 ]
+# CHECK: Vreg: %19[ 24 ]
+# CHECK: Instr: %92:sreg_32 = S_ANDN2_B32 killed %52, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %90[ 45 ]
+# CHECK: Vreg: %71[ 5 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %40[ 11 ]
+# CHECK: Vreg: %21[ 38 ]
+# CHECK: Vreg: %2[ 59 ]
+# CHECK: Vreg: %73[ 5 ]
+# CHECK: Vreg: %23[ 32 ]
+# CHECK: Vreg: %4[ 46 ]
+# CHECK: Vreg: %49[ 2 ]
+# CHECK: Vreg: %30[ 20 ]
+# CHECK: Vreg: %37[ 14 ]
+# CHECK: Vreg: %18[ 56 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %89[ 4 ]
+# CHECK: Vreg: %58[ 7 ]
+# CHECK: Vreg: %20[ 34 ]
+# CHECK: Vreg: %1[ 75 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %91[ 5 ]
+# CHECK: Vreg: %46[ 3 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %22:sub0[ 22 ]
+# CHECK: Vreg: %22:sub1[ 23 ]
+# CHECK: Vreg: %22[ 51 ]
+# CHECK: Vreg: %67[ 5 ]
+# CHECK: Vreg: %3[ 45 ]
+# CHECK: Vreg: %43[ 8 ]
+# CHECK: Vreg: %88[ 22 ]
+# CHECK: Vreg: %5[ 44 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %19:sub0[ 10 ]
+# CHECK: Vreg: %19:sub1[ 11 ]
+# CHECK: Vreg: %19[ 23 ]
+# CHECK: Instr: %93:sreg_32 = COPY %92
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 39 ]
+# CHECK: Vreg: %90[ 44 ]
+# CHECK: Vreg: %71[ 4 ]
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %21[ 37 ]
+# CHECK: Vreg: %2[ 58 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %73[ 4 ]
+# CHECK: Vreg: %23[ 31 ]
+# CHECK: Vreg: %4[ 45 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %30[ 19 ]
+# CHECK: Vreg: %37[ 13 ]
+# CHECK: Vreg: %18[ 55 ]
+# CHECK: Vreg: %63[ 4 ]
+# CHECK: Vreg: %89[ 3 ]
+# CHECK: Vreg: %58[ 6 ]
+# CHECK: Vreg: %20[ 33 ]
+# CHECK: Vreg: %1[ 74 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %91[ 4 ]
+# CHECK: Vreg: %46[ 2 ]
+# CHECK: Vreg: %60[ 4 ]
+# CHECK: Vreg: %22:sub0[ 21 ]
+# CHECK: Vreg: %22:sub1[ 22 ]
+# CHECK: Vreg: %22[ 50 ]
+# CHECK: Vreg: %67[ 4 ]
+# CHECK: Vreg: %3[ 44 ]
+# CHECK: Vreg: %43[ 7 ]
+# CHECK: Vreg: %88[ 21 ]
+# CHECK: Vreg: %5[ 43 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %19:sub0[ 9 ]
+# CHECK: Vreg: %19:sub1[ 10 ]
+# CHECK: Vreg: %19[ 22 ]
+# CHECK: Instr: %94:sreg_32 = S_OR_B32 killed %49, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 38 ]
+# CHECK: Vreg: %90[ 43 ]
+# CHECK: Vreg: %71[ 3 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 36 ]
+# CHECK: Vreg: %2[ 57 ]
+# CHECK: Vreg: %92[ 46 ]
+# CHECK: Vreg: %73[ 3 ]
+# CHECK: Vreg: %23[ 30 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %37[ 12 ]
+# CHECK: Vreg: %18[ 54 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %89[ 2 ]
+# CHECK: Vreg: %58[ 5 ]
+# CHECK: Vreg: %20[ 32 ]
+# CHECK: Vreg: %1[ 73 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %91[ 3 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %22:sub0[ 20 ]
+# CHECK: Vreg: %22:sub1[ 21 ]
+# CHECK: Vreg: %22[ 49 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %3[ 43 ]
+# CHECK: Vreg: %93[ 3 ]
+# CHECK: Vreg: %43[ 6 ]
+# CHECK: Vreg: %88[ 20 ]
+# CHECK: Vreg: %5[ 42 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %19:sub0[ 8 ]
+# CHECK: Vreg: %19:sub1[ 9 ]
+# CHECK: Vreg: %19[ 21 ]
+# CHECK: Instr: %95:sreg_32 = S_OR_B32 killed %46, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %90[ 42 ]
+# CHECK: Vreg: %71[ 2 ]
+# CHECK: Vreg: %40[ 8 ]
+# CHECK: Vreg: %21[ 35 ]
+# CHECK: Vreg: %2[ 56 ]
+# CHECK: Vreg: %92[ 45 ]
+# CHECK: Vreg: %73[ 2 ]
+# CHECK: Vreg: %23[ 29 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %94[ 2 ]
+# CHECK: Vreg: %30[ 17 ]
+# CHECK: Vreg: %37[ 11 ]
+# CHECK: Vreg: %18[ 53 ]
+# CHECK: Vreg: %63[ 2 ]
+# CHECK: Vreg: %89[ 1 ]
+# CHECK: Vreg: %58[ 4 ]
+# CHECK: Vreg: %20[ 31 ]
+# CHECK: Vreg: %1[ 72 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %91[ 2 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %60[ 2 ]
+# CHECK: Vreg: %22:sub0[ 19 ]
+# CHECK: Vreg: %22:sub1[ 20 ]
+# CHECK: Vreg: %22[ 48 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %93[ 2 ]
+# CHECK: Vreg: %43[ 5 ]
+# CHECK: Vreg: %88[ 19 ]
+# CHECK: Vreg: %5[ 41 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %19:sub0[ 7 ]
+# CHECK: Vreg: %19:sub1[ 8 ]
+# CHECK: Vreg: %19[ 20 ]
+# CHECK: Instr: %96:sreg_32 = SI_IF killed %89, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %90[ 41 ]
+# CHECK: Vreg: %71[ 1 ]
+# CHECK: Vreg: %40[ 7 ]
+# CHECK: Vreg: %21[ 34 ]
+# CHECK: Vreg: %2[ 55 ]
+# CHECK: Vreg: %92[ 44 ]
+# CHECK: Vreg: %73[ 1 ]
+# CHECK: Vreg: %23[ 28 ]
+# CHECK: Vreg: %4[ 42 ]
+# CHECK: Vreg: %94[ 1 ]
+# CHECK: Vreg: %30[ 16 ]
+# CHECK: Vreg: %37[ 10 ]
+# CHECK: Vreg: %18[ 52 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %58[ 3 ]
+# CHECK: Vreg: %20[ 30 ]
+# CHECK: Vreg: %1[ 71 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %91[ 1 ]
+# CHECK: Vreg: %60[ 1 ]
+# CHECK: Vreg: %22:sub0[ 18 ]
+# CHECK: Vreg: %22:sub1[ 19 ]
+# CHECK: Vreg: %22[ 47 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %3[ 41 ]
+# CHECK: Vreg: %93[ 1 ]
+# CHECK: Vreg: %43[ 4 ]
+# CHECK: Vreg: %88[ 18 ]
+# CHECK: Vreg: %5[ 40 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %95[ 1 ]
+# CHECK: Vreg: %19:sub0[ 6 ]
+# CHECK: Vreg: %19:sub1[ 7 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %90[ 40 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 33 ]
+# CHECK: Vreg: %2[ 54 ]
+# CHECK: Vreg: %92[ 43 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 51 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 29 ]
+# CHECK: Vreg: %1[ 70 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 46 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 40 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %88[ 17 ]
+# CHECK: Vreg: %5[ 39 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %19:sub0[ 5 ]
+# CHECK: Vreg: %19:sub1[ 6 ]
+# CHECK: Vreg: %19[ 18 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %90[ 40 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 33 ]
+# CHECK: Vreg: %2[ 54 ]
+# CHECK: Vreg: %92[ 43 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 51 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 29 ]
+# CHECK: Vreg: %1[ 70 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 46 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 40 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %88[ 17 ]
+# CHECK: Vreg: %5[ 39 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %19:sub0[ 5 ]
+# CHECK: Vreg: %19:sub1[ 6 ]
+# CHECK: Vreg: %19[ 18 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %97:vgpr_32 = V_ASHRREV_I32_e64 31, %67, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %90[ 39 ]
+# CHECK: Vreg: %71[ 37 ]
+# CHECK: Vreg: %21[ 32 ]
+# CHECK: Vreg: %2[ 53 ]
+# CHECK: Vreg: %40[ 57 ]
+# CHECK: Vreg: %92[ 42 ]
+# CHECK: Vreg: %73[ 37 ]
+# CHECK: Vreg: %23[ 78 ]
+# CHECK: Vreg: %4[ 40 ]
+# CHECK: Vreg: %94[ 45 ]
+# CHECK: Vreg: %30[ 14 ]
+# CHECK: Vreg: %37[ 60 ]
+# CHECK: Vreg: %18[ 50 ]
+# CHECK: Vreg: %63[ 30 ]
+# CHECK: Vreg: %96[ 52 ]
+# CHECK: Vreg: %58[ 53 ]
+# CHECK: Vreg: %20[ 28 ]
+# CHECK: Vreg: %1[ 69 ]
+# CHECK: Vreg: %65[ 37 ]
+# CHECK: Vreg: %60[ 30 ]
+# CHECK: Vreg: %22[ 45 ]
+# CHECK: Vreg: %22:sub0[ 68 ]
+# CHECK: Vreg: %22:sub1[ 69 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 39 ]
+# CHECK: Vreg: %43[ 54 ]
+# CHECK: Vreg: %88[ 16 ]
+# CHECK: Vreg: %5[ 38 ]
+# CHECK: Vreg: %69[ 37 ]
+# CHECK: Vreg: %95[ 48 ]
+# CHECK: Vreg: %19:sub0[ 4 ]
+# CHECK: Vreg: %19:sub1[ 5 ]
+# CHECK: Vreg: %19[ 17 ]
+# CHECK: Instr: %98:vreg_64 = REG_SEQUENCE %67, %subreg.sub0, killed %97, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %90[ 38 ]
+# CHECK: Vreg: %71[ 36 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %21[ 31 ]
+# CHECK: Vreg: %2[ 52 ]
+# CHECK: Vreg: %40[ 56 ]
+# CHECK: Vreg: %92[ 41 ]
+# CHECK: Vreg: %73[ 36 ]
+# CHECK: Vreg: %23[ 77 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ 44 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %37[ 59 ]
+# CHECK: Vreg: %18[ 49 ]
+# CHECK: Vreg: %63[ 29 ]
+# CHECK: Vreg: %96[ 51 ]
+# CHECK: Vreg: %58[ 52 ]
+# CHECK: Vreg: %20[ 27 ]
+# CHECK: Vreg: %1[ 68 ]
+# CHECK: Vreg: %65[ 36 ]
+# CHECK: Vreg: %60[ 29 ]
+# CHECK: Vreg: %22[ 44 ]
+# CHECK: Vreg: %22:sub0[ 67 ]
+# CHECK: Vreg: %22:sub1[ 68 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 38 ]
+# CHECK: Vreg: %43[ 53 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %69[ 36 ]
+# CHECK: Vreg: %95[ 47 ]
+# CHECK: Vreg: %19:sub0[ 3 ]
+# CHECK: Vreg: %19:sub1[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Instr: %99:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %90[ 37 ]
+# CHECK: Vreg: %71[ 35 ]
+# CHECK: Vreg: %21[ 30 ]
+# CHECK: Vreg: %2[ 51 ]
+# CHECK: Vreg: %40[ 55 ]
+# CHECK: Vreg: %92[ 40 ]
+# CHECK: Vreg: %73[ 35 ]
+# CHECK: Vreg: %23[ 76 ]
+# CHECK: Vreg: %4[ 38 ]
+# CHECK: Vreg: %94[ 43 ]
+# CHECK: Vreg: %30[ 12 ]
+# CHECK: Vreg: %37[ 58 ]
+# CHECK: Vreg: %18[ 48 ]
+# CHECK: Vreg: %63[ 28 ]
+# CHECK: Vreg: %96[ 50 ]
+# CHECK: Vreg: %58[ 51 ]
+# CHECK: Vreg: %20[ 26 ]
+# CHECK: Vreg: %1[ 67 ]
+# CHECK: Vreg: %65[ 35 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %60[ 28 ]
+# CHECK: Vreg: %22[ 43 ]
+# CHECK: Vreg: %22:sub0[ 66 ]
+# CHECK: Vreg: %22:sub1[ 67 ]
+# CHECK: Vreg: %67[ 7 ]
+# CHECK: Vreg: %3[ 37 ]
+# CHECK: Vreg: %43[ 52 ]
+# CHECK: Vreg: %88[ 14 ]
+# CHECK: Vreg: %5[ 36 ]
+# CHECK: Vreg: %69[ 35 ]
+# CHECK: Vreg: %95[ 46 ]
+# CHECK: Vreg: %19:sub0[ 2 ]
+# CHECK: Vreg: %19:sub1[ 3 ]
+# CHECK: Vreg: %19[ 15 ]
+# CHECK: Instr: %100:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %98, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %90[ 36 ]
+# CHECK: Vreg: %71[ 34 ]
+# CHECK: Vreg: %21[ 29 ]
+# CHECK: Vreg: %2[ 50 ]
+# CHECK: Vreg: %40[ 54 ]
+# CHECK: Vreg: %92[ 39 ]
+# CHECK: Vreg: %73[ 34 ]
+# CHECK: Vreg: %99[ 6 ]
+# CHECK: Vreg: %23[ 75 ]
+# CHECK: Vreg: %4[ 37 ]
+# CHECK: Vreg: %94[ 42 ]
+# CHECK: Vreg: %30[ 11 ]
+# CHECK: Vreg: %37[ 57 ]
+# CHECK: Vreg: %18[ 47 ]
+# CHECK: Vreg: %63[ 27 ]
+# CHECK: Vreg: %96[ 49 ]
+# CHECK: Vreg: %58[ 50 ]
+# CHECK: Vreg: %20[ 25 ]
+# CHECK: Vreg: %1[ 66 ]
+# CHECK: Vreg: %65[ 34 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %60[ 27 ]
+# CHECK: Vreg: %22[ 42 ]
+# CHECK: Vreg: %22:sub0[ 65 ]
+# CHECK: Vreg: %22:sub1[ 66 ]
+# CHECK: Vreg: %67[ 6 ]
+# CHECK: Vreg: %3[ 36 ]
+# CHECK: Vreg: %43[ 51 ]
+# CHECK: Vreg: %88[ 13 ]
+# CHECK: Vreg: %5[ 35 ]
+# CHECK: Vreg: %69[ 34 ]
+# CHECK: Vreg: %95[ 45 ]
+# CHECK: Vreg: %19:sub0[ 1 ]
+# CHECK: Vreg: %19:sub1[ 2 ]
+# CHECK: Vreg: %19[ 14 ]
+# CHECK: Instr: %101:vgpr_32, %102:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %19.sub0, %100.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %90[ 35 ]
+# CHECK: Vreg: %71[ 33 ]
+# CHECK: Vreg: %21[ 28 ]
+# CHECK: Vreg: %2[ 49 ]
+# CHECK: Vreg: %40[ 53 ]
+# CHECK: Vreg: %92[ 38 ]
+# CHECK: Vreg: %73[ 33 ]
+# CHECK: Vreg: %99[ 5 ]
+# CHECK: Vreg: %23[ 74 ]
+# CHECK: Vreg: %4[ 36 ]
+# CHECK: Vreg: %94[ 41 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %37[ 56 ]
+# CHECK: Vreg: %18[ 46 ]
+# CHECK: Vreg: %63[ 26 ]
+# CHECK: Vreg: %96[ 48 ]
+# CHECK: Vreg: %58[ 49 ]
+# CHECK: Vreg: %20[ 24 ]
+# CHECK: Vreg: %1[ 65 ]
+# CHECK: Vreg: %65[ 33 ]
+# CHECK: Vreg: %60[ 26 ]
+# CHECK: Vreg: %22[ 41 ]
+# CHECK: Vreg: %22:sub0[ 64 ]
+# CHECK: Vreg: %22:sub1[ 65 ]
+# CHECK: Vreg: %67[ 5 ]
+# CHECK: Vreg: %3[ 35 ]
+# CHECK: Vreg: %100:sub0[ 0 ]
+# CHECK: Vreg: %100:sub1[ 1 ]
+# CHECK: Vreg: %43[ 50 ]
+# CHECK: Vreg: %88[ 12 ]
+# CHECK: Vreg: %5[ 34 ]
+# CHECK: Vreg: %69[ 33 ]
+# CHECK: Vreg: %95[ 44 ]
+# CHECK: Vreg: %19:sub0[ 0 ]
+# CHECK: Vreg: %19:sub1[ 1 ]
+# CHECK: Vreg: %19[ 13 ]
+# CHECK: Instr: %103:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %19.sub1, killed %100.sub1, killed %102, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %90[ 34 ]
+# CHECK: Vreg: %71[ 32 ]
+# CHECK: Vreg: %21[ 27 ]
+# CHECK: Vreg: %2[ 48 ]
+# CHECK: Vreg: %40[ 52 ]
+# CHECK: Vreg: %92[ 37 ]
+# CHECK: Vreg: %73[ 32 ]
+# CHECK: Vreg: %99[ 4 ]
+# CHECK: Vreg: %23[ 73 ]
+# CHECK: Vreg: %4[ 35 ]
+# CHECK: Vreg: %94[ 40 ]
+# CHECK: Vreg: %30[ 9 ]
+# CHECK: Vreg: %37[ 55 ]
+# CHECK: Vreg: %18[ 45 ]
+# CHECK: Vreg: %63[ 25 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %96[ 47 ]
+# CHECK: Vreg: %58[ 48 ]
+# CHECK: Vreg: %20[ 23 ]
+# CHECK: Vreg: %1[ 64 ]
+# CHECK: Vreg: %65[ 32 ]
+# CHECK: Vreg: %60[ 25 ]
+# CHECK: Vreg: %22[ 40 ]
+# CHECK: Vreg: %22:sub0[ 63 ]
+# CHECK: Vreg: %22:sub1[ 64 ]
+# CHECK: Vreg: %67[ 4 ]
+# CHECK: Vreg: %3[ 34 ]
+# CHECK: Vreg: %100:sub1[ 0 ]
+# CHECK: Vreg: %43[ 49 ]
+# CHECK: Vreg: %88[ 11 ]
+# CHECK: Vreg: %5[ 33 ]
+# CHECK: Vreg: %69[ 32 ]
+# CHECK: Vreg: %95[ 43 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Vreg: %19:sub1[ 0 ]
+# CHECK: Vreg: %19[ 12 ]
+# CHECK: Vreg: %19:sub0[ 87 ]
+# CHECK: Instr: %104:vreg_64 = REG_SEQUENCE killed %101, %subreg.sub0, killed %103, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %90[ 33 ]
+# CHECK: Vreg: %71[ 31 ]
+# CHECK: Vreg: %21[ 26 ]
+# CHECK: Vreg: %2[ 47 ]
+# CHECK: Vreg: %40[ 51 ]
+# CHECK: Vreg: %92[ 36 ]
+# CHECK: Vreg: %73[ 31 ]
+# CHECK: Vreg: %99[ 3 ]
+# CHECK: Vreg: %23[ 72 ]
+# CHECK: Vreg: %4[ 34 ]
+# CHECK: Vreg: %94[ 39 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %37[ 54 ]
+# CHECK: Vreg: %18[ 44 ]
+# CHECK: Vreg: %63[ 24 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %96[ 46 ]
+# CHECK: Vreg: %58[ 47 ]
+# CHECK: Vreg: %103[ 0 ]
+# CHECK: Vreg: %20[ 22 ]
+# CHECK: Vreg: %1[ 63 ]
+# CHECK: Vreg: %65[ 31 ]
+# CHECK: Vreg: %60[ 24 ]
+# CHECK: Vreg: %22[ 39 ]
+# CHECK: Vreg: %22:sub0[ 62 ]
+# CHECK: Vreg: %22:sub1[ 63 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %3[ 33 ]
+# CHECK: Vreg: %43[ 48 ]
+# CHECK: Vreg: %88[ 10 ]
+# CHECK: Vreg: %5[ 32 ]
+# CHECK: Vreg: %69[ 31 ]
+# CHECK: Vreg: %95[ 42 ]
+# CHECK: Vreg: %19[ 11 ]
+# CHECK: Vreg: %19:sub0[ 86 ]
+# CHECK: Vreg: %19:sub1[ 87 ]
+# CHECK: Instr: %105:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %90[ 32 ]
+# CHECK: Vreg: %71[ 30 ]
+# CHECK: Vreg: %104[ 8 ]
+# CHECK: Vreg: %21[ 25 ]
+# CHECK: Vreg: %2[ 46 ]
+# CHECK: Vreg: %40[ 50 ]
+# CHECK: Vreg: %92[ 35 ]
+# CHECK: Vreg: %73[ 30 ]
+# CHECK: Vreg: %99[ 2 ]
+# CHECK: Vreg: %23[ 71 ]
+# CHECK: Vreg: %4[ 33 ]
+# CHECK: Vreg: %94[ 38 ]
+# CHECK: Vreg: %30[ 7 ]
+# CHECK: Vreg: %37[ 53 ]
+# CHECK: Vreg: %18[ 43 ]
+# CHECK: Vreg: %63[ 23 ]
+# CHECK: Vreg: %96[ 45 ]
+# CHECK: Vreg: %58[ 46 ]
+# CHECK: Vreg: %20[ 21 ]
+# CHECK: Vreg: %1[ 62 ]
+# CHECK: Vreg: %65[ 30 ]
+# CHECK: Vreg: %60[ 23 ]
+# CHECK: Vreg: %22[ 38 ]
+# CHECK: Vreg: %22:sub0[ 61 ]
+# CHECK: Vreg: %22:sub1[ 62 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %3[ 32 ]
+# CHECK: Vreg: %43[ 47 ]
+# CHECK: Vreg: %88[ 9 ]
+# CHECK: Vreg: %5[ 31 ]
+# CHECK: Vreg: %69[ 30 ]
+# CHECK: Vreg: %95[ 41 ]
+# CHECK: Vreg: %19[ 10 ]
+# CHECK: Vreg: %19:sub0[ 85 ]
+# CHECK: Vreg: %19:sub1[ 86 ]
+# CHECK: Instr: %106:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %90[ 31 ]
+# CHECK: Vreg: %71[ 29 ]
+# CHECK: Vreg: %104[ 7 ]
+# CHECK: Vreg: %21[ 24 ]
+# CHECK: Vreg: %2[ 45 ]
+# CHECK: Vreg: %40[ 49 ]
+# CHECK: Vreg: %92[ 34 ]
+# CHECK: Vreg: %73[ 29 ]
+# CHECK: Vreg: %99[ 1 ]
+# CHECK: Vreg: %23[ 70 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %94[ 37 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %37[ 52 ]
+# CHECK: Vreg: %18[ 42 ]
+# CHECK: Vreg: %63[ 22 ]
+# CHECK: Vreg: %96[ 44 ]
+# CHECK: Vreg: %58[ 45 ]
+# CHECK: Vreg: %20[ 20 ]
+# CHECK: Vreg: %1[ 61 ]
+# CHECK: Vreg: %65[ 29 ]
+# CHECK: Vreg: %60[ 22 ]
+# CHECK: Vreg: %105[ 1 ]
+# CHECK: Vreg: %22[ 37 ]
+# CHECK: Vreg: %22:sub0[ 60 ]
+# CHECK: Vreg: %22:sub1[ 61 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %3[ 31 ]
+# CHECK: Vreg: %43[ 46 ]
+# CHECK: Vreg: %88[ 8 ]
+# CHECK: Vreg: %5[ 30 ]
+# CHECK: Vreg: %69[ 29 ]
+# CHECK: Vreg: %95[ 40 ]
+# CHECK: Vreg: %19[ 9 ]
+# CHECK: Vreg: %19:sub0[ 84 ]
+# CHECK: Vreg: %19:sub1[ 85 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %90[ 30 ]
+# CHECK: Vreg: %71[ 28 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %21[ 23 ]
+# CHECK: Vreg: %2[ 44 ]
+# CHECK: Vreg: %40[ 48 ]
+# CHECK: Vreg: %92[ 33 ]
+# CHECK: Vreg: %73[ 28 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %23[ 69 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %94[ 36 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %37[ 51 ]
+# CHECK: Vreg: %18[ 41 ]
+# CHECK: Vreg: %63[ 21 ]
+# CHECK: Vreg: %96[ 43 ]
+# CHECK: Vreg: %58[ 44 ]
+# CHECK: Vreg: %20[ 19 ]
+# CHECK: Vreg: %1[ 60 ]
+# CHECK: Vreg: %65[ 28 ]
+# CHECK: Vreg: %60[ 21 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %22[ 36 ]
+# CHECK: Vreg: %22:sub0[ 59 ]
+# CHECK: Vreg: %22:sub1[ 60 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 30 ]
+# CHECK: Vreg: %43[ 45 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ 28 ]
+# CHECK: Vreg: %95[ 39 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ 83 ]
+# CHECK: Vreg: %19:sub1[ 84 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %90[ 30 ]
+# CHECK: Vreg: %71[ 28 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %21[ 23 ]
+# CHECK: Vreg: %2[ 44 ]
+# CHECK: Vreg: %40[ 48 ]
+# CHECK: Vreg: %92[ 33 ]
+# CHECK: Vreg: %73[ 28 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %23[ 69 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %94[ 36 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %37[ 51 ]
+# CHECK: Vreg: %18[ 41 ]
+# CHECK: Vreg: %63[ 21 ]
+# CHECK: Vreg: %96[ 43 ]
+# CHECK: Vreg: %58[ 44 ]
+# CHECK: Vreg: %20[ 19 ]
+# CHECK: Vreg: %1[ 60 ]
+# CHECK: Vreg: %65[ 28 ]
+# CHECK: Vreg: %60[ 21 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %22[ 36 ]
+# CHECK: Vreg: %22:sub0[ 59 ]
+# CHECK: Vreg: %22:sub1[ 60 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 30 ]
+# CHECK: Vreg: %43[ 45 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ 28 ]
+# CHECK: Vreg: %95[ 39 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ 83 ]
+# CHECK: Vreg: %19:sub1[ 84 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %48:sreg_32 = PHI %95, %bb.1, %107, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %51:sreg_32 = PHI %94, %bb.1, %108, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %54:sreg_32 = PHI %93, %bb.1, %109, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %57:sreg_32 = PHI %91, %bb.1, %110, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %62:vgpr_32 = PHI %60, %bb.1, %111, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %64:vgpr_32 = PHI %63, %bb.1, %112, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %74:vgpr_32 = PHI undef %113:vgpr_32, %bb.1, %114, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %72:vgpr_32 = PHI undef %113:vgpr_32, %bb.1, %115, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %70:vgpr_32 = PHI undef %113:vgpr_32, %bb.1, %116, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %72[ 13 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %68:vgpr_32 = PHI undef %113:vgpr_32, %bb.1, %117, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %70[ 13 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %72[ 13 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %66:vgpr_32 = PHI undef %113:vgpr_32, %bb.1, %118, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %68[ 13 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %70[ 13 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %72[ 13 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %119:vgpr_32 = PHI undef %120:vgpr_32, %bb.1, %121, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %66[ 13 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %68[ 13 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %70[ 13 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %72[ 13 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %122:vgpr_32 = PHI %65, %bb.1, %123, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %66[ 13 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %68[ 13 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %70[ 13 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %72[ 13 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %119[ LoopTag+22 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %124:vgpr_32 = PHI %67, %bb.1, %125, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %66[ 13 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %68[ 13 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %70[ 13 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %122[ LoopTag+28 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %72[ 13 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %119[ LoopTag+22 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %126:vgpr_32 = PHI %69, %bb.1, %127, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %66[ 13 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %68[ 13 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %70[ 13 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %122[ LoopTag+28 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %72[ 13 ]
+# CHECK: Vreg: %124[ LoopTag+31 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %119[ LoopTag+22 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %128:vgpr_32 = PHI %71, %bb.1, %129, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %66[ 13 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %68[ 13 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %70[ 13 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %122[ LoopTag+28 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %72[ 13 ]
+# CHECK: Vreg: %124[ LoopTag+31 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %119[ LoopTag+22 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %126[ LoopTag+30 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %130:vgpr_32 = PHI %73, %bb.1, %131, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+28 ]
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %66[ 13 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %68[ 13 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %70[ 13 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %122[ LoopTag+28 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %72[ 13 ]
+# CHECK: Vreg: %124[ LoopTag+31 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %119[ LoopTag+22 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %126[ LoopTag+30 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: %132:vgpr_32 = PHI undef %120:vgpr_32, %bb.1, %133, %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+28 ]
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %64[ 13 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %130[ LoopTag+31 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %66[ 13 ]
+# CHECK: Vreg: %54[ 7 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %68[ 13 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %70[ 13 ]
+# CHECK: Vreg: %51[ 10 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %122[ LoopTag+28 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %72[ 13 ]
+# CHECK: Vreg: %124[ LoopTag+31 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 13 ]
+# CHECK: Vreg: %119[ LoopTag+22 ]
+# CHECK: Vreg: %126[ LoopTag+30 ]
+# CHECK: Vreg: %62[ 13 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Instr: SI_END_CF killed %96, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+27 ]
+# CHECK: Vreg: %0[ 70 ]
+# CHECK: Vreg: %64[ 12 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %21[ 68 ]
+# CHECK: Vreg: %130[ LoopTag+30 ]
+# CHECK: Vreg: %2[ 89 ]
+# CHECK: Vreg: %66[ 12 ]
+# CHECK: Vreg: %54[ 6 ]
+# CHECK: Vreg: %23[ 26 ]
+# CHECK: Vreg: %132[ LoopTag+29 ]
+# CHECK: Vreg: %4[ 76 ]
+# CHECK: Vreg: %30[ 50 ]
+# CHECK: Vreg: %68[ 12 ]
+# CHECK: Vreg: %37[ 8 ]
+# CHECK: Vreg: %18[ 86 ]
+# CHECK: Vreg: %70[ 12 ]
+# CHECK: Vreg: %51[ 9 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %122[ LoopTag+27 ]
+# CHECK: Vreg: %58[ 1 ]
+# CHECK: Vreg: %20[ 64 ]
+# CHECK: Vreg: %1[ 105 ]
+# CHECK: Vreg: %72[ 12 ]
+# CHECK: Vreg: %124[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ 16 ]
+# CHECK: Vreg: %22:sub1[ 17 ]
+# CHECK: Vreg: %22[ 81 ]
+# CHECK: Vreg: %3[ 75 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %74[ 12 ]
+# CHECK: Vreg: %119[ LoopTag+21 ]
+# CHECK: Vreg: %126[ LoopTag+29 ]
+# CHECK: Vreg: %62[ 12 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %5[ 74 ]
+# CHECK: Vreg: %57[ 3 ]
+# CHECK: Vreg: %19:sub0[ 40 ]
+# CHECK: Vreg: %19:sub1[ 41 ]
+# CHECK: Vreg: %19[ 53 ]
+# CHECK: Instr: %59:sreg_32 = SI_IF_BREAK %48, killed %58, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+26 ]
+# CHECK: Vreg: %0[ 69 ]
+# CHECK: Vreg: %64[ 11 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %21[ 67 ]
+# CHECK: Vreg: %130[ LoopTag+29 ]
+# CHECK: Vreg: %2[ 88 ]
+# CHECK: Vreg: %66[ 11 ]
+# CHECK: Vreg: %54[ 5 ]
+# CHECK: Vreg: %23[ 25 ]
+# CHECK: Vreg: %132[ LoopTag+28 ]
+# CHECK: Vreg: %4[ 75 ]
+# CHECK: Vreg: %30[ 49 ]
+# CHECK: Vreg: %68[ 11 ]
+# CHECK: Vreg: %37[ 7 ]
+# CHECK: Vreg: %18[ 85 ]
+# CHECK: Vreg: %70[ 11 ]
+# CHECK: Vreg: %51[ 8 ]
+# CHECK: Vreg: %122[ LoopTag+26 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20[ 63 ]
+# CHECK: Vreg: %1[ 104 ]
+# CHECK: Vreg: %72[ 11 ]
+# CHECK: Vreg: %124[ LoopTag+29 ]
+# CHECK: Vreg: %22:sub0[ 15 ]
+# CHECK: Vreg: %22:sub1[ 16 ]
+# CHECK: Vreg: %22[ 80 ]
+# CHECK: Vreg: %3[ 74 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %74[ 11 ]
+# CHECK: Vreg: %119[ LoopTag+20 ]
+# CHECK: Vreg: %126[ LoopTag+28 ]
+# CHECK: Vreg: %62[ 11 ]
+# CHECK: Vreg: %43[ 1 ]
+# CHECK: Vreg: %5[ 73 ]
+# CHECK: Vreg: %57[ 2 ]
+# CHECK: Vreg: %19:sub0[ 39 ]
+# CHECK: Vreg: %19:sub1[ 40 ]
+# CHECK: Vreg: %19[ 52 ]
+# CHECK: Instr: %134:sreg_32 = S_ANDN2_B32 killed %43, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+25 ]
+# CHECK: Vreg: %0[ 68 ]
+# CHECK: Vreg: %64[ 10 ]
+# CHECK: Vreg: %59[ 9 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %21[ 66 ]
+# CHECK: Vreg: %130[ LoopTag+28 ]
+# CHECK: Vreg: %2[ 87 ]
+# CHECK: Vreg: %66[ 10 ]
+# CHECK: Vreg: %54[ 4 ]
+# CHECK: Vreg: %23[ 24 ]
+# CHECK: Vreg: %132[ LoopTag+27 ]
+# CHECK: Vreg: %4[ 74 ]
+# CHECK: Vreg: %30[ 48 ]
+# CHECK: Vreg: %68[ 10 ]
+# CHECK: Vreg: %37[ 6 ]
+# CHECK: Vreg: %18[ 84 ]
+# CHECK: Vreg: %70[ 10 ]
+# CHECK: Vreg: %51[ 7 ]
+# CHECK: Vreg: %122[ LoopTag+25 ]
+# CHECK: Vreg: %20[ 62 ]
+# CHECK: Vreg: %1[ 103 ]
+# CHECK: Vreg: %72[ 10 ]
+# CHECK: Vreg: %124[ LoopTag+28 ]
+# CHECK: Vreg: %22:sub0[ 14 ]
+# CHECK: Vreg: %22:sub1[ 15 ]
+# CHECK: Vreg: %22[ 79 ]
+# CHECK: Vreg: %3[ 73 ]
+# CHECK: Vreg: %48[ 10 ]
+# CHECK: Vreg: %74[ 10 ]
+# CHECK: Vreg: %119[ LoopTag+19 ]
+# CHECK: Vreg: %126[ LoopTag+27 ]
+# CHECK: Vreg: %62[ 10 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %5[ 72 ]
+# CHECK: Vreg: %57[ 1 ]
+# CHECK: Vreg: %19:sub0[ 38 ]
+# CHECK: Vreg: %19:sub1[ 39 ]
+# CHECK: Vreg: %19[ 51 ]
+# CHECK: Instr: %135:sreg_32 = S_AND_B32 %57, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+24 ]
+# CHECK: Vreg: %0[ 67 ]
+# CHECK: Vreg: %64[ 9 ]
+# CHECK: Vreg: %59[ 8 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 65 ]
+# CHECK: Vreg: %130[ LoopTag+27 ]
+# CHECK: Vreg: %2[ 86 ]
+# CHECK: Vreg: %66[ 9 ]
+# CHECK: Vreg: %54[ 3 ]
+# CHECK: Vreg: %23[ 23 ]
+# CHECK: Vreg: %132[ LoopTag+26 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %30[ 47 ]
+# CHECK: Vreg: %68[ 9 ]
+# CHECK: Vreg: %37[ 5 ]
+# CHECK: Vreg: %18[ 83 ]
+# CHECK: Vreg: %70[ 9 ]
+# CHECK: Vreg: %51[ 6 ]
+# CHECK: Vreg: %134[ 1 ]
+# CHECK: Vreg: %122[ LoopTag+24 ]
+# CHECK: Vreg: %20[ 61 ]
+# CHECK: Vreg: %1[ 102 ]
+# CHECK: Vreg: %72[ 9 ]
+# CHECK: Vreg: %124[ LoopTag+27 ]
+# CHECK: Vreg: %22:sub0[ 13 ]
+# CHECK: Vreg: %22:sub1[ 14 ]
+# CHECK: Vreg: %22[ 78 ]
+# CHECK: Vreg: %3[ 72 ]
+# CHECK: Vreg: %48[ 9 ]
+# CHECK: Vreg: %74[ 9 ]
+# CHECK: Vreg: %119[ LoopTag+18 ]
+# CHECK: Vreg: %126[ LoopTag+26 ]
+# CHECK: Vreg: %62[ 9 ]
+# CHECK: Vreg: %5[ 71 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 37 ]
+# CHECK: Vreg: %19:sub1[ 38 ]
+# CHECK: Vreg: %19[ 50 ]
+# CHECK: Instr: %45:sreg_32 = S_OR_B32 killed %134, killed %135, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+23 ]
+# CHECK: Vreg: %0[ 66 ]
+# CHECK: Vreg: %135[ 0 ]
+# CHECK: Vreg: %64[ 8 ]
+# CHECK: Vreg: %59[ 7 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 64 ]
+# CHECK: Vreg: %130[ LoopTag+26 ]
+# CHECK: Vreg: %2[ 85 ]
+# CHECK: Vreg: %66[ 8 ]
+# CHECK: Vreg: %54[ 2 ]
+# CHECK: Vreg: %23[ 22 ]
+# CHECK: Vreg: %132[ LoopTag+25 ]
+# CHECK: Vreg: %4[ 72 ]
+# CHECK: Vreg: %30[ 46 ]
+# CHECK: Vreg: %68[ 8 ]
+# CHECK: Vreg: %37[ 4 ]
+# CHECK: Vreg: %18[ 82 ]
+# CHECK: Vreg: %70[ 8 ]
+# CHECK: Vreg: %51[ 5 ]
+# CHECK: Vreg: %134[ 0 ]
+# CHECK: Vreg: %122[ LoopTag+23 ]
+# CHECK: Vreg: %20[ 60 ]
+# CHECK: Vreg: %1[ 101 ]
+# CHECK: Vreg: %72[ 8 ]
+# CHECK: Vreg: %124[ LoopTag+26 ]
+# CHECK: Vreg: %22:sub0[ 12 ]
+# CHECK: Vreg: %22:sub1[ 13 ]
+# CHECK: Vreg: %22[ 77 ]
+# CHECK: Vreg: %3[ 71 ]
+# CHECK: Vreg: %48[ 8 ]
+# CHECK: Vreg: %74[ 8 ]
+# CHECK: Vreg: %119[ LoopTag+17 ]
+# CHECK: Vreg: %126[ LoopTag+25 ]
+# CHECK: Vreg: %62[ 8 ]
+# CHECK: Vreg: %5[ 70 ]
+# CHECK: Vreg: %57[ 8 ]
+# CHECK: Vreg: %19:sub0[ 36 ]
+# CHECK: Vreg: %19:sub1[ 37 ]
+# CHECK: Vreg: %19[ 49 ]
+# CHECK: Instr: %136:sreg_32 = S_ANDN2_B32 killed %40, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+22 ]
+# CHECK: Vreg: %45[ 7 ]
+# CHECK: Vreg: %0[ 65 ]
+# CHECK: Vreg: %64[ 7 ]
+# CHECK: Vreg: %59[ 6 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 63 ]
+# CHECK: Vreg: %130[ LoopTag+25 ]
+# CHECK: Vreg: %2[ 84 ]
+# CHECK: Vreg: %66[ 7 ]
+# CHECK: Vreg: %54[ 1 ]
+# CHECK: Vreg: %23[ 21 ]
+# CHECK: Vreg: %132[ LoopTag+24 ]
+# CHECK: Vreg: %4[ 71 ]
+# CHECK: Vreg: %30[ 45 ]
+# CHECK: Vreg: %68[ 7 ]
+# CHECK: Vreg: %37[ 3 ]
+# CHECK: Vreg: %18[ 81 ]
+# CHECK: Vreg: %70[ 7 ]
+# CHECK: Vreg: %51[ 4 ]
+# CHECK: Vreg: %122[ LoopTag+22 ]
+# CHECK: Vreg: %20[ 59 ]
+# CHECK: Vreg: %1[ 100 ]
+# CHECK: Vreg: %72[ 7 ]
+# CHECK: Vreg: %124[ LoopTag+25 ]
+# CHECK: Vreg: %22:sub0[ 11 ]
+# CHECK: Vreg: %22:sub1[ 12 ]
+# CHECK: Vreg: %22[ 76 ]
+# CHECK: Vreg: %3[ 70 ]
+# CHECK: Vreg: %48[ 7 ]
+# CHECK: Vreg: %74[ 7 ]
+# CHECK: Vreg: %119[ LoopTag+16 ]
+# CHECK: Vreg: %126[ LoopTag+24 ]
+# CHECK: Vreg: %62[ 7 ]
+# CHECK: Vreg: %5[ 69 ]
+# CHECK: Vreg: %57[ 7 ]
+# CHECK: Vreg: %19:sub0[ 35 ]
+# CHECK: Vreg: %19:sub1[ 36 ]
+# CHECK: Vreg: %19[ 48 ]
+# CHECK: Instr: %137:sreg_32 = S_AND_B32 %54, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+21 ]
+# CHECK: Vreg: %45[ 6 ]
+# CHECK: Vreg: %0[ 64 ]
+# CHECK: Vreg: %64[ 6 ]
+# CHECK: Vreg: %59[ 5 ]
+# CHECK: Vreg: %21[ 62 ]
+# CHECK: Vreg: %130[ LoopTag+24 ]
+# CHECK: Vreg: %2[ 83 ]
+# CHECK: Vreg: %66[ 6 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %23[ 20 ]
+# CHECK: Vreg: %132[ LoopTag+23 ]
+# CHECK: Vreg: %4[ 70 ]
+# CHECK: Vreg: %30[ 44 ]
+# CHECK: Vreg: %68[ 6 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %18[ 80 ]
+# CHECK: Vreg: %70[ 6 ]
+# CHECK: Vreg: %51[ 3 ]
+# CHECK: Vreg: %122[ LoopTag+21 ]
+# CHECK: Vreg: %20[ 58 ]
+# CHECK: Vreg: %1[ 99 ]
+# CHECK: Vreg: %72[ 6 ]
+# CHECK: Vreg: %136[ 1 ]
+# CHECK: Vreg: %124[ LoopTag+24 ]
+# CHECK: Vreg: %22:sub0[ 10 ]
+# CHECK: Vreg: %22:sub1[ 11 ]
+# CHECK: Vreg: %22[ 75 ]
+# CHECK: Vreg: %3[ 69 ]
+# CHECK: Vreg: %48[ 6 ]
+# CHECK: Vreg: %74[ 6 ]
+# CHECK: Vreg: %119[ LoopTag+15 ]
+# CHECK: Vreg: %126[ LoopTag+23 ]
+# CHECK: Vreg: %62[ 6 ]
+# CHECK: Vreg: %5[ 68 ]
+# CHECK: Vreg: %57[ 6 ]
+# CHECK: Vreg: %19:sub0[ 34 ]
+# CHECK: Vreg: %19:sub1[ 35 ]
+# CHECK: Vreg: %19[ 47 ]
+# CHECK: Instr: %42:sreg_32 = S_OR_B32 killed %136, killed %137, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+20 ]
+# CHECK: Vreg: %45[ 5 ]
+# CHECK: Vreg: %0[ 63 ]
+# CHECK: Vreg: %64[ 5 ]
+# CHECK: Vreg: %59[ 4 ]
+# CHECK: Vreg: %21[ 61 ]
+# CHECK: Vreg: %130[ LoopTag+23 ]
+# CHECK: Vreg: %2[ 82 ]
+# CHECK: Vreg: %66[ 5 ]
+# CHECK: Vreg: %54[ 5 ]
+# CHECK: Vreg: %137[ 0 ]
+# CHECK: Vreg: %23[ 19 ]
+# CHECK: Vreg: %132[ LoopTag+22 ]
+# CHECK: Vreg: %4[ 69 ]
+# CHECK: Vreg: %30[ 43 ]
+# CHECK: Vreg: %68[ 5 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %18[ 79 ]
+# CHECK: Vreg: %70[ 5 ]
+# CHECK: Vreg: %51[ 2 ]
+# CHECK: Vreg: %122[ LoopTag+20 ]
+# CHECK: Vreg: %20[ 57 ]
+# CHECK: Vreg: %1[ 98 ]
+# CHECK: Vreg: %72[ 5 ]
+# CHECK: Vreg: %136[ 0 ]
+# CHECK: Vreg: %124[ LoopTag+23 ]
+# CHECK: Vreg: %22:sub0[ 9 ]
+# CHECK: Vreg: %22:sub1[ 10 ]
+# CHECK: Vreg: %22[ 74 ]
+# CHECK: Vreg: %3[ 68 ]
+# CHECK: Vreg: %48[ 5 ]
+# CHECK: Vreg: %74[ 5 ]
+# CHECK: Vreg: %119[ LoopTag+14 ]
+# CHECK: Vreg: %126[ LoopTag+22 ]
+# CHECK: Vreg: %62[ 5 ]
+# CHECK: Vreg: %5[ 67 ]
+# CHECK: Vreg: %57[ 5 ]
+# CHECK: Vreg: %19:sub0[ 33 ]
+# CHECK: Vreg: %19:sub1[ 34 ]
+# CHECK: Vreg: %19[ 46 ]
+# CHECK: Instr: %138:sreg_32 = S_ANDN2_B32 killed %37, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+19 ]
+# CHECK: Vreg: %45[ 4 ]
+# CHECK: Vreg: %0[ 62 ]
+# CHECK: Vreg: %64[ 4 ]
+# CHECK: Vreg: %59[ 3 ]
+# CHECK: Vreg: %21[ 60 ]
+# CHECK: Vreg: %130[ LoopTag+22 ]
+# CHECK: Vreg: %2[ 81 ]
+# CHECK: Vreg: %66[ 4 ]
+# CHECK: Vreg: %54[ 4 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %23[ 18 ]
+# CHECK: Vreg: %132[ LoopTag+21 ]
+# CHECK: Vreg: %4[ 68 ]
+# CHECK: Vreg: %30[ 42 ]
+# CHECK: Vreg: %68[ 4 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %18[ 78 ]
+# CHECK: Vreg: %70[ 4 ]
+# CHECK: Vreg: %51[ 1 ]
+# CHECK: Vreg: %122[ LoopTag+19 ]
+# CHECK: Vreg: %20[ 56 ]
+# CHECK: Vreg: %1[ 97 ]
+# CHECK: Vreg: %72[ 4 ]
+# CHECK: Vreg: %124[ LoopTag+22 ]
+# CHECK: Vreg: %22:sub0[ 8 ]
+# CHECK: Vreg: %22:sub1[ 9 ]
+# CHECK: Vreg: %22[ 73 ]
+# CHECK: Vreg: %3[ 67 ]
+# CHECK: Vreg: %48[ 4 ]
+# CHECK: Vreg: %74[ 4 ]
+# CHECK: Vreg: %119[ LoopTag+13 ]
+# CHECK: Vreg: %126[ LoopTag+21 ]
+# CHECK: Vreg: %62[ 4 ]
+# CHECK: Vreg: %5[ 66 ]
+# CHECK: Vreg: %57[ 4 ]
+# CHECK: Vreg: %19:sub0[ 32 ]
+# CHECK: Vreg: %19:sub1[ 33 ]
+# CHECK: Vreg: %19[ 45 ]
+# CHECK: Instr: %139:sreg_32 = S_AND_B32 %51, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+18 ]
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %0[ 61 ]
+# CHECK: Vreg: %64[ 3 ]
+# CHECK: Vreg: %59[ 2 ]
+# CHECK: Vreg: %21[ 59 ]
+# CHECK: Vreg: %130[ LoopTag+21 ]
+# CHECK: Vreg: %2[ 80 ]
+# CHECK: Vreg: %66[ 3 ]
+# CHECK: Vreg: %54[ 3 ]
+# CHECK: Vreg: %42[ 3 ]
+# CHECK: Vreg: %23[ 17 ]
+# CHECK: Vreg: %132[ LoopTag+20 ]
+# CHECK: Vreg: %4[ 67 ]
+# CHECK: Vreg: %30[ 41 ]
+# CHECK: Vreg: %68[ 3 ]
+# CHECK: Vreg: %18[ 77 ]
+# CHECK: Vreg: %70[ 3 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %122[ LoopTag+18 ]
+# CHECK: Vreg: %20[ 55 ]
+# CHECK: Vreg: %1[ 96 ]
+# CHECK: Vreg: %72[ 3 ]
+# CHECK: Vreg: %124[ LoopTag+21 ]
+# CHECK: Vreg: %22:sub0[ 7 ]
+# CHECK: Vreg: %22:sub1[ 8 ]
+# CHECK: Vreg: %22[ 72 ]
+# CHECK: Vreg: %3[ 66 ]
+# CHECK: Vreg: %48[ 3 ]
+# CHECK: Vreg: %74[ 3 ]
+# CHECK: Vreg: %119[ LoopTag+12 ]
+# CHECK: Vreg: %138[ 1 ]
+# CHECK: Vreg: %126[ LoopTag+20 ]
+# CHECK: Vreg: %62[ 3 ]
+# CHECK: Vreg: %5[ 65 ]
+# CHECK: Vreg: %57[ 3 ]
+# CHECK: Vreg: %19:sub0[ 31 ]
+# CHECK: Vreg: %19:sub1[ 32 ]
+# CHECK: Vreg: %19[ 44 ]
+# CHECK: Instr: %39:sreg_32 = S_OR_B32 killed %138, killed %139, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+17 ]
+# CHECK: Vreg: %45[ 2 ]
+# CHECK: Vreg: %0[ 60 ]
+# CHECK: Vreg: %64[ 2 ]
+# CHECK: Vreg: %59[ 1 ]
+# CHECK: Vreg: %21[ 58 ]
+# CHECK: Vreg: %130[ LoopTag+20 ]
+# CHECK: Vreg: %2[ 79 ]
+# CHECK: Vreg: %66[ 2 ]
+# CHECK: Vreg: %54[ 2 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %23[ 16 ]
+# CHECK: Vreg: %132[ LoopTag+19 ]
+# CHECK: Vreg: %4[ 66 ]
+# CHECK: Vreg: %30[ 40 ]
+# CHECK: Vreg: %68[ 2 ]
+# CHECK: Vreg: %139[ 0 ]
+# CHECK: Vreg: %18[ 76 ]
+# CHECK: Vreg: %70[ 2 ]
+# CHECK: Vreg: %51[ 2 ]
+# CHECK: Vreg: %122[ LoopTag+17 ]
+# CHECK: Vreg: %20[ 54 ]
+# CHECK: Vreg: %1[ 95 ]
+# CHECK: Vreg: %72[ 2 ]
+# CHECK: Vreg: %124[ LoopTag+20 ]
+# CHECK: Vreg: %22:sub0[ 6 ]
+# CHECK: Vreg: %22:sub1[ 7 ]
+# CHECK: Vreg: %22[ 71 ]
+# CHECK: Vreg: %3[ 65 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %74[ 2 ]
+# CHECK: Vreg: %119[ LoopTag+11 ]
+# CHECK: Vreg: %138[ 0 ]
+# CHECK: Vreg: %126[ LoopTag+19 ]
+# CHECK: Vreg: %62[ 2 ]
+# CHECK: Vreg: %5[ 64 ]
+# CHECK: Vreg: %57[ 2 ]
+# CHECK: Vreg: %19:sub0[ 30 ]
+# CHECK: Vreg: %19:sub1[ 31 ]
+# CHECK: Vreg: %19[ 43 ]
+# CHECK: Instr: SI_LOOP %59, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+16 ]
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %0[ 59 ]
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %21[ 57 ]
+# CHECK: Vreg: %130[ LoopTag+19 ]
+# CHECK: Vreg: %2[ 78 ]
+# CHECK: Vreg: %66[ 1 ]
+# CHECK: Vreg: %54[ 1 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %23[ 15 ]
+# CHECK: Vreg: %132[ LoopTag+18 ]
+# CHECK: Vreg: %4[ 65 ]
+# CHECK: Vreg: %30[ 39 ]
+# CHECK: Vreg: %68[ 1 ]
+# CHECK: Vreg: %18[ 75 ]
+# CHECK: Vreg: %70[ 1 ]
+# CHECK: Vreg: %51[ 1 ]
+# CHECK: Vreg: %122[ LoopTag+16 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %20[ 53 ]
+# CHECK: Vreg: %1[ 94 ]
+# CHECK: Vreg: %72[ 1 ]
+# CHECK: Vreg: %124[ LoopTag+19 ]
+# CHECK: Vreg: %22:sub0[ 5 ]
+# CHECK: Vreg: %22:sub1[ 6 ]
+# CHECK: Vreg: %22[ 70 ]
+# CHECK: Vreg: %3[ 64 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %74[ 1 ]
+# CHECK: Vreg: %119[ LoopTag+10 ]
+# CHECK: Vreg: %126[ LoopTag+18 ]
+# CHECK: Vreg: %62[ 1 ]
+# CHECK: Vreg: %5[ 63 ]
+# CHECK: Vreg: %57[ 1 ]
+# CHECK: Vreg: %19:sub0[ 29 ]
+# CHECK: Vreg: %19:sub1[ 30 ]
+# CHECK: Vreg: %19[ 42 ]
+# CHECK: Instr: S_BRANCH %bb.34
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ LoopTag+15 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %130[ LoopTag+18 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %132[ LoopTag+17 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %122[ LoopTag+15 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %124[ LoopTag+18 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %119[ LoopTag+9 ]
+# CHECK: Vreg: %126[ LoopTag+17 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %128[ LoopTag+15 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %130[ LoopTag+18 ]
+# CHECK: Vreg: %2[ 77 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %132[ LoopTag+17 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %18[ 74 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %122[ LoopTag+15 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 52 ]
+# CHECK: Vreg: %1[ 93 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %124[ LoopTag+18 ]
+# CHECK: Vreg: %22:sub0[ 4 ]
+# CHECK: Vreg: %22:sub1[ 5 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ 63 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %119[ LoopTag+9 ]
+# CHECK: Vreg: %126[ LoopTag+17 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %5[ 62 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %19:sub0[ 28 ]
+# CHECK: Vreg: %19:sub1[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %140:sreg_32 = PHI undef %141:sreg_32, %bb.2, %142, %bb.37
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %90[ LoopTag+30 ]
+# CHECK: Vreg: %71[ LoopTag+28 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+83 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+84 ]
+# CHECK: Vreg: %142[ 0 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %21[ LoopTag+23 ]
+# CHECK: Vreg: %40[ LoopTag+48 ]
+# CHECK: Vreg: %92[ LoopTag+33 ]
+# CHECK: Vreg: %73[ LoopTag+28 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+44 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+69 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %94[ LoopTag+36 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %18[ LoopTag+41 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %37[ LoopTag+51 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+43 ]
+# CHECK: Vreg: %58[ LoopTag+44 ]
+# CHECK: Vreg: %20[ LoopTag+19 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %148[ 0 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %22[ LoopTag+36 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %150[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ LoopTag+28 ]
+# CHECK: Vreg: %95[ LoopTag+39 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Instr: %143:sreg_32 = PHI %106, %bb.2, %144, %bb.37
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %90[ LoopTag+30 ]
+# CHECK: Vreg: %71[ LoopTag+28 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+83 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+84 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %21[ LoopTag+23 ]
+# CHECK: Vreg: %40[ LoopTag+48 ]
+# CHECK: Vreg: %92[ LoopTag+33 ]
+# CHECK: Vreg: %73[ LoopTag+28 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+44 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+69 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %94[ LoopTag+36 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %18[ LoopTag+41 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %37[ LoopTag+51 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+43 ]
+# CHECK: Vreg: %58[ LoopTag+44 ]
+# CHECK: Vreg: %20[ LoopTag+19 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %148[ 0 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %22[ LoopTag+36 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %150[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ LoopTag+28 ]
+# CHECK: Vreg: %95[ LoopTag+39 ]
+# CHECK: Vreg: %140[ 10 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Instr: %145:vgpr_32 = PHI %99, %bb.2, %146, %bb.37
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %90[ LoopTag+30 ]
+# CHECK: Vreg: %71[ LoopTag+28 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+83 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+84 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %21[ LoopTag+23 ]
+# CHECK: Vreg: %40[ LoopTag+48 ]
+# CHECK: Vreg: %92[ LoopTag+33 ]
+# CHECK: Vreg: %73[ LoopTag+28 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+44 ]
+# CHECK: Vreg: %23[ LoopTag+69 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %94[ LoopTag+36 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %18[ LoopTag+41 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %37[ LoopTag+51 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+43 ]
+# CHECK: Vreg: %58[ LoopTag+44 ]
+# CHECK: Vreg: %20[ LoopTag+19 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %148[ 0 ]
+# CHECK: Vreg: %143[ 9 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %22[ LoopTag+36 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %150[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ LoopTag+28 ]
+# CHECK: Vreg: %95[ LoopTag+39 ]
+# CHECK: Vreg: %140[ 10 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Instr: %147:vgpr_32 = PHI %105, %bb.2, %148, %bb.37
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %90[ LoopTag+30 ]
+# CHECK: Vreg: %71[ LoopTag+28 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+83 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+84 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %21[ LoopTag+23 ]
+# CHECK: Vreg: %40[ LoopTag+48 ]
+# CHECK: Vreg: %92[ LoopTag+33 ]
+# CHECK: Vreg: %73[ LoopTag+28 ]
+# CHECK: Vreg: %2[ LoopTag+44 ]
+# CHECK: Vreg: %23[ LoopTag+69 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %94[ LoopTag+36 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %18[ LoopTag+41 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %37[ LoopTag+51 ]
+# CHECK: Vreg: %96[ LoopTag+43 ]
+# CHECK: Vreg: %58[ LoopTag+44 ]
+# CHECK: Vreg: %20[ LoopTag+19 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %148[ 0 ]
+# CHECK: Vreg: %143[ 9 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %105[ 0 ]
+# CHECK: Vreg: %22[ LoopTag+36 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %150[ 0 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ LoopTag+28 ]
+# CHECK: Vreg: %95[ LoopTag+39 ]
+# CHECK: Vreg: %140[ 10 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Instr: %149:vgpr_32 = PHI %67, %bb.2, %150, %bb.37
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %90[ LoopTag+30 ]
+# CHECK: Vreg: %71[ LoopTag+28 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+83 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+84 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %21[ LoopTag+23 ]
+# CHECK: Vreg: %40[ LoopTag+48 ]
+# CHECK: Vreg: %92[ LoopTag+33 ]
+# CHECK: Vreg: %73[ LoopTag+28 ]
+# CHECK: Vreg: %2[ LoopTag+44 ]
+# CHECK: Vreg: %23[ LoopTag+69 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %94[ LoopTag+36 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %18[ LoopTag+41 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %37[ LoopTag+51 ]
+# CHECK: Vreg: %96[ LoopTag+43 ]
+# CHECK: Vreg: %58[ LoopTag+44 ]
+# CHECK: Vreg: %20[ LoopTag+19 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %143[ 9 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %22[ LoopTag+36 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %150[ 0 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ LoopTag+28 ]
+# CHECK: Vreg: %95[ LoopTag+39 ]
+# CHECK: Vreg: %140[ 10 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Vreg: %147[ 5 ]
+# CHECK: Instr: %151:vgpr_32 = PHI %67, %bb.2, %152, %bb.37
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %90[ LoopTag+30 ]
+# CHECK: Vreg: %71[ LoopTag+28 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+83 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+84 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %21[ LoopTag+23 ]
+# CHECK: Vreg: %149[ 13 ]
+# CHECK: Vreg: %40[ LoopTag+48 ]
+# CHECK: Vreg: %92[ LoopTag+33 ]
+# CHECK: Vreg: %73[ LoopTag+28 ]
+# CHECK: Vreg: %2[ LoopTag+44 ]
+# CHECK: Vreg: %23[ LoopTag+69 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %94[ LoopTag+36 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %18[ LoopTag+41 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %37[ LoopTag+51 ]
+# CHECK: Vreg: %96[ LoopTag+43 ]
+# CHECK: Vreg: %58[ LoopTag+44 ]
+# CHECK: Vreg: %20[ LoopTag+19 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %143[ 9 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %22[ LoopTag+36 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ LoopTag+28 ]
+# CHECK: Vreg: %95[ LoopTag+39 ]
+# CHECK: Vreg: %140[ 10 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Vreg: %147[ 5 ]
+# CHECK: Instr: %153:sreg_32 = V_CMP_GE_U32_e64 %145, %67, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Vreg: %104[ 5 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 12 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 30 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %151[ 12 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %147[ 4 ]
+# CHECK: Instr: %154:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+23 ]
+# CHECK: Vreg: %90[ LoopTag+28 ]
+# CHECK: Vreg: %71[ LoopTag+26 ]
+# CHECK: Vreg: %19[ 6 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+81 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+82 ]
+# CHECK: Vreg: %104[ 4 ]
+# CHECK: Vreg: %21[ LoopTag+21 ]
+# CHECK: Vreg: %149[ 11 ]
+# CHECK: Vreg: %40[ LoopTag+46 ]
+# CHECK: Vreg: %92[ LoopTag+31 ]
+# CHECK: Vreg: %73[ LoopTag+26 ]
+# CHECK: Vreg: %2[ LoopTag+42 ]
+# CHECK: Vreg: %23[ LoopTag+67 ]
+# CHECK: Vreg: %4[ 29 ]
+# CHECK: Vreg: %94[ LoopTag+34 ]
+# CHECK: Vreg: %30[ 3 ]
+# CHECK: Vreg: %151[ 11 ]
+# CHECK: Vreg: %18[ LoopTag+39 ]
+# CHECK: Vreg: %63[ LoopTag+19 ]
+# CHECK: Vreg: %37[ LoopTag+49 ]
+# CHECK: Vreg: %153[ 1 ]
+# CHECK: Vreg: %96[ LoopTag+41 ]
+# CHECK: Vreg: %58[ LoopTag+42 ]
+# CHECK: Vreg: %20[ LoopTag+17 ]
+# CHECK: Vreg: %1[ LoopTag+58 ]
+# CHECK: Vreg: %65[ LoopTag+26 ]
+# CHECK: Vreg: %143[ 7 ]
+# CHECK: Vreg: %60[ LoopTag+19 ]
+# CHECK: Vreg: %22[ LoopTag+34 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %67[ LoopTag+26 ]
+# CHECK: Vreg: %3[ LoopTag+28 ]
+# CHECK: Vreg: %145[ 9 ]
+# CHECK: Vreg: %43[ LoopTag+43 ]
+# CHECK: Vreg: %88[ 5 ]
+# CHECK: Vreg: %5[ 27 ]
+# CHECK: Vreg: %69[ LoopTag+26 ]
+# CHECK: Vreg: %95[ LoopTag+37 ]
+# CHECK: Vreg: %140[ 8 ]
+# CHECK: Vreg: %147[ 3 ]
+# CHECK: Instr: %155:sreg_32 = SI_IF killed %153, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+22 ]
+# CHECK: Vreg: %90[ LoopTag+27 ]
+# CHECK: Vreg: %71[ LoopTag+25 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+80 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+81 ]
+# CHECK: Vreg: %104[ 3 ]
+# CHECK: Vreg: %21[ LoopTag+20 ]
+# CHECK: Vreg: %149[ 10 ]
+# CHECK: Vreg: %40[ LoopTag+45 ]
+# CHECK: Vreg: %92[ LoopTag+30 ]
+# CHECK: Vreg: %73[ LoopTag+25 ]
+# CHECK: Vreg: %2[ LoopTag+41 ]
+# CHECK: Vreg: %154[ 1 ]
+# CHECK: Vreg: %23[ LoopTag+66 ]
+# CHECK: Vreg: %4[ 28 ]
+# CHECK: Vreg: %94[ LoopTag+33 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %151[ 10 ]
+# CHECK: Vreg: %18[ LoopTag+38 ]
+# CHECK: Vreg: %63[ LoopTag+18 ]
+# CHECK: Vreg: %37[ LoopTag+48 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+40 ]
+# CHECK: Vreg: %58[ LoopTag+41 ]
+# CHECK: Vreg: %20[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+57 ]
+# CHECK: Vreg: %65[ LoopTag+25 ]
+# CHECK: Vreg: %143[ 6 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %22[ LoopTag+33 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+56 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+57 ]
+# CHECK: Vreg: %67[ LoopTag+25 ]
+# CHECK: Vreg: %3[ LoopTag+27 ]
+# CHECK: Vreg: %145[ 8 ]
+# CHECK: Vreg: %43[ LoopTag+42 ]
+# CHECK: Vreg: %88[ 4 ]
+# CHECK: Vreg: %5[ 26 ]
+# CHECK: Vreg: %69[ LoopTag+25 ]
+# CHECK: Vreg: %95[ LoopTag+36 ]
+# CHECK: Vreg: %140[ 7 ]
+# CHECK: Vreg: %147[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %104[ 2 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 9 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %154[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %4[ 27 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %151[ 9 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 7 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %104[ 2 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 9 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %154[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %4[ 27 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %151[ 9 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 7 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %156:sreg_32 = PHI %157, %bb.7, %158, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %165[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %160[ 0 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %158[ 0 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Instr: %159:sreg_32 = PHI %157, %bb.7, %160, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %156[ 2 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %165[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %160[ 0 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Instr: %161:vgpr_32 = PHI undef %162:vgpr_32, %bb.7, %163, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %156[ 2 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %165[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %159[ 3 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Instr: %164:vgpr_32 = PHI undef %162:vgpr_32, %bb.7, %165, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %161[ 3 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %156[ 2 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %165[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %159[ 3 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Instr: %166:vgpr_32 = PHI undef %162:vgpr_32, %bb.7, %167, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %161[ 3 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %156[ 2 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %164[ 3 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %159[ 3 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Instr: %168:vgpr_32 = PHI undef %162:vgpr_32, %bb.7, %147, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %166[ 3 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %161[ 3 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %156[ 2 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %164[ 3 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %159[ 3 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Instr: %169:vgpr_32 = PHI undef %170:vgpr_32, %bb.7, %167, %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %166[ 3 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %147[ 3 ]
+# CHECK: Vreg: %161[ 3 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %168[ 3 ]
+# CHECK: Vreg: %156[ 2 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %164[ 3 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %159[ 3 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Instr: SI_END_CF killed %171, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+23 ]
+# CHECK: Vreg: %166[ 2 ]
+# CHECK: Vreg: %90[ LoopTag+28 ]
+# CHECK: Vreg: %71[ LoopTag+26 ]
+# CHECK: Vreg: %147[ 2 ]
+# CHECK: Vreg: %161[ 2 ]
+# CHECK: Vreg: %104[ 18 ]
+# CHECK: Vreg: %21[ LoopTag+21 ]
+# CHECK: Vreg: %149[ 2 ]
+# CHECK: Vreg: %40[ LoopTag+46 ]
+# CHECK: Vreg: %92[ LoopTag+31 ]
+# CHECK: Vreg: %73[ LoopTag+26 ]
+# CHECK: Vreg: %168[ 2 ]
+# CHECK: Vreg: %156[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+42 ]
+# CHECK: Vreg: %23[ LoopTag+67 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %94[ LoopTag+34 ]
+# CHECK: Vreg: %30[ 17 ]
+# CHECK: Vreg: %151[ 2 ]
+# CHECK: Vreg: %18[ LoopTag+39 ]
+# CHECK: Vreg: %63[ LoopTag+19 ]
+# CHECK: Vreg: %37[ LoopTag+49 ]
+# CHECK: Vreg: %96[ LoopTag+41 ]
+# CHECK: Vreg: %58[ LoopTag+42 ]
+# CHECK: Vreg: %20[ LoopTag+17 ]
+# CHECK: Vreg: %1[ LoopTag+58 ]
+# CHECK: Vreg: %65[ LoopTag+26 ]
+# CHECK: Vreg: %155[ 3 ]
+# CHECK: Vreg: %143[ 7 ]
+# CHECK: Vreg: %60[ LoopTag+19 ]
+# CHECK: Vreg: %169[ 2 ]
+# CHECK: Vreg: %22[ LoopTag+34 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %67[ LoopTag+26 ]
+# CHECK: Vreg: %3[ LoopTag+28 ]
+# CHECK: Vreg: %164[ 2 ]
+# CHECK: Vreg: %145[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+43 ]
+# CHECK: Vreg: %88[ 5 ]
+# CHECK: Vreg: %5[ 27 ]
+# CHECK: Vreg: %69[ LoopTag+26 ]
+# CHECK: Vreg: %95[ LoopTag+37 ]
+# CHECK: Vreg: %140[ 8 ]
+# CHECK: Vreg: %171[ 0 ]
+# CHECK: Vreg: %159[ 2 ]
+# CHECK: Vreg: %19[ 6 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+81 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+82 ]
+# CHECK: Instr: %172:sreg_32 = S_ORN2_B32 killed %156, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+22 ]
+# CHECK: Vreg: %166[ 1 ]
+# CHECK: Vreg: %90[ LoopTag+27 ]
+# CHECK: Vreg: %71[ LoopTag+25 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Vreg: %161[ 1 ]
+# CHECK: Vreg: %104[ 17 ]
+# CHECK: Vreg: %21[ LoopTag+20 ]
+# CHECK: Vreg: %149[ 1 ]
+# CHECK: Vreg: %40[ LoopTag+45 ]
+# CHECK: Vreg: %92[ LoopTag+30 ]
+# CHECK: Vreg: %73[ LoopTag+25 ]
+# CHECK: Vreg: %168[ 1 ]
+# CHECK: Vreg: %156[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+41 ]
+# CHECK: Vreg: %23[ LoopTag+66 ]
+# CHECK: Vreg: %4[ 42 ]
+# CHECK: Vreg: %94[ LoopTag+33 ]
+# CHECK: Vreg: %30[ 16 ]
+# CHECK: Vreg: %151[ 1 ]
+# CHECK: Vreg: %18[ LoopTag+38 ]
+# CHECK: Vreg: %63[ LoopTag+18 ]
+# CHECK: Vreg: %37[ LoopTag+48 ]
+# CHECK: Vreg: %96[ LoopTag+40 ]
+# CHECK: Vreg: %58[ LoopTag+41 ]
+# CHECK: Vreg: %20[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+57 ]
+# CHECK: Vreg: %65[ LoopTag+25 ]
+# CHECK: Vreg: %155[ 2 ]
+# CHECK: Vreg: %143[ 6 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %169[ 1 ]
+# CHECK: Vreg: %22[ LoopTag+33 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+56 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+57 ]
+# CHECK: Vreg: %67[ LoopTag+25 ]
+# CHECK: Vreg: %3[ LoopTag+27 ]
+# CHECK: Vreg: %164[ 1 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+42 ]
+# CHECK: Vreg: %88[ 4 ]
+# CHECK: Vreg: %5[ 26 ]
+# CHECK: Vreg: %69[ LoopTag+25 ]
+# CHECK: Vreg: %95[ LoopTag+36 ]
+# CHECK: Vreg: %140[ 7 ]
+# CHECK: Vreg: %159[ 1 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+80 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+81 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %172[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %159[ 0 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %172[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %159[ 0 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %173:vgpr_32 = V_MUL_LO_U32_e64 %88, %145, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+46 ]
+# CHECK: Vreg: %90[ LoopTag+51 ]
+# CHECK: Vreg: %71[ LoopTag+49 ]
+# CHECK: Vreg: %147[ 3 ]
+# CHECK: Vreg: %104[ 41 ]
+# CHECK: Vreg: %21[ LoopTag+44 ]
+# CHECK: Vreg: %149[ 27 ]
+# CHECK: Vreg: %40[ LoopTag+69 ]
+# CHECK: Vreg: %213[ 28 ]
+# CHECK: Vreg: %73[ LoopTag+49 ]
+# CHECK: Vreg: %92[ LoopTag+54 ]
+# CHECK: Vreg: %2[ LoopTag+65 ]
+# CHECK: Vreg: %23[ LoopTag+90 ]
+# CHECK: Vreg: %4[ 66 ]
+# CHECK: Vreg: %196[ 23 ]
+# CHECK: Vreg: %94[ LoopTag+57 ]
+# CHECK: Vreg: %30[ 40 ]
+# CHECK: Vreg: %151[ 27 ]
+# CHECK: Vreg: %18[ LoopTag+62 ]
+# CHECK: Vreg: %63[ LoopTag+42 ]
+# CHECK: Vreg: %37[ LoopTag+72 ]
+# CHECK: Vreg: %198[ 24 ]
+# CHECK: Vreg: %96[ LoopTag+64 ]
+# CHECK: Vreg: %58[ LoopTag+65 ]
+# CHECK: Vreg: %212[ LoopTag+43 ]
+# CHECK: Vreg: %1[ LoopTag+81 ]
+# CHECK: Vreg: %20[ LoopTag+40 ]
+# CHECK: Vreg: %65[ LoopTag+49 ]
+# CHECK: Vreg: %143[ 30 ]
+# CHECK: Vreg: %60[ LoopTag+42 ]
+# CHECK: Vreg: %22[ LoopTag+57 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+80 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+81 ]
+# CHECK: Vreg: %67[ LoopTag+49 ]
+# CHECK: Vreg: %3[ LoopTag+51 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+66 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %5[ 22 ]
+# CHECK: Vreg: %69[ LoopTag+49 ]
+# CHECK: Vreg: %95[ LoopTag+60 ]
+# CHECK: Vreg: %140[ 31 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %19, %173, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+45 ]
+# CHECK: Vreg: %173[ 0 ]
+# CHECK: Vreg: %90[ LoopTag+50 ]
+# CHECK: Vreg: %71[ LoopTag+48 ]
+# CHECK: Vreg: %147[ 2 ]
+# CHECK: Vreg: %104[ 40 ]
+# CHECK: Vreg: %21[ LoopTag+43 ]
+# CHECK: Vreg: %149[ 26 ]
+# CHECK: Vreg: %40[ LoopTag+68 ]
+# CHECK: Vreg: %213[ 27 ]
+# CHECK: Vreg: %73[ LoopTag+48 ]
+# CHECK: Vreg: %92[ LoopTag+53 ]
+# CHECK: Vreg: %2[ LoopTag+64 ]
+# CHECK: Vreg: %23[ LoopTag+89 ]
+# CHECK: Vreg: %4[ 65 ]
+# CHECK: Vreg: %196[ 22 ]
+# CHECK: Vreg: %94[ LoopTag+56 ]
+# CHECK: Vreg: %30[ 39 ]
+# CHECK: Vreg: %151[ 26 ]
+# CHECK: Vreg: %18[ LoopTag+61 ]
+# CHECK: Vreg: %63[ LoopTag+41 ]
+# CHECK: Vreg: %37[ LoopTag+71 ]
+# CHECK: Vreg: %198[ 23 ]
+# CHECK: Vreg: %96[ LoopTag+63 ]
+# CHECK: Vreg: %58[ LoopTag+64 ]
+# CHECK: Vreg: %212[ LoopTag+42 ]
+# CHECK: Vreg: %1[ LoopTag+80 ]
+# CHECK: Vreg: %20[ LoopTag+39 ]
+# CHECK: Vreg: %65[ LoopTag+48 ]
+# CHECK: Vreg: %143[ 29 ]
+# CHECK: Vreg: %60[ LoopTag+41 ]
+# CHECK: Vreg: %22[ LoopTag+56 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %67[ LoopTag+48 ]
+# CHECK: Vreg: %3[ LoopTag+50 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+65 ]
+# CHECK: Vreg: %88[ 41 ]
+# CHECK: Vreg: %5[ 21 ]
+# CHECK: Vreg: %69[ LoopTag+48 ]
+# CHECK: Vreg: %95[ LoopTag+59 ]
+# CHECK: Vreg: %140[ 30 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %174:vgpr_32 = V_ADD_U32_e64 1, %145, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+44 ]
+# CHECK: Vreg: %173[ 25 ]
+# CHECK: Vreg: %90[ LoopTag+49 ]
+# CHECK: Vreg: %71[ LoopTag+47 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Vreg: %104[ 39 ]
+# CHECK: Vreg: %21[ LoopTag+42 ]
+# CHECK: Vreg: %149[ 25 ]
+# CHECK: Vreg: %40[ LoopTag+67 ]
+# CHECK: Vreg: %213[ 26 ]
+# CHECK: Vreg: %73[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+52 ]
+# CHECK: Vreg: %2[ LoopTag+63 ]
+# CHECK: Vreg: %23[ LoopTag+88 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %196[ 21 ]
+# CHECK: Vreg: %94[ LoopTag+55 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %151[ 25 ]
+# CHECK: Vreg: %18[ LoopTag+60 ]
+# CHECK: Vreg: %63[ LoopTag+40 ]
+# CHECK: Vreg: %37[ LoopTag+70 ]
+# CHECK: Vreg: %198[ 22 ]
+# CHECK: Vreg: %96[ LoopTag+62 ]
+# CHECK: Vreg: %58[ LoopTag+63 ]
+# CHECK: Vreg: %212[ LoopTag+41 ]
+# CHECK: Vreg: %1[ LoopTag+79 ]
+# CHECK: Vreg: %20[ LoopTag+38 ]
+# CHECK: Vreg: %65[ LoopTag+47 ]
+# CHECK: Vreg: %143[ 28 ]
+# CHECK: Vreg: %60[ LoopTag+40 ]
+# CHECK: Vreg: %22[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+78 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+79 ]
+# CHECK: Vreg: %67[ LoopTag+47 ]
+# CHECK: Vreg: %3[ LoopTag+49 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+64 ]
+# CHECK: Vreg: %88[ 40 ]
+# CHECK: Vreg: %5[ 20 ]
+# CHECK: Vreg: %69[ LoopTag+47 ]
+# CHECK: Vreg: %95[ LoopTag+58 ]
+# CHECK: Vreg: %140[ 29 ]
+# CHECK: Vreg: %19[ 41 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+102 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+103 ]
+# CHECK: Instr: %175:vgpr_32 = V_CVT_F32_U32_e64 %147, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+43 ]
+# CHECK: Vreg: %173[ 24 ]
+# CHECK: Vreg: %90[ LoopTag+48 ]
+# CHECK: Vreg: %71[ LoopTag+46 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %104[ 38 ]
+# CHECK: Vreg: %21[ LoopTag+41 ]
+# CHECK: Vreg: %149[ 24 ]
+# CHECK: Vreg: %40[ LoopTag+66 ]
+# CHECK: Vreg: %213[ 25 ]
+# CHECK: Vreg: %73[ LoopTag+46 ]
+# CHECK: Vreg: %92[ LoopTag+51 ]
+# CHECK: Vreg: %2[ LoopTag+62 ]
+# CHECK: Vreg: %23[ LoopTag+87 ]
+# CHECK: Vreg: %4[ 63 ]
+# CHECK: Vreg: %196[ 20 ]
+# CHECK: Vreg: %94[ LoopTag+54 ]
+# CHECK: Vreg: %30[ 37 ]
+# CHECK: Vreg: %151[ 24 ]
+# CHECK: Vreg: %18[ LoopTag+59 ]
+# CHECK: Vreg: %63[ LoopTag+39 ]
+# CHECK: Vreg: %37[ LoopTag+69 ]
+# CHECK: Vreg: %198[ 21 ]
+# CHECK: Vreg: %96[ LoopTag+61 ]
+# CHECK: Vreg: %58[ LoopTag+62 ]
+# CHECK: Vreg: %212[ LoopTag+40 ]
+# CHECK: Vreg: %1[ LoopTag+78 ]
+# CHECK: Vreg: %174[ 19 ]
+# CHECK: Vreg: %20[ LoopTag+37 ]
+# CHECK: Vreg: %65[ LoopTag+46 ]
+# CHECK: Vreg: %143[ 27 ]
+# CHECK: Vreg: %60[ LoopTag+39 ]
+# CHECK: Vreg: %22[ LoopTag+54 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %67[ LoopTag+46 ]
+# CHECK: Vreg: %3[ LoopTag+48 ]
+# CHECK: Vreg: %145[ 8 ]
+# CHECK: Vreg: %43[ LoopTag+63 ]
+# CHECK: Vreg: %88[ 39 ]
+# CHECK: Vreg: %5[ 19 ]
+# CHECK: Vreg: %69[ LoopTag+46 ]
+# CHECK: Vreg: %95[ LoopTag+57 ]
+# CHECK: Vreg: %140[ 28 ]
+# CHECK: Vreg: %19[ 40 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+101 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+102 ]
+# CHECK: Instr: %176:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %175, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+42 ]
+# CHECK: Vreg: %173[ 23 ]
+# CHECK: Vreg: %90[ LoopTag+47 ]
+# CHECK: Vreg: %71[ LoopTag+45 ]
+# CHECK: Vreg: %147[ 3 ]
+# CHECK: Vreg: %104[ 37 ]
+# CHECK: Vreg: %21[ LoopTag+40 ]
+# CHECK: Vreg: %149[ 23 ]
+# CHECK: Vreg: %40[ LoopTag+65 ]
+# CHECK: Vreg: %213[ 24 ]
+# CHECK: Vreg: %73[ LoopTag+45 ]
+# CHECK: Vreg: %175[ 0 ]
+# CHECK: Vreg: %92[ LoopTag+50 ]
+# CHECK: Vreg: %2[ LoopTag+61 ]
+# CHECK: Vreg: %23[ LoopTag+86 ]
+# CHECK: Vreg: %4[ 62 ]
+# CHECK: Vreg: %196[ 19 ]
+# CHECK: Vreg: %94[ LoopTag+53 ]
+# CHECK: Vreg: %30[ 36 ]
+# CHECK: Vreg: %151[ 23 ]
+# CHECK: Vreg: %18[ LoopTag+58 ]
+# CHECK: Vreg: %63[ LoopTag+38 ]
+# CHECK: Vreg: %37[ LoopTag+68 ]
+# CHECK: Vreg: %198[ 20 ]
+# CHECK: Vreg: %96[ LoopTag+60 ]
+# CHECK: Vreg: %58[ LoopTag+61 ]
+# CHECK: Vreg: %212[ LoopTag+39 ]
+# CHECK: Vreg: %1[ LoopTag+77 ]
+# CHECK: Vreg: %174[ 18 ]
+# CHECK: Vreg: %20[ LoopTag+36 ]
+# CHECK: Vreg: %65[ LoopTag+45 ]
+# CHECK: Vreg: %143[ 26 ]
+# CHECK: Vreg: %60[ LoopTag+38 ]
+# CHECK: Vreg: %22[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+76 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+77 ]
+# CHECK: Vreg: %67[ LoopTag+45 ]
+# CHECK: Vreg: %3[ LoopTag+47 ]
+# CHECK: Vreg: %145[ 7 ]
+# CHECK: Vreg: %43[ LoopTag+62 ]
+# CHECK: Vreg: %88[ 38 ]
+# CHECK: Vreg: %5[ 18 ]
+# CHECK: Vreg: %69[ LoopTag+45 ]
+# CHECK: Vreg: %95[ LoopTag+56 ]
+# CHECK: Vreg: %140[ 27 ]
+# CHECK: Vreg: %19[ 39 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+100 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+101 ]
+# CHECK: Instr: %177:vgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, 1333788670, 0, killed %176, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+41 ]
+# CHECK: Vreg: %173[ 22 ]
+# CHECK: Vreg: %90[ LoopTag+46 ]
+# CHECK: Vreg: %71[ LoopTag+44 ]
+# CHECK: Vreg: %19[ 38 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+99 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+100 ]
+# CHECK: Vreg: %104[ 36 ]
+# CHECK: Vreg: %21[ LoopTag+39 ]
+# CHECK: Vreg: %149[ 22 ]
+# CHECK: Vreg: %40[ LoopTag+64 ]
+# CHECK: Vreg: %213[ 23 ]
+# CHECK: Vreg: %73[ LoopTag+44 ]
+# CHECK: Vreg: %92[ LoopTag+49 ]
+# CHECK: Vreg: %2[ LoopTag+60 ]
+# CHECK: Vreg: %23[ LoopTag+85 ]
+# CHECK: Vreg: %4[ 61 ]
+# CHECK: Vreg: %196[ 18 ]
+# CHECK: Vreg: %94[ LoopTag+52 ]
+# CHECK: Vreg: %30[ 35 ]
+# CHECK: Vreg: %151[ 22 ]
+# CHECK: Vreg: %18[ LoopTag+57 ]
+# CHECK: Vreg: %63[ LoopTag+37 ]
+# CHECK: Vreg: %37[ LoopTag+67 ]
+# CHECK: Vreg: %198[ 19 ]
+# CHECK: Vreg: %96[ LoopTag+59 ]
+# CHECK: Vreg: %58[ LoopTag+60 ]
+# CHECK: Vreg: %212[ LoopTag+38 ]
+# CHECK: Vreg: %1[ LoopTag+76 ]
+# CHECK: Vreg: %174[ 17 ]
+# CHECK: Vreg: %20[ LoopTag+35 ]
+# CHECK: Vreg: %65[ LoopTag+44 ]
+# CHECK: Vreg: %143[ 25 ]
+# CHECK: Vreg: %60[ LoopTag+37 ]
+# CHECK: Vreg: %22[ LoopTag+52 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+75 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+76 ]
+# CHECK: Vreg: %67[ LoopTag+44 ]
+# CHECK: Vreg: %3[ LoopTag+46 ]
+# CHECK: Vreg: %176[ 0 ]
+# CHECK: Vreg: %145[ 6 ]
+# CHECK: Vreg: %43[ LoopTag+61 ]
+# CHECK: Vreg: %88[ 37 ]
+# CHECK: Vreg: %5[ 17 ]
+# CHECK: Vreg: %69[ LoopTag+44 ]
+# CHECK: Vreg: %95[ LoopTag+55 ]
+# CHECK: Vreg: %140[ 26 ]
+# CHECK: Vreg: %147[ 2 ]
+# CHECK: Instr: %178:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, killed %177, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+40 ]
+# CHECK: Vreg: %173[ 21 ]
+# CHECK: Vreg: %90[ LoopTag+45 ]
+# CHECK: Vreg: %71[ LoopTag+43 ]
+# CHECK: Vreg: %19[ 37 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+98 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+99 ]
+# CHECK: Vreg: %104[ 35 ]
+# CHECK: Vreg: %21[ LoopTag+38 ]
+# CHECK: Vreg: %149[ 21 ]
+# CHECK: Vreg: %40[ LoopTag+63 ]
+# CHECK: Vreg: %213[ 22 ]
+# CHECK: Vreg: %73[ LoopTag+43 ]
+# CHECK: Vreg: %92[ LoopTag+48 ]
+# CHECK: Vreg: %2[ LoopTag+59 ]
+# CHECK: Vreg: %23[ LoopTag+84 ]
+# CHECK: Vreg: %4[ 60 ]
+# CHECK: Vreg: %196[ 17 ]
+# CHECK: Vreg: %94[ LoopTag+51 ]
+# CHECK: Vreg: %30[ 34 ]
+# CHECK: Vreg: %177[ 0 ]
+# CHECK: Vreg: %151[ 21 ]
+# CHECK: Vreg: %18[ LoopTag+56 ]
+# CHECK: Vreg: %63[ LoopTag+36 ]
+# CHECK: Vreg: %37[ LoopTag+66 ]
+# CHECK: Vreg: %198[ 18 ]
+# CHECK: Vreg: %96[ LoopTag+58 ]
+# CHECK: Vreg: %58[ LoopTag+59 ]
+# CHECK: Vreg: %212[ LoopTag+37 ]
+# CHECK: Vreg: %1[ LoopTag+75 ]
+# CHECK: Vreg: %174[ 16 ]
+# CHECK: Vreg: %20[ LoopTag+34 ]
+# CHECK: Vreg: %65[ LoopTag+43 ]
+# CHECK: Vreg: %143[ 24 ]
+# CHECK: Vreg: %60[ LoopTag+36 ]
+# CHECK: Vreg: %22[ LoopTag+51 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+74 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+75 ]
+# CHECK: Vreg: %67[ LoopTag+43 ]
+# CHECK: Vreg: %3[ LoopTag+45 ]
+# CHECK: Vreg: %145[ 5 ]
+# CHECK: Vreg: %43[ LoopTag+60 ]
+# CHECK: Vreg: %88[ 36 ]
+# CHECK: Vreg: %5[ 16 ]
+# CHECK: Vreg: %69[ LoopTag+43 ]
+# CHECK: Vreg: %95[ LoopTag+54 ]
+# CHECK: Vreg: %140[ 25 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Instr: %179:vgpr_32 = V_SUB_U32_e64 0, %147, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+39 ]
+# CHECK: Vreg: %173[ 20 ]
+# CHECK: Vreg: %90[ LoopTag+44 ]
+# CHECK: Vreg: %71[ LoopTag+42 ]
+# CHECK: Vreg: %19[ 36 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+97 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+98 ]
+# CHECK: Vreg: %104[ 34 ]
+# CHECK: Vreg: %21[ LoopTag+37 ]
+# CHECK: Vreg: %149[ 20 ]
+# CHECK: Vreg: %40[ LoopTag+62 ]
+# CHECK: Vreg: %213[ 21 ]
+# CHECK: Vreg: %73[ LoopTag+42 ]
+# CHECK: Vreg: %92[ LoopTag+47 ]
+# CHECK: Vreg: %2[ LoopTag+58 ]
+# CHECK: Vreg: %23[ LoopTag+83 ]
+# CHECK: Vreg: %4[ 59 ]
+# CHECK: Vreg: %196[ 16 ]
+# CHECK: Vreg: %94[ LoopTag+50 ]
+# CHECK: Vreg: %30[ 33 ]
+# CHECK: Vreg: %151[ 20 ]
+# CHECK: Vreg: %18[ LoopTag+55 ]
+# CHECK: Vreg: %63[ LoopTag+35 ]
+# CHECK: Vreg: %37[ LoopTag+65 ]
+# CHECK: Vreg: %198[ 17 ]
+# CHECK: Vreg: %96[ LoopTag+57 ]
+# CHECK: Vreg: %58[ LoopTag+58 ]
+# CHECK: Vreg: %212[ LoopTag+36 ]
+# CHECK: Vreg: %1[ LoopTag+74 ]
+# CHECK: Vreg: %174[ 15 ]
+# CHECK: Vreg: %20[ LoopTag+33 ]
+# CHECK: Vreg: %65[ LoopTag+42 ]
+# CHECK: Vreg: %143[ 23 ]
+# CHECK: Vreg: %60[ LoopTag+35 ]
+# CHECK: Vreg: %22[ LoopTag+50 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+73 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+74 ]
+# CHECK: Vreg: %67[ LoopTag+42 ]
+# CHECK: Vreg: %3[ LoopTag+44 ]
+# CHECK: Vreg: %145[ 4 ]
+# CHECK: Vreg: %43[ LoopTag+59 ]
+# CHECK: Vreg: %88[ 35 ]
+# CHECK: Vreg: %5[ 15 ]
+# CHECK: Vreg: %69[ LoopTag+42 ]
+# CHECK: Vreg: %95[ LoopTag+53 ]
+# CHECK: Vreg: %140[ 24 ]
+# CHECK: Vreg: %178[ 1 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: %180:vgpr_32 = V_MUL_LO_U32_e64 killed %179, %178, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+38 ]
+# CHECK: Vreg: %173[ 19 ]
+# CHECK: Vreg: %90[ LoopTag+43 ]
+# CHECK: Vreg: %71[ LoopTag+41 ]
+# CHECK: Vreg: %19[ 35 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+96 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+97 ]
+# CHECK: Vreg: %104[ 33 ]
+# CHECK: Vreg: %21[ LoopTag+36 ]
+# CHECK: Vreg: %149[ 19 ]
+# CHECK: Vreg: %40[ LoopTag+61 ]
+# CHECK: Vreg: %213[ 20 ]
+# CHECK: Vreg: %73[ LoopTag+41 ]
+# CHECK: Vreg: %92[ LoopTag+46 ]
+# CHECK: Vreg: %2[ LoopTag+57 ]
+# CHECK: Vreg: %23[ LoopTag+82 ]
+# CHECK: Vreg: %4[ 58 ]
+# CHECK: Vreg: %196[ 15 ]
+# CHECK: Vreg: %94[ LoopTag+49 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %151[ 19 ]
+# CHECK: Vreg: %18[ LoopTag+54 ]
+# CHECK: Vreg: %63[ LoopTag+34 ]
+# CHECK: Vreg: %37[ LoopTag+64 ]
+# CHECK: Vreg: %198[ 16 ]
+# CHECK: Vreg: %179[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+56 ]
+# CHECK: Vreg: %58[ LoopTag+57 ]
+# CHECK: Vreg: %212[ LoopTag+35 ]
+# CHECK: Vreg: %1[ LoopTag+73 ]
+# CHECK: Vreg: %174[ 14 ]
+# CHECK: Vreg: %20[ LoopTag+32 ]
+# CHECK: Vreg: %65[ LoopTag+41 ]
+# CHECK: Vreg: %143[ 22 ]
+# CHECK: Vreg: %60[ LoopTag+34 ]
+# CHECK: Vreg: %22[ LoopTag+49 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+72 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+73 ]
+# CHECK: Vreg: %67[ LoopTag+41 ]
+# CHECK: Vreg: %3[ LoopTag+43 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+58 ]
+# CHECK: Vreg: %88[ 34 ]
+# CHECK: Vreg: %5[ 14 ]
+# CHECK: Vreg: %69[ LoopTag+41 ]
+# CHECK: Vreg: %95[ LoopTag+52 ]
+# CHECK: Vreg: %140[ 23 ]
+# CHECK: Vreg: %178[ 0 ]
+# CHECK: Vreg: %147[ 4 ]
+# CHECK: Instr: %181:vgpr_32 = V_MUL_HI_U32_e64 %178, killed %180, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+37 ]
+# CHECK: Vreg: %173[ 18 ]
+# CHECK: Vreg: %90[ LoopTag+42 ]
+# CHECK: Vreg: %71[ LoopTag+40 ]
+# CHECK: Vreg: %180[ 0 ]
+# CHECK: Vreg: %19[ 34 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+95 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+96 ]
+# CHECK: Vreg: %104[ 32 ]
+# CHECK: Vreg: %21[ LoopTag+35 ]
+# CHECK: Vreg: %149[ 18 ]
+# CHECK: Vreg: %40[ LoopTag+60 ]
+# CHECK: Vreg: %213[ 19 ]
+# CHECK: Vreg: %73[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+45 ]
+# CHECK: Vreg: %2[ LoopTag+56 ]
+# CHECK: Vreg: %23[ LoopTag+81 ]
+# CHECK: Vreg: %4[ 57 ]
+# CHECK: Vreg: %196[ 14 ]
+# CHECK: Vreg: %94[ LoopTag+48 ]
+# CHECK: Vreg: %30[ 31 ]
+# CHECK: Vreg: %151[ 18 ]
+# CHECK: Vreg: %18[ LoopTag+53 ]
+# CHECK: Vreg: %63[ LoopTag+33 ]
+# CHECK: Vreg: %37[ LoopTag+63 ]
+# CHECK: Vreg: %198[ 15 ]
+# CHECK: Vreg: %96[ LoopTag+55 ]
+# CHECK: Vreg: %58[ LoopTag+56 ]
+# CHECK: Vreg: %212[ LoopTag+34 ]
+# CHECK: Vreg: %1[ LoopTag+72 ]
+# CHECK: Vreg: %174[ 13 ]
+# CHECK: Vreg: %20[ LoopTag+31 ]
+# CHECK: Vreg: %65[ LoopTag+40 ]
+# CHECK: Vreg: %143[ 21 ]
+# CHECK: Vreg: %60[ LoopTag+33 ]
+# CHECK: Vreg: %22[ LoopTag+48 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+71 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+72 ]
+# CHECK: Vreg: %67[ LoopTag+40 ]
+# CHECK: Vreg: %3[ LoopTag+42 ]
+# CHECK: Vreg: %145[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+57 ]
+# CHECK: Vreg: %88[ 33 ]
+# CHECK: Vreg: %5[ 13 ]
+# CHECK: Vreg: %69[ LoopTag+40 ]
+# CHECK: Vreg: %95[ LoopTag+51 ]
+# CHECK: Vreg: %140[ 22 ]
+# CHECK: Vreg: %178[ 0 ]
+# CHECK: Vreg: %147[ 3 ]
+# CHECK: Instr: %182:vgpr_32 = V_ADD_U32_e64 killed %178, killed %181, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+36 ]
+# CHECK: Vreg: %173[ 17 ]
+# CHECK: Vreg: %90[ LoopTag+41 ]
+# CHECK: Vreg: %71[ LoopTag+39 ]
+# CHECK: Vreg: %19[ 33 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+94 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+95 ]
+# CHECK: Vreg: %104[ 31 ]
+# CHECK: Vreg: %21[ LoopTag+34 ]
+# CHECK: Vreg: %149[ 17 ]
+# CHECK: Vreg: %40[ LoopTag+59 ]
+# CHECK: Vreg: %213[ 18 ]
+# CHECK: Vreg: %73[ LoopTag+39 ]
+# CHECK: Vreg: %92[ LoopTag+44 ]
+# CHECK: Vreg: %2[ LoopTag+55 ]
+# CHECK: Vreg: %23[ LoopTag+80 ]
+# CHECK: Vreg: %4[ 56 ]
+# CHECK: Vreg: %196[ 13 ]
+# CHECK: Vreg: %94[ LoopTag+47 ]
+# CHECK: Vreg: %30[ 30 ]
+# CHECK: Vreg: %151[ 17 ]
+# CHECK: Vreg: %18[ LoopTag+52 ]
+# CHECK: Vreg: %63[ LoopTag+32 ]
+# CHECK: Vreg: %37[ LoopTag+62 ]
+# CHECK: Vreg: %198[ 14 ]
+# CHECK: Vreg: %96[ LoopTag+54 ]
+# CHECK: Vreg: %58[ LoopTag+55 ]
+# CHECK: Vreg: %212[ LoopTag+33 ]
+# CHECK: Vreg: %1[ LoopTag+71 ]
+# CHECK: Vreg: %174[ 12 ]
+# CHECK: Vreg: %20[ LoopTag+30 ]
+# CHECK: Vreg: %65[ LoopTag+39 ]
+# CHECK: Vreg: %181[ 0 ]
+# CHECK: Vreg: %143[ 20 ]
+# CHECK: Vreg: %60[ LoopTag+32 ]
+# CHECK: Vreg: %22[ LoopTag+47 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+70 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+71 ]
+# CHECK: Vreg: %67[ LoopTag+39 ]
+# CHECK: Vreg: %3[ LoopTag+41 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+56 ]
+# CHECK: Vreg: %88[ 32 ]
+# CHECK: Vreg: %5[ 12 ]
+# CHECK: Vreg: %69[ LoopTag+39 ]
+# CHECK: Vreg: %95[ LoopTag+50 ]
+# CHECK: Vreg: %140[ 21 ]
+# CHECK: Vreg: %178[ 0 ]
+# CHECK: Vreg: %147[ 2 ]
+# CHECK: Instr: %183:vgpr_32 = V_MUL_HI_U32_e64 %145, killed %182, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+35 ]
+# CHECK: Vreg: %173[ 16 ]
+# CHECK: Vreg: %90[ LoopTag+40 ]
+# CHECK: Vreg: %71[ LoopTag+38 ]
+# CHECK: Vreg: %19[ 32 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+93 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+94 ]
+# CHECK: Vreg: %104[ 30 ]
+# CHECK: Vreg: %21[ LoopTag+33 ]
+# CHECK: Vreg: %149[ 16 ]
+# CHECK: Vreg: %40[ LoopTag+58 ]
+# CHECK: Vreg: %213[ 17 ]
+# CHECK: Vreg: %73[ LoopTag+38 ]
+# CHECK: Vreg: %182[ 0 ]
+# CHECK: Vreg: %92[ LoopTag+43 ]
+# CHECK: Vreg: %2[ LoopTag+54 ]
+# CHECK: Vreg: %23[ LoopTag+79 ]
+# CHECK: Vreg: %4[ 55 ]
+# CHECK: Vreg: %196[ 12 ]
+# CHECK: Vreg: %94[ LoopTag+46 ]
+# CHECK: Vreg: %30[ 29 ]
+# CHECK: Vreg: %151[ 16 ]
+# CHECK: Vreg: %18[ LoopTag+51 ]
+# CHECK: Vreg: %63[ LoopTag+31 ]
+# CHECK: Vreg: %37[ LoopTag+61 ]
+# CHECK: Vreg: %198[ 13 ]
+# CHECK: Vreg: %96[ LoopTag+53 ]
+# CHECK: Vreg: %58[ LoopTag+54 ]
+# CHECK: Vreg: %212[ LoopTag+32 ]
+# CHECK: Vreg: %1[ LoopTag+70 ]
+# CHECK: Vreg: %174[ 11 ]
+# CHECK: Vreg: %20[ LoopTag+29 ]
+# CHECK: Vreg: %65[ LoopTag+38 ]
+# CHECK: Vreg: %143[ 19 ]
+# CHECK: Vreg: %60[ LoopTag+31 ]
+# CHECK: Vreg: %22[ LoopTag+46 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+69 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+70 ]
+# CHECK: Vreg: %67[ LoopTag+38 ]
+# CHECK: Vreg: %3[ LoopTag+40 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+55 ]
+# CHECK: Vreg: %88[ 31 ]
+# CHECK: Vreg: %5[ 11 ]
+# CHECK: Vreg: %69[ LoopTag+38 ]
+# CHECK: Vreg: %95[ LoopTag+49 ]
+# CHECK: Vreg: %140[ 20 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Instr: %184:vgpr_32 = V_MUL_LO_U32_e64 %183, %147, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+34 ]
+# CHECK: Vreg: %173[ 15 ]
+# CHECK: Vreg: %90[ LoopTag+39 ]
+# CHECK: Vreg: %71[ LoopTag+37 ]
+# CHECK: Vreg: %19[ 31 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+92 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+93 ]
+# CHECK: Vreg: %104[ 29 ]
+# CHECK: Vreg: %21[ LoopTag+32 ]
+# CHECK: Vreg: %149[ 15 ]
+# CHECK: Vreg: %40[ LoopTag+57 ]
+# CHECK: Vreg: %213[ 16 ]
+# CHECK: Vreg: %73[ LoopTag+37 ]
+# CHECK: Vreg: %92[ LoopTag+42 ]
+# CHECK: Vreg: %2[ LoopTag+53 ]
+# CHECK: Vreg: %23[ LoopTag+78 ]
+# CHECK: Vreg: %4[ 54 ]
+# CHECK: Vreg: %196[ 11 ]
+# CHECK: Vreg: %94[ LoopTag+45 ]
+# CHECK: Vreg: %30[ 28 ]
+# CHECK: Vreg: %151[ 15 ]
+# CHECK: Vreg: %18[ LoopTag+50 ]
+# CHECK: Vreg: %63[ LoopTag+30 ]
+# CHECK: Vreg: %37[ LoopTag+60 ]
+# CHECK: Vreg: %198[ 12 ]
+# CHECK: Vreg: %96[ LoopTag+52 ]
+# CHECK: Vreg: %58[ LoopTag+53 ]
+# CHECK: Vreg: %212[ LoopTag+31 ]
+# CHECK: Vreg: %1[ LoopTag+69 ]
+# CHECK: Vreg: %174[ 10 ]
+# CHECK: Vreg: %20[ LoopTag+28 ]
+# CHECK: Vreg: %65[ LoopTag+37 ]
+# CHECK: Vreg: %143[ 18 ]
+# CHECK: Vreg: %60[ LoopTag+30 ]
+# CHECK: Vreg: %22[ LoopTag+45 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+68 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+69 ]
+# CHECK: Vreg: %67[ LoopTag+37 ]
+# CHECK: Vreg: %3[ LoopTag+39 ]
+# CHECK: Vreg: %183[ 0 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+54 ]
+# CHECK: Vreg: %88[ 30 ]
+# CHECK: Vreg: %5[ 10 ]
+# CHECK: Vreg: %69[ LoopTag+37 ]
+# CHECK: Vreg: %95[ LoopTag+48 ]
+# CHECK: Vreg: %140[ 19 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: %185:vgpr_32 = V_SUB_U32_e64 %145, killed %184, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+33 ]
+# CHECK: Vreg: %173[ 14 ]
+# CHECK: Vreg: %90[ LoopTag+38 ]
+# CHECK: Vreg: %71[ LoopTag+36 ]
+# CHECK: Vreg: %19[ 30 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+91 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+92 ]
+# CHECK: Vreg: %104[ 28 ]
+# CHECK: Vreg: %21[ LoopTag+31 ]
+# CHECK: Vreg: %149[ 14 ]
+# CHECK: Vreg: %40[ LoopTag+56 ]
+# CHECK: Vreg: %213[ 15 ]
+# CHECK: Vreg: %73[ LoopTag+36 ]
+# CHECK: Vreg: %92[ LoopTag+41 ]
+# CHECK: Vreg: %2[ LoopTag+52 ]
+# CHECK: Vreg: %23[ LoopTag+77 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %196[ 10 ]
+# CHECK: Vreg: %94[ LoopTag+44 ]
+# CHECK: Vreg: %30[ 27 ]
+# CHECK: Vreg: %184[ 0 ]
+# CHECK: Vreg: %151[ 14 ]
+# CHECK: Vreg: %18[ LoopTag+49 ]
+# CHECK: Vreg: %63[ LoopTag+29 ]
+# CHECK: Vreg: %37[ LoopTag+59 ]
+# CHECK: Vreg: %198[ 11 ]
+# CHECK: Vreg: %96[ LoopTag+51 ]
+# CHECK: Vreg: %58[ LoopTag+52 ]
+# CHECK: Vreg: %212[ LoopTag+30 ]
+# CHECK: Vreg: %1[ LoopTag+68 ]
+# CHECK: Vreg: %174[ 9 ]
+# CHECK: Vreg: %20[ LoopTag+27 ]
+# CHECK: Vreg: %65[ LoopTag+36 ]
+# CHECK: Vreg: %143[ 17 ]
+# CHECK: Vreg: %60[ LoopTag+29 ]
+# CHECK: Vreg: %22[ LoopTag+44 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+67 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+68 ]
+# CHECK: Vreg: %67[ LoopTag+36 ]
+# CHECK: Vreg: %3[ LoopTag+38 ]
+# CHECK: Vreg: %183[ 2 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+53 ]
+# CHECK: Vreg: %88[ 29 ]
+# CHECK: Vreg: %5[ 9 ]
+# CHECK: Vreg: %69[ LoopTag+36 ]
+# CHECK: Vreg: %95[ LoopTag+47 ]
+# CHECK: Vreg: %140[ 18 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Instr: %186:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 %185, %147, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+32 ]
+# CHECK: Vreg: %173[ 13 ]
+# CHECK: Vreg: %90[ LoopTag+37 ]
+# CHECK: Vreg: %71[ LoopTag+35 ]
+# CHECK: Vreg: %19[ 29 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+90 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+91 ]
+# CHECK: Vreg: %104[ 27 ]
+# CHECK: Vreg: %21[ LoopTag+30 ]
+# CHECK: Vreg: %149[ 13 ]
+# CHECK: Vreg: %40[ LoopTag+55 ]
+# CHECK: Vreg: %213[ 14 ]
+# CHECK: Vreg: %73[ LoopTag+35 ]
+# CHECK: Vreg: %92[ LoopTag+40 ]
+# CHECK: Vreg: %2[ LoopTag+51 ]
+# CHECK: Vreg: %23[ LoopTag+76 ]
+# CHECK: Vreg: %4[ 52 ]
+# CHECK: Vreg: %196[ 9 ]
+# CHECK: Vreg: %94[ LoopTag+43 ]
+# CHECK: Vreg: %30[ 26 ]
+# CHECK: Vreg: %151[ 13 ]
+# CHECK: Vreg: %18[ LoopTag+48 ]
+# CHECK: Vreg: %63[ LoopTag+28 ]
+# CHECK: Vreg: %37[ LoopTag+58 ]
+# CHECK: Vreg: %198[ 10 ]
+# CHECK: Vreg: %96[ LoopTag+50 ]
+# CHECK: Vreg: %58[ LoopTag+51 ]
+# CHECK: Vreg: %212[ LoopTag+29 ]
+# CHECK: Vreg: %1[ LoopTag+67 ]
+# CHECK: Vreg: %174[ 8 ]
+# CHECK: Vreg: %20[ LoopTag+26 ]
+# CHECK: Vreg: %65[ LoopTag+35 ]
+# CHECK: Vreg: %143[ 16 ]
+# CHECK: Vreg: %60[ LoopTag+28 ]
+# CHECK: Vreg: %22[ LoopTag+43 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+66 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+67 ]
+# CHECK: Vreg: %67[ LoopTag+35 ]
+# CHECK: Vreg: %3[ LoopTag+37 ]
+# CHECK: Vreg: %183[ 1 ]
+# CHECK: Vreg: %145[ 13 ]
+# CHECK: Vreg: %43[ LoopTag+52 ]
+# CHECK: Vreg: %88[ 28 ]
+# CHECK: Vreg: %5[ 8 ]
+# CHECK: Vreg: %69[ LoopTag+35 ]
+# CHECK: Vreg: %95[ LoopTag+46 ]
+# CHECK: Vreg: %140[ 17 ]
+# CHECK: Vreg: %185[ 0 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: %187:vgpr_32 = V_ADD_U32_e64 1, %183, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+31 ]
+# CHECK: Vreg: %173[ 12 ]
+# CHECK: Vreg: %90[ LoopTag+36 ]
+# CHECK: Vreg: %71[ LoopTag+34 ]
+# CHECK: Vreg: %19[ 28 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+89 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+90 ]
+# CHECK: Vreg: %104[ 26 ]
+# CHECK: Vreg: %21[ LoopTag+29 ]
+# CHECK: Vreg: %149[ 12 ]
+# CHECK: Vreg: %40[ LoopTag+54 ]
+# CHECK: Vreg: %213[ 13 ]
+# CHECK: Vreg: %73[ LoopTag+34 ]
+# CHECK: Vreg: %92[ LoopTag+39 ]
+# CHECK: Vreg: %2[ LoopTag+50 ]
+# CHECK: Vreg: %23[ LoopTag+75 ]
+# CHECK: Vreg: %4[ 51 ]
+# CHECK: Vreg: %196[ 8 ]
+# CHECK: Vreg: %94[ LoopTag+42 ]
+# CHECK: Vreg: %30[ 25 ]
+# CHECK: Vreg: %151[ 12 ]
+# CHECK: Vreg: %18[ LoopTag+47 ]
+# CHECK: Vreg: %63[ LoopTag+27 ]
+# CHECK: Vreg: %37[ LoopTag+57 ]
+# CHECK: Vreg: %198[ 9 ]
+# CHECK: Vreg: %96[ LoopTag+49 ]
+# CHECK: Vreg: %58[ LoopTag+50 ]
+# CHECK: Vreg: %186[ 1 ]
+# CHECK: Vreg: %212[ LoopTag+28 ]
+# CHECK: Vreg: %1[ LoopTag+66 ]
+# CHECK: Vreg: %174[ 7 ]
+# CHECK: Vreg: %20[ LoopTag+25 ]
+# CHECK: Vreg: %65[ LoopTag+34 ]
+# CHECK: Vreg: %143[ 15 ]
+# CHECK: Vreg: %60[ LoopTag+27 ]
+# CHECK: Vreg: %22[ LoopTag+42 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+65 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+66 ]
+# CHECK: Vreg: %67[ LoopTag+34 ]
+# CHECK: Vreg: %3[ LoopTag+36 ]
+# CHECK: Vreg: %183[ 0 ]
+# CHECK: Vreg: %145[ 12 ]
+# CHECK: Vreg: %43[ LoopTag+51 ]
+# CHECK: Vreg: %88[ 27 ]
+# CHECK: Vreg: %5[ 7 ]
+# CHECK: Vreg: %69[ LoopTag+34 ]
+# CHECK: Vreg: %95[ LoopTag+45 ]
+# CHECK: Vreg: %140[ 16 ]
+# CHECK: Vreg: %185[ 2 ]
+# CHECK: Vreg: %147[ 2 ]
+# CHECK: Instr: %188:vgpr_32 = V_CNDMASK_B32_e64 0, killed %183, 0, killed %187, %186, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+30 ]
+# CHECK: Vreg: %173[ 11 ]
+# CHECK: Vreg: %90[ LoopTag+35 ]
+# CHECK: Vreg: %71[ LoopTag+33 ]
+# CHECK: Vreg: %19[ 27 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+88 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+89 ]
+# CHECK: Vreg: %187[ 0 ]
+# CHECK: Vreg: %104[ 25 ]
+# CHECK: Vreg: %21[ LoopTag+28 ]
+# CHECK: Vreg: %149[ 11 ]
+# CHECK: Vreg: %40[ LoopTag+53 ]
+# CHECK: Vreg: %213[ 12 ]
+# CHECK: Vreg: %73[ LoopTag+33 ]
+# CHECK: Vreg: %92[ LoopTag+38 ]
+# CHECK: Vreg: %2[ LoopTag+49 ]
+# CHECK: Vreg: %23[ LoopTag+74 ]
+# CHECK: Vreg: %4[ 50 ]
+# CHECK: Vreg: %196[ 7 ]
+# CHECK: Vreg: %94[ LoopTag+41 ]
+# CHECK: Vreg: %30[ 24 ]
+# CHECK: Vreg: %151[ 11 ]
+# CHECK: Vreg: %18[ LoopTag+46 ]
+# CHECK: Vreg: %63[ LoopTag+26 ]
+# CHECK: Vreg: %37[ LoopTag+56 ]
+# CHECK: Vreg: %198[ 8 ]
+# CHECK: Vreg: %96[ LoopTag+48 ]
+# CHECK: Vreg: %58[ LoopTag+49 ]
+# CHECK: Vreg: %186[ 0 ]
+# CHECK: Vreg: %212[ LoopTag+27 ]
+# CHECK: Vreg: %1[ LoopTag+65 ]
+# CHECK: Vreg: %174[ 6 ]
+# CHECK: Vreg: %20[ LoopTag+24 ]
+# CHECK: Vreg: %65[ LoopTag+33 ]
+# CHECK: Vreg: %143[ 14 ]
+# CHECK: Vreg: %60[ LoopTag+26 ]
+# CHECK: Vreg: %22[ LoopTag+41 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+64 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+65 ]
+# CHECK: Vreg: %67[ LoopTag+33 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %183[ 0 ]
+# CHECK: Vreg: %145[ 11 ]
+# CHECK: Vreg: %43[ LoopTag+50 ]
+# CHECK: Vreg: %88[ 26 ]
+# CHECK: Vreg: %5[ 6 ]
+# CHECK: Vreg: %69[ LoopTag+33 ]
+# CHECK: Vreg: %95[ LoopTag+44 ]
+# CHECK: Vreg: %140[ 15 ]
+# CHECK: Vreg: %185[ 1 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Instr: %189:vgpr_32 = V_SUB_U32_e64 %185, %147, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+29 ]
+# CHECK: Vreg: %173[ 10 ]
+# CHECK: Vreg: %90[ LoopTag+34 ]
+# CHECK: Vreg: %71[ LoopTag+32 ]
+# CHECK: Vreg: %19[ 26 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+87 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+88 ]
+# CHECK: Vreg: %104[ 24 ]
+# CHECK: Vreg: %21[ LoopTag+27 ]
+# CHECK: Vreg: %149[ 10 ]
+# CHECK: Vreg: %40[ LoopTag+52 ]
+# CHECK: Vreg: %213[ 11 ]
+# CHECK: Vreg: %73[ LoopTag+32 ]
+# CHECK: Vreg: %92[ LoopTag+37 ]
+# CHECK: Vreg: %2[ LoopTag+48 ]
+# CHECK: Vreg: %23[ LoopTag+73 ]
+# CHECK: Vreg: %4[ 49 ]
+# CHECK: Vreg: %196[ 6 ]
+# CHECK: Vreg: %94[ LoopTag+40 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %151[ 10 ]
+# CHECK: Vreg: %18[ LoopTag+45 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %37[ LoopTag+55 ]
+# CHECK: Vreg: %198[ 7 ]
+# CHECK: Vreg: %96[ LoopTag+47 ]
+# CHECK: Vreg: %58[ LoopTag+48 ]
+# CHECK: Vreg: %186[ 1 ]
+# CHECK: Vreg: %212[ LoopTag+26 ]
+# CHECK: Vreg: %1[ LoopTag+64 ]
+# CHECK: Vreg: %174[ 5 ]
+# CHECK: Vreg: %20[ LoopTag+23 ]
+# CHECK: Vreg: %65[ LoopTag+32 ]
+# CHECK: Vreg: %143[ 13 ]
+# CHECK: Vreg: %60[ LoopTag+25 ]
+# CHECK: Vreg: %188[ 3 ]
+# CHECK: Vreg: %22[ LoopTag+40 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+63 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+64 ]
+# CHECK: Vreg: %67[ LoopTag+32 ]
+# CHECK: Vreg: %3[ LoopTag+34 ]
+# CHECK: Vreg: %145[ 10 ]
+# CHECK: Vreg: %43[ LoopTag+49 ]
+# CHECK: Vreg: %88[ 25 ]
+# CHECK: Vreg: %5[ 5 ]
+# CHECK: Vreg: %69[ LoopTag+32 ]
+# CHECK: Vreg: %95[ LoopTag+43 ]
+# CHECK: Vreg: %140[ 14 ]
+# CHECK: Vreg: %185[ 0 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: %190:vgpr_32 = V_CNDMASK_B32_e64 0, killed %185, 0, killed %189, killed %186, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+28 ]
+# CHECK: Vreg: %173[ 9 ]
+# CHECK: Vreg: %90[ LoopTag+33 ]
+# CHECK: Vreg: %71[ LoopTag+31 ]
+# CHECK: Vreg: %19[ 25 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+86 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+87 ]
+# CHECK: Vreg: %104[ 23 ]
+# CHECK: Vreg: %21[ LoopTag+26 ]
+# CHECK: Vreg: %149[ 9 ]
+# CHECK: Vreg: %40[ LoopTag+51 ]
+# CHECK: Vreg: %213[ 10 ]
+# CHECK: Vreg: %73[ LoopTag+31 ]
+# CHECK: Vreg: %92[ LoopTag+36 ]
+# CHECK: Vreg: %2[ LoopTag+47 ]
+# CHECK: Vreg: %189[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+72 ]
+# CHECK: Vreg: %4[ 48 ]
+# CHECK: Vreg: %196[ 5 ]
+# CHECK: Vreg: %94[ LoopTag+39 ]
+# CHECK: Vreg: %30[ 22 ]
+# CHECK: Vreg: %151[ 9 ]
+# CHECK: Vreg: %18[ LoopTag+44 ]
+# CHECK: Vreg: %63[ LoopTag+24 ]
+# CHECK: Vreg: %37[ LoopTag+54 ]
+# CHECK: Vreg: %198[ 6 ]
+# CHECK: Vreg: %96[ LoopTag+46 ]
+# CHECK: Vreg: %58[ LoopTag+47 ]
+# CHECK: Vreg: %186[ 0 ]
+# CHECK: Vreg: %212[ LoopTag+25 ]
+# CHECK: Vreg: %1[ LoopTag+63 ]
+# CHECK: Vreg: %174[ 4 ]
+# CHECK: Vreg: %20[ LoopTag+22 ]
+# CHECK: Vreg: %65[ LoopTag+31 ]
+# CHECK: Vreg: %143[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+24 ]
+# CHECK: Vreg: %188[ 2 ]
+# CHECK: Vreg: %22[ LoopTag+39 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+62 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+63 ]
+# CHECK: Vreg: %67[ LoopTag+31 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %145[ 9 ]
+# CHECK: Vreg: %43[ LoopTag+48 ]
+# CHECK: Vreg: %88[ 24 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Vreg: %69[ LoopTag+31 ]
+# CHECK: Vreg: %95[ LoopTag+42 ]
+# CHECK: Vreg: %140[ 13 ]
+# CHECK: Vreg: %185[ 0 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Instr: %191:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 killed %190, %147, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+27 ]
+# CHECK: Vreg: %173[ 8 ]
+# CHECK: Vreg: %90[ LoopTag+32 ]
+# CHECK: Vreg: %71[ LoopTag+30 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %104[ 22 ]
+# CHECK: Vreg: %21[ LoopTag+25 ]
+# CHECK: Vreg: %149[ 8 ]
+# CHECK: Vreg: %40[ LoopTag+50 ]
+# CHECK: Vreg: %213[ 9 ]
+# CHECK: Vreg: %73[ LoopTag+30 ]
+# CHECK: Vreg: %92[ LoopTag+35 ]
+# CHECK: Vreg: %2[ LoopTag+46 ]
+# CHECK: Vreg: %23[ LoopTag+71 ]
+# CHECK: Vreg: %4[ 47 ]
+# CHECK: Vreg: %196[ 4 ]
+# CHECK: Vreg: %94[ LoopTag+38 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %151[ 8 ]
+# CHECK: Vreg: %18[ LoopTag+43 ]
+# CHECK: Vreg: %63[ LoopTag+23 ]
+# CHECK: Vreg: %37[ LoopTag+53 ]
+# CHECK: Vreg: %198[ 5 ]
+# CHECK: Vreg: %96[ LoopTag+45 ]
+# CHECK: Vreg: %58[ LoopTag+46 ]
+# CHECK: Vreg: %212[ LoopTag+24 ]
+# CHECK: Vreg: %1[ LoopTag+62 ]
+# CHECK: Vreg: %174[ 3 ]
+# CHECK: Vreg: %20[ LoopTag+21 ]
+# CHECK: Vreg: %65[ LoopTag+30 ]
+# CHECK: Vreg: %143[ 11 ]
+# CHECK: Vreg: %60[ LoopTag+23 ]
+# CHECK: Vreg: %188[ 1 ]
+# CHECK: Vreg: %22[ LoopTag+38 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+61 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+62 ]
+# CHECK: Vreg: %67[ LoopTag+30 ]
+# CHECK: Vreg: %3[ LoopTag+32 ]
+# CHECK: Vreg: %145[ 8 ]
+# CHECK: Vreg: %190[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+47 ]
+# CHECK: Vreg: %88[ 23 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Vreg: %69[ LoopTag+30 ]
+# CHECK: Vreg: %95[ LoopTag+41 ]
+# CHECK: Vreg: %140[ 12 ]
+# CHECK: Vreg: %19[ 24 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+85 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+86 ]
+# CHECK: Instr: %192:vgpr_32 = V_ADD_U32_e64 1, %188, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+26 ]
+# CHECK: Vreg: %173[ 7 ]
+# CHECK: Vreg: %90[ LoopTag+31 ]
+# CHECK: Vreg: %71[ LoopTag+29 ]
+# CHECK: Vreg: %147[ 7 ]
+# CHECK: Vreg: %104[ 21 ]
+# CHECK: Vreg: %21[ LoopTag+24 ]
+# CHECK: Vreg: %149[ 7 ]
+# CHECK: Vreg: %40[ LoopTag+49 ]
+# CHECK: Vreg: %213[ 8 ]
+# CHECK: Vreg: %73[ LoopTag+29 ]
+# CHECK: Vreg: %92[ LoopTag+34 ]
+# CHECK: Vreg: %2[ LoopTag+45 ]
+# CHECK: Vreg: %23[ LoopTag+70 ]
+# CHECK: Vreg: %4[ 46 ]
+# CHECK: Vreg: %196[ 3 ]
+# CHECK: Vreg: %94[ LoopTag+37 ]
+# CHECK: Vreg: %30[ 20 ]
+# CHECK: Vreg: %151[ 7 ]
+# CHECK: Vreg: %18[ LoopTag+42 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %37[ LoopTag+52 ]
+# CHECK: Vreg: %198[ 4 ]
+# CHECK: Vreg: %96[ LoopTag+44 ]
+# CHECK: Vreg: %191[ 1 ]
+# CHECK: Vreg: %58[ LoopTag+45 ]
+# CHECK: Vreg: %212[ LoopTag+23 ]
+# CHECK: Vreg: %1[ LoopTag+61 ]
+# CHECK: Vreg: %174[ 2 ]
+# CHECK: Vreg: %20[ LoopTag+20 ]
+# CHECK: Vreg: %65[ LoopTag+29 ]
+# CHECK: Vreg: %143[ 10 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %188[ 0 ]
+# CHECK: Vreg: %22[ LoopTag+37 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+60 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+61 ]
+# CHECK: Vreg: %67[ LoopTag+29 ]
+# CHECK: Vreg: %3[ LoopTag+31 ]
+# CHECK: Vreg: %145[ 7 ]
+# CHECK: Vreg: %43[ LoopTag+46 ]
+# CHECK: Vreg: %88[ 22 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Vreg: %69[ LoopTag+29 ]
+# CHECK: Vreg: %95[ LoopTag+40 ]
+# CHECK: Vreg: %140[ 11 ]
+# CHECK: Vreg: %19[ 23 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+84 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+85 ]
+# CHECK: Instr: %193:vgpr_32 = V_CNDMASK_B32_e64 0, killed %188, 0, killed %192, killed %191, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %173[ 6 ]
+# CHECK: Vreg: %90[ LoopTag+30 ]
+# CHECK: Vreg: %71[ LoopTag+28 ]
+# CHECK: Vreg: %147[ 6 ]
+# CHECK: Vreg: %192[ 0 ]
+# CHECK: Vreg: %104[ 20 ]
+# CHECK: Vreg: %21[ LoopTag+23 ]
+# CHECK: Vreg: %149[ 6 ]
+# CHECK: Vreg: %40[ LoopTag+48 ]
+# CHECK: Vreg: %213[ 7 ]
+# CHECK: Vreg: %73[ LoopTag+28 ]
+# CHECK: Vreg: %92[ LoopTag+33 ]
+# CHECK: Vreg: %2[ LoopTag+44 ]
+# CHECK: Vreg: %23[ LoopTag+69 ]
+# CHECK: Vreg: %4[ 45 ]
+# CHECK: Vreg: %196[ 2 ]
+# CHECK: Vreg: %94[ LoopTag+36 ]
+# CHECK: Vreg: %30[ 19 ]
+# CHECK: Vreg: %151[ 6 ]
+# CHECK: Vreg: %18[ LoopTag+41 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %37[ LoopTag+51 ]
+# CHECK: Vreg: %198[ 3 ]
+# CHECK: Vreg: %96[ LoopTag+43 ]
+# CHECK: Vreg: %191[ 0 ]
+# CHECK: Vreg: %58[ LoopTag+44 ]
+# CHECK: Vreg: %212[ LoopTag+22 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %174[ 1 ]
+# CHECK: Vreg: %20[ LoopTag+19 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %143[ 9 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %188[ 0 ]
+# CHECK: Vreg: %22[ LoopTag+36 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %67[ LoopTag+28 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %145[ 6 ]
+# CHECK: Vreg: %43[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 21 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Vreg: %69[ LoopTag+28 ]
+# CHECK: Vreg: %95[ LoopTag+39 ]
+# CHECK: Vreg: %140[ 10 ]
+# CHECK: Vreg: %19[ 22 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+83 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+84 ]
+# CHECK: Instr: %194:sreg_32 = V_CMP_GE_U32_e64 %174, %5, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %173[ 5 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %147[ 5 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 5 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %213[ 6 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %196[ 1 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 5 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %212[ LoopTag+21 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %193[ 5 ]
+# CHECK: Vreg: %145[ 5 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 20 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %19[ 21 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Instr: %195:sreg_32 = S_OR_B32 killed %196, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+23 ]
+# CHECK: Vreg: %173[ 4 ]
+# CHECK: Vreg: %90[ LoopTag+28 ]
+# CHECK: Vreg: %71[ LoopTag+26 ]
+# CHECK: Vreg: %147[ 4 ]
+# CHECK: Vreg: %104[ 18 ]
+# CHECK: Vreg: %21[ LoopTag+21 ]
+# CHECK: Vreg: %149[ 4 ]
+# CHECK: Vreg: %40[ LoopTag+46 ]
+# CHECK: Vreg: %213[ 5 ]
+# CHECK: Vreg: %73[ LoopTag+26 ]
+# CHECK: Vreg: %92[ LoopTag+31 ]
+# CHECK: Vreg: %2[ LoopTag+42 ]
+# CHECK: Vreg: %23[ LoopTag+67 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %196[ 0 ]
+# CHECK: Vreg: %94[ LoopTag+34 ]
+# CHECK: Vreg: %30[ 17 ]
+# CHECK: Vreg: %151[ 4 ]
+# CHECK: Vreg: %18[ LoopTag+39 ]
+# CHECK: Vreg: %63[ LoopTag+19 ]
+# CHECK: Vreg: %37[ LoopTag+49 ]
+# CHECK: Vreg: %198[ 1 ]
+# CHECK: Vreg: %194[ 2 ]
+# CHECK: Vreg: %96[ LoopTag+41 ]
+# CHECK: Vreg: %58[ LoopTag+42 ]
+# CHECK: Vreg: %212[ LoopTag+20 ]
+# CHECK: Vreg: %1[ LoopTag+58 ]
+# CHECK: Vreg: %174[ 4 ]
+# CHECK: Vreg: %20[ LoopTag+17 ]
+# CHECK: Vreg: %65[ LoopTag+26 ]
+# CHECK: Vreg: %143[ 7 ]
+# CHECK: Vreg: %60[ LoopTag+19 ]
+# CHECK: Vreg: %22[ LoopTag+34 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+57 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+58 ]
+# CHECK: Vreg: %67[ LoopTag+26 ]
+# CHECK: Vreg: %3[ LoopTag+28 ]
+# CHECK: Vreg: %193[ 4 ]
+# CHECK: Vreg: %145[ 4 ]
+# CHECK: Vreg: %43[ LoopTag+43 ]
+# CHECK: Vreg: %88[ 19 ]
+# CHECK: Vreg: %5[ 41 ]
+# CHECK: Vreg: %69[ LoopTag+26 ]
+# CHECK: Vreg: %95[ LoopTag+37 ]
+# CHECK: Vreg: %140[ 8 ]
+# CHECK: Vreg: %19[ 20 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+81 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+82 ]
+# CHECK: Instr: %197:sreg_32 = S_ANDN2_B32 killed %198, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+22 ]
+# CHECK: Vreg: %173[ 3 ]
+# CHECK: Vreg: %90[ LoopTag+27 ]
+# CHECK: Vreg: %71[ LoopTag+25 ]
+# CHECK: Vreg: %147[ 3 ]
+# CHECK: Vreg: %104[ 17 ]
+# CHECK: Vreg: %21[ LoopTag+20 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+45 ]
+# CHECK: Vreg: %213[ 4 ]
+# CHECK: Vreg: %73[ LoopTag+25 ]
+# CHECK: Vreg: %92[ LoopTag+30 ]
+# CHECK: Vreg: %2[ LoopTag+41 ]
+# CHECK: Vreg: %23[ LoopTag+66 ]
+# CHECK: Vreg: %4[ 42 ]
+# CHECK: Vreg: %94[ LoopTag+33 ]
+# CHECK: Vreg: %30[ 16 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+38 ]
+# CHECK: Vreg: %63[ LoopTag+18 ]
+# CHECK: Vreg: %37[ LoopTag+48 ]
+# CHECK: Vreg: %198[ 0 ]
+# CHECK: Vreg: %194[ 1 ]
+# CHECK: Vreg: %96[ LoopTag+40 ]
+# CHECK: Vreg: %58[ LoopTag+41 ]
+# CHECK: Vreg: %212[ LoopTag+19 ]
+# CHECK: Vreg: %1[ LoopTag+57 ]
+# CHECK: Vreg: %174[ 3 ]
+# CHECK: Vreg: %20[ LoopTag+16 ]
+# CHECK: Vreg: %65[ LoopTag+25 ]
+# CHECK: Vreg: %143[ 6 ]
+# CHECK: Vreg: %60[ LoopTag+18 ]
+# CHECK: Vreg: %22[ LoopTag+33 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+56 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+57 ]
+# CHECK: Vreg: %67[ LoopTag+25 ]
+# CHECK: Vreg: %195[ 3 ]
+# CHECK: Vreg: %3[ LoopTag+27 ]
+# CHECK: Vreg: %193[ 3 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+42 ]
+# CHECK: Vreg: %88[ 18 ]
+# CHECK: Vreg: %5[ 40 ]
+# CHECK: Vreg: %69[ LoopTag+25 ]
+# CHECK: Vreg: %95[ LoopTag+36 ]
+# CHECK: Vreg: %140[ 7 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+80 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+81 ]
+# CHECK: Instr: %199:sreg_32 = S_AND_B32 killed %194, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %173[ 2 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %147[ 2 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 2 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %213[ 3 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %197[ 1 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %151[ 2 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %194[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %212[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %174[ 2 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %195[ 2 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %193[ 2 ]
+# CHECK: Vreg: %145[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 17 ]
+# CHECK: Vreg: %5[ 39 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 18 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Instr: %200:sreg_32 = S_OR_B32 killed %197, killed %199, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+20 ]
+# CHECK: Vreg: %173[ 1 ]
+# CHECK: Vreg: %90[ LoopTag+25 ]
+# CHECK: Vreg: %71[ LoopTag+23 ]
+# CHECK: Vreg: %199[ 0 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Vreg: %104[ 15 ]
+# CHECK: Vreg: %21[ LoopTag+18 ]
+# CHECK: Vreg: %149[ 1 ]
+# CHECK: Vreg: %40[ LoopTag+43 ]
+# CHECK: Vreg: %213[ 2 ]
+# CHECK: Vreg: %73[ LoopTag+23 ]
+# CHECK: Vreg: %197[ 0 ]
+# CHECK: Vreg: %92[ LoopTag+28 ]
+# CHECK: Vreg: %2[ LoopTag+39 ]
+# CHECK: Vreg: %23[ LoopTag+64 ]
+# CHECK: Vreg: %4[ 40 ]
+# CHECK: Vreg: %94[ LoopTag+31 ]
+# CHECK: Vreg: %30[ 14 ]
+# CHECK: Vreg: %151[ 1 ]
+# CHECK: Vreg: %18[ LoopTag+36 ]
+# CHECK: Vreg: %63[ LoopTag+16 ]
+# CHECK: Vreg: %37[ LoopTag+46 ]
+# CHECK: Vreg: %96[ LoopTag+38 ]
+# CHECK: Vreg: %58[ LoopTag+39 ]
+# CHECK: Vreg: %212[ LoopTag+17 ]
+# CHECK: Vreg: %1[ LoopTag+55 ]
+# CHECK: Vreg: %174[ 1 ]
+# CHECK: Vreg: %20[ LoopTag+14 ]
+# CHECK: Vreg: %65[ LoopTag+23 ]
+# CHECK: Vreg: %143[ 4 ]
+# CHECK: Vreg: %60[ LoopTag+16 ]
+# CHECK: Vreg: %22[ LoopTag+31 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+54 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+55 ]
+# CHECK: Vreg: %67[ LoopTag+23 ]
+# CHECK: Vreg: %195[ 1 ]
+# CHECK: Vreg: %3[ LoopTag+25 ]
+# CHECK: Vreg: %193[ 1 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+40 ]
+# CHECK: Vreg: %88[ 16 ]
+# CHECK: Vreg: %5[ 38 ]
+# CHECK: Vreg: %69[ LoopTag+23 ]
+# CHECK: Vreg: %95[ LoopTag+34 ]
+# CHECK: Vreg: %140[ 5 ]
+# CHECK: Vreg: %19[ 17 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+78 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+79 ]
+# CHECK: Instr: S_BRANCH %bb.37
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %173[ 0 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %200[ 0 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %195[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %193[ 0 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %173[ 0 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %200[ 0 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %195[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %193[ 0 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: %163:vgpr_32 = V_MUL_LO_U32_e64 %30, %147, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+29 ]
+# CHECK: Vreg: %90[ LoopTag+34 ]
+# CHECK: Vreg: %71[ LoopTag+32 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %104[ 1 ]
+# CHECK: Vreg: %21[ LoopTag+27 ]
+# CHECK: Vreg: %149[ 8 ]
+# CHECK: Vreg: %40[ LoopTag+52 ]
+# CHECK: Vreg: %92[ LoopTag+37 ]
+# CHECK: Vreg: %73[ LoopTag+32 ]
+# CHECK: Vreg: %2[ LoopTag+48 ]
+# CHECK: Vreg: %23[ LoopTag+73 ]
+# CHECK: Vreg: %4[ 26 ]
+# CHECK: Vreg: %94[ LoopTag+40 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %151[ 8 ]
+# CHECK: Vreg: %18[ LoopTag+45 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %37[ LoopTag+55 ]
+# CHECK: Vreg: %96[ LoopTag+47 ]
+# CHECK: Vreg: %58[ LoopTag+48 ]
+# CHECK: Vreg: %20[ LoopTag+23 ]
+# CHECK: Vreg: %1[ LoopTag+64 ]
+# CHECK: Vreg: %65[ LoopTag+32 ]
+# CHECK: Vreg: %155[ 9 ]
+# CHECK: Vreg: %143[ 13 ]
+# CHECK: Vreg: %60[ LoopTag+25 ]
+# CHECK: Vreg: %22[ LoopTag+40 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+63 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+64 ]
+# CHECK: Vreg: %67[ LoopTag+32 ]
+# CHECK: Vreg: %3[ LoopTag+34 ]
+# CHECK: Vreg: %145[ 6 ]
+# CHECK: Vreg: %43[ LoopTag+49 ]
+# CHECK: Vreg: %88[ 2 ]
+# CHECK: Vreg: %5[ 33 ]
+# CHECK: Vreg: %69[ LoopTag+32 ]
+# CHECK: Vreg: %95[ LoopTag+43 ]
+# CHECK: Vreg: %140[ 14 ]
+# CHECK: Vreg: %19[ 12 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+87 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+88 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %104, %163, 0, 0, implicit $exec :: (store (s32) into %ir.gep2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+28 ]
+# CHECK: Vreg: %90[ LoopTag+33 ]
+# CHECK: Vreg: %71[ LoopTag+31 ]
+# CHECK: Vreg: %147[ 13 ]
+# CHECK: Vreg: %104[ 0 ]
+# CHECK: Vreg: %21[ LoopTag+26 ]
+# CHECK: Vreg: %149[ 7 ]
+# CHECK: Vreg: %40[ LoopTag+51 ]
+# CHECK: Vreg: %92[ LoopTag+36 ]
+# CHECK: Vreg: %73[ LoopTag+31 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+47 ]
+# CHECK: Vreg: %23[ LoopTag+72 ]
+# CHECK: Vreg: %4[ 25 ]
+# CHECK: Vreg: %94[ LoopTag+39 ]
+# CHECK: Vreg: %30[ 22 ]
+# CHECK: Vreg: %151[ 7 ]
+# CHECK: Vreg: %18[ LoopTag+44 ]
+# CHECK: Vreg: %63[ LoopTag+24 ]
+# CHECK: Vreg: %37[ LoopTag+54 ]
+# CHECK: Vreg: %96[ LoopTag+46 ]
+# CHECK: Vreg: %58[ LoopTag+47 ]
+# CHECK: Vreg: %20[ LoopTag+22 ]
+# CHECK: Vreg: %1[ LoopTag+63 ]
+# CHECK: Vreg: %65[ LoopTag+31 ]
+# CHECK: Vreg: %155[ 8 ]
+# CHECK: Vreg: %143[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+24 ]
+# CHECK: Vreg: %22[ LoopTag+39 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+62 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+63 ]
+# CHECK: Vreg: %67[ LoopTag+31 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %145[ 5 ]
+# CHECK: Vreg: %43[ LoopTag+48 ]
+# CHECK: Vreg: %88[ 1 ]
+# CHECK: Vreg: %5[ 32 ]
+# CHECK: Vreg: %69[ LoopTag+31 ]
+# CHECK: Vreg: %95[ LoopTag+42 ]
+# CHECK: Vreg: %140[ 13 ]
+# CHECK: Vreg: %19[ 11 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+86 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+87 ]
+# CHECK: Instr: %201:sreg_32 = V_CMP_LT_U32_e64 %163, %88, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+27 ]
+# CHECK: Vreg: %90[ LoopTag+32 ]
+# CHECK: Vreg: %71[ LoopTag+30 ]
+# CHECK: Vreg: %147[ 12 ]
+# CHECK: Vreg: %104[ 22 ]
+# CHECK: Vreg: %21[ LoopTag+25 ]
+# CHECK: Vreg: %149[ 6 ]
+# CHECK: Vreg: %40[ LoopTag+50 ]
+# CHECK: Vreg: %92[ LoopTag+35 ]
+# CHECK: Vreg: %73[ LoopTag+30 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+46 ]
+# CHECK: Vreg: %23[ LoopTag+71 ]
+# CHECK: Vreg: %4[ 24 ]
+# CHECK: Vreg: %94[ LoopTag+38 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %151[ 6 ]
+# CHECK: Vreg: %18[ LoopTag+43 ]
+# CHECK: Vreg: %63[ LoopTag+23 ]
+# CHECK: Vreg: %37[ LoopTag+53 ]
+# CHECK: Vreg: %96[ LoopTag+45 ]
+# CHECK: Vreg: %58[ LoopTag+46 ]
+# CHECK: Vreg: %20[ LoopTag+21 ]
+# CHECK: Vreg: %1[ LoopTag+62 ]
+# CHECK: Vreg: %65[ LoopTag+30 ]
+# CHECK: Vreg: %155[ 7 ]
+# CHECK: Vreg: %143[ 11 ]
+# CHECK: Vreg: %60[ LoopTag+23 ]
+# CHECK: Vreg: %22[ LoopTag+38 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+61 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+62 ]
+# CHECK: Vreg: %67[ LoopTag+30 ]
+# CHECK: Vreg: %3[ LoopTag+32 ]
+# CHECK: Vreg: %145[ 4 ]
+# CHECK: Vreg: %43[ LoopTag+47 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %5[ 31 ]
+# CHECK: Vreg: %69[ LoopTag+30 ]
+# CHECK: Vreg: %95[ LoopTag+41 ]
+# CHECK: Vreg: %140[ 12 ]
+# CHECK: Vreg: %19[ 10 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+85 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+86 ]
+# CHECK: Instr: %157:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+26 ]
+# CHECK: Vreg: %90[ LoopTag+31 ]
+# CHECK: Vreg: %71[ LoopTag+29 ]
+# CHECK: Vreg: %147[ 11 ]
+# CHECK: Vreg: %104[ 21 ]
+# CHECK: Vreg: %21[ LoopTag+24 ]
+# CHECK: Vreg: %149[ 5 ]
+# CHECK: Vreg: %40[ LoopTag+49 ]
+# CHECK: Vreg: %92[ LoopTag+34 ]
+# CHECK: Vreg: %73[ LoopTag+29 ]
+# CHECK: Vreg: %201[ 1 ]
+# CHECK: Vreg: %163[ 26 ]
+# CHECK: Vreg: %2[ LoopTag+45 ]
+# CHECK: Vreg: %23[ LoopTag+70 ]
+# CHECK: Vreg: %4[ 23 ]
+# CHECK: Vreg: %94[ LoopTag+37 ]
+# CHECK: Vreg: %30[ 20 ]
+# CHECK: Vreg: %151[ 5 ]
+# CHECK: Vreg: %18[ LoopTag+42 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %37[ LoopTag+52 ]
+# CHECK: Vreg: %96[ LoopTag+44 ]
+# CHECK: Vreg: %58[ LoopTag+45 ]
+# CHECK: Vreg: %20[ LoopTag+20 ]
+# CHECK: Vreg: %1[ LoopTag+61 ]
+# CHECK: Vreg: %65[ LoopTag+29 ]
+# CHECK: Vreg: %155[ 6 ]
+# CHECK: Vreg: %143[ 10 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %22[ LoopTag+37 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+60 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+61 ]
+# CHECK: Vreg: %67[ LoopTag+29 ]
+# CHECK: Vreg: %3[ LoopTag+31 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+46 ]
+# CHECK: Vreg: %88[ 8 ]
+# CHECK: Vreg: %5[ 30 ]
+# CHECK: Vreg: %69[ LoopTag+29 ]
+# CHECK: Vreg: %95[ LoopTag+40 ]
+# CHECK: Vreg: %140[ 11 ]
+# CHECK: Vreg: %19[ 9 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+84 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+85 ]
+# CHECK: Instr: %171:sreg_32 = SI_IF killed %201, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %90[ LoopTag+30 ]
+# CHECK: Vreg: %71[ LoopTag+28 ]
+# CHECK: Vreg: %147[ 10 ]
+# CHECK: Vreg: %104[ 20 ]
+# CHECK: Vreg: %21[ LoopTag+23 ]
+# CHECK: Vreg: %149[ 4 ]
+# CHECK: Vreg: %40[ LoopTag+48 ]
+# CHECK: Vreg: %92[ LoopTag+33 ]
+# CHECK: Vreg: %73[ LoopTag+28 ]
+# CHECK: Vreg: %201[ 0 ]
+# CHECK: Vreg: %163[ 25 ]
+# CHECK: Vreg: %2[ LoopTag+44 ]
+# CHECK: Vreg: %23[ LoopTag+69 ]
+# CHECK: Vreg: %4[ 22 ]
+# CHECK: Vreg: %94[ LoopTag+36 ]
+# CHECK: Vreg: %30[ 19 ]
+# CHECK: Vreg: %151[ 4 ]
+# CHECK: Vreg: %18[ LoopTag+41 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %37[ LoopTag+51 ]
+# CHECK: Vreg: %96[ LoopTag+43 ]
+# CHECK: Vreg: %58[ LoopTag+44 ]
+# CHECK: Vreg: %20[ LoopTag+19 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %155[ 5 ]
+# CHECK: Vreg: %143[ 9 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %22[ LoopTag+36 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %67[ LoopTag+28 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %157[ 1 ]
+# CHECK: Vreg: %145[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ LoopTag+28 ]
+# CHECK: Vreg: %95[ LoopTag+39 ]
+# CHECK: Vreg: %140[ 10 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+83 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+84 ]
+# CHECK: Instr: S_BRANCH %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %147[ 9 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %163[ 24 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 21 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %147[ 9 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %163[ 24 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 21 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: %198:sreg_32 = PHI %154, %bb.4, %172, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %154[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %172[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %159[ 0 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Instr: %196:sreg_32 = PHI undef %202:sreg_32, %bb.4, %159, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %159[ 0 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Instr: %203:vgpr_32 = PHI undef %204:vgpr_32, %bb.4, %161, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %196[ 2 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Instr: %205:vgpr_32 = PHI undef %204:vgpr_32, %bb.4, %164, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %196[ 2 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %203[ 2 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Instr: %206:vgpr_32 = PHI undef %204:vgpr_32, %bb.4, %166, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %205[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %196[ 2 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %203[ 2 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Instr: %207:vgpr_32 = PHI undef %204:vgpr_32, %bb.4, %168, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %205[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %206[ 2 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %196[ 2 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %203[ 2 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Instr: %208:vgpr_32 = PHI undef %204:vgpr_32, %bb.4, %145, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %205[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %206[ 2 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %196[ 2 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %203[ 2 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %207[ 2 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Instr: %209:vgpr_32 = PHI undef %204:vgpr_32, %bb.4, %147, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %208[ 2 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %205[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %206[ 2 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %196[ 2 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %203[ 2 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %207[ 2 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Instr: %210:vgpr_32 = PHI undef %204:vgpr_32, %bb.4, %149, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %208[ 2 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %205[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %209[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 6 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %206[ 2 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %196[ 2 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %203[ 2 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %207[ 2 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Instr: %211:vgpr_32 = PHI undef %204:vgpr_32, %bb.4, %151, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 30 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %208[ 2 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %205[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %209[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 6 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %206[ 2 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %196[ 2 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %203[ 2 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %210[ 2 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %207[ 2 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Instr: %212:vgpr_32 = PHI undef %204:vgpr_32, %bb.4, %169, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %90[ LoopTag+26 ]
+# CHECK: Vreg: %104[ 16 ]
+# CHECK: Vreg: %21[ LoopTag+19 ]
+# CHECK: Vreg: %149[ 30 ]
+# CHECK: Vreg: %73[ LoopTag+24 ]
+# CHECK: Vreg: %208[ 2 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %94[ LoopTag+32 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %63[ LoopTag+17 ]
+# CHECK: Vreg: %198[ 2 ]
+# CHECK: Vreg: %205[ 2 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %143[ 5 ]
+# CHECK: Vreg: %60[ LoopTag+17 ]
+# CHECK: Vreg: %22[ LoopTag+32 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+56 ]
+# CHECK: Vreg: %67[ LoopTag+24 ]
+# CHECK: Vreg: %209[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+41 ]
+# CHECK: Vreg: %88[ 3 ]
+# CHECK: Vreg: %5[ 25 ]
+# CHECK: Vreg: %95[ LoopTag+35 ]
+# CHECK: Vreg: %140[ 6 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %147[ 6 ]
+# CHECK: Vreg: %71[ LoopTag+24 ]
+# CHECK: Vreg: %206[ 2 ]
+# CHECK: Vreg: %40[ LoopTag+44 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %92[ LoopTag+29 ]
+# CHECK: Vreg: %23[ LoopTag+65 ]
+# CHECK: Vreg: %196[ 2 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %203[ 2 ]
+# CHECK: Vreg: %151[ 30 ]
+# CHECK: Vreg: %37[ LoopTag+47 ]
+# CHECK: Vreg: %210[ 2 ]
+# CHECK: Vreg: %96[ LoopTag+39 ]
+# CHECK: Vreg: %58[ LoopTag+40 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %65[ LoopTag+24 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %207[ 2 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %69[ LoopTag+24 ]
+# CHECK: Vreg: %211[ 2 ]
+# CHECK: Instr: %213:sreg_32 = SI_ELSE killed %155, %bb.37, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+20 ]
+# CHECK: Vreg: %90[ LoopTag+25 ]
+# CHECK: Vreg: %104[ 15 ]
+# CHECK: Vreg: %21[ LoopTag+18 ]
+# CHECK: Vreg: %149[ 29 ]
+# CHECK: Vreg: %73[ LoopTag+23 ]
+# CHECK: Vreg: %208[ 1 ]
+# CHECK: Vreg: %4[ 40 ]
+# CHECK: Vreg: %94[ LoopTag+31 ]
+# CHECK: Vreg: %18[ LoopTag+36 ]
+# CHECK: Vreg: %63[ LoopTag+16 ]
+# CHECK: Vreg: %198[ 1 ]
+# CHECK: Vreg: %205[ 1 ]
+# CHECK: Vreg: %212[ LoopTag+17 ]
+# CHECK: Vreg: %1[ LoopTag+55 ]
+# CHECK: Vreg: %143[ 4 ]
+# CHECK: Vreg: %60[ LoopTag+16 ]
+# CHECK: Vreg: %22[ LoopTag+31 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+54 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+55 ]
+# CHECK: Vreg: %67[ LoopTag+23 ]
+# CHECK: Vreg: %209[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+40 ]
+# CHECK: Vreg: %88[ 2 ]
+# CHECK: Vreg: %5[ 24 ]
+# CHECK: Vreg: %95[ LoopTag+34 ]
+# CHECK: Vreg: %140[ 5 ]
+# CHECK: Vreg: %19[ 3 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+78 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+79 ]
+# CHECK: Vreg: %147[ 5 ]
+# CHECK: Vreg: %71[ LoopTag+23 ]
+# CHECK: Vreg: %206[ 1 ]
+# CHECK: Vreg: %40[ LoopTag+43 ]
+# CHECK: Vreg: %2[ LoopTag+39 ]
+# CHECK: Vreg: %92[ LoopTag+28 ]
+# CHECK: Vreg: %23[ LoopTag+64 ]
+# CHECK: Vreg: %196[ 1 ]
+# CHECK: Vreg: %30[ 14 ]
+# CHECK: Vreg: %203[ 1 ]
+# CHECK: Vreg: %151[ 29 ]
+# CHECK: Vreg: %37[ LoopTag+46 ]
+# CHECK: Vreg: %210[ 1 ]
+# CHECK: Vreg: %96[ LoopTag+38 ]
+# CHECK: Vreg: %58[ LoopTag+39 ]
+# CHECK: Vreg: %20[ LoopTag+14 ]
+# CHECK: Vreg: %65[ LoopTag+23 ]
+# CHECK: Vreg: %155[ 0 ]
+# CHECK: Vreg: %207[ 1 ]
+# CHECK: Vreg: %3[ LoopTag+25 ]
+# CHECK: Vreg: %145[ 2 ]
+# CHECK: Vreg: %69[ LoopTag+23 ]
+# CHECK: Vreg: %211[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 28 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %208[ 0 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %198[ 0 ]
+# CHECK: Vreg: %205[ 0 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %209[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 1 ]
+# CHECK: Vreg: %5[ 23 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %147[ 4 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %206[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %196[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %203[ 0 ]
+# CHECK: Vreg: %151[ 28 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %207[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 28 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %208[ 0 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %198[ 0 ]
+# CHECK: Vreg: %205[ 0 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %209[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 1 ]
+# CHECK: Vreg: %5[ 23 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %147[ 4 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %206[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %196[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %203[ 0 ]
+# CHECK: Vreg: %151[ 28 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %207[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: --- MBB_9 ---
+# CHECK: Instr: %214:vgpr_32 = V_CVT_F32_U32_e64 %145, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+47 ]
+# CHECK: Vreg: %90[ LoopTag+52 ]
+# CHECK: Vreg: %71[ LoopTag+50 ]
+# CHECK: Vreg: %19[ 30 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+105 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+106 ]
+# CHECK: Vreg: %104[ 42 ]
+# CHECK: Vreg: %21[ LoopTag+45 ]
+# CHECK: Vreg: %149[ 26 ]
+# CHECK: Vreg: %40[ LoopTag+70 ]
+# CHECK: Vreg: %92[ LoopTag+55 ]
+# CHECK: Vreg: %73[ LoopTag+50 ]
+# CHECK: Vreg: %163[ 23 ]
+# CHECK: Vreg: %2[ LoopTag+66 ]
+# CHECK: Vreg: %23[ LoopTag+91 ]
+# CHECK: Vreg: %4[ 20 ]
+# CHECK: Vreg: %94[ LoopTag+58 ]
+# CHECK: Vreg: %30[ 41 ]
+# CHECK: Vreg: %151[ 26 ]
+# CHECK: Vreg: %18[ LoopTag+63 ]
+# CHECK: Vreg: %63[ LoopTag+43 ]
+# CHECK: Vreg: %37[ LoopTag+73 ]
+# CHECK: Vreg: %96[ LoopTag+65 ]
+# CHECK: Vreg: %58[ LoopTag+66 ]
+# CHECK: Vreg: %20[ LoopTag+41 ]
+# CHECK: Vreg: %1[ LoopTag+82 ]
+# CHECK: Vreg: %65[ LoopTag+50 ]
+# CHECK: Vreg: %155[ 27 ]
+# CHECK: Vreg: %143[ 31 ]
+# CHECK: Vreg: %60[ LoopTag+43 ]
+# CHECK: Vreg: %22[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+81 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+82 ]
+# CHECK: Vreg: %67[ LoopTag+50 ]
+# CHECK: Vreg: %3[ LoopTag+52 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+67 ]
+# CHECK: Vreg: %88[ 29 ]
+# CHECK: Vreg: %5[ 51 ]
+# CHECK: Vreg: %69[ LoopTag+50 ]
+# CHECK: Vreg: %95[ LoopTag+61 ]
+# CHECK: Vreg: %140[ 32 ]
+# CHECK: Vreg: %171[ 24 ]
+# CHECK: Vreg: %147[ 8 ]
+# CHECK: Instr: %215:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %214, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+46 ]
+# CHECK: Vreg: %90[ LoopTag+51 ]
+# CHECK: Vreg: %71[ LoopTag+49 ]
+# CHECK: Vreg: %19[ 29 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+104 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+105 ]
+# CHECK: Vreg: %104[ 41 ]
+# CHECK: Vreg: %21[ LoopTag+44 ]
+# CHECK: Vreg: %149[ 25 ]
+# CHECK: Vreg: %40[ LoopTag+69 ]
+# CHECK: Vreg: %92[ LoopTag+54 ]
+# CHECK: Vreg: %73[ LoopTag+49 ]
+# CHECK: Vreg: %163[ 22 ]
+# CHECK: Vreg: %2[ LoopTag+65 ]
+# CHECK: Vreg: %23[ LoopTag+90 ]
+# CHECK: Vreg: %4[ 19 ]
+# CHECK: Vreg: %94[ LoopTag+57 ]
+# CHECK: Vreg: %30[ 40 ]
+# CHECK: Vreg: %151[ 25 ]
+# CHECK: Vreg: %18[ LoopTag+62 ]
+# CHECK: Vreg: %63[ LoopTag+42 ]
+# CHECK: Vreg: %37[ LoopTag+72 ]
+# CHECK: Vreg: %96[ LoopTag+64 ]
+# CHECK: Vreg: %58[ LoopTag+65 ]
+# CHECK: Vreg: %20[ LoopTag+40 ]
+# CHECK: Vreg: %1[ LoopTag+81 ]
+# CHECK: Vreg: %65[ LoopTag+49 ]
+# CHECK: Vreg: %155[ 26 ]
+# CHECK: Vreg: %143[ 30 ]
+# CHECK: Vreg: %60[ LoopTag+42 ]
+# CHECK: Vreg: %22[ LoopTag+57 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+80 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+81 ]
+# CHECK: Vreg: %67[ LoopTag+49 ]
+# CHECK: Vreg: %3[ LoopTag+51 ]
+# CHECK: Vreg: %214[ 0 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+66 ]
+# CHECK: Vreg: %88[ 28 ]
+# CHECK: Vreg: %5[ 50 ]
+# CHECK: Vreg: %69[ LoopTag+49 ]
+# CHECK: Vreg: %95[ LoopTag+60 ]
+# CHECK: Vreg: %140[ 31 ]
+# CHECK: Vreg: %171[ 23 ]
+# CHECK: Vreg: %147[ 7 ]
+# CHECK: Instr: %216:vgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, 1333788670, 0, killed %215, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+45 ]
+# CHECK: Vreg: %90[ LoopTag+50 ]
+# CHECK: Vreg: %71[ LoopTag+48 ]
+# CHECK: Vreg: %19[ 28 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+103 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+104 ]
+# CHECK: Vreg: %104[ 40 ]
+# CHECK: Vreg: %21[ LoopTag+43 ]
+# CHECK: Vreg: %149[ 24 ]
+# CHECK: Vreg: %40[ LoopTag+68 ]
+# CHECK: Vreg: %92[ LoopTag+53 ]
+# CHECK: Vreg: %73[ LoopTag+48 ]
+# CHECK: Vreg: %163[ 21 ]
+# CHECK: Vreg: %2[ LoopTag+64 ]
+# CHECK: Vreg: %23[ LoopTag+89 ]
+# CHECK: Vreg: %4[ 18 ]
+# CHECK: Vreg: %94[ LoopTag+56 ]
+# CHECK: Vreg: %30[ 39 ]
+# CHECK: Vreg: %151[ 24 ]
+# CHECK: Vreg: %18[ LoopTag+61 ]
+# CHECK: Vreg: %63[ LoopTag+41 ]
+# CHECK: Vreg: %37[ LoopTag+71 ]
+# CHECK: Vreg: %215[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+63 ]
+# CHECK: Vreg: %58[ LoopTag+64 ]
+# CHECK: Vreg: %20[ LoopTag+39 ]
+# CHECK: Vreg: %1[ LoopTag+80 ]
+# CHECK: Vreg: %65[ LoopTag+48 ]
+# CHECK: Vreg: %155[ 25 ]
+# CHECK: Vreg: %143[ 29 ]
+# CHECK: Vreg: %60[ LoopTag+41 ]
+# CHECK: Vreg: %22[ LoopTag+56 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+79 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+80 ]
+# CHECK: Vreg: %67[ LoopTag+48 ]
+# CHECK: Vreg: %3[ LoopTag+50 ]
+# CHECK: Vreg: %145[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+65 ]
+# CHECK: Vreg: %88[ 27 ]
+# CHECK: Vreg: %5[ 49 ]
+# CHECK: Vreg: %69[ LoopTag+48 ]
+# CHECK: Vreg: %95[ LoopTag+59 ]
+# CHECK: Vreg: %140[ 30 ]
+# CHECK: Vreg: %171[ 22 ]
+# CHECK: Vreg: %147[ 6 ]
+# CHECK: Instr: %217:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, killed %216, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+44 ]
+# CHECK: Vreg: %90[ LoopTag+49 ]
+# CHECK: Vreg: %71[ LoopTag+47 ]
+# CHECK: Vreg: %19[ 27 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+102 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+103 ]
+# CHECK: Vreg: %104[ 39 ]
+# CHECK: Vreg: %21[ LoopTag+42 ]
+# CHECK: Vreg: %149[ 23 ]
+# CHECK: Vreg: %40[ LoopTag+67 ]
+# CHECK: Vreg: %92[ LoopTag+52 ]
+# CHECK: Vreg: %73[ LoopTag+47 ]
+# CHECK: Vreg: %163[ 20 ]
+# CHECK: Vreg: %2[ LoopTag+63 ]
+# CHECK: Vreg: %23[ LoopTag+88 ]
+# CHECK: Vreg: %4[ 17 ]
+# CHECK: Vreg: %94[ LoopTag+55 ]
+# CHECK: Vreg: %30[ 38 ]
+# CHECK: Vreg: %151[ 23 ]
+# CHECK: Vreg: %18[ LoopTag+60 ]
+# CHECK: Vreg: %63[ LoopTag+40 ]
+# CHECK: Vreg: %37[ LoopTag+70 ]
+# CHECK: Vreg: %96[ LoopTag+62 ]
+# CHECK: Vreg: %58[ LoopTag+63 ]
+# CHECK: Vreg: %20[ LoopTag+38 ]
+# CHECK: Vreg: %1[ LoopTag+79 ]
+# CHECK: Vreg: %65[ LoopTag+47 ]
+# CHECK: Vreg: %155[ 24 ]
+# CHECK: Vreg: %143[ 28 ]
+# CHECK: Vreg: %60[ LoopTag+40 ]
+# CHECK: Vreg: %22[ LoopTag+55 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+78 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+79 ]
+# CHECK: Vreg: %67[ LoopTag+47 ]
+# CHECK: Vreg: %3[ LoopTag+49 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+64 ]
+# CHECK: Vreg: %88[ 26 ]
+# CHECK: Vreg: %5[ 48 ]
+# CHECK: Vreg: %69[ LoopTag+47 ]
+# CHECK: Vreg: %95[ LoopTag+58 ]
+# CHECK: Vreg: %140[ 29 ]
+# CHECK: Vreg: %171[ 21 ]
+# CHECK: Vreg: %216[ 0 ]
+# CHECK: Vreg: %147[ 5 ]
+# CHECK: Instr: %218:vgpr_32 = V_SUB_U32_e64 0, %145, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+43 ]
+# CHECK: Vreg: %90[ LoopTag+48 ]
+# CHECK: Vreg: %71[ LoopTag+46 ]
+# CHECK: Vreg: %19[ 26 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+101 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+102 ]
+# CHECK: Vreg: %104[ 38 ]
+# CHECK: Vreg: %21[ LoopTag+41 ]
+# CHECK: Vreg: %149[ 22 ]
+# CHECK: Vreg: %40[ LoopTag+66 ]
+# CHECK: Vreg: %92[ LoopTag+51 ]
+# CHECK: Vreg: %73[ LoopTag+46 ]
+# CHECK: Vreg: %163[ 19 ]
+# CHECK: Vreg: %2[ LoopTag+62 ]
+# CHECK: Vreg: %23[ LoopTag+87 ]
+# CHECK: Vreg: %4[ 16 ]
+# CHECK: Vreg: %94[ LoopTag+54 ]
+# CHECK: Vreg: %30[ 37 ]
+# CHECK: Vreg: %151[ 22 ]
+# CHECK: Vreg: %18[ LoopTag+59 ]
+# CHECK: Vreg: %63[ LoopTag+39 ]
+# CHECK: Vreg: %37[ LoopTag+69 ]
+# CHECK: Vreg: %217[ 1 ]
+# CHECK: Vreg: %96[ LoopTag+61 ]
+# CHECK: Vreg: %58[ LoopTag+62 ]
+# CHECK: Vreg: %20[ LoopTag+37 ]
+# CHECK: Vreg: %1[ LoopTag+78 ]
+# CHECK: Vreg: %65[ LoopTag+46 ]
+# CHECK: Vreg: %155[ 23 ]
+# CHECK: Vreg: %143[ 27 ]
+# CHECK: Vreg: %60[ LoopTag+39 ]
+# CHECK: Vreg: %22[ LoopTag+54 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %67[ LoopTag+46 ]
+# CHECK: Vreg: %3[ LoopTag+48 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+63 ]
+# CHECK: Vreg: %88[ 25 ]
+# CHECK: Vreg: %5[ 47 ]
+# CHECK: Vreg: %69[ LoopTag+46 ]
+# CHECK: Vreg: %95[ LoopTag+57 ]
+# CHECK: Vreg: %140[ 28 ]
+# CHECK: Vreg: %171[ 20 ]
+# CHECK: Vreg: %147[ 4 ]
+# CHECK: Instr: %219:vgpr_32 = V_MUL_LO_U32_e64 killed %218, %217, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+42 ]
+# CHECK: Vreg: %90[ LoopTag+47 ]
+# CHECK: Vreg: %71[ LoopTag+45 ]
+# CHECK: Vreg: %19[ 25 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+100 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+101 ]
+# CHECK: Vreg: %104[ 37 ]
+# CHECK: Vreg: %21[ LoopTag+40 ]
+# CHECK: Vreg: %149[ 21 ]
+# CHECK: Vreg: %40[ LoopTag+65 ]
+# CHECK: Vreg: %92[ LoopTag+50 ]
+# CHECK: Vreg: %73[ LoopTag+45 ]
+# CHECK: Vreg: %163[ 18 ]
+# CHECK: Vreg: %2[ LoopTag+61 ]
+# CHECK: Vreg: %218[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+86 ]
+# CHECK: Vreg: %4[ 15 ]
+# CHECK: Vreg: %94[ LoopTag+53 ]
+# CHECK: Vreg: %30[ 36 ]
+# CHECK: Vreg: %151[ 21 ]
+# CHECK: Vreg: %18[ LoopTag+58 ]
+# CHECK: Vreg: %63[ LoopTag+38 ]
+# CHECK: Vreg: %37[ LoopTag+68 ]
+# CHECK: Vreg: %217[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+60 ]
+# CHECK: Vreg: %58[ LoopTag+61 ]
+# CHECK: Vreg: %20[ LoopTag+36 ]
+# CHECK: Vreg: %1[ LoopTag+77 ]
+# CHECK: Vreg: %65[ LoopTag+45 ]
+# CHECK: Vreg: %155[ 22 ]
+# CHECK: Vreg: %143[ 26 ]
+# CHECK: Vreg: %60[ LoopTag+38 ]
+# CHECK: Vreg: %22[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+76 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+77 ]
+# CHECK: Vreg: %67[ LoopTag+45 ]
+# CHECK: Vreg: %3[ LoopTag+47 ]
+# CHECK: Vreg: %145[ 4 ]
+# CHECK: Vreg: %43[ LoopTag+62 ]
+# CHECK: Vreg: %88[ 24 ]
+# CHECK: Vreg: %5[ 46 ]
+# CHECK: Vreg: %69[ LoopTag+45 ]
+# CHECK: Vreg: %95[ LoopTag+56 ]
+# CHECK: Vreg: %140[ 27 ]
+# CHECK: Vreg: %171[ 19 ]
+# CHECK: Vreg: %147[ 3 ]
+# CHECK: Instr: %220:vgpr_32 = V_MUL_HI_U32_e64 %217, killed %219, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+41 ]
+# CHECK: Vreg: %90[ LoopTag+46 ]
+# CHECK: Vreg: %71[ LoopTag+44 ]
+# CHECK: Vreg: %19[ 24 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+99 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+100 ]
+# CHECK: Vreg: %104[ 36 ]
+# CHECK: Vreg: %21[ LoopTag+39 ]
+# CHECK: Vreg: %149[ 20 ]
+# CHECK: Vreg: %40[ LoopTag+64 ]
+# CHECK: Vreg: %92[ LoopTag+49 ]
+# CHECK: Vreg: %73[ LoopTag+44 ]
+# CHECK: Vreg: %163[ 17 ]
+# CHECK: Vreg: %2[ LoopTag+60 ]
+# CHECK: Vreg: %23[ LoopTag+85 ]
+# CHECK: Vreg: %4[ 14 ]
+# CHECK: Vreg: %94[ LoopTag+52 ]
+# CHECK: Vreg: %30[ 35 ]
+# CHECK: Vreg: %151[ 20 ]
+# CHECK: Vreg: %18[ LoopTag+57 ]
+# CHECK: Vreg: %63[ LoopTag+37 ]
+# CHECK: Vreg: %37[ LoopTag+67 ]
+# CHECK: Vreg: %217[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+59 ]
+# CHECK: Vreg: %58[ LoopTag+60 ]
+# CHECK: Vreg: %20[ LoopTag+35 ]
+# CHECK: Vreg: %1[ LoopTag+76 ]
+# CHECK: Vreg: %65[ LoopTag+44 ]
+# CHECK: Vreg: %155[ 21 ]
+# CHECK: Vreg: %219[ 0 ]
+# CHECK: Vreg: %143[ 25 ]
+# CHECK: Vreg: %60[ LoopTag+37 ]
+# CHECK: Vreg: %22[ LoopTag+52 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+75 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+76 ]
+# CHECK: Vreg: %67[ LoopTag+44 ]
+# CHECK: Vreg: %3[ LoopTag+46 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+61 ]
+# CHECK: Vreg: %88[ 23 ]
+# CHECK: Vreg: %5[ 45 ]
+# CHECK: Vreg: %69[ LoopTag+44 ]
+# CHECK: Vreg: %95[ LoopTag+55 ]
+# CHECK: Vreg: %140[ 26 ]
+# CHECK: Vreg: %171[ 18 ]
+# CHECK: Vreg: %147[ 2 ]
+# CHECK: Instr: %221:vgpr_32 = V_ADD_U32_e64 killed %217, killed %220, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+40 ]
+# CHECK: Vreg: %90[ LoopTag+45 ]
+# CHECK: Vreg: %71[ LoopTag+43 ]
+# CHECK: Vreg: %19[ 23 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+98 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+99 ]
+# CHECK: Vreg: %104[ 35 ]
+# CHECK: Vreg: %21[ LoopTag+38 ]
+# CHECK: Vreg: %149[ 19 ]
+# CHECK: Vreg: %40[ LoopTag+63 ]
+# CHECK: Vreg: %92[ LoopTag+48 ]
+# CHECK: Vreg: %73[ LoopTag+43 ]
+# CHECK: Vreg: %163[ 16 ]
+# CHECK: Vreg: %2[ LoopTag+59 ]
+# CHECK: Vreg: %220[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+84 ]
+# CHECK: Vreg: %4[ 13 ]
+# CHECK: Vreg: %94[ LoopTag+51 ]
+# CHECK: Vreg: %30[ 34 ]
+# CHECK: Vreg: %151[ 19 ]
+# CHECK: Vreg: %18[ LoopTag+56 ]
+# CHECK: Vreg: %63[ LoopTag+36 ]
+# CHECK: Vreg: %37[ LoopTag+66 ]
+# CHECK: Vreg: %217[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+58 ]
+# CHECK: Vreg: %58[ LoopTag+59 ]
+# CHECK: Vreg: %20[ LoopTag+34 ]
+# CHECK: Vreg: %1[ LoopTag+75 ]
+# CHECK: Vreg: %65[ LoopTag+43 ]
+# CHECK: Vreg: %155[ 20 ]
+# CHECK: Vreg: %143[ 24 ]
+# CHECK: Vreg: %60[ LoopTag+36 ]
+# CHECK: Vreg: %22[ LoopTag+51 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+74 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+75 ]
+# CHECK: Vreg: %67[ LoopTag+43 ]
+# CHECK: Vreg: %3[ LoopTag+45 ]
+# CHECK: Vreg: %145[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+60 ]
+# CHECK: Vreg: %88[ 22 ]
+# CHECK: Vreg: %5[ 44 ]
+# CHECK: Vreg: %69[ LoopTag+43 ]
+# CHECK: Vreg: %95[ LoopTag+54 ]
+# CHECK: Vreg: %140[ 25 ]
+# CHECK: Vreg: %171[ 17 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Instr: %222:vgpr_32 = V_MUL_HI_U32_e64 %147, killed %221, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+39 ]
+# CHECK: Vreg: %90[ LoopTag+44 ]
+# CHECK: Vreg: %71[ LoopTag+42 ]
+# CHECK: Vreg: %19[ 22 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+97 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+98 ]
+# CHECK: Vreg: %104[ 34 ]
+# CHECK: Vreg: %21[ LoopTag+37 ]
+# CHECK: Vreg: %149[ 18 ]
+# CHECK: Vreg: %40[ LoopTag+62 ]
+# CHECK: Vreg: %92[ LoopTag+47 ]
+# CHECK: Vreg: %73[ LoopTag+42 ]
+# CHECK: Vreg: %163[ 15 ]
+# CHECK: Vreg: %2[ LoopTag+58 ]
+# CHECK: Vreg: %23[ LoopTag+83 ]
+# CHECK: Vreg: %4[ 12 ]
+# CHECK: Vreg: %94[ LoopTag+50 ]
+# CHECK: Vreg: %30[ 33 ]
+# CHECK: Vreg: %151[ 18 ]
+# CHECK: Vreg: %18[ LoopTag+55 ]
+# CHECK: Vreg: %63[ LoopTag+35 ]
+# CHECK: Vreg: %37[ LoopTag+65 ]
+# CHECK: Vreg: %96[ LoopTag+57 ]
+# CHECK: Vreg: %58[ LoopTag+58 ]
+# CHECK: Vreg: %20[ LoopTag+33 ]
+# CHECK: Vreg: %1[ LoopTag+74 ]
+# CHECK: Vreg: %65[ LoopTag+42 ]
+# CHECK: Vreg: %155[ 19 ]
+# CHECK: Vreg: %143[ 23 ]
+# CHECK: Vreg: %60[ LoopTag+35 ]
+# CHECK: Vreg: %22[ LoopTag+50 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+73 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+74 ]
+# CHECK: Vreg: %67[ LoopTag+42 ]
+# CHECK: Vreg: %3[ LoopTag+44 ]
+# CHECK: Vreg: %221[ 0 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+59 ]
+# CHECK: Vreg: %88[ 21 ]
+# CHECK: Vreg: %5[ 43 ]
+# CHECK: Vreg: %69[ LoopTag+42 ]
+# CHECK: Vreg: %95[ LoopTag+53 ]
+# CHECK: Vreg: %140[ 24 ]
+# CHECK: Vreg: %171[ 16 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: %223:vgpr_32 = V_MUL_LO_U32_e64 %222, %145, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+38 ]
+# CHECK: Vreg: %90[ LoopTag+43 ]
+# CHECK: Vreg: %71[ LoopTag+41 ]
+# CHECK: Vreg: %19[ 21 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+96 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+97 ]
+# CHECK: Vreg: %104[ 33 ]
+# CHECK: Vreg: %21[ LoopTag+36 ]
+# CHECK: Vreg: %149[ 17 ]
+# CHECK: Vreg: %40[ LoopTag+61 ]
+# CHECK: Vreg: %92[ LoopTag+46 ]
+# CHECK: Vreg: %73[ LoopTag+41 ]
+# CHECK: Vreg: %163[ 14 ]
+# CHECK: Vreg: %2[ LoopTag+57 ]
+# CHECK: Vreg: %23[ LoopTag+82 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %94[ LoopTag+49 ]
+# CHECK: Vreg: %30[ 32 ]
+# CHECK: Vreg: %151[ 17 ]
+# CHECK: Vreg: %18[ LoopTag+54 ]
+# CHECK: Vreg: %63[ LoopTag+34 ]
+# CHECK: Vreg: %37[ LoopTag+64 ]
+# CHECK: Vreg: %96[ LoopTag+56 ]
+# CHECK: Vreg: %58[ LoopTag+57 ]
+# CHECK: Vreg: %20[ LoopTag+32 ]
+# CHECK: Vreg: %1[ LoopTag+73 ]
+# CHECK: Vreg: %65[ LoopTag+41 ]
+# CHECK: Vreg: %155[ 18 ]
+# CHECK: Vreg: %143[ 22 ]
+# CHECK: Vreg: %60[ LoopTag+34 ]
+# CHECK: Vreg: %22[ LoopTag+49 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+72 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+73 ]
+# CHECK: Vreg: %67[ LoopTag+41 ]
+# CHECK: Vreg: %3[ LoopTag+43 ]
+# CHECK: Vreg: %222[ 0 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+58 ]
+# CHECK: Vreg: %88[ 20 ]
+# CHECK: Vreg: %5[ 42 ]
+# CHECK: Vreg: %69[ LoopTag+41 ]
+# CHECK: Vreg: %95[ LoopTag+52 ]
+# CHECK: Vreg: %140[ 23 ]
+# CHECK: Vreg: %171[ 15 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Instr: %224:vgpr_32 = V_SUB_U32_e64 %147, killed %223, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+37 ]
+# CHECK: Vreg: %90[ LoopTag+42 ]
+# CHECK: Vreg: %71[ LoopTag+40 ]
+# CHECK: Vreg: %19[ 20 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+95 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+96 ]
+# CHECK: Vreg: %104[ 32 ]
+# CHECK: Vreg: %21[ LoopTag+35 ]
+# CHECK: Vreg: %149[ 16 ]
+# CHECK: Vreg: %40[ LoopTag+60 ]
+# CHECK: Vreg: %92[ LoopTag+45 ]
+# CHECK: Vreg: %73[ LoopTag+40 ]
+# CHECK: Vreg: %163[ 13 ]
+# CHECK: Vreg: %2[ LoopTag+56 ]
+# CHECK: Vreg: %23[ LoopTag+81 ]
+# CHECK: Vreg: %4[ 10 ]
+# CHECK: Vreg: %94[ LoopTag+48 ]
+# CHECK: Vreg: %30[ 31 ]
+# CHECK: Vreg: %151[ 16 ]
+# CHECK: Vreg: %18[ LoopTag+53 ]
+# CHECK: Vreg: %63[ LoopTag+33 ]
+# CHECK: Vreg: %37[ LoopTag+63 ]
+# CHECK: Vreg: %96[ LoopTag+55 ]
+# CHECK: Vreg: %58[ LoopTag+56 ]
+# CHECK: Vreg: %20[ LoopTag+31 ]
+# CHECK: Vreg: %1[ LoopTag+72 ]
+# CHECK: Vreg: %65[ LoopTag+40 ]
+# CHECK: Vreg: %155[ 17 ]
+# CHECK: Vreg: %143[ 21 ]
+# CHECK: Vreg: %60[ LoopTag+33 ]
+# CHECK: Vreg: %22[ LoopTag+48 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+71 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+72 ]
+# CHECK: Vreg: %67[ LoopTag+40 ]
+# CHECK: Vreg: %3[ LoopTag+42 ]
+# CHECK: Vreg: %222[ 2 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+57 ]
+# CHECK: Vreg: %88[ 19 ]
+# CHECK: Vreg: %5[ 41 ]
+# CHECK: Vreg: %69[ LoopTag+40 ]
+# CHECK: Vreg: %95[ LoopTag+51 ]
+# CHECK: Vreg: %140[ 22 ]
+# CHECK: Vreg: %171[ 14 ]
+# CHECK: Vreg: %223[ 0 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: %225:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 %224, %145, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+36 ]
+# CHECK: Vreg: %90[ LoopTag+41 ]
+# CHECK: Vreg: %71[ LoopTag+39 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+94 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+95 ]
+# CHECK: Vreg: %104[ 31 ]
+# CHECK: Vreg: %21[ LoopTag+34 ]
+# CHECK: Vreg: %149[ 15 ]
+# CHECK: Vreg: %40[ LoopTag+59 ]
+# CHECK: Vreg: %92[ LoopTag+44 ]
+# CHECK: Vreg: %73[ LoopTag+39 ]
+# CHECK: Vreg: %163[ 12 ]
+# CHECK: Vreg: %2[ LoopTag+55 ]
+# CHECK: Vreg: %23[ LoopTag+80 ]
+# CHECK: Vreg: %4[ 9 ]
+# CHECK: Vreg: %94[ LoopTag+47 ]
+# CHECK: Vreg: %30[ 30 ]
+# CHECK: Vreg: %151[ 15 ]
+# CHECK: Vreg: %18[ LoopTag+52 ]
+# CHECK: Vreg: %63[ LoopTag+32 ]
+# CHECK: Vreg: %37[ LoopTag+62 ]
+# CHECK: Vreg: %96[ LoopTag+54 ]
+# CHECK: Vreg: %224[ 0 ]
+# CHECK: Vreg: %58[ LoopTag+55 ]
+# CHECK: Vreg: %20[ LoopTag+30 ]
+# CHECK: Vreg: %1[ LoopTag+71 ]
+# CHECK: Vreg: %65[ LoopTag+39 ]
+# CHECK: Vreg: %155[ 16 ]
+# CHECK: Vreg: %143[ 20 ]
+# CHECK: Vreg: %60[ LoopTag+32 ]
+# CHECK: Vreg: %22[ LoopTag+47 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+70 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+71 ]
+# CHECK: Vreg: %67[ LoopTag+39 ]
+# CHECK: Vreg: %3[ LoopTag+41 ]
+# CHECK: Vreg: %222[ 1 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+56 ]
+# CHECK: Vreg: %88[ 18 ]
+# CHECK: Vreg: %5[ 40 ]
+# CHECK: Vreg: %69[ LoopTag+39 ]
+# CHECK: Vreg: %95[ LoopTag+50 ]
+# CHECK: Vreg: %140[ 21 ]
+# CHECK: Vreg: %171[ 13 ]
+# CHECK: Vreg: %147[ 8 ]
+# CHECK: Instr: %226:vgpr_32 = V_ADD_U32_e64 1, %222, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+35 ]
+# CHECK: Vreg: %90[ LoopTag+40 ]
+# CHECK: Vreg: %71[ LoopTag+38 ]
+# CHECK: Vreg: %19[ 18 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+93 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+94 ]
+# CHECK: Vreg: %225[ 1 ]
+# CHECK: Vreg: %104[ 30 ]
+# CHECK: Vreg: %21[ LoopTag+33 ]
+# CHECK: Vreg: %149[ 14 ]
+# CHECK: Vreg: %40[ LoopTag+58 ]
+# CHECK: Vreg: %92[ LoopTag+43 ]
+# CHECK: Vreg: %73[ LoopTag+38 ]
+# CHECK: Vreg: %163[ 11 ]
+# CHECK: Vreg: %2[ LoopTag+54 ]
+# CHECK: Vreg: %23[ LoopTag+79 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %94[ LoopTag+46 ]
+# CHECK: Vreg: %30[ 29 ]
+# CHECK: Vreg: %151[ 14 ]
+# CHECK: Vreg: %18[ LoopTag+51 ]
+# CHECK: Vreg: %63[ LoopTag+31 ]
+# CHECK: Vreg: %37[ LoopTag+61 ]
+# CHECK: Vreg: %96[ LoopTag+53 ]
+# CHECK: Vreg: %224[ 2 ]
+# CHECK: Vreg: %58[ LoopTag+54 ]
+# CHECK: Vreg: %20[ LoopTag+29 ]
+# CHECK: Vreg: %1[ LoopTag+70 ]
+# CHECK: Vreg: %65[ LoopTag+38 ]
+# CHECK: Vreg: %155[ 15 ]
+# CHECK: Vreg: %143[ 19 ]
+# CHECK: Vreg: %60[ LoopTag+31 ]
+# CHECK: Vreg: %22[ LoopTag+46 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+69 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+70 ]
+# CHECK: Vreg: %67[ LoopTag+38 ]
+# CHECK: Vreg: %3[ LoopTag+40 ]
+# CHECK: Vreg: %222[ 0 ]
+# CHECK: Vreg: %145[ 2 ]
+# CHECK: Vreg: %43[ LoopTag+55 ]
+# CHECK: Vreg: %88[ 17 ]
+# CHECK: Vreg: %5[ 39 ]
+# CHECK: Vreg: %69[ LoopTag+38 ]
+# CHECK: Vreg: %95[ LoopTag+49 ]
+# CHECK: Vreg: %140[ 20 ]
+# CHECK: Vreg: %171[ 12 ]
+# CHECK: Vreg: %147[ 7 ]
+# CHECK: Instr: %227:vgpr_32 = V_CNDMASK_B32_e64 0, killed %222, 0, killed %226, %225, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+34 ]
+# CHECK: Vreg: %90[ LoopTag+39 ]
+# CHECK: Vreg: %71[ LoopTag+37 ]
+# CHECK: Vreg: %19[ 17 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+92 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+93 ]
+# CHECK: Vreg: %225[ 0 ]
+# CHECK: Vreg: %104[ 29 ]
+# CHECK: Vreg: %21[ LoopTag+32 ]
+# CHECK: Vreg: %149[ 13 ]
+# CHECK: Vreg: %40[ LoopTag+57 ]
+# CHECK: Vreg: %92[ LoopTag+42 ]
+# CHECK: Vreg: %73[ LoopTag+37 ]
+# CHECK: Vreg: %163[ 10 ]
+# CHECK: Vreg: %2[ LoopTag+53 ]
+# CHECK: Vreg: %23[ LoopTag+78 ]
+# CHECK: Vreg: %4[ 7 ]
+# CHECK: Vreg: %94[ LoopTag+45 ]
+# CHECK: Vreg: %30[ 28 ]
+# CHECK: Vreg: %151[ 13 ]
+# CHECK: Vreg: %18[ LoopTag+50 ]
+# CHECK: Vreg: %63[ LoopTag+30 ]
+# CHECK: Vreg: %37[ LoopTag+60 ]
+# CHECK: Vreg: %96[ LoopTag+52 ]
+# CHECK: Vreg: %224[ 1 ]
+# CHECK: Vreg: %58[ LoopTag+53 ]
+# CHECK: Vreg: %20[ LoopTag+28 ]
+# CHECK: Vreg: %1[ LoopTag+69 ]
+# CHECK: Vreg: %65[ LoopTag+37 ]
+# CHECK: Vreg: %155[ 14 ]
+# CHECK: Vreg: %226[ 0 ]
+# CHECK: Vreg: %143[ 18 ]
+# CHECK: Vreg: %60[ LoopTag+30 ]
+# CHECK: Vreg: %22[ LoopTag+45 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+68 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+69 ]
+# CHECK: Vreg: %67[ LoopTag+37 ]
+# CHECK: Vreg: %3[ LoopTag+39 ]
+# CHECK: Vreg: %222[ 0 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+54 ]
+# CHECK: Vreg: %88[ 16 ]
+# CHECK: Vreg: %5[ 38 ]
+# CHECK: Vreg: %69[ LoopTag+37 ]
+# CHECK: Vreg: %95[ LoopTag+48 ]
+# CHECK: Vreg: %140[ 19 ]
+# CHECK: Vreg: %171[ 11 ]
+# CHECK: Vreg: %147[ 6 ]
+# CHECK: Instr: %228:vgpr_32 = V_SUB_U32_e64 %224, %145, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+33 ]
+# CHECK: Vreg: %90[ LoopTag+38 ]
+# CHECK: Vreg: %71[ LoopTag+36 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+91 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+92 ]
+# CHECK: Vreg: %225[ 1 ]
+# CHECK: Vreg: %104[ 28 ]
+# CHECK: Vreg: %21[ LoopTag+31 ]
+# CHECK: Vreg: %149[ 12 ]
+# CHECK: Vreg: %40[ LoopTag+56 ]
+# CHECK: Vreg: %92[ LoopTag+41 ]
+# CHECK: Vreg: %73[ LoopTag+36 ]
+# CHECK: Vreg: %163[ 9 ]
+# CHECK: Vreg: %2[ LoopTag+52 ]
+# CHECK: Vreg: %227[ 3 ]
+# CHECK: Vreg: %23[ LoopTag+77 ]
+# CHECK: Vreg: %4[ 6 ]
+# CHECK: Vreg: %94[ LoopTag+44 ]
+# CHECK: Vreg: %30[ 27 ]
+# CHECK: Vreg: %151[ 12 ]
+# CHECK: Vreg: %18[ LoopTag+49 ]
+# CHECK: Vreg: %63[ LoopTag+29 ]
+# CHECK: Vreg: %37[ LoopTag+59 ]
+# CHECK: Vreg: %96[ LoopTag+51 ]
+# CHECK: Vreg: %224[ 0 ]
+# CHECK: Vreg: %58[ LoopTag+52 ]
+# CHECK: Vreg: %20[ LoopTag+27 ]
+# CHECK: Vreg: %1[ LoopTag+68 ]
+# CHECK: Vreg: %65[ LoopTag+36 ]
+# CHECK: Vreg: %155[ 13 ]
+# CHECK: Vreg: %143[ 17 ]
+# CHECK: Vreg: %60[ LoopTag+29 ]
+# CHECK: Vreg: %22[ LoopTag+44 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+67 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+68 ]
+# CHECK: Vreg: %67[ LoopTag+36 ]
+# CHECK: Vreg: %3[ LoopTag+38 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+53 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %69[ LoopTag+36 ]
+# CHECK: Vreg: %95[ LoopTag+47 ]
+# CHECK: Vreg: %140[ 18 ]
+# CHECK: Vreg: %171[ 10 ]
+# CHECK: Vreg: %147[ 5 ]
+# CHECK: Instr: %229:vgpr_32 = V_CNDMASK_B32_e64 0, killed %224, 0, killed %228, killed %225, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+32 ]
+# CHECK: Vreg: %90[ LoopTag+37 ]
+# CHECK: Vreg: %71[ LoopTag+35 ]
+# CHECK: Vreg: %19[ 15 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+90 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+91 ]
+# CHECK: Vreg: %225[ 0 ]
+# CHECK: Vreg: %104[ 27 ]
+# CHECK: Vreg: %21[ LoopTag+30 ]
+# CHECK: Vreg: %149[ 11 ]
+# CHECK: Vreg: %40[ LoopTag+55 ]
+# CHECK: Vreg: %92[ LoopTag+40 ]
+# CHECK: Vreg: %73[ LoopTag+35 ]
+# CHECK: Vreg: %163[ 8 ]
+# CHECK: Vreg: %2[ LoopTag+51 ]
+# CHECK: Vreg: %227[ 2 ]
+# CHECK: Vreg: %23[ LoopTag+76 ]
+# CHECK: Vreg: %4[ 5 ]
+# CHECK: Vreg: %94[ LoopTag+43 ]
+# CHECK: Vreg: %30[ 26 ]
+# CHECK: Vreg: %151[ 11 ]
+# CHECK: Vreg: %18[ LoopTag+48 ]
+# CHECK: Vreg: %63[ LoopTag+28 ]
+# CHECK: Vreg: %37[ LoopTag+58 ]
+# CHECK: Vreg: %96[ LoopTag+50 ]
+# CHECK: Vreg: %224[ 0 ]
+# CHECK: Vreg: %58[ LoopTag+51 ]
+# CHECK: Vreg: %20[ LoopTag+26 ]
+# CHECK: Vreg: %1[ LoopTag+67 ]
+# CHECK: Vreg: %65[ LoopTag+35 ]
+# CHECK: Vreg: %155[ 12 ]
+# CHECK: Vreg: %143[ 16 ]
+# CHECK: Vreg: %60[ LoopTag+28 ]
+# CHECK: Vreg: %22[ LoopTag+43 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+66 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+67 ]
+# CHECK: Vreg: %67[ LoopTag+35 ]
+# CHECK: Vreg: %3[ LoopTag+37 ]
+# CHECK: Vreg: %228[ 0 ]
+# CHECK: Vreg: %145[ 1 ]
+# CHECK: Vreg: %43[ LoopTag+52 ]
+# CHECK: Vreg: %88[ 14 ]
+# CHECK: Vreg: %5[ 36 ]
+# CHECK: Vreg: %69[ LoopTag+35 ]
+# CHECK: Vreg: %95[ LoopTag+46 ]
+# CHECK: Vreg: %140[ 17 ]
+# CHECK: Vreg: %171[ 9 ]
+# CHECK: Vreg: %147[ 4 ]
+# CHECK: Instr: %230:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 killed %229, %145, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+31 ]
+# CHECK: Vreg: %90[ LoopTag+36 ]
+# CHECK: Vreg: %71[ LoopTag+34 ]
+# CHECK: Vreg: %19[ 14 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+89 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+90 ]
+# CHECK: Vreg: %104[ 26 ]
+# CHECK: Vreg: %21[ LoopTag+29 ]
+# CHECK: Vreg: %149[ 10 ]
+# CHECK: Vreg: %40[ LoopTag+54 ]
+# CHECK: Vreg: %92[ LoopTag+39 ]
+# CHECK: Vreg: %73[ LoopTag+34 ]
+# CHECK: Vreg: %163[ 7 ]
+# CHECK: Vreg: %2[ LoopTag+50 ]
+# CHECK: Vreg: %227[ 1 ]
+# CHECK: Vreg: %23[ LoopTag+75 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %94[ LoopTag+42 ]
+# CHECK: Vreg: %30[ 25 ]
+# CHECK: Vreg: %151[ 10 ]
+# CHECK: Vreg: %18[ LoopTag+47 ]
+# CHECK: Vreg: %63[ LoopTag+27 ]
+# CHECK: Vreg: %37[ LoopTag+57 ]
+# CHECK: Vreg: %229[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+49 ]
+# CHECK: Vreg: %58[ LoopTag+50 ]
+# CHECK: Vreg: %20[ LoopTag+25 ]
+# CHECK: Vreg: %1[ LoopTag+66 ]
+# CHECK: Vreg: %65[ LoopTag+34 ]
+# CHECK: Vreg: %155[ 11 ]
+# CHECK: Vreg: %143[ 15 ]
+# CHECK: Vreg: %60[ LoopTag+27 ]
+# CHECK: Vreg: %22[ LoopTag+42 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+65 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+66 ]
+# CHECK: Vreg: %67[ LoopTag+34 ]
+# CHECK: Vreg: %3[ LoopTag+36 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+51 ]
+# CHECK: Vreg: %88[ 13 ]
+# CHECK: Vreg: %5[ 35 ]
+# CHECK: Vreg: %69[ LoopTag+34 ]
+# CHECK: Vreg: %95[ LoopTag+45 ]
+# CHECK: Vreg: %140[ 16 ]
+# CHECK: Vreg: %171[ 8 ]
+# CHECK: Vreg: %147[ 3 ]
+# CHECK: Instr: %231:vgpr_32 = V_ADD_U32_e64 1, %227, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+30 ]
+# CHECK: Vreg: %90[ LoopTag+35 ]
+# CHECK: Vreg: %71[ LoopTag+33 ]
+# CHECK: Vreg: %19[ 13 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+88 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+89 ]
+# CHECK: Vreg: %104[ 25 ]
+# CHECK: Vreg: %21[ LoopTag+28 ]
+# CHECK: Vreg: %149[ 9 ]
+# CHECK: Vreg: %40[ LoopTag+53 ]
+# CHECK: Vreg: %92[ LoopTag+38 ]
+# CHECK: Vreg: %73[ LoopTag+33 ]
+# CHECK: Vreg: %163[ 6 ]
+# CHECK: Vreg: %2[ LoopTag+49 ]
+# CHECK: Vreg: %227[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+74 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %94[ LoopTag+41 ]
+# CHECK: Vreg: %30[ 24 ]
+# CHECK: Vreg: %151[ 9 ]
+# CHECK: Vreg: %18[ LoopTag+46 ]
+# CHECK: Vreg: %63[ LoopTag+26 ]
+# CHECK: Vreg: %37[ LoopTag+56 ]
+# CHECK: Vreg: %96[ LoopTag+48 ]
+# CHECK: Vreg: %58[ LoopTag+49 ]
+# CHECK: Vreg: %20[ LoopTag+24 ]
+# CHECK: Vreg: %1[ LoopTag+65 ]
+# CHECK: Vreg: %65[ LoopTag+33 ]
+# CHECK: Vreg: %155[ 10 ]
+# CHECK: Vreg: %143[ 14 ]
+# CHECK: Vreg: %60[ LoopTag+26 ]
+# CHECK: Vreg: %22[ LoopTag+41 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+64 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+65 ]
+# CHECK: Vreg: %67[ LoopTag+33 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %145[ 9 ]
+# CHECK: Vreg: %43[ LoopTag+50 ]
+# CHECK: Vreg: %88[ 12 ]
+# CHECK: Vreg: %5[ 34 ]
+# CHECK: Vreg: %69[ LoopTag+33 ]
+# CHECK: Vreg: %95[ LoopTag+44 ]
+# CHECK: Vreg: %140[ 15 ]
+# CHECK: Vreg: %171[ 7 ]
+# CHECK: Vreg: %230[ 1 ]
+# CHECK: Vreg: %147[ 2 ]
+# CHECK: Instr: %165:vgpr_32 = V_CNDMASK_B32_e64 0, killed %227, 0, killed %231, killed %230, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+29 ]
+# CHECK: Vreg: %90[ LoopTag+34 ]
+# CHECK: Vreg: %71[ LoopTag+32 ]
+# CHECK: Vreg: %19[ 12 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+87 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+88 ]
+# CHECK: Vreg: %104[ 24 ]
+# CHECK: Vreg: %21[ LoopTag+27 ]
+# CHECK: Vreg: %149[ 8 ]
+# CHECK: Vreg: %40[ LoopTag+52 ]
+# CHECK: Vreg: %92[ LoopTag+37 ]
+# CHECK: Vreg: %73[ LoopTag+32 ]
+# CHECK: Vreg: %163[ 5 ]
+# CHECK: Vreg: %2[ LoopTag+48 ]
+# CHECK: Vreg: %227[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+73 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %94[ LoopTag+40 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %151[ 8 ]
+# CHECK: Vreg: %18[ LoopTag+45 ]
+# CHECK: Vreg: %63[ LoopTag+25 ]
+# CHECK: Vreg: %37[ LoopTag+55 ]
+# CHECK: Vreg: %96[ LoopTag+47 ]
+# CHECK: Vreg: %58[ LoopTag+48 ]
+# CHECK: Vreg: %231[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+23 ]
+# CHECK: Vreg: %1[ LoopTag+64 ]
+# CHECK: Vreg: %65[ LoopTag+32 ]
+# CHECK: Vreg: %155[ 9 ]
+# CHECK: Vreg: %143[ 13 ]
+# CHECK: Vreg: %60[ LoopTag+25 ]
+# CHECK: Vreg: %22[ LoopTag+40 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+63 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+64 ]
+# CHECK: Vreg: %67[ LoopTag+32 ]
+# CHECK: Vreg: %3[ LoopTag+34 ]
+# CHECK: Vreg: %145[ 8 ]
+# CHECK: Vreg: %43[ LoopTag+49 ]
+# CHECK: Vreg: %88[ 11 ]
+# CHECK: Vreg: %5[ 33 ]
+# CHECK: Vreg: %69[ LoopTag+32 ]
+# CHECK: Vreg: %95[ LoopTag+43 ]
+# CHECK: Vreg: %140[ 14 ]
+# CHECK: Vreg: %171[ 6 ]
+# CHECK: Vreg: %230[ 0 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Instr: %167:vgpr_32 = V_ADD_U32_e64 1, %147, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+28 ]
+# CHECK: Vreg: %90[ LoopTag+33 ]
+# CHECK: Vreg: %71[ LoopTag+31 ]
+# CHECK: Vreg: %19[ 11 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+86 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+87 ]
+# CHECK: Vreg: %104[ 23 ]
+# CHECK: Vreg: %21[ LoopTag+26 ]
+# CHECK: Vreg: %149[ 7 ]
+# CHECK: Vreg: %40[ LoopTag+51 ]
+# CHECK: Vreg: %92[ LoopTag+36 ]
+# CHECK: Vreg: %73[ LoopTag+31 ]
+# CHECK: Vreg: %163[ 4 ]
+# CHECK: Vreg: %2[ LoopTag+47 ]
+# CHECK: Vreg: %23[ LoopTag+72 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %94[ LoopTag+39 ]
+# CHECK: Vreg: %30[ 22 ]
+# CHECK: Vreg: %151[ 7 ]
+# CHECK: Vreg: %18[ LoopTag+44 ]
+# CHECK: Vreg: %63[ LoopTag+24 ]
+# CHECK: Vreg: %37[ LoopTag+54 ]
+# CHECK: Vreg: %165[ 4 ]
+# CHECK: Vreg: %96[ LoopTag+46 ]
+# CHECK: Vreg: %58[ LoopTag+47 ]
+# CHECK: Vreg: %20[ LoopTag+22 ]
+# CHECK: Vreg: %1[ LoopTag+63 ]
+# CHECK: Vreg: %65[ LoopTag+31 ]
+# CHECK: Vreg: %155[ 8 ]
+# CHECK: Vreg: %143[ 12 ]
+# CHECK: Vreg: %60[ LoopTag+24 ]
+# CHECK: Vreg: %22[ LoopTag+39 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+62 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+63 ]
+# CHECK: Vreg: %67[ LoopTag+31 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %145[ 7 ]
+# CHECK: Vreg: %43[ LoopTag+48 ]
+# CHECK: Vreg: %88[ 10 ]
+# CHECK: Vreg: %5[ 32 ]
+# CHECK: Vreg: %69[ LoopTag+31 ]
+# CHECK: Vreg: %95[ LoopTag+42 ]
+# CHECK: Vreg: %140[ 13 ]
+# CHECK: Vreg: %171[ 5 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: %232:sreg_32 = V_CMP_GE_U32_e64 %167, %4, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+27 ]
+# CHECK: Vreg: %90[ LoopTag+32 ]
+# CHECK: Vreg: %71[ LoopTag+30 ]
+# CHECK: Vreg: %19[ 10 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+85 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+86 ]
+# CHECK: Vreg: %104[ 22 ]
+# CHECK: Vreg: %21[ LoopTag+25 ]
+# CHECK: Vreg: %149[ 6 ]
+# CHECK: Vreg: %40[ LoopTag+50 ]
+# CHECK: Vreg: %92[ LoopTag+35 ]
+# CHECK: Vreg: %73[ LoopTag+30 ]
+# CHECK: Vreg: %163[ 3 ]
+# CHECK: Vreg: %2[ LoopTag+46 ]
+# CHECK: Vreg: %23[ LoopTag+71 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %94[ LoopTag+38 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %151[ 6 ]
+# CHECK: Vreg: %18[ LoopTag+43 ]
+# CHECK: Vreg: %63[ LoopTag+23 ]
+# CHECK: Vreg: %37[ LoopTag+53 ]
+# CHECK: Vreg: %165[ 3 ]
+# CHECK: Vreg: %96[ LoopTag+45 ]
+# CHECK: Vreg: %58[ LoopTag+46 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+21 ]
+# CHECK: Vreg: %1[ LoopTag+62 ]
+# CHECK: Vreg: %65[ LoopTag+30 ]
+# CHECK: Vreg: %155[ 7 ]
+# CHECK: Vreg: %143[ 11 ]
+# CHECK: Vreg: %60[ LoopTag+23 ]
+# CHECK: Vreg: %22[ LoopTag+38 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+61 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+62 ]
+# CHECK: Vreg: %67[ LoopTag+30 ]
+# CHECK: Vreg: %3[ LoopTag+32 ]
+# CHECK: Vreg: %145[ 6 ]
+# CHECK: Vreg: %43[ LoopTag+47 ]
+# CHECK: Vreg: %88[ 9 ]
+# CHECK: Vreg: %5[ 31 ]
+# CHECK: Vreg: %69[ LoopTag+30 ]
+# CHECK: Vreg: %95[ LoopTag+41 ]
+# CHECK: Vreg: %140[ 12 ]
+# CHECK: Vreg: %171[ 4 ]
+# CHECK: Vreg: %147[ 3 ]
+# CHECK: Instr: %160:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+26 ]
+# CHECK: Vreg: %90[ LoopTag+31 ]
+# CHECK: Vreg: %71[ LoopTag+29 ]
+# CHECK: Vreg: %19[ 9 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+84 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+85 ]
+# CHECK: Vreg: %104[ 21 ]
+# CHECK: Vreg: %21[ LoopTag+24 ]
+# CHECK: Vreg: %149[ 5 ]
+# CHECK: Vreg: %40[ LoopTag+49 ]
+# CHECK: Vreg: %92[ LoopTag+34 ]
+# CHECK: Vreg: %73[ LoopTag+29 ]
+# CHECK: Vreg: %232[ 1 ]
+# CHECK: Vreg: %163[ 2 ]
+# CHECK: Vreg: %2[ LoopTag+45 ]
+# CHECK: Vreg: %23[ LoopTag+70 ]
+# CHECK: Vreg: %4[ 46 ]
+# CHECK: Vreg: %94[ LoopTag+37 ]
+# CHECK: Vreg: %30[ 20 ]
+# CHECK: Vreg: %151[ 5 ]
+# CHECK: Vreg: %18[ LoopTag+42 ]
+# CHECK: Vreg: %63[ LoopTag+22 ]
+# CHECK: Vreg: %37[ LoopTag+52 ]
+# CHECK: Vreg: %165[ 2 ]
+# CHECK: Vreg: %96[ LoopTag+44 ]
+# CHECK: Vreg: %58[ LoopTag+45 ]
+# CHECK: Vreg: %167[ 2 ]
+# CHECK: Vreg: %20[ LoopTag+20 ]
+# CHECK: Vreg: %1[ LoopTag+61 ]
+# CHECK: Vreg: %65[ LoopTag+29 ]
+# CHECK: Vreg: %155[ 6 ]
+# CHECK: Vreg: %143[ 10 ]
+# CHECK: Vreg: %60[ LoopTag+22 ]
+# CHECK: Vreg: %22[ LoopTag+37 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+60 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+61 ]
+# CHECK: Vreg: %67[ LoopTag+29 ]
+# CHECK: Vreg: %3[ LoopTag+31 ]
+# CHECK: Vreg: %145[ 5 ]
+# CHECK: Vreg: %43[ LoopTag+46 ]
+# CHECK: Vreg: %88[ 8 ]
+# CHECK: Vreg: %5[ 30 ]
+# CHECK: Vreg: %69[ LoopTag+29 ]
+# CHECK: Vreg: %95[ LoopTag+40 ]
+# CHECK: Vreg: %140[ 11 ]
+# CHECK: Vreg: %171[ 3 ]
+# CHECK: Vreg: %147[ 2 ]
+# CHECK: Instr: %158:sreg_32 = S_ORN2_B32 killed %232, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %90[ LoopTag+30 ]
+# CHECK: Vreg: %71[ LoopTag+28 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+83 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+84 ]
+# CHECK: Vreg: %104[ 20 ]
+# CHECK: Vreg: %21[ LoopTag+23 ]
+# CHECK: Vreg: %149[ 4 ]
+# CHECK: Vreg: %40[ LoopTag+48 ]
+# CHECK: Vreg: %92[ LoopTag+33 ]
+# CHECK: Vreg: %73[ LoopTag+28 ]
+# CHECK: Vreg: %232[ 0 ]
+# CHECK: Vreg: %163[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+44 ]
+# CHECK: Vreg: %23[ LoopTag+69 ]
+# CHECK: Vreg: %4[ 45 ]
+# CHECK: Vreg: %94[ LoopTag+36 ]
+# CHECK: Vreg: %30[ 19 ]
+# CHECK: Vreg: %151[ 4 ]
+# CHECK: Vreg: %18[ LoopTag+41 ]
+# CHECK: Vreg: %63[ LoopTag+21 ]
+# CHECK: Vreg: %37[ LoopTag+51 ]
+# CHECK: Vreg: %165[ 1 ]
+# CHECK: Vreg: %96[ LoopTag+43 ]
+# CHECK: Vreg: %160[ 1 ]
+# CHECK: Vreg: %58[ LoopTag+44 ]
+# CHECK: Vreg: %167[ 1 ]
+# CHECK: Vreg: %20[ LoopTag+19 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %65[ LoopTag+28 ]
+# CHECK: Vreg: %155[ 5 ]
+# CHECK: Vreg: %143[ 9 ]
+# CHECK: Vreg: %60[ LoopTag+21 ]
+# CHECK: Vreg: %22[ LoopTag+36 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+59 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+60 ]
+# CHECK: Vreg: %67[ LoopTag+28 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %145[ 4 ]
+# CHECK: Vreg: %43[ LoopTag+45 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ LoopTag+28 ]
+# CHECK: Vreg: %95[ LoopTag+39 ]
+# CHECK: Vreg: %140[ 10 ]
+# CHECK: Vreg: %171[ 2 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %165[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %160[ 0 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %158[ 0 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %90[ LoopTag+29 ]
+# CHECK: Vreg: %71[ LoopTag+27 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+82 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+83 ]
+# CHECK: Vreg: %104[ 19 ]
+# CHECK: Vreg: %21[ LoopTag+22 ]
+# CHECK: Vreg: %149[ 3 ]
+# CHECK: Vreg: %40[ LoopTag+47 ]
+# CHECK: Vreg: %92[ LoopTag+32 ]
+# CHECK: Vreg: %73[ LoopTag+27 ]
+# CHECK: Vreg: %163[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %23[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %94[ LoopTag+35 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %151[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+40 ]
+# CHECK: Vreg: %63[ LoopTag+20 ]
+# CHECK: Vreg: %37[ LoopTag+50 ]
+# CHECK: Vreg: %165[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+42 ]
+# CHECK: Vreg: %160[ 0 ]
+# CHECK: Vreg: %58[ LoopTag+43 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %65[ LoopTag+27 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %143[ 8 ]
+# CHECK: Vreg: %60[ LoopTag+20 ]
+# CHECK: Vreg: %22[ LoopTag+35 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+58 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+59 ]
+# CHECK: Vreg: %67[ LoopTag+27 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %158[ 0 ]
+# CHECK: Vreg: %145[ 3 ]
+# CHECK: Vreg: %43[ LoopTag+44 ]
+# CHECK: Vreg: %88[ 6 ]
+# CHECK: Vreg: %5[ 28 ]
+# CHECK: Vreg: %69[ LoopTag+27 ]
+# CHECK: Vreg: %95[ LoopTag+38 ]
+# CHECK: Vreg: %140[ 9 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: --- MBB_10 ---
+# CHECK: Instr: %233:sreg_32 = PHI %234, %bb.38, %235, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %90[ 12 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %244[ 2 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %246[ 4 ]
+# CHECK: Vreg: %234[ 0 ]
+# CHECK: Vreg: %23[ 51 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %241[ 0 ]
+# CHECK: Vreg: %94[ 18 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %37[ 33 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %96[ 25 ]
+# CHECK: Vreg: %58[ 26 ]
+# CHECK: Vreg: %250[ 6 ]
+# CHECK: Vreg: %20[ 13 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %238[ 0 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %22:sub0[ 41 ]
+# CHECK: Vreg: %22:sub1[ 42 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %247[ 4 ]
+# CHECK: Vreg: %43[ 27 ]
+# CHECK: Vreg: %235[ 0 ]
+# CHECK: Vreg: %5[ 99 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 21 ]
+# CHECK: Vreg: %249[ 6 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Vreg: %19:sub0[ 65 ]
+# CHECK: Vreg: %19:sub1[ 66 ]
+# CHECK: Instr: %236:vgpr_32 = PHI undef %237:vgpr_32, %bb.38, %238, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %90[ 12 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %244[ 2 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %246[ 4 ]
+# CHECK: Vreg: %234[ 3 ]
+# CHECK: Vreg: %23[ 51 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %241[ 0 ]
+# CHECK: Vreg: %94[ 18 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %37[ 33 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %96[ 25 ]
+# CHECK: Vreg: %58[ 26 ]
+# CHECK: Vreg: %250[ 6 ]
+# CHECK: Vreg: %20[ 13 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %238[ 0 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %233[ 3 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %22:sub0[ 41 ]
+# CHECK: Vreg: %22:sub1[ 42 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %247[ 4 ]
+# CHECK: Vreg: %43[ 27 ]
+# CHECK: Vreg: %5[ 99 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 21 ]
+# CHECK: Vreg: %249[ 6 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Vreg: %19:sub0[ 65 ]
+# CHECK: Vreg: %19:sub1[ 66 ]
+# CHECK: Instr: %239:sreg_32 = PHI undef %240:sreg_32, %bb.38, %241, %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %90[ 12 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %244[ 2 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %246[ 4 ]
+# CHECK: Vreg: %234[ 3 ]
+# CHECK: Vreg: %23[ 51 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %241[ 0 ]
+# CHECK: Vreg: %94[ 18 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %37[ 33 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %236[ 3 ]
+# CHECK: Vreg: %96[ 25 ]
+# CHECK: Vreg: %58[ 26 ]
+# CHECK: Vreg: %250[ 6 ]
+# CHECK: Vreg: %20[ 13 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %233[ 3 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %22:sub0[ 41 ]
+# CHECK: Vreg: %22:sub1[ 42 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %247[ 4 ]
+# CHECK: Vreg: %43[ 27 ]
+# CHECK: Vreg: %5[ 99 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 21 ]
+# CHECK: Vreg: %249[ 6 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Vreg: %19:sub0[ 65 ]
+# CHECK: Vreg: %19:sub1[ 66 ]
+# CHECK: Instr: %242:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %90[ 11 ]
+# CHECK: Vreg: %71[ 9 ]
+# CHECK: Vreg: %244[ 1 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %2[ 25 ]
+# CHECK: Vreg: %239[ 2 ]
+# CHECK: Vreg: %92[ 14 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %246[ 3 ]
+# CHECK: Vreg: %234[ 2 ]
+# CHECK: Vreg: %23[ 50 ]
+# CHECK: Vreg: %4[ 100 ]
+# CHECK: Vreg: %94[ 17 ]
+# CHECK: Vreg: %30[ 74 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %18[ 22 ]
+# CHECK: Vreg: %63[ 2 ]
+# CHECK: Vreg: %236[ 2 ]
+# CHECK: Vreg: %96[ 24 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %250[ 5 ]
+# CHECK: Vreg: %20[ 12 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %60[ 2 ]
+# CHECK: Vreg: %233[ 2 ]
+# CHECK: Vreg: %22[ 17 ]
+# CHECK: Vreg: %22:sub0[ 40 ]
+# CHECK: Vreg: %22:sub1[ 41 ]
+# CHECK: Vreg: %3[ 11 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %247[ 3 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 98 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %95[ 20 ]
+# CHECK: Vreg: %249[ 5 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ 64 ]
+# CHECK: Vreg: %19:sub1[ 65 ]
+# CHECK: Instr: %243:sreg_32 = SI_ELSE killed %244, %bb.12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %90[ 10 ]
+# CHECK: Vreg: %71[ 8 ]
+# CHECK: Vreg: %242[ 1 ]
+# CHECK: Vreg: %244[ 0 ]
+# CHECK: Vreg: %40[ 28 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %2[ 24 ]
+# CHECK: Vreg: %239[ 1 ]
+# CHECK: Vreg: %92[ 13 ]
+# CHECK: Vreg: %73[ 8 ]
+# CHECK: Vreg: %246[ 2 ]
+# CHECK: Vreg: %234[ 1 ]
+# CHECK: Vreg: %23[ 49 ]
+# CHECK: Vreg: %4[ 99 ]
+# CHECK: Vreg: %94[ 16 ]
+# CHECK: Vreg: %30[ 73 ]
+# CHECK: Vreg: %37[ 31 ]
+# CHECK: Vreg: %18[ 21 ]
+# CHECK: Vreg: %63[ 1 ]
+# CHECK: Vreg: %236[ 1 ]
+# CHECK: Vreg: %96[ 23 ]
+# CHECK: Vreg: %58[ 24 ]
+# CHECK: Vreg: %250[ 4 ]
+# CHECK: Vreg: %20[ 11 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %60[ 1 ]
+# CHECK: Vreg: %233[ 1 ]
+# CHECK: Vreg: %22[ 16 ]
+# CHECK: Vreg: %22:sub0[ 39 ]
+# CHECK: Vreg: %22:sub1[ 40 ]
+# CHECK: Vreg: %3[ 10 ]
+# CHECK: Vreg: %67[ 8 ]
+# CHECK: Vreg: %247[ 2 ]
+# CHECK: Vreg: %43[ 25 ]
+# CHECK: Vreg: %5[ 97 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %95[ 19 ]
+# CHECK: Vreg: %249[ 4 ]
+# CHECK: Vreg: %19[ 3 ]
+# CHECK: Vreg: %19:sub0[ 63 ]
+# CHECK: Vreg: %19:sub1[ 64 ]
+# CHECK: Instr: S_BRANCH %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 7 ]
+# CHECK: Vreg: %242[ 0 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %239[ 0 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 7 ]
+# CHECK: Vreg: %246[ 1 ]
+# CHECK: Vreg: %234[ 0 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %250[ 3 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %233[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %67[ 7 ]
+# CHECK: Vreg: %247[ 1 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %249[ 3 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 7 ]
+# CHECK: Vreg: %242[ 0 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %239[ 0 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 7 ]
+# CHECK: Vreg: %246[ 1 ]
+# CHECK: Vreg: %234[ 0 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %250[ 3 ]
+# CHECK: Vreg: %20[ 10 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %233[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %67[ 7 ]
+# CHECK: Vreg: %247[ 1 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %249[ 3 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: --- MBB_11 ---
+# CHECK: Instr: %245:vgpr_32 = V_MUL_LO_U32_e64 killed %246, killed %247, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %90[ 27 ]
+# CHECK: Vreg: %71[ 6 ]
+# CHECK: Vreg: %40[ 45 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %2[ 41 ]
+# CHECK: Vreg: %239[ 10 ]
+# CHECK: Vreg: %92[ 30 ]
+# CHECK: Vreg: %73[ 6 ]
+# CHECK: Vreg: %246[ 0 ]
+# CHECK: Vreg: %23[ 66 ]
+# CHECK: Vreg: %4[ 116 ]
+# CHECK: Vreg: %94[ 33 ]
+# CHECK: Vreg: %30[ 90 ]
+# CHECK: Vreg: %37[ 48 ]
+# CHECK: Vreg: %18[ 38 ]
+# CHECK: Vreg: %243[ 19 ]
+# CHECK: Vreg: %96[ 40 ]
+# CHECK: Vreg: %58[ 41 ]
+# CHECK: Vreg: %250[ 2 ]
+# CHECK: Vreg: %20[ 9 ]
+# CHECK: Vreg: %1[ 57 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %60[ 6 ]
+# CHECK: Vreg: %233[ 6 ]
+# CHECK: Vreg: %22[ 33 ]
+# CHECK: Vreg: %22:sub0[ 56 ]
+# CHECK: Vreg: %22:sub1[ 57 ]
+# CHECK: Vreg: %3[ 27 ]
+# CHECK: Vreg: %67[ 6 ]
+# CHECK: Vreg: %247[ 0 ]
+# CHECK: Vreg: %43[ 42 ]
+# CHECK: Vreg: %5[ 114 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %95[ 36 ]
+# CHECK: Vreg: %249[ 2 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %19, %245, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %90[ 26 ]
+# CHECK: Vreg: %71[ 5 ]
+# CHECK: Vreg: %40[ 44 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %2[ 40 ]
+# CHECK: Vreg: %239[ 9 ]
+# CHECK: Vreg: %92[ 29 ]
+# CHECK: Vreg: %73[ 5 ]
+# CHECK: Vreg: %23[ 65 ]
+# CHECK: Vreg: %4[ 115 ]
+# CHECK: Vreg: %94[ 32 ]
+# CHECK: Vreg: %30[ 89 ]
+# CHECK: Vreg: %37[ 47 ]
+# CHECK: Vreg: %18[ 37 ]
+# CHECK: Vreg: %243[ 18 ]
+# CHECK: Vreg: %96[ 39 ]
+# CHECK: Vreg: %58[ 40 ]
+# CHECK: Vreg: %250[ 1 ]
+# CHECK: Vreg: %20[ 8 ]
+# CHECK: Vreg: %1[ 56 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %245[ 0 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %233[ 5 ]
+# CHECK: Vreg: %22[ 32 ]
+# CHECK: Vreg: %22:sub0[ 55 ]
+# CHECK: Vreg: %22:sub1[ 56 ]
+# CHECK: Vreg: %3[ 26 ]
+# CHECK: Vreg: %67[ 5 ]
+# CHECK: Vreg: %43[ 41 ]
+# CHECK: Vreg: %5[ 113 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %95[ 35 ]
+# CHECK: Vreg: %249[ 1 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %248:vgpr_32 = V_MUL_LO_U32_e64 %249, killed %250, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %90[ 25 ]
+# CHECK: Vreg: %71[ 4 ]
+# CHECK: Vreg: %40[ 43 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %2[ 39 ]
+# CHECK: Vreg: %239[ 8 ]
+# CHECK: Vreg: %92[ 28 ]
+# CHECK: Vreg: %73[ 4 ]
+# CHECK: Vreg: %23[ 64 ]
+# CHECK: Vreg: %4[ 114 ]
+# CHECK: Vreg: %94[ 31 ]
+# CHECK: Vreg: %30[ 88 ]
+# CHECK: Vreg: %37[ 46 ]
+# CHECK: Vreg: %18[ 36 ]
+# CHECK: Vreg: %243[ 17 ]
+# CHECK: Vreg: %96[ 38 ]
+# CHECK: Vreg: %58[ 39 ]
+# CHECK: Vreg: %250[ 0 ]
+# CHECK: Vreg: %20[ 7 ]
+# CHECK: Vreg: %1[ 55 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %245[ 1 ]
+# CHECK: Vreg: %60[ 4 ]
+# CHECK: Vreg: %233[ 4 ]
+# CHECK: Vreg: %22[ 31 ]
+# CHECK: Vreg: %22:sub0[ 54 ]
+# CHECK: Vreg: %22:sub1[ 55 ]
+# CHECK: Vreg: %3[ 25 ]
+# CHECK: Vreg: %67[ 4 ]
+# CHECK: Vreg: %43[ 40 ]
+# CHECK: Vreg: %5[ 112 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %95[ 34 ]
+# CHECK: Vreg: %249[ 0 ]
+# CHECK: Vreg: %19[ 23 ]
+# CHECK: Vreg: %19:sub0[ 78 ]
+# CHECK: Vreg: %19:sub1[ 79 ]
+# CHECK: Instr: %251:sreg_32 = V_CMP_LT_U32_e64 %245, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %90[ 24 ]
+# CHECK: Vreg: %71[ 3 ]
+# CHECK: Vreg: %40[ 42 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %2[ 38 ]
+# CHECK: Vreg: %239[ 7 ]
+# CHECK: Vreg: %92[ 27 ]
+# CHECK: Vreg: %73[ 3 ]
+# CHECK: Vreg: %23[ 63 ]
+# CHECK: Vreg: %4[ 113 ]
+# CHECK: Vreg: %94[ 30 ]
+# CHECK: Vreg: %30[ 87 ]
+# CHECK: Vreg: %248[ 15 ]
+# CHECK: Vreg: %37[ 45 ]
+# CHECK: Vreg: %18[ 35 ]
+# CHECK: Vreg: %243[ 16 ]
+# CHECK: Vreg: %96[ 37 ]
+# CHECK: Vreg: %58[ 38 ]
+# CHECK: Vreg: %20[ 6 ]
+# CHECK: Vreg: %1[ 54 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %245[ 0 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %233[ 3 ]
+# CHECK: Vreg: %22[ 30 ]
+# CHECK: Vreg: %22:sub0[ 53 ]
+# CHECK: Vreg: %22:sub1[ 54 ]
+# CHECK: Vreg: %3[ 24 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %43[ 39 ]
+# CHECK: Vreg: %5[ 111 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %95[ 33 ]
+# CHECK: Vreg: %249[ 48 ]
+# CHECK: Vreg: %19[ 22 ]
+# CHECK: Vreg: %19:sub0[ 77 ]
+# CHECK: Vreg: %19:sub1[ 78 ]
+# CHECK: Instr: %252:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 106 ]
+# CHECK: Vreg: %90[ 23 ]
+# CHECK: Vreg: %71[ 2 ]
+# CHECK: Vreg: %251[ 1 ]
+# CHECK: Vreg: %40[ 41 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 37 ]
+# CHECK: Vreg: %239[ 6 ]
+# CHECK: Vreg: %92[ 26 ]
+# CHECK: Vreg: %73[ 2 ]
+# CHECK: Vreg: %23[ 62 ]
+# CHECK: Vreg: %4[ 112 ]
+# CHECK: Vreg: %94[ 29 ]
+# CHECK: Vreg: %30[ 86 ]
+# CHECK: Vreg: %248[ 14 ]
+# CHECK: Vreg: %37[ 44 ]
+# CHECK: Vreg: %18[ 34 ]
+# CHECK: Vreg: %243[ 15 ]
+# CHECK: Vreg: %96[ 36 ]
+# CHECK: Vreg: %58[ 37 ]
+# CHECK: Vreg: %20[ 5 ]
+# CHECK: Vreg: %1[ 53 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %245[ 5 ]
+# CHECK: Vreg: %60[ 2 ]
+# CHECK: Vreg: %233[ 2 ]
+# CHECK: Vreg: %22[ 29 ]
+# CHECK: Vreg: %22:sub0[ 52 ]
+# CHECK: Vreg: %22:sub1[ 53 ]
+# CHECK: Vreg: %3[ 23 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %43[ 38 ]
+# CHECK: Vreg: %5[ 110 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %95[ 32 ]
+# CHECK: Vreg: %249[ 47 ]
+# CHECK: Vreg: %19[ 21 ]
+# CHECK: Vreg: %19:sub0[ 76 ]
+# CHECK: Vreg: %19:sub1[ 77 ]
+# CHECK: Instr: %253:sreg_32 = SI_IF killed %251, %bb.15, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 105 ]
+# CHECK: Vreg: %90[ 22 ]
+# CHECK: Vreg: %71[ 1 ]
+# CHECK: Vreg: %251[ 0 ]
+# CHECK: Vreg: %40[ 40 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %2[ 36 ]
+# CHECK: Vreg: %239[ 5 ]
+# CHECK: Vreg: %92[ 25 ]
+# CHECK: Vreg: %73[ 1 ]
+# CHECK: Vreg: %23[ 61 ]
+# CHECK: Vreg: %4[ 111 ]
+# CHECK: Vreg: %94[ 28 ]
+# CHECK: Vreg: %30[ 85 ]
+# CHECK: Vreg: %248[ 13 ]
+# CHECK: Vreg: %37[ 43 ]
+# CHECK: Vreg: %18[ 33 ]
+# CHECK: Vreg: %243[ 14 ]
+# CHECK: Vreg: %96[ 35 ]
+# CHECK: Vreg: %58[ 36 ]
+# CHECK: Vreg: %20[ 4 ]
+# CHECK: Vreg: %1[ 52 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %245[ 4 ]
+# CHECK: Vreg: %60[ 1 ]
+# CHECK: Vreg: %233[ 1 ]
+# CHECK: Vreg: %22[ 28 ]
+# CHECK: Vreg: %22:sub0[ 51 ]
+# CHECK: Vreg: %22:sub1[ 52 ]
+# CHECK: Vreg: %3[ 22 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %252[ 1 ]
+# CHECK: Vreg: %43[ 37 ]
+# CHECK: Vreg: %5[ 109 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %95[ 31 ]
+# CHECK: Vreg: %249[ 46 ]
+# CHECK: Vreg: %19[ 20 ]
+# CHECK: Vreg: %19:sub0[ 75 ]
+# CHECK: Vreg: %19:sub1[ 76 ]
+# CHECK: Instr: S_BRANCH %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %20[ 3 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %245[ 3 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %233[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %252[ 0 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %20[ 3 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %245[ 3 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %233[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %252[ 0 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: --- MBB_12 ---
+# CHECK: Instr: %254:sreg_32 = PHI %233, %bb.10, %255, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %263[ 0 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %239[ 0 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %267[ 0 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %257[ 0 ]
+# CHECK: Vreg: %264[ 0 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %233[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %261[ 0 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %234[ 0 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %255[ 0 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %259[ 0 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %242[ 0 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Instr: %256:sreg_32 = PHI %234, %bb.10, %257, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %263[ 0 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %239[ 0 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %267[ 0 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %257[ 0 ]
+# CHECK: Vreg: %264[ 0 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %261[ 0 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %234[ 0 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %259[ 0 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %242[ 0 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Instr: %258:sreg_32 = PHI %239, %bb.10, %259, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %263[ 0 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %239[ 0 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %267[ 0 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %264[ 0 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %261[ 0 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %234[ 0 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %259[ 0 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %242[ 0 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Instr: %260:sreg_32 = PHI %242, %bb.10, %261, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %263[ 0 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %261[ 0 ]
+# CHECK: Vreg: %234[ 0 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %264[ 0 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %267[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %242[ 0 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Instr: %262:sreg_32 = PHI %234, %bb.10, %263, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %263[ 0 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %234[ 0 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %264[ 0 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %267[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %242[ 4 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Instr: %111:vgpr_32 = PHI %60, %bb.10, %264, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %242[ 4 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %264[ 0 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %267[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Instr: %112:vgpr_32 = PHI %63, %bb.10, %248, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %242[ 4 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %111[ 19 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %267[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Instr: %265:vgpr_32 = PHI undef %266:vgpr_32, %bb.10, %267, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %242[ 4 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %111[ 19 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %267[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %112[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Instr: %268:vgpr_32 = PHI undef %266:vgpr_32, %bb.10, %269, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %242[ 4 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %111[ 19 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %265[ 4 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %112[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Instr: %270:vgpr_32 = PHI undef %266:vgpr_32, %bb.10, %271, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %242[ 4 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %111[ 19 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %265[ 4 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %112[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %268[ 4 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Instr: %272:vgpr_32 = PHI undef %266:vgpr_32, %bb.10, %273, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %242[ 4 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %270[ 4 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %111[ 19 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %265[ 4 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %112[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %268[ 4 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Instr: %274:vgpr_32 = PHI undef %266:vgpr_32, %bb.10, %275, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %242[ 4 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %270[ 4 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %111[ 19 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %265[ 4 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %272[ 4 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %112[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %268[ 4 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Instr: %276:vgpr_32 = PHI undef %277:vgpr_32, %bb.10, %248, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %242[ 4 ]
+# CHECK: Vreg: %270[ 4 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %111[ 19 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %265[ 4 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %272[ 4 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %274[ 4 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %112[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %268[ 4 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Instr: %278:vgpr_32 = PHI %236, %bb.10, %279, %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %242[ 4 ]
+# CHECK: Vreg: %270[ 4 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %111[ 19 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %265[ 4 ]
+# CHECK: Vreg: %258[ 6 ]
+# CHECK: Vreg: %272[ 4 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %274[ 4 ]
+# CHECK: Vreg: %236[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %276[ 7 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %112[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %254[ 3 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %268[ 4 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Instr: SI_END_CF killed %243, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 91 ]
+# CHECK: Vreg: %256[ 3 ]
+# CHECK: Vreg: %90[ 8 ]
+# CHECK: Vreg: %71[ 18 ]
+# CHECK: Vreg: %242[ 3 ]
+# CHECK: Vreg: %270[ 3 ]
+# CHECK: Vreg: %40[ 26 ]
+# CHECK: Vreg: %21[ 89 ]
+# CHECK: Vreg: %2[ 22 ]
+# CHECK: Vreg: %111[ 18 ]
+# CHECK: Vreg: %92[ 11 ]
+# CHECK: Vreg: %73[ 18 ]
+# CHECK: Vreg: %265[ 3 ]
+# CHECK: Vreg: %258[ 5 ]
+# CHECK: Vreg: %272[ 3 ]
+# CHECK: Vreg: %23[ 47 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %260[ 3 ]
+# CHECK: Vreg: %94[ 14 ]
+# CHECK: Vreg: %30[ 71 ]
+# CHECK: Vreg: %37[ 29 ]
+# CHECK: Vreg: %18[ 19 ]
+# CHECK: Vreg: %274[ 3 ]
+# CHECK: Vreg: %262[ 3 ]
+# CHECK: Vreg: %243[ 0 ]
+# CHECK: Vreg: %96[ 21 ]
+# CHECK: Vreg: %58[ 22 ]
+# CHECK: Vreg: %20[ 85 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %276[ 6 ]
+# CHECK: Vreg: %22[ 14 ]
+# CHECK: Vreg: %22:sub0[ 37 ]
+# CHECK: Vreg: %22:sub1[ 38 ]
+# CHECK: Vreg: %67[ 18 ]
+# CHECK: Vreg: %112[ 18 ]
+# CHECK: Vreg: %278[ 13 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Vreg: %254[ 2 ]
+# CHECK: Vreg: %43[ 23 ]
+# CHECK: Vreg: %5[ 95 ]
+# CHECK: Vreg: %69[ 18 ]
+# CHECK: Vreg: %95[ 17 ]
+# CHECK: Vreg: %268[ 3 ]
+# CHECK: Vreg: %249[ 32 ]
+# CHECK: Vreg: %19[ 6 ]
+# CHECK: Vreg: %19:sub0[ 61 ]
+# CHECK: Vreg: %19:sub1[ 62 ]
+# CHECK: Instr: %280:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 90 ]
+# CHECK: Vreg: %256[ 2 ]
+# CHECK: Vreg: %90[ 7 ]
+# CHECK: Vreg: %71[ 17 ]
+# CHECK: Vreg: %242[ 2 ]
+# CHECK: Vreg: %270[ 2 ]
+# CHECK: Vreg: %40[ 25 ]
+# CHECK: Vreg: %21[ 88 ]
+# CHECK: Vreg: %2[ 21 ]
+# CHECK: Vreg: %111[ 17 ]
+# CHECK: Vreg: %92[ 10 ]
+# CHECK: Vreg: %73[ 17 ]
+# CHECK: Vreg: %265[ 2 ]
+# CHECK: Vreg: %258[ 4 ]
+# CHECK: Vreg: %272[ 2 ]
+# CHECK: Vreg: %23[ 46 ]
+# CHECK: Vreg: %4[ 96 ]
+# CHECK: Vreg: %260[ 2 ]
+# CHECK: Vreg: %94[ 13 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %37[ 28 ]
+# CHECK: Vreg: %18[ 18 ]
+# CHECK: Vreg: %274[ 2 ]
+# CHECK: Vreg: %262[ 2 ]
+# CHECK: Vreg: %96[ 20 ]
+# CHECK: Vreg: %58[ 21 ]
+# CHECK: Vreg: %20[ 84 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %276[ 5 ]
+# CHECK: Vreg: %22[ 13 ]
+# CHECK: Vreg: %22:sub0[ 36 ]
+# CHECK: Vreg: %22:sub1[ 37 ]
+# CHECK: Vreg: %67[ 17 ]
+# CHECK: Vreg: %112[ 17 ]
+# CHECK: Vreg: %278[ 12 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Vreg: %254[ 1 ]
+# CHECK: Vreg: %43[ 22 ]
+# CHECK: Vreg: %5[ 94 ]
+# CHECK: Vreg: %69[ 17 ]
+# CHECK: Vreg: %95[ 16 ]
+# CHECK: Vreg: %268[ 2 ]
+# CHECK: Vreg: %249[ 31 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Vreg: %19:sub0[ 60 ]
+# CHECK: Vreg: %19:sub1[ 61 ]
+# CHECK: Instr: %281:sreg_32 = SI_IF killed %254, %bb.17, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 89 ]
+# CHECK: Vreg: %256[ 1 ]
+# CHECK: Vreg: %90[ 6 ]
+# CHECK: Vreg: %71[ 16 ]
+# CHECK: Vreg: %242[ 1 ]
+# CHECK: Vreg: %270[ 1 ]
+# CHECK: Vreg: %40[ 24 ]
+# CHECK: Vreg: %21[ 87 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %111[ 16 ]
+# CHECK: Vreg: %92[ 9 ]
+# CHECK: Vreg: %73[ 16 ]
+# CHECK: Vreg: %265[ 1 ]
+# CHECK: Vreg: %258[ 3 ]
+# CHECK: Vreg: %272[ 1 ]
+# CHECK: Vreg: %23[ 45 ]
+# CHECK: Vreg: %4[ 95 ]
+# CHECK: Vreg: %260[ 1 ]
+# CHECK: Vreg: %94[ 12 ]
+# CHECK: Vreg: %30[ 69 ]
+# CHECK: Vreg: %37[ 27 ]
+# CHECK: Vreg: %18[ 17 ]
+# CHECK: Vreg: %274[ 1 ]
+# CHECK: Vreg: %262[ 1 ]
+# CHECK: Vreg: %96[ 19 ]
+# CHECK: Vreg: %58[ 20 ]
+# CHECK: Vreg: %20[ 83 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %276[ 4 ]
+# CHECK: Vreg: %22[ 12 ]
+# CHECK: Vreg: %22:sub0[ 35 ]
+# CHECK: Vreg: %22:sub1[ 36 ]
+# CHECK: Vreg: %67[ 16 ]
+# CHECK: Vreg: %112[ 16 ]
+# CHECK: Vreg: %278[ 11 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %254[ 0 ]
+# CHECK: Vreg: %43[ 21 ]
+# CHECK: Vreg: %280[ 1 ]
+# CHECK: Vreg: %5[ 93 ]
+# CHECK: Vreg: %69[ 16 ]
+# CHECK: Vreg: %95[ 15 ]
+# CHECK: Vreg: %268[ 1 ]
+# CHECK: Vreg: %249[ 30 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Vreg: %19:sub0[ 59 ]
+# CHECK: Vreg: %19:sub1[ 60 ]
+# CHECK: Instr: S_BRANCH %bb.16
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %256[ 0 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %242[ 0 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %258[ 2 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %18[ 16 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %22[ 11 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %278[ 10 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %280[ 0 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %249[ 29 ]
+# CHECK: Vreg: %19[ 3 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %256[ 0 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %242[ 0 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %258[ 2 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %18[ 16 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %22[ 11 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %278[ 10 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %280[ 0 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %249[ 29 ]
+# CHECK: Vreg: %19[ 3 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: --- MBB_13 ---
+# CHECK: Instr: %282:vgpr_32 = GLOBAL_LOAD_DWORD %21, 0, 0, implicit $exec :: (load (s32) from %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 113 ]
+# CHECK: Vreg: %90[ 30 ]
+# CHECK: Vreg: %40[ 48 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 44 ]
+# CHECK: Vreg: %239[ 13 ]
+# CHECK: Vreg: %92[ 33 ]
+# CHECK: Vreg: %253[ 10 ]
+# CHECK: Vreg: %23[ 69 ]
+# CHECK: Vreg: %4[ 119 ]
+# CHECK: Vreg: %94[ 36 ]
+# CHECK: Vreg: %248[ 21 ]
+# CHECK: Vreg: %30[ 93 ]
+# CHECK: Vreg: %18[ 41 ]
+# CHECK: Vreg: %37[ 51 ]
+# CHECK: Vreg: %243[ 22 ]
+# CHECK: Vreg: %96[ 43 ]
+# CHECK: Vreg: %58[ 44 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %1[ 60 ]
+# CHECK: Vreg: %245[ 2 ]
+# CHECK: Vreg: %233[ 6 ]
+# CHECK: Vreg: %22[ 36 ]
+# CHECK: Vreg: %22:sub0[ 59 ]
+# CHECK: Vreg: %22:sub1[ 60 ]
+# CHECK: Vreg: %3[ 30 ]
+# CHECK: Vreg: %43[ 45 ]
+# CHECK: Vreg: %5[ 117 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %95[ 39 ]
+# CHECK: Vreg: %249[ 54 ]
+# CHECK: Vreg: %19[ 28 ]
+# CHECK: Vreg: %19:sub0[ 83 ]
+# CHECK: Vreg: %19:sub1[ 84 ]
+# CHECK: Instr: %283:vgpr_32 = V_MUL_LO_U32_e64 %282, %69, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 43 ]
+# CHECK: Vreg: %239[ 12 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %253[ 9 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %248[ 20 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %18[ 40 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %243[ 21 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %1[ 59 ]
+# CHECK: Vreg: %245[ 1 ]
+# CHECK: Vreg: %233[ 5 ]
+# CHECK: Vreg: %22[ 35 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 53 ]
+# CHECK: Vreg: %19[ 27 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %20, %245, 0, 0, implicit $exec :: (store (s32) into %ir.p4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 111 ]
+# CHECK: Vreg: %90[ 28 ]
+# CHECK: Vreg: %282[ 7 ]
+# CHECK: Vreg: %40[ 46 ]
+# CHECK: Vreg: %21[ 109 ]
+# CHECK: Vreg: %2[ 42 ]
+# CHECK: Vreg: %239[ 11 ]
+# CHECK: Vreg: %92[ 31 ]
+# CHECK: Vreg: %253[ 8 ]
+# CHECK: Vreg: %23[ 67 ]
+# CHECK: Vreg: %4[ 117 ]
+# CHECK: Vreg: %94[ 34 ]
+# CHECK: Vreg: %248[ 19 ]
+# CHECK: Vreg: %30[ 91 ]
+# CHECK: Vreg: %18[ 39 ]
+# CHECK: Vreg: %37[ 49 ]
+# CHECK: Vreg: %243[ 20 ]
+# CHECK: Vreg: %96[ 41 ]
+# CHECK: Vreg: %58[ 42 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 58 ]
+# CHECK: Vreg: %283[ 1 ]
+# CHECK: Vreg: %245[ 0 ]
+# CHECK: Vreg: %233[ 4 ]
+# CHECK: Vreg: %22[ 34 ]
+# CHECK: Vreg: %22:sub0[ 57 ]
+# CHECK: Vreg: %22:sub1[ 58 ]
+# CHECK: Vreg: %3[ 28 ]
+# CHECK: Vreg: %43[ 43 ]
+# CHECK: Vreg: %5[ 115 ]
+# CHECK: Vreg: %95[ 37 ]
+# CHECK: Vreg: %249[ 52 ]
+# CHECK: Vreg: %19[ 26 ]
+# CHECK: Vreg: %19:sub0[ 81 ]
+# CHECK: Vreg: %19:sub1[ 82 ]
+# CHECK: Instr: %284:sreg_32 = V_CMP_LT_U32_e64 %283, %245, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 110 ]
+# CHECK: Vreg: %90[ 27 ]
+# CHECK: Vreg: %282[ 6 ]
+# CHECK: Vreg: %40[ 45 ]
+# CHECK: Vreg: %21[ 108 ]
+# CHECK: Vreg: %2[ 41 ]
+# CHECK: Vreg: %239[ 10 ]
+# CHECK: Vreg: %92[ 30 ]
+# CHECK: Vreg: %253[ 7 ]
+# CHECK: Vreg: %23[ 66 ]
+# CHECK: Vreg: %4[ 116 ]
+# CHECK: Vreg: %94[ 33 ]
+# CHECK: Vreg: %248[ 18 ]
+# CHECK: Vreg: %30[ 90 ]
+# CHECK: Vreg: %18[ 38 ]
+# CHECK: Vreg: %37[ 48 ]
+# CHECK: Vreg: %243[ 19 ]
+# CHECK: Vreg: %96[ 40 ]
+# CHECK: Vreg: %58[ 41 ]
+# CHECK: Vreg: %20[ 104 ]
+# CHECK: Vreg: %1[ 57 ]
+# CHECK: Vreg: %283[ 0 ]
+# CHECK: Vreg: %245[ 0 ]
+# CHECK: Vreg: %233[ 3 ]
+# CHECK: Vreg: %22[ 33 ]
+# CHECK: Vreg: %22:sub0[ 56 ]
+# CHECK: Vreg: %22:sub1[ 57 ]
+# CHECK: Vreg: %3[ 27 ]
+# CHECK: Vreg: %43[ 42 ]
+# CHECK: Vreg: %5[ 114 ]
+# CHECK: Vreg: %95[ 36 ]
+# CHECK: Vreg: %249[ 51 ]
+# CHECK: Vreg: %19[ 25 ]
+# CHECK: Vreg: %19:sub0[ 80 ]
+# CHECK: Vreg: %19:sub1[ 81 ]
+# CHECK: Instr: %285:sreg_32 = V_CMP_GE_U32_e64 %283, killed %245, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 109 ]
+# CHECK: Vreg: %90[ 26 ]
+# CHECK: Vreg: %282[ 5 ]
+# CHECK: Vreg: %40[ 44 ]
+# CHECK: Vreg: %21[ 107 ]
+# CHECK: Vreg: %2[ 40 ]
+# CHECK: Vreg: %239[ 9 ]
+# CHECK: Vreg: %92[ 29 ]
+# CHECK: Vreg: %284[ 5 ]
+# CHECK: Vreg: %253[ 6 ]
+# CHECK: Vreg: %23[ 65 ]
+# CHECK: Vreg: %4[ 115 ]
+# CHECK: Vreg: %94[ 32 ]
+# CHECK: Vreg: %248[ 17 ]
+# CHECK: Vreg: %30[ 89 ]
+# CHECK: Vreg: %18[ 37 ]
+# CHECK: Vreg: %37[ 47 ]
+# CHECK: Vreg: %243[ 18 ]
+# CHECK: Vreg: %96[ 39 ]
+# CHECK: Vreg: %58[ 40 ]
+# CHECK: Vreg: %20[ 103 ]
+# CHECK: Vreg: %1[ 56 ]
+# CHECK: Vreg: %283[ 0 ]
+# CHECK: Vreg: %245[ 0 ]
+# CHECK: Vreg: %233[ 2 ]
+# CHECK: Vreg: %22[ 32 ]
+# CHECK: Vreg: %22:sub0[ 55 ]
+# CHECK: Vreg: %22:sub1[ 56 ]
+# CHECK: Vreg: %3[ 26 ]
+# CHECK: Vreg: %43[ 41 ]
+# CHECK: Vreg: %5[ 113 ]
+# CHECK: Vreg: %95[ 35 ]
+# CHECK: Vreg: %249[ 50 ]
+# CHECK: Vreg: %19[ 24 ]
+# CHECK: Vreg: %19:sub0[ 79 ]
+# CHECK: Vreg: %19:sub1[ 80 ]
+# CHECK: Instr: %286:sreg_32 = COPY $exec_lo
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 108 ]
+# CHECK: Vreg: %90[ 25 ]
+# CHECK: Vreg: %282[ 4 ]
+# CHECK: Vreg: %40[ 43 ]
+# CHECK: Vreg: %21[ 106 ]
+# CHECK: Vreg: %2[ 39 ]
+# CHECK: Vreg: %239[ 8 ]
+# CHECK: Vreg: %92[ 28 ]
+# CHECK: Vreg: %284[ 4 ]
+# CHECK: Vreg: %253[ 5 ]
+# CHECK: Vreg: %23[ 64 ]
+# CHECK: Vreg: %4[ 114 ]
+# CHECK: Vreg: %94[ 31 ]
+# CHECK: Vreg: %248[ 16 ]
+# CHECK: Vreg: %30[ 88 ]
+# CHECK: Vreg: %18[ 36 ]
+# CHECK: Vreg: %37[ 46 ]
+# CHECK: Vreg: %243[ 17 ]
+# CHECK: Vreg: %96[ 38 ]
+# CHECK: Vreg: %58[ 39 ]
+# CHECK: Vreg: %20[ 102 ]
+# CHECK: Vreg: %1[ 55 ]
+# CHECK: Vreg: %283[ 4 ]
+# CHECK: Vreg: %233[ 1 ]
+# CHECK: Vreg: %22[ 31 ]
+# CHECK: Vreg: %22:sub0[ 54 ]
+# CHECK: Vreg: %22:sub1[ 55 ]
+# CHECK: Vreg: %3[ 25 ]
+# CHECK: Vreg: %285[ 2 ]
+# CHECK: Vreg: %43[ 40 ]
+# CHECK: Vreg: %5[ 112 ]
+# CHECK: Vreg: %95[ 34 ]
+# CHECK: Vreg: %249[ 49 ]
+# CHECK: Vreg: %19[ 23 ]
+# CHECK: Vreg: %19:sub0[ 78 ]
+# CHECK: Vreg: %19:sub1[ 79 ]
+# CHECK: Instr: %287:sreg_32 = S_ANDN2_B32 %233, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 107 ]
+# CHECK: Vreg: %90[ 24 ]
+# CHECK: Vreg: %282[ 3 ]
+# CHECK: Vreg: %40[ 42 ]
+# CHECK: Vreg: %21[ 105 ]
+# CHECK: Vreg: %2[ 38 ]
+# CHECK: Vreg: %239[ 7 ]
+# CHECK: Vreg: %92[ 27 ]
+# CHECK: Vreg: %284[ 3 ]
+# CHECK: Vreg: %253[ 4 ]
+# CHECK: Vreg: %23[ 63 ]
+# CHECK: Vreg: %4[ 113 ]
+# CHECK: Vreg: %94[ 30 ]
+# CHECK: Vreg: %286[ 3 ]
+# CHECK: Vreg: %248[ 15 ]
+# CHECK: Vreg: %30[ 87 ]
+# CHECK: Vreg: %18[ 35 ]
+# CHECK: Vreg: %37[ 45 ]
+# CHECK: Vreg: %243[ 16 ]
+# CHECK: Vreg: %96[ 37 ]
+# CHECK: Vreg: %58[ 38 ]
+# CHECK: Vreg: %20[ 101 ]
+# CHECK: Vreg: %1[ 54 ]
+# CHECK: Vreg: %283[ 3 ]
+# CHECK: Vreg: %233[ 0 ]
+# CHECK: Vreg: %22[ 30 ]
+# CHECK: Vreg: %22:sub0[ 53 ]
+# CHECK: Vreg: %22:sub1[ 54 ]
+# CHECK: Vreg: %3[ 24 ]
+# CHECK: Vreg: %285[ 1 ]
+# CHECK: Vreg: %43[ 39 ]
+# CHECK: Vreg: %5[ 111 ]
+# CHECK: Vreg: %95[ 33 ]
+# CHECK: Vreg: %249[ 48 ]
+# CHECK: Vreg: %19[ 22 ]
+# CHECK: Vreg: %19:sub0[ 77 ]
+# CHECK: Vreg: %19:sub1[ 78 ]
+# CHECK: Instr: %288:sreg_32 = S_AND_B32 killed %285, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 106 ]
+# CHECK: Vreg: %90[ 23 ]
+# CHECK: Vreg: %282[ 2 ]
+# CHECK: Vreg: %40[ 41 ]
+# CHECK: Vreg: %21[ 104 ]
+# CHECK: Vreg: %2[ 37 ]
+# CHECK: Vreg: %239[ 6 ]
+# CHECK: Vreg: %92[ 26 ]
+# CHECK: Vreg: %284[ 2 ]
+# CHECK: Vreg: %253[ 3 ]
+# CHECK: Vreg: %23[ 62 ]
+# CHECK: Vreg: %4[ 112 ]
+# CHECK: Vreg: %94[ 29 ]
+# CHECK: Vreg: %286[ 2 ]
+# CHECK: Vreg: %248[ 14 ]
+# CHECK: Vreg: %30[ 86 ]
+# CHECK: Vreg: %18[ 34 ]
+# CHECK: Vreg: %37[ 44 ]
+# CHECK: Vreg: %243[ 15 ]
+# CHECK: Vreg: %96[ 36 ]
+# CHECK: Vreg: %58[ 37 ]
+# CHECK: Vreg: %20[ 100 ]
+# CHECK: Vreg: %1[ 53 ]
+# CHECK: Vreg: %283[ 2 ]
+# CHECK: Vreg: %22[ 29 ]
+# CHECK: Vreg: %22:sub0[ 52 ]
+# CHECK: Vreg: %22:sub1[ 53 ]
+# CHECK: Vreg: %3[ 23 ]
+# CHECK: Vreg: %285[ 0 ]
+# CHECK: Vreg: %43[ 38 ]
+# CHECK: Vreg: %5[ 110 ]
+# CHECK: Vreg: %95[ 32 ]
+# CHECK: Vreg: %287[ 1 ]
+# CHECK: Vreg: %249[ 47 ]
+# CHECK: Vreg: %19[ 21 ]
+# CHECK: Vreg: %19:sub0[ 76 ]
+# CHECK: Vreg: %19:sub1[ 77 ]
+# CHECK: Instr: %289:sreg_32 = S_OR_B32 killed %287, killed %288, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 105 ]
+# CHECK: Vreg: %90[ 22 ]
+# CHECK: Vreg: %282[ 1 ]
+# CHECK: Vreg: %40[ 40 ]
+# CHECK: Vreg: %21[ 103 ]
+# CHECK: Vreg: %2[ 36 ]
+# CHECK: Vreg: %239[ 5 ]
+# CHECK: Vreg: %92[ 25 ]
+# CHECK: Vreg: %284[ 1 ]
+# CHECK: Vreg: %253[ 2 ]
+# CHECK: Vreg: %23[ 61 ]
+# CHECK: Vreg: %4[ 111 ]
+# CHECK: Vreg: %94[ 28 ]
+# CHECK: Vreg: %286[ 1 ]
+# CHECK: Vreg: %248[ 13 ]
+# CHECK: Vreg: %30[ 85 ]
+# CHECK: Vreg: %18[ 33 ]
+# CHECK: Vreg: %37[ 43 ]
+# CHECK: Vreg: %243[ 14 ]
+# CHECK: Vreg: %96[ 35 ]
+# CHECK: Vreg: %288[ 0 ]
+# CHECK: Vreg: %58[ 36 ]
+# CHECK: Vreg: %20[ 99 ]
+# CHECK: Vreg: %1[ 52 ]
+# CHECK: Vreg: %283[ 1 ]
+# CHECK: Vreg: %22[ 28 ]
+# CHECK: Vreg: %22:sub0[ 51 ]
+# CHECK: Vreg: %22:sub1[ 52 ]
+# CHECK: Vreg: %3[ 22 ]
+# CHECK: Vreg: %43[ 37 ]
+# CHECK: Vreg: %5[ 109 ]
+# CHECK: Vreg: %95[ 31 ]
+# CHECK: Vreg: %287[ 0 ]
+# CHECK: Vreg: %249[ 46 ]
+# CHECK: Vreg: %19[ 20 ]
+# CHECK: Vreg: %19:sub0[ 75 ]
+# CHECK: Vreg: %19:sub1[ 76 ]
+# CHECK: Instr: S_BRANCH %bb.15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %289[ 0 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %284[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %286[ 0 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %283[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %289[ 0 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %284[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %286[ 0 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %283[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: --- MBB_14 ---
+# CHECK: Instr: %290:vgpr_32 = GLOBAL_LOAD_USHORT %20, 0, 0, implicit $exec :: (load (s16) from %ir.p4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %90[ 19 ]
+# CHECK: Vreg: %71[ 17 ]
+# CHECK: Vreg: %244[ 9 ]
+# CHECK: Vreg: %40[ 37 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %2[ 33 ]
+# CHECK: Vreg: %92[ 22 ]
+# CHECK: Vreg: %73[ 17 ]
+# CHECK: Vreg: %246[ 11 ]
+# CHECK: Vreg: %23[ 58 ]
+# CHECK: Vreg: %4[ 108 ]
+# CHECK: Vreg: %94[ 25 ]
+# CHECK: Vreg: %30[ 82 ]
+# CHECK: Vreg: %37[ 40 ]
+# CHECK: Vreg: %18[ 30 ]
+# CHECK: Vreg: %63[ 10 ]
+# CHECK: Vreg: %96[ 32 ]
+# CHECK: Vreg: %58[ 33 ]
+# CHECK: Vreg: %250[ 13 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 49 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %212[ 3 ]
+# CHECK: Vreg: %60[ 10 ]
+# CHECK: Vreg: %22[ 25 ]
+# CHECK: Vreg: %22:sub0[ 48 ]
+# CHECK: Vreg: %22:sub1[ 49 ]
+# CHECK: Vreg: %3[ 19 ]
+# CHECK: Vreg: %67[ 17 ]
+# CHECK: Vreg: %247[ 11 ]
+# CHECK: Vreg: %43[ 34 ]
+# CHECK: Vreg: %5[ 106 ]
+# CHECK: Vreg: %69[ 17 ]
+# CHECK: Vreg: %95[ 28 ]
+# CHECK: Vreg: %249[ 13 ]
+# CHECK: Vreg: %19[ 12 ]
+# CHECK: Vreg: %19:sub0[ 72 ]
+# CHECK: Vreg: %19:sub1[ 73 ]
+# CHECK: Instr: %291:vgpr_32 = GLOBAL_LOAD_USHORT %20, 2, 0, implicit $exec :: (load (s16) from %ir.p4 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %71[ 16 ]
+# CHECK: Vreg: %244[ 8 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %73[ 16 ]
+# CHECK: Vreg: %246[ 10 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %18[ 29 ]
+# CHECK: Vreg: %63[ 9 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %250[ 12 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 48 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %212[ 2 ]
+# CHECK: Vreg: %290[ 1 ]
+# CHECK: Vreg: %60[ 9 ]
+# CHECK: Vreg: %22[ 24 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %67[ 16 ]
+# CHECK: Vreg: %247[ 10 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %69[ 16 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %249[ 12 ]
+# CHECK: Vreg: %19[ 11 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Instr: %238:vgpr_32 = V_LSHL_OR_B32_e64 killed %291, 16, killed %290, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %90[ 17 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %244[ 7 ]
+# CHECK: Vreg: %40[ 35 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %2[ 31 ]
+# CHECK: Vreg: %92[ 20 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %246[ 9 ]
+# CHECK: Vreg: %291[ 0 ]
+# CHECK: Vreg: %23[ 56 ]
+# CHECK: Vreg: %4[ 106 ]
+# CHECK: Vreg: %94[ 23 ]
+# CHECK: Vreg: %30[ 80 ]
+# CHECK: Vreg: %37[ 38 ]
+# CHECK: Vreg: %18[ 28 ]
+# CHECK: Vreg: %63[ 8 ]
+# CHECK: Vreg: %96[ 30 ]
+# CHECK: Vreg: %58[ 31 ]
+# CHECK: Vreg: %250[ 11 ]
+# CHECK: Vreg: %20[ 18 ]
+# CHECK: Vreg: %1[ 47 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %212[ 1 ]
+# CHECK: Vreg: %290[ 0 ]
+# CHECK: Vreg: %60[ 8 ]
+# CHECK: Vreg: %22[ 23 ]
+# CHECK: Vreg: %22:sub0[ 46 ]
+# CHECK: Vreg: %22:sub1[ 47 ]
+# CHECK: Vreg: %3[ 17 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %247[ 9 ]
+# CHECK: Vreg: %43[ 32 ]
+# CHECK: Vreg: %5[ 104 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %95[ 26 ]
+# CHECK: Vreg: %249[ 11 ]
+# CHECK: Vreg: %19[ 10 ]
+# CHECK: Vreg: %19:sub0[ 70 ]
+# CHECK: Vreg: %19:sub1[ 71 ]
+# CHECK: Instr: %292:vgpr_32 = V_MUL_LO_U32_e64 %238, killed %212, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %90[ 16 ]
+# CHECK: Vreg: %71[ 14 ]
+# CHECK: Vreg: %244[ 6 ]
+# CHECK: Vreg: %40[ 34 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 30 ]
+# CHECK: Vreg: %92[ 19 ]
+# CHECK: Vreg: %73[ 14 ]
+# CHECK: Vreg: %246[ 8 ]
+# CHECK: Vreg: %23[ 55 ]
+# CHECK: Vreg: %4[ 105 ]
+# CHECK: Vreg: %94[ 22 ]
+# CHECK: Vreg: %30[ 79 ]
+# CHECK: Vreg: %37[ 37 ]
+# CHECK: Vreg: %18[ 27 ]
+# CHECK: Vreg: %63[ 7 ]
+# CHECK: Vreg: %96[ 29 ]
+# CHECK: Vreg: %58[ 30 ]
+# CHECK: Vreg: %250[ 10 ]
+# CHECK: Vreg: %20[ 17 ]
+# CHECK: Vreg: %1[ 46 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %238[ 0 ]
+# CHECK: Vreg: %212[ 0 ]
+# CHECK: Vreg: %60[ 7 ]
+# CHECK: Vreg: %22[ 22 ]
+# CHECK: Vreg: %22:sub0[ 45 ]
+# CHECK: Vreg: %22:sub1[ 46 ]
+# CHECK: Vreg: %3[ 16 ]
+# CHECK: Vreg: %67[ 14 ]
+# CHECK: Vreg: %247[ 8 ]
+# CHECK: Vreg: %43[ 31 ]
+# CHECK: Vreg: %5[ 103 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %95[ 25 ]
+# CHECK: Vreg: %249[ 10 ]
+# CHECK: Vreg: %19[ 9 ]
+# CHECK: Vreg: %19:sub0[ 69 ]
+# CHECK: Vreg: %19:sub1[ 70 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %21, killed %292, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %90[ 15 ]
+# CHECK: Vreg: %71[ 13 ]
+# CHECK: Vreg: %244[ 5 ]
+# CHECK: Vreg: %40[ 33 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %92[ 18 ]
+# CHECK: Vreg: %73[ 13 ]
+# CHECK: Vreg: %246[ 7 ]
+# CHECK: Vreg: %23[ 54 ]
+# CHECK: Vreg: %4[ 104 ]
+# CHECK: Vreg: %94[ 21 ]
+# CHECK: Vreg: %30[ 78 ]
+# CHECK: Vreg: %37[ 36 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %63[ 6 ]
+# CHECK: Vreg: %96[ 28 ]
+# CHECK: Vreg: %58[ 29 ]
+# CHECK: Vreg: %250[ 9 ]
+# CHECK: Vreg: %20[ 16 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %238[ 3 ]
+# CHECK: Vreg: %60[ 6 ]
+# CHECK: Vreg: %22[ 21 ]
+# CHECK: Vreg: %22:sub0[ 44 ]
+# CHECK: Vreg: %22:sub1[ 45 ]
+# CHECK: Vreg: %3[ 15 ]
+# CHECK: Vreg: %67[ 13 ]
+# CHECK: Vreg: %247[ 7 ]
+# CHECK: Vreg: %292[ 0 ]
+# CHECK: Vreg: %43[ 30 ]
+# CHECK: Vreg: %5[ 102 ]
+# CHECK: Vreg: %69[ 13 ]
+# CHECK: Vreg: %95[ 24 ]
+# CHECK: Vreg: %249[ 9 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ 68 ]
+# CHECK: Vreg: %19:sub1[ 69 ]
+# CHECK: Instr: %241:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %90[ 14 ]
+# CHECK: Vreg: %71[ 12 ]
+# CHECK: Vreg: %244[ 4 ]
+# CHECK: Vreg: %40[ 32 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %2[ 28 ]
+# CHECK: Vreg: %92[ 17 ]
+# CHECK: Vreg: %73[ 12 ]
+# CHECK: Vreg: %246[ 6 ]
+# CHECK: Vreg: %23[ 53 ]
+# CHECK: Vreg: %4[ 103 ]
+# CHECK: Vreg: %94[ 20 ]
+# CHECK: Vreg: %30[ 77 ]
+# CHECK: Vreg: %37[ 35 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %96[ 27 ]
+# CHECK: Vreg: %58[ 28 ]
+# CHECK: Vreg: %250[ 8 ]
+# CHECK: Vreg: %20[ 15 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %238[ 2 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %22[ 20 ]
+# CHECK: Vreg: %22:sub0[ 43 ]
+# CHECK: Vreg: %22:sub1[ 44 ]
+# CHECK: Vreg: %3[ 14 ]
+# CHECK: Vreg: %67[ 12 ]
+# CHECK: Vreg: %247[ 6 ]
+# CHECK: Vreg: %43[ 29 ]
+# CHECK: Vreg: %5[ 101 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %95[ 23 ]
+# CHECK: Vreg: %249[ 8 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 67 ]
+# CHECK: Vreg: %19:sub1[ 68 ]
+# CHECK: Instr: %235:sreg_32 = COPY $exec_lo
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %90[ 13 ]
+# CHECK: Vreg: %71[ 11 ]
+# CHECK: Vreg: %244[ 3 ]
+# CHECK: Vreg: %40[ 31 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %92[ 16 ]
+# CHECK: Vreg: %73[ 11 ]
+# CHECK: Vreg: %246[ 5 ]
+# CHECK: Vreg: %23[ 52 ]
+# CHECK: Vreg: %4[ 102 ]
+# CHECK: Vreg: %241[ 1 ]
+# CHECK: Vreg: %94[ 19 ]
+# CHECK: Vreg: %30[ 76 ]
+# CHECK: Vreg: %37[ 34 ]
+# CHECK: Vreg: %18[ 24 ]
+# CHECK: Vreg: %63[ 4 ]
+# CHECK: Vreg: %96[ 26 ]
+# CHECK: Vreg: %58[ 27 ]
+# CHECK: Vreg: %250[ 7 ]
+# CHECK: Vreg: %20[ 14 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %238[ 1 ]
+# CHECK: Vreg: %60[ 4 ]
+# CHECK: Vreg: %22[ 19 ]
+# CHECK: Vreg: %22:sub0[ 42 ]
+# CHECK: Vreg: %22:sub1[ 43 ]
+# CHECK: Vreg: %3[ 13 ]
+# CHECK: Vreg: %67[ 11 ]
+# CHECK: Vreg: %247[ 5 ]
+# CHECK: Vreg: %43[ 28 ]
+# CHECK: Vreg: %5[ 100 ]
+# CHECK: Vreg: %69[ 11 ]
+# CHECK: Vreg: %95[ 22 ]
+# CHECK: Vreg: %249[ 7 ]
+# CHECK: Vreg: %19[ 6 ]
+# CHECK: Vreg: %19:sub0[ 66 ]
+# CHECK: Vreg: %19:sub1[ 67 ]
+# CHECK: Instr: S_BRANCH %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %90[ 12 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %244[ 2 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %246[ 4 ]
+# CHECK: Vreg: %23[ 51 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %241[ 0 ]
+# CHECK: Vreg: %94[ 18 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %37[ 33 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %96[ 25 ]
+# CHECK: Vreg: %58[ 26 ]
+# CHECK: Vreg: %250[ 6 ]
+# CHECK: Vreg: %20[ 13 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %238[ 0 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %22:sub0[ 41 ]
+# CHECK: Vreg: %22:sub1[ 42 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %247[ 4 ]
+# CHECK: Vreg: %43[ 27 ]
+# CHECK: Vreg: %235[ 0 ]
+# CHECK: Vreg: %5[ 99 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 21 ]
+# CHECK: Vreg: %249[ 6 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Vreg: %19:sub0[ 65 ]
+# CHECK: Vreg: %19:sub1[ 66 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %90[ 12 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %244[ 2 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %246[ 4 ]
+# CHECK: Vreg: %23[ 51 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %241[ 0 ]
+# CHECK: Vreg: %94[ 18 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %37[ 33 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %96[ 25 ]
+# CHECK: Vreg: %58[ 26 ]
+# CHECK: Vreg: %250[ 6 ]
+# CHECK: Vreg: %20[ 13 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %238[ 0 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %22:sub0[ 41 ]
+# CHECK: Vreg: %22:sub1[ 42 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %247[ 4 ]
+# CHECK: Vreg: %43[ 27 ]
+# CHECK: Vreg: %235[ 0 ]
+# CHECK: Vreg: %5[ 99 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 21 ]
+# CHECK: Vreg: %249[ 6 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Vreg: %19:sub0[ 65 ]
+# CHECK: Vreg: %19:sub1[ 66 ]
+# CHECK: --- MBB_15 ---
+# CHECK: Instr: %293:sreg_32 = PHI %233, %bb.11, %289, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %289[ 0 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %284[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %286[ 0 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %283[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %233[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %252[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: %294:sreg_32 = PHI %252, %bb.11, %286, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %293[ 10 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %284[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %286[ 0 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %283[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %233[ 9 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %252[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: %295:sreg_32 = PHI undef %296:sreg_32, %bb.11, %284, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %293[ 10 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %284[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %283[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %233[ 9 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %294[ 7 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: %264:vgpr_32 = PHI %60, %bb.11, %283, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %293[ 10 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %295[ 5 ]
+# CHECK: Vreg: %283[ 0 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %233[ 9 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %294[ 7 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: %267:vgpr_32 = PHI %65, %bb.11, undef %297:vgpr_32, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %293[ 10 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %295[ 5 ]
+# CHECK: Vreg: %264[ 12 ]
+# CHECK: Vreg: %233[ 9 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %294[ 7 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: %269:vgpr_32 = PHI %67, %bb.11, undef %297:vgpr_32, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %293[ 10 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %267[ 12 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %295[ 5 ]
+# CHECK: Vreg: %264[ 12 ]
+# CHECK: Vreg: %233[ 9 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %65[ 20 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %294[ 7 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: %271:vgpr_32 = PHI %69, %bb.11, undef %297:vgpr_32, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %293[ 10 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %267[ 12 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %269[ 12 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %295[ 5 ]
+# CHECK: Vreg: %264[ 12 ]
+# CHECK: Vreg: %233[ 9 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %65[ 20 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %294[ 7 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: %273:vgpr_32 = PHI %71, %bb.11, undef %297:vgpr_32, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %293[ 10 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %267[ 12 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %269[ 12 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %295[ 5 ]
+# CHECK: Vreg: %264[ 12 ]
+# CHECK: Vreg: %271[ 12 ]
+# CHECK: Vreg: %233[ 9 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %65[ 20 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %69[ 31 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %294[ 7 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: %275:vgpr_32 = PHI %73, %bb.11, undef %297:vgpr_32, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %71[ 31 ]
+# CHECK: Vreg: %293[ 10 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %267[ 12 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %269[ 12 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %295[ 5 ]
+# CHECK: Vreg: %264[ 12 ]
+# CHECK: Vreg: %271[ 12 ]
+# CHECK: Vreg: %233[ 9 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %65[ 20 ]
+# CHECK: Vreg: %273[ 12 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %69[ 31 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %294[ 7 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: %279:vgpr_32 = PHI undef %298:vgpr_32, %bb.11, %282, %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %282[ 0 ]
+# CHECK: Vreg: %71[ 31 ]
+# CHECK: Vreg: %275[ 12 ]
+# CHECK: Vreg: %293[ 10 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 35 ]
+# CHECK: Vreg: %239[ 4 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 31 ]
+# CHECK: Vreg: %253[ 1 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %267[ 12 ]
+# CHECK: Vreg: %248[ 12 ]
+# CHECK: Vreg: %18[ 32 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %243[ 13 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %269[ 12 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %295[ 5 ]
+# CHECK: Vreg: %264[ 12 ]
+# CHECK: Vreg: %271[ 12 ]
+# CHECK: Vreg: %233[ 9 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %65[ 20 ]
+# CHECK: Vreg: %273[ 12 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %69[ 31 ]
+# CHECK: Vreg: %249[ 45 ]
+# CHECK: Vreg: %294[ 7 ]
+# CHECK: Vreg: %19[ 19 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Instr: SI_END_CF killed %253, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %71[ 30 ]
+# CHECK: Vreg: %275[ 11 ]
+# CHECK: Vreg: %293[ 9 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %2[ 34 ]
+# CHECK: Vreg: %239[ 3 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %73[ 30 ]
+# CHECK: Vreg: %253[ 0 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %267[ 11 ]
+# CHECK: Vreg: %248[ 11 ]
+# CHECK: Vreg: %279[ 11 ]
+# CHECK: Vreg: %18[ 31 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %243[ 12 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %269[ 11 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %1[ 50 ]
+# CHECK: Vreg: %295[ 4 ]
+# CHECK: Vreg: %264[ 11 ]
+# CHECK: Vreg: %271[ 11 ]
+# CHECK: Vreg: %233[ 8 ]
+# CHECK: Vreg: %22[ 26 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %67[ 30 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %65[ 19 ]
+# CHECK: Vreg: %273[ 11 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %69[ 30 ]
+# CHECK: Vreg: %249[ 44 ]
+# CHECK: Vreg: %294[ 6 ]
+# CHECK: Vreg: %19[ 18 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Instr: %263:sreg_32 = COPY $exec_lo
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 102 ]
+# CHECK: Vreg: %90[ 19 ]
+# CHECK: Vreg: %71[ 29 ]
+# CHECK: Vreg: %275[ 10 ]
+# CHECK: Vreg: %293[ 8 ]
+# CHECK: Vreg: %40[ 37 ]
+# CHECK: Vreg: %21[ 100 ]
+# CHECK: Vreg: %2[ 33 ]
+# CHECK: Vreg: %239[ 2 ]
+# CHECK: Vreg: %92[ 22 ]
+# CHECK: Vreg: %73[ 29 ]
+# CHECK: Vreg: %23[ 58 ]
+# CHECK: Vreg: %4[ 108 ]
+# CHECK: Vreg: %94[ 25 ]
+# CHECK: Vreg: %267[ 10 ]
+# CHECK: Vreg: %248[ 10 ]
+# CHECK: Vreg: %279[ 10 ]
+# CHECK: Vreg: %18[ 30 ]
+# CHECK: Vreg: %30[ 82 ]
+# CHECK: Vreg: %243[ 11 ]
+# CHECK: Vreg: %96[ 32 ]
+# CHECK: Vreg: %269[ 10 ]
+# CHECK: Vreg: %58[ 33 ]
+# CHECK: Vreg: %37[ 40 ]
+# CHECK: Vreg: %20[ 96 ]
+# CHECK: Vreg: %1[ 49 ]
+# CHECK: Vreg: %295[ 3 ]
+# CHECK: Vreg: %264[ 10 ]
+# CHECK: Vreg: %271[ 10 ]
+# CHECK: Vreg: %233[ 7 ]
+# CHECK: Vreg: %22[ 25 ]
+# CHECK: Vreg: %22:sub0[ 48 ]
+# CHECK: Vreg: %22:sub1[ 49 ]
+# CHECK: Vreg: %67[ 29 ]
+# CHECK: Vreg: %3[ 19 ]
+# CHECK: Vreg: %65[ 18 ]
+# CHECK: Vreg: %273[ 10 ]
+# CHECK: Vreg: %43[ 34 ]
+# CHECK: Vreg: %5[ 106 ]
+# CHECK: Vreg: %95[ 28 ]
+# CHECK: Vreg: %69[ 29 ]
+# CHECK: Vreg: %249[ 43 ]
+# CHECK: Vreg: %294[ 5 ]
+# CHECK: Vreg: %19[ 17 ]
+# CHECK: Vreg: %19:sub0[ 72 ]
+# CHECK: Vreg: %19:sub1[ 73 ]
+# CHECK: Instr: %261:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %263[ 9 ]
+# CHECK: Vreg: %71[ 28 ]
+# CHECK: Vreg: %275[ 9 ]
+# CHECK: Vreg: %293[ 7 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %2[ 32 ]
+# CHECK: Vreg: %239[ 1 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %73[ 28 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %267[ 9 ]
+# CHECK: Vreg: %248[ 9 ]
+# CHECK: Vreg: %279[ 9 ]
+# CHECK: Vreg: %18[ 29 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %243[ 10 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %269[ 9 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %1[ 48 ]
+# CHECK: Vreg: %295[ 2 ]
+# CHECK: Vreg: %264[ 9 ]
+# CHECK: Vreg: %271[ 9 ]
+# CHECK: Vreg: %233[ 6 ]
+# CHECK: Vreg: %22[ 24 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %67[ 28 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %273[ 9 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %69[ 28 ]
+# CHECK: Vreg: %249[ 42 ]
+# CHECK: Vreg: %294[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Instr: %299:sreg_32 = S_ANDN2_B32 killed %239, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 100 ]
+# CHECK: Vreg: %90[ 17 ]
+# CHECK: Vreg: %263[ 8 ]
+# CHECK: Vreg: %71[ 27 ]
+# CHECK: Vreg: %275[ 8 ]
+# CHECK: Vreg: %293[ 6 ]
+# CHECK: Vreg: %40[ 35 ]
+# CHECK: Vreg: %21[ 98 ]
+# CHECK: Vreg: %2[ 31 ]
+# CHECK: Vreg: %239[ 0 ]
+# CHECK: Vreg: %92[ 20 ]
+# CHECK: Vreg: %73[ 27 ]
+# CHECK: Vreg: %23[ 56 ]
+# CHECK: Vreg: %4[ 106 ]
+# CHECK: Vreg: %94[ 23 ]
+# CHECK: Vreg: %267[ 8 ]
+# CHECK: Vreg: %248[ 8 ]
+# CHECK: Vreg: %279[ 8 ]
+# CHECK: Vreg: %18[ 28 ]
+# CHECK: Vreg: %30[ 80 ]
+# CHECK: Vreg: %243[ 9 ]
+# CHECK: Vreg: %96[ 30 ]
+# CHECK: Vreg: %269[ 8 ]
+# CHECK: Vreg: %58[ 31 ]
+# CHECK: Vreg: %37[ 38 ]
+# CHECK: Vreg: %20[ 94 ]
+# CHECK: Vreg: %1[ 47 ]
+# CHECK: Vreg: %295[ 1 ]
+# CHECK: Vreg: %264[ 8 ]
+# CHECK: Vreg: %271[ 8 ]
+# CHECK: Vreg: %233[ 5 ]
+# CHECK: Vreg: %22[ 23 ]
+# CHECK: Vreg: %22:sub0[ 46 ]
+# CHECK: Vreg: %22:sub1[ 47 ]
+# CHECK: Vreg: %67[ 27 ]
+# CHECK: Vreg: %3[ 17 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %273[ 8 ]
+# CHECK: Vreg: %43[ 32 ]
+# CHECK: Vreg: %261[ 8 ]
+# CHECK: Vreg: %5[ 104 ]
+# CHECK: Vreg: %95[ 26 ]
+# CHECK: Vreg: %69[ 27 ]
+# CHECK: Vreg: %249[ 41 ]
+# CHECK: Vreg: %294[ 3 ]
+# CHECK: Vreg: %19[ 15 ]
+# CHECK: Vreg: %19:sub0[ 70 ]
+# CHECK: Vreg: %19:sub1[ 71 ]
+# CHECK: Instr: %300:sreg_32 = S_AND_B32 killed %295, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 99 ]
+# CHECK: Vreg: %90[ 16 ]
+# CHECK: Vreg: %263[ 7 ]
+# CHECK: Vreg: %71[ 26 ]
+# CHECK: Vreg: %275[ 7 ]
+# CHECK: Vreg: %293[ 5 ]
+# CHECK: Vreg: %40[ 34 ]
+# CHECK: Vreg: %21[ 97 ]
+# CHECK: Vreg: %2[ 30 ]
+# CHECK: Vreg: %92[ 19 ]
+# CHECK: Vreg: %73[ 26 ]
+# CHECK: Vreg: %23[ 55 ]
+# CHECK: Vreg: %4[ 105 ]
+# CHECK: Vreg: %94[ 22 ]
+# CHECK: Vreg: %267[ 7 ]
+# CHECK: Vreg: %248[ 7 ]
+# CHECK: Vreg: %279[ 7 ]
+# CHECK: Vreg: %18[ 27 ]
+# CHECK: Vreg: %30[ 79 ]
+# CHECK: Vreg: %243[ 8 ]
+# CHECK: Vreg: %96[ 29 ]
+# CHECK: Vreg: %269[ 7 ]
+# CHECK: Vreg: %58[ 30 ]
+# CHECK: Vreg: %37[ 37 ]
+# CHECK: Vreg: %20[ 93 ]
+# CHECK: Vreg: %1[ 46 ]
+# CHECK: Vreg: %295[ 0 ]
+# CHECK: Vreg: %264[ 7 ]
+# CHECK: Vreg: %271[ 7 ]
+# CHECK: Vreg: %233[ 4 ]
+# CHECK: Vreg: %22[ 22 ]
+# CHECK: Vreg: %22:sub0[ 45 ]
+# CHECK: Vreg: %22:sub1[ 46 ]
+# CHECK: Vreg: %67[ 26 ]
+# CHECK: Vreg: %3[ 16 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %273[ 7 ]
+# CHECK: Vreg: %43[ 31 ]
+# CHECK: Vreg: %299[ 1 ]
+# CHECK: Vreg: %261[ 7 ]
+# CHECK: Vreg: %5[ 103 ]
+# CHECK: Vreg: %95[ 25 ]
+# CHECK: Vreg: %69[ 26 ]
+# CHECK: Vreg: %249[ 40 ]
+# CHECK: Vreg: %294[ 2 ]
+# CHECK: Vreg: %19[ 14 ]
+# CHECK: Vreg: %19:sub0[ 69 ]
+# CHECK: Vreg: %19:sub1[ 70 ]
+# CHECK: Instr: %259:sreg_32 = S_OR_B32 killed %299, killed %300, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 98 ]
+# CHECK: Vreg: %90[ 15 ]
+# CHECK: Vreg: %263[ 6 ]
+# CHECK: Vreg: %71[ 25 ]
+# CHECK: Vreg: %275[ 6 ]
+# CHECK: Vreg: %293[ 4 ]
+# CHECK: Vreg: %40[ 33 ]
+# CHECK: Vreg: %21[ 96 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %92[ 18 ]
+# CHECK: Vreg: %73[ 25 ]
+# CHECK: Vreg: %23[ 54 ]
+# CHECK: Vreg: %4[ 104 ]
+# CHECK: Vreg: %94[ 21 ]
+# CHECK: Vreg: %267[ 6 ]
+# CHECK: Vreg: %248[ 6 ]
+# CHECK: Vreg: %279[ 6 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %30[ 78 ]
+# CHECK: Vreg: %300[ 0 ]
+# CHECK: Vreg: %243[ 7 ]
+# CHECK: Vreg: %96[ 28 ]
+# CHECK: Vreg: %269[ 6 ]
+# CHECK: Vreg: %58[ 29 ]
+# CHECK: Vreg: %37[ 36 ]
+# CHECK: Vreg: %20[ 92 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %264[ 6 ]
+# CHECK: Vreg: %271[ 6 ]
+# CHECK: Vreg: %233[ 3 ]
+# CHECK: Vreg: %22[ 21 ]
+# CHECK: Vreg: %22:sub0[ 44 ]
+# CHECK: Vreg: %22:sub1[ 45 ]
+# CHECK: Vreg: %67[ 25 ]
+# CHECK: Vreg: %3[ 15 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %273[ 6 ]
+# CHECK: Vreg: %43[ 30 ]
+# CHECK: Vreg: %299[ 0 ]
+# CHECK: Vreg: %261[ 6 ]
+# CHECK: Vreg: %5[ 102 ]
+# CHECK: Vreg: %95[ 24 ]
+# CHECK: Vreg: %69[ 25 ]
+# CHECK: Vreg: %249[ 39 ]
+# CHECK: Vreg: %294[ 1 ]
+# CHECK: Vreg: %19[ 13 ]
+# CHECK: Vreg: %19:sub0[ 68 ]
+# CHECK: Vreg: %19:sub1[ 69 ]
+# CHECK: Instr: %301:sreg_32 = S_AND_B32 killed %294, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 97 ]
+# CHECK: Vreg: %90[ 14 ]
+# CHECK: Vreg: %263[ 5 ]
+# CHECK: Vreg: %71[ 24 ]
+# CHECK: Vreg: %275[ 5 ]
+# CHECK: Vreg: %293[ 3 ]
+# CHECK: Vreg: %40[ 32 ]
+# CHECK: Vreg: %21[ 95 ]
+# CHECK: Vreg: %2[ 28 ]
+# CHECK: Vreg: %92[ 17 ]
+# CHECK: Vreg: %73[ 24 ]
+# CHECK: Vreg: %23[ 53 ]
+# CHECK: Vreg: %4[ 103 ]
+# CHECK: Vreg: %94[ 20 ]
+# CHECK: Vreg: %267[ 5 ]
+# CHECK: Vreg: %248[ 5 ]
+# CHECK: Vreg: %279[ 5 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %30[ 77 ]
+# CHECK: Vreg: %243[ 6 ]
+# CHECK: Vreg: %96[ 27 ]
+# CHECK: Vreg: %269[ 5 ]
+# CHECK: Vreg: %58[ 28 ]
+# CHECK: Vreg: %37[ 35 ]
+# CHECK: Vreg: %20[ 91 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %264[ 5 ]
+# CHECK: Vreg: %271[ 5 ]
+# CHECK: Vreg: %233[ 2 ]
+# CHECK: Vreg: %22[ 20 ]
+# CHECK: Vreg: %22:sub0[ 43 ]
+# CHECK: Vreg: %22:sub1[ 44 ]
+# CHECK: Vreg: %67[ 24 ]
+# CHECK: Vreg: %3[ 14 ]
+# CHECK: Vreg: %259[ 5 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %273[ 5 ]
+# CHECK: Vreg: %43[ 29 ]
+# CHECK: Vreg: %261[ 5 ]
+# CHECK: Vreg: %5[ 101 ]
+# CHECK: Vreg: %95[ 23 ]
+# CHECK: Vreg: %69[ 24 ]
+# CHECK: Vreg: %249[ 38 ]
+# CHECK: Vreg: %294[ 0 ]
+# CHECK: Vreg: %19[ 12 ]
+# CHECK: Vreg: %19:sub0[ 67 ]
+# CHECK: Vreg: %19:sub1[ 68 ]
+# CHECK: Instr: %257:sreg_32 = COPY killed %301
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 96 ]
+# CHECK: Vreg: %301[ 0 ]
+# CHECK: Vreg: %90[ 13 ]
+# CHECK: Vreg: %263[ 4 ]
+# CHECK: Vreg: %71[ 23 ]
+# CHECK: Vreg: %275[ 4 ]
+# CHECK: Vreg: %293[ 2 ]
+# CHECK: Vreg: %40[ 31 ]
+# CHECK: Vreg: %21[ 94 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %92[ 16 ]
+# CHECK: Vreg: %73[ 23 ]
+# CHECK: Vreg: %23[ 52 ]
+# CHECK: Vreg: %4[ 102 ]
+# CHECK: Vreg: %94[ 19 ]
+# CHECK: Vreg: %267[ 4 ]
+# CHECK: Vreg: %248[ 4 ]
+# CHECK: Vreg: %279[ 4 ]
+# CHECK: Vreg: %18[ 24 ]
+# CHECK: Vreg: %30[ 76 ]
+# CHECK: Vreg: %243[ 5 ]
+# CHECK: Vreg: %96[ 26 ]
+# CHECK: Vreg: %269[ 4 ]
+# CHECK: Vreg: %58[ 27 ]
+# CHECK: Vreg: %37[ 34 ]
+# CHECK: Vreg: %20[ 90 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %264[ 4 ]
+# CHECK: Vreg: %271[ 4 ]
+# CHECK: Vreg: %233[ 1 ]
+# CHECK: Vreg: %22[ 19 ]
+# CHECK: Vreg: %22:sub0[ 42 ]
+# CHECK: Vreg: %22:sub1[ 43 ]
+# CHECK: Vreg: %67[ 23 ]
+# CHECK: Vreg: %3[ 13 ]
+# CHECK: Vreg: %259[ 4 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %273[ 4 ]
+# CHECK: Vreg: %43[ 28 ]
+# CHECK: Vreg: %261[ 4 ]
+# CHECK: Vreg: %5[ 100 ]
+# CHECK: Vreg: %95[ 22 ]
+# CHECK: Vreg: %69[ 23 ]
+# CHECK: Vreg: %249[ 37 ]
+# CHECK: Vreg: %19[ 11 ]
+# CHECK: Vreg: %19:sub0[ 66 ]
+# CHECK: Vreg: %19:sub1[ 67 ]
+# CHECK: Instr: %302:sreg_32 = S_ANDN2_B32 killed %233, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 95 ]
+# CHECK: Vreg: %90[ 12 ]
+# CHECK: Vreg: %263[ 3 ]
+# CHECK: Vreg: %71[ 22 ]
+# CHECK: Vreg: %275[ 3 ]
+# CHECK: Vreg: %293[ 1 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %21[ 93 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %73[ 22 ]
+# CHECK: Vreg: %23[ 51 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %94[ 18 ]
+# CHECK: Vreg: %267[ 3 ]
+# CHECK: Vreg: %248[ 3 ]
+# CHECK: Vreg: %279[ 3 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %243[ 4 ]
+# CHECK: Vreg: %96[ 25 ]
+# CHECK: Vreg: %269[ 3 ]
+# CHECK: Vreg: %58[ 26 ]
+# CHECK: Vreg: %37[ 33 ]
+# CHECK: Vreg: %20[ 89 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %257[ 3 ]
+# CHECK: Vreg: %264[ 3 ]
+# CHECK: Vreg: %271[ 3 ]
+# CHECK: Vreg: %233[ 0 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %22:sub0[ 41 ]
+# CHECK: Vreg: %22:sub1[ 42 ]
+# CHECK: Vreg: %67[ 22 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %259[ 3 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %273[ 3 ]
+# CHECK: Vreg: %43[ 27 ]
+# CHECK: Vreg: %261[ 3 ]
+# CHECK: Vreg: %5[ 99 ]
+# CHECK: Vreg: %95[ 21 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %249[ 36 ]
+# CHECK: Vreg: %19[ 10 ]
+# CHECK: Vreg: %19:sub0[ 65 ]
+# CHECK: Vreg: %19:sub1[ 66 ]
+# CHECK: Instr: %303:sreg_32 = S_AND_B32 killed %293, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 94 ]
+# CHECK: Vreg: %90[ 11 ]
+# CHECK: Vreg: %263[ 2 ]
+# CHECK: Vreg: %71[ 21 ]
+# CHECK: Vreg: %275[ 2 ]
+# CHECK: Vreg: %293[ 0 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 92 ]
+# CHECK: Vreg: %2[ 25 ]
+# CHECK: Vreg: %92[ 14 ]
+# CHECK: Vreg: %73[ 21 ]
+# CHECK: Vreg: %23[ 50 ]
+# CHECK: Vreg: %4[ 100 ]
+# CHECK: Vreg: %94[ 17 ]
+# CHECK: Vreg: %267[ 2 ]
+# CHECK: Vreg: %248[ 2 ]
+# CHECK: Vreg: %279[ 2 ]
+# CHECK: Vreg: %18[ 22 ]
+# CHECK: Vreg: %30[ 74 ]
+# CHECK: Vreg: %243[ 3 ]
+# CHECK: Vreg: %96[ 24 ]
+# CHECK: Vreg: %269[ 2 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %20[ 88 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %257[ 2 ]
+# CHECK: Vreg: %302[ 1 ]
+# CHECK: Vreg: %264[ 2 ]
+# CHECK: Vreg: %271[ 2 ]
+# CHECK: Vreg: %22[ 17 ]
+# CHECK: Vreg: %22:sub0[ 40 ]
+# CHECK: Vreg: %22:sub1[ 41 ]
+# CHECK: Vreg: %67[ 21 ]
+# CHECK: Vreg: %3[ 11 ]
+# CHECK: Vreg: %259[ 2 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %273[ 2 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %261[ 2 ]
+# CHECK: Vreg: %5[ 98 ]
+# CHECK: Vreg: %95[ 20 ]
+# CHECK: Vreg: %69[ 21 ]
+# CHECK: Vreg: %249[ 35 ]
+# CHECK: Vreg: %19[ 9 ]
+# CHECK: Vreg: %19:sub0[ 64 ]
+# CHECK: Vreg: %19:sub1[ 65 ]
+# CHECK: Instr: %255:sreg_32 = S_OR_B32 killed %302, killed %303, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 93 ]
+# CHECK: Vreg: %90[ 10 ]
+# CHECK: Vreg: %263[ 1 ]
+# CHECK: Vreg: %71[ 20 ]
+# CHECK: Vreg: %275[ 1 ]
+# CHECK: Vreg: %40[ 28 ]
+# CHECK: Vreg: %21[ 91 ]
+# CHECK: Vreg: %2[ 24 ]
+# CHECK: Vreg: %303[ 0 ]
+# CHECK: Vreg: %92[ 13 ]
+# CHECK: Vreg: %73[ 20 ]
+# CHECK: Vreg: %23[ 49 ]
+# CHECK: Vreg: %4[ 99 ]
+# CHECK: Vreg: %94[ 16 ]
+# CHECK: Vreg: %267[ 1 ]
+# CHECK: Vreg: %248[ 1 ]
+# CHECK: Vreg: %279[ 1 ]
+# CHECK: Vreg: %18[ 21 ]
+# CHECK: Vreg: %30[ 73 ]
+# CHECK: Vreg: %243[ 2 ]
+# CHECK: Vreg: %96[ 23 ]
+# CHECK: Vreg: %269[ 1 ]
+# CHECK: Vreg: %58[ 24 ]
+# CHECK: Vreg: %37[ 31 ]
+# CHECK: Vreg: %20[ 87 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %257[ 1 ]
+# CHECK: Vreg: %302[ 0 ]
+# CHECK: Vreg: %264[ 1 ]
+# CHECK: Vreg: %271[ 1 ]
+# CHECK: Vreg: %22[ 16 ]
+# CHECK: Vreg: %22:sub0[ 39 ]
+# CHECK: Vreg: %22:sub1[ 40 ]
+# CHECK: Vreg: %67[ 20 ]
+# CHECK: Vreg: %3[ 10 ]
+# CHECK: Vreg: %259[ 1 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %273[ 1 ]
+# CHECK: Vreg: %43[ 25 ]
+# CHECK: Vreg: %261[ 1 ]
+# CHECK: Vreg: %5[ 97 ]
+# CHECK: Vreg: %95[ 19 ]
+# CHECK: Vreg: %69[ 20 ]
+# CHECK: Vreg: %249[ 34 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ 63 ]
+# CHECK: Vreg: %19:sub1[ 64 ]
+# CHECK: Instr: S_BRANCH %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %263[ 0 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %267[ 0 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %255[ 0 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %257[ 0 ]
+# CHECK: Vreg: %264[ 0 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %259[ 0 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %261[ 0 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %263[ 0 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %275[ 0 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %267[ 0 ]
+# CHECK: Vreg: %248[ 0 ]
+# CHECK: Vreg: %279[ 0 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %255[ 0 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %243[ 1 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %269[ 0 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %257[ 0 ]
+# CHECK: Vreg: %264[ 0 ]
+# CHECK: Vreg: %271[ 0 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %259[ 0 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %273[ 0 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %261[ 0 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: --- MBB_16 ---
+# CHECK: Instr: %304:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 117 ]
+# CHECK: Vreg: %256[ 27 ]
+# CHECK: Vreg: %90[ 34 ]
+# CHECK: Vreg: %71[ 37 ]
+# CHECK: Vreg: %40[ 52 ]
+# CHECK: Vreg: %21[ 115 ]
+# CHECK: Vreg: %2[ 18 ]
+# CHECK: Vreg: %111[ 44 ]
+# CHECK: Vreg: %92[ 37 ]
+# CHECK: Vreg: %73[ 41 ]
+# CHECK: Vreg: %258[ 1 ]
+# CHECK: Vreg: %23[ 73 ]
+# CHECK: Vreg: %4[ 123 ]
+# CHECK: Vreg: %260[ 14 ]
+# CHECK: Vreg: %94[ 40 ]
+# CHECK: Vreg: %30[ 97 ]
+# CHECK: Vreg: %37[ 55 ]
+# CHECK: Vreg: %18[ 15 ]
+# CHECK: Vreg: %281[ 30 ]
+# CHECK: Vreg: %262[ 14 ]
+# CHECK: Vreg: %96[ 47 ]
+# CHECK: Vreg: %58[ 48 ]
+# CHECK: Vreg: %20[ 111 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %65[ 41 ]
+# CHECK: Vreg: %276[ 32 ]
+# CHECK: Vreg: %22[ 10 ]
+# CHECK: Vreg: %67[ 41 ]
+# CHECK: Vreg: %112[ 44 ]
+# CHECK: Vreg: %278[ 9 ]
+# CHECK: Vreg: %3[ 34 ]
+# CHECK: Vreg: %43[ 49 ]
+# CHECK: Vreg: %5[ 121 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %95[ 43 ]
+# CHECK: Vreg: %249[ 28 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Instr: %305:sreg_32 = S_XOR_B32 killed %258, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 116 ]
+# CHECK: Vreg: %256[ 26 ]
+# CHECK: Vreg: %90[ 33 ]
+# CHECK: Vreg: %71[ 36 ]
+# CHECK: Vreg: %40[ 51 ]
+# CHECK: Vreg: %21[ 114 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %111[ 43 ]
+# CHECK: Vreg: %92[ 36 ]
+# CHECK: Vreg: %73[ 40 ]
+# CHECK: Vreg: %258[ 0 ]
+# CHECK: Vreg: %23[ 72 ]
+# CHECK: Vreg: %4[ 122 ]
+# CHECK: Vreg: %260[ 13 ]
+# CHECK: Vreg: %94[ 39 ]
+# CHECK: Vreg: %30[ 96 ]
+# CHECK: Vreg: %37[ 54 ]
+# CHECK: Vreg: %18[ 14 ]
+# CHECK: Vreg: %281[ 29 ]
+# CHECK: Vreg: %262[ 13 ]
+# CHECK: Vreg: %96[ 46 ]
+# CHECK: Vreg: %58[ 47 ]
+# CHECK: Vreg: %20[ 110 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %65[ 40 ]
+# CHECK: Vreg: %276[ 31 ]
+# CHECK: Vreg: %22[ 9 ]
+# CHECK: Vreg: %67[ 40 ]
+# CHECK: Vreg: %112[ 43 ]
+# CHECK: Vreg: %278[ 8 ]
+# CHECK: Vreg: %3[ 33 ]
+# CHECK: Vreg: %304[ 13 ]
+# CHECK: Vreg: %43[ 48 ]
+# CHECK: Vreg: %5[ 120 ]
+# CHECK: Vreg: %69[ 21 ]
+# CHECK: Vreg: %95[ 42 ]
+# CHECK: Vreg: %249[ 27 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: %306:vgpr_32 = GLOBAL_LOAD_UBYTE %19, 0, 0, implicit $exec :: (load (s8) from %ir.p5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 115 ]
+# CHECK: Vreg: %256[ 25 ]
+# CHECK: Vreg: %90[ 32 ]
+# CHECK: Vreg: %71[ 35 ]
+# CHECK: Vreg: %40[ 50 ]
+# CHECK: Vreg: %21[ 113 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %111[ 42 ]
+# CHECK: Vreg: %92[ 35 ]
+# CHECK: Vreg: %73[ 39 ]
+# CHECK: Vreg: %23[ 71 ]
+# CHECK: Vreg: %4[ 121 ]
+# CHECK: Vreg: %260[ 12 ]
+# CHECK: Vreg: %94[ 38 ]
+# CHECK: Vreg: %30[ 95 ]
+# CHECK: Vreg: %305[ 11 ]
+# CHECK: Vreg: %37[ 53 ]
+# CHECK: Vreg: %18[ 13 ]
+# CHECK: Vreg: %281[ 28 ]
+# CHECK: Vreg: %262[ 12 ]
+# CHECK: Vreg: %96[ 45 ]
+# CHECK: Vreg: %58[ 46 ]
+# CHECK: Vreg: %20[ 109 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %65[ 39 ]
+# CHECK: Vreg: %276[ 30 ]
+# CHECK: Vreg: %22[ 8 ]
+# CHECK: Vreg: %67[ 39 ]
+# CHECK: Vreg: %112[ 42 ]
+# CHECK: Vreg: %278[ 7 ]
+# CHECK: Vreg: %3[ 32 ]
+# CHECK: Vreg: %304[ 12 ]
+# CHECK: Vreg: %43[ 47 ]
+# CHECK: Vreg: %5[ 119 ]
+# CHECK: Vreg: %69[ 20 ]
+# CHECK: Vreg: %95[ 41 ]
+# CHECK: Vreg: %249[ 26 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %307:vgpr_32 = GLOBAL_LOAD_UBYTE %19, 1, 0, implicit $exec :: (load (s8) from %ir.p5 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 114 ]
+# CHECK: Vreg: %256[ 24 ]
+# CHECK: Vreg: %90[ 31 ]
+# CHECK: Vreg: %71[ 34 ]
+# CHECK: Vreg: %306[ 1 ]
+# CHECK: Vreg: %40[ 49 ]
+# CHECK: Vreg: %21[ 112 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %111[ 41 ]
+# CHECK: Vreg: %92[ 34 ]
+# CHECK: Vreg: %73[ 38 ]
+# CHECK: Vreg: %23[ 70 ]
+# CHECK: Vreg: %4[ 120 ]
+# CHECK: Vreg: %260[ 11 ]
+# CHECK: Vreg: %94[ 37 ]
+# CHECK: Vreg: %30[ 94 ]
+# CHECK: Vreg: %305[ 10 ]
+# CHECK: Vreg: %37[ 52 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %281[ 27 ]
+# CHECK: Vreg: %262[ 11 ]
+# CHECK: Vreg: %96[ 44 ]
+# CHECK: Vreg: %58[ 45 ]
+# CHECK: Vreg: %20[ 108 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %65[ 38 ]
+# CHECK: Vreg: %276[ 29 ]
+# CHECK: Vreg: %22[ 7 ]
+# CHECK: Vreg: %67[ 38 ]
+# CHECK: Vreg: %112[ 41 ]
+# CHECK: Vreg: %278[ 6 ]
+# CHECK: Vreg: %3[ 31 ]
+# CHECK: Vreg: %304[ 11 ]
+# CHECK: Vreg: %43[ 46 ]
+# CHECK: Vreg: %5[ 118 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %95[ 40 ]
+# CHECK: Vreg: %249[ 25 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %308:vgpr_32 = V_LSHL_OR_B32_e64 killed %307, 8, killed %306, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 113 ]
+# CHECK: Vreg: %256[ 23 ]
+# CHECK: Vreg: %90[ 30 ]
+# CHECK: Vreg: %71[ 33 ]
+# CHECK: Vreg: %306[ 0 ]
+# CHECK: Vreg: %40[ 48 ]
+# CHECK: Vreg: %21[ 111 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %111[ 40 ]
+# CHECK: Vreg: %92[ 33 ]
+# CHECK: Vreg: %73[ 37 ]
+# CHECK: Vreg: %23[ 69 ]
+# CHECK: Vreg: %4[ 119 ]
+# CHECK: Vreg: %260[ 10 ]
+# CHECK: Vreg: %94[ 36 ]
+# CHECK: Vreg: %30[ 93 ]
+# CHECK: Vreg: %305[ 9 ]
+# CHECK: Vreg: %37[ 51 ]
+# CHECK: Vreg: %18[ 11 ]
+# CHECK: Vreg: %281[ 26 ]
+# CHECK: Vreg: %262[ 10 ]
+# CHECK: Vreg: %307[ 0 ]
+# CHECK: Vreg: %96[ 43 ]
+# CHECK: Vreg: %58[ 44 ]
+# CHECK: Vreg: %20[ 107 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %65[ 37 ]
+# CHECK: Vreg: %276[ 28 ]
+# CHECK: Vreg: %22[ 6 ]
+# CHECK: Vreg: %67[ 37 ]
+# CHECK: Vreg: %112[ 40 ]
+# CHECK: Vreg: %278[ 5 ]
+# CHECK: Vreg: %3[ 30 ]
+# CHECK: Vreg: %304[ 10 ]
+# CHECK: Vreg: %43[ 45 ]
+# CHECK: Vreg: %5[ 117 ]
+# CHECK: Vreg: %69[ 18 ]
+# CHECK: Vreg: %95[ 39 ]
+# CHECK: Vreg: %249[ 24 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: %309:vgpr_32 = GLOBAL_LOAD_UBYTE %19, 2, 0, implicit $exec :: (load (s8) from %ir.p5 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %71[ 32 ]
+# CHECK: Vreg: %308[ 3 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %73[ 36 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %305[ 8 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 9 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %65[ 36 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %22[ 5 ]
+# CHECK: Vreg: %67[ 36 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %278[ 4 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %304[ 9 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 17 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %310:vgpr_32 = GLOBAL_LOAD_UBYTE %19, 3, 0, implicit $exec :: (load (s8) from %ir.p5 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 111 ]
+# CHECK: Vreg: %256[ 21 ]
+# CHECK: Vreg: %90[ 28 ]
+# CHECK: Vreg: %71[ 31 ]
+# CHECK: Vreg: %308[ 2 ]
+# CHECK: Vreg: %40[ 46 ]
+# CHECK: Vreg: %21[ 109 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %111[ 38 ]
+# CHECK: Vreg: %92[ 31 ]
+# CHECK: Vreg: %73[ 35 ]
+# CHECK: Vreg: %23[ 67 ]
+# CHECK: Vreg: %4[ 117 ]
+# CHECK: Vreg: %260[ 8 ]
+# CHECK: Vreg: %94[ 34 ]
+# CHECK: Vreg: %30[ 91 ]
+# CHECK: Vreg: %305[ 7 ]
+# CHECK: Vreg: %37[ 49 ]
+# CHECK: Vreg: %18[ 9 ]
+# CHECK: Vreg: %281[ 24 ]
+# CHECK: Vreg: %262[ 8 ]
+# CHECK: Vreg: %96[ 41 ]
+# CHECK: Vreg: %58[ 42 ]
+# CHECK: Vreg: %20[ 105 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %65[ 35 ]
+# CHECK: Vreg: %276[ 26 ]
+# CHECK: Vreg: %309[ 1 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: Vreg: %67[ 35 ]
+# CHECK: Vreg: %112[ 38 ]
+# CHECK: Vreg: %278[ 3 ]
+# CHECK: Vreg: %3[ 28 ]
+# CHECK: Vreg: %304[ 8 ]
+# CHECK: Vreg: %43[ 43 ]
+# CHECK: Vreg: %5[ 115 ]
+# CHECK: Vreg: %69[ 16 ]
+# CHECK: Vreg: %95[ 37 ]
+# CHECK: Vreg: %249[ 22 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %311:vgpr_32 = V_LSHL_OR_B32_e64 killed %310, 8, killed %309, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 110 ]
+# CHECK: Vreg: %256[ 20 ]
+# CHECK: Vreg: %90[ 27 ]
+# CHECK: Vreg: %71[ 30 ]
+# CHECK: Vreg: %308[ 1 ]
+# CHECK: Vreg: %40[ 45 ]
+# CHECK: Vreg: %21[ 108 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %111[ 37 ]
+# CHECK: Vreg: %92[ 30 ]
+# CHECK: Vreg: %73[ 34 ]
+# CHECK: Vreg: %310[ 0 ]
+# CHECK: Vreg: %23[ 66 ]
+# CHECK: Vreg: %4[ 116 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 33 ]
+# CHECK: Vreg: %30[ 90 ]
+# CHECK: Vreg: %305[ 6 ]
+# CHECK: Vreg: %37[ 48 ]
+# CHECK: Vreg: %18[ 8 ]
+# CHECK: Vreg: %281[ 23 ]
+# CHECK: Vreg: %262[ 7 ]
+# CHECK: Vreg: %96[ 40 ]
+# CHECK: Vreg: %58[ 41 ]
+# CHECK: Vreg: %20[ 104 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %65[ 34 ]
+# CHECK: Vreg: %276[ 25 ]
+# CHECK: Vreg: %309[ 0 ]
+# CHECK: Vreg: %22[ 3 ]
+# CHECK: Vreg: %67[ 34 ]
+# CHECK: Vreg: %112[ 37 ]
+# CHECK: Vreg: %278[ 2 ]
+# CHECK: Vreg: %3[ 27 ]
+# CHECK: Vreg: %304[ 7 ]
+# CHECK: Vreg: %43[ 42 ]
+# CHECK: Vreg: %5[ 114 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %95[ 36 ]
+# CHECK: Vreg: %249[ 21 ]
+# CHECK: Vreg: %19:sub0[ 80 ]
+# CHECK: Vreg: %19:sub1[ 81 ]
+# CHECK: Vreg: %19[ 93 ]
+# CHECK: Instr: %312:vgpr_32 = V_LSHL_OR_B32_e64 killed %311, 16, killed %308, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 109 ]
+# CHECK: Vreg: %256[ 19 ]
+# CHECK: Vreg: %90[ 26 ]
+# CHECK: Vreg: %71[ 29 ]
+# CHECK: Vreg: %308[ 0 ]
+# CHECK: Vreg: %40[ 44 ]
+# CHECK: Vreg: %21[ 107 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %111[ 36 ]
+# CHECK: Vreg: %92[ 29 ]
+# CHECK: Vreg: %73[ 33 ]
+# CHECK: Vreg: %23[ 65 ]
+# CHECK: Vreg: %4[ 115 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 32 ]
+# CHECK: Vreg: %30[ 89 ]
+# CHECK: Vreg: %305[ 5 ]
+# CHECK: Vreg: %37[ 47 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %281[ 22 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 39 ]
+# CHECK: Vreg: %58[ 40 ]
+# CHECK: Vreg: %20[ 103 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %65[ 33 ]
+# CHECK: Vreg: %276[ 24 ]
+# CHECK: Vreg: %22[ 2 ]
+# CHECK: Vreg: %67[ 33 ]
+# CHECK: Vreg: %112[ 36 ]
+# CHECK: Vreg: %278[ 1 ]
+# CHECK: Vreg: %3[ 26 ]
+# CHECK: Vreg: %304[ 6 ]
+# CHECK: Vreg: %311[ 0 ]
+# CHECK: Vreg: %43[ 41 ]
+# CHECK: Vreg: %5[ 113 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %95[ 35 ]
+# CHECK: Vreg: %249[ 20 ]
+# CHECK: Vreg: %19:sub0[ 79 ]
+# CHECK: Vreg: %19:sub1[ 80 ]
+# CHECK: Vreg: %19[ 92 ]
+# CHECK: Instr: %313:vgpr_32 = V_MUL_LO_U32_e64 killed %312, %278, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 108 ]
+# CHECK: Vreg: %256[ 18 ]
+# CHECK: Vreg: %90[ 25 ]
+# CHECK: Vreg: %71[ 28 ]
+# CHECK: Vreg: %40[ 43 ]
+# CHECK: Vreg: %21[ 106 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %111[ 35 ]
+# CHECK: Vreg: %92[ 28 ]
+# CHECK: Vreg: %73[ 32 ]
+# CHECK: Vreg: %23[ 64 ]
+# CHECK: Vreg: %4[ 114 ]
+# CHECK: Vreg: %260[ 5 ]
+# CHECK: Vreg: %94[ 31 ]
+# CHECK: Vreg: %30[ 88 ]
+# CHECK: Vreg: %305[ 4 ]
+# CHECK: Vreg: %37[ 46 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %312[ 0 ]
+# CHECK: Vreg: %281[ 21 ]
+# CHECK: Vreg: %262[ 5 ]
+# CHECK: Vreg: %96[ 38 ]
+# CHECK: Vreg: %58[ 39 ]
+# CHECK: Vreg: %20[ 102 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %65[ 32 ]
+# CHECK: Vreg: %276[ 23 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %67[ 32 ]
+# CHECK: Vreg: %112[ 35 ]
+# CHECK: Vreg: %278[ 0 ]
+# CHECK: Vreg: %3[ 25 ]
+# CHECK: Vreg: %304[ 5 ]
+# CHECK: Vreg: %43[ 40 ]
+# CHECK: Vreg: %5[ 112 ]
+# CHECK: Vreg: %69[ 13 ]
+# CHECK: Vreg: %95[ 34 ]
+# CHECK: Vreg: %249[ 19 ]
+# CHECK: Vreg: %19:sub0[ 78 ]
+# CHECK: Vreg: %19:sub1[ 79 ]
+# CHECK: Vreg: %19[ 91 ]
+# CHECK: Instr: GLOBAL_STORE_SHORT_D16_HI %22, %313, 2, 0, implicit $exec :: (store (s16) into %ir.p2 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 107 ]
+# CHECK: Vreg: %256[ 17 ]
+# CHECK: Vreg: %90[ 24 ]
+# CHECK: Vreg: %71[ 27 ]
+# CHECK: Vreg: %40[ 42 ]
+# CHECK: Vreg: %21[ 105 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %111[ 34 ]
+# CHECK: Vreg: %92[ 27 ]
+# CHECK: Vreg: %73[ 31 ]
+# CHECK: Vreg: %23[ 63 ]
+# CHECK: Vreg: %4[ 113 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 30 ]
+# CHECK: Vreg: %30[ 87 ]
+# CHECK: Vreg: %305[ 3 ]
+# CHECK: Vreg: %37[ 45 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %281[ 20 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 37 ]
+# CHECK: Vreg: %58[ 38 ]
+# CHECK: Vreg: %20[ 101 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %65[ 31 ]
+# CHECK: Vreg: %276[ 22 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %67[ 31 ]
+# CHECK: Vreg: %112[ 34 ]
+# CHECK: Vreg: %278[ 19 ]
+# CHECK: Vreg: %3[ 24 ]
+# CHECK: Vreg: %304[ 4 ]
+# CHECK: Vreg: %43[ 39 ]
+# CHECK: Vreg: %5[ 111 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %95[ 33 ]
+# CHECK: Vreg: %249[ 18 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 77 ]
+# CHECK: Vreg: %19:sub1[ 78 ]
+# CHECK: Vreg: %19[ 90 ]
+# CHECK: Instr: GLOBAL_STORE_SHORT %22, %313, 0, 0, implicit $exec :: (store (s16) into %ir.p2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 106 ]
+# CHECK: Vreg: %256[ 16 ]
+# CHECK: Vreg: %90[ 23 ]
+# CHECK: Vreg: %71[ 26 ]
+# CHECK: Vreg: %40[ 41 ]
+# CHECK: Vreg: %21[ 104 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %111[ 33 ]
+# CHECK: Vreg: %92[ 26 ]
+# CHECK: Vreg: %73[ 30 ]
+# CHECK: Vreg: %23[ 62 ]
+# CHECK: Vreg: %4[ 112 ]
+# CHECK: Vreg: %260[ 3 ]
+# CHECK: Vreg: %94[ 29 ]
+# CHECK: Vreg: %30[ 86 ]
+# CHECK: Vreg: %305[ 2 ]
+# CHECK: Vreg: %37[ 44 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %281[ 19 ]
+# CHECK: Vreg: %262[ 3 ]
+# CHECK: Vreg: %96[ 36 ]
+# CHECK: Vreg: %58[ 37 ]
+# CHECK: Vreg: %20[ 100 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %65[ 30 ]
+# CHECK: Vreg: %276[ 21 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %67[ 30 ]
+# CHECK: Vreg: %112[ 33 ]
+# CHECK: Vreg: %278[ 18 ]
+# CHECK: Vreg: %3[ 23 ]
+# CHECK: Vreg: %304[ 3 ]
+# CHECK: Vreg: %43[ 38 ]
+# CHECK: Vreg: %5[ 110 ]
+# CHECK: Vreg: %69[ 11 ]
+# CHECK: Vreg: %95[ 32 ]
+# CHECK: Vreg: %249[ 17 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 76 ]
+# CHECK: Vreg: %19:sub1[ 77 ]
+# CHECK: Vreg: %19[ 89 ]
+# CHECK: Instr: %314:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 105 ]
+# CHECK: Vreg: %256[ 15 ]
+# CHECK: Vreg: %90[ 22 ]
+# CHECK: Vreg: %71[ 25 ]
+# CHECK: Vreg: %40[ 40 ]
+# CHECK: Vreg: %21[ 103 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %111[ 32 ]
+# CHECK: Vreg: %92[ 25 ]
+# CHECK: Vreg: %73[ 29 ]
+# CHECK: Vreg: %23[ 61 ]
+# CHECK: Vreg: %4[ 111 ]
+# CHECK: Vreg: %260[ 2 ]
+# CHECK: Vreg: %94[ 28 ]
+# CHECK: Vreg: %30[ 85 ]
+# CHECK: Vreg: %305[ 1 ]
+# CHECK: Vreg: %37[ 43 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %281[ 18 ]
+# CHECK: Vreg: %262[ 2 ]
+# CHECK: Vreg: %96[ 35 ]
+# CHECK: Vreg: %58[ 36 ]
+# CHECK: Vreg: %20[ 99 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %65[ 29 ]
+# CHECK: Vreg: %276[ 20 ]
+# CHECK: Vreg: %22:sub0[ 51 ]
+# CHECK: Vreg: %22:sub1[ 52 ]
+# CHECK: Vreg: %22[ 116 ]
+# CHECK: Vreg: %67[ 29 ]
+# CHECK: Vreg: %112[ 32 ]
+# CHECK: Vreg: %278[ 17 ]
+# CHECK: Vreg: %3[ 22 ]
+# CHECK: Vreg: %304[ 2 ]
+# CHECK: Vreg: %43[ 37 ]
+# CHECK: Vreg: %5[ 109 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 31 ]
+# CHECK: Vreg: %249[ 16 ]
+# CHECK: Vreg: %313[ 2 ]
+# CHECK: Vreg: %19:sub0[ 75 ]
+# CHECK: Vreg: %19:sub1[ 76 ]
+# CHECK: Vreg: %19[ 88 ]
+# CHECK: Instr: %315:sreg_32 = SI_IF killed %305, %bb.23, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %256[ 14 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %71[ 24 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %111[ 31 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 28 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %260[ 1 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %305[ 0 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %281[ 17 ]
+# CHECK: Vreg: %262[ 1 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %314[ 1 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %65[ 28 ]
+# CHECK: Vreg: %276[ 19 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %22[ 115 ]
+# CHECK: Vreg: %67[ 28 ]
+# CHECK: Vreg: %112[ 31 ]
+# CHECK: Vreg: %278[ 16 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %304[ 1 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %249[ 15 ]
+# CHECK: Vreg: %313[ 1 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Vreg: %19[ 87 ]
+# CHECK: Instr: S_BRANCH %bb.18
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %71[ 23 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %73[ 27 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %314[ 0 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %65[ 27 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 27 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %278[ 15 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %304[ 0 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %71[ 23 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %73[ 27 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %314[ 0 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %65[ 27 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 27 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %278[ 15 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %304[ 0 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: --- MBB_17 ---
+# CHECK: Instr: %316:sreg_32 = PHI %256, %bb.12, %317, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %256[ 0 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %319[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %330[ 0 ]
+# CHECK: Vreg: %323[ 0 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %317[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %321[ 0 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %328[ 0 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %280[ 0 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %325[ 0 ]
+# CHECK: Vreg: %242[ 0 ]
+# CHECK: Vreg: %332[ 0 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %318:sreg_32 = PHI %242, %bb.12, %319, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %319[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %330[ 0 ]
+# CHECK: Vreg: %323[ 0 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %321[ 0 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %328[ 0 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %280[ 0 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %325[ 0 ]
+# CHECK: Vreg: %242[ 0 ]
+# CHECK: Vreg: %332[ 0 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %320:sreg_32 = PHI %260, %bb.12, %321, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %330[ 0 ]
+# CHECK: Vreg: %323[ 0 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %321[ 0 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %328[ 0 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %280[ 0 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %325[ 0 ]
+# CHECK: Vreg: %332[ 0 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %322:sreg_32 = PHI %262, %bb.12, %323, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %330[ 0 ]
+# CHECK: Vreg: %323[ 0 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %328[ 0 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %280[ 0 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %325[ 0 ]
+# CHECK: Vreg: %332[ 0 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %324:sreg_32 = PHI %280, %bb.12, %325, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %330[ 0 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %328[ 0 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %280[ 0 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %325[ 0 ]
+# CHECK: Vreg: %332[ 0 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %326:vgpr_32 = PHI undef %327:vgpr_32, %bb.12, %328, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %330[ 0 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %328[ 0 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %332[ 0 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %329:vgpr_32 = PHI undef %327:vgpr_32, %bb.12, %330, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %326[ 3 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %330[ 0 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %332[ 0 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %331:vgpr_32 = PHI undef %327:vgpr_32, %bb.12, %332, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %329[ 3 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %326[ 3 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %332[ 0 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %333:vgpr_32 = PHI undef %327:vgpr_32, %bb.12, %334, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %329[ 3 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %326[ 3 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %331[ 3 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %335:vgpr_32 = PHI undef %327:vgpr_32, %bb.12, %336, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %329[ 3 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %326[ 3 ]
+# CHECK: Vreg: %333[ 3 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %331[ 3 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %337:vgpr_32 = PHI undef %338:vgpr_32, %bb.12, %339, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %329[ 3 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %326[ 3 ]
+# CHECK: Vreg: %333[ 3 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %331[ 3 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %335[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Instr: %340:vgpr_32 = PHI %265, %bb.12, %341, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %329[ 3 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %326[ 3 ]
+# CHECK: Vreg: %333[ 3 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %337[ 3 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %265[ 0 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %331[ 3 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %335[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Instr: %342:vgpr_32 = PHI %268, %bb.12, %343, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %329[ 3 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %326[ 3 ]
+# CHECK: Vreg: %333[ 3 ]
+# CHECK: Vreg: %340[ 3 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %337[ 3 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %268[ 0 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %331[ 3 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %335[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Instr: %344:vgpr_32 = PHI %270, %bb.12, %345, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %270[ 0 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %329[ 3 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %326[ 3 ]
+# CHECK: Vreg: %333[ 3 ]
+# CHECK: Vreg: %340[ 3 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %337[ 3 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %331[ 3 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %335[ 3 ]
+# CHECK: Vreg: %342[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Instr: %346:vgpr_32 = PHI %272, %bb.12, %347, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %329[ 3 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %326[ 3 ]
+# CHECK: Vreg: %333[ 3 ]
+# CHECK: Vreg: %340[ 3 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %337[ 3 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %344[ 3 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %272[ 0 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %331[ 3 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %335[ 3 ]
+# CHECK: Vreg: %342[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Instr: %348:vgpr_32 = PHI %274, %bb.12, %349, %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %346[ 3 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %329[ 3 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %274[ 0 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %326[ 3 ]
+# CHECK: Vreg: %333[ 3 ]
+# CHECK: Vreg: %340[ 3 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %316[ 2 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %337[ 3 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %344[ 3 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %324[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %331[ 3 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %335[ 3 ]
+# CHECK: Vreg: %342[ 3 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Instr: SI_END_CF killed %281, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 87 ]
+# CHECK: Vreg: %320[ 2 ]
+# CHECK: Vreg: %90[ 4 ]
+# CHECK: Vreg: %71[ 14 ]
+# CHECK: Vreg: %346[ 2 ]
+# CHECK: Vreg: %40[ 22 ]
+# CHECK: Vreg: %21[ 85 ]
+# CHECK: Vreg: %322[ 2 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 7 ]
+# CHECK: Vreg: %73[ 14 ]
+# CHECK: Vreg: %329[ 2 ]
+# CHECK: Vreg: %348[ 2 ]
+# CHECK: Vreg: %2[ 106 ]
+# CHECK: Vreg: %23[ 43 ]
+# CHECK: Vreg: %4[ 93 ]
+# CHECK: Vreg: %324[ 2 ]
+# CHECK: Vreg: %94[ 10 ]
+# CHECK: Vreg: %331[ 2 ]
+# CHECK: Vreg: %30[ 67 ]
+# CHECK: Vreg: %18[ 103 ]
+# CHECK: Vreg: %37[ 25 ]
+# CHECK: Vreg: %281[ 0 ]
+# CHECK: Vreg: %326[ 2 ]
+# CHECK: Vreg: %96[ 17 ]
+# CHECK: Vreg: %333[ 2 ]
+# CHECK: Vreg: %58[ 18 ]
+# CHECK: Vreg: %20[ 81 ]
+# CHECK: Vreg: %1[ 122 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %340[ 2 ]
+# CHECK: Vreg: %276[ 2 ]
+# CHECK: Vreg: %335[ 2 ]
+# CHECK: Vreg: %316[ 1 ]
+# CHECK: Vreg: %22:sub0[ 33 ]
+# CHECK: Vreg: %22:sub1[ 34 ]
+# CHECK: Vreg: %22[ 98 ]
+# CHECK: Vreg: %67[ 14 ]
+# CHECK: Vreg: %112[ 14 ]
+# CHECK: Vreg: %342[ 2 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %337[ 2 ]
+# CHECK: Vreg: %318[ 2 ]
+# CHECK: Vreg: %43[ 19 ]
+# CHECK: Vreg: %344[ 2 ]
+# CHECK: Vreg: %5[ 91 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %95[ 13 ]
+# CHECK: Vreg: %19:sub0[ 57 ]
+# CHECK: Vreg: %19:sub1[ 58 ]
+# CHECK: Vreg: %19[ 70 ]
+# CHECK: Instr: %350:sreg_32 = SI_IF killed %316, %bb.33, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 86 ]
+# CHECK: Vreg: %320[ 1 ]
+# CHECK: Vreg: %90[ 3 ]
+# CHECK: Vreg: %71[ 13 ]
+# CHECK: Vreg: %346[ 1 ]
+# CHECK: Vreg: %40[ 21 ]
+# CHECK: Vreg: %21[ 84 ]
+# CHECK: Vreg: %322[ 1 ]
+# CHECK: Vreg: %111[ 13 ]
+# CHECK: Vreg: %92[ 6 ]
+# CHECK: Vreg: %73[ 13 ]
+# CHECK: Vreg: %329[ 1 ]
+# CHECK: Vreg: %348[ 1 ]
+# CHECK: Vreg: %2[ 105 ]
+# CHECK: Vreg: %23[ 42 ]
+# CHECK: Vreg: %4[ 92 ]
+# CHECK: Vreg: %324[ 1 ]
+# CHECK: Vreg: %94[ 9 ]
+# CHECK: Vreg: %331[ 1 ]
+# CHECK: Vreg: %30[ 66 ]
+# CHECK: Vreg: %18[ 102 ]
+# CHECK: Vreg: %37[ 24 ]
+# CHECK: Vreg: %326[ 1 ]
+# CHECK: Vreg: %96[ 16 ]
+# CHECK: Vreg: %333[ 1 ]
+# CHECK: Vreg: %58[ 17 ]
+# CHECK: Vreg: %20[ 80 ]
+# CHECK: Vreg: %1[ 121 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %340[ 1 ]
+# CHECK: Vreg: %276[ 1 ]
+# CHECK: Vreg: %335[ 1 ]
+# CHECK: Vreg: %316[ 0 ]
+# CHECK: Vreg: %22:sub0[ 32 ]
+# CHECK: Vreg: %22:sub1[ 33 ]
+# CHECK: Vreg: %22[ 97 ]
+# CHECK: Vreg: %67[ 13 ]
+# CHECK: Vreg: %112[ 13 ]
+# CHECK: Vreg: %342[ 1 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Vreg: %337[ 1 ]
+# CHECK: Vreg: %318[ 1 ]
+# CHECK: Vreg: %43[ 18 ]
+# CHECK: Vreg: %344[ 1 ]
+# CHECK: Vreg: %5[ 90 ]
+# CHECK: Vreg: %69[ 13 ]
+# CHECK: Vreg: %95[ 12 ]
+# CHECK: Vreg: %19:sub0[ 56 ]
+# CHECK: Vreg: %19:sub1[ 57 ]
+# CHECK: Vreg: %19[ 69 ]
+# CHECK: Instr: S_BRANCH %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %320[ 0 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %71[ 12 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %322[ 0 ]
+# CHECK: Vreg: %111[ 12 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %73[ 12 ]
+# CHECK: Vreg: %329[ 0 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %324[ 0 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %331[ 0 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %326[ 0 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %333[ 0 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %67[ 12 ]
+# CHECK: Vreg: %112[ 12 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %318[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %320[ 0 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %71[ 12 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %322[ 0 ]
+# CHECK: Vreg: %111[ 12 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %73[ 12 ]
+# CHECK: Vreg: %329[ 0 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %324[ 0 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %331[ 0 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %326[ 0 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %333[ 0 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %67[ 12 ]
+# CHECK: Vreg: %112[ 12 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %318[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: --- MBB_18 ---
+# CHECK: Instr: %351:vgpr_32 = GLOBAL_LOAD_UBYTE %18, 0, 0, implicit $exec :: (load (s8) from %ir.p6, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 129 ]
+# CHECK: Vreg: %256[ 39 ]
+# CHECK: Vreg: %90[ 46 ]
+# CHECK: Vreg: %71[ 22 ]
+# CHECK: Vreg: %315[ 27 ]
+# CHECK: Vreg: %40[ 64 ]
+# CHECK: Vreg: %21[ 127 ]
+# CHECK: Vreg: %2[ 30 ]
+# CHECK: Vreg: %111[ 56 ]
+# CHECK: Vreg: %92[ 49 ]
+# CHECK: Vreg: %73[ 26 ]
+# CHECK: Vreg: %23[ 85 ]
+# CHECK: Vreg: %4[ 135 ]
+# CHECK: Vreg: %260[ 23 ]
+# CHECK: Vreg: %94[ 52 ]
+# CHECK: Vreg: %30[ 109 ]
+# CHECK: Vreg: %37[ 67 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %281[ 42 ]
+# CHECK: Vreg: %262[ 21 ]
+# CHECK: Vreg: %96[ 59 ]
+# CHECK: Vreg: %58[ 60 ]
+# CHECK: Vreg: %20[ 123 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %65[ 26 ]
+# CHECK: Vreg: %276[ 44 ]
+# CHECK: Vreg: %22:sub0[ 75 ]
+# CHECK: Vreg: %22:sub1[ 76 ]
+# CHECK: Vreg: %22[ 140 ]
+# CHECK: Vreg: %67[ 26 ]
+# CHECK: Vreg: %112[ 56 ]
+# CHECK: Vreg: %278[ 14 ]
+# CHECK: Vreg: %3[ 46 ]
+# CHECK: Vreg: %43[ 61 ]
+# CHECK: Vreg: %5[ 133 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %95[ 55 ]
+# CHECK: Vreg: %249[ 40 ]
+# CHECK: Vreg: %19:sub0[ 99 ]
+# CHECK: Vreg: %19:sub1[ 100 ]
+# CHECK: Vreg: %19[ 112 ]
+# CHECK: Instr: %352:vgpr_32 = GLOBAL_LOAD_UBYTE %18, 1, 0, implicit $exec :: (load (s8) from %ir.p6 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 128 ]
+# CHECK: Vreg: %256[ 38 ]
+# CHECK: Vreg: %90[ 45 ]
+# CHECK: Vreg: %71[ 21 ]
+# CHECK: Vreg: %315[ 26 ]
+# CHECK: Vreg: %40[ 63 ]
+# CHECK: Vreg: %21[ 126 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %111[ 55 ]
+# CHECK: Vreg: %92[ 48 ]
+# CHECK: Vreg: %73[ 25 ]
+# CHECK: Vreg: %23[ 84 ]
+# CHECK: Vreg: %4[ 134 ]
+# CHECK: Vreg: %260[ 22 ]
+# CHECK: Vreg: %94[ 51 ]
+# CHECK: Vreg: %30[ 108 ]
+# CHECK: Vreg: %37[ 66 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %281[ 41 ]
+# CHECK: Vreg: %262[ 20 ]
+# CHECK: Vreg: %96[ 58 ]
+# CHECK: Vreg: %58[ 59 ]
+# CHECK: Vreg: %20[ 122 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %65[ 25 ]
+# CHECK: Vreg: %276[ 43 ]
+# CHECK: Vreg: %22:sub0[ 74 ]
+# CHECK: Vreg: %22:sub1[ 75 ]
+# CHECK: Vreg: %22[ 139 ]
+# CHECK: Vreg: %67[ 25 ]
+# CHECK: Vreg: %112[ 55 ]
+# CHECK: Vreg: %278[ 13 ]
+# CHECK: Vreg: %3[ 45 ]
+# CHECK: Vreg: %43[ 60 ]
+# CHECK: Vreg: %5[ 132 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %95[ 54 ]
+# CHECK: Vreg: %351[ 1 ]
+# CHECK: Vreg: %249[ 39 ]
+# CHECK: Vreg: %19:sub0[ 98 ]
+# CHECK: Vreg: %19:sub1[ 99 ]
+# CHECK: Vreg: %19[ 111 ]
+# CHECK: Instr: %353:vgpr_32 = V_LSHL_OR_B32_e64 killed %352, 8, killed %351, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 127 ]
+# CHECK: Vreg: %256[ 37 ]
+# CHECK: Vreg: %90[ 44 ]
+# CHECK: Vreg: %71[ 20 ]
+# CHECK: Vreg: %315[ 25 ]
+# CHECK: Vreg: %40[ 62 ]
+# CHECK: Vreg: %21[ 125 ]
+# CHECK: Vreg: %2[ 28 ]
+# CHECK: Vreg: %111[ 54 ]
+# CHECK: Vreg: %92[ 47 ]
+# CHECK: Vreg: %73[ 24 ]
+# CHECK: Vreg: %23[ 83 ]
+# CHECK: Vreg: %4[ 133 ]
+# CHECK: Vreg: %260[ 21 ]
+# CHECK: Vreg: %94[ 50 ]
+# CHECK: Vreg: %30[ 107 ]
+# CHECK: Vreg: %37[ 65 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %281[ 40 ]
+# CHECK: Vreg: %262[ 19 ]
+# CHECK: Vreg: %96[ 57 ]
+# CHECK: Vreg: %352[ 0 ]
+# CHECK: Vreg: %58[ 58 ]
+# CHECK: Vreg: %20[ 121 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %65[ 24 ]
+# CHECK: Vreg: %276[ 42 ]
+# CHECK: Vreg: %22:sub0[ 73 ]
+# CHECK: Vreg: %22:sub1[ 74 ]
+# CHECK: Vreg: %22[ 138 ]
+# CHECK: Vreg: %67[ 24 ]
+# CHECK: Vreg: %112[ 54 ]
+# CHECK: Vreg: %278[ 12 ]
+# CHECK: Vreg: %3[ 44 ]
+# CHECK: Vreg: %43[ 59 ]
+# CHECK: Vreg: %5[ 131 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %95[ 53 ]
+# CHECK: Vreg: %351[ 0 ]
+# CHECK: Vreg: %249[ 38 ]
+# CHECK: Vreg: %19:sub0[ 97 ]
+# CHECK: Vreg: %19:sub1[ 98 ]
+# CHECK: Vreg: %19[ 110 ]
+# CHECK: Instr: %354:vgpr_32 = GLOBAL_LOAD_UBYTE %18, 2, 0, implicit $exec :: (load (s8) from %ir.p6 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 126 ]
+# CHECK: Vreg: %256[ 36 ]
+# CHECK: Vreg: %90[ 43 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %353[ 3 ]
+# CHECK: Vreg: %315[ 24 ]
+# CHECK: Vreg: %40[ 61 ]
+# CHECK: Vreg: %21[ 124 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %111[ 53 ]
+# CHECK: Vreg: %92[ 46 ]
+# CHECK: Vreg: %73[ 23 ]
+# CHECK: Vreg: %23[ 82 ]
+# CHECK: Vreg: %4[ 132 ]
+# CHECK: Vreg: %260[ 20 ]
+# CHECK: Vreg: %94[ 49 ]
+# CHECK: Vreg: %30[ 106 ]
+# CHECK: Vreg: %37[ 64 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %281[ 39 ]
+# CHECK: Vreg: %262[ 18 ]
+# CHECK: Vreg: %96[ 56 ]
+# CHECK: Vreg: %58[ 57 ]
+# CHECK: Vreg: %20[ 120 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %65[ 23 ]
+# CHECK: Vreg: %276[ 41 ]
+# CHECK: Vreg: %22:sub0[ 72 ]
+# CHECK: Vreg: %22:sub1[ 73 ]
+# CHECK: Vreg: %22[ 137 ]
+# CHECK: Vreg: %67[ 23 ]
+# CHECK: Vreg: %112[ 53 ]
+# CHECK: Vreg: %278[ 11 ]
+# CHECK: Vreg: %3[ 43 ]
+# CHECK: Vreg: %43[ 58 ]
+# CHECK: Vreg: %5[ 130 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %95[ 52 ]
+# CHECK: Vreg: %249[ 37 ]
+# CHECK: Vreg: %19:sub0[ 96 ]
+# CHECK: Vreg: %19:sub1[ 97 ]
+# CHECK: Vreg: %19[ 109 ]
+# CHECK: Instr: %355:vgpr_32 = GLOBAL_LOAD_UBYTE %18, 3, 0, implicit $exec :: (load (s8) from %ir.p6 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 125 ]
+# CHECK: Vreg: %256[ 35 ]
+# CHECK: Vreg: %90[ 42 ]
+# CHECK: Vreg: %71[ 18 ]
+# CHECK: Vreg: %353[ 2 ]
+# CHECK: Vreg: %315[ 23 ]
+# CHECK: Vreg: %40[ 60 ]
+# CHECK: Vreg: %21[ 123 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %111[ 52 ]
+# CHECK: Vreg: %92[ 45 ]
+# CHECK: Vreg: %73[ 22 ]
+# CHECK: Vreg: %23[ 81 ]
+# CHECK: Vreg: %4[ 131 ]
+# CHECK: Vreg: %260[ 19 ]
+# CHECK: Vreg: %94[ 48 ]
+# CHECK: Vreg: %30[ 105 ]
+# CHECK: Vreg: %37[ 63 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %281[ 38 ]
+# CHECK: Vreg: %262[ 17 ]
+# CHECK: Vreg: %96[ 55 ]
+# CHECK: Vreg: %58[ 56 ]
+# CHECK: Vreg: %20[ 119 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %65[ 22 ]
+# CHECK: Vreg: %276[ 40 ]
+# CHECK: Vreg: %354[ 1 ]
+# CHECK: Vreg: %22:sub0[ 71 ]
+# CHECK: Vreg: %22:sub1[ 72 ]
+# CHECK: Vreg: %22[ 136 ]
+# CHECK: Vreg: %67[ 22 ]
+# CHECK: Vreg: %112[ 52 ]
+# CHECK: Vreg: %278[ 10 ]
+# CHECK: Vreg: %3[ 42 ]
+# CHECK: Vreg: %43[ 57 ]
+# CHECK: Vreg: %5[ 129 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %95[ 51 ]
+# CHECK: Vreg: %249[ 36 ]
+# CHECK: Vreg: %19:sub0[ 95 ]
+# CHECK: Vreg: %19:sub1[ 96 ]
+# CHECK: Vreg: %19[ 108 ]
+# CHECK: Instr: %356:vgpr_32 = V_LSHL_OR_B32_e64 killed %355, 8, killed %354, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 124 ]
+# CHECK: Vreg: %256[ 34 ]
+# CHECK: Vreg: %90[ 41 ]
+# CHECK: Vreg: %71[ 17 ]
+# CHECK: Vreg: %353[ 1 ]
+# CHECK: Vreg: %315[ 22 ]
+# CHECK: Vreg: %40[ 59 ]
+# CHECK: Vreg: %21[ 122 ]
+# CHECK: Vreg: %2[ 25 ]
+# CHECK: Vreg: %111[ 51 ]
+# CHECK: Vreg: %92[ 44 ]
+# CHECK: Vreg: %73[ 21 ]
+# CHECK: Vreg: %355[ 0 ]
+# CHECK: Vreg: %23[ 80 ]
+# CHECK: Vreg: %4[ 130 ]
+# CHECK: Vreg: %260[ 18 ]
+# CHECK: Vreg: %94[ 47 ]
+# CHECK: Vreg: %30[ 104 ]
+# CHECK: Vreg: %37[ 62 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %281[ 37 ]
+# CHECK: Vreg: %262[ 16 ]
+# CHECK: Vreg: %96[ 54 ]
+# CHECK: Vreg: %58[ 55 ]
+# CHECK: Vreg: %20[ 118 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %65[ 21 ]
+# CHECK: Vreg: %276[ 39 ]
+# CHECK: Vreg: %354[ 0 ]
+# CHECK: Vreg: %22:sub0[ 70 ]
+# CHECK: Vreg: %22:sub1[ 71 ]
+# CHECK: Vreg: %22[ 135 ]
+# CHECK: Vreg: %67[ 21 ]
+# CHECK: Vreg: %112[ 51 ]
+# CHECK: Vreg: %278[ 9 ]
+# CHECK: Vreg: %3[ 41 ]
+# CHECK: Vreg: %43[ 56 ]
+# CHECK: Vreg: %5[ 128 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %95[ 50 ]
+# CHECK: Vreg: %249[ 35 ]
+# CHECK: Vreg: %19:sub0[ 94 ]
+# CHECK: Vreg: %19:sub1[ 95 ]
+# CHECK: Vreg: %19[ 107 ]
+# CHECK: Instr: %357:vgpr_32 = V_LSHL_OR_B32_e64 killed %356, 16, killed %353, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 123 ]
+# CHECK: Vreg: %256[ 33 ]
+# CHECK: Vreg: %90[ 40 ]
+# CHECK: Vreg: %71[ 16 ]
+# CHECK: Vreg: %353[ 0 ]
+# CHECK: Vreg: %315[ 21 ]
+# CHECK: Vreg: %40[ 58 ]
+# CHECK: Vreg: %21[ 121 ]
+# CHECK: Vreg: %2[ 24 ]
+# CHECK: Vreg: %111[ 50 ]
+# CHECK: Vreg: %92[ 43 ]
+# CHECK: Vreg: %73[ 20 ]
+# CHECK: Vreg: %23[ 79 ]
+# CHECK: Vreg: %4[ 129 ]
+# CHECK: Vreg: %260[ 17 ]
+# CHECK: Vreg: %94[ 46 ]
+# CHECK: Vreg: %30[ 103 ]
+# CHECK: Vreg: %37[ 61 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %281[ 36 ]
+# CHECK: Vreg: %262[ 15 ]
+# CHECK: Vreg: %96[ 53 ]
+# CHECK: Vreg: %58[ 54 ]
+# CHECK: Vreg: %20[ 117 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %65[ 20 ]
+# CHECK: Vreg: %276[ 38 ]
+# CHECK: Vreg: %22:sub0[ 69 ]
+# CHECK: Vreg: %22:sub1[ 70 ]
+# CHECK: Vreg: %22[ 134 ]
+# CHECK: Vreg: %67[ 20 ]
+# CHECK: Vreg: %112[ 50 ]
+# CHECK: Vreg: %278[ 8 ]
+# CHECK: Vreg: %3[ 40 ]
+# CHECK: Vreg: %356[ 0 ]
+# CHECK: Vreg: %43[ 55 ]
+# CHECK: Vreg: %5[ 127 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %95[ 49 ]
+# CHECK: Vreg: %249[ 34 ]
+# CHECK: Vreg: %19:sub0[ 93 ]
+# CHECK: Vreg: %19:sub1[ 94 ]
+# CHECK: Vreg: %19[ 106 ]
+# CHECK: Instr: %358:vgpr_32 = V_MUL_LO_U32_e64 killed %357, %69, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 122 ]
+# CHECK: Vreg: %256[ 32 ]
+# CHECK: Vreg: %90[ 39 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %315[ 20 ]
+# CHECK: Vreg: %40[ 57 ]
+# CHECK: Vreg: %21[ 120 ]
+# CHECK: Vreg: %2[ 23 ]
+# CHECK: Vreg: %111[ 49 ]
+# CHECK: Vreg: %92[ 42 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %23[ 78 ]
+# CHECK: Vreg: %4[ 128 ]
+# CHECK: Vreg: %260[ 16 ]
+# CHECK: Vreg: %94[ 45 ]
+# CHECK: Vreg: %30[ 102 ]
+# CHECK: Vreg: %37[ 60 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %357[ 0 ]
+# CHECK: Vreg: %281[ 35 ]
+# CHECK: Vreg: %262[ 14 ]
+# CHECK: Vreg: %96[ 52 ]
+# CHECK: Vreg: %58[ 53 ]
+# CHECK: Vreg: %20[ 116 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %65[ 19 ]
+# CHECK: Vreg: %276[ 37 ]
+# CHECK: Vreg: %22:sub0[ 68 ]
+# CHECK: Vreg: %22:sub1[ 69 ]
+# CHECK: Vreg: %22[ 133 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %112[ 49 ]
+# CHECK: Vreg: %278[ 7 ]
+# CHECK: Vreg: %3[ 39 ]
+# CHECK: Vreg: %43[ 54 ]
+# CHECK: Vreg: %5[ 126 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 48 ]
+# CHECK: Vreg: %249[ 33 ]
+# CHECK: Vreg: %19:sub0[ 92 ]
+# CHECK: Vreg: %19:sub1[ 93 ]
+# CHECK: Vreg: %19[ 105 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %18, %358, 0, 0, implicit $exec :: (store (s8) into %ir.p6, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 121 ]
+# CHECK: Vreg: %256[ 31 ]
+# CHECK: Vreg: %90[ 38 ]
+# CHECK: Vreg: %71[ 14 ]
+# CHECK: Vreg: %315[ 19 ]
+# CHECK: Vreg: %40[ 56 ]
+# CHECK: Vreg: %21[ 119 ]
+# CHECK: Vreg: %2[ 22 ]
+# CHECK: Vreg: %111[ 48 ]
+# CHECK: Vreg: %92[ 41 ]
+# CHECK: Vreg: %73[ 18 ]
+# CHECK: Vreg: %23[ 77 ]
+# CHECK: Vreg: %4[ 127 ]
+# CHECK: Vreg: %260[ 15 ]
+# CHECK: Vreg: %94[ 44 ]
+# CHECK: Vreg: %30[ 101 ]
+# CHECK: Vreg: %37[ 59 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %281[ 34 ]
+# CHECK: Vreg: %262[ 13 ]
+# CHECK: Vreg: %96[ 51 ]
+# CHECK: Vreg: %58[ 52 ]
+# CHECK: Vreg: %20[ 115 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %65[ 18 ]
+# CHECK: Vreg: %276[ 36 ]
+# CHECK: Vreg: %22:sub0[ 67 ]
+# CHECK: Vreg: %22:sub1[ 68 ]
+# CHECK: Vreg: %22[ 132 ]
+# CHECK: Vreg: %67[ 18 ]
+# CHECK: Vreg: %112[ 48 ]
+# CHECK: Vreg: %278[ 6 ]
+# CHECK: Vreg: %3[ 38 ]
+# CHECK: Vreg: %43[ 53 ]
+# CHECK: Vreg: %5[ 125 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 47 ]
+# CHECK: Vreg: %249[ 32 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 91 ]
+# CHECK: Vreg: %19:sub1[ 92 ]
+# CHECK: Vreg: %19[ 104 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE_D16_HI %18, %358, 2, 0, implicit $exec :: (store (s8) into %ir.p6 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 120 ]
+# CHECK: Vreg: %256[ 30 ]
+# CHECK: Vreg: %90[ 37 ]
+# CHECK: Vreg: %71[ 13 ]
+# CHECK: Vreg: %315[ 18 ]
+# CHECK: Vreg: %40[ 55 ]
+# CHECK: Vreg: %21[ 118 ]
+# CHECK: Vreg: %2[ 21 ]
+# CHECK: Vreg: %111[ 47 ]
+# CHECK: Vreg: %92[ 40 ]
+# CHECK: Vreg: %73[ 17 ]
+# CHECK: Vreg: %23[ 76 ]
+# CHECK: Vreg: %4[ 126 ]
+# CHECK: Vreg: %260[ 14 ]
+# CHECK: Vreg: %94[ 43 ]
+# CHECK: Vreg: %30[ 100 ]
+# CHECK: Vreg: %37[ 58 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %281[ 33 ]
+# CHECK: Vreg: %262[ 12 ]
+# CHECK: Vreg: %96[ 50 ]
+# CHECK: Vreg: %58[ 51 ]
+# CHECK: Vreg: %20[ 114 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %276[ 35 ]
+# CHECK: Vreg: %22:sub0[ 66 ]
+# CHECK: Vreg: %22:sub1[ 67 ]
+# CHECK: Vreg: %22[ 131 ]
+# CHECK: Vreg: %67[ 17 ]
+# CHECK: Vreg: %112[ 47 ]
+# CHECK: Vreg: %278[ 5 ]
+# CHECK: Vreg: %3[ 37 ]
+# CHECK: Vreg: %43[ 52 ]
+# CHECK: Vreg: %5[ 124 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %95[ 46 ]
+# CHECK: Vreg: %249[ 31 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 90 ]
+# CHECK: Vreg: %19:sub1[ 91 ]
+# CHECK: Vreg: %19[ 103 ]
+# CHECK: Instr: %359:vgpr_32 = V_LSHRREV_B32_e64 8, %358, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 119 ]
+# CHECK: Vreg: %256[ 29 ]
+# CHECK: Vreg: %90[ 36 ]
+# CHECK: Vreg: %71[ 12 ]
+# CHECK: Vreg: %315[ 17 ]
+# CHECK: Vreg: %40[ 54 ]
+# CHECK: Vreg: %21[ 117 ]
+# CHECK: Vreg: %2[ 20 ]
+# CHECK: Vreg: %111[ 46 ]
+# CHECK: Vreg: %92[ 39 ]
+# CHECK: Vreg: %73[ 16 ]
+# CHECK: Vreg: %23[ 75 ]
+# CHECK: Vreg: %4[ 125 ]
+# CHECK: Vreg: %260[ 13 ]
+# CHECK: Vreg: %94[ 42 ]
+# CHECK: Vreg: %30[ 99 ]
+# CHECK: Vreg: %37[ 57 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %281[ 32 ]
+# CHECK: Vreg: %262[ 11 ]
+# CHECK: Vreg: %96[ 49 ]
+# CHECK: Vreg: %58[ 50 ]
+# CHECK: Vreg: %20[ 113 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %276[ 34 ]
+# CHECK: Vreg: %22:sub0[ 65 ]
+# CHECK: Vreg: %22:sub1[ 66 ]
+# CHECK: Vreg: %22[ 130 ]
+# CHECK: Vreg: %67[ 16 ]
+# CHECK: Vreg: %112[ 46 ]
+# CHECK: Vreg: %278[ 4 ]
+# CHECK: Vreg: %3[ 36 ]
+# CHECK: Vreg: %43[ 51 ]
+# CHECK: Vreg: %5[ 123 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %95[ 45 ]
+# CHECK: Vreg: %249[ 30 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 89 ]
+# CHECK: Vreg: %19:sub1[ 90 ]
+# CHECK: Vreg: %19[ 102 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %18, killed %359, 1, 0, implicit $exec :: (store (s8) into %ir.p6 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 118 ]
+# CHECK: Vreg: %256[ 28 ]
+# CHECK: Vreg: %90[ 35 ]
+# CHECK: Vreg: %71[ 11 ]
+# CHECK: Vreg: %315[ 16 ]
+# CHECK: Vreg: %40[ 53 ]
+# CHECK: Vreg: %21[ 116 ]
+# CHECK: Vreg: %2[ 19 ]
+# CHECK: Vreg: %111[ 45 ]
+# CHECK: Vreg: %92[ 38 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %23[ 74 ]
+# CHECK: Vreg: %4[ 124 ]
+# CHECK: Vreg: %260[ 12 ]
+# CHECK: Vreg: %94[ 41 ]
+# CHECK: Vreg: %30[ 98 ]
+# CHECK: Vreg: %37[ 56 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %281[ 31 ]
+# CHECK: Vreg: %262[ 10 ]
+# CHECK: Vreg: %96[ 48 ]
+# CHECK: Vreg: %58[ 49 ]
+# CHECK: Vreg: %359[ 0 ]
+# CHECK: Vreg: %20[ 112 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %276[ 33 ]
+# CHECK: Vreg: %22:sub0[ 64 ]
+# CHECK: Vreg: %22:sub1[ 65 ]
+# CHECK: Vreg: %22[ 129 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 45 ]
+# CHECK: Vreg: %278[ 3 ]
+# CHECK: Vreg: %3[ 35 ]
+# CHECK: Vreg: %43[ 50 ]
+# CHECK: Vreg: %5[ 122 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %95[ 44 ]
+# CHECK: Vreg: %249[ 29 ]
+# CHECK: Vreg: %358[ 1 ]
+# CHECK: Vreg: %19:sub0[ 88 ]
+# CHECK: Vreg: %19:sub1[ 89 ]
+# CHECK: Vreg: %19[ 101 ]
+# CHECK: Instr: %360:vgpr_32 = V_LSHRREV_B32_e64 24, %358, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 117 ]
+# CHECK: Vreg: %256[ 27 ]
+# CHECK: Vreg: %90[ 34 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %315[ 15 ]
+# CHECK: Vreg: %40[ 52 ]
+# CHECK: Vreg: %21[ 115 ]
+# CHECK: Vreg: %2[ 18 ]
+# CHECK: Vreg: %111[ 44 ]
+# CHECK: Vreg: %92[ 37 ]
+# CHECK: Vreg: %73[ 14 ]
+# CHECK: Vreg: %23[ 73 ]
+# CHECK: Vreg: %4[ 123 ]
+# CHECK: Vreg: %260[ 11 ]
+# CHECK: Vreg: %94[ 40 ]
+# CHECK: Vreg: %30[ 97 ]
+# CHECK: Vreg: %37[ 55 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %281[ 30 ]
+# CHECK: Vreg: %262[ 9 ]
+# CHECK: Vreg: %96[ 47 ]
+# CHECK: Vreg: %58[ 48 ]
+# CHECK: Vreg: %20[ 111 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %276[ 32 ]
+# CHECK: Vreg: %22:sub0[ 63 ]
+# CHECK: Vreg: %22:sub1[ 64 ]
+# CHECK: Vreg: %22[ 128 ]
+# CHECK: Vreg: %67[ 14 ]
+# CHECK: Vreg: %112[ 44 ]
+# CHECK: Vreg: %278[ 2 ]
+# CHECK: Vreg: %3[ 34 ]
+# CHECK: Vreg: %43[ 49 ]
+# CHECK: Vreg: %5[ 121 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %95[ 43 ]
+# CHECK: Vreg: %249[ 28 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 87 ]
+# CHECK: Vreg: %19:sub1[ 88 ]
+# CHECK: Vreg: %19[ 100 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %18, killed %360, 3, 0, implicit $exec :: (store (s8) into %ir.p6 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 116 ]
+# CHECK: Vreg: %256[ 26 ]
+# CHECK: Vreg: %90[ 33 ]
+# CHECK: Vreg: %71[ 9 ]
+# CHECK: Vreg: %315[ 14 ]
+# CHECK: Vreg: %40[ 51 ]
+# CHECK: Vreg: %21[ 114 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %111[ 43 ]
+# CHECK: Vreg: %92[ 36 ]
+# CHECK: Vreg: %73[ 13 ]
+# CHECK: Vreg: %360[ 0 ]
+# CHECK: Vreg: %23[ 72 ]
+# CHECK: Vreg: %4[ 122 ]
+# CHECK: Vreg: %260[ 10 ]
+# CHECK: Vreg: %94[ 39 ]
+# CHECK: Vreg: %30[ 96 ]
+# CHECK: Vreg: %37[ 54 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %281[ 29 ]
+# CHECK: Vreg: %262[ 8 ]
+# CHECK: Vreg: %96[ 46 ]
+# CHECK: Vreg: %58[ 47 ]
+# CHECK: Vreg: %20[ 110 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %276[ 31 ]
+# CHECK: Vreg: %22:sub0[ 62 ]
+# CHECK: Vreg: %22:sub1[ 63 ]
+# CHECK: Vreg: %22[ 127 ]
+# CHECK: Vreg: %67[ 13 ]
+# CHECK: Vreg: %112[ 43 ]
+# CHECK: Vreg: %278[ 1 ]
+# CHECK: Vreg: %3[ 33 ]
+# CHECK: Vreg: %43[ 48 ]
+# CHECK: Vreg: %5[ 120 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %95[ 42 ]
+# CHECK: Vreg: %249[ 27 ]
+# CHECK: Vreg: %358[ 1 ]
+# CHECK: Vreg: %19:sub0[ 86 ]
+# CHECK: Vreg: %19:sub1[ 87 ]
+# CHECK: Vreg: %19[ 99 ]
+# CHECK: Instr: %361:sreg_32 = V_CMP_LT_U32_e64 %358, killed %278, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 115 ]
+# CHECK: Vreg: %256[ 25 ]
+# CHECK: Vreg: %90[ 32 ]
+# CHECK: Vreg: %71[ 8 ]
+# CHECK: Vreg: %315[ 13 ]
+# CHECK: Vreg: %40[ 50 ]
+# CHECK: Vreg: %21[ 113 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %111[ 42 ]
+# CHECK: Vreg: %92[ 35 ]
+# CHECK: Vreg: %73[ 12 ]
+# CHECK: Vreg: %23[ 71 ]
+# CHECK: Vreg: %4[ 121 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 38 ]
+# CHECK: Vreg: %30[ 95 ]
+# CHECK: Vreg: %37[ 53 ]
+# CHECK: Vreg: %18[ 131 ]
+# CHECK: Vreg: %281[ 28 ]
+# CHECK: Vreg: %262[ 7 ]
+# CHECK: Vreg: %96[ 45 ]
+# CHECK: Vreg: %58[ 46 ]
+# CHECK: Vreg: %20[ 109 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %276[ 30 ]
+# CHECK: Vreg: %22:sub0[ 61 ]
+# CHECK: Vreg: %22:sub1[ 62 ]
+# CHECK: Vreg: %22[ 126 ]
+# CHECK: Vreg: %67[ 12 ]
+# CHECK: Vreg: %112[ 42 ]
+# CHECK: Vreg: %278[ 0 ]
+# CHECK: Vreg: %3[ 32 ]
+# CHECK: Vreg: %43[ 47 ]
+# CHECK: Vreg: %5[ 119 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %95[ 41 ]
+# CHECK: Vreg: %249[ 26 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 85 ]
+# CHECK: Vreg: %19:sub1[ 86 ]
+# CHECK: Vreg: %19[ 98 ]
+# CHECK: Instr: %362:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 114 ]
+# CHECK: Vreg: %256[ 24 ]
+# CHECK: Vreg: %90[ 31 ]
+# CHECK: Vreg: %71[ 7 ]
+# CHECK: Vreg: %315[ 12 ]
+# CHECK: Vreg: %40[ 49 ]
+# CHECK: Vreg: %21[ 112 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %111[ 41 ]
+# CHECK: Vreg: %92[ 34 ]
+# CHECK: Vreg: %73[ 11 ]
+# CHECK: Vreg: %23[ 70 ]
+# CHECK: Vreg: %4[ 120 ]
+# CHECK: Vreg: %260[ 8 ]
+# CHECK: Vreg: %94[ 37 ]
+# CHECK: Vreg: %30[ 94 ]
+# CHECK: Vreg: %37[ 52 ]
+# CHECK: Vreg: %18[ 130 ]
+# CHECK: Vreg: %281[ 27 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 44 ]
+# CHECK: Vreg: %58[ 45 ]
+# CHECK: Vreg: %20[ 108 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %276[ 29 ]
+# CHECK: Vreg: %361[ 1 ]
+# CHECK: Vreg: %22:sub0[ 60 ]
+# CHECK: Vreg: %22:sub1[ 61 ]
+# CHECK: Vreg: %22[ 125 ]
+# CHECK: Vreg: %67[ 11 ]
+# CHECK: Vreg: %112[ 41 ]
+# CHECK: Vreg: %3[ 31 ]
+# CHECK: Vreg: %43[ 46 ]
+# CHECK: Vreg: %5[ 118 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %95[ 40 ]
+# CHECK: Vreg: %249[ 25 ]
+# CHECK: Vreg: %358[ 7 ]
+# CHECK: Vreg: %19:sub0[ 84 ]
+# CHECK: Vreg: %19:sub1[ 85 ]
+# CHECK: Vreg: %19[ 97 ]
+# CHECK: Instr: %363:sreg_32 = SI_IF killed %361, %bb.21, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 113 ]
+# CHECK: Vreg: %256[ 23 ]
+# CHECK: Vreg: %90[ 30 ]
+# CHECK: Vreg: %71[ 6 ]
+# CHECK: Vreg: %315[ 11 ]
+# CHECK: Vreg: %40[ 48 ]
+# CHECK: Vreg: %21[ 111 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %111[ 40 ]
+# CHECK: Vreg: %92[ 33 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %362[ 1 ]
+# CHECK: Vreg: %23[ 69 ]
+# CHECK: Vreg: %4[ 119 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 36 ]
+# CHECK: Vreg: %30[ 93 ]
+# CHECK: Vreg: %37[ 51 ]
+# CHECK: Vreg: %18[ 129 ]
+# CHECK: Vreg: %281[ 26 ]
+# CHECK: Vreg: %262[ 5 ]
+# CHECK: Vreg: %96[ 43 ]
+# CHECK: Vreg: %58[ 44 ]
+# CHECK: Vreg: %20[ 107 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %276[ 28 ]
+# CHECK: Vreg: %361[ 0 ]
+# CHECK: Vreg: %22:sub0[ 59 ]
+# CHECK: Vreg: %22:sub1[ 60 ]
+# CHECK: Vreg: %22[ 124 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %112[ 40 ]
+# CHECK: Vreg: %3[ 30 ]
+# CHECK: Vreg: %43[ 45 ]
+# CHECK: Vreg: %5[ 117 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %95[ 39 ]
+# CHECK: Vreg: %249[ 24 ]
+# CHECK: Vreg: %358[ 6 ]
+# CHECK: Vreg: %19:sub0[ 83 ]
+# CHECK: Vreg: %19:sub1[ 84 ]
+# CHECK: Vreg: %19[ 96 ]
+# CHECK: Instr: S_BRANCH %bb.24
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %71[ 5 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %362[ 0 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %358[ 5 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %71[ 5 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %362[ 0 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %358[ 5 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: --- MBB_19 ---
+# CHECK: Instr: %364:sreg_32 = PHI %365, %bb.23, %366, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %371[ 0 ]
+# CHECK: Vreg: %378[ 0 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %368[ 0 ]
+# CHECK: Vreg: %375[ 0 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %365[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %372[ 0 ]
+# CHECK: Vreg: %379[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %369[ 0 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %376[ 0 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %366[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %377[ 0 ]
+# CHECK: Vreg: %249[ 0 ]
+# CHECK: Instr: %367:sreg_32 = PHI %368, %bb.23, %369, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %371[ 0 ]
+# CHECK: Vreg: %378[ 0 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %368[ 0 ]
+# CHECK: Vreg: %375[ 0 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %372[ 0 ]
+# CHECK: Vreg: %379[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %369[ 0 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %376[ 0 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %377[ 0 ]
+# CHECK: Vreg: %249[ 0 ]
+# CHECK: Instr: %370:sreg_32 = PHI %371, %bb.23, %372, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %371[ 0 ]
+# CHECK: Vreg: %378[ 0 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %375[ 0 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %372[ 0 ]
+# CHECK: Vreg: %379[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %376[ 0 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %377[ 0 ]
+# CHECK: Vreg: %249[ 0 ]
+# CHECK: Instr: %373:sreg_32 = PHI %374, %bb.23, %375, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %378[ 0 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %375[ 0 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %379[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %376[ 0 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %377[ 0 ]
+# CHECK: Vreg: %249[ 0 ]
+# CHECK: Instr: %328:vgpr_32 = PHI %376, %bb.23, %249, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %378[ 0 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %379[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %376[ 0 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %377[ 0 ]
+# CHECK: Vreg: %249[ 0 ]
+# CHECK: Instr: %330:vgpr_32 = PHI %377, %bb.23, %378, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %378[ 0 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %379[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %328[ 13 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %377[ 0 ]
+# CHECK: Instr: %332:vgpr_32 = PHI %379, %bb.23, %67, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %330[ 13 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %379[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %328[ 13 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Instr: %334:vgpr_32 = PHI %380, %bb.23, %381, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %330[ 13 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %328[ 13 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %332[ 13 ]
+# CHECK: Instr: %336:vgpr_32 = PHI %380, %bb.23, %67, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %330[ 13 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %334[ 13 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %328[ 13 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %332[ 13 ]
+# CHECK: Instr: %339:vgpr_32 = PHI %382, %bb.23, %381, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %336[ 13 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %330[ 13 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %334[ 13 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %328[ 13 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %332[ 13 ]
+# CHECK: Instr: %341:vgpr_32 = PHI %383, %bb.23, %65, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %336[ 13 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %330[ 13 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %334[ 13 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %328[ 13 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %332[ 13 ]
+# CHECK: Vreg: %339[ 13 ]
+# CHECK: Instr: %343:vgpr_32 = PHI %384, %bb.23, %67, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %336[ 13 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %330[ 13 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %334[ 13 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %341[ 13 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %328[ 13 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %332[ 13 ]
+# CHECK: Vreg: %339[ 13 ]
+# CHECK: Instr: %345:vgpr_32 = PHI %385, %bb.23, %69, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %336[ 13 ]
+# CHECK: Vreg: %343[ 13 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 28 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %330[ 13 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %334[ 13 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %341[ 13 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %328[ 13 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %332[ 13 ]
+# CHECK: Vreg: %339[ 13 ]
+# CHECK: Instr: %347:vgpr_32 = PHI %386, %bb.23, %71, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %336[ 13 ]
+# CHECK: Vreg: %343[ 13 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 28 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %330[ 13 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %334[ 13 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %341[ 13 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %345[ 13 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %328[ 13 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 28 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %332[ 13 ]
+# CHECK: Vreg: %339[ 13 ]
+# CHECK: Instr: %349:vgpr_32 = PHI %387, %bb.23, %73, %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %367[ 8 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %336[ 13 ]
+# CHECK: Vreg: %343[ 13 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %364[ 10 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %347[ 13 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 28 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %330[ 13 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %71[ 28 ]
+# CHECK: Vreg: %334[ 13 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %341[ 13 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %345[ 13 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 17 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %328[ 13 ]
+# CHECK: Vreg: %373[ 2 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 28 ]
+# CHECK: Vreg: %370[ 5 ]
+# CHECK: Vreg: %332[ 13 ]
+# CHECK: Vreg: %339[ 13 ]
+# CHECK: Instr: SI_END_CF killed %388, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 100 ]
+# CHECK: Vreg: %256[ 10 ]
+# CHECK: Vreg: %90[ 17 ]
+# CHECK: Vreg: %21[ 98 ]
+# CHECK: Vreg: %111[ 27 ]
+# CHECK: Vreg: %367[ 7 ]
+# CHECK: Vreg: %73[ 27 ]
+# CHECK: Vreg: %336[ 12 ]
+# CHECK: Vreg: %343[ 12 ]
+# CHECK: Vreg: %4[ 106 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 23 ]
+# CHECK: Vreg: %388[ 0 ]
+# CHECK: Vreg: %18[ 116 ]
+# CHECK: Vreg: %364[ 9 ]
+# CHECK: Vreg: %281[ 13 ]
+# CHECK: Vreg: %1[ 135 ]
+# CHECK: Vreg: %347[ 12 ]
+# CHECK: Vreg: %22:sub0[ 46 ]
+# CHECK: Vreg: %22:sub1[ 47 ]
+# CHECK: Vreg: %22[ 111 ]
+# CHECK: Vreg: %67[ 27 ]
+# CHECK: Vreg: %112[ 27 ]
+# CHECK: Vreg: %330[ 12 ]
+# CHECK: Vreg: %43[ 32 ]
+# CHECK: Vreg: %5[ 104 ]
+# CHECK: Vreg: %95[ 26 ]
+# CHECK: Vreg: %19:sub0[ 70 ]
+# CHECK: Vreg: %19:sub1[ 71 ]
+# CHECK: Vreg: %19[ 83 ]
+# CHECK: Vreg: %71[ 27 ]
+# CHECK: Vreg: %334[ 12 ]
+# CHECK: Vreg: %40[ 35 ]
+# CHECK: Vreg: %341[ 12 ]
+# CHECK: Vreg: %2[ 119 ]
+# CHECK: Vreg: %92[ 20 ]
+# CHECK: Vreg: %23[ 56 ]
+# CHECK: Vreg: %30[ 80 ]
+# CHECK: Vreg: %37[ 38 ]
+# CHECK: Vreg: %345[ 12 ]
+# CHECK: Vreg: %262[ 3 ]
+# CHECK: Vreg: %96[ 30 ]
+# CHECK: Vreg: %58[ 31 ]
+# CHECK: Vreg: %20[ 94 ]
+# CHECK: Vreg: %65[ 16 ]
+# CHECK: Vreg: %276[ 15 ]
+# CHECK: Vreg: %328[ 12 ]
+# CHECK: Vreg: %373[ 1 ]
+# CHECK: Vreg: %3[ 17 ]
+# CHECK: Vreg: %349[ 12 ]
+# CHECK: Vreg: %69[ 27 ]
+# CHECK: Vreg: %370[ 4 ]
+# CHECK: Vreg: %332[ 12 ]
+# CHECK: Vreg: %339[ 12 ]
+# CHECK: Instr: %389:sreg_32 = S_AND_B32 killed %373, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 99 ]
+# CHECK: Vreg: %256[ 9 ]
+# CHECK: Vreg: %90[ 16 ]
+# CHECK: Vreg: %21[ 97 ]
+# CHECK: Vreg: %111[ 26 ]
+# CHECK: Vreg: %367[ 6 ]
+# CHECK: Vreg: %73[ 26 ]
+# CHECK: Vreg: %336[ 11 ]
+# CHECK: Vreg: %343[ 11 ]
+# CHECK: Vreg: %4[ 105 ]
+# CHECK: Vreg: %260[ 5 ]
+# CHECK: Vreg: %94[ 22 ]
+# CHECK: Vreg: %18[ 115 ]
+# CHECK: Vreg: %364[ 8 ]
+# CHECK: Vreg: %281[ 12 ]
+# CHECK: Vreg: %1[ 134 ]
+# CHECK: Vreg: %347[ 11 ]
+# CHECK: Vreg: %22:sub0[ 45 ]
+# CHECK: Vreg: %22:sub1[ 46 ]
+# CHECK: Vreg: %22[ 110 ]
+# CHECK: Vreg: %67[ 26 ]
+# CHECK: Vreg: %112[ 26 ]
+# CHECK: Vreg: %330[ 11 ]
+# CHECK: Vreg: %43[ 31 ]
+# CHECK: Vreg: %5[ 103 ]
+# CHECK: Vreg: %95[ 25 ]
+# CHECK: Vreg: %19:sub0[ 69 ]
+# CHECK: Vreg: %19:sub1[ 70 ]
+# CHECK: Vreg: %19[ 82 ]
+# CHECK: Vreg: %71[ 26 ]
+# CHECK: Vreg: %334[ 11 ]
+# CHECK: Vreg: %40[ 34 ]
+# CHECK: Vreg: %341[ 11 ]
+# CHECK: Vreg: %2[ 118 ]
+# CHECK: Vreg: %92[ 19 ]
+# CHECK: Vreg: %23[ 55 ]
+# CHECK: Vreg: %30[ 79 ]
+# CHECK: Vreg: %37[ 37 ]
+# CHECK: Vreg: %345[ 11 ]
+# CHECK: Vreg: %262[ 2 ]
+# CHECK: Vreg: %96[ 29 ]
+# CHECK: Vreg: %58[ 30 ]
+# CHECK: Vreg: %20[ 93 ]
+# CHECK: Vreg: %65[ 15 ]
+# CHECK: Vreg: %276[ 14 ]
+# CHECK: Vreg: %328[ 11 ]
+# CHECK: Vreg: %373[ 0 ]
+# CHECK: Vreg: %3[ 16 ]
+# CHECK: Vreg: %349[ 11 ]
+# CHECK: Vreg: %69[ 26 ]
+# CHECK: Vreg: %370[ 3 ]
+# CHECK: Vreg: %332[ 11 ]
+# CHECK: Vreg: %339[ 11 ]
+# CHECK: Instr: %325:sreg_32 = COPY killed %389
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 98 ]
+# CHECK: Vreg: %256[ 8 ]
+# CHECK: Vreg: %90[ 15 ]
+# CHECK: Vreg: %21[ 96 ]
+# CHECK: Vreg: %111[ 25 ]
+# CHECK: Vreg: %367[ 5 ]
+# CHECK: Vreg: %73[ 25 ]
+# CHECK: Vreg: %336[ 10 ]
+# CHECK: Vreg: %343[ 10 ]
+# CHECK: Vreg: %4[ 104 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 21 ]
+# CHECK: Vreg: %18[ 114 ]
+# CHECK: Vreg: %364[ 7 ]
+# CHECK: Vreg: %281[ 11 ]
+# CHECK: Vreg: %1[ 133 ]
+# CHECK: Vreg: %347[ 10 ]
+# CHECK: Vreg: %22:sub0[ 44 ]
+# CHECK: Vreg: %22:sub1[ 45 ]
+# CHECK: Vreg: %22[ 109 ]
+# CHECK: Vreg: %67[ 25 ]
+# CHECK: Vreg: %112[ 25 ]
+# CHECK: Vreg: %330[ 10 ]
+# CHECK: Vreg: %43[ 30 ]
+# CHECK: Vreg: %5[ 102 ]
+# CHECK: Vreg: %389[ 0 ]
+# CHECK: Vreg: %95[ 24 ]
+# CHECK: Vreg: %19:sub0[ 68 ]
+# CHECK: Vreg: %19:sub1[ 69 ]
+# CHECK: Vreg: %19[ 81 ]
+# CHECK: Vreg: %71[ 25 ]
+# CHECK: Vreg: %334[ 10 ]
+# CHECK: Vreg: %40[ 33 ]
+# CHECK: Vreg: %341[ 10 ]
+# CHECK: Vreg: %2[ 117 ]
+# CHECK: Vreg: %92[ 18 ]
+# CHECK: Vreg: %23[ 54 ]
+# CHECK: Vreg: %30[ 78 ]
+# CHECK: Vreg: %37[ 36 ]
+# CHECK: Vreg: %345[ 10 ]
+# CHECK: Vreg: %262[ 1 ]
+# CHECK: Vreg: %96[ 28 ]
+# CHECK: Vreg: %58[ 29 ]
+# CHECK: Vreg: %20[ 92 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %276[ 13 ]
+# CHECK: Vreg: %328[ 10 ]
+# CHECK: Vreg: %3[ 15 ]
+# CHECK: Vreg: %349[ 10 ]
+# CHECK: Vreg: %69[ 25 ]
+# CHECK: Vreg: %370[ 2 ]
+# CHECK: Vreg: %332[ 10 ]
+# CHECK: Vreg: %339[ 10 ]
+# CHECK: Instr: %390:sreg_32 = S_ANDN2_B32 killed %262, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 97 ]
+# CHECK: Vreg: %256[ 7 ]
+# CHECK: Vreg: %90[ 14 ]
+# CHECK: Vreg: %21[ 95 ]
+# CHECK: Vreg: %111[ 24 ]
+# CHECK: Vreg: %367[ 4 ]
+# CHECK: Vreg: %73[ 24 ]
+# CHECK: Vreg: %336[ 9 ]
+# CHECK: Vreg: %343[ 9 ]
+# CHECK: Vreg: %4[ 103 ]
+# CHECK: Vreg: %260[ 3 ]
+# CHECK: Vreg: %94[ 20 ]
+# CHECK: Vreg: %18[ 113 ]
+# CHECK: Vreg: %364[ 6 ]
+# CHECK: Vreg: %281[ 10 ]
+# CHECK: Vreg: %1[ 132 ]
+# CHECK: Vreg: %347[ 9 ]
+# CHECK: Vreg: %22:sub0[ 43 ]
+# CHECK: Vreg: %22:sub1[ 44 ]
+# CHECK: Vreg: %22[ 108 ]
+# CHECK: Vreg: %67[ 24 ]
+# CHECK: Vreg: %112[ 24 ]
+# CHECK: Vreg: %330[ 9 ]
+# CHECK: Vreg: %43[ 29 ]
+# CHECK: Vreg: %5[ 101 ]
+# CHECK: Vreg: %95[ 23 ]
+# CHECK: Vreg: %19:sub0[ 67 ]
+# CHECK: Vreg: %19:sub1[ 68 ]
+# CHECK: Vreg: %19[ 80 ]
+# CHECK: Vreg: %71[ 24 ]
+# CHECK: Vreg: %334[ 9 ]
+# CHECK: Vreg: %40[ 32 ]
+# CHECK: Vreg: %341[ 9 ]
+# CHECK: Vreg: %2[ 116 ]
+# CHECK: Vreg: %92[ 17 ]
+# CHECK: Vreg: %23[ 53 ]
+# CHECK: Vreg: %30[ 77 ]
+# CHECK: Vreg: %37[ 35 ]
+# CHECK: Vreg: %345[ 9 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 27 ]
+# CHECK: Vreg: %58[ 28 ]
+# CHECK: Vreg: %20[ 91 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %276[ 12 ]
+# CHECK: Vreg: %328[ 9 ]
+# CHECK: Vreg: %3[ 14 ]
+# CHECK: Vreg: %349[ 9 ]
+# CHECK: Vreg: %69[ 24 ]
+# CHECK: Vreg: %325[ 9 ]
+# CHECK: Vreg: %370[ 1 ]
+# CHECK: Vreg: %332[ 9 ]
+# CHECK: Vreg: %339[ 9 ]
+# CHECK: Instr: %391:sreg_32 = S_AND_B32 killed %370, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 96 ]
+# CHECK: Vreg: %256[ 6 ]
+# CHECK: Vreg: %90[ 13 ]
+# CHECK: Vreg: %21[ 94 ]
+# CHECK: Vreg: %111[ 23 ]
+# CHECK: Vreg: %367[ 3 ]
+# CHECK: Vreg: %73[ 23 ]
+# CHECK: Vreg: %336[ 8 ]
+# CHECK: Vreg: %343[ 8 ]
+# CHECK: Vreg: %4[ 102 ]
+# CHECK: Vreg: %260[ 2 ]
+# CHECK: Vreg: %94[ 19 ]
+# CHECK: Vreg: %18[ 112 ]
+# CHECK: Vreg: %364[ 5 ]
+# CHECK: Vreg: %281[ 9 ]
+# CHECK: Vreg: %1[ 131 ]
+# CHECK: Vreg: %347[ 8 ]
+# CHECK: Vreg: %22:sub0[ 42 ]
+# CHECK: Vreg: %22:sub1[ 43 ]
+# CHECK: Vreg: %22[ 107 ]
+# CHECK: Vreg: %67[ 23 ]
+# CHECK: Vreg: %112[ 23 ]
+# CHECK: Vreg: %330[ 8 ]
+# CHECK: Vreg: %43[ 28 ]
+# CHECK: Vreg: %5[ 100 ]
+# CHECK: Vreg: %95[ 22 ]
+# CHECK: Vreg: %19:sub0[ 66 ]
+# CHECK: Vreg: %19:sub1[ 67 ]
+# CHECK: Vreg: %19[ 79 ]
+# CHECK: Vreg: %71[ 23 ]
+# CHECK: Vreg: %334[ 8 ]
+# CHECK: Vreg: %40[ 31 ]
+# CHECK: Vreg: %341[ 8 ]
+# CHECK: Vreg: %2[ 115 ]
+# CHECK: Vreg: %92[ 16 ]
+# CHECK: Vreg: %23[ 52 ]
+# CHECK: Vreg: %30[ 76 ]
+# CHECK: Vreg: %37[ 34 ]
+# CHECK: Vreg: %345[ 8 ]
+# CHECK: Vreg: %390[ 1 ]
+# CHECK: Vreg: %96[ 26 ]
+# CHECK: Vreg: %58[ 27 ]
+# CHECK: Vreg: %20[ 90 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %276[ 11 ]
+# CHECK: Vreg: %328[ 8 ]
+# CHECK: Vreg: %3[ 13 ]
+# CHECK: Vreg: %349[ 8 ]
+# CHECK: Vreg: %69[ 23 ]
+# CHECK: Vreg: %325[ 8 ]
+# CHECK: Vreg: %370[ 0 ]
+# CHECK: Vreg: %332[ 8 ]
+# CHECK: Vreg: %339[ 8 ]
+# CHECK: Instr: %323:sreg_32 = S_OR_B32 killed %390, killed %391, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 95 ]
+# CHECK: Vreg: %256[ 5 ]
+# CHECK: Vreg: %90[ 12 ]
+# CHECK: Vreg: %391[ 0 ]
+# CHECK: Vreg: %21[ 93 ]
+# CHECK: Vreg: %111[ 22 ]
+# CHECK: Vreg: %367[ 2 ]
+# CHECK: Vreg: %73[ 22 ]
+# CHECK: Vreg: %336[ 7 ]
+# CHECK: Vreg: %343[ 7 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %260[ 1 ]
+# CHECK: Vreg: %94[ 18 ]
+# CHECK: Vreg: %18[ 111 ]
+# CHECK: Vreg: %364[ 4 ]
+# CHECK: Vreg: %281[ 8 ]
+# CHECK: Vreg: %1[ 130 ]
+# CHECK: Vreg: %347[ 7 ]
+# CHECK: Vreg: %22:sub0[ 41 ]
+# CHECK: Vreg: %22:sub1[ 42 ]
+# CHECK: Vreg: %22[ 106 ]
+# CHECK: Vreg: %67[ 22 ]
+# CHECK: Vreg: %112[ 22 ]
+# CHECK: Vreg: %330[ 7 ]
+# CHECK: Vreg: %43[ 27 ]
+# CHECK: Vreg: %5[ 99 ]
+# CHECK: Vreg: %95[ 21 ]
+# CHECK: Vreg: %19:sub0[ 65 ]
+# CHECK: Vreg: %19:sub1[ 66 ]
+# CHECK: Vreg: %19[ 78 ]
+# CHECK: Vreg: %71[ 22 ]
+# CHECK: Vreg: %334[ 7 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %341[ 7 ]
+# CHECK: Vreg: %2[ 114 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %23[ 51 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %37[ 33 ]
+# CHECK: Vreg: %345[ 7 ]
+# CHECK: Vreg: %390[ 0 ]
+# CHECK: Vreg: %96[ 25 ]
+# CHECK: Vreg: %58[ 26 ]
+# CHECK: Vreg: %20[ 89 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %276[ 10 ]
+# CHECK: Vreg: %328[ 7 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %349[ 7 ]
+# CHECK: Vreg: %69[ 22 ]
+# CHECK: Vreg: %325[ 7 ]
+# CHECK: Vreg: %332[ 7 ]
+# CHECK: Vreg: %339[ 7 ]
+# CHECK: Instr: %392:sreg_32 = S_ANDN2_B32 killed %260, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 94 ]
+# CHECK: Vreg: %256[ 4 ]
+# CHECK: Vreg: %90[ 11 ]
+# CHECK: Vreg: %21[ 92 ]
+# CHECK: Vreg: %111[ 21 ]
+# CHECK: Vreg: %367[ 1 ]
+# CHECK: Vreg: %73[ 21 ]
+# CHECK: Vreg: %336[ 6 ]
+# CHECK: Vreg: %343[ 6 ]
+# CHECK: Vreg: %4[ 100 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 17 ]
+# CHECK: Vreg: %18[ 110 ]
+# CHECK: Vreg: %364[ 3 ]
+# CHECK: Vreg: %281[ 7 ]
+# CHECK: Vreg: %1[ 129 ]
+# CHECK: Vreg: %347[ 6 ]
+# CHECK: Vreg: %22:sub0[ 40 ]
+# CHECK: Vreg: %22:sub1[ 41 ]
+# CHECK: Vreg: %22[ 105 ]
+# CHECK: Vreg: %67[ 21 ]
+# CHECK: Vreg: %112[ 21 ]
+# CHECK: Vreg: %330[ 6 ]
+# CHECK: Vreg: %323[ 6 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 98 ]
+# CHECK: Vreg: %95[ 20 ]
+# CHECK: Vreg: %19:sub0[ 64 ]
+# CHECK: Vreg: %19:sub1[ 65 ]
+# CHECK: Vreg: %19[ 77 ]
+# CHECK: Vreg: %71[ 21 ]
+# CHECK: Vreg: %334[ 6 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %341[ 6 ]
+# CHECK: Vreg: %2[ 113 ]
+# CHECK: Vreg: %92[ 14 ]
+# CHECK: Vreg: %23[ 50 ]
+# CHECK: Vreg: %30[ 74 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %345[ 6 ]
+# CHECK: Vreg: %96[ 24 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %20[ 88 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %276[ 9 ]
+# CHECK: Vreg: %328[ 6 ]
+# CHECK: Vreg: %3[ 11 ]
+# CHECK: Vreg: %349[ 6 ]
+# CHECK: Vreg: %69[ 21 ]
+# CHECK: Vreg: %325[ 6 ]
+# CHECK: Vreg: %332[ 6 ]
+# CHECK: Vreg: %339[ 6 ]
+# CHECK: Instr: %393:sreg_32 = S_AND_B32 killed %367, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 93 ]
+# CHECK: Vreg: %256[ 3 ]
+# CHECK: Vreg: %90[ 10 ]
+# CHECK: Vreg: %21[ 91 ]
+# CHECK: Vreg: %111[ 20 ]
+# CHECK: Vreg: %367[ 0 ]
+# CHECK: Vreg: %73[ 20 ]
+# CHECK: Vreg: %336[ 5 ]
+# CHECK: Vreg: %343[ 5 ]
+# CHECK: Vreg: %4[ 99 ]
+# CHECK: Vreg: %94[ 16 ]
+# CHECK: Vreg: %18[ 109 ]
+# CHECK: Vreg: %364[ 2 ]
+# CHECK: Vreg: %281[ 6 ]
+# CHECK: Vreg: %1[ 128 ]
+# CHECK: Vreg: %347[ 5 ]
+# CHECK: Vreg: %392[ 1 ]
+# CHECK: Vreg: %22:sub0[ 39 ]
+# CHECK: Vreg: %22:sub1[ 40 ]
+# CHECK: Vreg: %22[ 104 ]
+# CHECK: Vreg: %67[ 20 ]
+# CHECK: Vreg: %112[ 20 ]
+# CHECK: Vreg: %330[ 5 ]
+# CHECK: Vreg: %323[ 5 ]
+# CHECK: Vreg: %43[ 25 ]
+# CHECK: Vreg: %5[ 97 ]
+# CHECK: Vreg: %95[ 19 ]
+# CHECK: Vreg: %19:sub0[ 63 ]
+# CHECK: Vreg: %19:sub1[ 64 ]
+# CHECK: Vreg: %19[ 76 ]
+# CHECK: Vreg: %71[ 20 ]
+# CHECK: Vreg: %334[ 5 ]
+# CHECK: Vreg: %40[ 28 ]
+# CHECK: Vreg: %341[ 5 ]
+# CHECK: Vreg: %2[ 112 ]
+# CHECK: Vreg: %92[ 13 ]
+# CHECK: Vreg: %23[ 49 ]
+# CHECK: Vreg: %30[ 73 ]
+# CHECK: Vreg: %37[ 31 ]
+# CHECK: Vreg: %345[ 5 ]
+# CHECK: Vreg: %96[ 23 ]
+# CHECK: Vreg: %58[ 24 ]
+# CHECK: Vreg: %20[ 87 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 8 ]
+# CHECK: Vreg: %328[ 5 ]
+# CHECK: Vreg: %3[ 10 ]
+# CHECK: Vreg: %349[ 5 ]
+# CHECK: Vreg: %69[ 20 ]
+# CHECK: Vreg: %325[ 5 ]
+# CHECK: Vreg: %332[ 5 ]
+# CHECK: Vreg: %339[ 5 ]
+# CHECK: Instr: %321:sreg_32 = S_OR_B32 killed %392, killed %393, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %256[ 2 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %111[ 19 ]
+# CHECK: Vreg: %73[ 19 ]
+# CHECK: Vreg: %336[ 4 ]
+# CHECK: Vreg: %343[ 4 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %18[ 108 ]
+# CHECK: Vreg: %364[ 1 ]
+# CHECK: Vreg: %281[ 5 ]
+# CHECK: Vreg: %1[ 127 ]
+# CHECK: Vreg: %347[ 4 ]
+# CHECK: Vreg: %392[ 0 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %22[ 103 ]
+# CHECK: Vreg: %67[ 19 ]
+# CHECK: Vreg: %112[ 19 ]
+# CHECK: Vreg: %330[ 4 ]
+# CHECK: Vreg: %323[ 4 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Vreg: %19[ 75 ]
+# CHECK: Vreg: %71[ 19 ]
+# CHECK: Vreg: %334[ 4 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %341[ 4 ]
+# CHECK: Vreg: %2[ 111 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %393[ 0 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %345[ 4 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %276[ 7 ]
+# CHECK: Vreg: %328[ 4 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Vreg: %349[ 4 ]
+# CHECK: Vreg: %69[ 19 ]
+# CHECK: Vreg: %325[ 4 ]
+# CHECK: Vreg: %332[ 4 ]
+# CHECK: Vreg: %339[ 4 ]
+# CHECK: Instr: %319:sreg_32 = S_ORN2_B32 killed %364, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 91 ]
+# CHECK: Vreg: %256[ 1 ]
+# CHECK: Vreg: %90[ 8 ]
+# CHECK: Vreg: %71[ 18 ]
+# CHECK: Vreg: %339[ 3 ]
+# CHECK: Vreg: %334[ 3 ]
+# CHECK: Vreg: %40[ 26 ]
+# CHECK: Vreg: %21[ 89 ]
+# CHECK: Vreg: %341[ 3 ]
+# CHECK: Vreg: %111[ 18 ]
+# CHECK: Vreg: %92[ 11 ]
+# CHECK: Vreg: %73[ 18 ]
+# CHECK: Vreg: %336[ 3 ]
+# CHECK: Vreg: %343[ 3 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %94[ 14 ]
+# CHECK: Vreg: %30[ 71 ]
+# CHECK: Vreg: %2[ 110 ]
+# CHECK: Vreg: %18[ 107 ]
+# CHECK: Vreg: %37[ 29 ]
+# CHECK: Vreg: %281[ 4 ]
+# CHECK: Vreg: %345[ 3 ]
+# CHECK: Vreg: %364[ 0 ]
+# CHECK: Vreg: %96[ 21 ]
+# CHECK: Vreg: %23[ 47 ]
+# CHECK: Vreg: %58[ 22 ]
+# CHECK: Vreg: %20[ 85 ]
+# CHECK: Vreg: %1[ 126 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %347[ 3 ]
+# CHECK: Vreg: %321[ 3 ]
+# CHECK: Vreg: %328[ 3 ]
+# CHECK: Vreg: %276[ 6 ]
+# CHECK: Vreg: %22:sub0[ 37 ]
+# CHECK: Vreg: %22:sub1[ 38 ]
+# CHECK: Vreg: %22[ 102 ]
+# CHECK: Vreg: %67[ 18 ]
+# CHECK: Vreg: %112[ 18 ]
+# CHECK: Vreg: %349[ 3 ]
+# CHECK: Vreg: %330[ 3 ]
+# CHECK: Vreg: %323[ 3 ]
+# CHECK: Vreg: %43[ 23 ]
+# CHECK: Vreg: %5[ 95 ]
+# CHECK: Vreg: %69[ 18 ]
+# CHECK: Vreg: %95[ 17 ]
+# CHECK: Vreg: %325[ 3 ]
+# CHECK: Vreg: %332[ 3 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Vreg: %19:sub0[ 61 ]
+# CHECK: Vreg: %19:sub1[ 62 ]
+# CHECK: Vreg: %19[ 74 ]
+# CHECK: Instr: %394:sreg_32 = S_ANDN2_B32 killed %256, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 90 ]
+# CHECK: Vreg: %256[ 0 ]
+# CHECK: Vreg: %90[ 7 ]
+# CHECK: Vreg: %71[ 17 ]
+# CHECK: Vreg: %339[ 2 ]
+# CHECK: Vreg: %334[ 2 ]
+# CHECK: Vreg: %40[ 25 ]
+# CHECK: Vreg: %21[ 88 ]
+# CHECK: Vreg: %341[ 2 ]
+# CHECK: Vreg: %111[ 17 ]
+# CHECK: Vreg: %92[ 10 ]
+# CHECK: Vreg: %73[ 17 ]
+# CHECK: Vreg: %336[ 2 ]
+# CHECK: Vreg: %343[ 2 ]
+# CHECK: Vreg: %4[ 96 ]
+# CHECK: Vreg: %94[ 13 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %2[ 109 ]
+# CHECK: Vreg: %18[ 106 ]
+# CHECK: Vreg: %319[ 2 ]
+# CHECK: Vreg: %37[ 28 ]
+# CHECK: Vreg: %281[ 3 ]
+# CHECK: Vreg: %345[ 2 ]
+# CHECK: Vreg: %96[ 20 ]
+# CHECK: Vreg: %23[ 46 ]
+# CHECK: Vreg: %58[ 21 ]
+# CHECK: Vreg: %20[ 84 ]
+# CHECK: Vreg: %1[ 125 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %347[ 2 ]
+# CHECK: Vreg: %321[ 2 ]
+# CHECK: Vreg: %328[ 2 ]
+# CHECK: Vreg: %276[ 5 ]
+# CHECK: Vreg: %22:sub0[ 36 ]
+# CHECK: Vreg: %22:sub1[ 37 ]
+# CHECK: Vreg: %22[ 101 ]
+# CHECK: Vreg: %67[ 17 ]
+# CHECK: Vreg: %112[ 17 ]
+# CHECK: Vreg: %349[ 2 ]
+# CHECK: Vreg: %330[ 2 ]
+# CHECK: Vreg: %323[ 2 ]
+# CHECK: Vreg: %43[ 22 ]
+# CHECK: Vreg: %5[ 94 ]
+# CHECK: Vreg: %69[ 17 ]
+# CHECK: Vreg: %95[ 16 ]
+# CHECK: Vreg: %325[ 2 ]
+# CHECK: Vreg: %332[ 2 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Vreg: %19:sub0[ 60 ]
+# CHECK: Vreg: %19:sub1[ 61 ]
+# CHECK: Vreg: %19[ 73 ]
+# CHECK: Instr: %317:sreg_32 = COPY killed %394
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 89 ]
+# CHECK: Vreg: %90[ 6 ]
+# CHECK: Vreg: %71[ 16 ]
+# CHECK: Vreg: %339[ 1 ]
+# CHECK: Vreg: %334[ 1 ]
+# CHECK: Vreg: %40[ 24 ]
+# CHECK: Vreg: %21[ 87 ]
+# CHECK: Vreg: %341[ 1 ]
+# CHECK: Vreg: %111[ 16 ]
+# CHECK: Vreg: %92[ 9 ]
+# CHECK: Vreg: %73[ 16 ]
+# CHECK: Vreg: %336[ 1 ]
+# CHECK: Vreg: %343[ 1 ]
+# CHECK: Vreg: %4[ 95 ]
+# CHECK: Vreg: %94[ 12 ]
+# CHECK: Vreg: %30[ 69 ]
+# CHECK: Vreg: %2[ 108 ]
+# CHECK: Vreg: %18[ 105 ]
+# CHECK: Vreg: %319[ 1 ]
+# CHECK: Vreg: %37[ 27 ]
+# CHECK: Vreg: %281[ 2 ]
+# CHECK: Vreg: %345[ 1 ]
+# CHECK: Vreg: %96[ 19 ]
+# CHECK: Vreg: %23[ 45 ]
+# CHECK: Vreg: %58[ 20 ]
+# CHECK: Vreg: %20[ 83 ]
+# CHECK: Vreg: %1[ 124 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %347[ 1 ]
+# CHECK: Vreg: %321[ 1 ]
+# CHECK: Vreg: %328[ 1 ]
+# CHECK: Vreg: %276[ 4 ]
+# CHECK: Vreg: %22:sub0[ 35 ]
+# CHECK: Vreg: %22:sub1[ 36 ]
+# CHECK: Vreg: %22[ 100 ]
+# CHECK: Vreg: %67[ 16 ]
+# CHECK: Vreg: %112[ 16 ]
+# CHECK: Vreg: %349[ 1 ]
+# CHECK: Vreg: %330[ 1 ]
+# CHECK: Vreg: %394[ 0 ]
+# CHECK: Vreg: %323[ 1 ]
+# CHECK: Vreg: %43[ 21 ]
+# CHECK: Vreg: %5[ 93 ]
+# CHECK: Vreg: %69[ 16 ]
+# CHECK: Vreg: %95[ 15 ]
+# CHECK: Vreg: %325[ 1 ]
+# CHECK: Vreg: %332[ 1 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %19:sub0[ 59 ]
+# CHECK: Vreg: %19:sub1[ 60 ]
+# CHECK: Vreg: %19[ 72 ]
+# CHECK: Instr: S_BRANCH %bb.17
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %317[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %319[ 0 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %321[ 0 ]
+# CHECK: Vreg: %328[ 0 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %330[ 0 ]
+# CHECK: Vreg: %323[ 0 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %325[ 0 ]
+# CHECK: Vreg: %332[ 0 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %71[ 15 ]
+# CHECK: Vreg: %339[ 0 ]
+# CHECK: Vreg: %334[ 0 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %341[ 0 ]
+# CHECK: Vreg: %111[ 15 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %73[ 15 ]
+# CHECK: Vreg: %336[ 0 ]
+# CHECK: Vreg: %317[ 0 ]
+# CHECK: Vreg: %343[ 0 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %319[ 0 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %281[ 1 ]
+# CHECK: Vreg: %345[ 0 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %347[ 0 ]
+# CHECK: Vreg: %321[ 0 ]
+# CHECK: Vreg: %328[ 0 ]
+# CHECK: Vreg: %276[ 3 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 15 ]
+# CHECK: Vreg: %112[ 15 ]
+# CHECK: Vreg: %349[ 0 ]
+# CHECK: Vreg: %330[ 0 ]
+# CHECK: Vreg: %323[ 0 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %69[ 15 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %325[ 0 ]
+# CHECK: Vreg: %332[ 0 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: --- MBB_20 ---
+# CHECK: Instr: %395:vgpr_32 = V_ADD_U32_e64 1, %65, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 96 ]
+# CHECK: Vreg: %320[ 6 ]
+# CHECK: Vreg: %90[ 13 ]
+# CHECK: Vreg: %71[ 11 ]
+# CHECK: Vreg: %40[ 31 ]
+# CHECK: Vreg: %21[ 94 ]
+# CHECK: Vreg: %322[ 4 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %92[ 16 ]
+# CHECK: Vreg: %73[ 11 ]
+# CHECK: Vreg: %2[ 115 ]
+# CHECK: Vreg: %23[ 52 ]
+# CHECK: Vreg: %4[ 102 ]
+# CHECK: Vreg: %324[ 2 ]
+# CHECK: Vreg: %94[ 19 ]
+# CHECK: Vreg: %350[ 12 ]
+# CHECK: Vreg: %18[ 112 ]
+# CHECK: Vreg: %30[ 76 ]
+# CHECK: Vreg: %37[ 34 ]
+# CHECK: Vreg: %96[ 26 ]
+# CHECK: Vreg: %58[ 27 ]
+# CHECK: Vreg: %20[ 90 ]
+# CHECK: Vreg: %1[ 131 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22:sub0[ 42 ]
+# CHECK: Vreg: %22:sub1[ 43 ]
+# CHECK: Vreg: %22[ 107 ]
+# CHECK: Vreg: %67[ 11 ]
+# CHECK: Vreg: %112[ 11 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %318[ 8 ]
+# CHECK: Vreg: %43[ 28 ]
+# CHECK: Vreg: %5[ 100 ]
+# CHECK: Vreg: %69[ 11 ]
+# CHECK: Vreg: %95[ 22 ]
+# CHECK: Vreg: %19:sub0[ 66 ]
+# CHECK: Vreg: %19:sub1[ 67 ]
+# CHECK: Vreg: %19[ 79 ]
+# CHECK: Instr: %396:sreg_32 = V_CMP_GE_U32_e64 %395, %3, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 95 ]
+# CHECK: Vreg: %320[ 5 ]
+# CHECK: Vreg: %90[ 12 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %21[ 93 ]
+# CHECK: Vreg: %322[ 3 ]
+# CHECK: Vreg: %111[ 10 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %2[ 114 ]
+# CHECK: Vreg: %23[ 51 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %324[ 1 ]
+# CHECK: Vreg: %94[ 18 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %350[ 11 ]
+# CHECK: Vreg: %18[ 111 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %37[ 33 ]
+# CHECK: Vreg: %96[ 25 ]
+# CHECK: Vreg: %58[ 26 ]
+# CHECK: Vreg: %20[ 89 ]
+# CHECK: Vreg: %1[ 130 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %22:sub0[ 41 ]
+# CHECK: Vreg: %22:sub1[ 42 ]
+# CHECK: Vreg: %22[ 106 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %112[ 10 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %318[ 7 ]
+# CHECK: Vreg: %43[ 27 ]
+# CHECK: Vreg: %5[ 99 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 21 ]
+# CHECK: Vreg: %19:sub0[ 65 ]
+# CHECK: Vreg: %19:sub1[ 66 ]
+# CHECK: Vreg: %19[ 78 ]
+# CHECK: Instr: %397:sreg_32 = S_ANDN2_B32 killed %324, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 94 ]
+# CHECK: Vreg: %320[ 4 ]
+# CHECK: Vreg: %90[ 11 ]
+# CHECK: Vreg: %71[ 9 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 92 ]
+# CHECK: Vreg: %322[ 2 ]
+# CHECK: Vreg: %111[ 9 ]
+# CHECK: Vreg: %92[ 14 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %2[ 113 ]
+# CHECK: Vreg: %23[ 50 ]
+# CHECK: Vreg: %4[ 100 ]
+# CHECK: Vreg: %324[ 0 ]
+# CHECK: Vreg: %94[ 17 ]
+# CHECK: Vreg: %395[ 9 ]
+# CHECK: Vreg: %350[ 10 ]
+# CHECK: Vreg: %18[ 110 ]
+# CHECK: Vreg: %30[ 74 ]
+# CHECK: Vreg: %37[ 32 ]
+# CHECK: Vreg: %96[ 24 ]
+# CHECK: Vreg: %58[ 25 ]
+# CHECK: Vreg: %20[ 88 ]
+# CHECK: Vreg: %1[ 129 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %22:sub0[ 40 ]
+# CHECK: Vreg: %22:sub1[ 41 ]
+# CHECK: Vreg: %22[ 105 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 9 ]
+# CHECK: Vreg: %3[ 99 ]
+# CHECK: Vreg: %318[ 6 ]
+# CHECK: Vreg: %43[ 26 ]
+# CHECK: Vreg: %5[ 98 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %95[ 20 ]
+# CHECK: Vreg: %396[ 7 ]
+# CHECK: Vreg: %19:sub0[ 64 ]
+# CHECK: Vreg: %19:sub1[ 65 ]
+# CHECK: Vreg: %19[ 77 ]
+# CHECK: Instr: %398:sreg_32 = COPY killed %397
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 93 ]
+# CHECK: Vreg: %320[ 3 ]
+# CHECK: Vreg: %90[ 10 ]
+# CHECK: Vreg: %71[ 8 ]
+# CHECK: Vreg: %40[ 28 ]
+# CHECK: Vreg: %21[ 91 ]
+# CHECK: Vreg: %322[ 1 ]
+# CHECK: Vreg: %111[ 8 ]
+# CHECK: Vreg: %92[ 13 ]
+# CHECK: Vreg: %73[ 8 ]
+# CHECK: Vreg: %2[ 112 ]
+# CHECK: Vreg: %23[ 49 ]
+# CHECK: Vreg: %4[ 99 ]
+# CHECK: Vreg: %94[ 16 ]
+# CHECK: Vreg: %395[ 8 ]
+# CHECK: Vreg: %350[ 9 ]
+# CHECK: Vreg: %18[ 109 ]
+# CHECK: Vreg: %30[ 73 ]
+# CHECK: Vreg: %37[ 31 ]
+# CHECK: Vreg: %96[ 23 ]
+# CHECK: Vreg: %397[ 0 ]
+# CHECK: Vreg: %58[ 24 ]
+# CHECK: Vreg: %20[ 87 ]
+# CHECK: Vreg: %1[ 128 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %22:sub0[ 39 ]
+# CHECK: Vreg: %22:sub1[ 40 ]
+# CHECK: Vreg: %22[ 104 ]
+# CHECK: Vreg: %67[ 8 ]
+# CHECK: Vreg: %112[ 8 ]
+# CHECK: Vreg: %3[ 98 ]
+# CHECK: Vreg: %318[ 5 ]
+# CHECK: Vreg: %43[ 25 ]
+# CHECK: Vreg: %5[ 97 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %95[ 19 ]
+# CHECK: Vreg: %396[ 6 ]
+# CHECK: Vreg: %19:sub0[ 63 ]
+# CHECK: Vreg: %19:sub1[ 64 ]
+# CHECK: Vreg: %19[ 76 ]
+# CHECK: Instr: %399:sreg_32 = S_ANDN2_B32 killed %322, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 92 ]
+# CHECK: Vreg: %320[ 2 ]
+# CHECK: Vreg: %90[ 9 ]
+# CHECK: Vreg: %71[ 7 ]
+# CHECK: Vreg: %398[ 7 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 90 ]
+# CHECK: Vreg: %322[ 0 ]
+# CHECK: Vreg: %111[ 7 ]
+# CHECK: Vreg: %92[ 12 ]
+# CHECK: Vreg: %73[ 7 ]
+# CHECK: Vreg: %2[ 111 ]
+# CHECK: Vreg: %23[ 48 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %94[ 15 ]
+# CHECK: Vreg: %395[ 7 ]
+# CHECK: Vreg: %350[ 8 ]
+# CHECK: Vreg: %18[ 108 ]
+# CHECK: Vreg: %30[ 72 ]
+# CHECK: Vreg: %37[ 30 ]
+# CHECK: Vreg: %96[ 22 ]
+# CHECK: Vreg: %58[ 23 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 127 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %22:sub0[ 38 ]
+# CHECK: Vreg: %22:sub1[ 39 ]
+# CHECK: Vreg: %22[ 103 ]
+# CHECK: Vreg: %67[ 7 ]
+# CHECK: Vreg: %112[ 7 ]
+# CHECK: Vreg: %3[ 97 ]
+# CHECK: Vreg: %318[ 4 ]
+# CHECK: Vreg: %43[ 24 ]
+# CHECK: Vreg: %5[ 96 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %95[ 18 ]
+# CHECK: Vreg: %396[ 5 ]
+# CHECK: Vreg: %19:sub0[ 62 ]
+# CHECK: Vreg: %19:sub1[ 63 ]
+# CHECK: Vreg: %19[ 75 ]
+# CHECK: Instr: %400:sreg_32 = COPY killed %399
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 91 ]
+# CHECK: Vreg: %320[ 1 ]
+# CHECK: Vreg: %90[ 8 ]
+# CHECK: Vreg: %71[ 6 ]
+# CHECK: Vreg: %398[ 6 ]
+# CHECK: Vreg: %40[ 26 ]
+# CHECK: Vreg: %21[ 89 ]
+# CHECK: Vreg: %111[ 6 ]
+# CHECK: Vreg: %92[ 11 ]
+# CHECK: Vreg: %73[ 6 ]
+# CHECK: Vreg: %2[ 110 ]
+# CHECK: Vreg: %23[ 47 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %94[ 14 ]
+# CHECK: Vreg: %395[ 6 ]
+# CHECK: Vreg: %350[ 7 ]
+# CHECK: Vreg: %18[ 107 ]
+# CHECK: Vreg: %30[ 71 ]
+# CHECK: Vreg: %37[ 29 ]
+# CHECK: Vreg: %96[ 21 ]
+# CHECK: Vreg: %58[ 22 ]
+# CHECK: Vreg: %20[ 85 ]
+# CHECK: Vreg: %1[ 126 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %399[ 0 ]
+# CHECK: Vreg: %22:sub0[ 37 ]
+# CHECK: Vreg: %22:sub1[ 38 ]
+# CHECK: Vreg: %22[ 102 ]
+# CHECK: Vreg: %67[ 6 ]
+# CHECK: Vreg: %112[ 6 ]
+# CHECK: Vreg: %3[ 96 ]
+# CHECK: Vreg: %318[ 3 ]
+# CHECK: Vreg: %43[ 23 ]
+# CHECK: Vreg: %5[ 95 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %95[ 17 ]
+# CHECK: Vreg: %396[ 4 ]
+# CHECK: Vreg: %19:sub0[ 61 ]
+# CHECK: Vreg: %19:sub1[ 62 ]
+# CHECK: Vreg: %19[ 74 ]
+# CHECK: Instr: %401:sreg_32 = S_ANDN2_B32 killed %320, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 90 ]
+# CHECK: Vreg: %320[ 0 ]
+# CHECK: Vreg: %90[ 7 ]
+# CHECK: Vreg: %71[ 5 ]
+# CHECK: Vreg: %398[ 5 ]
+# CHECK: Vreg: %40[ 25 ]
+# CHECK: Vreg: %21[ 88 ]
+# CHECK: Vreg: %111[ 5 ]
+# CHECK: Vreg: %92[ 10 ]
+# CHECK: Vreg: %73[ 5 ]
+# CHECK: Vreg: %2[ 109 ]
+# CHECK: Vreg: %400[ 5 ]
+# CHECK: Vreg: %23[ 46 ]
+# CHECK: Vreg: %4[ 96 ]
+# CHECK: Vreg: %94[ 13 ]
+# CHECK: Vreg: %395[ 5 ]
+# CHECK: Vreg: %350[ 6 ]
+# CHECK: Vreg: %18[ 106 ]
+# CHECK: Vreg: %30[ 70 ]
+# CHECK: Vreg: %37[ 28 ]
+# CHECK: Vreg: %96[ 20 ]
+# CHECK: Vreg: %58[ 21 ]
+# CHECK: Vreg: %20[ 84 ]
+# CHECK: Vreg: %1[ 125 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %22:sub0[ 36 ]
+# CHECK: Vreg: %22:sub1[ 37 ]
+# CHECK: Vreg: %22[ 101 ]
+# CHECK: Vreg: %67[ 5 ]
+# CHECK: Vreg: %112[ 5 ]
+# CHECK: Vreg: %3[ 95 ]
+# CHECK: Vreg: %318[ 2 ]
+# CHECK: Vreg: %43[ 22 ]
+# CHECK: Vreg: %5[ 94 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %95[ 16 ]
+# CHECK: Vreg: %396[ 3 ]
+# CHECK: Vreg: %19:sub0[ 60 ]
+# CHECK: Vreg: %19:sub1[ 61 ]
+# CHECK: Vreg: %19[ 73 ]
+# CHECK: Instr: %402:sreg_32 = COPY killed %401
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 89 ]
+# CHECK: Vreg: %90[ 6 ]
+# CHECK: Vreg: %71[ 4 ]
+# CHECK: Vreg: %398[ 4 ]
+# CHECK: Vreg: %40[ 24 ]
+# CHECK: Vreg: %21[ 87 ]
+# CHECK: Vreg: %111[ 4 ]
+# CHECK: Vreg: %92[ 9 ]
+# CHECK: Vreg: %73[ 4 ]
+# CHECK: Vreg: %2[ 108 ]
+# CHECK: Vreg: %400[ 4 ]
+# CHECK: Vreg: %23[ 45 ]
+# CHECK: Vreg: %4[ 95 ]
+# CHECK: Vreg: %94[ 12 ]
+# CHECK: Vreg: %395[ 4 ]
+# CHECK: Vreg: %350[ 5 ]
+# CHECK: Vreg: %18[ 105 ]
+# CHECK: Vreg: %30[ 69 ]
+# CHECK: Vreg: %37[ 27 ]
+# CHECK: Vreg: %96[ 19 ]
+# CHECK: Vreg: %58[ 20 ]
+# CHECK: Vreg: %20[ 83 ]
+# CHECK: Vreg: %1[ 124 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %22:sub0[ 35 ]
+# CHECK: Vreg: %22:sub1[ 36 ]
+# CHECK: Vreg: %22[ 100 ]
+# CHECK: Vreg: %67[ 4 ]
+# CHECK: Vreg: %112[ 4 ]
+# CHECK: Vreg: %3[ 94 ]
+# CHECK: Vreg: %401[ 0 ]
+# CHECK: Vreg: %318[ 1 ]
+# CHECK: Vreg: %43[ 21 ]
+# CHECK: Vreg: %5[ 93 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %95[ 15 ]
+# CHECK: Vreg: %396[ 2 ]
+# CHECK: Vreg: %19:sub0[ 59 ]
+# CHECK: Vreg: %19:sub1[ 60 ]
+# CHECK: Vreg: %19[ 72 ]
+# CHECK: Instr: %403:sreg_32 = S_ANDN2_B32 killed %318, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 88 ]
+# CHECK: Vreg: %90[ 5 ]
+# CHECK: Vreg: %71[ 3 ]
+# CHECK: Vreg: %398[ 3 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %21[ 86 ]
+# CHECK: Vreg: %111[ 3 ]
+# CHECK: Vreg: %92[ 8 ]
+# CHECK: Vreg: %73[ 3 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %400[ 3 ]
+# CHECK: Vreg: %23[ 44 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %94[ 11 ]
+# CHECK: Vreg: %395[ 3 ]
+# CHECK: Vreg: %350[ 4 ]
+# CHECK: Vreg: %18[ 104 ]
+# CHECK: Vreg: %402[ 3 ]
+# CHECK: Vreg: %30[ 68 ]
+# CHECK: Vreg: %37[ 26 ]
+# CHECK: Vreg: %96[ 18 ]
+# CHECK: Vreg: %58[ 19 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %1[ 123 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %22:sub0[ 34 ]
+# CHECK: Vreg: %22:sub1[ 35 ]
+# CHECK: Vreg: %22[ 99 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %112[ 3 ]
+# CHECK: Vreg: %3[ 93 ]
+# CHECK: Vreg: %318[ 0 ]
+# CHECK: Vreg: %43[ 20 ]
+# CHECK: Vreg: %5[ 92 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %95[ 14 ]
+# CHECK: Vreg: %396[ 1 ]
+# CHECK: Vreg: %19:sub0[ 58 ]
+# CHECK: Vreg: %19:sub1[ 59 ]
+# CHECK: Vreg: %19[ 71 ]
+# CHECK: Instr: %404:sreg_32 = S_AND_B32 killed %396, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 87 ]
+# CHECK: Vreg: %90[ 4 ]
+# CHECK: Vreg: %71[ 2 ]
+# CHECK: Vreg: %403[ 1 ]
+# CHECK: Vreg: %398[ 2 ]
+# CHECK: Vreg: %40[ 22 ]
+# CHECK: Vreg: %21[ 85 ]
+# CHECK: Vreg: %111[ 2 ]
+# CHECK: Vreg: %92[ 7 ]
+# CHECK: Vreg: %73[ 2 ]
+# CHECK: Vreg: %2[ 106 ]
+# CHECK: Vreg: %400[ 2 ]
+# CHECK: Vreg: %23[ 43 ]
+# CHECK: Vreg: %4[ 93 ]
+# CHECK: Vreg: %94[ 10 ]
+# CHECK: Vreg: %395[ 2 ]
+# CHECK: Vreg: %350[ 3 ]
+# CHECK: Vreg: %18[ 103 ]
+# CHECK: Vreg: %402[ 2 ]
+# CHECK: Vreg: %30[ 67 ]
+# CHECK: Vreg: %37[ 25 ]
+# CHECK: Vreg: %96[ 17 ]
+# CHECK: Vreg: %58[ 18 ]
+# CHECK: Vreg: %20[ 81 ]
+# CHECK: Vreg: %1[ 122 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %22:sub0[ 33 ]
+# CHECK: Vreg: %22:sub1[ 34 ]
+# CHECK: Vreg: %22[ 98 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %112[ 2 ]
+# CHECK: Vreg: %3[ 92 ]
+# CHECK: Vreg: %43[ 19 ]
+# CHECK: Vreg: %5[ 91 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %95[ 13 ]
+# CHECK: Vreg: %396[ 0 ]
+# CHECK: Vreg: %19:sub0[ 57 ]
+# CHECK: Vreg: %19:sub1[ 58 ]
+# CHECK: Vreg: %19[ 70 ]
+# CHECK: Instr: %405:sreg_32 = S_OR_B32 killed %403, killed %404, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 86 ]
+# CHECK: Vreg: %90[ 3 ]
+# CHECK: Vreg: %71[ 1 ]
+# CHECK: Vreg: %403[ 0 ]
+# CHECK: Vreg: %398[ 1 ]
+# CHECK: Vreg: %40[ 21 ]
+# CHECK: Vreg: %21[ 84 ]
+# CHECK: Vreg: %111[ 1 ]
+# CHECK: Vreg: %92[ 6 ]
+# CHECK: Vreg: %73[ 1 ]
+# CHECK: Vreg: %2[ 105 ]
+# CHECK: Vreg: %400[ 1 ]
+# CHECK: Vreg: %23[ 42 ]
+# CHECK: Vreg: %4[ 92 ]
+# CHECK: Vreg: %94[ 9 ]
+# CHECK: Vreg: %395[ 1 ]
+# CHECK: Vreg: %350[ 2 ]
+# CHECK: Vreg: %18[ 102 ]
+# CHECK: Vreg: %402[ 1 ]
+# CHECK: Vreg: %30[ 66 ]
+# CHECK: Vreg: %37[ 24 ]
+# CHECK: Vreg: %96[ 16 ]
+# CHECK: Vreg: %58[ 17 ]
+# CHECK: Vreg: %20[ 80 ]
+# CHECK: Vreg: %1[ 121 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %404[ 0 ]
+# CHECK: Vreg: %22:sub0[ 32 ]
+# CHECK: Vreg: %22:sub1[ 33 ]
+# CHECK: Vreg: %22[ 97 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %112[ 1 ]
+# CHECK: Vreg: %3[ 91 ]
+# CHECK: Vreg: %43[ 18 ]
+# CHECK: Vreg: %5[ 90 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %95[ 12 ]
+# CHECK: Vreg: %19:sub0[ 56 ]
+# CHECK: Vreg: %19:sub1[ 57 ]
+# CHECK: Vreg: %19[ 69 ]
+# CHECK: Instr: S_BRANCH %bb.33
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %398[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %405[ 0 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %400[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %402[ 0 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %398[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %405[ 0 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %400[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %402[ 0 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: --- MBB_21 ---
+# CHECK: Instr: %406:sreg_32 = PHI %362, %bb.18, %407, %bb.24
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %362[ 0 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %414[ 0 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %409[ 0 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %407[ 0 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Instr: %408:sreg_32 = PHI %362, %bb.18, %409, %bb.24
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %362[ 0 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %414[ 0 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %409[ 0 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %406[ 8 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Instr: %410:vgpr_32 = PHI undef %411:vgpr_32, %bb.18, %71, %bb.24
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %414[ 0 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %406[ 8 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %408[ 2 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Instr: %412:vgpr_32 = PHI undef %411:vgpr_32, %bb.18, %358, %bb.24
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %410[ 9 ]
+# CHECK: Vreg: %71[ 9 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %414[ 0 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %406[ 8 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %408[ 2 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Instr: %413:vgpr_32 = PHI undef %411:vgpr_32, %bb.18, %414, %bb.24
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %410[ 9 ]
+# CHECK: Vreg: %71[ 9 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %412[ 9 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %414[ 0 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %406[ 8 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %408[ 2 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Instr: %415:vgpr_32 = PHI undef %411:vgpr_32, %bb.18, %69, %bb.24
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %410[ 9 ]
+# CHECK: Vreg: %71[ 9 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %412[ 9 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %414[ 0 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %413[ 9 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %406[ 8 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %408[ 2 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Instr: %416:vgpr_32 = PHI undef %417:vgpr_32, %bb.18, %414, %bb.24
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %410[ 9 ]
+# CHECK: Vreg: %71[ 9 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %412[ 9 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %414[ 0 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %413[ 9 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %406[ 8 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %408[ 2 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %415[ 9 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Instr: SI_END_CF killed %363, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 111 ]
+# CHECK: Vreg: %256[ 21 ]
+# CHECK: Vreg: %90[ 28 ]
+# CHECK: Vreg: %410[ 8 ]
+# CHECK: Vreg: %71[ 8 ]
+# CHECK: Vreg: %363[ 0 ]
+# CHECK: Vreg: %315[ 9 ]
+# CHECK: Vreg: %40[ 46 ]
+# CHECK: Vreg: %21[ 109 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %111[ 38 ]
+# CHECK: Vreg: %412[ 8 ]
+# CHECK: Vreg: %73[ 8 ]
+# CHECK: Vreg: %92[ 31 ]
+# CHECK: Vreg: %23[ 67 ]
+# CHECK: Vreg: %4[ 117 ]
+# CHECK: Vreg: %260[ 5 ]
+# CHECK: Vreg: %94[ 34 ]
+# CHECK: Vreg: %30[ 91 ]
+# CHECK: Vreg: %37[ 49 ]
+# CHECK: Vreg: %18[ 127 ]
+# CHECK: Vreg: %281[ 24 ]
+# CHECK: Vreg: %262[ 3 ]
+# CHECK: Vreg: %416[ 8 ]
+# CHECK: Vreg: %96[ 41 ]
+# CHECK: Vreg: %58[ 42 ]
+# CHECK: Vreg: %20[ 105 ]
+# CHECK: Vreg: %1[ 146 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %276[ 26 ]
+# CHECK: Vreg: %22:sub0[ 57 ]
+# CHECK: Vreg: %22:sub1[ 58 ]
+# CHECK: Vreg: %22[ 122 ]
+# CHECK: Vreg: %67[ 8 ]
+# CHECK: Vreg: %112[ 38 ]
+# CHECK: Vreg: %413[ 8 ]
+# CHECK: Vreg: %3[ 28 ]
+# CHECK: Vreg: %406[ 7 ]
+# CHECK: Vreg: %43[ 43 ]
+# CHECK: Vreg: %408[ 1 ]
+# CHECK: Vreg: %5[ 115 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %95[ 37 ]
+# CHECK: Vreg: %415[ 8 ]
+# CHECK: Vreg: %249[ 22 ]
+# CHECK: Vreg: %19:sub0[ 81 ]
+# CHECK: Vreg: %19:sub1[ 82 ]
+# CHECK: Vreg: %19[ 94 ]
+# CHECK: Instr: %418:sreg_32 = S_AND_B32 killed %408, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 110 ]
+# CHECK: Vreg: %256[ 20 ]
+# CHECK: Vreg: %90[ 27 ]
+# CHECK: Vreg: %410[ 7 ]
+# CHECK: Vreg: %71[ 7 ]
+# CHECK: Vreg: %315[ 8 ]
+# CHECK: Vreg: %40[ 45 ]
+# CHECK: Vreg: %21[ 108 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %111[ 37 ]
+# CHECK: Vreg: %412[ 7 ]
+# CHECK: Vreg: %73[ 7 ]
+# CHECK: Vreg: %92[ 30 ]
+# CHECK: Vreg: %23[ 66 ]
+# CHECK: Vreg: %4[ 116 ]
+# CHECK: Vreg: %260[ 4 ]
+# CHECK: Vreg: %94[ 33 ]
+# CHECK: Vreg: %30[ 90 ]
+# CHECK: Vreg: %37[ 48 ]
+# CHECK: Vreg: %18[ 126 ]
+# CHECK: Vreg: %281[ 23 ]
+# CHECK: Vreg: %262[ 2 ]
+# CHECK: Vreg: %416[ 7 ]
+# CHECK: Vreg: %96[ 40 ]
+# CHECK: Vreg: %58[ 41 ]
+# CHECK: Vreg: %20[ 104 ]
+# CHECK: Vreg: %1[ 145 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %276[ 25 ]
+# CHECK: Vreg: %22:sub0[ 56 ]
+# CHECK: Vreg: %22:sub1[ 57 ]
+# CHECK: Vreg: %22[ 121 ]
+# CHECK: Vreg: %67[ 7 ]
+# CHECK: Vreg: %112[ 37 ]
+# CHECK: Vreg: %413[ 7 ]
+# CHECK: Vreg: %3[ 27 ]
+# CHECK: Vreg: %406[ 6 ]
+# CHECK: Vreg: %43[ 42 ]
+# CHECK: Vreg: %408[ 0 ]
+# CHECK: Vreg: %5[ 114 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %95[ 36 ]
+# CHECK: Vreg: %415[ 7 ]
+# CHECK: Vreg: %249[ 21 ]
+# CHECK: Vreg: %19:sub0[ 80 ]
+# CHECK: Vreg: %19:sub1[ 81 ]
+# CHECK: Vreg: %19[ 93 ]
+# CHECK: Instr: %419:sreg_32 = COPY killed %418
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 109 ]
+# CHECK: Vreg: %256[ 19 ]
+# CHECK: Vreg: %90[ 26 ]
+# CHECK: Vreg: %410[ 6 ]
+# CHECK: Vreg: %71[ 6 ]
+# CHECK: Vreg: %315[ 7 ]
+# CHECK: Vreg: %40[ 44 ]
+# CHECK: Vreg: %21[ 107 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %111[ 36 ]
+# CHECK: Vreg: %412[ 6 ]
+# CHECK: Vreg: %73[ 6 ]
+# CHECK: Vreg: %92[ 29 ]
+# CHECK: Vreg: %23[ 65 ]
+# CHECK: Vreg: %4[ 115 ]
+# CHECK: Vreg: %260[ 3 ]
+# CHECK: Vreg: %94[ 32 ]
+# CHECK: Vreg: %30[ 89 ]
+# CHECK: Vreg: %37[ 47 ]
+# CHECK: Vreg: %18[ 125 ]
+# CHECK: Vreg: %281[ 22 ]
+# CHECK: Vreg: %262[ 1 ]
+# CHECK: Vreg: %416[ 6 ]
+# CHECK: Vreg: %96[ 39 ]
+# CHECK: Vreg: %58[ 40 ]
+# CHECK: Vreg: %20[ 103 ]
+# CHECK: Vreg: %1[ 144 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %276[ 24 ]
+# CHECK: Vreg: %418[ 0 ]
+# CHECK: Vreg: %22:sub0[ 55 ]
+# CHECK: Vreg: %22:sub1[ 56 ]
+# CHECK: Vreg: %22[ 120 ]
+# CHECK: Vreg: %67[ 6 ]
+# CHECK: Vreg: %112[ 36 ]
+# CHECK: Vreg: %413[ 6 ]
+# CHECK: Vreg: %3[ 26 ]
+# CHECK: Vreg: %406[ 5 ]
+# CHECK: Vreg: %43[ 41 ]
+# CHECK: Vreg: %5[ 113 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %95[ 35 ]
+# CHECK: Vreg: %415[ 6 ]
+# CHECK: Vreg: %249[ 20 ]
+# CHECK: Vreg: %19:sub0[ 79 ]
+# CHECK: Vreg: %19:sub1[ 80 ]
+# CHECK: Vreg: %19[ 92 ]
+# CHECK: Instr: %420:sreg_32 = S_ANDN2_B32 %262, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 108 ]
+# CHECK: Vreg: %256[ 18 ]
+# CHECK: Vreg: %90[ 25 ]
+# CHECK: Vreg: %410[ 5 ]
+# CHECK: Vreg: %71[ 5 ]
+# CHECK: Vreg: %315[ 6 ]
+# CHECK: Vreg: %40[ 43 ]
+# CHECK: Vreg: %21[ 106 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %111[ 35 ]
+# CHECK: Vreg: %412[ 5 ]
+# CHECK: Vreg: %73[ 5 ]
+# CHECK: Vreg: %419[ 5 ]
+# CHECK: Vreg: %92[ 28 ]
+# CHECK: Vreg: %23[ 64 ]
+# CHECK: Vreg: %4[ 114 ]
+# CHECK: Vreg: %260[ 2 ]
+# CHECK: Vreg: %94[ 31 ]
+# CHECK: Vreg: %30[ 88 ]
+# CHECK: Vreg: %37[ 46 ]
+# CHECK: Vreg: %18[ 124 ]
+# CHECK: Vreg: %281[ 21 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %416[ 5 ]
+# CHECK: Vreg: %96[ 38 ]
+# CHECK: Vreg: %58[ 39 ]
+# CHECK: Vreg: %20[ 102 ]
+# CHECK: Vreg: %1[ 143 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %276[ 23 ]
+# CHECK: Vreg: %22:sub0[ 54 ]
+# CHECK: Vreg: %22:sub1[ 55 ]
+# CHECK: Vreg: %22[ 119 ]
+# CHECK: Vreg: %67[ 5 ]
+# CHECK: Vreg: %112[ 35 ]
+# CHECK: Vreg: %413[ 5 ]
+# CHECK: Vreg: %3[ 25 ]
+# CHECK: Vreg: %406[ 4 ]
+# CHECK: Vreg: %43[ 40 ]
+# CHECK: Vreg: %5[ 112 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %95[ 34 ]
+# CHECK: Vreg: %415[ 5 ]
+# CHECK: Vreg: %249[ 19 ]
+# CHECK: Vreg: %19:sub0[ 78 ]
+# CHECK: Vreg: %19:sub1[ 79 ]
+# CHECK: Vreg: %19[ 91 ]
+# CHECK: Instr: %421:sreg_32 = COPY killed %420
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 107 ]
+# CHECK: Vreg: %256[ 17 ]
+# CHECK: Vreg: %90[ 24 ]
+# CHECK: Vreg: %410[ 4 ]
+# CHECK: Vreg: %71[ 4 ]
+# CHECK: Vreg: %315[ 5 ]
+# CHECK: Vreg: %40[ 42 ]
+# CHECK: Vreg: %21[ 105 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %111[ 34 ]
+# CHECK: Vreg: %412[ 4 ]
+# CHECK: Vreg: %73[ 4 ]
+# CHECK: Vreg: %419[ 4 ]
+# CHECK: Vreg: %92[ 27 ]
+# CHECK: Vreg: %23[ 63 ]
+# CHECK: Vreg: %4[ 113 ]
+# CHECK: Vreg: %260[ 1 ]
+# CHECK: Vreg: %94[ 30 ]
+# CHECK: Vreg: %30[ 87 ]
+# CHECK: Vreg: %37[ 45 ]
+# CHECK: Vreg: %18[ 123 ]
+# CHECK: Vreg: %281[ 20 ]
+# CHECK: Vreg: %416[ 4 ]
+# CHECK: Vreg: %96[ 37 ]
+# CHECK: Vreg: %58[ 38 ]
+# CHECK: Vreg: %20[ 101 ]
+# CHECK: Vreg: %1[ 142 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 22 ]
+# CHECK: Vreg: %22:sub0[ 53 ]
+# CHECK: Vreg: %22:sub1[ 54 ]
+# CHECK: Vreg: %22[ 118 ]
+# CHECK: Vreg: %67[ 4 ]
+# CHECK: Vreg: %112[ 34 ]
+# CHECK: Vreg: %413[ 4 ]
+# CHECK: Vreg: %3[ 24 ]
+# CHECK: Vreg: %406[ 3 ]
+# CHECK: Vreg: %420[ 0 ]
+# CHECK: Vreg: %43[ 39 ]
+# CHECK: Vreg: %5[ 111 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %95[ 33 ]
+# CHECK: Vreg: %415[ 4 ]
+# CHECK: Vreg: %249[ 18 ]
+# CHECK: Vreg: %19:sub0[ 77 ]
+# CHECK: Vreg: %19:sub1[ 78 ]
+# CHECK: Vreg: %19[ 90 ]
+# CHECK: Instr: %422:sreg_32 = S_ANDN2_B32 %260, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 106 ]
+# CHECK: Vreg: %256[ 16 ]
+# CHECK: Vreg: %90[ 23 ]
+# CHECK: Vreg: %410[ 3 ]
+# CHECK: Vreg: %71[ 3 ]
+# CHECK: Vreg: %315[ 4 ]
+# CHECK: Vreg: %40[ 41 ]
+# CHECK: Vreg: %21[ 104 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %111[ 33 ]
+# CHECK: Vreg: %412[ 3 ]
+# CHECK: Vreg: %73[ 3 ]
+# CHECK: Vreg: %419[ 3 ]
+# CHECK: Vreg: %92[ 26 ]
+# CHECK: Vreg: %23[ 62 ]
+# CHECK: Vreg: %4[ 112 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 29 ]
+# CHECK: Vreg: %30[ 86 ]
+# CHECK: Vreg: %37[ 44 ]
+# CHECK: Vreg: %18[ 122 ]
+# CHECK: Vreg: %421[ 3 ]
+# CHECK: Vreg: %281[ 19 ]
+# CHECK: Vreg: %416[ 3 ]
+# CHECK: Vreg: %96[ 36 ]
+# CHECK: Vreg: %58[ 37 ]
+# CHECK: Vreg: %20[ 100 ]
+# CHECK: Vreg: %1[ 141 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %276[ 21 ]
+# CHECK: Vreg: %22:sub0[ 52 ]
+# CHECK: Vreg: %22:sub1[ 53 ]
+# CHECK: Vreg: %22[ 117 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %112[ 33 ]
+# CHECK: Vreg: %413[ 3 ]
+# CHECK: Vreg: %3[ 23 ]
+# CHECK: Vreg: %406[ 2 ]
+# CHECK: Vreg: %43[ 38 ]
+# CHECK: Vreg: %5[ 110 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %95[ 32 ]
+# CHECK: Vreg: %415[ 3 ]
+# CHECK: Vreg: %249[ 17 ]
+# CHECK: Vreg: %19:sub0[ 76 ]
+# CHECK: Vreg: %19:sub1[ 77 ]
+# CHECK: Vreg: %19[ 89 ]
+# CHECK: Instr: %423:sreg_32 = COPY killed %422
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 105 ]
+# CHECK: Vreg: %256[ 15 ]
+# CHECK: Vreg: %90[ 22 ]
+# CHECK: Vreg: %410[ 2 ]
+# CHECK: Vreg: %71[ 2 ]
+# CHECK: Vreg: %315[ 3 ]
+# CHECK: Vreg: %40[ 40 ]
+# CHECK: Vreg: %21[ 103 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %111[ 32 ]
+# CHECK: Vreg: %412[ 2 ]
+# CHECK: Vreg: %73[ 2 ]
+# CHECK: Vreg: %419[ 2 ]
+# CHECK: Vreg: %92[ 25 ]
+# CHECK: Vreg: %23[ 61 ]
+# CHECK: Vreg: %4[ 111 ]
+# CHECK: Vreg: %94[ 28 ]
+# CHECK: Vreg: %30[ 85 ]
+# CHECK: Vreg: %37[ 43 ]
+# CHECK: Vreg: %18[ 121 ]
+# CHECK: Vreg: %421[ 2 ]
+# CHECK: Vreg: %281[ 18 ]
+# CHECK: Vreg: %416[ 2 ]
+# CHECK: Vreg: %96[ 35 ]
+# CHECK: Vreg: %58[ 36 ]
+# CHECK: Vreg: %20[ 99 ]
+# CHECK: Vreg: %1[ 140 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %276[ 20 ]
+# CHECK: Vreg: %22:sub0[ 51 ]
+# CHECK: Vreg: %22:sub1[ 52 ]
+# CHECK: Vreg: %22[ 116 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %112[ 32 ]
+# CHECK: Vreg: %413[ 2 ]
+# CHECK: Vreg: %3[ 22 ]
+# CHECK: Vreg: %406[ 1 ]
+# CHECK: Vreg: %43[ 37 ]
+# CHECK: Vreg: %5[ 109 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %95[ 31 ]
+# CHECK: Vreg: %415[ 2 ]
+# CHECK: Vreg: %249[ 16 ]
+# CHECK: Vreg: %422[ 0 ]
+# CHECK: Vreg: %19:sub0[ 75 ]
+# CHECK: Vreg: %19:sub1[ 76 ]
+# CHECK: Vreg: %19[ 88 ]
+# CHECK: Instr: %424:sreg_32 = S_ORN2_B32 killed %406, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %256[ 14 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %410[ 1 ]
+# CHECK: Vreg: %71[ 1 ]
+# CHECK: Vreg: %315[ 2 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %111[ 31 ]
+# CHECK: Vreg: %412[ 1 ]
+# CHECK: Vreg: %73[ 1 ]
+# CHECK: Vreg: %419[ 1 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %18[ 120 ]
+# CHECK: Vreg: %421[ 1 ]
+# CHECK: Vreg: %281[ 17 ]
+# CHECK: Vreg: %416[ 1 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %423[ 1 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 139 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %276[ 19 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %22[ 115 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %112[ 31 ]
+# CHECK: Vreg: %413[ 1 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %406[ 0 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %415[ 1 ]
+# CHECK: Vreg: %249[ 15 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Vreg: %19[ 87 ]
+# CHECK: Instr: S_BRANCH %bb.23
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %410[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %412[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %424[ 0 ]
+# CHECK: Vreg: %419[ 0 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %421[ 0 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %423[ 0 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %413[ 0 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %415[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %410[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %412[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %424[ 0 ]
+# CHECK: Vreg: %419[ 0 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %421[ 0 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %423[ 0 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %413[ 0 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %415[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: --- MBB_22 ---
+# CHECK: Instr: %381:vgpr_32 = V_ADD_U32_e64 1, %67, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %71[ 11 ]
+# CHECK: Vreg: %365[ 8 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %73[ 11 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 18 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %388[ 12 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 15 ]
+# CHECK: Vreg: %371[ 4 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %378[ 11 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %368[ 6 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 11 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 11 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Instr: %425:sreg_32 = V_CMP_GE_U32_e64 %381, %2, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 111 ]
+# CHECK: Vreg: %256[ 21 ]
+# CHECK: Vreg: %90[ 28 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %365[ 7 ]
+# CHECK: Vreg: %40[ 46 ]
+# CHECK: Vreg: %21[ 109 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %111[ 38 ]
+# CHECK: Vreg: %92[ 31 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %374[ 1 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %23[ 67 ]
+# CHECK: Vreg: %4[ 117 ]
+# CHECK: Vreg: %260[ 17 ]
+# CHECK: Vreg: %94[ 34 ]
+# CHECK: Vreg: %388[ 11 ]
+# CHECK: Vreg: %30[ 91 ]
+# CHECK: Vreg: %18[ 127 ]
+# CHECK: Vreg: %37[ 49 ]
+# CHECK: Vreg: %281[ 24 ]
+# CHECK: Vreg: %262[ 14 ]
+# CHECK: Vreg: %371[ 3 ]
+# CHECK: Vreg: %96[ 41 ]
+# CHECK: Vreg: %378[ 10 ]
+# CHECK: Vreg: %58[ 42 ]
+# CHECK: Vreg: %20[ 105 ]
+# CHECK: Vreg: %1[ 146 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %276[ 26 ]
+# CHECK: Vreg: %22:sub0[ 57 ]
+# CHECK: Vreg: %22:sub1[ 58 ]
+# CHECK: Vreg: %22[ 122 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %112[ 38 ]
+# CHECK: Vreg: %368[ 5 ]
+# CHECK: Vreg: %3[ 28 ]
+# CHECK: Vreg: %43[ 43 ]
+# CHECK: Vreg: %5[ 115 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 37 ]
+# CHECK: Vreg: %249[ 10 ]
+# CHECK: Vreg: %19:sub0[ 81 ]
+# CHECK: Vreg: %19:sub1[ 82 ]
+# CHECK: Vreg: %19[ 94 ]
+# CHECK: Instr: %426:sreg_32 = S_ANDN2_B32 killed %374, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 110 ]
+# CHECK: Vreg: %256[ 20 ]
+# CHECK: Vreg: %90[ 27 ]
+# CHECK: Vreg: %71[ 9 ]
+# CHECK: Vreg: %365[ 6 ]
+# CHECK: Vreg: %40[ 45 ]
+# CHECK: Vreg: %21[ 108 ]
+# CHECK: Vreg: %2[ 129 ]
+# CHECK: Vreg: %111[ 37 ]
+# CHECK: Vreg: %92[ 30 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %374[ 0 ]
+# CHECK: Vreg: %381[ 9 ]
+# CHECK: Vreg: %23[ 66 ]
+# CHECK: Vreg: %4[ 116 ]
+# CHECK: Vreg: %260[ 16 ]
+# CHECK: Vreg: %94[ 33 ]
+# CHECK: Vreg: %388[ 10 ]
+# CHECK: Vreg: %30[ 90 ]
+# CHECK: Vreg: %18[ 126 ]
+# CHECK: Vreg: %37[ 48 ]
+# CHECK: Vreg: %281[ 23 ]
+# CHECK: Vreg: %262[ 13 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %96[ 40 ]
+# CHECK: Vreg: %378[ 9 ]
+# CHECK: Vreg: %58[ 41 ]
+# CHECK: Vreg: %20[ 104 ]
+# CHECK: Vreg: %1[ 145 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 25 ]
+# CHECK: Vreg: %425[ 7 ]
+# CHECK: Vreg: %22:sub0[ 56 ]
+# CHECK: Vreg: %22:sub1[ 57 ]
+# CHECK: Vreg: %22[ 121 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 37 ]
+# CHECK: Vreg: %368[ 4 ]
+# CHECK: Vreg: %3[ 27 ]
+# CHECK: Vreg: %43[ 42 ]
+# CHECK: Vreg: %5[ 114 ]
+# CHECK: Vreg: %69[ 9 ]
+# CHECK: Vreg: %95[ 36 ]
+# CHECK: Vreg: %249[ 9 ]
+# CHECK: Vreg: %19:sub0[ 80 ]
+# CHECK: Vreg: %19:sub1[ 81 ]
+# CHECK: Vreg: %19[ 93 ]
+# CHECK: Instr: %375:sreg_32 = COPY killed %426
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 109 ]
+# CHECK: Vreg: %256[ 19 ]
+# CHECK: Vreg: %90[ 26 ]
+# CHECK: Vreg: %71[ 8 ]
+# CHECK: Vreg: %365[ 5 ]
+# CHECK: Vreg: %40[ 44 ]
+# CHECK: Vreg: %21[ 107 ]
+# CHECK: Vreg: %2[ 128 ]
+# CHECK: Vreg: %111[ 36 ]
+# CHECK: Vreg: %92[ 29 ]
+# CHECK: Vreg: %73[ 8 ]
+# CHECK: Vreg: %381[ 8 ]
+# CHECK: Vreg: %426[ 0 ]
+# CHECK: Vreg: %23[ 65 ]
+# CHECK: Vreg: %4[ 115 ]
+# CHECK: Vreg: %260[ 15 ]
+# CHECK: Vreg: %94[ 32 ]
+# CHECK: Vreg: %388[ 9 ]
+# CHECK: Vreg: %30[ 89 ]
+# CHECK: Vreg: %18[ 125 ]
+# CHECK: Vreg: %37[ 47 ]
+# CHECK: Vreg: %281[ 22 ]
+# CHECK: Vreg: %262[ 12 ]
+# CHECK: Vreg: %371[ 1 ]
+# CHECK: Vreg: %96[ 39 ]
+# CHECK: Vreg: %378[ 8 ]
+# CHECK: Vreg: %58[ 40 ]
+# CHECK: Vreg: %20[ 103 ]
+# CHECK: Vreg: %1[ 144 ]
+# CHECK: Vreg: %65[ 8 ]
+# CHECK: Vreg: %276[ 24 ]
+# CHECK: Vreg: %425[ 6 ]
+# CHECK: Vreg: %22:sub0[ 55 ]
+# CHECK: Vreg: %22:sub1[ 56 ]
+# CHECK: Vreg: %22[ 120 ]
+# CHECK: Vreg: %67[ 8 ]
+# CHECK: Vreg: %112[ 36 ]
+# CHECK: Vreg: %368[ 3 ]
+# CHECK: Vreg: %3[ 26 ]
+# CHECK: Vreg: %43[ 41 ]
+# CHECK: Vreg: %5[ 113 ]
+# CHECK: Vreg: %69[ 8 ]
+# CHECK: Vreg: %95[ 35 ]
+# CHECK: Vreg: %249[ 8 ]
+# CHECK: Vreg: %19:sub0[ 79 ]
+# CHECK: Vreg: %19:sub1[ 80 ]
+# CHECK: Vreg: %19[ 92 ]
+# CHECK: Instr: %427:sreg_32 = S_ANDN2_B32 killed %371, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 108 ]
+# CHECK: Vreg: %256[ 18 ]
+# CHECK: Vreg: %90[ 25 ]
+# CHECK: Vreg: %71[ 7 ]
+# CHECK: Vreg: %365[ 4 ]
+# CHECK: Vreg: %40[ 43 ]
+# CHECK: Vreg: %21[ 106 ]
+# CHECK: Vreg: %2[ 127 ]
+# CHECK: Vreg: %111[ 35 ]
+# CHECK: Vreg: %92[ 28 ]
+# CHECK: Vreg: %73[ 7 ]
+# CHECK: Vreg: %381[ 7 ]
+# CHECK: Vreg: %23[ 64 ]
+# CHECK: Vreg: %4[ 114 ]
+# CHECK: Vreg: %260[ 14 ]
+# CHECK: Vreg: %94[ 31 ]
+# CHECK: Vreg: %388[ 8 ]
+# CHECK: Vreg: %30[ 88 ]
+# CHECK: Vreg: %18[ 124 ]
+# CHECK: Vreg: %37[ 46 ]
+# CHECK: Vreg: %281[ 21 ]
+# CHECK: Vreg: %262[ 11 ]
+# CHECK: Vreg: %371[ 0 ]
+# CHECK: Vreg: %96[ 38 ]
+# CHECK: Vreg: %378[ 7 ]
+# CHECK: Vreg: %58[ 39 ]
+# CHECK: Vreg: %20[ 102 ]
+# CHECK: Vreg: %1[ 143 ]
+# CHECK: Vreg: %65[ 7 ]
+# CHECK: Vreg: %276[ 23 ]
+# CHECK: Vreg: %425[ 5 ]
+# CHECK: Vreg: %22:sub0[ 54 ]
+# CHECK: Vreg: %22:sub1[ 55 ]
+# CHECK: Vreg: %22[ 119 ]
+# CHECK: Vreg: %67[ 7 ]
+# CHECK: Vreg: %112[ 35 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %3[ 25 ]
+# CHECK: Vreg: %375[ 7 ]
+# CHECK: Vreg: %43[ 40 ]
+# CHECK: Vreg: %5[ 112 ]
+# CHECK: Vreg: %69[ 7 ]
+# CHECK: Vreg: %95[ 34 ]
+# CHECK: Vreg: %249[ 7 ]
+# CHECK: Vreg: %19:sub0[ 78 ]
+# CHECK: Vreg: %19:sub1[ 79 ]
+# CHECK: Vreg: %19[ 91 ]
+# CHECK: Instr: %372:sreg_32 = COPY killed %427
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 107 ]
+# CHECK: Vreg: %256[ 17 ]
+# CHECK: Vreg: %90[ 24 ]
+# CHECK: Vreg: %71[ 6 ]
+# CHECK: Vreg: %365[ 3 ]
+# CHECK: Vreg: %40[ 42 ]
+# CHECK: Vreg: %21[ 105 ]
+# CHECK: Vreg: %2[ 126 ]
+# CHECK: Vreg: %111[ 34 ]
+# CHECK: Vreg: %92[ 27 ]
+# CHECK: Vreg: %73[ 6 ]
+# CHECK: Vreg: %381[ 6 ]
+# CHECK: Vreg: %23[ 63 ]
+# CHECK: Vreg: %4[ 113 ]
+# CHECK: Vreg: %260[ 13 ]
+# CHECK: Vreg: %94[ 30 ]
+# CHECK: Vreg: %388[ 7 ]
+# CHECK: Vreg: %30[ 87 ]
+# CHECK: Vreg: %18[ 123 ]
+# CHECK: Vreg: %37[ 45 ]
+# CHECK: Vreg: %281[ 20 ]
+# CHECK: Vreg: %262[ 10 ]
+# CHECK: Vreg: %96[ 37 ]
+# CHECK: Vreg: %378[ 6 ]
+# CHECK: Vreg: %58[ 38 ]
+# CHECK: Vreg: %20[ 101 ]
+# CHECK: Vreg: %1[ 142 ]
+# CHECK: Vreg: %65[ 6 ]
+# CHECK: Vreg: %276[ 22 ]
+# CHECK: Vreg: %425[ 4 ]
+# CHECK: Vreg: %22:sub0[ 53 ]
+# CHECK: Vreg: %22:sub1[ 54 ]
+# CHECK: Vreg: %22[ 118 ]
+# CHECK: Vreg: %67[ 6 ]
+# CHECK: Vreg: %112[ 34 ]
+# CHECK: Vreg: %368[ 1 ]
+# CHECK: Vreg: %3[ 24 ]
+# CHECK: Vreg: %375[ 6 ]
+# CHECK: Vreg: %43[ 39 ]
+# CHECK: Vreg: %427[ 0 ]
+# CHECK: Vreg: %5[ 111 ]
+# CHECK: Vreg: %69[ 6 ]
+# CHECK: Vreg: %95[ 33 ]
+# CHECK: Vreg: %249[ 6 ]
+# CHECK: Vreg: %19:sub0[ 77 ]
+# CHECK: Vreg: %19:sub1[ 78 ]
+# CHECK: Vreg: %19[ 90 ]
+# CHECK: Instr: %428:sreg_32 = S_ANDN2_B32 killed %368, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 106 ]
+# CHECK: Vreg: %256[ 16 ]
+# CHECK: Vreg: %90[ 23 ]
+# CHECK: Vreg: %71[ 5 ]
+# CHECK: Vreg: %372[ 5 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %40[ 41 ]
+# CHECK: Vreg: %21[ 104 ]
+# CHECK: Vreg: %2[ 125 ]
+# CHECK: Vreg: %111[ 33 ]
+# CHECK: Vreg: %92[ 26 ]
+# CHECK: Vreg: %73[ 5 ]
+# CHECK: Vreg: %381[ 5 ]
+# CHECK: Vreg: %23[ 62 ]
+# CHECK: Vreg: %4[ 112 ]
+# CHECK: Vreg: %260[ 12 ]
+# CHECK: Vreg: %94[ 29 ]
+# CHECK: Vreg: %388[ 6 ]
+# CHECK: Vreg: %30[ 86 ]
+# CHECK: Vreg: %18[ 122 ]
+# CHECK: Vreg: %37[ 44 ]
+# CHECK: Vreg: %281[ 19 ]
+# CHECK: Vreg: %262[ 9 ]
+# CHECK: Vreg: %96[ 36 ]
+# CHECK: Vreg: %378[ 5 ]
+# CHECK: Vreg: %58[ 37 ]
+# CHECK: Vreg: %20[ 100 ]
+# CHECK: Vreg: %1[ 141 ]
+# CHECK: Vreg: %65[ 5 ]
+# CHECK: Vreg: %276[ 21 ]
+# CHECK: Vreg: %425[ 3 ]
+# CHECK: Vreg: %22:sub0[ 52 ]
+# CHECK: Vreg: %22:sub1[ 53 ]
+# CHECK: Vreg: %22[ 117 ]
+# CHECK: Vreg: %67[ 5 ]
+# CHECK: Vreg: %112[ 33 ]
+# CHECK: Vreg: %368[ 0 ]
+# CHECK: Vreg: %3[ 23 ]
+# CHECK: Vreg: %375[ 5 ]
+# CHECK: Vreg: %43[ 38 ]
+# CHECK: Vreg: %5[ 110 ]
+# CHECK: Vreg: %69[ 5 ]
+# CHECK: Vreg: %95[ 32 ]
+# CHECK: Vreg: %249[ 5 ]
+# CHECK: Vreg: %19:sub0[ 76 ]
+# CHECK: Vreg: %19:sub1[ 77 ]
+# CHECK: Vreg: %19[ 89 ]
+# CHECK: Instr: %369:sreg_32 = COPY killed %428
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 105 ]
+# CHECK: Vreg: %256[ 15 ]
+# CHECK: Vreg: %90[ 22 ]
+# CHECK: Vreg: %71[ 4 ]
+# CHECK: Vreg: %372[ 4 ]
+# CHECK: Vreg: %365[ 1 ]
+# CHECK: Vreg: %40[ 40 ]
+# CHECK: Vreg: %21[ 103 ]
+# CHECK: Vreg: %2[ 124 ]
+# CHECK: Vreg: %111[ 32 ]
+# CHECK: Vreg: %92[ 25 ]
+# CHECK: Vreg: %73[ 4 ]
+# CHECK: Vreg: %381[ 4 ]
+# CHECK: Vreg: %23[ 61 ]
+# CHECK: Vreg: %4[ 111 ]
+# CHECK: Vreg: %260[ 11 ]
+# CHECK: Vreg: %94[ 28 ]
+# CHECK: Vreg: %388[ 5 ]
+# CHECK: Vreg: %30[ 85 ]
+# CHECK: Vreg: %18[ 121 ]
+# CHECK: Vreg: %37[ 43 ]
+# CHECK: Vreg: %281[ 18 ]
+# CHECK: Vreg: %262[ 8 ]
+# CHECK: Vreg: %428[ 0 ]
+# CHECK: Vreg: %96[ 35 ]
+# CHECK: Vreg: %378[ 4 ]
+# CHECK: Vreg: %58[ 36 ]
+# CHECK: Vreg: %20[ 99 ]
+# CHECK: Vreg: %1[ 140 ]
+# CHECK: Vreg: %65[ 4 ]
+# CHECK: Vreg: %276[ 20 ]
+# CHECK: Vreg: %425[ 2 ]
+# CHECK: Vreg: %22:sub0[ 51 ]
+# CHECK: Vreg: %22:sub1[ 52 ]
+# CHECK: Vreg: %22[ 116 ]
+# CHECK: Vreg: %67[ 4 ]
+# CHECK: Vreg: %112[ 32 ]
+# CHECK: Vreg: %3[ 22 ]
+# CHECK: Vreg: %375[ 4 ]
+# CHECK: Vreg: %43[ 37 ]
+# CHECK: Vreg: %5[ 109 ]
+# CHECK: Vreg: %69[ 4 ]
+# CHECK: Vreg: %95[ 31 ]
+# CHECK: Vreg: %249[ 4 ]
+# CHECK: Vreg: %19:sub0[ 75 ]
+# CHECK: Vreg: %19:sub1[ 76 ]
+# CHECK: Vreg: %19[ 88 ]
+# CHECK: Instr: %429:sreg_32 = S_ANDN2_B32 killed %365, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %256[ 14 ]
+# CHECK: Vreg: %90[ 21 ]
+# CHECK: Vreg: %71[ 3 ]
+# CHECK: Vreg: %372[ 3 ]
+# CHECK: Vreg: %365[ 0 ]
+# CHECK: Vreg: %40[ 39 ]
+# CHECK: Vreg: %21[ 102 ]
+# CHECK: Vreg: %2[ 123 ]
+# CHECK: Vreg: %111[ 31 ]
+# CHECK: Vreg: %92[ 24 ]
+# CHECK: Vreg: %73[ 3 ]
+# CHECK: Vreg: %381[ 3 ]
+# CHECK: Vreg: %23[ 60 ]
+# CHECK: Vreg: %4[ 110 ]
+# CHECK: Vreg: %260[ 10 ]
+# CHECK: Vreg: %94[ 27 ]
+# CHECK: Vreg: %388[ 4 ]
+# CHECK: Vreg: %369[ 3 ]
+# CHECK: Vreg: %30[ 84 ]
+# CHECK: Vreg: %18[ 120 ]
+# CHECK: Vreg: %37[ 42 ]
+# CHECK: Vreg: %281[ 17 ]
+# CHECK: Vreg: %262[ 7 ]
+# CHECK: Vreg: %96[ 34 ]
+# CHECK: Vreg: %378[ 3 ]
+# CHECK: Vreg: %58[ 35 ]
+# CHECK: Vreg: %20[ 98 ]
+# CHECK: Vreg: %1[ 139 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %276[ 19 ]
+# CHECK: Vreg: %425[ 1 ]
+# CHECK: Vreg: %22:sub0[ 50 ]
+# CHECK: Vreg: %22:sub1[ 51 ]
+# CHECK: Vreg: %22[ 115 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %112[ 31 ]
+# CHECK: Vreg: %3[ 21 ]
+# CHECK: Vreg: %375[ 3 ]
+# CHECK: Vreg: %43[ 36 ]
+# CHECK: Vreg: %5[ 108 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %95[ 30 ]
+# CHECK: Vreg: %249[ 3 ]
+# CHECK: Vreg: %19:sub0[ 74 ]
+# CHECK: Vreg: %19:sub1[ 75 ]
+# CHECK: Vreg: %19[ 87 ]
+# CHECK: Instr: %430:sreg_32 = S_AND_B32 killed %425, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %71[ 2 ]
+# CHECK: Vreg: %372[ 2 ]
+# CHECK: Vreg: %429[ 1 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %2[ 122 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %73[ 2 ]
+# CHECK: Vreg: %381[ 2 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %388[ 3 ]
+# CHECK: Vreg: %369[ 2 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %378[ 2 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %425[ 0 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %375[ 2 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %249[ 2 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Instr: %366:sreg_32 = S_OR_B32 killed %429, killed %430, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 102 ]
+# CHECK: Vreg: %256[ 12 ]
+# CHECK: Vreg: %90[ 19 ]
+# CHECK: Vreg: %71[ 1 ]
+# CHECK: Vreg: %372[ 1 ]
+# CHECK: Vreg: %429[ 0 ]
+# CHECK: Vreg: %40[ 37 ]
+# CHECK: Vreg: %21[ 100 ]
+# CHECK: Vreg: %2[ 121 ]
+# CHECK: Vreg: %111[ 29 ]
+# CHECK: Vreg: %92[ 22 ]
+# CHECK: Vreg: %73[ 1 ]
+# CHECK: Vreg: %381[ 1 ]
+# CHECK: Vreg: %23[ 58 ]
+# CHECK: Vreg: %4[ 108 ]
+# CHECK: Vreg: %260[ 8 ]
+# CHECK: Vreg: %94[ 25 ]
+# CHECK: Vreg: %388[ 2 ]
+# CHECK: Vreg: %369[ 1 ]
+# CHECK: Vreg: %30[ 82 ]
+# CHECK: Vreg: %18[ 118 ]
+# CHECK: Vreg: %37[ 40 ]
+# CHECK: Vreg: %281[ 15 ]
+# CHECK: Vreg: %262[ 5 ]
+# CHECK: Vreg: %96[ 32 ]
+# CHECK: Vreg: %378[ 1 ]
+# CHECK: Vreg: %58[ 33 ]
+# CHECK: Vreg: %20[ 96 ]
+# CHECK: Vreg: %1[ 137 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %430[ 0 ]
+# CHECK: Vreg: %276[ 17 ]
+# CHECK: Vreg: %22:sub0[ 48 ]
+# CHECK: Vreg: %22:sub1[ 49 ]
+# CHECK: Vreg: %22[ 113 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %112[ 29 ]
+# CHECK: Vreg: %3[ 19 ]
+# CHECK: Vreg: %375[ 1 ]
+# CHECK: Vreg: %43[ 34 ]
+# CHECK: Vreg: %5[ 106 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %95[ 28 ]
+# CHECK: Vreg: %249[ 1 ]
+# CHECK: Vreg: %19:sub0[ 72 ]
+# CHECK: Vreg: %19:sub1[ 73 ]
+# CHECK: Vreg: %19[ 85 ]
+# CHECK: Instr: S_BRANCH %bb.19
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %372[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %369[ 0 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %378[ 0 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %366[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %375[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %249[ 0 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %372[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %381[ 0 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %369[ 0 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %378[ 0 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %366[ 0 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %375[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %249[ 0 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: --- MBB_23 ---
+# CHECK: Instr: %365:sreg_32 = PHI %304, %bb.16, %424, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %412[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %419[ 0 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %423[ 0 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %413[ 0 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %410[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %424[ 0 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %421[ 0 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %314[ 0 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %304[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %415[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Instr: %368:sreg_32 = PHI %260, %bb.16, %423, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %412[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %419[ 0 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 0 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %423[ 0 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %413[ 0 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %410[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %421[ 0 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %314[ 0 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %415[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Instr: %371:sreg_32 = PHI %262, %bb.16, %421, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %412[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %419[ 0 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %413[ 0 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %410[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %421[ 0 ]
+# CHECK: Vreg: %262[ 0 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %314[ 0 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %415[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Instr: %374:sreg_32 = PHI %314, %bb.16, %419, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %412[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %419[ 0 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %413[ 0 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %410[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %314[ 0 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %415[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Instr: %376:vgpr_32 = PHI undef %431:vgpr_32, %bb.16, %410, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %412[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %413[ 0 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %410[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %415[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Instr: %377:vgpr_32 = PHI undef %431:vgpr_32, %bb.16, %412, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %412[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %413[ 0 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %376[ 2 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %415[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Instr: %379:vgpr_32 = PHI undef %431:vgpr_32, %bb.16, %413, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %413[ 0 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %376[ 2 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %415[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %377[ 2 ]
+# CHECK: Instr: %380:vgpr_32 = PHI undef %431:vgpr_32, %bb.16, %415, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %379[ 2 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %376[ 2 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %415[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %377[ 2 ]
+# CHECK: Instr: %382:vgpr_32 = PHI undef %432:vgpr_32, %bb.16, %416, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %416[ 0 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %379[ 2 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %376[ 2 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %380[ 2 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %377[ 2 ]
+# CHECK: Instr: %383:vgpr_32 = PHI undef %431:vgpr_32, %bb.16, %65, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %382[ 2 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %379[ 2 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %376[ 2 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %380[ 2 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %377[ 2 ]
+# CHECK: Instr: %384:vgpr_32 = PHI undef %431:vgpr_32, %bb.16, %67, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %382[ 2 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %379[ 2 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %376[ 2 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %383[ 2 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %380[ 2 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %377[ 2 ]
+# CHECK: Instr: %385:vgpr_32 = PHI undef %431:vgpr_32, %bb.16, %69, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %384[ 2 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %382[ 2 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %379[ 2 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %376[ 2 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %383[ 2 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %380[ 2 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %377[ 2 ]
+# CHECK: Instr: %386:vgpr_32 = PHI undef %431:vgpr_32, %bb.16, %71, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %384[ 2 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %385[ 2 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %382[ 2 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %379[ 2 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %376[ 2 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %383[ 2 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %380[ 2 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %377[ 2 ]
+# CHECK: Instr: %387:vgpr_32 = PHI undef %431:vgpr_32, %bb.16, %73, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %384[ 2 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %385[ 2 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %382[ 2 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %71[ 14 ]
+# CHECK: Vreg: %379[ 2 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %386[ 2 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %376[ 2 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %383[ 2 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %380[ 2 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %377[ 2 ]
+# CHECK: Instr: %378:vgpr_32 = PHI %313, %bb.16, undef %433:vgpr_32, %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %256[ 13 ]
+# CHECK: Vreg: %90[ 20 ]
+# CHECK: Vreg: %384[ 2 ]
+# CHECK: Vreg: %315[ 1 ]
+# CHECK: Vreg: %21[ 101 ]
+# CHECK: Vreg: %111[ 30 ]
+# CHECK: Vreg: %73[ 14 ]
+# CHECK: Vreg: %374[ 2 ]
+# CHECK: Vreg: %4[ 109 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 26 ]
+# CHECK: Vreg: %18[ 119 ]
+# CHECK: Vreg: %281[ 16 ]
+# CHECK: Vreg: %371[ 2 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %385[ 2 ]
+# CHECK: Vreg: %22:sub0[ 49 ]
+# CHECK: Vreg: %22:sub1[ 50 ]
+# CHECK: Vreg: %22[ 114 ]
+# CHECK: Vreg: %67[ 3 ]
+# CHECK: Vreg: %112[ 30 ]
+# CHECK: Vreg: %368[ 2 ]
+# CHECK: Vreg: %382[ 2 ]
+# CHECK: Vreg: %43[ 35 ]
+# CHECK: Vreg: %5[ 107 ]
+# CHECK: Vreg: %95[ 29 ]
+# CHECK: Vreg: %313[ 0 ]
+# CHECK: Vreg: %19:sub0[ 73 ]
+# CHECK: Vreg: %19:sub1[ 74 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Vreg: %365[ 2 ]
+# CHECK: Vreg: %71[ 14 ]
+# CHECK: Vreg: %379[ 2 ]
+# CHECK: Vreg: %40[ 38 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %386[ 2 ]
+# CHECK: Vreg: %92[ 23 ]
+# CHECK: Vreg: %23[ 59 ]
+# CHECK: Vreg: %30[ 83 ]
+# CHECK: Vreg: %376[ 2 ]
+# CHECK: Vreg: %37[ 41 ]
+# CHECK: Vreg: %383[ 2 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 33 ]
+# CHECK: Vreg: %58[ 34 ]
+# CHECK: Vreg: %20[ 97 ]
+# CHECK: Vreg: %65[ 14 ]
+# CHECK: Vreg: %276[ 18 ]
+# CHECK: Vreg: %380[ 2 ]
+# CHECK: Vreg: %3[ 20 ]
+# CHECK: Vreg: %387[ 2 ]
+# CHECK: Vreg: %69[ 14 ]
+# CHECK: Vreg: %249[ 14 ]
+# CHECK: Vreg: %377[ 2 ]
+# CHECK: Instr: %388:sreg_32 = SI_ELSE killed %315, %bb.19, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 102 ]
+# CHECK: Vreg: %256[ 12 ]
+# CHECK: Vreg: %90[ 19 ]
+# CHECK: Vreg: %384[ 1 ]
+# CHECK: Vreg: %315[ 0 ]
+# CHECK: Vreg: %21[ 100 ]
+# CHECK: Vreg: %111[ 29 ]
+# CHECK: Vreg: %73[ 13 ]
+# CHECK: Vreg: %374[ 1 ]
+# CHECK: Vreg: %4[ 108 ]
+# CHECK: Vreg: %260[ 8 ]
+# CHECK: Vreg: %94[ 25 ]
+# CHECK: Vreg: %18[ 118 ]
+# CHECK: Vreg: %281[ 15 ]
+# CHECK: Vreg: %371[ 1 ]
+# CHECK: Vreg: %378[ 13 ]
+# CHECK: Vreg: %1[ 137 ]
+# CHECK: Vreg: %385[ 1 ]
+# CHECK: Vreg: %22:sub0[ 48 ]
+# CHECK: Vreg: %22:sub1[ 49 ]
+# CHECK: Vreg: %22[ 113 ]
+# CHECK: Vreg: %67[ 2 ]
+# CHECK: Vreg: %112[ 29 ]
+# CHECK: Vreg: %368[ 1 ]
+# CHECK: Vreg: %382[ 1 ]
+# CHECK: Vreg: %43[ 34 ]
+# CHECK: Vreg: %5[ 106 ]
+# CHECK: Vreg: %95[ 28 ]
+# CHECK: Vreg: %19:sub0[ 72 ]
+# CHECK: Vreg: %19:sub1[ 73 ]
+# CHECK: Vreg: %19[ 85 ]
+# CHECK: Vreg: %365[ 1 ]
+# CHECK: Vreg: %71[ 13 ]
+# CHECK: Vreg: %379[ 1 ]
+# CHECK: Vreg: %40[ 37 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %386[ 1 ]
+# CHECK: Vreg: %92[ 22 ]
+# CHECK: Vreg: %23[ 58 ]
+# CHECK: Vreg: %30[ 82 ]
+# CHECK: Vreg: %376[ 1 ]
+# CHECK: Vreg: %37[ 40 ]
+# CHECK: Vreg: %383[ 1 ]
+# CHECK: Vreg: %262[ 5 ]
+# CHECK: Vreg: %96[ 32 ]
+# CHECK: Vreg: %58[ 33 ]
+# CHECK: Vreg: %20[ 96 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %276[ 17 ]
+# CHECK: Vreg: %380[ 1 ]
+# CHECK: Vreg: %3[ 19 ]
+# CHECK: Vreg: %387[ 1 ]
+# CHECK: Vreg: %69[ 13 ]
+# CHECK: Vreg: %249[ 13 ]
+# CHECK: Vreg: %377[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.22
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %73[ 12 ]
+# CHECK: Vreg: %374[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %371[ 0 ]
+# CHECK: Vreg: %378[ 12 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %368[ 0 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %365[ 0 ]
+# CHECK: Vreg: %71[ 12 ]
+# CHECK: Vreg: %379[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %376[ 0 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %249[ 12 ]
+# CHECK: Vreg: %377[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %256[ 11 ]
+# CHECK: Vreg: %90[ 18 ]
+# CHECK: Vreg: %384[ 0 ]
+# CHECK: Vreg: %21[ 99 ]
+# CHECK: Vreg: %111[ 28 ]
+# CHECK: Vreg: %73[ 12 ]
+# CHECK: Vreg: %374[ 0 ]
+# CHECK: Vreg: %4[ 107 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 24 ]
+# CHECK: Vreg: %388[ 1 ]
+# CHECK: Vreg: %18[ 117 ]
+# CHECK: Vreg: %281[ 14 ]
+# CHECK: Vreg: %371[ 0 ]
+# CHECK: Vreg: %378[ 12 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %385[ 0 ]
+# CHECK: Vreg: %22:sub0[ 47 ]
+# CHECK: Vreg: %22:sub1[ 48 ]
+# CHECK: Vreg: %22[ 112 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %112[ 28 ]
+# CHECK: Vreg: %368[ 0 ]
+# CHECK: Vreg: %382[ 0 ]
+# CHECK: Vreg: %43[ 33 ]
+# CHECK: Vreg: %5[ 105 ]
+# CHECK: Vreg: %95[ 27 ]
+# CHECK: Vreg: %19:sub0[ 71 ]
+# CHECK: Vreg: %19:sub1[ 72 ]
+# CHECK: Vreg: %19[ 84 ]
+# CHECK: Vreg: %365[ 0 ]
+# CHECK: Vreg: %71[ 12 ]
+# CHECK: Vreg: %379[ 0 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %386[ 0 ]
+# CHECK: Vreg: %92[ 21 ]
+# CHECK: Vreg: %23[ 57 ]
+# CHECK: Vreg: %30[ 81 ]
+# CHECK: Vreg: %376[ 0 ]
+# CHECK: Vreg: %37[ 39 ]
+# CHECK: Vreg: %383[ 0 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %96[ 31 ]
+# CHECK: Vreg: %58[ 32 ]
+# CHECK: Vreg: %20[ 95 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %276[ 16 ]
+# CHECK: Vreg: %380[ 0 ]
+# CHECK: Vreg: %3[ 18 ]
+# CHECK: Vreg: %387[ 0 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %249[ 12 ]
+# CHECK: Vreg: %377[ 0 ]
+# CHECK: --- MBB_24 ---
+# CHECK: Instr: %414:vgpr_32 = V_ADD_U32_e64 1, %69, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 116 ]
+# CHECK: Vreg: %256[ 26 ]
+# CHECK: Vreg: %90[ 33 ]
+# CHECK: Vreg: %71[ 4 ]
+# CHECK: Vreg: %315[ 14 ]
+# CHECK: Vreg: %40[ 51 ]
+# CHECK: Vreg: %21[ 114 ]
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %111[ 43 ]
+# CHECK: Vreg: %92[ 36 ]
+# CHECK: Vreg: %73[ 13 ]
+# CHECK: Vreg: %23[ 72 ]
+# CHECK: Vreg: %4[ 122 ]
+# CHECK: Vreg: %260[ 10 ]
+# CHECK: Vreg: %94[ 39 ]
+# CHECK: Vreg: %30[ 96 ]
+# CHECK: Vreg: %37[ 54 ]
+# CHECK: Vreg: %18[ 132 ]
+# CHECK: Vreg: %281[ 29 ]
+# CHECK: Vreg: %262[ 8 ]
+# CHECK: Vreg: %96[ 46 ]
+# CHECK: Vreg: %58[ 47 ]
+# CHECK: Vreg: %20[ 110 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %276[ 31 ]
+# CHECK: Vreg: %22:sub0[ 62 ]
+# CHECK: Vreg: %22:sub1[ 63 ]
+# CHECK: Vreg: %22[ 127 ]
+# CHECK: Vreg: %67[ 13 ]
+# CHECK: Vreg: %112[ 43 ]
+# CHECK: Vreg: %3[ 33 ]
+# CHECK: Vreg: %363[ 5 ]
+# CHECK: Vreg: %43[ 48 ]
+# CHECK: Vreg: %5[ 120 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 42 ]
+# CHECK: Vreg: %249[ 27 ]
+# CHECK: Vreg: %358[ 4 ]
+# CHECK: Vreg: %19:sub0[ 86 ]
+# CHECK: Vreg: %19:sub1[ 87 ]
+# CHECK: Vreg: %19[ 99 ]
+# CHECK: Instr: %434:sreg_32 = V_CMP_GE_U32_e64 %414, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 115 ]
+# CHECK: Vreg: %256[ 25 ]
+# CHECK: Vreg: %90[ 32 ]
+# CHECK: Vreg: %71[ 3 ]
+# CHECK: Vreg: %315[ 13 ]
+# CHECK: Vreg: %40[ 50 ]
+# CHECK: Vreg: %21[ 113 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %111[ 42 ]
+# CHECK: Vreg: %92[ 35 ]
+# CHECK: Vreg: %73[ 12 ]
+# CHECK: Vreg: %23[ 71 ]
+# CHECK: Vreg: %4[ 121 ]
+# CHECK: Vreg: %260[ 9 ]
+# CHECK: Vreg: %94[ 38 ]
+# CHECK: Vreg: %30[ 95 ]
+# CHECK: Vreg: %37[ 53 ]
+# CHECK: Vreg: %18[ 131 ]
+# CHECK: Vreg: %414[ 0 ]
+# CHECK: Vreg: %281[ 28 ]
+# CHECK: Vreg: %262[ 7 ]
+# CHECK: Vreg: %96[ 45 ]
+# CHECK: Vreg: %58[ 46 ]
+# CHECK: Vreg: %20[ 109 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %276[ 30 ]
+# CHECK: Vreg: %22:sub0[ 61 ]
+# CHECK: Vreg: %22:sub1[ 62 ]
+# CHECK: Vreg: %22[ 126 ]
+# CHECK: Vreg: %67[ 12 ]
+# CHECK: Vreg: %112[ 42 ]
+# CHECK: Vreg: %3[ 32 ]
+# CHECK: Vreg: %363[ 4 ]
+# CHECK: Vreg: %43[ 47 ]
+# CHECK: Vreg: %5[ 119 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Vreg: %95[ 41 ]
+# CHECK: Vreg: %249[ 26 ]
+# CHECK: Vreg: %358[ 3 ]
+# CHECK: Vreg: %19:sub0[ 85 ]
+# CHECK: Vreg: %19:sub1[ 86 ]
+# CHECK: Vreg: %19[ 98 ]
+# CHECK: Instr: %409:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 114 ]
+# CHECK: Vreg: %256[ 24 ]
+# CHECK: Vreg: %90[ 31 ]
+# CHECK: Vreg: %71[ 2 ]
+# CHECK: Vreg: %434[ 1 ]
+# CHECK: Vreg: %315[ 12 ]
+# CHECK: Vreg: %40[ 49 ]
+# CHECK: Vreg: %21[ 112 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %111[ 41 ]
+# CHECK: Vreg: %92[ 34 ]
+# CHECK: Vreg: %73[ 11 ]
+# CHECK: Vreg: %23[ 70 ]
+# CHECK: Vreg: %4[ 120 ]
+# CHECK: Vreg: %260[ 8 ]
+# CHECK: Vreg: %94[ 37 ]
+# CHECK: Vreg: %30[ 94 ]
+# CHECK: Vreg: %37[ 52 ]
+# CHECK: Vreg: %18[ 130 ]
+# CHECK: Vreg: %414[ 2 ]
+# CHECK: Vreg: %281[ 27 ]
+# CHECK: Vreg: %262[ 6 ]
+# CHECK: Vreg: %96[ 44 ]
+# CHECK: Vreg: %58[ 45 ]
+# CHECK: Vreg: %20[ 108 ]
+# CHECK: Vreg: %1[ 149 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %276[ 29 ]
+# CHECK: Vreg: %22:sub0[ 60 ]
+# CHECK: Vreg: %22:sub1[ 61 ]
+# CHECK: Vreg: %22[ 125 ]
+# CHECK: Vreg: %67[ 11 ]
+# CHECK: Vreg: %112[ 41 ]
+# CHECK: Vreg: %3[ 31 ]
+# CHECK: Vreg: %363[ 3 ]
+# CHECK: Vreg: %43[ 46 ]
+# CHECK: Vreg: %5[ 118 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Vreg: %95[ 40 ]
+# CHECK: Vreg: %249[ 25 ]
+# CHECK: Vreg: %358[ 2 ]
+# CHECK: Vreg: %19:sub0[ 84 ]
+# CHECK: Vreg: %19:sub1[ 85 ]
+# CHECK: Vreg: %19[ 97 ]
+# CHECK: Instr: %407:sreg_32 = S_ORN2_B32 killed %434, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 113 ]
+# CHECK: Vreg: %256[ 23 ]
+# CHECK: Vreg: %90[ 30 ]
+# CHECK: Vreg: %71[ 1 ]
+# CHECK: Vreg: %434[ 0 ]
+# CHECK: Vreg: %315[ 11 ]
+# CHECK: Vreg: %40[ 48 ]
+# CHECK: Vreg: %21[ 111 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %111[ 40 ]
+# CHECK: Vreg: %92[ 33 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %23[ 69 ]
+# CHECK: Vreg: %4[ 119 ]
+# CHECK: Vreg: %260[ 7 ]
+# CHECK: Vreg: %94[ 36 ]
+# CHECK: Vreg: %30[ 93 ]
+# CHECK: Vreg: %37[ 51 ]
+# CHECK: Vreg: %18[ 129 ]
+# CHECK: Vreg: %414[ 1 ]
+# CHECK: Vreg: %281[ 26 ]
+# CHECK: Vreg: %262[ 5 ]
+# CHECK: Vreg: %409[ 1 ]
+# CHECK: Vreg: %96[ 43 ]
+# CHECK: Vreg: %58[ 44 ]
+# CHECK: Vreg: %20[ 107 ]
+# CHECK: Vreg: %1[ 148 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %276[ 28 ]
+# CHECK: Vreg: %22:sub0[ 59 ]
+# CHECK: Vreg: %22:sub1[ 60 ]
+# CHECK: Vreg: %22[ 124 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %112[ 40 ]
+# CHECK: Vreg: %3[ 30 ]
+# CHECK: Vreg: %363[ 2 ]
+# CHECK: Vreg: %43[ 45 ]
+# CHECK: Vreg: %5[ 117 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Vreg: %95[ 39 ]
+# CHECK: Vreg: %249[ 24 ]
+# CHECK: Vreg: %358[ 1 ]
+# CHECK: Vreg: %19:sub0[ 83 ]
+# CHECK: Vreg: %19:sub1[ 84 ]
+# CHECK: Vreg: %19[ 96 ]
+# CHECK: Instr: S_BRANCH %bb.21
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %414[ 0 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %409[ 0 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %407[ 0 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %256[ 22 ]
+# CHECK: Vreg: %90[ 29 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %315[ 10 ]
+# CHECK: Vreg: %40[ 47 ]
+# CHECK: Vreg: %21[ 110 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 39 ]
+# CHECK: Vreg: %92[ 32 ]
+# CHECK: Vreg: %73[ 9 ]
+# CHECK: Vreg: %23[ 68 ]
+# CHECK: Vreg: %4[ 118 ]
+# CHECK: Vreg: %260[ 6 ]
+# CHECK: Vreg: %94[ 35 ]
+# CHECK: Vreg: %30[ 92 ]
+# CHECK: Vreg: %37[ 50 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %414[ 0 ]
+# CHECK: Vreg: %281[ 25 ]
+# CHECK: Vreg: %262[ 4 ]
+# CHECK: Vreg: %409[ 0 ]
+# CHECK: Vreg: %96[ 42 ]
+# CHECK: Vreg: %58[ 43 ]
+# CHECK: Vreg: %20[ 106 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %65[ 9 ]
+# CHECK: Vreg: %276[ 27 ]
+# CHECK: Vreg: %407[ 0 ]
+# CHECK: Vreg: %22:sub0[ 58 ]
+# CHECK: Vreg: %22:sub1[ 59 ]
+# CHECK: Vreg: %22[ 123 ]
+# CHECK: Vreg: %67[ 9 ]
+# CHECK: Vreg: %112[ 39 ]
+# CHECK: Vreg: %3[ 29 ]
+# CHECK: Vreg: %363[ 1 ]
+# CHECK: Vreg: %43[ 44 ]
+# CHECK: Vreg: %5[ 116 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 38 ]
+# CHECK: Vreg: %249[ 23 ]
+# CHECK: Vreg: %358[ 0 ]
+# CHECK: Vreg: %19:sub0[ 82 ]
+# CHECK: Vreg: %19:sub1[ 83 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: --- MBB_25 ---
+# CHECK: Instr: %435:vgpr_32 = PHI undef %436:vgpr_32, %bb.34, %437, %bb.31
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 10 ]
+# CHECK: Vreg: %443[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %122[ 10 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %437[ 0 ]
+# CHECK: Instr: %438:vreg_64 = PHI %21, %bb.34, undef %439:vreg_64, %bb.31
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 10 ]
+# CHECK: Vreg: %443[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %435[ 2 ]
+# CHECK: Vreg: %122[ 10 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Instr: %440:vreg_64 = PHI %20, %bb.34, undef %441:vreg_64, %bb.31
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 10 ]
+# CHECK: Vreg: %443[ 1 ]
+# CHECK: Vreg: %438[ 3 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %435[ 2 ]
+# CHECK: Vreg: %122[ 10 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Instr: %442:sreg_32 = SI_ELSE killed %443, %bb.32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 9 ]
+# CHECK: Vreg: %443[ 0 ]
+# CHECK: Vreg: %438[ 2 ]
+# CHECK: Vreg: %30[ 3 ]
+# CHECK: Vreg: %440[ 10 ]
+# CHECK: Vreg: %435[ 1 ]
+# CHECK: Vreg: %122[ 9 ]
+# CHECK: Instr: S_BRANCH %bb.26
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 8 ]
+# CHECK: Vreg: %438[ 1 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %440[ 9 ]
+# CHECK: Vreg: %435[ 0 ]
+# CHECK: Vreg: %442[ 1 ]
+# CHECK: Vreg: %122[ 8 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %128[ 8 ]
+# CHECK: Vreg: %438[ 1 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %440[ 9 ]
+# CHECK: Vreg: %435[ 0 ]
+# CHECK: Vreg: %442[ 1 ]
+# CHECK: Vreg: %122[ 8 ]
+# CHECK: --- MBB_26 ---
+# CHECK: Instr: %444:vgpr_32 = GLOBAL_LOAD_UBYTE %438, 0, 0, implicit $exec :: (load (s8) from %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 7 ]
+# CHECK: Vreg: %438[ 0 ]
+# CHECK: Vreg: %30[ 16 ]
+# CHECK: Vreg: %440[ 8 ]
+# CHECK: Vreg: %442[ 15 ]
+# CHECK: Vreg: %122[ 7 ]
+# CHECK: Instr: %445:vgpr_32 = GLOBAL_LOAD_UBYTE %438, 1, 0, implicit $exec :: (load (s8) from %ir.p3 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 6 ]
+# CHECK: Vreg: %438[ 0 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %440[ 7 ]
+# CHECK: Vreg: %442[ 14 ]
+# CHECK: Vreg: %122[ 6 ]
+# CHECK: Vreg: %444[ 1 ]
+# CHECK: Instr: %446:vgpr_32 = V_LSHL_OR_B32_e64 killed %445, 8, killed %444, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 5 ]
+# CHECK: Vreg: %438[ 1 ]
+# CHECK: Vreg: %445[ 0 ]
+# CHECK: Vreg: %30[ 14 ]
+# CHECK: Vreg: %440[ 6 ]
+# CHECK: Vreg: %442[ 13 ]
+# CHECK: Vreg: %122[ 5 ]
+# CHECK: Vreg: %444[ 0 ]
+# CHECK: Instr: %447:vgpr_32 = GLOBAL_LOAD_UBYTE %438, 2, 0, implicit $exec :: (load (s8) from %ir.p3 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 4 ]
+# CHECK: Vreg: %438[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %440[ 5 ]
+# CHECK: Vreg: %442[ 12 ]
+# CHECK: Vreg: %122[ 4 ]
+# CHECK: Vreg: %446[ 3 ]
+# CHECK: Instr: %448:vgpr_32 = GLOBAL_LOAD_UBYTE killed %438, 3, 0, implicit $exec :: (load (s8) from %ir.p3 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 3 ]
+# CHECK: Vreg: %438[ 0 ]
+# CHECK: Vreg: %30[ 12 ]
+# CHECK: Vreg: %440[ 4 ]
+# CHECK: Vreg: %447[ 1 ]
+# CHECK: Vreg: %442[ 11 ]
+# CHECK: Vreg: %122[ 3 ]
+# CHECK: Vreg: %446[ 2 ]
+# CHECK: Instr: %449:vgpr_32 = V_LSHL_OR_B32_e64 killed %448, 8, killed %447, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 2 ]
+# CHECK: Vreg: %448[ 0 ]
+# CHECK: Vreg: %30[ 11 ]
+# CHECK: Vreg: %440[ 3 ]
+# CHECK: Vreg: %447[ 0 ]
+# CHECK: Vreg: %442[ 10 ]
+# CHECK: Vreg: %122[ 2 ]
+# CHECK: Vreg: %446[ 1 ]
+# CHECK: Instr: %450:vgpr_32 = V_LSHL_OR_B32_e64 killed %449, 16, killed %446, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 1 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %440[ 2 ]
+# CHECK: Vreg: %442[ 9 ]
+# CHECK: Vreg: %122[ 1 ]
+# CHECK: Vreg: %449[ 0 ]
+# CHECK: Vreg: %446[ 0 ]
+# CHECK: Instr: %451:vgpr_32 = V_ADD3_U32_e64 killed %450, killed %122, killed %128, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 0 ]
+# CHECK: Vreg: %450[ 0 ]
+# CHECK: Vreg: %30[ 9 ]
+# CHECK: Vreg: %440[ 1 ]
+# CHECK: Vreg: %442[ 8 ]
+# CHECK: Vreg: %122[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE_D16_HI %440, %451, 2, 0, implicit $exec :: (store (s8) into %ir.p4 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %440[ 0 ]
+# CHECK: Vreg: %442[ 7 ]
+# CHECK: Vreg: %451[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %440, %451, 0, 0, implicit $exec :: (store (s8) into %ir.p4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %30[ 7 ]
+# CHECK: Vreg: %440[ 0 ]
+# CHECK: Vreg: %442[ 6 ]
+# CHECK: Vreg: %451[ 0 ]
+# CHECK: Instr: %452:vgpr_32 = V_LSHRREV_B32_e64 24, %451, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %440[ 1 ]
+# CHECK: Vreg: %442[ 5 ]
+# CHECK: Vreg: %451[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %440, killed %452, 3, 0, implicit $exec :: (store (s8) into %ir.p4 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %452[ 0 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %440[ 0 ]
+# CHECK: Vreg: %442[ 4 ]
+# CHECK: Vreg: %451[ 1 ]
+# CHECK: Instr: %453:vgpr_32 = V_LSHRREV_B32_e64 8, %451, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %440[ 1 ]
+# CHECK: Vreg: %442[ 3 ]
+# CHECK: Vreg: %451[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE killed %440, killed %453, 1, 0, implicit $exec :: (store (s8) into %ir.p4 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %30[ 3 ]
+# CHECK: Vreg: %440[ 0 ]
+# CHECK: Vreg: %442[ 2 ]
+# CHECK: Vreg: %451[ 1 ]
+# CHECK: Vreg: %453[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.32
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %442[ 1 ]
+# CHECK: Vreg: %451[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %442[ 1 ]
+# CHECK: Vreg: %451[ 0 ]
+# CHECK: --- MBB_27 ---
+# CHECK: Instr: %454:vgpr_32 = PHI undef %455:vgpr_32, %bb.35, %456, %bb.30
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 14 ]
+# CHECK: Vreg: %462[ 1 ]
+# CHECK: Vreg: %443[ 5 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %132[ 10 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %122[ 14 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %456[ 0 ]
+# CHECK: Vreg: %124[ 11 ]
+# CHECK: Instr: %457:vreg_64 = PHI %20, %bb.35, undef %458:vreg_64, %bb.30
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 14 ]
+# CHECK: Vreg: %462[ 1 ]
+# CHECK: Vreg: %443[ 5 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %132[ 10 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %454[ 2 ]
+# CHECK: Vreg: %122[ 14 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %124[ 11 ]
+# CHECK: Instr: %459:vreg_64 = PHI %21, %bb.35, undef %460:vreg_64, %bb.30
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 14 ]
+# CHECK: Vreg: %462[ 1 ]
+# CHECK: Vreg: %443[ 5 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %457[ 3 ]
+# CHECK: Vreg: %132[ 10 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %454[ 2 ]
+# CHECK: Vreg: %122[ 14 ]
+# CHECK: Vreg: %124[ 11 ]
+# CHECK: Instr: %461:sreg_32 = SI_ELSE killed %462, %bb.31, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 13 ]
+# CHECK: Vreg: %462[ 0 ]
+# CHECK: Vreg: %443[ 4 ]
+# CHECK: Vreg: %457[ 2 ]
+# CHECK: Vreg: %132[ 9 ]
+# CHECK: Vreg: %30[ 7 ]
+# CHECK: Vreg: %459[ 12 ]
+# CHECK: Vreg: %454[ 1 ]
+# CHECK: Vreg: %122[ 13 ]
+# CHECK: Vreg: %124[ 10 ]
+# CHECK: Instr: S_BRANCH %bb.28
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 12 ]
+# CHECK: Vreg: %443[ 3 ]
+# CHECK: Vreg: %457[ 1 ]
+# CHECK: Vreg: %132[ 8 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %459[ 11 ]
+# CHECK: Vreg: %454[ 0 ]
+# CHECK: Vreg: %461[ 1 ]
+# CHECK: Vreg: %122[ 12 ]
+# CHECK: Vreg: %124[ 9 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %128[ 12 ]
+# CHECK: Vreg: %443[ 3 ]
+# CHECK: Vreg: %457[ 1 ]
+# CHECK: Vreg: %132[ 8 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %459[ 11 ]
+# CHECK: Vreg: %454[ 0 ]
+# CHECK: Vreg: %461[ 1 ]
+# CHECK: Vreg: %122[ 12 ]
+# CHECK: Vreg: %124[ 9 ]
+# CHECK: --- MBB_28 ---
+# CHECK: Instr: %463:vgpr_32 = GLOBAL_LOAD_UBYTE %457, 0, 0, implicit $exec :: (load (s8) from %ir.p4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 28 ]
+# CHECK: Vreg: %443[ 19 ]
+# CHECK: Vreg: %457[ 0 ]
+# CHECK: Vreg: %132[ 7 ]
+# CHECK: Vreg: %30[ 22 ]
+# CHECK: Vreg: %459[ 10 ]
+# CHECK: Vreg: %461[ 17 ]
+# CHECK: Vreg: %122[ 28 ]
+# CHECK: Vreg: %124[ 8 ]
+# CHECK: Instr: %464:vgpr_32 = GLOBAL_LOAD_UBYTE %457, 1, 0, implicit $exec :: (load (s8) from %ir.p4 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 27 ]
+# CHECK: Vreg: %443[ 18 ]
+# CHECK: Vreg: %457[ 0 ]
+# CHECK: Vreg: %132[ 6 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %459[ 9 ]
+# CHECK: Vreg: %461[ 16 ]
+# CHECK: Vreg: %122[ 27 ]
+# CHECK: Vreg: %463[ 1 ]
+# CHECK: Vreg: %124[ 7 ]
+# CHECK: Instr: %465:vgpr_32 = V_LSHL_OR_B32_e64 killed %464, 8, killed %463, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 26 ]
+# CHECK: Vreg: %443[ 17 ]
+# CHECK: Vreg: %457[ 1 ]
+# CHECK: Vreg: %464[ 0 ]
+# CHECK: Vreg: %132[ 5 ]
+# CHECK: Vreg: %30[ 20 ]
+# CHECK: Vreg: %459[ 8 ]
+# CHECK: Vreg: %461[ 15 ]
+# CHECK: Vreg: %122[ 26 ]
+# CHECK: Vreg: %463[ 0 ]
+# CHECK: Vreg: %124[ 6 ]
+# CHECK: Instr: %466:vgpr_32 = GLOBAL_LOAD_UBYTE %457, 2, 0, implicit $exec :: (load (s8) from %ir.p4 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 25 ]
+# CHECK: Vreg: %443[ 16 ]
+# CHECK: Vreg: %457[ 0 ]
+# CHECK: Vreg: %132[ 4 ]
+# CHECK: Vreg: %30[ 19 ]
+# CHECK: Vreg: %459[ 7 ]
+# CHECK: Vreg: %461[ 14 ]
+# CHECK: Vreg: %122[ 25 ]
+# CHECK: Vreg: %124[ 5 ]
+# CHECK: Vreg: %465[ 3 ]
+# CHECK: Instr: %467:vgpr_32 = GLOBAL_LOAD_UBYTE killed %457, 3, 0, implicit $exec :: (load (s8) from %ir.p4 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 24 ]
+# CHECK: Vreg: %443[ 15 ]
+# CHECK: Vreg: %457[ 0 ]
+# CHECK: Vreg: %132[ 3 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %459[ 6 ]
+# CHECK: Vreg: %466[ 1 ]
+# CHECK: Vreg: %461[ 13 ]
+# CHECK: Vreg: %122[ 24 ]
+# CHECK: Vreg: %124[ 4 ]
+# CHECK: Vreg: %465[ 2 ]
+# CHECK: Instr: %468:vgpr_32 = V_LSHL_OR_B32_e64 killed %467, 8, killed %466, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 23 ]
+# CHECK: Vreg: %443[ 14 ]
+# CHECK: Vreg: %132[ 2 ]
+# CHECK: Vreg: %30[ 17 ]
+# CHECK: Vreg: %459[ 5 ]
+# CHECK: Vreg: %466[ 0 ]
+# CHECK: Vreg: %461[ 12 ]
+# CHECK: Vreg: %122[ 23 ]
+# CHECK: Vreg: %124[ 3 ]
+# CHECK: Vreg: %465[ 1 ]
+# CHECK: Vreg: %467[ 0 ]
+# CHECK: Instr: %469:vgpr_32 = V_LSHL_OR_B32_e64 killed %468, 16, killed %465, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 22 ]
+# CHECK: Vreg: %443[ 13 ]
+# CHECK: Vreg: %132[ 1 ]
+# CHECK: Vreg: %30[ 16 ]
+# CHECK: Vreg: %459[ 4 ]
+# CHECK: Vreg: %461[ 11 ]
+# CHECK: Vreg: %122[ 22 ]
+# CHECK: Vreg: %468[ 0 ]
+# CHECK: Vreg: %124[ 2 ]
+# CHECK: Vreg: %465[ 0 ]
+# CHECK: Instr: %470:vreg_64 = REG_SEQUENCE killed %132, %subreg.sub0, undef %471:vgpr_32, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 21 ]
+# CHECK: Vreg: %443[ 12 ]
+# CHECK: Vreg: %469[ 1 ]
+# CHECK: Vreg: %132[ 0 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %459[ 3 ]
+# CHECK: Vreg: %461[ 10 ]
+# CHECK: Vreg: %122[ 21 ]
+# CHECK: Vreg: %124[ 1 ]
+# CHECK: Instr: %472:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 killed %469, killed %124, killed %470, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 20 ]
+# CHECK: Vreg: %443[ 11 ]
+# CHECK: Vreg: %469[ 0 ]
+# CHECK: Vreg: %30[ 14 ]
+# CHECK: Vreg: %459[ 2 ]
+# CHECK: Vreg: %461[ 9 ]
+# CHECK: Vreg: %122[ 20 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %470[ 0 ]
+# CHECK: Instr: %473:vgpr_32 = COPY %472.sub0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 19 ]
+# CHECK: Vreg: %443[ 10 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %459[ 1 ]
+# CHECK: Vreg: %461[ 8 ]
+# CHECK: Vreg: %122[ 19 ]
+# CHECK: Vreg: %472:sub0[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE_D16_HI %459, %472.sub0, 2, 0, implicit $exec :: (store (s8) into %ir.p3 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 18 ]
+# CHECK: Vreg: %443[ 9 ]
+# CHECK: Vreg: %30[ 12 ]
+# CHECK: Vreg: %459[ 0 ]
+# CHECK: Vreg: %473[ 6 ]
+# CHECK: Vreg: %461[ 7 ]
+# CHECK: Vreg: %122[ 18 ]
+# CHECK: Vreg: %472:sub0[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %459, %472.sub0, 0, 0, implicit $exec :: (store (s8) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 17 ]
+# CHECK: Vreg: %443[ 8 ]
+# CHECK: Vreg: %30[ 11 ]
+# CHECK: Vreg: %459[ 0 ]
+# CHECK: Vreg: %473[ 5 ]
+# CHECK: Vreg: %461[ 6 ]
+# CHECK: Vreg: %122[ 17 ]
+# CHECK: Vreg: %472:sub0[ 0 ]
+# CHECK: Instr: %474:vgpr_32 = V_LSHRREV_B32_e64 24, %472.sub0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 16 ]
+# CHECK: Vreg: %443[ 7 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %459[ 1 ]
+# CHECK: Vreg: %473[ 4 ]
+# CHECK: Vreg: %461[ 5 ]
+# CHECK: Vreg: %122[ 16 ]
+# CHECK: Vreg: %472:sub0[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %459, killed %474, 3, 0, implicit $exec :: (store (s8) into %ir.p3 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 15 ]
+# CHECK: Vreg: %474[ 0 ]
+# CHECK: Vreg: %443[ 6 ]
+# CHECK: Vreg: %30[ 9 ]
+# CHECK: Vreg: %459[ 0 ]
+# CHECK: Vreg: %473[ 3 ]
+# CHECK: Vreg: %461[ 4 ]
+# CHECK: Vreg: %122[ 15 ]
+# CHECK: Vreg: %472:sub0[ 1 ]
+# CHECK: Instr: %475:vgpr_32 = V_LSHRREV_B32_e64 8, killed %472.sub0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 14 ]
+# CHECK: Vreg: %443[ 5 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %459[ 1 ]
+# CHECK: Vreg: %473[ 2 ]
+# CHECK: Vreg: %461[ 3 ]
+# CHECK: Vreg: %122[ 14 ]
+# CHECK: Vreg: %472:sub0[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE killed %459, killed %475, 1, 0, implicit $exec :: (store (s8) into %ir.p3 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 13 ]
+# CHECK: Vreg: %443[ 4 ]
+# CHECK: Vreg: %30[ 7 ]
+# CHECK: Vreg: %459[ 0 ]
+# CHECK: Vreg: %473[ 1 ]
+# CHECK: Vreg: %461[ 2 ]
+# CHECK: Vreg: %122[ 13 ]
+# CHECK: Vreg: %475[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.31
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 12 ]
+# CHECK: Vreg: %443[ 3 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %473[ 0 ]
+# CHECK: Vreg: %461[ 1 ]
+# CHECK: Vreg: %122[ 12 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %128[ 12 ]
+# CHECK: Vreg: %443[ 3 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %473[ 0 ]
+# CHECK: Vreg: %461[ 1 ]
+# CHECK: Vreg: %122[ 12 ]
+# CHECK: --- MBB_29 ---
+# CHECK: Instr: %476:vgpr_32 = GLOBAL_LOAD_UBYTE %19, 0, 0, implicit $exec :: (load (s8) from %ir.p5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 30 ]
+# CHECK: Vreg: %462[ 17 ]
+# CHECK: Vreg: %443[ 21 ]
+# CHECK: Vreg: %130[ 8 ]
+# CHECK: Vreg: %132[ 26 ]
+# CHECK: Vreg: %30[ 24 ]
+# CHECK: Vreg: %122[ 30 ]
+# CHECK: Vreg: %487[ 15 ]
+# CHECK: Vreg: %124[ 27 ]
+# CHECK: Vreg: %22[ 9 ]
+# CHECK: Vreg: %126[ 7 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %477:vgpr_32 = GLOBAL_LOAD_UBYTE %19, 1, 0, implicit $exec :: (load (s8) from %ir.p5 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 29 ]
+# CHECK: Vreg: %462[ 16 ]
+# CHECK: Vreg: %443[ 20 ]
+# CHECK: Vreg: %130[ 7 ]
+# CHECK: Vreg: %476[ 1 ]
+# CHECK: Vreg: %132[ 25 ]
+# CHECK: Vreg: %30[ 23 ]
+# CHECK: Vreg: %122[ 29 ]
+# CHECK: Vreg: %487[ 14 ]
+# CHECK: Vreg: %124[ 26 ]
+# CHECK: Vreg: %22[ 8 ]
+# CHECK: Vreg: %126[ 6 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %478:vgpr_32 = V_LSHL_OR_B32_e64 killed %477, 8, killed %476, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 28 ]
+# CHECK: Vreg: %462[ 15 ]
+# CHECK: Vreg: %443[ 19 ]
+# CHECK: Vreg: %130[ 6 ]
+# CHECK: Vreg: %476[ 0 ]
+# CHECK: Vreg: %132[ 24 ]
+# CHECK: Vreg: %30[ 22 ]
+# CHECK: Vreg: %122[ 28 ]
+# CHECK: Vreg: %487[ 13 ]
+# CHECK: Vreg: %124[ 25 ]
+# CHECK: Vreg: %22[ 7 ]
+# CHECK: Vreg: %477[ 0 ]
+# CHECK: Vreg: %126[ 5 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: %479:vgpr_32 = GLOBAL_LOAD_UBYTE %19, 2, 0, implicit $exec :: (load (s8) from %ir.p5 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 27 ]
+# CHECK: Vreg: %462[ 14 ]
+# CHECK: Vreg: %443[ 18 ]
+# CHECK: Vreg: %130[ 5 ]
+# CHECK: Vreg: %132[ 23 ]
+# CHECK: Vreg: %30[ 21 ]
+# CHECK: Vreg: %478[ 3 ]
+# CHECK: Vreg: %122[ 27 ]
+# CHECK: Vreg: %487[ 12 ]
+# CHECK: Vreg: %124[ 24 ]
+# CHECK: Vreg: %22[ 6 ]
+# CHECK: Vreg: %126[ 4 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %480:vgpr_32 = GLOBAL_LOAD_UBYTE killed %19, 3, 0, implicit $exec :: (load (s8) from %ir.p5 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 26 ]
+# CHECK: Vreg: %462[ 13 ]
+# CHECK: Vreg: %443[ 17 ]
+# CHECK: Vreg: %130[ 4 ]
+# CHECK: Vreg: %132[ 22 ]
+# CHECK: Vreg: %30[ 20 ]
+# CHECK: Vreg: %478[ 2 ]
+# CHECK: Vreg: %122[ 26 ]
+# CHECK: Vreg: %487[ 11 ]
+# CHECK: Vreg: %124[ 23 ]
+# CHECK: Vreg: %22[ 5 ]
+# CHECK: Vreg: %126[ 3 ]
+# CHECK: Vreg: %479[ 1 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %481:vgpr_32 = V_LSHL_OR_B32_e64 killed %480, 8, killed %479, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 25 ]
+# CHECK: Vreg: %462[ 12 ]
+# CHECK: Vreg: %443[ 16 ]
+# CHECK: Vreg: %130[ 3 ]
+# CHECK: Vreg: %132[ 21 ]
+# CHECK: Vreg: %30[ 19 ]
+# CHECK: Vreg: %478[ 1 ]
+# CHECK: Vreg: %480[ 0 ]
+# CHECK: Vreg: %122[ 25 ]
+# CHECK: Vreg: %487[ 10 ]
+# CHECK: Vreg: %124[ 22 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: Vreg: %126[ 2 ]
+# CHECK: Vreg: %479[ 0 ]
+# CHECK: Instr: %482:vgpr_32 = V_LSHL_OR_B32_e64 killed %481, 16, killed %478, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 24 ]
+# CHECK: Vreg: %481[ 0 ]
+# CHECK: Vreg: %462[ 11 ]
+# CHECK: Vreg: %443[ 15 ]
+# CHECK: Vreg: %130[ 2 ]
+# CHECK: Vreg: %132[ 20 ]
+# CHECK: Vreg: %30[ 18 ]
+# CHECK: Vreg: %478[ 0 ]
+# CHECK: Vreg: %122[ 24 ]
+# CHECK: Vreg: %487[ 9 ]
+# CHECK: Vreg: %124[ 21 ]
+# CHECK: Vreg: %22[ 3 ]
+# CHECK: Vreg: %126[ 1 ]
+# CHECK: Instr: %483:vgpr_32 = V_SUB_U32_e64 killed %482, killed %126, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 23 ]
+# CHECK: Vreg: %462[ 10 ]
+# CHECK: Vreg: %443[ 14 ]
+# CHECK: Vreg: %130[ 1 ]
+# CHECK: Vreg: %132[ 19 ]
+# CHECK: Vreg: %30[ 17 ]
+# CHECK: Vreg: %122[ 23 ]
+# CHECK: Vreg: %487[ 8 ]
+# CHECK: Vreg: %482[ 0 ]
+# CHECK: Vreg: %124[ 20 ]
+# CHECK: Vreg: %22[ 2 ]
+# CHECK: Vreg: %126[ 0 ]
+# CHECK: Instr: %484:vgpr_32 = V_ADD_U32_e64 killed %483, killed %130, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 22 ]
+# CHECK: Vreg: %462[ 9 ]
+# CHECK: Vreg: %443[ 13 ]
+# CHECK: Vreg: %130[ 0 ]
+# CHECK: Vreg: %483[ 0 ]
+# CHECK: Vreg: %132[ 18 ]
+# CHECK: Vreg: %30[ 16 ]
+# CHECK: Vreg: %122[ 22 ]
+# CHECK: Vreg: %487[ 7 ]
+# CHECK: Vreg: %124[ 19 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE_D16_HI %22, %484, 2, 0, implicit $exec :: (store (s8) into %ir.p2 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 21 ]
+# CHECK: Vreg: %462[ 8 ]
+# CHECK: Vreg: %443[ 12 ]
+# CHECK: Vreg: %132[ 17 ]
+# CHECK: Vreg: %30[ 15 ]
+# CHECK: Vreg: %122[ 21 ]
+# CHECK: Vreg: %487[ 6 ]
+# CHECK: Vreg: %124[ 18 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %484[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %22, %484, 0, 0, implicit $exec :: (store (s8) into %ir.p2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 20 ]
+# CHECK: Vreg: %462[ 7 ]
+# CHECK: Vreg: %443[ 11 ]
+# CHECK: Vreg: %132[ 16 ]
+# CHECK: Vreg: %30[ 14 ]
+# CHECK: Vreg: %122[ 20 ]
+# CHECK: Vreg: %487[ 5 ]
+# CHECK: Vreg: %124[ 17 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %484[ 0 ]
+# CHECK: Instr: %485:vgpr_32 = V_LSHRREV_B32_e64 24, %484, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 19 ]
+# CHECK: Vreg: %462[ 6 ]
+# CHECK: Vreg: %443[ 10 ]
+# CHECK: Vreg: %132[ 15 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %122[ 19 ]
+# CHECK: Vreg: %487[ 4 ]
+# CHECK: Vreg: %124[ 16 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %484[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %22, killed %485, 3, 0, implicit $exec :: (store (s8) into %ir.p2 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 18 ]
+# CHECK: Vreg: %462[ 5 ]
+# CHECK: Vreg: %443[ 9 ]
+# CHECK: Vreg: %132[ 14 ]
+# CHECK: Vreg: %30[ 12 ]
+# CHECK: Vreg: %485[ 0 ]
+# CHECK: Vreg: %122[ 18 ]
+# CHECK: Vreg: %487[ 3 ]
+# CHECK: Vreg: %124[ 15 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %484[ 1 ]
+# CHECK: Instr: %486:vgpr_32 = V_LSHRREV_B32_e64 8, %484, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 17 ]
+# CHECK: Vreg: %462[ 4 ]
+# CHECK: Vreg: %443[ 8 ]
+# CHECK: Vreg: %132[ 13 ]
+# CHECK: Vreg: %30[ 11 ]
+# CHECK: Vreg: %122[ 17 ]
+# CHECK: Vreg: %487[ 2 ]
+# CHECK: Vreg: %124[ 14 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %484[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE killed %22, killed %486, 1, 0, implicit $exec :: (store (s8) into %ir.p2 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 16 ]
+# CHECK: Vreg: %462[ 3 ]
+# CHECK: Vreg: %443[ 7 ]
+# CHECK: Vreg: %132[ 12 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %122[ 16 ]
+# CHECK: Vreg: %487[ 1 ]
+# CHECK: Vreg: %124[ 13 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %484[ 0 ]
+# CHECK: Vreg: %486[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %128[ 16 ]
+# CHECK: Vreg: %462[ 3 ]
+# CHECK: Vreg: %443[ 7 ]
+# CHECK: Vreg: %132[ 12 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %122[ 16 ]
+# CHECK: Vreg: %487[ 1 ]
+# CHECK: Vreg: %124[ 13 ]
+# CHECK: Vreg: %484[ 0 ]
+# CHECK: --- MBB_30 ---
+# CHECK: Instr: %456:vgpr_32 = PHI %119, %bb.36, %484, %bb.29
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 16 ]
+# CHECK: Vreg: %462[ 3 ]
+# CHECK: Vreg: %443[ 7 ]
+# CHECK: Vreg: %132[ 12 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %122[ 16 ]
+# CHECK: Vreg: %487[ 1 ]
+# CHECK: Vreg: %124[ 13 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %484[ 0 ]
+# CHECK: Instr: SI_END_CF killed %487, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 15 ]
+# CHECK: Vreg: %462[ 2 ]
+# CHECK: Vreg: %443[ 6 ]
+# CHECK: Vreg: %132[ 11 ]
+# CHECK: Vreg: %30[ 9 ]
+# CHECK: Vreg: %122[ 15 ]
+# CHECK: Vreg: %487[ 0 ]
+# CHECK: Vreg: %456[ 1 ]
+# CHECK: Vreg: %124[ 12 ]
+# CHECK: Instr: S_BRANCH %bb.27
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 14 ]
+# CHECK: Vreg: %462[ 1 ]
+# CHECK: Vreg: %443[ 5 ]
+# CHECK: Vreg: %132[ 10 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %122[ 14 ]
+# CHECK: Vreg: %456[ 0 ]
+# CHECK: Vreg: %124[ 11 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %128[ 14 ]
+# CHECK: Vreg: %462[ 1 ]
+# CHECK: Vreg: %443[ 5 ]
+# CHECK: Vreg: %132[ 10 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %122[ 14 ]
+# CHECK: Vreg: %456[ 0 ]
+# CHECK: Vreg: %124[ 11 ]
+# CHECK: --- MBB_31 ---
+# CHECK: Instr: %437:vgpr_32 = PHI %454, %bb.27, %473, %bb.28
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 12 ]
+# CHECK: Vreg: %443[ 3 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %473[ 0 ]
+# CHECK: Vreg: %454[ 0 ]
+# CHECK: Vreg: %461[ 1 ]
+# CHECK: Vreg: %122[ 12 ]
+# CHECK: Instr: SI_END_CF killed %461, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 11 ]
+# CHECK: Vreg: %443[ 2 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %461[ 0 ]
+# CHECK: Vreg: %122[ 11 ]
+# CHECK: Vreg: %437[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.25
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 10 ]
+# CHECK: Vreg: %443[ 1 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %122[ 10 ]
+# CHECK: Vreg: %437[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %128[ 10 ]
+# CHECK: Vreg: %443[ 1 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %122[ 10 ]
+# CHECK: Vreg: %437[ 0 ]
+# CHECK: --- MBB_32 ---
+# CHECK: Instr: %488:vgpr_32 = PHI %435, %bb.25, %451, %bb.26
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %435[ 0 ]
+# CHECK: Vreg: %442[ 1 ]
+# CHECK: Vreg: %451[ 0 ]
+# CHECK: Instr: SI_END_CF killed %442, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %488[ 1 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %442[ 0 ]
+# CHECK: Instr: %489:vgpr_32 = V_ADD3_U32_e64 killed %30, killed %488, 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %488[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Instr: %490:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %489, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %489[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %490
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %490[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: --- MBB_33 ---
+# CHECK: Instr: %491:sreg_32 = PHI %318, %bb.17, %405, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %398[ 0 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %322[ 0 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %405[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %329[ 0 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %402[ 0 ]
+# CHECK: Vreg: %326[ 0 ]
+# CHECK: Vreg: %333[ 0 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Vreg: %320[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %400[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %324[ 0 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %331[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %318[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Instr: %492:sreg_32 = PHI %320, %bb.17, %402, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %398[ 0 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %322[ 0 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %329[ 0 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %402[ 0 ]
+# CHECK: Vreg: %326[ 0 ]
+# CHECK: Vreg: %333[ 0 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Vreg: %320[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %400[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %324[ 0 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %331[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Instr: %493:sreg_32 = PHI %322, %bb.17, %400, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %398[ 0 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %322[ 0 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %329[ 0 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %326[ 0 ]
+# CHECK: Vreg: %333[ 0 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %400[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %324[ 0 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %331[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Instr: %494:sreg_32 = PHI %324, %bb.17, %398, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %398[ 0 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %329[ 0 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %326[ 0 ]
+# CHECK: Vreg: %333[ 0 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %324[ 0 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %331[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Instr: %114:vgpr_32 = PHI %326, %bb.17, %112, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %329[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %331[ 0 ]
+# CHECK: Vreg: %326[ 0 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %333[ 0 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %115:vgpr_32 = PHI %329, %bb.17, %111, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %329[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %331[ 0 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %333[ 0 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %116:vgpr_32 = PHI %331, %bb.17, %65, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %331[ 0 ]
+# CHECK: Vreg: %115[ 14 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %333[ 0 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %117:vgpr_32 = PHI %333, %bb.17, %65, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %116[ 14 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %115[ 14 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %333[ 0 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %118:vgpr_32 = PHI %335, %bb.17, %395, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %116[ 14 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %115[ 14 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %117[ 14 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %335[ 0 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %121:vgpr_32 = PHI %337, %bb.17, %395, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %116[ 14 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %118[ 14 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %395[ 0 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %115[ 14 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %117[ 14 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %337[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %123:vgpr_32 = PHI %340, %bb.17, %65, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %116[ 14 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %118[ 14 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %115[ 14 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %117[ 14 ]
+# CHECK: Vreg: %340[ 0 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %121[ 14 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %125:vgpr_32 = PHI %342, %bb.17, %67, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %116[ 14 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %123[ 14 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %118[ 14 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %115[ 14 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %117[ 14 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %342[ 0 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %121[ 14 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %127:vgpr_32 = PHI %344, %bb.17, %69, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %116[ 14 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %123[ 14 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %118[ 14 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 14 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %115[ 14 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %117[ 14 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %121[ 14 ]
+# CHECK: Vreg: %344[ 0 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %129:vgpr_32 = PHI %346, %bb.17, %71, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %346[ 0 ]
+# CHECK: Vreg: %116[ 14 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %123[ 14 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %118[ 14 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 14 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %127[ 14 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %115[ 14 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %117[ 14 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %121[ 14 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %131:vgpr_32 = PHI %348, %bb.17, %73, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %116[ 14 ]
+# CHECK: Vreg: %123[ 14 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %348[ 0 ]
+# CHECK: Vreg: %118[ 14 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %125[ 14 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %127[ 14 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %115[ 14 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %129[ 14 ]
+# CHECK: Vreg: %117[ 14 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %121[ 14 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: %133:vgpr_32 = PHI %276, %bb.17, %112, %bb.20
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 85 ]
+# CHECK: Vreg: %493[ 6 ]
+# CHECK: Vreg: %90[ 2 ]
+# CHECK: Vreg: %116[ 14 ]
+# CHECK: Vreg: %123[ 14 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 83 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %92[ 5 ]
+# CHECK: Vreg: %118[ 14 ]
+# CHECK: Vreg: %125[ 14 ]
+# CHECK: Vreg: %23[ 41 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %30[ 65 ]
+# CHECK: Vreg: %94[ 8 ]
+# CHECK: Vreg: %37[ 23 ]
+# CHECK: Vreg: %18[ 101 ]
+# CHECK: Vreg: %127[ 14 ]
+# CHECK: Vreg: %492[ 9 ]
+# CHECK: Vreg: %115[ 14 ]
+# CHECK: Vreg: %96[ 15 ]
+# CHECK: Vreg: %58[ 16 ]
+# CHECK: Vreg: %20[ 79 ]
+# CHECK: Vreg: %1[ 120 ]
+# CHECK: Vreg: %494[ 3 ]
+# CHECK: Vreg: %276[ 0 ]
+# CHECK: Vreg: %129[ 14 ]
+# CHECK: Vreg: %117[ 14 ]
+# CHECK: Vreg: %350[ 1 ]
+# CHECK: Vreg: %22:sub0[ 31 ]
+# CHECK: Vreg: %22:sub1[ 32 ]
+# CHECK: Vreg: %22[ 96 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %131[ 14 ]
+# CHECK: Vreg: %43[ 17 ]
+# CHECK: Vreg: %491[ 12 ]
+# CHECK: Vreg: %5[ 89 ]
+# CHECK: Vreg: %114[ 14 ]
+# CHECK: Vreg: %95[ 11 ]
+# CHECK: Vreg: %121[ 14 ]
+# CHECK: Vreg: %19:sub0[ 55 ]
+# CHECK: Vreg: %19:sub1[ 56 ]
+# CHECK: Vreg: %19[ 68 ]
+# CHECK: Instr: SI_END_CF killed %350, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 84 ]
+# CHECK: Vreg: %493[ 5 ]
+# CHECK: Vreg: %90[ 1 ]
+# CHECK: Vreg: %116[ 13 ]
+# CHECK: Vreg: %123[ 13 ]
+# CHECK: Vreg: %40[ 19 ]
+# CHECK: Vreg: %21[ 82 ]
+# CHECK: Vreg: %2[ 103 ]
+# CHECK: Vreg: %111[ 13 ]
+# CHECK: Vreg: %92[ 4 ]
+# CHECK: Vreg: %118[ 13 ]
+# CHECK: Vreg: %125[ 13 ]
+# CHECK: Vreg: %23[ 40 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %30[ 64 ]
+# CHECK: Vreg: %94[ 7 ]
+# CHECK: Vreg: %37[ 22 ]
+# CHECK: Vreg: %18[ 100 ]
+# CHECK: Vreg: %127[ 13 ]
+# CHECK: Vreg: %492[ 8 ]
+# CHECK: Vreg: %115[ 13 ]
+# CHECK: Vreg: %96[ 14 ]
+# CHECK: Vreg: %58[ 15 ]
+# CHECK: Vreg: %20[ 78 ]
+# CHECK: Vreg: %1[ 119 ]
+# CHECK: Vreg: %494[ 2 ]
+# CHECK: Vreg: %129[ 13 ]
+# CHECK: Vreg: %117[ 13 ]
+# CHECK: Vreg: %350[ 0 ]
+# CHECK: Vreg: %22:sub0[ 30 ]
+# CHECK: Vreg: %22:sub1[ 31 ]
+# CHECK: Vreg: %22[ 95 ]
+# CHECK: Vreg: %3[ 89 ]
+# CHECK: Vreg: %112[ 13 ]
+# CHECK: Vreg: %131[ 13 ]
+# CHECK: Vreg: %43[ 16 ]
+# CHECK: Vreg: %491[ 11 ]
+# CHECK: Vreg: %5[ 88 ]
+# CHECK: Vreg: %133[ 13 ]
+# CHECK: Vreg: %114[ 13 ]
+# CHECK: Vreg: %95[ 10 ]
+# CHECK: Vreg: %121[ 13 ]
+# CHECK: Vreg: %19:sub0[ 54 ]
+# CHECK: Vreg: %19:sub1[ 55 ]
+# CHECK: Vreg: %19[ 67 ]
+# CHECK: Instr: %495:sreg_32 = S_ANDN2_B32 killed %90, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 83 ]
+# CHECK: Vreg: %493[ 4 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %116[ 12 ]
+# CHECK: Vreg: %123[ 12 ]
+# CHECK: Vreg: %40[ 18 ]
+# CHECK: Vreg: %21[ 81 ]
+# CHECK: Vreg: %2[ 102 ]
+# CHECK: Vreg: %111[ 12 ]
+# CHECK: Vreg: %92[ 3 ]
+# CHECK: Vreg: %118[ 12 ]
+# CHECK: Vreg: %125[ 12 ]
+# CHECK: Vreg: %23[ 39 ]
+# CHECK: Vreg: %4[ 89 ]
+# CHECK: Vreg: %30[ 63 ]
+# CHECK: Vreg: %94[ 6 ]
+# CHECK: Vreg: %37[ 21 ]
+# CHECK: Vreg: %18[ 99 ]
+# CHECK: Vreg: %127[ 12 ]
+# CHECK: Vreg: %492[ 7 ]
+# CHECK: Vreg: %115[ 12 ]
+# CHECK: Vreg: %96[ 13 ]
+# CHECK: Vreg: %58[ 14 ]
+# CHECK: Vreg: %20[ 77 ]
+# CHECK: Vreg: %1[ 118 ]
+# CHECK: Vreg: %494[ 1 ]
+# CHECK: Vreg: %129[ 12 ]
+# CHECK: Vreg: %117[ 12 ]
+# CHECK: Vreg: %22:sub0[ 29 ]
+# CHECK: Vreg: %22:sub1[ 30 ]
+# CHECK: Vreg: %22[ 94 ]
+# CHECK: Vreg: %3[ 88 ]
+# CHECK: Vreg: %112[ 12 ]
+# CHECK: Vreg: %131[ 12 ]
+# CHECK: Vreg: %43[ 15 ]
+# CHECK: Vreg: %491[ 10 ]
+# CHECK: Vreg: %5[ 87 ]
+# CHECK: Vreg: %133[ 12 ]
+# CHECK: Vreg: %114[ 12 ]
+# CHECK: Vreg: %95[ 9 ]
+# CHECK: Vreg: %121[ 12 ]
+# CHECK: Vreg: %19:sub0[ 53 ]
+# CHECK: Vreg: %19:sub1[ 54 ]
+# CHECK: Vreg: %19[ 66 ]
+# CHECK: Instr: %496:sreg_32 = S_AND_B32 killed %494, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 82 ]
+# CHECK: Vreg: %493[ 3 ]
+# CHECK: Vreg: %116[ 11 ]
+# CHECK: Vreg: %123[ 11 ]
+# CHECK: Vreg: %40[ 17 ]
+# CHECK: Vreg: %21[ 80 ]
+# CHECK: Vreg: %2[ 101 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %92[ 2 ]
+# CHECK: Vreg: %118[ 11 ]
+# CHECK: Vreg: %125[ 11 ]
+# CHECK: Vreg: %23[ 38 ]
+# CHECK: Vreg: %4[ 88 ]
+# CHECK: Vreg: %495[ 1 ]
+# CHECK: Vreg: %30[ 62 ]
+# CHECK: Vreg: %94[ 5 ]
+# CHECK: Vreg: %37[ 20 ]
+# CHECK: Vreg: %18[ 98 ]
+# CHECK: Vreg: %127[ 11 ]
+# CHECK: Vreg: %492[ 6 ]
+# CHECK: Vreg: %115[ 11 ]
+# CHECK: Vreg: %96[ 12 ]
+# CHECK: Vreg: %58[ 13 ]
+# CHECK: Vreg: %20[ 76 ]
+# CHECK: Vreg: %1[ 117 ]
+# CHECK: Vreg: %494[ 0 ]
+# CHECK: Vreg: %129[ 11 ]
+# CHECK: Vreg: %117[ 11 ]
+# CHECK: Vreg: %22:sub0[ 28 ]
+# CHECK: Vreg: %22:sub1[ 29 ]
+# CHECK: Vreg: %22[ 93 ]
+# CHECK: Vreg: %3[ 87 ]
+# CHECK: Vreg: %112[ 11 ]
+# CHECK: Vreg: %131[ 11 ]
+# CHECK: Vreg: %43[ 14 ]
+# CHECK: Vreg: %491[ 9 ]
+# CHECK: Vreg: %5[ 86 ]
+# CHECK: Vreg: %133[ 11 ]
+# CHECK: Vreg: %114[ 11 ]
+# CHECK: Vreg: %95[ 8 ]
+# CHECK: Vreg: %121[ 11 ]
+# CHECK: Vreg: %19:sub0[ 52 ]
+# CHECK: Vreg: %19:sub1[ 53 ]
+# CHECK: Vreg: %19[ 65 ]
+# CHECK: Instr: %110:sreg_32 = S_OR_B32 killed %495, killed %496, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 81 ]
+# CHECK: Vreg: %493[ 2 ]
+# CHECK: Vreg: %116[ 10 ]
+# CHECK: Vreg: %123[ 10 ]
+# CHECK: Vreg: %40[ 16 ]
+# CHECK: Vreg: %21[ 79 ]
+# CHECK: Vreg: %2[ 100 ]
+# CHECK: Vreg: %111[ 10 ]
+# CHECK: Vreg: %92[ 1 ]
+# CHECK: Vreg: %118[ 10 ]
+# CHECK: Vreg: %125[ 10 ]
+# CHECK: Vreg: %23[ 37 ]
+# CHECK: Vreg: %4[ 87 ]
+# CHECK: Vreg: %495[ 0 ]
+# CHECK: Vreg: %30[ 61 ]
+# CHECK: Vreg: %94[ 4 ]
+# CHECK: Vreg: %37[ 19 ]
+# CHECK: Vreg: %18[ 97 ]
+# CHECK: Vreg: %127[ 10 ]
+# CHECK: Vreg: %492[ 5 ]
+# CHECK: Vreg: %115[ 10 ]
+# CHECK: Vreg: %96[ 11 ]
+# CHECK: Vreg: %58[ 12 ]
+# CHECK: Vreg: %20[ 75 ]
+# CHECK: Vreg: %1[ 116 ]
+# CHECK: Vreg: %129[ 10 ]
+# CHECK: Vreg: %117[ 10 ]
+# CHECK: Vreg: %22:sub0[ 27 ]
+# CHECK: Vreg: %22:sub1[ 28 ]
+# CHECK: Vreg: %22[ 92 ]
+# CHECK: Vreg: %3[ 86 ]
+# CHECK: Vreg: %112[ 10 ]
+# CHECK: Vreg: %496[ 0 ]
+# CHECK: Vreg: %131[ 10 ]
+# CHECK: Vreg: %43[ 13 ]
+# CHECK: Vreg: %491[ 8 ]
+# CHECK: Vreg: %5[ 85 ]
+# CHECK: Vreg: %133[ 10 ]
+# CHECK: Vreg: %114[ 10 ]
+# CHECK: Vreg: %95[ 7 ]
+# CHECK: Vreg: %121[ 10 ]
+# CHECK: Vreg: %19:sub0[ 51 ]
+# CHECK: Vreg: %19:sub1[ 52 ]
+# CHECK: Vreg: %19[ 64 ]
+# CHECK: Instr: %497:sreg_32 = S_ANDN2_B32 killed %92, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 80 ]
+# CHECK: Vreg: %493[ 1 ]
+# CHECK: Vreg: %116[ 9 ]
+# CHECK: Vreg: %123[ 9 ]
+# CHECK: Vreg: %40[ 15 ]
+# CHECK: Vreg: %21[ 78 ]
+# CHECK: Vreg: %2[ 99 ]
+# CHECK: Vreg: %111[ 9 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %118[ 9 ]
+# CHECK: Vreg: %125[ 9 ]
+# CHECK: Vreg: %23[ 36 ]
+# CHECK: Vreg: %4[ 86 ]
+# CHECK: Vreg: %30[ 60 ]
+# CHECK: Vreg: %94[ 3 ]
+# CHECK: Vreg: %37[ 18 ]
+# CHECK: Vreg: %18[ 96 ]
+# CHECK: Vreg: %127[ 9 ]
+# CHECK: Vreg: %492[ 4 ]
+# CHECK: Vreg: %115[ 9 ]
+# CHECK: Vreg: %96[ 10 ]
+# CHECK: Vreg: %58[ 11 ]
+# CHECK: Vreg: %20[ 74 ]
+# CHECK: Vreg: %1[ 115 ]
+# CHECK: Vreg: %110[ 9 ]
+# CHECK: Vreg: %129[ 9 ]
+# CHECK: Vreg: %117[ 9 ]
+# CHECK: Vreg: %22:sub0[ 26 ]
+# CHECK: Vreg: %22:sub1[ 27 ]
+# CHECK: Vreg: %22[ 91 ]
+# CHECK: Vreg: %3[ 85 ]
+# CHECK: Vreg: %112[ 9 ]
+# CHECK: Vreg: %131[ 9 ]
+# CHECK: Vreg: %43[ 12 ]
+# CHECK: Vreg: %491[ 7 ]
+# CHECK: Vreg: %5[ 84 ]
+# CHECK: Vreg: %133[ 9 ]
+# CHECK: Vreg: %114[ 9 ]
+# CHECK: Vreg: %95[ 6 ]
+# CHECK: Vreg: %121[ 9 ]
+# CHECK: Vreg: %19:sub0[ 50 ]
+# CHECK: Vreg: %19:sub1[ 51 ]
+# CHECK: Vreg: %19[ 63 ]
+# CHECK: Instr: %498:sreg_32 = S_AND_B32 killed %493, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 79 ]
+# CHECK: Vreg: %493[ 0 ]
+# CHECK: Vreg: %116[ 8 ]
+# CHECK: Vreg: %123[ 8 ]
+# CHECK: Vreg: %40[ 14 ]
+# CHECK: Vreg: %21[ 77 ]
+# CHECK: Vreg: %2[ 98 ]
+# CHECK: Vreg: %111[ 8 ]
+# CHECK: Vreg: %118[ 8 ]
+# CHECK: Vreg: %125[ 8 ]
+# CHECK: Vreg: %23[ 35 ]
+# CHECK: Vreg: %4[ 85 ]
+# CHECK: Vreg: %497[ 1 ]
+# CHECK: Vreg: %30[ 59 ]
+# CHECK: Vreg: %94[ 2 ]
+# CHECK: Vreg: %37[ 17 ]
+# CHECK: Vreg: %18[ 95 ]
+# CHECK: Vreg: %127[ 8 ]
+# CHECK: Vreg: %492[ 3 ]
+# CHECK: Vreg: %115[ 8 ]
+# CHECK: Vreg: %96[ 9 ]
+# CHECK: Vreg: %58[ 10 ]
+# CHECK: Vreg: %20[ 73 ]
+# CHECK: Vreg: %1[ 114 ]
+# CHECK: Vreg: %110[ 8 ]
+# CHECK: Vreg: %129[ 8 ]
+# CHECK: Vreg: %117[ 8 ]
+# CHECK: Vreg: %22:sub0[ 25 ]
+# CHECK: Vreg: %22:sub1[ 26 ]
+# CHECK: Vreg: %22[ 90 ]
+# CHECK: Vreg: %3[ 84 ]
+# CHECK: Vreg: %112[ 8 ]
+# CHECK: Vreg: %131[ 8 ]
+# CHECK: Vreg: %43[ 11 ]
+# CHECK: Vreg: %491[ 6 ]
+# CHECK: Vreg: %5[ 83 ]
+# CHECK: Vreg: %133[ 8 ]
+# CHECK: Vreg: %114[ 8 ]
+# CHECK: Vreg: %95[ 5 ]
+# CHECK: Vreg: %121[ 8 ]
+# CHECK: Vreg: %19:sub0[ 49 ]
+# CHECK: Vreg: %19:sub1[ 50 ]
+# CHECK: Vreg: %19[ 62 ]
+# CHECK: Instr: %109:sreg_32 = S_OR_B32 killed %497, killed %498, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 78 ]
+# CHECK: Vreg: %116[ 7 ]
+# CHECK: Vreg: %123[ 7 ]
+# CHECK: Vreg: %40[ 13 ]
+# CHECK: Vreg: %21[ 76 ]
+# CHECK: Vreg: %2[ 97 ]
+# CHECK: Vreg: %111[ 7 ]
+# CHECK: Vreg: %118[ 7 ]
+# CHECK: Vreg: %498[ 0 ]
+# CHECK: Vreg: %125[ 7 ]
+# CHECK: Vreg: %23[ 34 ]
+# CHECK: Vreg: %4[ 84 ]
+# CHECK: Vreg: %497[ 0 ]
+# CHECK: Vreg: %30[ 58 ]
+# CHECK: Vreg: %94[ 1 ]
+# CHECK: Vreg: %37[ 16 ]
+# CHECK: Vreg: %18[ 94 ]
+# CHECK: Vreg: %127[ 7 ]
+# CHECK: Vreg: %492[ 2 ]
+# CHECK: Vreg: %115[ 7 ]
+# CHECK: Vreg: %96[ 8 ]
+# CHECK: Vreg: %58[ 9 ]
+# CHECK: Vreg: %20[ 72 ]
+# CHECK: Vreg: %1[ 113 ]
+# CHECK: Vreg: %110[ 7 ]
+# CHECK: Vreg: %129[ 7 ]
+# CHECK: Vreg: %117[ 7 ]
+# CHECK: Vreg: %22:sub0[ 24 ]
+# CHECK: Vreg: %22:sub1[ 25 ]
+# CHECK: Vreg: %22[ 89 ]
+# CHECK: Vreg: %3[ 83 ]
+# CHECK: Vreg: %112[ 7 ]
+# CHECK: Vreg: %131[ 7 ]
+# CHECK: Vreg: %43[ 10 ]
+# CHECK: Vreg: %491[ 5 ]
+# CHECK: Vreg: %5[ 82 ]
+# CHECK: Vreg: %133[ 7 ]
+# CHECK: Vreg: %114[ 7 ]
+# CHECK: Vreg: %95[ 4 ]
+# CHECK: Vreg: %121[ 7 ]
+# CHECK: Vreg: %19:sub0[ 48 ]
+# CHECK: Vreg: %19:sub1[ 49 ]
+# CHECK: Vreg: %19[ 61 ]
+# CHECK: Instr: %499:sreg_32 = S_ANDN2_B32 killed %94, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 77 ]
+# CHECK: Vreg: %109[ 6 ]
+# CHECK: Vreg: %116[ 6 ]
+# CHECK: Vreg: %123[ 6 ]
+# CHECK: Vreg: %40[ 12 ]
+# CHECK: Vreg: %21[ 75 ]
+# CHECK: Vreg: %2[ 96 ]
+# CHECK: Vreg: %111[ 6 ]
+# CHECK: Vreg: %118[ 6 ]
+# CHECK: Vreg: %125[ 6 ]
+# CHECK: Vreg: %23[ 33 ]
+# CHECK: Vreg: %4[ 83 ]
+# CHECK: Vreg: %30[ 57 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %37[ 15 ]
+# CHECK: Vreg: %18[ 93 ]
+# CHECK: Vreg: %127[ 6 ]
+# CHECK: Vreg: %492[ 1 ]
+# CHECK: Vreg: %115[ 6 ]
+# CHECK: Vreg: %96[ 7 ]
+# CHECK: Vreg: %58[ 8 ]
+# CHECK: Vreg: %20[ 71 ]
+# CHECK: Vreg: %1[ 112 ]
+# CHECK: Vreg: %110[ 6 ]
+# CHECK: Vreg: %129[ 6 ]
+# CHECK: Vreg: %117[ 6 ]
+# CHECK: Vreg: %22:sub0[ 23 ]
+# CHECK: Vreg: %22:sub1[ 24 ]
+# CHECK: Vreg: %22[ 88 ]
+# CHECK: Vreg: %3[ 82 ]
+# CHECK: Vreg: %112[ 6 ]
+# CHECK: Vreg: %131[ 6 ]
+# CHECK: Vreg: %43[ 9 ]
+# CHECK: Vreg: %491[ 4 ]
+# CHECK: Vreg: %5[ 81 ]
+# CHECK: Vreg: %133[ 6 ]
+# CHECK: Vreg: %114[ 6 ]
+# CHECK: Vreg: %95[ 3 ]
+# CHECK: Vreg: %121[ 6 ]
+# CHECK: Vreg: %19:sub0[ 47 ]
+# CHECK: Vreg: %19:sub1[ 48 ]
+# CHECK: Vreg: %19[ 60 ]
+# CHECK: Instr: %500:sreg_32 = S_AND_B32 killed %492, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 76 ]
+# CHECK: Vreg: %109[ 5 ]
+# CHECK: Vreg: %116[ 5 ]
+# CHECK: Vreg: %123[ 5 ]
+# CHECK: Vreg: %40[ 11 ]
+# CHECK: Vreg: %21[ 74 ]
+# CHECK: Vreg: %2[ 95 ]
+# CHECK: Vreg: %111[ 5 ]
+# CHECK: Vreg: %118[ 5 ]
+# CHECK: Vreg: %125[ 5 ]
+# CHECK: Vreg: %23[ 32 ]
+# CHECK: Vreg: %4[ 82 ]
+# CHECK: Vreg: %30[ 56 ]
+# CHECK: Vreg: %37[ 14 ]
+# CHECK: Vreg: %18[ 92 ]
+# CHECK: Vreg: %127[ 5 ]
+# CHECK: Vreg: %492[ 0 ]
+# CHECK: Vreg: %115[ 5 ]
+# CHECK: Vreg: %96[ 6 ]
+# CHECK: Vreg: %58[ 7 ]
+# CHECK: Vreg: %20[ 70 ]
+# CHECK: Vreg: %1[ 111 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %129[ 5 ]
+# CHECK: Vreg: %117[ 5 ]
+# CHECK: Vreg: %22:sub0[ 22 ]
+# CHECK: Vreg: %22:sub1[ 23 ]
+# CHECK: Vreg: %22[ 87 ]
+# CHECK: Vreg: %3[ 81 ]
+# CHECK: Vreg: %112[ 5 ]
+# CHECK: Vreg: %131[ 5 ]
+# CHECK: Vreg: %499[ 1 ]
+# CHECK: Vreg: %43[ 8 ]
+# CHECK: Vreg: %491[ 3 ]
+# CHECK: Vreg: %5[ 80 ]
+# CHECK: Vreg: %133[ 5 ]
+# CHECK: Vreg: %114[ 5 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: Vreg: %121[ 5 ]
+# CHECK: Vreg: %19:sub0[ 46 ]
+# CHECK: Vreg: %19:sub1[ 47 ]
+# CHECK: Vreg: %19[ 59 ]
+# CHECK: Instr: %108:sreg_32 = S_OR_B32 killed %499, killed %500, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 75 ]
+# CHECK: Vreg: %109[ 4 ]
+# CHECK: Vreg: %116[ 4 ]
+# CHECK: Vreg: %500[ 0 ]
+# CHECK: Vreg: %123[ 4 ]
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %21[ 73 ]
+# CHECK: Vreg: %2[ 94 ]
+# CHECK: Vreg: %111[ 4 ]
+# CHECK: Vreg: %118[ 4 ]
+# CHECK: Vreg: %125[ 4 ]
+# CHECK: Vreg: %23[ 31 ]
+# CHECK: Vreg: %4[ 81 ]
+# CHECK: Vreg: %30[ 55 ]
+# CHECK: Vreg: %37[ 13 ]
+# CHECK: Vreg: %18[ 91 ]
+# CHECK: Vreg: %127[ 4 ]
+# CHECK: Vreg: %115[ 4 ]
+# CHECK: Vreg: %96[ 5 ]
+# CHECK: Vreg: %58[ 6 ]
+# CHECK: Vreg: %20[ 69 ]
+# CHECK: Vreg: %1[ 110 ]
+# CHECK: Vreg: %110[ 4 ]
+# CHECK: Vreg: %129[ 4 ]
+# CHECK: Vreg: %117[ 4 ]
+# CHECK: Vreg: %22:sub0[ 21 ]
+# CHECK: Vreg: %22:sub1[ 22 ]
+# CHECK: Vreg: %22[ 86 ]
+# CHECK: Vreg: %3[ 80 ]
+# CHECK: Vreg: %112[ 4 ]
+# CHECK: Vreg: %131[ 4 ]
+# CHECK: Vreg: %499[ 0 ]
+# CHECK: Vreg: %43[ 7 ]
+# CHECK: Vreg: %491[ 2 ]
+# CHECK: Vreg: %5[ 79 ]
+# CHECK: Vreg: %133[ 4 ]
+# CHECK: Vreg: %114[ 4 ]
+# CHECK: Vreg: %95[ 1 ]
+# CHECK: Vreg: %121[ 4 ]
+# CHECK: Vreg: %19:sub0[ 45 ]
+# CHECK: Vreg: %19:sub1[ 46 ]
+# CHECK: Vreg: %19[ 58 ]
+# CHECK: Instr: %501:sreg_32 = S_ANDN2_B32 killed %95, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 74 ]
+# CHECK: Vreg: %109[ 3 ]
+# CHECK: Vreg: %116[ 3 ]
+# CHECK: Vreg: %123[ 3 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 72 ]
+# CHECK: Vreg: %2[ 93 ]
+# CHECK: Vreg: %111[ 3 ]
+# CHECK: Vreg: %118[ 3 ]
+# CHECK: Vreg: %125[ 3 ]
+# CHECK: Vreg: %23[ 30 ]
+# CHECK: Vreg: %4[ 80 ]
+# CHECK: Vreg: %30[ 54 ]
+# CHECK: Vreg: %37[ 12 ]
+# CHECK: Vreg: %18[ 90 ]
+# CHECK: Vreg: %127[ 3 ]
+# CHECK: Vreg: %108[ 3 ]
+# CHECK: Vreg: %115[ 3 ]
+# CHECK: Vreg: %96[ 4 ]
+# CHECK: Vreg: %58[ 5 ]
+# CHECK: Vreg: %20[ 68 ]
+# CHECK: Vreg: %1[ 109 ]
+# CHECK: Vreg: %110[ 3 ]
+# CHECK: Vreg: %129[ 3 ]
+# CHECK: Vreg: %117[ 3 ]
+# CHECK: Vreg: %22:sub0[ 20 ]
+# CHECK: Vreg: %22:sub1[ 21 ]
+# CHECK: Vreg: %22[ 85 ]
+# CHECK: Vreg: %3[ 79 ]
+# CHECK: Vreg: %112[ 3 ]
+# CHECK: Vreg: %131[ 3 ]
+# CHECK: Vreg: %43[ 6 ]
+# CHECK: Vreg: %491[ 1 ]
+# CHECK: Vreg: %5[ 78 ]
+# CHECK: Vreg: %133[ 3 ]
+# CHECK: Vreg: %114[ 3 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %121[ 3 ]
+# CHECK: Vreg: %19:sub0[ 44 ]
+# CHECK: Vreg: %19:sub1[ 45 ]
+# CHECK: Vreg: %19[ 57 ]
+# CHECK: Instr: %502:sreg_32 = S_AND_B32 killed %491, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 73 ]
+# CHECK: Vreg: %109[ 2 ]
+# CHECK: Vreg: %116[ 2 ]
+# CHECK: Vreg: %123[ 2 ]
+# CHECK: Vreg: %40[ 8 ]
+# CHECK: Vreg: %21[ 71 ]
+# CHECK: Vreg: %2[ 92 ]
+# CHECK: Vreg: %111[ 2 ]
+# CHECK: Vreg: %118[ 2 ]
+# CHECK: Vreg: %125[ 2 ]
+# CHECK: Vreg: %23[ 29 ]
+# CHECK: Vreg: %4[ 79 ]
+# CHECK: Vreg: %30[ 53 ]
+# CHECK: Vreg: %37[ 11 ]
+# CHECK: Vreg: %18[ 89 ]
+# CHECK: Vreg: %127[ 2 ]
+# CHECK: Vreg: %108[ 2 ]
+# CHECK: Vreg: %115[ 2 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %58[ 4 ]
+# CHECK: Vreg: %20[ 67 ]
+# CHECK: Vreg: %1[ 108 ]
+# CHECK: Vreg: %110[ 2 ]
+# CHECK: Vreg: %129[ 2 ]
+# CHECK: Vreg: %117[ 2 ]
+# CHECK: Vreg: %501[ 1 ]
+# CHECK: Vreg: %22:sub0[ 19 ]
+# CHECK: Vreg: %22:sub1[ 20 ]
+# CHECK: Vreg: %22[ 84 ]
+# CHECK: Vreg: %3[ 78 ]
+# CHECK: Vreg: %112[ 2 ]
+# CHECK: Vreg: %131[ 2 ]
+# CHECK: Vreg: %43[ 5 ]
+# CHECK: Vreg: %491[ 0 ]
+# CHECK: Vreg: %5[ 77 ]
+# CHECK: Vreg: %133[ 2 ]
+# CHECK: Vreg: %114[ 2 ]
+# CHECK: Vreg: %121[ 2 ]
+# CHECK: Vreg: %19:sub0[ 43 ]
+# CHECK: Vreg: %19:sub1[ 44 ]
+# CHECK: Vreg: %19[ 56 ]
+# CHECK: Instr: %107:sreg_32 = S_OR_B32 killed %501, killed %502, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 72 ]
+# CHECK: Vreg: %109[ 1 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %123[ 1 ]
+# CHECK: Vreg: %40[ 7 ]
+# CHECK: Vreg: %21[ 70 ]
+# CHECK: Vreg: %2[ 91 ]
+# CHECK: Vreg: %111[ 1 ]
+# CHECK: Vreg: %118[ 1 ]
+# CHECK: Vreg: %502[ 0 ]
+# CHECK: Vreg: %125[ 1 ]
+# CHECK: Vreg: %23[ 28 ]
+# CHECK: Vreg: %4[ 78 ]
+# CHECK: Vreg: %30[ 52 ]
+# CHECK: Vreg: %37[ 10 ]
+# CHECK: Vreg: %18[ 88 ]
+# CHECK: Vreg: %127[ 1 ]
+# CHECK: Vreg: %108[ 1 ]
+# CHECK: Vreg: %115[ 1 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %58[ 3 ]
+# CHECK: Vreg: %20[ 66 ]
+# CHECK: Vreg: %1[ 107 ]
+# CHECK: Vreg: %110[ 1 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %117[ 1 ]
+# CHECK: Vreg: %501[ 0 ]
+# CHECK: Vreg: %22:sub0[ 18 ]
+# CHECK: Vreg: %22:sub1[ 19 ]
+# CHECK: Vreg: %22[ 83 ]
+# CHECK: Vreg: %3[ 77 ]
+# CHECK: Vreg: %112[ 1 ]
+# CHECK: Vreg: %131[ 1 ]
+# CHECK: Vreg: %43[ 4 ]
+# CHECK: Vreg: %5[ 76 ]
+# CHECK: Vreg: %133[ 1 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Vreg: %121[ 1 ]
+# CHECK: Vreg: %19:sub0[ 42 ]
+# CHECK: Vreg: %19:sub1[ 43 ]
+# CHECK: Vreg: %19[ 55 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 71 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ 90 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %23[ 27 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %30[ 51 ]
+# CHECK: Vreg: %37[ 9 ]
+# CHECK: Vreg: %18[ 87 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %58[ 2 ]
+# CHECK: Vreg: %20[ 65 ]
+# CHECK: Vreg: %1[ 106 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %22:sub0[ 17 ]
+# CHECK: Vreg: %22:sub1[ 18 ]
+# CHECK: Vreg: %22[ 82 ]
+# CHECK: Vreg: %3[ 76 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %5[ 75 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %19:sub0[ 41 ]
+# CHECK: Vreg: %19:sub1[ 42 ]
+# CHECK: Vreg: %19[ 54 ]
+# CHECK: --- MBB_34 ---
+# CHECK: Instr: SI_END_CF killed %59, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 14 ]
+# CHECK: Vreg: %45[ 7 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %130[ 17 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %132[ 16 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %122[ 14 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %20[ 4 ]
+# CHECK: Vreg: %124[ 17 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %119[ 8 ]
+# CHECK: Vreg: %126[ 16 ]
+# CHECK: Vreg: %19[ 9 ]
+# CHECK: Instr: %503:sreg_32 = S_XOR_B32 killed %39, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 13 ]
+# CHECK: Vreg: %45[ 6 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %130[ 16 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %132[ 15 ]
+# CHECK: Vreg: %30[ 7 ]
+# CHECK: Vreg: %122[ 13 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ 3 ]
+# CHECK: Vreg: %124[ 16 ]
+# CHECK: Vreg: %22[ 17 ]
+# CHECK: Vreg: %119[ 7 ]
+# CHECK: Vreg: %126[ 15 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Instr: %504:sreg_32 = S_XOR_B32 killed %42, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 12 ]
+# CHECK: Vreg: %45[ 5 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %130[ 15 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %132[ 14 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %122[ 12 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %124[ 15 ]
+# CHECK: Vreg: %22[ 16 ]
+# CHECK: Vreg: %119[ 6 ]
+# CHECK: Vreg: %503[ 1 ]
+# CHECK: Vreg: %126[ 14 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Instr: %443:sreg_32 = SI_IF killed %503, %bb.25, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 11 ]
+# CHECK: Vreg: %45[ 4 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %130[ 14 ]
+# CHECK: Vreg: %132[ 13 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %504[ 2 ]
+# CHECK: Vreg: %122[ 11 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %124[ 14 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %119[ 5 ]
+# CHECK: Vreg: %503[ 0 ]
+# CHECK: Vreg: %126[ 13 ]
+# CHECK: Vreg: %19[ 6 ]
+# CHECK: Instr: S_BRANCH %bb.35
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 10 ]
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %443[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %130[ 13 ]
+# CHECK: Vreg: %132[ 12 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %504[ 1 ]
+# CHECK: Vreg: %122[ 10 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %124[ 13 ]
+# CHECK: Vreg: %22[ 14 ]
+# CHECK: Vreg: %119[ 4 ]
+# CHECK: Vreg: %126[ 12 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %128[ 10 ]
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %443[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %130[ 13 ]
+# CHECK: Vreg: %132[ 12 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %504[ 1 ]
+# CHECK: Vreg: %122[ 10 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %124[ 13 ]
+# CHECK: Vreg: %22[ 14 ]
+# CHECK: Vreg: %119[ 4 ]
+# CHECK: Vreg: %126[ 12 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: --- MBB_35 ---
+# CHECK: Instr: %462:sreg_32 = SI_IF killed %504, %bb.27, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 15 ]
+# CHECK: Vreg: %45[ 2 ]
+# CHECK: Vreg: %443[ 6 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %130[ 12 ]
+# CHECK: Vreg: %132[ 11 ]
+# CHECK: Vreg: %30[ 9 ]
+# CHECK: Vreg: %504[ 0 ]
+# CHECK: Vreg: %122[ 15 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %124[ 12 ]
+# CHECK: Vreg: %22[ 13 ]
+# CHECK: Vreg: %119[ 3 ]
+# CHECK: Vreg: %126[ 11 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Instr: S_BRANCH %bb.36
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 14 ]
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %462[ 1 ]
+# CHECK: Vreg: %443[ 5 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %130[ 11 ]
+# CHECK: Vreg: %132[ 10 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %122[ 14 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %124[ 11 ]
+# CHECK: Vreg: %22[ 12 ]
+# CHECK: Vreg: %119[ 2 ]
+# CHECK: Vreg: %126[ 10 ]
+# CHECK: Vreg: %19[ 3 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %128[ 14 ]
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %462[ 1 ]
+# CHECK: Vreg: %443[ 5 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %130[ 11 ]
+# CHECK: Vreg: %132[ 10 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %122[ 14 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %124[ 11 ]
+# CHECK: Vreg: %22[ 12 ]
+# CHECK: Vreg: %119[ 2 ]
+# CHECK: Vreg: %126[ 10 ]
+# CHECK: Vreg: %19[ 3 ]
+# CHECK: --- MBB_36 ---
+# CHECK: Instr: %487:sreg_32 = SI_IF killed %45, %bb.30, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 17 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %462[ 4 ]
+# CHECK: Vreg: %443[ 8 ]
+# CHECK: Vreg: %130[ 10 ]
+# CHECK: Vreg: %132[ 13 ]
+# CHECK: Vreg: %30[ 11 ]
+# CHECK: Vreg: %122[ 17 ]
+# CHECK: Vreg: %124[ 14 ]
+# CHECK: Vreg: %22[ 11 ]
+# CHECK: Vreg: %119[ 1 ]
+# CHECK: Vreg: %126[ 9 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.29
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %128[ 16 ]
+# CHECK: Vreg: %462[ 3 ]
+# CHECK: Vreg: %443[ 7 ]
+# CHECK: Vreg: %130[ 9 ]
+# CHECK: Vreg: %132[ 12 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %122[ 16 ]
+# CHECK: Vreg: %487[ 1 ]
+# CHECK: Vreg: %124[ 13 ]
+# CHECK: Vreg: %22[ 10 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %126[ 8 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %128[ 16 ]
+# CHECK: Vreg: %462[ 3 ]
+# CHECK: Vreg: %443[ 7 ]
+# CHECK: Vreg: %130[ 9 ]
+# CHECK: Vreg: %132[ 12 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %122[ 16 ]
+# CHECK: Vreg: %487[ 1 ]
+# CHECK: Vreg: %124[ 13 ]
+# CHECK: Vreg: %22[ 10 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %126[ 8 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: --- MBB_37 ---
+# CHECK: Instr: %505:sreg_32 = PHI %198, %bb.8, %200, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %173[ 0 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %208[ 0 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %198[ 0 ]
+# CHECK: Vreg: %205[ 0 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %195[ 0 ]
+# CHECK: Vreg: %209[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %206[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %196[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %203[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %193[ 0 ]
+# CHECK: Vreg: %200[ 0 ]
+# CHECK: Vreg: %207[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Instr: %506:sreg_32 = PHI %196, %bb.8, %195, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %173[ 0 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %208[ 0 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %205[ 0 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %195[ 0 ]
+# CHECK: Vreg: %209[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %206[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %196[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %203[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %193[ 0 ]
+# CHECK: Vreg: %207[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %505[ 3 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Instr: %152:vgpr_32 = PHI %203, %bb.8, %173, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %173[ 0 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %208[ 0 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %205[ 0 ]
+# CHECK: Vreg: %506[ 2 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %209[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %206[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %203[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %193[ 0 ]
+# CHECK: Vreg: %207[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %505[ 3 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Instr: %150:vgpr_32 = PHI %205, %bb.8, %193, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %208[ 0 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %205[ 0 ]
+# CHECK: Vreg: %506[ 2 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %209[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %206[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %193[ 0 ]
+# CHECK: Vreg: %207[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %152[ 8 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %505[ 3 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Instr: %148:vgpr_32 = PHI %206, %bb.8, %145, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %208[ 0 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %506[ 2 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %150[ 8 ]
+# CHECK: Vreg: %209[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %206[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %207[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %152[ 8 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %505[ 3 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Instr: %146:vgpr_32 = PHI %207, %bb.8, %174, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %208[ 0 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %506[ 2 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %150[ 8 ]
+# CHECK: Vreg: %209[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %148[ 8 ]
+# CHECK: Vreg: %207[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %152[ 8 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %505[ 3 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Instr: %246:vgpr_32 = PHI %208, %bb.8, %145, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %208[ 0 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %146[ 8 ]
+# CHECK: Vreg: %506[ 2 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %150[ 8 ]
+# CHECK: Vreg: %209[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %148[ 8 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %152[ 8 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %505[ 3 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Instr: %247:vgpr_32 = PHI %209, %bb.8, %147, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %246[ LoopTag+16 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %146[ 8 ]
+# CHECK: Vreg: %506[ 2 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %150[ 8 ]
+# CHECK: Vreg: %209[ 0 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %148[ 8 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %152[ 8 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %505[ 3 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Instr: %250:vgpr_32 = PHI %210, %bb.8, %149, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %246[ LoopTag+16 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %505[ 3 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %149[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %146[ 8 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %506[ 2 ]
+# CHECK: Vreg: %210[ 0 ]
+# CHECK: Vreg: %148[ 8 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %150[ 8 ]
+# CHECK: Vreg: %247[ LoopTag+16 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %152[ 8 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Instr: %249:vgpr_32 = PHI %211, %bb.8, %151, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %90[ LoopTag+24 ]
+# CHECK: Vreg: %71[ LoopTag+22 ]
+# CHECK: Vreg: %211[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+42 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %104[ 14 ]
+# CHECK: Vreg: %92[ LoopTag+27 ]
+# CHECK: Vreg: %73[ LoopTag+22 ]
+# CHECK: Vreg: %246[ LoopTag+16 ]
+# CHECK: Vreg: %213[ 1 ]
+# CHECK: Vreg: %505[ 3 ]
+# CHECK: Vreg: %23[ LoopTag+63 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %151[ 0 ]
+# CHECK: Vreg: %94[ LoopTag+30 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %37[ LoopTag+45 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %63[ LoopTag+15 ]
+# CHECK: Vreg: %146[ 8 ]
+# CHECK: Vreg: %96[ LoopTag+37 ]
+# CHECK: Vreg: %58[ LoopTag+38 ]
+# CHECK: Vreg: %250[ LoopTag+18 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %65[ LoopTag+22 ]
+# CHECK: Vreg: %212[ LoopTag+16 ]
+# CHECK: Vreg: %506[ 2 ]
+# CHECK: Vreg: %148[ 8 ]
+# CHECK: Vreg: %143[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+15 ]
+# CHECK: Vreg: %22[ LoopTag+30 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+53 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+54 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %67[ LoopTag+22 ]
+# CHECK: Vreg: %150[ 8 ]
+# CHECK: Vreg: %247[ LoopTag+16 ]
+# CHECK: Vreg: %43[ LoopTag+39 ]
+# CHECK: Vreg: %88[ 15 ]
+# CHECK: Vreg: %5[ 37 ]
+# CHECK: Vreg: %69[ LoopTag+22 ]
+# CHECK: Vreg: %95[ LoopTag+33 ]
+# CHECK: Vreg: %140[ 4 ]
+# CHECK: Vreg: %152[ 8 ]
+# CHECK: Vreg: %19[ 16 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+77 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+78 ]
+# CHECK: Instr: SI_END_CF killed %213, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+18 ]
+# CHECK: Vreg: %90[ LoopTag+23 ]
+# CHECK: Vreg: %71[ LoopTag+21 ]
+# CHECK: Vreg: %40[ LoopTag+41 ]
+# CHECK: Vreg: %21[ LoopTag+16 ]
+# CHECK: Vreg: %2[ LoopTag+37 ]
+# CHECK: Vreg: %104[ 13 ]
+# CHECK: Vreg: %92[ LoopTag+26 ]
+# CHECK: Vreg: %73[ LoopTag+21 ]
+# CHECK: Vreg: %246[ LoopTag+15 ]
+# CHECK: Vreg: %213[ 0 ]
+# CHECK: Vreg: %505[ 2 ]
+# CHECK: Vreg: %23[ LoopTag+62 ]
+# CHECK: Vreg: %4[ 38 ]
+# CHECK: Vreg: %94[ LoopTag+29 ]
+# CHECK: Vreg: %30[ 12 ]
+# CHECK: Vreg: %37[ LoopTag+44 ]
+# CHECK: Vreg: %18[ LoopTag+34 ]
+# CHECK: Vreg: %63[ LoopTag+14 ]
+# CHECK: Vreg: %146[ 7 ]
+# CHECK: Vreg: %96[ LoopTag+36 ]
+# CHECK: Vreg: %58[ LoopTag+37 ]
+# CHECK: Vreg: %250[ LoopTag+17 ]
+# CHECK: Vreg: %20[ LoopTag+12 ]
+# CHECK: Vreg: %1[ LoopTag+53 ]
+# CHECK: Vreg: %65[ LoopTag+21 ]
+# CHECK: Vreg: %212[ LoopTag+15 ]
+# CHECK: Vreg: %506[ 1 ]
+# CHECK: Vreg: %148[ 7 ]
+# CHECK: Vreg: %143[ 2 ]
+# CHECK: Vreg: %60[ LoopTag+14 ]
+# CHECK: Vreg: %22[ LoopTag+29 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+52 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+53 ]
+# CHECK: Vreg: %3[ LoopTag+23 ]
+# CHECK: Vreg: %67[ LoopTag+21 ]
+# CHECK: Vreg: %150[ 7 ]
+# CHECK: Vreg: %247[ LoopTag+15 ]
+# CHECK: Vreg: %43[ LoopTag+38 ]
+# CHECK: Vreg: %88[ 14 ]
+# CHECK: Vreg: %5[ 36 ]
+# CHECK: Vreg: %69[ LoopTag+21 ]
+# CHECK: Vreg: %95[ LoopTag+32 ]
+# CHECK: Vreg: %140[ 3 ]
+# CHECK: Vreg: %249[ LoopTag+17 ]
+# CHECK: Vreg: %152[ 7 ]
+# CHECK: Vreg: %19[ 15 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+76 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+77 ]
+# CHECK: Instr: %507:sreg_32 = S_XOR_B32 killed %506, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+17 ]
+# CHECK: Vreg: %90[ LoopTag+22 ]
+# CHECK: Vreg: %71[ LoopTag+20 ]
+# CHECK: Vreg: %40[ LoopTag+40 ]
+# CHECK: Vreg: %21[ LoopTag+15 ]
+# CHECK: Vreg: %2[ LoopTag+36 ]
+# CHECK: Vreg: %104[ 12 ]
+# CHECK: Vreg: %92[ LoopTag+25 ]
+# CHECK: Vreg: %73[ LoopTag+20 ]
+# CHECK: Vreg: %246[ LoopTag+14 ]
+# CHECK: Vreg: %505[ 1 ]
+# CHECK: Vreg: %23[ LoopTag+61 ]
+# CHECK: Vreg: %4[ 37 ]
+# CHECK: Vreg: %94[ LoopTag+28 ]
+# CHECK: Vreg: %30[ 11 ]
+# CHECK: Vreg: %37[ LoopTag+43 ]
+# CHECK: Vreg: %18[ LoopTag+33 ]
+# CHECK: Vreg: %63[ LoopTag+13 ]
+# CHECK: Vreg: %146[ 6 ]
+# CHECK: Vreg: %96[ LoopTag+35 ]
+# CHECK: Vreg: %58[ LoopTag+36 ]
+# CHECK: Vreg: %250[ LoopTag+16 ]
+# CHECK: Vreg: %20[ LoopTag+11 ]
+# CHECK: Vreg: %1[ LoopTag+52 ]
+# CHECK: Vreg: %65[ LoopTag+20 ]
+# CHECK: Vreg: %212[ LoopTag+14 ]
+# CHECK: Vreg: %506[ 0 ]
+# CHECK: Vreg: %148[ 6 ]
+# CHECK: Vreg: %143[ 1 ]
+# CHECK: Vreg: %60[ LoopTag+13 ]
+# CHECK: Vreg: %22[ LoopTag+28 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+51 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+52 ]
+# CHECK: Vreg: %3[ LoopTag+22 ]
+# CHECK: Vreg: %67[ LoopTag+20 ]
+# CHECK: Vreg: %150[ 6 ]
+# CHECK: Vreg: %247[ LoopTag+14 ]
+# CHECK: Vreg: %43[ LoopTag+37 ]
+# CHECK: Vreg: %88[ 13 ]
+# CHECK: Vreg: %5[ 35 ]
+# CHECK: Vreg: %69[ LoopTag+20 ]
+# CHECK: Vreg: %95[ LoopTag+31 ]
+# CHECK: Vreg: %140[ 2 ]
+# CHECK: Vreg: %249[ LoopTag+16 ]
+# CHECK: Vreg: %152[ 6 ]
+# CHECK: Vreg: %19[ 14 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+75 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+76 ]
+# CHECK: Instr: %144:sreg_32 = SI_IF_BREAK killed %505, killed %143, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+16 ]
+# CHECK: Vreg: %90[ LoopTag+21 ]
+# CHECK: Vreg: %71[ LoopTag+19 ]
+# CHECK: Vreg: %507[ 2 ]
+# CHECK: Vreg: %40[ LoopTag+39 ]
+# CHECK: Vreg: %21[ LoopTag+14 ]
+# CHECK: Vreg: %2[ LoopTag+35 ]
+# CHECK: Vreg: %104[ 11 ]
+# CHECK: Vreg: %92[ LoopTag+24 ]
+# CHECK: Vreg: %73[ LoopTag+19 ]
+# CHECK: Vreg: %246[ LoopTag+13 ]
+# CHECK: Vreg: %505[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+60 ]
+# CHECK: Vreg: %4[ 36 ]
+# CHECK: Vreg: %94[ LoopTag+27 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %37[ LoopTag+42 ]
+# CHECK: Vreg: %18[ LoopTag+32 ]
+# CHECK: Vreg: %63[ LoopTag+12 ]
+# CHECK: Vreg: %146[ 5 ]
+# CHECK: Vreg: %96[ LoopTag+34 ]
+# CHECK: Vreg: %58[ LoopTag+35 ]
+# CHECK: Vreg: %250[ LoopTag+15 ]
+# CHECK: Vreg: %20[ LoopTag+10 ]
+# CHECK: Vreg: %1[ LoopTag+51 ]
+# CHECK: Vreg: %65[ LoopTag+19 ]
+# CHECK: Vreg: %212[ LoopTag+13 ]
+# CHECK: Vreg: %148[ 5 ]
+# CHECK: Vreg: %143[ 0 ]
+# CHECK: Vreg: %60[ LoopTag+12 ]
+# CHECK: Vreg: %22[ LoopTag+27 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+50 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+51 ]
+# CHECK: Vreg: %3[ LoopTag+21 ]
+# CHECK: Vreg: %67[ LoopTag+19 ]
+# CHECK: Vreg: %150[ 5 ]
+# CHECK: Vreg: %247[ LoopTag+13 ]
+# CHECK: Vreg: %43[ LoopTag+36 ]
+# CHECK: Vreg: %88[ 12 ]
+# CHECK: Vreg: %5[ 34 ]
+# CHECK: Vreg: %69[ LoopTag+19 ]
+# CHECK: Vreg: %95[ LoopTag+30 ]
+# CHECK: Vreg: %140[ 1 ]
+# CHECK: Vreg: %249[ LoopTag+15 ]
+# CHECK: Vreg: %152[ 5 ]
+# CHECK: Vreg: %19[ 13 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+74 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+75 ]
+# CHECK: Instr: %508:sreg_32 = S_ANDN2_B32 killed %140, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %90[ LoopTag+20 ]
+# CHECK: Vreg: %71[ LoopTag+18 ]
+# CHECK: Vreg: %507[ 1 ]
+# CHECK: Vreg: %40[ LoopTag+38 ]
+# CHECK: Vreg: %21[ LoopTag+13 ]
+# CHECK: Vreg: %2[ LoopTag+34 ]
+# CHECK: Vreg: %104[ 10 ]
+# CHECK: Vreg: %92[ LoopTag+23 ]
+# CHECK: Vreg: %73[ LoopTag+18 ]
+# CHECK: Vreg: %246[ LoopTag+12 ]
+# CHECK: Vreg: %144[ 3 ]
+# CHECK: Vreg: %23[ LoopTag+59 ]
+# CHECK: Vreg: %4[ 35 ]
+# CHECK: Vreg: %94[ LoopTag+26 ]
+# CHECK: Vreg: %30[ 9 ]
+# CHECK: Vreg: %37[ LoopTag+41 ]
+# CHECK: Vreg: %18[ LoopTag+31 ]
+# CHECK: Vreg: %63[ LoopTag+11 ]
+# CHECK: Vreg: %146[ 4 ]
+# CHECK: Vreg: %96[ LoopTag+33 ]
+# CHECK: Vreg: %58[ LoopTag+34 ]
+# CHECK: Vreg: %250[ LoopTag+14 ]
+# CHECK: Vreg: %20[ LoopTag+9 ]
+# CHECK: Vreg: %1[ LoopTag+50 ]
+# CHECK: Vreg: %65[ LoopTag+18 ]
+# CHECK: Vreg: %212[ LoopTag+12 ]
+# CHECK: Vreg: %148[ 4 ]
+# CHECK: Vreg: %60[ LoopTag+11 ]
+# CHECK: Vreg: %22[ LoopTag+26 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+49 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+50 ]
+# CHECK: Vreg: %3[ LoopTag+20 ]
+# CHECK: Vreg: %67[ LoopTag+18 ]
+# CHECK: Vreg: %150[ 4 ]
+# CHECK: Vreg: %247[ LoopTag+12 ]
+# CHECK: Vreg: %43[ LoopTag+35 ]
+# CHECK: Vreg: %88[ 11 ]
+# CHECK: Vreg: %5[ 33 ]
+# CHECK: Vreg: %69[ LoopTag+18 ]
+# CHECK: Vreg: %95[ LoopTag+29 ]
+# CHECK: Vreg: %140[ 0 ]
+# CHECK: Vreg: %249[ LoopTag+14 ]
+# CHECK: Vreg: %152[ 4 ]
+# CHECK: Vreg: %19[ 12 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+73 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+74 ]
+# CHECK: Instr: %509:sreg_32 = S_AND_B32 killed %507, $exec_lo, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+14 ]
+# CHECK: Vreg: %90[ LoopTag+19 ]
+# CHECK: Vreg: %71[ LoopTag+17 ]
+# CHECK: Vreg: %507[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+37 ]
+# CHECK: Vreg: %21[ LoopTag+12 ]
+# CHECK: Vreg: %2[ LoopTag+33 ]
+# CHECK: Vreg: %104[ 9 ]
+# CHECK: Vreg: %92[ LoopTag+22 ]
+# CHECK: Vreg: %73[ LoopTag+17 ]
+# CHECK: Vreg: %246[ LoopTag+11 ]
+# CHECK: Vreg: %144[ 2 ]
+# CHECK: Vreg: %23[ LoopTag+58 ]
+# CHECK: Vreg: %4[ 34 ]
+# CHECK: Vreg: %94[ LoopTag+25 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %37[ LoopTag+40 ]
+# CHECK: Vreg: %18[ LoopTag+30 ]
+# CHECK: Vreg: %63[ LoopTag+10 ]
+# CHECK: Vreg: %146[ 3 ]
+# CHECK: Vreg: %96[ LoopTag+32 ]
+# CHECK: Vreg: %58[ LoopTag+33 ]
+# CHECK: Vreg: %250[ LoopTag+13 ]
+# CHECK: Vreg: %20[ LoopTag+8 ]
+# CHECK: Vreg: %1[ LoopTag+49 ]
+# CHECK: Vreg: %65[ LoopTag+17 ]
+# CHECK: Vreg: %212[ LoopTag+11 ]
+# CHECK: Vreg: %148[ 3 ]
+# CHECK: Vreg: %60[ LoopTag+10 ]
+# CHECK: Vreg: %508[ 1 ]
+# CHECK: Vreg: %22[ LoopTag+25 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+48 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+49 ]
+# CHECK: Vreg: %3[ LoopTag+19 ]
+# CHECK: Vreg: %67[ LoopTag+17 ]
+# CHECK: Vreg: %150[ 3 ]
+# CHECK: Vreg: %247[ LoopTag+11 ]
+# CHECK: Vreg: %43[ LoopTag+34 ]
+# CHECK: Vreg: %88[ 10 ]
+# CHECK: Vreg: %5[ 32 ]
+# CHECK: Vreg: %69[ LoopTag+17 ]
+# CHECK: Vreg: %95[ LoopTag+28 ]
+# CHECK: Vreg: %249[ LoopTag+13 ]
+# CHECK: Vreg: %152[ 3 ]
+# CHECK: Vreg: %19[ 11 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+72 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+73 ]
+# CHECK: Instr: %142:sreg_32 = S_OR_B32 killed %508, killed %509, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+13 ]
+# CHECK: Vreg: %90[ LoopTag+18 ]
+# CHECK: Vreg: %71[ LoopTag+16 ]
+# CHECK: Vreg: %40[ LoopTag+36 ]
+# CHECK: Vreg: %21[ LoopTag+11 ]
+# CHECK: Vreg: %2[ LoopTag+32 ]
+# CHECK: Vreg: %104[ 8 ]
+# CHECK: Vreg: %92[ LoopTag+21 ]
+# CHECK: Vreg: %73[ LoopTag+16 ]
+# CHECK: Vreg: %246[ LoopTag+10 ]
+# CHECK: Vreg: %144[ 1 ]
+# CHECK: Vreg: %509[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+57 ]
+# CHECK: Vreg: %4[ 33 ]
+# CHECK: Vreg: %94[ LoopTag+24 ]
+# CHECK: Vreg: %30[ 7 ]
+# CHECK: Vreg: %37[ LoopTag+39 ]
+# CHECK: Vreg: %18[ LoopTag+29 ]
+# CHECK: Vreg: %63[ LoopTag+9 ]
+# CHECK: Vreg: %146[ 2 ]
+# CHECK: Vreg: %96[ LoopTag+31 ]
+# CHECK: Vreg: %58[ LoopTag+32 ]
+# CHECK: Vreg: %250[ LoopTag+12 ]
+# CHECK: Vreg: %20[ LoopTag+7 ]
+# CHECK: Vreg: %1[ LoopTag+48 ]
+# CHECK: Vreg: %65[ LoopTag+16 ]
+# CHECK: Vreg: %212[ LoopTag+10 ]
+# CHECK: Vreg: %148[ 2 ]
+# CHECK: Vreg: %60[ LoopTag+9 ]
+# CHECK: Vreg: %508[ 0 ]
+# CHECK: Vreg: %22[ LoopTag+24 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+47 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+48 ]
+# CHECK: Vreg: %3[ LoopTag+18 ]
+# CHECK: Vreg: %67[ LoopTag+16 ]
+# CHECK: Vreg: %150[ 2 ]
+# CHECK: Vreg: %247[ LoopTag+10 ]
+# CHECK: Vreg: %43[ LoopTag+33 ]
+# CHECK: Vreg: %88[ 9 ]
+# CHECK: Vreg: %5[ 31 ]
+# CHECK: Vreg: %69[ LoopTag+16 ]
+# CHECK: Vreg: %95[ LoopTag+27 ]
+# CHECK: Vreg: %249[ LoopTag+12 ]
+# CHECK: Vreg: %152[ 2 ]
+# CHECK: Vreg: %19[ 10 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+71 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+72 ]
+# CHECK: Instr: SI_LOOP %144, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %90[ LoopTag+17 ]
+# CHECK: Vreg: %71[ LoopTag+15 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %40[ LoopTag+35 ]
+# CHECK: Vreg: %21[ LoopTag+10 ]
+# CHECK: Vreg: %2[ LoopTag+31 ]
+# CHECK: Vreg: %104[ 7 ]
+# CHECK: Vreg: %92[ LoopTag+20 ]
+# CHECK: Vreg: %73[ LoopTag+15 ]
+# CHECK: Vreg: %246[ LoopTag+9 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+56 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %94[ LoopTag+23 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %37[ LoopTag+38 ]
+# CHECK: Vreg: %18[ LoopTag+28 ]
+# CHECK: Vreg: %63[ LoopTag+8 ]
+# CHECK: Vreg: %146[ 1 ]
+# CHECK: Vreg: %96[ LoopTag+30 ]
+# CHECK: Vreg: %58[ LoopTag+31 ]
+# CHECK: Vreg: %250[ LoopTag+11 ]
+# CHECK: Vreg: %20[ LoopTag+6 ]
+# CHECK: Vreg: %1[ LoopTag+47 ]
+# CHECK: Vreg: %65[ LoopTag+15 ]
+# CHECK: Vreg: %212[ LoopTag+9 ]
+# CHECK: Vreg: %148[ 1 ]
+# CHECK: Vreg: %60[ LoopTag+8 ]
+# CHECK: Vreg: %22[ LoopTag+23 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+46 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+47 ]
+# CHECK: Vreg: %3[ LoopTag+17 ]
+# CHECK: Vreg: %67[ LoopTag+15 ]
+# CHECK: Vreg: %150[ 1 ]
+# CHECK: Vreg: %247[ LoopTag+9 ]
+# CHECK: Vreg: %43[ LoopTag+32 ]
+# CHECK: Vreg: %88[ 8 ]
+# CHECK: Vreg: %5[ 30 ]
+# CHECK: Vreg: %69[ LoopTag+15 ]
+# CHECK: Vreg: %95[ LoopTag+26 ]
+# CHECK: Vreg: %249[ LoopTag+11 ]
+# CHECK: Vreg: %152[ 1 ]
+# CHECK: Vreg: %19[ 9 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+70 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+71 ]
+# CHECK: Instr: S_BRANCH %bb.38
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+11 ]
+# CHECK: Vreg: %90[ LoopTag+16 ]
+# CHECK: Vreg: %71[ LoopTag+14 ]
+# CHECK: Vreg: %142[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+34 ]
+# CHECK: Vreg: %21[ LoopTag+9 ]
+# CHECK: Vreg: %2[ LoopTag+30 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %92[ LoopTag+19 ]
+# CHECK: Vreg: %73[ LoopTag+14 ]
+# CHECK: Vreg: %246[ LoopTag+8 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+55 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %94[ LoopTag+22 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %37[ LoopTag+37 ]
+# CHECK: Vreg: %18[ LoopTag+27 ]
+# CHECK: Vreg: %63[ LoopTag+7 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+29 ]
+# CHECK: Vreg: %58[ LoopTag+30 ]
+# CHECK: Vreg: %250[ LoopTag+10 ]
+# CHECK: Vreg: %20[ LoopTag+5 ]
+# CHECK: Vreg: %1[ LoopTag+46 ]
+# CHECK: Vreg: %65[ LoopTag+14 ]
+# CHECK: Vreg: %212[ LoopTag+8 ]
+# CHECK: Vreg: %148[ 0 ]
+# CHECK: Vreg: %60[ LoopTag+7 ]
+# CHECK: Vreg: %22[ LoopTag+22 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+46 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %67[ LoopTag+14 ]
+# CHECK: Vreg: %150[ 0 ]
+# CHECK: Vreg: %247[ LoopTag+8 ]
+# CHECK: Vreg: %43[ LoopTag+31 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ LoopTag+14 ]
+# CHECK: Vreg: %95[ LoopTag+25 ]
+# CHECK: Vreg: %249[ LoopTag+10 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+69 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+70 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+11 ]
+# CHECK: Vreg: %90[ LoopTag+16 ]
+# CHECK: Vreg: %71[ LoopTag+14 ]
+# CHECK: Vreg: %142[ 0 ]
+# CHECK: Vreg: %40[ LoopTag+34 ]
+# CHECK: Vreg: %21[ LoopTag+9 ]
+# CHECK: Vreg: %2[ LoopTag+30 ]
+# CHECK: Vreg: %104[ 6 ]
+# CHECK: Vreg: %92[ LoopTag+19 ]
+# CHECK: Vreg: %73[ LoopTag+14 ]
+# CHECK: Vreg: %246[ LoopTag+8 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+55 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %94[ LoopTag+22 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %37[ LoopTag+37 ]
+# CHECK: Vreg: %18[ LoopTag+27 ]
+# CHECK: Vreg: %63[ LoopTag+7 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %96[ LoopTag+29 ]
+# CHECK: Vreg: %58[ LoopTag+30 ]
+# CHECK: Vreg: %250[ LoopTag+10 ]
+# CHECK: Vreg: %20[ LoopTag+5 ]
+# CHECK: Vreg: %1[ LoopTag+46 ]
+# CHECK: Vreg: %65[ LoopTag+14 ]
+# CHECK: Vreg: %212[ LoopTag+8 ]
+# CHECK: Vreg: %148[ 0 ]
+# CHECK: Vreg: %60[ LoopTag+7 ]
+# CHECK: Vreg: %22[ LoopTag+22 ]
+# CHECK: Vreg: %22:sub0[ LoopTag+45 ]
+# CHECK: Vreg: %22:sub1[ LoopTag+46 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %67[ LoopTag+14 ]
+# CHECK: Vreg: %150[ 0 ]
+# CHECK: Vreg: %247[ LoopTag+8 ]
+# CHECK: Vreg: %43[ LoopTag+31 ]
+# CHECK: Vreg: %88[ 7 ]
+# CHECK: Vreg: %5[ 29 ]
+# CHECK: Vreg: %69[ LoopTag+14 ]
+# CHECK: Vreg: %95[ LoopTag+25 ]
+# CHECK: Vreg: %249[ LoopTag+10 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ LoopTag+69 ]
+# CHECK: Vreg: %19:sub1[ LoopTag+70 ]
+# CHECK: --- MBB_38 ---
+# CHECK: Instr: SI_END_CF killed %144, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %90[ 15 ]
+# CHECK: Vreg: %71[ 13 ]
+# CHECK: Vreg: %142[ 2 ]
+# CHECK: Vreg: %40[ 33 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %2[ 29 ]
+# CHECK: Vreg: %92[ 18 ]
+# CHECK: Vreg: %73[ 13 ]
+# CHECK: Vreg: %246[ 7 ]
+# CHECK: Vreg: %144[ 0 ]
+# CHECK: Vreg: %23[ 54 ]
+# CHECK: Vreg: %4[ 104 ]
+# CHECK: Vreg: %94[ 21 ]
+# CHECK: Vreg: %30[ 78 ]
+# CHECK: Vreg: %37[ 36 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %63[ 6 ]
+# CHECK: Vreg: %96[ 28 ]
+# CHECK: Vreg: %58[ 29 ]
+# CHECK: Vreg: %250[ 9 ]
+# CHECK: Vreg: %20[ 4 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %65[ 13 ]
+# CHECK: Vreg: %212[ 7 ]
+# CHECK: Vreg: %60[ 6 ]
+# CHECK: Vreg: %22[ 21 ]
+# CHECK: Vreg: %22:sub0[ 44 ]
+# CHECK: Vreg: %22:sub1[ 45 ]
+# CHECK: Vreg: %3[ 15 ]
+# CHECK: Vreg: %67[ 13 ]
+# CHECK: Vreg: %247[ 7 ]
+# CHECK: Vreg: %43[ 30 ]
+# CHECK: Vreg: %5[ 102 ]
+# CHECK: Vreg: %69[ 13 ]
+# CHECK: Vreg: %95[ 24 ]
+# CHECK: Vreg: %249[ 9 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Vreg: %19:sub0[ 68 ]
+# CHECK: Vreg: %19:sub1[ 69 ]
+# CHECK: Instr: %234:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %90[ 14 ]
+# CHECK: Vreg: %71[ 12 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %40[ 32 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %2[ 28 ]
+# CHECK: Vreg: %92[ 17 ]
+# CHECK: Vreg: %73[ 12 ]
+# CHECK: Vreg: %246[ 6 ]
+# CHECK: Vreg: %23[ 53 ]
+# CHECK: Vreg: %4[ 103 ]
+# CHECK: Vreg: %94[ 20 ]
+# CHECK: Vreg: %30[ 77 ]
+# CHECK: Vreg: %37[ 35 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %63[ 5 ]
+# CHECK: Vreg: %96[ 27 ]
+# CHECK: Vreg: %58[ 28 ]
+# CHECK: Vreg: %250[ 8 ]
+# CHECK: Vreg: %20[ 3 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %65[ 12 ]
+# CHECK: Vreg: %212[ 6 ]
+# CHECK: Vreg: %60[ 5 ]
+# CHECK: Vreg: %22[ 20 ]
+# CHECK: Vreg: %22:sub0[ 43 ]
+# CHECK: Vreg: %22:sub1[ 44 ]
+# CHECK: Vreg: %3[ 14 ]
+# CHECK: Vreg: %67[ 12 ]
+# CHECK: Vreg: %247[ 6 ]
+# CHECK: Vreg: %43[ 29 ]
+# CHECK: Vreg: %5[ 101 ]
+# CHECK: Vreg: %69[ 12 ]
+# CHECK: Vreg: %95[ 23 ]
+# CHECK: Vreg: %249[ 8 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Vreg: %19:sub0[ 67 ]
+# CHECK: Vreg: %19:sub1[ 68 ]
+# CHECK: Instr: %244:sreg_32 = SI_IF killed %142, %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %90[ 13 ]
+# CHECK: Vreg: %71[ 11 ]
+# CHECK: Vreg: %142[ 0 ]
+# CHECK: Vreg: %40[ 31 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %2[ 27 ]
+# CHECK: Vreg: %92[ 16 ]
+# CHECK: Vreg: %73[ 11 ]
+# CHECK: Vreg: %246[ 5 ]
+# CHECK: Vreg: %234[ 1 ]
+# CHECK: Vreg: %23[ 52 ]
+# CHECK: Vreg: %4[ 102 ]
+# CHECK: Vreg: %94[ 19 ]
+# CHECK: Vreg: %30[ 76 ]
+# CHECK: Vreg: %37[ 34 ]
+# CHECK: Vreg: %18[ 24 ]
+# CHECK: Vreg: %63[ 4 ]
+# CHECK: Vreg: %96[ 26 ]
+# CHECK: Vreg: %58[ 27 ]
+# CHECK: Vreg: %250[ 7 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %65[ 11 ]
+# CHECK: Vreg: %212[ 5 ]
+# CHECK: Vreg: %60[ 4 ]
+# CHECK: Vreg: %22[ 19 ]
+# CHECK: Vreg: %22:sub0[ 42 ]
+# CHECK: Vreg: %22:sub1[ 43 ]
+# CHECK: Vreg: %3[ 13 ]
+# CHECK: Vreg: %67[ 11 ]
+# CHECK: Vreg: %247[ 5 ]
+# CHECK: Vreg: %43[ 28 ]
+# CHECK: Vreg: %5[ 100 ]
+# CHECK: Vreg: %69[ 11 ]
+# CHECK: Vreg: %95[ 22 ]
+# CHECK: Vreg: %249[ 7 ]
+# CHECK: Vreg: %19[ 6 ]
+# CHECK: Vreg: %19:sub0[ 66 ]
+# CHECK: Vreg: %19:sub1[ 67 ]
+# CHECK: Instr: S_BRANCH %bb.14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %90[ 12 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %244[ 2 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %246[ 4 ]
+# CHECK: Vreg: %234[ 0 ]
+# CHECK: Vreg: %23[ 51 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %94[ 18 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %37[ 33 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %96[ 25 ]
+# CHECK: Vreg: %58[ 26 ]
+# CHECK: Vreg: %250[ 6 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %212[ 4 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %22:sub0[ 41 ]
+# CHECK: Vreg: %22:sub1[ 42 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %247[ 4 ]
+# CHECK: Vreg: %43[ 27 ]
+# CHECK: Vreg: %5[ 99 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 21 ]
+# CHECK: Vreg: %249[ 6 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Vreg: %19:sub0[ 65 ]
+# CHECK: Vreg: %19:sub1[ 66 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %90[ 12 ]
+# CHECK: Vreg: %71[ 10 ]
+# CHECK: Vreg: %244[ 2 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %2[ 26 ]
+# CHECK: Vreg: %92[ 15 ]
+# CHECK: Vreg: %73[ 10 ]
+# CHECK: Vreg: %246[ 4 ]
+# CHECK: Vreg: %234[ 0 ]
+# CHECK: Vreg: %23[ 51 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %94[ 18 ]
+# CHECK: Vreg: %30[ 75 ]
+# CHECK: Vreg: %37[ 33 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %63[ 3 ]
+# CHECK: Vreg: %96[ 25 ]
+# CHECK: Vreg: %58[ 26 ]
+# CHECK: Vreg: %250[ 6 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %65[ 10 ]
+# CHECK: Vreg: %212[ 4 ]
+# CHECK: Vreg: %60[ 3 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %22:sub0[ 41 ]
+# CHECK: Vreg: %22:sub1[ 42 ]
+# CHECK: Vreg: %3[ 12 ]
+# CHECK: Vreg: %67[ 10 ]
+# CHECK: Vreg: %247[ 4 ]
+# CHECK: Vreg: %43[ 27 ]
+# CHECK: Vreg: %5[ 99 ]
+# CHECK: Vreg: %69[ 10 ]
+# CHECK: Vreg: %95[ 21 ]
+# CHECK: Vreg: %249[ 6 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Vreg: %19:sub0[ 65 ]
+# CHECK: Vreg: %19:sub1[ 66 ]
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test15(ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, ptr addrspace(1) %p4, ptr addrspace(1) %p5, ptr addrspace(1) %p6, i32 %TC1, i32 %TC2, i32 %TC3, i32 %TC4, i32 %TC5, i32 %Val) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  %add1 = add i32 %ld1, 100
+  br label %1
+  1:
+  %phi.inc1 = phi i32 [ 0, %0 ], [ %inc1, %11 ], [ %phi.inc2, %12 ], [ %phi.inc3, %13 ]
+  %phi.inc2 = phi i32 [ 1, %0 ], [ %phi.inc1, %11 ], [ %inc2, %12 ], [ %phi.inc3, %13 ]
+  %phi.inc3 = phi i32 [ 2, %0 ], [ %phi.inc1, %11 ], [ %phi.inc2, %12 ], [ %inc3, %13 ]
+  %phi.mul1 = phi i32 [ 100, %0 ], [ %mul4, %11 ], [ %mul6, %12 ], [ %mul7, %13 ]
+  %phi.mul2 = phi i32 [ 500, %0 ], [ %mul9, %11 ], [ %phi.mul3, %12 ], [ %phi.mul1, %13 ]
+  %sext1 = sext i32 %phi.inc1 to i64
+  %gep1 = getelementptr inbounds i64, ptr addrspace(1) %p2, i64 %sext1
+  %ld2 = load i32, ptr addrspace(1) %gep1, align 1
+  store i32 %ld2, ptr addrspace(1) %p1
+  %cond1 = icmp ult i32 %phi.inc1, %phi.inc2
+  br i1 %cond1, label %2, label %14
+  2:
+  %phi.inc4 = phi i32 [ 3, %1 ], [ %inc4, %3 ], [ %phi.inc5, %5 ]
+  %phi.inc5 = phi i32 [ 4, %1 ], [ %phi.inc4, %3 ], [ %inc5, %5 ]
+  %phi.div = phi i32 [ %phi.inc2, %1 ], [ %div1, %3 ], [ %div2, %5 ]
+  %phi.mul3 = phi i32 [ %phi.inc2, %1 ], [ %mul1, %3 ], [ %mul2, %5 ]
+  %cond2 = icmp ult i32 %phi.inc4, %phi.inc2
+  br i1 %cond2, label %3, label %4
+  3:
+  %mul1 = mul i32 %ld2, %phi.inc4
+  store i32 %mul1, ptr addrspace(1) %p5
+  %inc4 = add i32 %phi.inc4, 1
+  %div1 = udiv i32 %phi.inc4, %phi.inc5
+  %cond3 = icmp ult i32 %inc4, %TC1
+  br i1 %cond3, label %2, label %6
+  4:
+  %mul2 = mul i32 %ld1, %phi.inc5
+  %sext2 = sext i32 %phi.inc2 to i64
+  %gep2 = getelementptr inbounds i64, ptr addrspace(1) %p5, i64 %sext2
+  store i32 %mul2, ptr addrspace(1) %gep2
+  %div2 = udiv i32 %phi.inc5, %phi.inc4
+  %cond4 = icmp ult i32 %mul2, %ld2
+  br i1 %cond4, label %5, label %6
+  5:
+  %inc5 = add i32 %phi.inc5, 1
+  %cond5 = icmp ult i32 %inc5, %TC2
+  br i1 %cond5, label %2, label %8
+  6:
+  %mul3 = mul i32 %phi.inc4, %phi.inc5
+  store i32 %mul3, ptr addrspace(1) %p5
+  %mul9 = mul i32 %phi.mul3, %phi.div
+  %cond11 = icmp ult i32 %mul3, %Val
+  br i1 %cond11, label %7, label %15
+  7:
+  %ld3 = load i32, ptr addrspace(1) %p3, align 4
+  %mul4 = mul i32 %ld3, %phi.inc3
+  store i32 %mul3, ptr addrspace(1) %p4
+  %cond6 = icmp ult i32 %mul4, %mul3
+  br i1 %cond6, label %11, label %9
+  8:
+  %ld4 = load i32, ptr addrspace(1) %p4, align 2
+  %mul5 = mul i32 %ld4, %inc5
+  store i32 %mul5, ptr addrspace(1) %p3
+  br label %9
+  9:
+  %phi1 = phi i1 [ %cond6, %7 ], [ %cond4, %8 ]
+  %phi2 = phi i32 [ %ld3, %7 ], [ %ld4, %8 ]
+  %ld5 = load i32, ptr addrspace(1) %p5, align 1
+  %mul6 = mul i32 %ld5, %phi2
+  store i32 %mul6, ptr addrspace(1) %p2, align 2
+  br i1 %phi1, label %12, label %10
+  10:
+  %ld6 = load i32, ptr addrspace(1) %p6, align 1
+  %mul7 = mul i32 %ld6, %phi.inc3
+  store i32 %mul7, ptr addrspace(1) %p6, align 1
+  %cond7 = icmp ult i32 %mul7, %phi2
+  br i1 %cond7, label %13, label %16
+  11:
+  %inc1 = add i32 %phi.inc1, 1
+  %cond8 = icmp ult i32 %inc1, %TC3
+  br i1 %cond8, label %1, label %17
+  12:
+  %inc2 = add i32 %phi.inc2, 1
+  %cond9 = icmp ult i32 %inc2, %TC4
+  br i1 %cond9, label %1, label %17
+  13:
+  %inc3 = add i32 %phi.inc3, 1
+  %cond10 = icmp ult i32 %inc3, %TC5
+  br i1 %cond10, label %1, label %17
+  14:
+  %ld7 = load i32, ptr addrspace(1) %p3, align 1
+  %add2 = add i32 %ld7, %phi.inc1
+  %add3 = add i32 %add2, %phi.mul1
+  store i32 %add3, ptr addrspace(1) %p4, align 1
+  br label %17
+  15:
+  %ld8 = load i32, ptr addrspace(1) %p4, align 1
+  %mul8 = mul i32 %ld8, %phi.inc2
+  %add4 = add i32 %mul9, %mul8
+  store i32 %add4, ptr addrspace(1) %p3, align 1
+  br label %17
+  16:
+  %ld9 = load i32, ptr addrspace(1) %p5, align 1
+  %sub1 = sub i32 %ld9, %phi.inc3
+  %add5 = add i32 %sub1, %phi.mul2
+  store i32 %add5, ptr addrspace(1) %p2, align 1
+  br label %17
+  17:
+  %phi3 = phi i32 [ %inc1, %11 ], [ %inc2, %12 ], [ %inc3, %13 ], [ %add3, %14 ], [ %add4, %15 ], [ %add5, %16 ]
+  %add6 = add i32 %phi3, %add1
+  ret i32 %add6
+  }
+...
+
+---
+name:            test15
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16, $vgpr17
+  
+    %244:vgpr_32 = COPY killed $vgpr17
+    %243:vgpr_32 = COPY killed $vgpr16
+    %242:vgpr_32 = COPY killed $vgpr15
+    %241:vgpr_32 = COPY killed $vgpr14
+    %240:vgpr_32 = COPY killed $vgpr13
+    %239:vgpr_32 = COPY killed $vgpr12
+    %238:vgpr_32 = COPY killed $vgpr11
+    %237:vgpr_32 = COPY killed $vgpr10
+    %236:vgpr_32 = COPY killed $vgpr9
+    %235:vgpr_32 = COPY killed $vgpr8
+    %234:vgpr_32 = COPY killed $vgpr7
+    %233:vgpr_32 = COPY killed $vgpr6
+    %232:vgpr_32 = COPY killed $vgpr5
+    %231:vgpr_32 = COPY killed $vgpr4
+    %230:vgpr_32 = COPY killed $vgpr3
+    %229:vgpr_32 = COPY killed $vgpr2
+    %228:vgpr_32 = COPY killed $vgpr1
+    %227:vgpr_32 = COPY killed $vgpr0
+    %517:vreg_64 = REG_SEQUENCE killed %237, %subreg.sub0, killed %238, %subreg.sub1
+    %516:vreg_64 = REG_SEQUENCE killed %235, %subreg.sub0, killed %236, %subreg.sub1
+    %515:vreg_64 = REG_SEQUENCE killed %233, %subreg.sub0, killed %234, %subreg.sub1
+    %514:vreg_64 = REG_SEQUENCE killed %231, %subreg.sub0, killed %232, %subreg.sub1
+    %513:vreg_64 = REG_SEQUENCE killed %229, %subreg.sub0, killed %230, %subreg.sub1
+    %512:vreg_64 = REG_SEQUENCE killed %227, %subreg.sub0, killed %228, %subreg.sub1
+    %263:vgpr_32 = GLOBAL_LOAD_UBYTE %512, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %265:vgpr_32 = GLOBAL_LOAD_UBYTE %512, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %268:vgpr_32 = V_LSHL_OR_B32_e64 killed %265, 8, killed %263, implicit $exec
+    %269:vgpr_32 = GLOBAL_LOAD_UBYTE %512, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %271:vgpr_32 = GLOBAL_LOAD_UBYTE %512, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %273:vgpr_32 = V_LSHL_OR_B32_e64 killed %271, 8, killed %269, implicit $exec
+    %0:vgpr_32 = V_LSHL_OR_B32_e64 killed %273, 16, killed %268, implicit $exec
+    %256:vgpr_32 = V_MOV_B32_e32 500, implicit $exec
+    %255:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+    %254:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
+    %253:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    %251:sreg_32 = S_MOV_B32 0
+    %518:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  
+  bb.1:
+    successors: %bb.2(0x40000000), %bb.3(0x40000000)
+  
+    %612:sreg_32 = PHI undef %611:sreg_32, %bb.0, %194, %bb.3
+    %608:sreg_32 = PHI undef %607:sreg_32, %bb.0, %193, %bb.3
+    %604:sreg_32 = PHI undef %603:sreg_32, %bb.0, %192, %bb.3
+    %542:sreg_32 = PHI undef %539:sreg_32, %bb.0, %29, %bb.3
+    %536:sreg_32 = PHI undef %533:sreg_32, %bb.0, %21, %bb.3
+    %529:sreg_32 = PHI undef %526:sreg_32, %bb.0, %20, %bb.3
+    %522:sreg_32 = PHI undef %519:sreg_32, %bb.0, %19, %bb.3
+    %1:sreg_32 = PHI %251, %bb.0, %30, %bb.3
+    %2:vgpr_32 = PHI undef %252:vgpr_32, %bb.0, %12, %bb.3
+    %3:vgpr_32 = PHI undef %252:vgpr_32, %bb.0, %13, %bb.3
+    %4:vgpr_32 = PHI %518, %bb.0, %18, %bb.3
+    %5:vgpr_32 = PHI %253, %bb.0, %17, %bb.3
+    %6:vgpr_32 = PHI %254, %bb.0, %16, %bb.3
+    %7:vgpr_32 = PHI %255, %bb.0, %15, %bb.3
+    %8:vgpr_32 = PHI %256, %bb.0, %14, %bb.3
+    %279:vgpr_32 = V_ASHRREV_I32_e64 31, %4, implicit $exec
+    %281:vreg_64 = REG_SEQUENCE %4, %subreg.sub0, killed %279, %subreg.sub1
+    %283:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %281, implicit $exec
+    %623:vgpr_32, %625:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %513.sub0, %283.sub0, 0, implicit $exec
+    %624:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %513.sub1, killed %283.sub1, killed %625, 0, implicit $exec
+    %284:vreg_64 = REG_SEQUENCE killed %623, %subreg.sub0, killed %624, %subreg.sub1
+    %285:vgpr_32 = GLOBAL_LOAD_UBYTE %284, 0, 0, implicit $exec :: (load (s8) from %ir.gep1, addrspace 1)
+    %286:vgpr_32 = GLOBAL_LOAD_UBYTE %284, 1, 0, implicit $exec :: (load (s8) from %ir.gep1 + 1, addrspace 1)
+    %288:vgpr_32 = V_LSHL_OR_B32_e64 killed %286, 8, killed %285, implicit $exec
+    %289:vgpr_32 = GLOBAL_LOAD_UBYTE %284, 2, 0, implicit $exec :: (load (s8) from %ir.gep1 + 2, addrspace 1)
+    %290:vgpr_32 = GLOBAL_LOAD_UBYTE killed %284, 3, 0, implicit $exec :: (load (s8) from %ir.gep1 + 3, addrspace 1)
+    %291:vgpr_32 = V_LSHL_OR_B32_e64 killed %290, 8, killed %289, implicit $exec
+    %9:vgpr_32 = V_LSHL_OR_B32_e64 killed %291, 16, killed %288, implicit $exec
+    GLOBAL_STORE_DWORD %512, %9, 0, 0, implicit $exec :: (store (s32) into %ir.p1, addrspace 1)
+    %293:sreg_32 = V_CMP_LT_U32_e64 %4, %5, implicit $exec
+    %523:sreg_32 = S_ANDN2_B32 killed %522, $exec_lo, implicit-def dead $scc
+    %520:sreg_32 = COPY %523
+    %530:sreg_32 = S_ANDN2_B32 killed %529, $exec_lo, implicit-def dead $scc
+    %527:sreg_32 = COPY %530
+    %534:sreg_32 = S_OR_B32 killed %536, $exec_lo, implicit-def dead $scc
+    %540:sreg_32 = S_OR_B32 killed %542, $exec_lo, implicit-def dead $scc
+    %10:sreg_32 = SI_IF killed %293, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+  
+  bb.2:
+    successors: %bb.4(0x80000000)
+  
+    %299:vgpr_32 = V_ASHRREV_I32_e64 31, %5, implicit $exec
+    %301:vreg_64 = REG_SEQUENCE %5, %subreg.sub0, killed %299, %subreg.sub1
+    %297:vgpr_32 = V_MOV_B32_e32 3, implicit $exec
+    %302:vreg_64 = nsw V_LSHLREV_B64_pseudo_e64 3, killed %301, implicit $exec
+    %626:vgpr_32, %628:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %516.sub0, %302.sub0, 0, implicit $exec
+    %627:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %516.sub1, killed %302.sub1, killed %628, 0, implicit $exec
+    %11:vreg_64 = REG_SEQUENCE killed %626, %subreg.sub0, killed %627, %subreg.sub1
+    %298:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
+    %296:sreg_32 = S_MOV_B32 0
+    S_BRANCH %bb.4
+  
+  bb.3:
+    successors: %bb.34(0x04000000), %bb.1(0x7c000000)
+  
+    %29:sreg_32 = PHI %540, %bb.1, %541, %bb.33
+    %21:sreg_32 = PHI %534, %bb.1, %535, %bb.33
+    %20:sreg_32 = PHI %527, %bb.1, %528, %bb.33
+    %19:sreg_32 = PHI %520, %bb.1, %521, %bb.33
+    %12:vgpr_32 = PHI %2, %bb.1, %72, %bb.33
+    %13:vgpr_32 = PHI %3, %bb.1, %73, %bb.33
+    %14:vgpr_32 = PHI undef %275:vgpr_32, %bb.1, %176, %bb.33
+    %15:vgpr_32 = PHI undef %275:vgpr_32, %bb.1, %177, %bb.33
+    %16:vgpr_32 = PHI undef %275:vgpr_32, %bb.1, %178, %bb.33
+    %17:vgpr_32 = PHI undef %275:vgpr_32, %bb.1, %179, %bb.33
+    %18:vgpr_32 = PHI undef %275:vgpr_32, %bb.1, %180, %bb.33
+    %22:vgpr_32 = PHI undef %278:vgpr_32, %bb.1, %184, %bb.33
+    %23:vgpr_32 = PHI %4, %bb.1, %185, %bb.33
+    %24:vgpr_32 = PHI %5, %bb.1, %186, %bb.33
+    %25:vgpr_32 = PHI %6, %bb.1, %187, %bb.33
+    %26:vgpr_32 = PHI %7, %bb.1, %188, %bb.33
+    %27:vgpr_32 = PHI %8, %bb.1, %189, %bb.33
+    %28:vgpr_32 = PHI undef %278:vgpr_32, %bb.1, %190, %bb.33
+    SI_END_CF killed %10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %30:sreg_32 = SI_IF_BREAK %29, killed %1, implicit-def dead $scc
+    %605:sreg_32 = S_ANDN2_B32 killed %604, $exec_lo, implicit-def dead $scc
+    %606:sreg_32 = S_AND_B32 %19, $exec_lo, implicit-def dead $scc
+    %192:sreg_32 = S_OR_B32 killed %605, killed %606, implicit-def dead $scc
+    %609:sreg_32 = S_ANDN2_B32 killed %608, $exec_lo, implicit-def dead $scc
+    %610:sreg_32 = S_AND_B32 %20, $exec_lo, implicit-def dead $scc
+    %193:sreg_32 = S_OR_B32 killed %609, killed %610, implicit-def dead $scc
+    %613:sreg_32 = S_ANDN2_B32 killed %612, $exec_lo, implicit-def dead $scc
+    %614:sreg_32 = S_AND_B32 %21, $exec_lo, implicit-def dead $scc
+    %194:sreg_32 = S_OR_B32 killed %613, killed %614, implicit-def dead $scc
+    SI_LOOP %30, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.34
+  
+  bb.4:
+    successors: %bb.7(0x40000000), %bb.8(0x40000000)
+  
+    %620:sreg_32 = PHI undef %619:sreg_32, %bb.2, %223, %bb.37
+    %31:sreg_32 = PHI %296, %bb.2, %218, %bb.37
+    %32:vgpr_32 = PHI %297, %bb.2, %210, %bb.37
+    %33:vgpr_32 = PHI %298, %bb.2, %209, %bb.37
+    %34:vgpr_32 = PHI %5, %bb.2, %208, %bb.37
+    %35:vgpr_32 = PHI %5, %bb.2, %207, %bb.37
+    %306:sreg_32 = V_CMP_GE_U32_e64 %32, %5, implicit $exec
+    %307:sreg_32 = S_MOV_B32 -1
+    %36:sreg_32 = SI_IF killed %306, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.7
+  
+  bb.5:
+    successors: %bb.8(0x80000000)
+  
+    %43:sreg_32 = PHI %312, %bb.7, %546, %bb.9
+    %41:sreg_32 = PHI %312, %bb.7, %545, %bb.9
+    %37:vgpr_32 = PHI undef %308:vgpr_32, %bb.7, %48, %bb.9
+    %38:vgpr_32 = PHI undef %308:vgpr_32, %bb.7, %62, %bb.9
+    %39:vgpr_32 = PHI undef %308:vgpr_32, %bb.7, %63, %bb.9
+    %40:vgpr_32 = PHI undef %308:vgpr_32, %bb.7, %33, %bb.9
+    %42:vgpr_32 = PHI undef %310:vgpr_32, %bb.7, %63, %bb.9
+    SI_END_CF killed %49, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %548:sreg_32 = S_ORN2_B32 killed %43, $exec_lo, implicit-def dead $scc
+    S_BRANCH %bb.8
+  
+  bb.6:
+    successors: %bb.37(0x80000000)
+  
+    %44:vgpr_32 = V_MUL_LO_U32_e64 %9, %32, implicit $exec
+    GLOBAL_STORE_DWORD %516, %44, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+    %45:vgpr_32 = V_ADD_U32_e64 1, %32, 0, implicit $exec
+    %339:vgpr_32 = V_CVT_F32_U32_e64 %33, 0, 0, implicit $mode, implicit $exec
+    %340:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %339, 0, 0, implicit $mode, implicit $exec
+    %342:vgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, 1333788670, 0, killed %340, 0, 0, implicit $mode, implicit $exec
+    %343:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, killed %342, 0, 0, implicit $mode, implicit $exec
+    %345:vgpr_32 = V_SUB_U32_e64 0, %33, 0, implicit $exec
+    %346:vgpr_32 = V_MUL_LO_U32_e64 killed %345, %343, implicit $exec
+    %347:vgpr_32 = V_MUL_HI_U32_e64 %343, killed %346, implicit $exec
+    %348:vgpr_32 = V_ADD_U32_e64 killed %343, killed %347, 0, implicit $exec
+    %349:vgpr_32 = V_MUL_HI_U32_e64 %32, killed %348, implicit $exec
+    %350:vgpr_32 = V_MUL_LO_U32_e64 %349, %33, implicit $exec
+    %351:vgpr_32 = V_SUB_U32_e64 %32, killed %350, 0, implicit $exec
+    %352:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 %351, %33, implicit $exec
+    %353:vgpr_32 = V_ADD_U32_e64 1, %349, 0, implicit $exec
+    %354:vgpr_32 = V_CNDMASK_B32_e64 0, killed %349, 0, killed %353, %352, implicit $exec
+    %355:vgpr_32 = V_SUB_U32_e64 %351, %33, 0, implicit $exec
+    %356:vgpr_32 = V_CNDMASK_B32_e64 0, killed %351, 0, killed %355, killed %352, implicit $exec
+    %357:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 killed %356, %33, implicit $exec
+    %358:vgpr_32 = V_ADD_U32_e64 1, %354, 0, implicit $exec
+    %46:vgpr_32 = V_CNDMASK_B32_e64 0, killed %354, 0, killed %358, killed %357, implicit $exec
+    %359:sreg_32 = V_CMP_GE_U32_e64 %45, %239, implicit $exec
+    %615:sreg_32 = S_OR_B32 killed %54, $exec_lo, implicit-def dead $scc
+    %617:sreg_32 = S_ANDN2_B32 killed %60, $exec_lo, implicit-def dead $scc
+    %618:sreg_32 = S_AND_B32 killed %359, $exec_lo, implicit-def dead $scc
+    %616:sreg_32 = S_OR_B32 killed %617, killed %618, implicit-def dead $scc
+    S_BRANCH %bb.37
+  
+  bb.7:
+    successors: %bb.9(0x40000000), %bb.5(0x40000000)
+  
+    %48:vgpr_32 = V_MUL_LO_U32_e64 %0, %33, implicit $exec
+    GLOBAL_STORE_DWORD %11, %48, 0, 0, implicit $exec :: (store (s32) into %ir.gep2, addrspace 1)
+    %311:sreg_32 = V_CMP_LT_U32_e64 %48, %9, implicit $exec
+    %312:sreg_32 = S_MOV_B32 -1
+    %49:sreg_32 = SI_IF killed %311, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.9
+  
+  bb.8:
+    successors: %bb.6(0x40000000), %bb.37(0x40000000)
+  
+    %60:sreg_32 = PHI %307, %bb.4, %548, %bb.5
+    %54:sreg_32 = PHI undef %547:sreg_32, %bb.4, %41, %bb.5
+    %50:vgpr_32 = PHI undef %303:vgpr_32, %bb.4, %37, %bb.5
+    %51:vgpr_32 = PHI undef %303:vgpr_32, %bb.4, %38, %bb.5
+    %52:vgpr_32 = PHI undef %303:vgpr_32, %bb.4, %39, %bb.5
+    %53:vgpr_32 = PHI undef %303:vgpr_32, %bb.4, %40, %bb.5
+    %55:vgpr_32 = PHI undef %303:vgpr_32, %bb.4, %32, %bb.5
+    %56:vgpr_32 = PHI undef %303:vgpr_32, %bb.4, %33, %bb.5
+    %57:vgpr_32 = PHI undef %303:vgpr_32, %bb.4, %34, %bb.5
+    %58:vgpr_32 = PHI undef %303:vgpr_32, %bb.4, %35, %bb.5
+    %59:vgpr_32 = PHI undef %303:vgpr_32, %bb.4, %42, %bb.5
+    %61:sreg_32 = SI_ELSE killed %36, %bb.37, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.6
+  
+  bb.9:
+    successors: %bb.5(0x80000000)
+  
+    %314:vgpr_32 = V_CVT_F32_U32_e64 %32, 0, 0, implicit $mode, implicit $exec
+    %315:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %314, 0, 0, implicit $mode, implicit $exec
+    %317:vgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, 1333788670, 0, killed %315, 0, 0, implicit $mode, implicit $exec
+    %318:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, killed %317, 0, 0, implicit $mode, implicit $exec
+    %320:vgpr_32 = V_SUB_U32_e64 0, %32, 0, implicit $exec
+    %321:vgpr_32 = V_MUL_LO_U32_e64 killed %320, %318, implicit $exec
+    %322:vgpr_32 = V_MUL_HI_U32_e64 %318, killed %321, implicit $exec
+    %323:vgpr_32 = V_ADD_U32_e64 killed %318, killed %322, 0, implicit $exec
+    %324:vgpr_32 = V_MUL_HI_U32_e64 %33, killed %323, implicit $exec
+    %325:vgpr_32 = V_MUL_LO_U32_e64 %324, %32, implicit $exec
+    %326:vgpr_32 = V_SUB_U32_e64 %33, killed %325, 0, implicit $exec
+    %327:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 %326, %32, implicit $exec
+    %329:vgpr_32 = V_ADD_U32_e64 1, %324, 0, implicit $exec
+    %330:vgpr_32 = V_CNDMASK_B32_e64 0, killed %324, 0, killed %329, %327, implicit $exec
+    %331:vgpr_32 = V_SUB_U32_e64 %326, %32, 0, implicit $exec
+    %332:vgpr_32 = V_CNDMASK_B32_e64 0, killed %326, 0, killed %331, killed %327, implicit $exec
+    %333:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 killed %332, %32, implicit $exec
+    %334:vgpr_32 = V_ADD_U32_e64 1, %330, 0, implicit $exec
+    %62:vgpr_32 = V_CNDMASK_B32_e64 0, killed %330, 0, killed %334, killed %333, implicit $exec
+    %63:vgpr_32 = V_ADD_U32_e64 1, %33, 0, implicit $exec
+    %335:sreg_32 = V_CMP_GE_U32_e64 %63, %240, implicit $exec
+    %545:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+    %546:sreg_32 = S_ORN2_B32 killed %335, $exec_lo, implicit-def dead $scc
+    S_BRANCH %bb.5
+  
+  bb.10:
+    successors: %bb.11(0x40000000), %bb.12(0x40000000)
+  
+    %67:sreg_32 = PHI %368, %bb.38, %549, %bb.14
+    %65:vgpr_32 = PHI undef %365:vgpr_32, %bb.38, %91, %bb.14
+    %66:sreg_32 = PHI undef %366:sreg_32, %bb.38, %370, %bb.14
+    %379:sreg_32 = S_MOV_B32 -1
+    %68:sreg_32 = SI_ELSE killed %226, %bb.12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.11
+  
+  bb.11:
+    successors: %bb.13(0x40000000), %bb.15(0x40000000)
+  
+    %69:vgpr_32 = V_MUL_LO_U32_e64 killed %212, killed %213, implicit $exec
+    GLOBAL_STORE_DWORD %516, %69, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+    %70:vgpr_32 = V_MUL_LO_U32_e64 %215, killed %214, implicit $exec
+    %384:sreg_32 = V_CMP_LT_U32_e64 %69, %244, implicit $exec
+    %385:sreg_32 = S_MOV_B32 0
+    %71:sreg_32 = SI_IF killed %384, %bb.15, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.13
+  
+  bb.12:
+    successors: %bb.16(0x40000000), %bb.17(0x40000000)
+  
+    %85:sreg_32 = PHI %67, %bb.10, %557, %bb.15
+    %84:sreg_32 = PHI %368, %bb.10, %555, %bb.15
+    %83:sreg_32 = PHI %66, %bb.10, %552, %bb.15
+    %75:sreg_32 = PHI %379, %bb.10, %551, %bb.15
+    %74:sreg_32 = PHI %368, %bb.10, %550, %bb.15
+    %72:vgpr_32 = PHI %2, %bb.10, %92, %bb.15
+    %73:vgpr_32 = PHI %3, %bb.10, %70, %bb.15
+    %76:vgpr_32 = PHI undef %377:vgpr_32, %bb.10, %93, %bb.15
+    %77:vgpr_32 = PHI undef %377:vgpr_32, %bb.10, %94, %bb.15
+    %78:vgpr_32 = PHI undef %377:vgpr_32, %bb.10, %95, %bb.15
+    %79:vgpr_32 = PHI undef %377:vgpr_32, %bb.10, %96, %bb.15
+    %80:vgpr_32 = PHI undef %377:vgpr_32, %bb.10, %97, %bb.15
+    %81:vgpr_32 = PHI undef %378:vgpr_32, %bb.10, %70, %bb.15
+    %82:vgpr_32 = PHI %65, %bb.10, %98, %bb.15
+    SI_END_CF killed %68, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %400:sreg_32 = S_MOV_B32 0
+    %86:sreg_32 = SI_IF killed %85, %bb.17, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.16
+  
+  bb.13:
+    successors: %bb.15(0x80000000)
+  
+    %87:vgpr_32 = GLOBAL_LOAD_DWORD %514, 0, 0, implicit $exec :: (load (s32) from %ir.p3, addrspace 1)
+    %88:vgpr_32 = V_MUL_LO_U32_e64 %87, %6, implicit $exec
+    GLOBAL_STORE_DWORD %515, %69, 0, 0, implicit $exec :: (store (s32) into %ir.p4, addrspace 1)
+    %388:sreg_32 = V_CMP_LT_U32_e64 %88, %69, implicit $exec
+    %389:sreg_32 = V_CMP_GE_U32_e64 %88, killed %69, implicit $exec
+    %561:sreg_32 = COPY $exec_lo
+    %563:sreg_32 = S_ANDN2_B32 %67, $exec_lo, implicit-def dead $scc
+    %564:sreg_32 = S_AND_B32 killed %389, $exec_lo, implicit-def dead $scc
+    %562:sreg_32 = S_OR_B32 killed %563, killed %564, implicit-def dead $scc
+    S_BRANCH %bb.15
+  
+  bb.14:
+    successors: %bb.10(0x80000000)
+  
+    %371:vgpr_32 = GLOBAL_LOAD_USHORT %515, 0, 0, implicit $exec :: (load (s16) from %ir.p4, addrspace 1)
+    %372:vgpr_32 = GLOBAL_LOAD_USHORT %515, 2, 0, implicit $exec :: (load (s16) from %ir.p4 + 2, addrspace 1)
+    %91:vgpr_32 = V_LSHL_OR_B32_e64 killed %372, 16, killed %371, implicit $exec
+    %374:vgpr_32 = V_MUL_LO_U32_e64 %91, killed %59, implicit $exec
+    GLOBAL_STORE_DWORD %514, killed %374, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    %370:sreg_32 = S_MOV_B32 -1
+    %549:sreg_32 = COPY $exec_lo
+    S_BRANCH %bb.10
+  
+  bb.15:
+    successors: %bb.12(0x80000000)
+  
+    %101:sreg_32 = PHI %67, %bb.11, %562, %bb.13
+    %100:sreg_32 = PHI %385, %bb.11, %561, %bb.13
+    %99:sreg_32 = PHI undef %560:sreg_32, %bb.11, %388, %bb.13
+    %92:vgpr_32 = PHI %2, %bb.11, %88, %bb.13
+    %93:vgpr_32 = PHI %4, %bb.11, undef %386:vgpr_32, %bb.13
+    %94:vgpr_32 = PHI %5, %bb.11, undef %386:vgpr_32, %bb.13
+    %95:vgpr_32 = PHI %6, %bb.11, undef %386:vgpr_32, %bb.13
+    %96:vgpr_32 = PHI %7, %bb.11, undef %386:vgpr_32, %bb.13
+    %97:vgpr_32 = PHI %8, %bb.11, undef %386:vgpr_32, %bb.13
+    %98:vgpr_32 = PHI undef %381:vgpr_32, %bb.11, %87, %bb.13
+    SI_END_CF killed %71, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %550:sreg_32 = COPY $exec_lo
+    %551:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+    %553:sreg_32 = S_ANDN2_B32 killed %66, $exec_lo, implicit-def dead $scc
+    %554:sreg_32 = S_AND_B32 killed %99, $exec_lo, implicit-def dead $scc
+    %552:sreg_32 = S_OR_B32 killed %553, killed %554, implicit-def dead $scc
+    %556:sreg_32 = S_AND_B32 killed %100, $exec_lo, implicit-def dead $scc
+    %555:sreg_32 = COPY killed %556
+    %558:sreg_32 = S_ANDN2_B32 killed %67, $exec_lo, implicit-def dead $scc
+    %559:sreg_32 = S_AND_B32 killed %101, $exec_lo, implicit-def dead $scc
+    %557:sreg_32 = S_OR_B32 killed %558, killed %559, implicit-def dead $scc
+    S_BRANCH %bb.12
+  
+  bb.16:
+    successors: %bb.18(0x40000000), %bb.23(0x40000000)
+  
+    %406:sreg_32 = S_MOV_B32 -1
+    %407:sreg_32 = S_XOR_B32 killed %83, -1, implicit-def dead $scc
+    %409:vgpr_32 = GLOBAL_LOAD_UBYTE %516, 0, 0, implicit $exec :: (load (s8) from %ir.p5, addrspace 1)
+    %410:vgpr_32 = GLOBAL_LOAD_UBYTE %516, 1, 0, implicit $exec :: (load (s8) from %ir.p5 + 1, addrspace 1)
+    %412:vgpr_32 = V_LSHL_OR_B32_e64 killed %410, 8, killed %409, implicit $exec
+    %413:vgpr_32 = GLOBAL_LOAD_UBYTE %516, 2, 0, implicit $exec :: (load (s8) from %ir.p5 + 2, addrspace 1)
+    %414:vgpr_32 = GLOBAL_LOAD_UBYTE %516, 3, 0, implicit $exec :: (load (s8) from %ir.p5 + 3, addrspace 1)
+    %415:vgpr_32 = V_LSHL_OR_B32_e64 killed %414, 8, killed %413, implicit $exec
+    %417:vgpr_32 = V_LSHL_OR_B32_e64 killed %415, 16, killed %412, implicit $exec
+    %102:vgpr_32 = V_MUL_LO_U32_e64 killed %417, %82, implicit $exec
+    GLOBAL_STORE_SHORT_D16_HI %513, %102, 2, 0, implicit $exec :: (store (s16) into %ir.p2 + 2, addrspace 1)
+    GLOBAL_STORE_SHORT %513, %102, 0, 0, implicit $exec :: (store (s16) into %ir.p2, addrspace 1)
+    %418:sreg_32 = S_MOV_B32 0
+    %103:sreg_32 = SI_IF killed %407, %bb.23, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.18
+  
+  bb.17:
+    successors: %bb.20(0x40000000), %bb.33(0x40000000)
+  
+    %119:sreg_32 = PHI %84, %bb.12, %574, %bb.19
+    %118:sreg_32 = PHI %379, %bb.12, %573, %bb.19
+    %111:sreg_32 = PHI %75, %bb.12, %570, %bb.19
+    %110:sreg_32 = PHI %74, %bb.12, %567, %bb.19
+    %109:sreg_32 = PHI %400, %bb.12, %565, %bb.19
+    %104:vgpr_32 = PHI undef %395:vgpr_32, %bb.12, %123, %bb.19
+    %105:vgpr_32 = PHI undef %395:vgpr_32, %bb.12, %124, %bb.19
+    %106:vgpr_32 = PHI undef %395:vgpr_32, %bb.12, %125, %bb.19
+    %107:vgpr_32 = PHI undef %395:vgpr_32, %bb.12, %126, %bb.19
+    %108:vgpr_32 = PHI undef %395:vgpr_32, %bb.12, %127, %bb.19
+    %112:vgpr_32 = PHI undef %397:vgpr_32, %bb.12, %131, %bb.19
+    %113:vgpr_32 = PHI %76, %bb.12, %132, %bb.19
+    %114:vgpr_32 = PHI %77, %bb.12, %133, %bb.19
+    %115:vgpr_32 = PHI %78, %bb.12, %134, %bb.19
+    %116:vgpr_32 = PHI %79, %bb.12, %135, %bb.19
+    %117:vgpr_32 = PHI %80, %bb.12, %136, %bb.19
+    SI_END_CF killed %86, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %120:sreg_32 = SI_IF killed %119, %bb.33, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.20
+  
+  bb.18:
+    successors: %bb.24(0x40000000), %bb.21(0x40000000)
+  
+    %422:vgpr_32 = GLOBAL_LOAD_UBYTE %517, 0, 0, implicit $exec :: (load (s8) from %ir.p6, addrspace 1)
+    %423:vgpr_32 = GLOBAL_LOAD_UBYTE %517, 1, 0, implicit $exec :: (load (s8) from %ir.p6 + 1, addrspace 1)
+    %425:vgpr_32 = V_LSHL_OR_B32_e64 killed %423, 8, killed %422, implicit $exec
+    %426:vgpr_32 = GLOBAL_LOAD_UBYTE %517, 2, 0, implicit $exec :: (load (s8) from %ir.p6 + 2, addrspace 1)
+    %427:vgpr_32 = GLOBAL_LOAD_UBYTE %517, 3, 0, implicit $exec :: (load (s8) from %ir.p6 + 3, addrspace 1)
+    %428:vgpr_32 = V_LSHL_OR_B32_e64 killed %427, 8, killed %426, implicit $exec
+    %430:vgpr_32 = V_LSHL_OR_B32_e64 killed %428, 16, killed %425, implicit $exec
+    %121:vgpr_32 = V_MUL_LO_U32_e64 killed %430, %6, implicit $exec
+    GLOBAL_STORE_BYTE %517, %121, 0, 0, implicit $exec :: (store (s8) into %ir.p6, addrspace 1)
+    GLOBAL_STORE_BYTE_D16_HI %517, %121, 2, 0, implicit $exec :: (store (s8) into %ir.p6 + 2, addrspace 1)
+    %431:vgpr_32 = V_LSHRREV_B32_e64 8, %121, implicit $exec
+    GLOBAL_STORE_BYTE %517, killed %431, 1, 0, implicit $exec :: (store (s8) into %ir.p6 + 1, addrspace 1)
+    %433:vgpr_32 = V_LSHRREV_B32_e64 24, %121, implicit $exec
+    GLOBAL_STORE_BYTE %517, killed %433, 3, 0, implicit $exec :: (store (s8) into %ir.p6 + 3, addrspace 1)
+    %434:sreg_32 = V_CMP_LT_U32_e64 %121, killed %82, implicit $exec
+    %435:sreg_32 = S_MOV_B32 -1
+    %122:sreg_32 = SI_IF killed %434, %bb.21, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.24
+  
+  bb.19:
+    successors: %bb.17(0x80000000)
+  
+    %137:sreg_32 = PHI %162, %bb.23, %582, %bb.22
+    %130:sreg_32 = PHI %155, %bb.23, %580, %bb.22
+    %129:sreg_32 = PHI %154, %bb.23, %578, %bb.22
+    %128:sreg_32 = PHI %153, %bb.23, %576, %bb.22
+    %123:vgpr_32 = PHI %149, %bb.23, %215, %bb.22
+    %124:vgpr_32 = PHI %150, %bb.23, %629, %bb.22
+    %125:vgpr_32 = PHI %151, %bb.23, %5, %bb.22
+    %126:vgpr_32 = PHI %152, %bb.23, %147, %bb.22
+    %127:vgpr_32 = PHI %152, %bb.23, %5, %bb.22
+    %131:vgpr_32 = PHI %156, %bb.23, %147, %bb.22
+    %132:vgpr_32 = PHI %157, %bb.23, %4, %bb.22
+    %133:vgpr_32 = PHI %158, %bb.23, %5, %bb.22
+    %134:vgpr_32 = PHI %159, %bb.23, %6, %bb.22
+    %135:vgpr_32 = PHI %160, %bb.23, %7, %bb.22
+    %136:vgpr_32 = PHI %161, %bb.23, %8, %bb.22
+    SI_END_CF killed %163, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %566:sreg_32 = S_AND_B32 killed %128, $exec_lo, implicit-def dead $scc
+    %565:sreg_32 = COPY killed %566
+    %568:sreg_32 = S_ANDN2_B32 killed %74, $exec_lo, implicit-def dead $scc
+    %569:sreg_32 = S_AND_B32 killed %129, $exec_lo, implicit-def dead $scc
+    %567:sreg_32 = S_OR_B32 killed %568, killed %569, implicit-def dead $scc
+    %571:sreg_32 = S_ANDN2_B32 killed %75, $exec_lo, implicit-def dead $scc
+    %572:sreg_32 = S_AND_B32 killed %130, $exec_lo, implicit-def dead $scc
+    %570:sreg_32 = S_OR_B32 killed %571, killed %572, implicit-def dead $scc
+    %573:sreg_32 = S_ORN2_B32 killed %137, $exec_lo, implicit-def dead $scc
+    %575:sreg_32 = S_ANDN2_B32 killed %84, $exec_lo, implicit-def dead $scc
+    %574:sreg_32 = COPY killed %575
+    S_BRANCH %bb.17
+  
+  bb.20:
+    successors: %bb.33(0x80000000)
+  
+    %138:vgpr_32 = V_ADD_U32_e64 1, %4, 0, implicit $exec
+    %451:sreg_32 = V_CMP_GE_U32_e64 %138, %241, implicit $exec
+    %595:sreg_32 = S_ANDN2_B32 killed %109, $exec_lo, implicit-def dead $scc
+    %594:sreg_32 = COPY killed %595
+    %597:sreg_32 = S_ANDN2_B32 killed %110, $exec_lo, implicit-def dead $scc
+    %596:sreg_32 = COPY killed %597
+    %599:sreg_32 = S_ANDN2_B32 killed %111, $exec_lo, implicit-def dead $scc
+    %598:sreg_32 = COPY killed %599
+    %601:sreg_32 = S_ANDN2_B32 killed %118, $exec_lo, implicit-def dead $scc
+    %602:sreg_32 = S_AND_B32 killed %451, $exec_lo, implicit-def dead $scc
+    %600:sreg_32 = S_OR_B32 killed %601, killed %602, implicit-def dead $scc
+    S_BRANCH %bb.33
+  
+  bb.21:
+    successors: %bb.23(0x80000000)
+  
+    %146:sreg_32 = PHI %435, %bb.18, %586, %bb.24
+    %144:sreg_32 = PHI %435, %bb.18, %585, %bb.24
+    %140:vgpr_32 = PHI undef %419:vgpr_32, %bb.18, %7, %bb.24
+    %141:vgpr_32 = PHI undef %419:vgpr_32, %bb.18, %121, %bb.24
+    %142:vgpr_32 = PHI undef %419:vgpr_32, %bb.18, %164, %bb.24
+    %143:vgpr_32 = PHI undef %419:vgpr_32, %bb.18, %6, %bb.24
+    %145:vgpr_32 = PHI undef %421:vgpr_32, %bb.18, %164, %bb.24
+    SI_END_CF killed %122, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %588:sreg_32 = S_AND_B32 killed %144, $exec_lo, implicit-def dead $scc
+    %587:sreg_32 = COPY killed %588
+    %590:sreg_32 = S_ANDN2_B32 %74, $exec_lo, implicit-def dead $scc
+    %589:sreg_32 = COPY killed %590
+    %592:sreg_32 = S_ANDN2_B32 %75, $exec_lo, implicit-def dead $scc
+    %591:sreg_32 = COPY killed %592
+    %593:sreg_32 = S_ORN2_B32 killed %146, $exec_lo, implicit-def dead $scc
+    S_BRANCH %bb.23
+  
+  bb.22:
+    successors: %bb.19(0x80000000)
+  
+    %147:vgpr_32 = V_ADD_U32_e64 1, %5, 0, implicit $exec
+    %444:sreg_32 = V_CMP_GE_U32_e64 %147, %242, implicit $exec
+    %577:sreg_32 = S_ANDN2_B32 killed %153, $exec_lo, implicit-def dead $scc
+    %576:sreg_32 = COPY killed %577
+    %579:sreg_32 = S_ANDN2_B32 killed %154, $exec_lo, implicit-def dead $scc
+    %578:sreg_32 = COPY killed %579
+    %581:sreg_32 = S_ANDN2_B32 killed %155, $exec_lo, implicit-def dead $scc
+    %580:sreg_32 = COPY killed %581
+    %583:sreg_32 = S_ANDN2_B32 killed %162, $exec_lo, implicit-def dead $scc
+    %584:sreg_32 = S_AND_B32 killed %444, $exec_lo, implicit-def dead $scc
+    %582:sreg_32 = S_OR_B32 killed %583, killed %584, implicit-def dead $scc
+    S_BRANCH %bb.19
+  
+  bb.23:
+    successors: %bb.22(0x40000000), %bb.19(0x40000000)
+  
+    %162:sreg_32 = PHI %406, %bb.16, %593, %bb.21
+    %155:sreg_32 = PHI %75, %bb.16, %591, %bb.21
+    %154:sreg_32 = PHI %74, %bb.16, %589, %bb.21
+    %153:sreg_32 = PHI %418, %bb.16, %587, %bb.21
+    %149:vgpr_32 = PHI undef %402:vgpr_32, %bb.16, %140, %bb.21
+    %150:vgpr_32 = PHI undef %402:vgpr_32, %bb.16, %141, %bb.21
+    %151:vgpr_32 = PHI undef %402:vgpr_32, %bb.16, %142, %bb.21
+    %152:vgpr_32 = PHI undef %402:vgpr_32, %bb.16, %143, %bb.21
+    %156:vgpr_32 = PHI undef %404:vgpr_32, %bb.16, %145, %bb.21
+    %157:vgpr_32 = PHI undef %402:vgpr_32, %bb.16, %4, %bb.21
+    %158:vgpr_32 = PHI undef %402:vgpr_32, %bb.16, %5, %bb.21
+    %159:vgpr_32 = PHI undef %402:vgpr_32, %bb.16, %6, %bb.21
+    %160:vgpr_32 = PHI undef %402:vgpr_32, %bb.16, %7, %bb.21
+    %161:vgpr_32 = PHI undef %402:vgpr_32, %bb.16, %8, %bb.21
+    %629:vgpr_32 = PHI %102, %bb.16, undef %630:vgpr_32, %bb.21
+    %163:sreg_32 = SI_ELSE killed %103, %bb.19, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.22
+  
+  bb.24:
+    successors: %bb.21(0x80000000)
+  
+    %164:vgpr_32 = V_ADD_U32_e64 1, %6, 0, implicit $exec
+    %438:sreg_32 = V_CMP_GE_U32_e64 %164, %243, implicit $exec
+    %585:sreg_32 = S_XOR_B32 $exec_lo, -1, implicit-def dead $scc
+    %586:sreg_32 = S_ORN2_B32 killed %438, $exec_lo, implicit-def dead $scc
+    S_BRANCH %bb.21
+  
+  bb.25:
+    successors: %bb.26(0x40000000), %bb.32(0x40000000)
+  
+    %166:vgpr_32 = PHI undef %454:vgpr_32, %bb.34, %174, %bb.31
+    %631:vreg_64 = PHI %514, %bb.34, undef %632:vreg_64, %bb.31
+    %633:vreg_64 = PHI %515, %bb.34, undef %634:vreg_64, %bb.31
+    %167:sreg_32 = SI_ELSE killed %204, %bb.32, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.26
+  
+  bb.26:
+    successors: %bb.32(0x80000000)
+  
+    %493:vgpr_32 = GLOBAL_LOAD_UBYTE %631, 0, 0, implicit $exec :: (load (s8) from %ir.p3, addrspace 1)
+    %494:vgpr_32 = GLOBAL_LOAD_UBYTE %631, 1, 0, implicit $exec :: (load (s8) from %ir.p3 + 1, addrspace 1)
+    %496:vgpr_32 = V_LSHL_OR_B32_e64 killed %494, 8, killed %493, implicit $exec
+    %497:vgpr_32 = GLOBAL_LOAD_UBYTE %631, 2, 0, implicit $exec :: (load (s8) from %ir.p3 + 2, addrspace 1)
+    %498:vgpr_32 = GLOBAL_LOAD_UBYTE killed %631, 3, 0, implicit $exec :: (load (s8) from %ir.p3 + 3, addrspace 1)
+    %499:vgpr_32 = V_LSHL_OR_B32_e64 killed %498, 8, killed %497, implicit $exec
+    %501:vgpr_32 = V_LSHL_OR_B32_e64 killed %499, 16, killed %496, implicit $exec
+    %168:vgpr_32 = V_ADD3_U32_e64 killed %501, killed %23, killed %26, implicit $exec
+    GLOBAL_STORE_BYTE_D16_HI %633, %168, 2, 0, implicit $exec :: (store (s8) into %ir.p4 + 2, addrspace 1)
+    GLOBAL_STORE_BYTE %633, %168, 0, 0, implicit $exec :: (store (s8) into %ir.p4, addrspace 1)
+    %503:vgpr_32 = V_LSHRREV_B32_e64 24, %168, implicit $exec
+    GLOBAL_STORE_BYTE %633, killed %503, 3, 0, implicit $exec :: (store (s8) into %ir.p4 + 3, addrspace 1)
+    %504:vgpr_32 = V_LSHRREV_B32_e64 8, %168, implicit $exec
+    GLOBAL_STORE_BYTE killed %633, killed %504, 1, 0, implicit $exec :: (store (s8) into %ir.p4 + 1, addrspace 1)
+    S_BRANCH %bb.32
+  
+  bb.27:
+    successors: %bb.28(0x40000000), %bb.31(0x40000000)
+  
+    %169:vgpr_32 = PHI undef %460:vgpr_32, %bb.35, %173, %bb.30
+    %635:vreg_64 = PHI %515, %bb.35, undef %636:vreg_64, %bb.30
+    %637:vreg_64 = PHI %514, %bb.35, undef %638:vreg_64, %bb.30
+    %170:sreg_32 = SI_ELSE killed %205, %bb.31, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.28
+  
+  bb.28:
+    successors: %bb.31(0x80000000)
+  
+    %476:vgpr_32 = GLOBAL_LOAD_UBYTE %635, 0, 0, implicit $exec :: (load (s8) from %ir.p4, addrspace 1)
+    %477:vgpr_32 = GLOBAL_LOAD_UBYTE %635, 1, 0, implicit $exec :: (load (s8) from %ir.p4 + 1, addrspace 1)
+    %479:vgpr_32 = V_LSHL_OR_B32_e64 killed %477, 8, killed %476, implicit $exec
+    %480:vgpr_32 = GLOBAL_LOAD_UBYTE %635, 2, 0, implicit $exec :: (load (s8) from %ir.p4 + 2, addrspace 1)
+    %481:vgpr_32 = GLOBAL_LOAD_UBYTE killed %635, 3, 0, implicit $exec :: (load (s8) from %ir.p4 + 3, addrspace 1)
+    %482:vgpr_32 = V_LSHL_OR_B32_e64 killed %481, 8, killed %480, implicit $exec
+    %484:vgpr_32 = V_LSHL_OR_B32_e64 killed %482, 16, killed %479, implicit $exec
+    %510:vreg_64 = REG_SEQUENCE killed %28, %subreg.sub0, undef %511:vgpr_32, %subreg.sub1
+    %488:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 killed %484, killed %24, killed %510, 0, implicit $exec
+    %171:vgpr_32 = COPY %488.sub0
+    GLOBAL_STORE_BYTE_D16_HI %637, %488.sub0, 2, 0, implicit $exec :: (store (s8) into %ir.p3 + 2, addrspace 1)
+    GLOBAL_STORE_BYTE %637, %488.sub0, 0, 0, implicit $exec :: (store (s8) into %ir.p3, addrspace 1)
+    %491:vgpr_32 = V_LSHRREV_B32_e64 24, %488.sub0, implicit $exec
+    GLOBAL_STORE_BYTE %637, killed %491, 3, 0, implicit $exec :: (store (s8) into %ir.p3 + 3, addrspace 1)
+    %492:vgpr_32 = V_LSHRREV_B32_e64 8, killed %488.sub0, implicit $exec
+    GLOBAL_STORE_BYTE killed %637, killed %492, 1, 0, implicit $exec :: (store (s8) into %ir.p3 + 1, addrspace 1)
+    S_BRANCH %bb.31
+  
+  bb.29:
+    successors: %bb.30(0x80000000)
+  
+    %463:vgpr_32 = GLOBAL_LOAD_UBYTE %516, 0, 0, implicit $exec :: (load (s8) from %ir.p5, addrspace 1)
+    %464:vgpr_32 = GLOBAL_LOAD_UBYTE %516, 1, 0, implicit $exec :: (load (s8) from %ir.p5 + 1, addrspace 1)
+    %466:vgpr_32 = V_LSHL_OR_B32_e64 killed %464, 8, killed %463, implicit $exec
+    %467:vgpr_32 = GLOBAL_LOAD_UBYTE %516, 2, 0, implicit $exec :: (load (s8) from %ir.p5 + 2, addrspace 1)
+    %468:vgpr_32 = GLOBAL_LOAD_UBYTE killed %516, 3, 0, implicit $exec :: (load (s8) from %ir.p5 + 3, addrspace 1)
+    %469:vgpr_32 = V_LSHL_OR_B32_e64 killed %468, 8, killed %467, implicit $exec
+    %471:vgpr_32 = V_LSHL_OR_B32_e64 killed %469, 16, killed %466, implicit $exec
+    %472:vgpr_32 = V_SUB_U32_e64 killed %471, killed %25, 0, implicit $exec
+    %172:vgpr_32 = V_ADD_U32_e64 killed %472, killed %27, 0, implicit $exec
+    GLOBAL_STORE_BYTE_D16_HI %513, %172, 2, 0, implicit $exec :: (store (s8) into %ir.p2 + 2, addrspace 1)
+    GLOBAL_STORE_BYTE %513, %172, 0, 0, implicit $exec :: (store (s8) into %ir.p2, addrspace 1)
+    %474:vgpr_32 = V_LSHRREV_B32_e64 24, %172, implicit $exec
+    GLOBAL_STORE_BYTE %513, killed %474, 3, 0, implicit $exec :: (store (s8) into %ir.p2 + 3, addrspace 1)
+    %475:vgpr_32 = V_LSHRREV_B32_e64 8, %172, implicit $exec
+    GLOBAL_STORE_BYTE killed %513, killed %475, 1, 0, implicit $exec :: (store (s8) into %ir.p2 + 1, addrspace 1)
+  
+  bb.30:
+    successors: %bb.27(0x80000000)
+  
+    %173:vgpr_32 = PHI %22, %bb.36, %172, %bb.29
+    SI_END_CF killed %206, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.27
+  
+  bb.31:
+    successors: %bb.25(0x80000000)
+  
+    %174:vgpr_32 = PHI %169, %bb.27, %171, %bb.28
+    SI_END_CF killed %170, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.25
+  
+  bb.32:
+    %175:vgpr_32 = PHI %166, %bb.25, %168, %bb.26
+    SI_END_CF killed %167, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %506:vgpr_32 = V_ADD3_U32_e64 killed %0, killed %175, 100, implicit $exec
+    %507:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %506, implicit $exec
+    $sgpr0 = COPY killed %507
+    SI_RETURN_TO_EPILOG killed $sgpr0
+  
+  bb.33:
+    successors: %bb.3(0x80000000)
+  
+    %191:sreg_32 = PHI %118, %bb.17, %600, %bb.20
+    %183:sreg_32 = PHI %111, %bb.17, %598, %bb.20
+    %182:sreg_32 = PHI %110, %bb.17, %596, %bb.20
+    %181:sreg_32 = PHI %109, %bb.17, %594, %bb.20
+    %176:vgpr_32 = PHI %104, %bb.17, %73, %bb.20
+    %177:vgpr_32 = PHI %105, %bb.17, %72, %bb.20
+    %178:vgpr_32 = PHI %106, %bb.17, %4, %bb.20
+    %179:vgpr_32 = PHI %107, %bb.17, %4, %bb.20
+    %180:vgpr_32 = PHI %108, %bb.17, %138, %bb.20
+    %184:vgpr_32 = PHI %112, %bb.17, %138, %bb.20
+    %185:vgpr_32 = PHI %113, %bb.17, %4, %bb.20
+    %186:vgpr_32 = PHI %114, %bb.17, %5, %bb.20
+    %187:vgpr_32 = PHI %115, %bb.17, %6, %bb.20
+    %188:vgpr_32 = PHI %116, %bb.17, %7, %bb.20
+    %189:vgpr_32 = PHI %117, %bb.17, %8, %bb.20
+    %190:vgpr_32 = PHI %81, %bb.17, %73, %bb.20
+    SI_END_CF killed %120, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %524:sreg_32 = S_ANDN2_B32 killed %523, $exec_lo, implicit-def dead $scc
+    %525:sreg_32 = S_AND_B32 killed %181, $exec_lo, implicit-def dead $scc
+    %521:sreg_32 = S_OR_B32 killed %524, killed %525, implicit-def dead $scc
+    %531:sreg_32 = S_ANDN2_B32 killed %530, $exec_lo, implicit-def dead $scc
+    %532:sreg_32 = S_AND_B32 killed %182, $exec_lo, implicit-def dead $scc
+    %528:sreg_32 = S_OR_B32 killed %531, killed %532, implicit-def dead $scc
+    %537:sreg_32 = S_ANDN2_B32 killed %534, $exec_lo, implicit-def dead $scc
+    %538:sreg_32 = S_AND_B32 killed %183, $exec_lo, implicit-def dead $scc
+    %535:sreg_32 = S_OR_B32 killed %537, killed %538, implicit-def dead $scc
+    %543:sreg_32 = S_ANDN2_B32 killed %540, $exec_lo, implicit-def dead $scc
+    %544:sreg_32 = S_AND_B32 killed %191, $exec_lo, implicit-def dead $scc
+    %541:sreg_32 = S_OR_B32 killed %543, killed %544, implicit-def dead $scc
+    S_BRANCH %bb.3
+  
+  bb.34:
+    successors: %bb.35(0x40000000), %bb.25(0x40000000)
+  
+    SI_END_CF killed %30, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %456:sreg_32 = S_XOR_B32 killed %194, -1, implicit-def dead $scc
+    %458:sreg_32 = S_XOR_B32 killed %193, -1, implicit-def dead $scc
+    %204:sreg_32 = SI_IF killed %456, %bb.25, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.35
+  
+  bb.35:
+    successors: %bb.36(0x40000000), %bb.27(0x40000000)
+  
+    %205:sreg_32 = SI_IF killed %458, %bb.27, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.36
+  
+  bb.36:
+    successors: %bb.29(0x40000000), %bb.30(0x40000000)
+  
+    %206:sreg_32 = SI_IF killed %192, %bb.30, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.29
+  
+  bb.37:
+    successors: %bb.38(0x04000000), %bb.4(0x7c000000)
+  
+    %216:sreg_32 = PHI %60, %bb.8, %616, %bb.6
+    %211:sreg_32 = PHI %54, %bb.8, %615, %bb.6
+    %207:vgpr_32 = PHI %50, %bb.8, %44, %bb.6
+    %208:vgpr_32 = PHI %51, %bb.8, %46, %bb.6
+    %209:vgpr_32 = PHI %52, %bb.8, %32, %bb.6
+    %210:vgpr_32 = PHI %53, %bb.8, %45, %bb.6
+    %212:vgpr_32 = PHI %55, %bb.8, %32, %bb.6
+    %213:vgpr_32 = PHI %56, %bb.8, %33, %bb.6
+    %214:vgpr_32 = PHI %57, %bb.8, %34, %bb.6
+    %215:vgpr_32 = PHI %58, %bb.8, %35, %bb.6
+    SI_END_CF killed %61, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %362:sreg_32 = S_XOR_B32 killed %211, -1, implicit-def dead $scc
+    %218:sreg_32 = SI_IF_BREAK killed %216, killed %31, implicit-def dead $scc
+    %621:sreg_32 = S_ANDN2_B32 killed %620, $exec_lo, implicit-def dead $scc
+    %622:sreg_32 = S_AND_B32 killed %362, $exec_lo, implicit-def dead $scc
+    %223:sreg_32 = S_OR_B32 killed %621, killed %622, implicit-def dead $scc
+    SI_LOOP %218, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.38
+  
+  bb.38:
+    successors: %bb.14(0x40000000), %bb.10(0x40000000)
+  
+    SI_END_CF killed %218, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %368:sreg_32 = S_MOV_B32 0
+    %226:sreg_32 = SI_IF killed %223, %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.14
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
new file mode 100644
index 0000000000000..6d1a5f530e483
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
@@ -0,0 +1,1314 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#       bb.0.entry
+#           |
+#           +<--------+
+#       bb.1.loop1    |
+#           +---------+
+#           |
+#        bb.2.bb
+#           |
+#           +<--------+
+#       bb.3.loop2    |
+#           +---------+
+#           |
+#       bb.4.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test6 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 53 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 52 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 51 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 50 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 49 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 48 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Instr: %8:vreg_64 = REG_SEQUENCE killed %3, %subreg.sub0, killed %2, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Instr: %9:vreg_64 = REG_SEQUENCE killed %5, %subreg.sub0, killed %4, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %8:sub0[ 24 ]
+# CHECK: Vreg: %8:sub1[ 25 ]
+# CHECK: Vreg: %8[ 42 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %10:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, killed %6, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 44 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %9:sub0[ 15 ]
+# CHECK: Vreg: %9:sub1[ 16 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %8:sub0[ 23 ]
+# CHECK: Vreg: %8:sub1[ 24 ]
+# CHECK: Vreg: %8[ 41 ]
+# CHECK: Instr: %11:vgpr_32 = GLOBAL_LOAD_UBYTE %10, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Vreg: %9:sub0[ 14 ]
+# CHECK: Vreg: %9:sub1[ 15 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %8:sub0[ 22 ]
+# CHECK: Vreg: %8:sub1[ 23 ]
+# CHECK: Vreg: %8[ 40 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %12:vgpr_32 = GLOBAL_LOAD_UBYTE %10, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 42 ]
+# CHECK: Vreg: %9:sub0[ 13 ]
+# CHECK: Vreg: %9:sub1[ 14 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %8:sub0[ 21 ]
+# CHECK: Vreg: %8:sub1[ 22 ]
+# CHECK: Vreg: %8[ 39 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %13:vgpr_32 = V_LSHL_OR_B32_e64 killed %12, 8, killed %11, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %9:sub0[ 12 ]
+# CHECK: Vreg: %9:sub1[ 13 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %8:sub0[ 20 ]
+# CHECK: Vreg: %8:sub1[ 21 ]
+# CHECK: Vreg: %8[ 38 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %14:vgpr_32 = GLOBAL_LOAD_UBYTE %10, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %9:sub0[ 11 ]
+# CHECK: Vreg: %9:sub1[ 12 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %8:sub0[ 19 ]
+# CHECK: Vreg: %8:sub1[ 20 ]
+# CHECK: Vreg: %8[ 37 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %15:vgpr_32 = GLOBAL_LOAD_UBYTE %10, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 39 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %9:sub0[ 10 ]
+# CHECK: Vreg: %9:sub1[ 11 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %8:sub0[ 18 ]
+# CHECK: Vreg: %8:sub1[ 19 ]
+# CHECK: Vreg: %8[ 36 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %16:vgpr_32 = V_LSHL_OR_B32_e64 killed %15, 8, killed %14, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 38 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %9:sub0[ 9 ]
+# CHECK: Vreg: %9:sub1[ 10 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %8:sub0[ 17 ]
+# CHECK: Vreg: %8:sub1[ 18 ]
+# CHECK: Vreg: %8[ 35 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %10[ 15 ]
+# CHECK: Instr: %17:vgpr_32 = V_LSHL_OR_B32_e64 killed %16, 16, killed %13, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %9:sub0[ 8 ]
+# CHECK: Vreg: %9:sub1[ 9 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %8:sub0[ 16 ]
+# CHECK: Vreg: %8:sub1[ 17 ]
+# CHECK: Vreg: %8[ 34 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Instr: %18:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %9:sub0[ 7 ]
+# CHECK: Vreg: %9:sub1[ 8 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %8:sub0[ 15 ]
+# CHECK: Vreg: %8:sub1[ 16 ]
+# CHECK: Vreg: %8[ 33 ]
+# CHECK: Vreg: %10[ 13 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Instr: %19:sreg_32 = S_MOV_B32 1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %9:sub0[ 6 ]
+# CHECK: Vreg: %9:sub1[ 7 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %8:sub0[ 14 ]
+# CHECK: Vreg: %8:sub1[ 15 ]
+# CHECK: Vreg: %8[ 32 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Instr: %20:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %8[ 31 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %8[ 31 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %21:sreg_32 = PHI %20, %bb.0, %22, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+34 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %8[ LoopTag+31 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %23:sreg_32 = PHI %20, %bb.0, %24, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+34 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %21[ 23 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %8[ LoopTag+31 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %25:sreg_32 = PHI %19, %bb.0, %26, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+34 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %21[ 23 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %23[ 20 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %8[ LoopTag+31 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %27:vgpr_32 = PHI %17, %bb.0, %28, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+34 ]
+# CHECK: Vreg: %21[ 23 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %23[ 20 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %8[ LoopTag+31 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: %29:vgpr_32 = PHI %18, %bb.0, %30, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+34 ]
+# CHECK: Vreg: %21[ 23 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %23[ 20 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %27[ LoopTag+30 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %8[ LoopTag+31 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: %31:vgpr_32 = PHI %17, %bb.0, %32, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+34 ]
+# CHECK: Vreg: %21[ 23 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %23[ 20 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %27[ LoopTag+30 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %8[ LoopTag+31 ]
+# CHECK: Vreg: %29[ LoopTag+41 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: %33:sreg_32 = S_ADD_I32 %25, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+33 ]
+# CHECK: Vreg: %21[ 22 ]
+# CHECK: Vreg: %9:sub0[ 4 ]
+# CHECK: Vreg: %9:sub1[ 5 ]
+# CHECK: Vreg: %23[ 19 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %27[ LoopTag+29 ]
+# CHECK: Vreg: %8:sub0[ 12 ]
+# CHECK: Vreg: %8:sub1[ 13 ]
+# CHECK: Vreg: %8[ LoopTag+30 ]
+# CHECK: Vreg: %29[ LoopTag+40 ]
+# CHECK: Vreg: %10[ 10 ]
+# CHECK: Vreg: %17[ LoopTag+42 ]
+# CHECK: Vreg: %31[ LoopTag+31 ]
+# CHECK: Instr: %34:sreg_32_xm0 = S_ASHR_I32 %33, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+32 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 21 ]
+# CHECK: Vreg: %9:sub0[ 3 ]
+# CHECK: Vreg: %9:sub1[ 4 ]
+# CHECK: Vreg: %23[ 18 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %27[ LoopTag+28 ]
+# CHECK: Vreg: %8:sub0[ 11 ]
+# CHECK: Vreg: %8:sub1[ 12 ]
+# CHECK: Vreg: %8[ LoopTag+29 ]
+# CHECK: Vreg: %29[ LoopTag+39 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %17[ LoopTag+41 ]
+# CHECK: Vreg: %31[ LoopTag+30 ]
+# CHECK: Instr: %35:sreg_64 = REG_SEQUENCE killed %33, %subreg.sub0, killed %34, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+31 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 20 ]
+# CHECK: Vreg: %9:sub0[ 2 ]
+# CHECK: Vreg: %9:sub1[ 3 ]
+# CHECK: Vreg: %23[ 17 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %27[ LoopTag+27 ]
+# CHECK: Vreg: %8:sub0[ 10 ]
+# CHECK: Vreg: %8:sub1[ 11 ]
+# CHECK: Vreg: %8[ LoopTag+28 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+38 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %17[ LoopTag+40 ]
+# CHECK: Vreg: %31[ LoopTag+29 ]
+# CHECK: Instr: %36:sreg_64 = nsw S_LSHL_B64 killed %35, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+30 ]
+# CHECK: Vreg: %21[ 19 ]
+# CHECK: Vreg: %9:sub0[ 1 ]
+# CHECK: Vreg: %9:sub1[ 2 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ 16 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %27[ LoopTag+26 ]
+# CHECK: Vreg: %8:sub0[ 9 ]
+# CHECK: Vreg: %8:sub1[ 10 ]
+# CHECK: Vreg: %8[ LoopTag+27 ]
+# CHECK: Vreg: %29[ LoopTag+37 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %17[ LoopTag+39 ]
+# CHECK: Vreg: %31[ LoopTag+28 ]
+# CHECK: Instr: %37:vgpr_32, %38:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %9.sub0, %36.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+29 ]
+# CHECK: Vreg: %21[ 18 ]
+# CHECK: Vreg: %9:sub0[ 0 ]
+# CHECK: Vreg: %9:sub1[ 1 ]
+# CHECK: Vreg: %23[ 15 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %27[ LoopTag+25 ]
+# CHECK: Vreg: %8:sub0[ 8 ]
+# CHECK: Vreg: %8:sub1[ 9 ]
+# CHECK: Vreg: %8[ LoopTag+26 ]
+# CHECK: Vreg: %29[ LoopTag+36 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %36:sub0[ 0 ]
+# CHECK: Vreg: %36:sub1[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+38 ]
+# CHECK: Vreg: %31[ LoopTag+27 ]
+# CHECK: Instr: %39:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %36.sub1, %9.sub1, killed %38, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+28 ]
+# CHECK: Vreg: %21[ 17 ]
+# CHECK: Vreg: %9:sub1[ 0 ]
+# CHECK: Vreg: %9:sub0[ 25 ]
+# CHECK: Vreg: %23[ 14 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %27[ LoopTag+24 ]
+# CHECK: Vreg: %8:sub0[ 7 ]
+# CHECK: Vreg: %8:sub1[ 8 ]
+# CHECK: Vreg: %8[ LoopTag+25 ]
+# CHECK: Vreg: %29[ LoopTag+35 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %36:sub1[ 0 ]
+# CHECK: Vreg: %36:sub0[ 7 ]
+# CHECK: Vreg: %17[ LoopTag+37 ]
+# CHECK: Vreg: %31[ LoopTag+26 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Instr: %40:vreg_64 = REG_SEQUENCE killed %37, %subreg.sub0, killed %39, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+27 ]
+# CHECK: Vreg: %21[ 16 ]
+# CHECK: Vreg: %9:sub0[ 24 ]
+# CHECK: Vreg: %9:sub1[ 25 ]
+# CHECK: Vreg: %23[ 13 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %27[ LoopTag+23 ]
+# CHECK: Vreg: %8:sub0[ 6 ]
+# CHECK: Vreg: %8:sub1[ 7 ]
+# CHECK: Vreg: %8[ LoopTag+24 ]
+# CHECK: Vreg: %29[ LoopTag+34 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %36:sub0[ 6 ]
+# CHECK: Vreg: %36:sub1[ 7 ]
+# CHECK: Vreg: %17[ LoopTag+36 ]
+# CHECK: Vreg: %31[ LoopTag+25 ]
+# CHECK: Instr: %41:vgpr_32 = GLOBAL_LOAD_DWORD killed %40, 0, 0, implicit $exec :: (load (s32) from %ir.gep1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+26 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 15 ]
+# CHECK: Vreg: %9:sub0[ 23 ]
+# CHECK: Vreg: %9:sub1[ 24 ]
+# CHECK: Vreg: %23[ 12 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %27[ LoopTag+22 ]
+# CHECK: Vreg: %8:sub0[ 5 ]
+# CHECK: Vreg: %8:sub1[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+23 ]
+# CHECK: Vreg: %29[ LoopTag+33 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %36:sub0[ 5 ]
+# CHECK: Vreg: %36:sub1[ 6 ]
+# CHECK: Vreg: %17[ LoopTag+35 ]
+# CHECK: Vreg: %31[ LoopTag+24 ]
+# CHECK: Instr: %28:vgpr_32 = V_ADD_U32_e64 %25, %41, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %21[ 14 ]
+# CHECK: Vreg: %9:sub0[ 22 ]
+# CHECK: Vreg: %9:sub1[ 23 ]
+# CHECK: Vreg: %23[ 11 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %27[ LoopTag+21 ]
+# CHECK: Vreg: %8:sub0[ 4 ]
+# CHECK: Vreg: %8:sub1[ 5 ]
+# CHECK: Vreg: %8[ LoopTag+22 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+32 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %36:sub0[ 4 ]
+# CHECK: Vreg: %36:sub1[ 5 ]
+# CHECK: Vreg: %17[ LoopTag+34 ]
+# CHECK: Vreg: %31[ LoopTag+23 ]
+# CHECK: Instr: %30:vgpr_32 = V_MUL_LO_U32_e64 %41, %25, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %28[ 16 ]
+# CHECK: Vreg: %9:sub0[ 21 ]
+# CHECK: Vreg: %9:sub1[ 22 ]
+# CHECK: Vreg: %23[ 10 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %27[ LoopTag+20 ]
+# CHECK: Vreg: %8:sub0[ 3 ]
+# CHECK: Vreg: %8:sub1[ 4 ]
+# CHECK: Vreg: %8[ LoopTag+21 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+31 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %36:sub0[ 3 ]
+# CHECK: Vreg: %36:sub1[ 4 ]
+# CHECK: Vreg: %17[ LoopTag+33 ]
+# CHECK: Vreg: %31[ LoopTag+22 ]
+# CHECK: Instr: GLOBAL_STORE_SHORT_D16_HI %10, %30, 2, 0, implicit $exec :: (store (s16) into %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+23 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %28[ 15 ]
+# CHECK: Vreg: %9:sub0[ 20 ]
+# CHECK: Vreg: %9:sub1[ 21 ]
+# CHECK: Vreg: %23[ 9 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %25[ 8 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %27[ LoopTag+19 ]
+# CHECK: Vreg: %8:sub0[ 2 ]
+# CHECK: Vreg: %8:sub1[ 3 ]
+# CHECK: Vreg: %8[ LoopTag+20 ]
+# CHECK: Vreg: %41[ LoopTag+31 ]
+# CHECK: Vreg: %29[ LoopTag+30 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %36:sub0[ 2 ]
+# CHECK: Vreg: %36:sub1[ 3 ]
+# CHECK: Vreg: %17[ LoopTag+32 ]
+# CHECK: Vreg: %31[ LoopTag+21 ]
+# CHECK: Instr: GLOBAL_STORE_SHORT %10, %30, 0, 0, implicit $exec :: (store (s16) into %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+22 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %28[ 14 ]
+# CHECK: Vreg: %9:sub0[ 19 ]
+# CHECK: Vreg: %9:sub1[ 20 ]
+# CHECK: Vreg: %23[ 8 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %25[ 7 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %27[ LoopTag+18 ]
+# CHECK: Vreg: %8:sub0[ 1 ]
+# CHECK: Vreg: %8:sub1[ 2 ]
+# CHECK: Vreg: %8[ LoopTag+19 ]
+# CHECK: Vreg: %41[ LoopTag+30 ]
+# CHECK: Vreg: %29[ LoopTag+29 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %36:sub0[ 1 ]
+# CHECK: Vreg: %36:sub1[ 2 ]
+# CHECK: Vreg: %17[ LoopTag+31 ]
+# CHECK: Vreg: %31[ LoopTag+20 ]
+# CHECK: Instr: %42:vgpr_32, %43:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %8.sub0, %36.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %28[ 13 ]
+# CHECK: Vreg: %9:sub0[ 18 ]
+# CHECK: Vreg: %9:sub1[ 19 ]
+# CHECK: Vreg: %23[ 7 ]
+# CHECK: Vreg: %30[ 13 ]
+# CHECK: Vreg: %25[ 6 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %27[ LoopTag+17 ]
+# CHECK: Vreg: %8:sub0[ 0 ]
+# CHECK: Vreg: %8:sub1[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+18 ]
+# CHECK: Vreg: %41[ LoopTag+29 ]
+# CHECK: Vreg: %29[ LoopTag+28 ]
+# CHECK: Vreg: %10[ 24 ]
+# CHECK: Vreg: %36:sub0[ 0 ]
+# CHECK: Vreg: %36:sub1[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+30 ]
+# CHECK: Vreg: %31[ LoopTag+19 ]
+# CHECK: Instr: %44:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %36.sub1, %8.sub1, killed %43, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+20 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %28[ 12 ]
+# CHECK: Vreg: %9:sub0[ 17 ]
+# CHECK: Vreg: %9:sub1[ 18 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %23[ 6 ]
+# CHECK: Vreg: %30[ 12 ]
+# CHECK: Vreg: %25[ 5 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %27[ LoopTag+16 ]
+# CHECK: Vreg: %8:sub1[ 0 ]
+# CHECK: Vreg: %8:sub0[ 25 ]
+# CHECK: Vreg: %8[ LoopTag+17 ]
+# CHECK: Vreg: %41[ LoopTag+28 ]
+# CHECK: Vreg: %29[ LoopTag+27 ]
+# CHECK: Vreg: %10[ 23 ]
+# CHECK: Vreg: %36:sub1[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+29 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ LoopTag+18 ]
+# CHECK: Instr: %45:vreg_64 = REG_SEQUENCE killed %42, %subreg.sub0, killed %44, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %28[ 11 ]
+# CHECK: Vreg: %9:sub0[ 16 ]
+# CHECK: Vreg: %9:sub1[ 17 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ 5 ]
+# CHECK: Vreg: %30[ 11 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %27[ LoopTag+15 ]
+# CHECK: Vreg: %8:sub0[ 24 ]
+# CHECK: Vreg: %8:sub1[ 25 ]
+# CHECK: Vreg: %8[ LoopTag+16 ]
+# CHECK: Vreg: %41[ LoopTag+27 ]
+# CHECK: Vreg: %29[ LoopTag+26 ]
+# CHECK: Vreg: %10[ 22 ]
+# CHECK: Vreg: %17[ LoopTag+28 ]
+# CHECK: Vreg: %31[ LoopTag+17 ]
+# CHECK: Instr: %46:vgpr_32 = GLOBAL_LOAD_USHORT %45, 0, 0, implicit $exec :: (load (s16) from %ir.gep2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+18 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %28[ 10 ]
+# CHECK: Vreg: %9:sub0[ 15 ]
+# CHECK: Vreg: %9:sub1[ 16 ]
+# CHECK: Vreg: %23[ 4 ]
+# CHECK: Vreg: %30[ 10 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %27[ LoopTag+14 ]
+# CHECK: Vreg: %8:sub0[ 23 ]
+# CHECK: Vreg: %8:sub1[ 24 ]
+# CHECK: Vreg: %8[ LoopTag+15 ]
+# CHECK: Vreg: %41[ LoopTag+26 ]
+# CHECK: Vreg: %29[ LoopTag+25 ]
+# CHECK: Vreg: %10[ 21 ]
+# CHECK: Vreg: %17[ LoopTag+27 ]
+# CHECK: Vreg: %31[ LoopTag+16 ]
+# CHECK: Instr: %47:vgpr_32 = GLOBAL_LOAD_USHORT killed %45, 2, 0, implicit $exec :: (load (s16) from %ir.gep2 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+17 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %28[ 9 ]
+# CHECK: Vreg: %9:sub0[ 14 ]
+# CHECK: Vreg: %9:sub1[ 15 ]
+# CHECK: Vreg: %23[ 3 ]
+# CHECK: Vreg: %30[ 9 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %27[ LoopTag+13 ]
+# CHECK: Vreg: %8:sub0[ 22 ]
+# CHECK: Vreg: %8:sub1[ 23 ]
+# CHECK: Vreg: %8[ LoopTag+14 ]
+# CHECK: Vreg: %41[ LoopTag+25 ]
+# CHECK: Vreg: %29[ LoopTag+24 ]
+# CHECK: Vreg: %10[ 20 ]
+# CHECK: Vreg: %17[ LoopTag+26 ]
+# CHECK: Vreg: %31[ LoopTag+15 ]
+# CHECK: Instr: %48:vgpr_32 = V_LSHL_OR_B32_e64 killed %47, 16, killed %46, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+16 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %28[ 8 ]
+# CHECK: Vreg: %9:sub0[ 13 ]
+# CHECK: Vreg: %9:sub1[ 14 ]
+# CHECK: Vreg: %23[ 2 ]
+# CHECK: Vreg: %30[ 8 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ LoopTag+12 ]
+# CHECK: Vreg: %8:sub0[ 21 ]
+# CHECK: Vreg: %8:sub1[ 22 ]
+# CHECK: Vreg: %8[ LoopTag+13 ]
+# CHECK: Vreg: %41[ LoopTag+24 ]
+# CHECK: Vreg: %29[ LoopTag+23 ]
+# CHECK: Vreg: %10[ 19 ]
+# CHECK: Vreg: %17[ LoopTag+25 ]
+# CHECK: Vreg: %31[ LoopTag+14 ]
+# CHECK: Instr: %26:sreg_32 = S_ADD_I32 %25, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %28[ 7 ]
+# CHECK: Vreg: %9:sub0[ 12 ]
+# CHECK: Vreg: %9:sub1[ 13 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %30[ 7 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %27[ LoopTag+11 ]
+# CHECK: Vreg: %8:sub0[ 20 ]
+# CHECK: Vreg: %8:sub1[ 21 ]
+# CHECK: Vreg: %8[ LoopTag+12 ]
+# CHECK: Vreg: %41[ LoopTag+23 ]
+# CHECK: Vreg: %48[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+22 ]
+# CHECK: Vreg: %10[ 18 ]
+# CHECK: Vreg: %17[ LoopTag+24 ]
+# CHECK: Vreg: %31[ LoopTag+13 ]
+# CHECK: Instr: %24:sreg_32 = S_ADD_I32 %23, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+14 ]
+# CHECK: Vreg: %26[ 4 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %28[ 6 ]
+# CHECK: Vreg: %9:sub0[ 11 ]
+# CHECK: Vreg: %9:sub1[ 12 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 6 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %27[ LoopTag+10 ]
+# CHECK: Vreg: %8:sub0[ 19 ]
+# CHECK: Vreg: %8:sub1[ 20 ]
+# CHECK: Vreg: %8[ LoopTag+11 ]
+# CHECK: Vreg: %41[ LoopTag+22 ]
+# CHECK: Vreg: %48[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+21 ]
+# CHECK: Vreg: %10[ 17 ]
+# CHECK: Vreg: %17[ LoopTag+23 ]
+# CHECK: Vreg: %31[ LoopTag+12 ]
+# CHECK: Instr: %32:vgpr_32 = V_ADD_U32_e64 killed %23, killed %48, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+13 ]
+# CHECK: Vreg: %26[ 3 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %28[ 5 ]
+# CHECK: Vreg: %9:sub0[ 10 ]
+# CHECK: Vreg: %9:sub1[ 11 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 5 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %27[ LoopTag+9 ]
+# CHECK: Vreg: %8:sub0[ 18 ]
+# CHECK: Vreg: %8:sub1[ 19 ]
+# CHECK: Vreg: %8[ LoopTag+10 ]
+# CHECK: Vreg: %41[ LoopTag+21 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+20 ]
+# CHECK: Vreg: %10[ 16 ]
+# CHECK: Vreg: %17[ LoopTag+22 ]
+# CHECK: Vreg: %24[ 5 ]
+# CHECK: Vreg: %31[ LoopTag+11 ]
+# CHECK: Instr: %49:sreg_32 = V_CMP_GE_U32_e64 killed %25, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %26[ 2 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %28[ 4 ]
+# CHECK: Vreg: %9:sub0[ 9 ]
+# CHECK: Vreg: %9:sub1[ 10 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %32[ 4 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %27[ LoopTag+8 ]
+# CHECK: Vreg: %8:sub0[ 17 ]
+# CHECK: Vreg: %8:sub1[ 18 ]
+# CHECK: Vreg: %8[ LoopTag+9 ]
+# CHECK: Vreg: %41[ LoopTag+20 ]
+# CHECK: Vreg: %29[ LoopTag+19 ]
+# CHECK: Vreg: %10[ 15 ]
+# CHECK: Vreg: %17[ LoopTag+21 ]
+# CHECK: Vreg: %24[ 4 ]
+# CHECK: Vreg: %31[ LoopTag+10 ]
+# CHECK: Instr: %22:sreg_32 = SI_IF_BREAK killed %49, killed %21, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+11 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %28[ 3 ]
+# CHECK: Vreg: %9:sub0[ 8 ]
+# CHECK: Vreg: %9:sub1[ 9 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %30[ 3 ]
+# CHECK: Vreg: %32[ 3 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %27[ LoopTag+7 ]
+# CHECK: Vreg: %8:sub0[ 16 ]
+# CHECK: Vreg: %8:sub1[ 17 ]
+# CHECK: Vreg: %8[ LoopTag+8 ]
+# CHECK: Vreg: %41[ LoopTag+19 ]
+# CHECK: Vreg: %29[ LoopTag+18 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %17[ LoopTag+20 ]
+# CHECK: Vreg: %24[ 3 ]
+# CHECK: Vreg: %31[ LoopTag+9 ]
+# CHECK: Instr: %50:vgpr_32 = COPY %26, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %28[ 2 ]
+# CHECK: Vreg: %9:sub0[ 7 ]
+# CHECK: Vreg: %9:sub1[ 8 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %27[ LoopTag+6 ]
+# CHECK: Vreg: %8:sub0[ 15 ]
+# CHECK: Vreg: %8:sub1[ 16 ]
+# CHECK: Vreg: %8[ LoopTag+7 ]
+# CHECK: Vreg: %41[ LoopTag+18 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+17 ]
+# CHECK: Vreg: %10[ 13 ]
+# CHECK: Vreg: %17[ LoopTag+19 ]
+# CHECK: Vreg: %24[ 2 ]
+# CHECK: Vreg: %31[ LoopTag+8 ]
+# CHECK: Instr: SI_LOOP %22, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+9 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %9:sub0[ 6 ]
+# CHECK: Vreg: %9:sub1[ 7 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %27[ LoopTag+5 ]
+# CHECK: Vreg: %8:sub0[ 14 ]
+# CHECK: Vreg: %8:sub1[ 15 ]
+# CHECK: Vreg: %8[ LoopTag+6 ]
+# CHECK: Vreg: %41[ LoopTag+17 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+16 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Vreg: %17[ LoopTag+18 ]
+# CHECK: Vreg: %24[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+3 ]
+# CHECK: Vreg: %31[ LoopTag+7 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+8 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %27[ LoopTag+4 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %8[ LoopTag+5 ]
+# CHECK: Vreg: %41[ LoopTag+16 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+15 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ LoopTag+17 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+2 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+8 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9:sub0[ 5 ]
+# CHECK: Vreg: %9:sub1[ 6 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %27[ LoopTag+4 ]
+# CHECK: Vreg: %8:sub0[ 13 ]
+# CHECK: Vreg: %8:sub1[ 14 ]
+# CHECK: Vreg: %8[ LoopTag+5 ]
+# CHECK: Vreg: %41[ LoopTag+16 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+15 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ LoopTag+17 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+2 ]
+# CHECK: Vreg: %31[ LoopTag+6 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: SI_END_CF killed %22, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %27[ 3 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: Vreg: %41[ 15 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %29[ 14 ]
+# CHECK: Vreg: %17[ 16 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %31[ 5 ]
+# CHECK: Instr: %51:vgpr_32 = V_ADD_U32_e64 -2, killed %50, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %41[ 14 ]
+# CHECK: Vreg: %29[ 13 ]
+# CHECK: Vreg: %17[ 15 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %31[ 4 ]
+# CHECK: Instr: %52:vgpr_32 = V_MUL_LO_U32_e64 killed %30, killed %51, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %41[ 13 ]
+# CHECK: Vreg: %29[ 12 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %31[ 3 ]
+# CHECK: Instr: %53:vgpr_32 = V_MUL_LO_U32_e64 100, killed %27, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %41[ 12 ]
+# CHECK: Vreg: %29[ 11 ]
+# CHECK: Vreg: %17[ 13 ]
+# CHECK: Vreg: %31[ 2 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %8, %53, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %41[ 11 ]
+# CHECK: Vreg: %29[ 10 ]
+# CHECK: Vreg: %17[ 12 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: Instr: %54:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %8[ 8 ]
+# CHECK: Vreg: %53[ 10 ]
+# CHECK: Vreg: %41[ 10 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %17[ 11 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %8[ 8 ]
+# CHECK: Vreg: %53[ 10 ]
+# CHECK: Vreg: %41[ 10 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %17[ 11 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %55:sreg_32 = PHI %54, %bb.2, %56, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+8 ]
+# CHECK: Vreg: %53[ LoopTag+10 ]
+# CHECK: Vreg: %41[ LoopTag+10 ]
+# CHECK: Vreg: %29[ LoopTag+9 ]
+# CHECK: Vreg: %17[ LoopTag+11 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %57:sreg_32 = PHI %54, %bb.2, %58, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+8 ]
+# CHECK: Vreg: %53[ LoopTag+10 ]
+# CHECK: Vreg: %41[ LoopTag+10 ]
+# CHECK: Vreg: %29[ LoopTag+9 ]
+# CHECK: Vreg: %55[ 3 ]
+# CHECK: Vreg: %17[ LoopTag+11 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %59:vgpr_32 = PHI %31, %bb.2, %52, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+8 ]
+# CHECK: Vreg: %53[ LoopTag+10 ]
+# CHECK: Vreg: %41[ LoopTag+10 ]
+# CHECK: Vreg: %29[ LoopTag+9 ]
+# CHECK: Vreg: %55[ 3 ]
+# CHECK: Vreg: %17[ LoopTag+11 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %57[ 1 ]
+# CHECK: Instr: %58:sreg_32 = S_ADD_I32 killed %57, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %52[ 5 ]
+# CHECK: Vreg: %59[ LoopTag+7 ]
+# CHECK: Vreg: %8[ LoopTag+7 ]
+# CHECK: Vreg: %53[ LoopTag+9 ]
+# CHECK: Vreg: %41[ LoopTag+9 ]
+# CHECK: Vreg: %29[ LoopTag+8 ]
+# CHECK: Vreg: %55[ 2 ]
+# CHECK: Vreg: %17[ LoopTag+10 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Instr: %60:sreg_32 = V_CMP_GE_U32_e64 %58, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %52[ 4 ]
+# CHECK: Vreg: %59[ LoopTag+6 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+6 ]
+# CHECK: Vreg: %53[ LoopTag+8 ]
+# CHECK: Vreg: %41[ LoopTag+8 ]
+# CHECK: Vreg: %29[ LoopTag+7 ]
+# CHECK: Vreg: %55[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+9 ]
+# CHECK: Instr: %56:sreg_32 = SI_IF_BREAK killed %60, killed %55, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %52[ 3 ]
+# CHECK: Vreg: %59[ LoopTag+5 ]
+# CHECK: Vreg: %58[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+5 ]
+# CHECK: Vreg: %53[ LoopTag+7 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %41[ LoopTag+7 ]
+# CHECK: Vreg: %29[ LoopTag+6 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+8 ]
+# CHECK: Instr: %61:vgpr_32 = COPY %58, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %52[ 2 ]
+# CHECK: Vreg: %59[ LoopTag+4 ]
+# CHECK: Vreg: %56[ 1 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+4 ]
+# CHECK: Vreg: %53[ LoopTag+6 ]
+# CHECK: Vreg: %41[ LoopTag+6 ]
+# CHECK: Vreg: %29[ LoopTag+5 ]
+# CHECK: Vreg: %17[ LoopTag+7 ]
+# CHECK: Instr: SI_LOOP %56, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %59[ LoopTag+3 ]
+# CHECK: Vreg: %61[ LoopTag+4 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %58[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+3 ]
+# CHECK: Vreg: %53[ LoopTag+5 ]
+# CHECK: Vreg: %41[ LoopTag+5 ]
+# CHECK: Vreg: %29[ LoopTag+4 ]
+# CHECK: Vreg: %17[ LoopTag+6 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %59[ LoopTag+2 ]
+# CHECK: Vreg: %61[ LoopTag+3 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+2 ]
+# CHECK: Vreg: %53[ LoopTag+4 ]
+# CHECK: Vreg: %41[ LoopTag+4 ]
+# CHECK: Vreg: %29[ LoopTag+3 ]
+# CHECK: Vreg: %17[ LoopTag+5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %59[ LoopTag+2 ]
+# CHECK: Vreg: %61[ LoopTag+3 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+2 ]
+# CHECK: Vreg: %53[ LoopTag+4 ]
+# CHECK: Vreg: %41[ LoopTag+4 ]
+# CHECK: Vreg: %29[ LoopTag+3 ]
+# CHECK: Vreg: %17[ LoopTag+5 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: SI_END_CF killed %56, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %59[ 1 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %53[ 3 ]
+# CHECK: Vreg: %41[ 3 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %17[ 4 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %8, %59, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %53[ 2 ]
+# CHECK: Vreg: %41[ 2 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Instr: %62:vgpr_32 = V_ADD3_U32_e64 killed %59, killed %61, killed %29, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %53[ 1 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Instr: %63:vgpr_32 = V_ADD3_U32_e64 killed %62, killed %53, killed %41, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Instr: %64:vgpr_32 = V_ADD3_U32_e64 killed %17, killed %63, 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: %65:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %64, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %65
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test6(ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, i32 %TC1, i32 %TC2) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  %add1 = add i32 %ld1, 100
+  br label %1
+  1:
+  %phi.inc1 = phi i32 [ 0, %0 ], [ %inc1, %1 ]
+  %phi1 = phi i32 [ %ld1, %0 ], [ %add2, %1 ]
+  %phi2 = phi i32 [ 100, %0 ], [ %mul1, %1 ]
+  %phi3 = phi i32 [ %ld1, %0 ], [ %sub, %1 ]
+  %sext1 = sext i32 %phi.inc1 to i64
+  %gep1 = getelementptr inbounds i32, ptr addrspace(1) %p2, i64 %sext1
+  %ld2 = load i32, ptr addrspace(1) %gep1, align 4
+  %inc1 = add i32 %phi.inc1, 1
+  %add2 = add i32 %ld2, %inc1
+  %mul1 = mul i32 %ld2, %inc1
+  store i32 %mul1, ptr addrspace(1) %p1, align 2
+  %mul2 = mul i32 %mul1, %phi.inc1
+  %sext2 = sext i32 %inc1 to i64
+  %gep2 = getelementptr inbounds i32, ptr addrspace(1) %p3, i64 %sext1
+  %ld3 = load i32, ptr addrspace(1) %gep2, align 2
+  %sub =  sub i32 %ld3, %phi.inc1
+  %cond1 = icmp ult i32 %inc1, %TC1
+  br i1 %cond1, label %1, label %2
+  2:
+  %mul3 = mul i32 %phi1, 100
+  store i32 %mul3, ptr addrspace(1) %p3
+  br label %3
+  3:
+  %phi.inc2 = phi i32 [ 0, %2 ], [ %inc2, %3 ]
+  %phi4 = phi i32 [ %phi3, %2 ], [ %mul2, %3 ]
+  %inc2 = add i32 %phi.inc2, 2
+  store i32 %phi4, ptr addrspace(1) %p3
+  %add3 = add i32 %phi4, %inc2
+  %cond2 = icmp ult i32 %inc2, %TC2
+  br i1 %cond2, label %3, label %4
+  4:
+  %add4 = add i32 %add3, %phi2
+  %add5 = add i32 %add4, %mul3
+  %add6 = add i32 %add5, %ld2
+  %add7 = add i32 %add6, %add1
+  ret i32 %add7
+  }
+...
+
+---
+name:            test6
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
+  
+    %38:vgpr_32 = COPY killed $vgpr7
+    %37:vgpr_32 = COPY killed $vgpr6
+    %36:vgpr_32 = COPY killed $vgpr5
+    %35:vgpr_32 = COPY killed $vgpr4
+    %34:vgpr_32 = COPY killed $vgpr3
+    %33:vgpr_32 = COPY killed $vgpr2
+    %32:vgpr_32 = COPY killed $vgpr1
+    %31:vgpr_32 = COPY killed $vgpr0
+    %82:vreg_64 = REG_SEQUENCE killed %35, %subreg.sub0, killed %36, %subreg.sub1
+    %81:vreg_64 = REG_SEQUENCE killed %33, %subreg.sub0, killed %34, %subreg.sub1
+    %80:vreg_64 = REG_SEQUENCE killed %31, %subreg.sub0, killed %32, %subreg.sub1
+    %48:vgpr_32 = GLOBAL_LOAD_UBYTE %80, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %50:vgpr_32 = GLOBAL_LOAD_UBYTE %80, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %53:vgpr_32 = V_LSHL_OR_B32_e64 killed %50, 8, killed %48, implicit $exec
+    %54:vgpr_32 = GLOBAL_LOAD_UBYTE %80, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %56:vgpr_32 = GLOBAL_LOAD_UBYTE %80, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %58:vgpr_32 = V_LSHL_OR_B32_e64 killed %56, 8, killed %54, implicit $exec
+    %0:vgpr_32 = V_LSHL_OR_B32_e64 killed %58, 16, killed %53, implicit $exec
+    %44:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+    %43:sreg_32 = S_MOV_B32 1
+    %42:sreg_32 = S_MOV_B32 0
+  
+  bb.1:
+    successors: %bb.2(0x04000000), %bb.1(0x7c000000)
+  
+    %1:sreg_32 = PHI %42, %bb.0, %13, %bb.1
+    %2:sreg_32 = PHI %42, %bb.0, %11, %bb.1
+    %3:sreg_32 = PHI %43, %bb.0, %10, %bb.1
+    %4:vgpr_32 = PHI %0, %bb.0, %8, %bb.1
+    %5:vgpr_32 = PHI %44, %bb.0, %9, %bb.1
+    %6:vgpr_32 = PHI %0, %bb.0, %12, %bb.1
+    %61:sreg_32 = S_ADD_I32 %3, -1, implicit-def dead $scc
+    %62:sreg_32_xm0 = S_ASHR_I32 %61, 31, implicit-def dead $scc
+    %64:sreg_64 = REG_SEQUENCE killed %61, %subreg.sub0, killed %62, %subreg.sub1
+    %66:sreg_64 = nsw S_LSHL_B64 killed %64, 2, implicit-def dead $scc
+    %85:vgpr_32, %87:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %81.sub0, %66.sub0, 0, implicit $exec
+    %86:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 %66.sub1, %81.sub1, killed %87, 0, implicit $exec
+    %67:vreg_64 = REG_SEQUENCE killed %85, %subreg.sub0, killed %86, %subreg.sub1
+    %7:vgpr_32 = GLOBAL_LOAD_DWORD killed %67, 0, 0, implicit $exec :: (load (s32) from %ir.gep1, addrspace 1)
+    %8:vgpr_32 = V_ADD_U32_e64 %3, %7, 0, implicit $exec
+    %9:vgpr_32 = V_MUL_LO_U32_e64 %7, %3, implicit $exec
+    GLOBAL_STORE_SHORT_D16_HI %80, %9, 2, 0, implicit $exec :: (store (s16) into %ir.p1 + 2, addrspace 1)
+    GLOBAL_STORE_SHORT %80, %9, 0, 0, implicit $exec :: (store (s16) into %ir.p1, addrspace 1)
+    %88:vgpr_32, %90:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %82.sub0, %66.sub0, 0, implicit $exec
+    %89:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %66.sub1, %82.sub1, killed %90, 0, implicit $exec
+    %68:vreg_64 = REG_SEQUENCE killed %88, %subreg.sub0, killed %89, %subreg.sub1
+    %69:vgpr_32 = GLOBAL_LOAD_USHORT %68, 0, 0, implicit $exec :: (load (s16) from %ir.gep2, addrspace 1)
+    %70:vgpr_32 = GLOBAL_LOAD_USHORT killed %68, 2, 0, implicit $exec :: (load (s16) from %ir.gep2 + 2, addrspace 1)
+    %71:vgpr_32 = V_LSHL_OR_B32_e64 killed %70, 16, killed %69, implicit $exec
+    %10:sreg_32 = S_ADD_I32 %3, 1, implicit-def dead $scc
+    %11:sreg_32 = S_ADD_I32 %2, -1, implicit-def dead $scc
+    %12:vgpr_32 = V_ADD_U32_e64 killed %2, killed %71, 0, implicit $exec
+    %72:sreg_32 = V_CMP_GE_U32_e64 killed %3, %37, implicit $exec
+    %13:sreg_32 = SI_IF_BREAK killed %72, killed %1, implicit-def dead $scc
+    %83:vgpr_32 = COPY %10, implicit $exec
+    SI_LOOP %13, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+  
+  bb.2:
+    successors: %bb.3(0x80000000)
+  
+    SI_END_CF killed %13, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %74:vgpr_32 = V_ADD_U32_e64 -2, killed %83, 0, implicit $exec
+    %21:vgpr_32 = V_MUL_LO_U32_e64 killed %9, killed %74, implicit $exec
+    %22:vgpr_32 = V_MUL_LO_U32_e64 100, killed %4, implicit $exec
+    GLOBAL_STORE_DWORD %82, %22, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    %73:sreg_32 = S_MOV_B32 0
+  
+  bb.3:
+    successors: %bb.4(0x04000000), %bb.3(0x7c000000)
+  
+    %23:sreg_32 = PHI %73, %bb.2, %27, %bb.3
+    %24:sreg_32 = PHI %73, %bb.2, %26, %bb.3
+    %25:vgpr_32 = PHI %6, %bb.2, %21, %bb.3
+    %26:sreg_32 = S_ADD_I32 killed %24, 2, implicit-def dead $scc
+    %75:sreg_32 = V_CMP_GE_U32_e64 %26, %38, implicit $exec
+    %27:sreg_32 = SI_IF_BREAK killed %75, killed %23, implicit-def dead $scc
+    %84:vgpr_32 = COPY %26, implicit $exec
+    SI_LOOP %27, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.4
+  
+  bb.4:
+    SI_END_CF killed %27, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    GLOBAL_STORE_DWORD killed %82, %25, 0, 0, implicit $exec :: (store (s32) into %ir.p3, addrspace 1)
+    %76:vgpr_32 = V_ADD3_U32_e64 killed %25, killed %84, killed %5, implicit $exec
+    %77:vgpr_32 = V_ADD3_U32_e64 killed %76, killed %22, killed %7, implicit $exec
+    %78:vgpr_32 = V_ADD3_U32_e64 killed %0, killed %77, 100, implicit $exec
+    %79:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %78, implicit $exec
+    $sgpr0 = COPY killed %79
+    SI_RETURN_TO_EPILOG killed $sgpr0
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-linear-block-distances.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-linear-block-distances.mir
new file mode 100644
index 0000000000000..29117dee6d0c0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-linear-block-distances.mir
@@ -0,0 +1,731 @@
+# NOTE: Test validates basic next-use distance calculations for COPY instructions and register liveness tracking
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test1 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %10:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %9:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %9[ 10 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %10[ 10 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Instr: %14:vgpr_32 = V_AND_B32_e64 1, killed %8, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Instr: %15:sreg_32 = V_CMP_NE_U32_e64 1, killed %14, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Instr: %0:sreg_32 = SI_IF killed %15, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %1:vreg_64 = PHI undef %12:vreg_64, %bb.0, %4, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Instr: %72:vgpr_32 = PHI %6, %bb.0, undef %73:vgpr_32, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Instr: %2:sreg_32 = SI_ELSE killed %0, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %72[ 2 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %72[ 1 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %72[ 1 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %33:vgpr_32 = DS_READ_U8_gfx9 %72, 0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 17 ]
+# CHECK: Vreg: %9[ 18 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %10[ 19 ]
+# CHECK: Instr: %34:vgpr_32 = DS_READ_U8_gfx9 %72, 1, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 10 ]
+# CHECK: Vreg: %2[ 16 ]
+# CHECK: Vreg: %9[ 17 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %10[ 18 ]
+# CHECK: Instr: %35:vgpr_32 = DS_READ_U8_gfx9 %72, 2, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 9 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %9[ 16 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %10[ 17 ]
+# CHECK: Instr: %36:vgpr_32 = DS_READ_U8_gfx9 %72, 3, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 8 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %9[ 15 ]
+# CHECK: Vreg: %35[ 9 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %10[ 16 ]
+# CHECK: Instr: %37:vgpr_32 = DS_READ_U8_gfx9 %72, 4, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 7 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %9[ 14 ]
+# CHECK: Vreg: %35[ 8 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %10[ 15 ]
+# CHECK: Vreg: %36[ 8 ]
+# CHECK: Instr: %38:vgpr_32 = DS_READ_U8_gfx9 %72, 5, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 6 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %9[ 13 ]
+# CHECK: Vreg: %35[ 7 ]
+# CHECK: Vreg: %37[ 3 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Instr: %39:vgpr_32 = DS_READ_U8_gfx9 %72, 6, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 5 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %9[ 12 ]
+# CHECK: Vreg: %35[ 6 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %10[ 13 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Instr: %40:vgpr_32 = DS_READ_U8_gfx9 killed %72, 7, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 4 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %35[ 5 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %39[ 2 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Instr: %42:vgpr_32 = V_LSHL_OR_B32_e64 killed %38, 8, killed %37, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 3 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %9[ 10 ]
+# CHECK: Vreg: %35[ 4 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Instr: %43:vgpr_32 = V_LSHL_OR_B32_e64 killed %40, 8, killed %39, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 2 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %35[ 3 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %10[ 10 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Instr: %45:vgpr_32 = V_LSHL_OR_B32_e64 killed %43, 16, killed %42, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %33[ 1 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Instr: %46:vgpr_32 = V_LSHL_OR_B32_e64 killed %34, 8, killed %33, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 3 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Instr: %47:vgpr_32 = V_LSHL_OR_B32_e64 killed %36, 8, killed %35, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 2 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Instr: %48:vgpr_32 = V_LSHL_OR_B32_e64 killed %47, 16, killed %46, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Instr: %62:vreg_64 = REG_SEQUENCE killed %48, %subreg.sub0, killed %45, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Instr: %3:vreg_64 = COPY killed %62
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %16:vgpr_32 = DS_READ_U8_gfx9 %7, 0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 17 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %9[ 20 ]
+# CHECK: Vreg: %10[ 21 ]
+# CHECK: Instr: %17:vgpr_32 = DS_READ_U8_gfx9 %7, 1, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 16 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %9[ 19 ]
+# CHECK: Vreg: %16[ 10 ]
+# CHECK: Vreg: %10[ 20 ]
+# CHECK: Instr: %18:vgpr_32 = DS_READ_U8_gfx9 %7, 2, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %9[ 18 ]
+# CHECK: Vreg: %16[ 9 ]
+# CHECK: Vreg: %10[ 19 ]
+# CHECK: Vreg: %17[ 9 ]
+# CHECK: Instr: %19:vgpr_32 = DS_READ_U8_gfx9 %7, 3, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %9[ 17 ]
+# CHECK: Vreg: %16[ 8 ]
+# CHECK: Vreg: %18[ 9 ]
+# CHECK: Vreg: %10[ 18 ]
+# CHECK: Vreg: %17[ 8 ]
+# CHECK: Instr: %20:vgpr_32 = DS_READ_U8_gfx9 %7, 4, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %9[ 16 ]
+# CHECK: Vreg: %16[ 7 ]
+# CHECK: Vreg: %18[ 8 ]
+# CHECK: Vreg: %10[ 17 ]
+# CHECK: Vreg: %17[ 7 ]
+# CHECK: Vreg: %19[ 8 ]
+# CHECK: Instr: %21:vgpr_32 = DS_READ_U8_gfx9 %7, 5, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %9[ 15 ]
+# CHECK: Vreg: %16[ 6 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %20[ 3 ]
+# CHECK: Vreg: %10[ 16 ]
+# CHECK: Vreg: %17[ 6 ]
+# CHECK: Vreg: %19[ 7 ]
+# CHECK: Instr: %22:vgpr_32 = DS_READ_U8_gfx9 %7, 6, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %9[ 14 ]
+# CHECK: Vreg: %16[ 5 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %20[ 2 ]
+# CHECK: Vreg: %10[ 15 ]
+# CHECK: Vreg: %17[ 5 ]
+# CHECK: Vreg: %19[ 6 ]
+# CHECK: Instr: %23:vgpr_32 = DS_READ_U8_gfx9 killed %7, 7, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %9[ 13 ]
+# CHECK: Vreg: %16[ 4 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %22[ 2 ]
+# CHECK: Vreg: %10[ 14 ]
+# CHECK: Vreg: %17[ 4 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Instr: %25:vgpr_32 = V_LSHL_OR_B32_e64 killed %21, 8, killed %20, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %9[ 12 ]
+# CHECK: Vreg: %16[ 3 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %10[ 13 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Instr: %26:vgpr_32 = V_LSHL_OR_B32_e64 killed %23, 8, killed %22, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %16[ 2 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %10[ 12 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %19[ 3 ]
+# CHECK: Instr: %28:vgpr_32 = V_LSHL_OR_B32_e64 killed %26, 16, killed %25, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %9[ 10 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %10[ 11 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Instr: %29:vgpr_32 = V_LSHL_OR_B32_e64 killed %17, 8, killed %16, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %28[ 3 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %10[ 10 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: %30:vgpr_32 = V_LSHL_OR_B32_e64 killed %19, 8, killed %18, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %28[ 2 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %10[ 9 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %31:vgpr_32 = V_LSHL_OR_B32_e64 killed %30, 16, killed %29, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Instr: %61:vreg_64 = REG_SEQUENCE killed %31, %subreg.sub0, killed %28, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Instr: %4:vreg_64 = COPY killed %61
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Instr: S_BRANCH %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %5:vreg_64 = PHI %1, %bb.1, %3, %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Instr: SI_END_CF killed %2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %5:sub0[ 1 ]
+# CHECK: Vreg: %5:sub1[ 2 ]
+# CHECK: Instr: %64:vgpr_32, %66:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %5.sub0, killed %9, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %5:sub0[ 0 ]
+# CHECK: Vreg: %5:sub1[ 1 ]
+# CHECK: Instr: %65:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %5.sub1, killed %10, killed %66, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %5:sub1[ 0 ]
+# CHECK: Instr: %53:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %64, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Instr: %54:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %65, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %53[ 1 ]
+# CHECK: Instr: $sgpr0 = COPY killed %53
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %54[ 1 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Instr: $sgpr1 = COPY killed %54
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0, killed $sgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+---
+name:            test1
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+noVRegs:         false
+hasFakeUses:     false
+callsEHReturn:   false
+callsUnwindInit: false
+hasEHContTarget: false
+hasEHScopes:     false
+hasEHFunclets:   false
+isOutlined:      false
+debugInstrRef:   true
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+  - { id: 0, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 1, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 2, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 3, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 4, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 5, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 6, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 7, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 8, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 9, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 10, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 11, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 12, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 13, class: sreg_64, preferred-register: '', flags: [  ] }
+  - { id: 14, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 15, class: sreg_32, preferred-register: '$vcc_lo', flags: [  ] }
+  - { id: 16, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 17, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 18, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 19, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 20, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 21, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 22, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 23, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 24, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 25, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 26, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 27, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 28, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 29, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 30, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 31, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 32, class: sreg_64, preferred-register: '', flags: [  ] }
+  - { id: 33, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 34, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 35, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 36, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 37, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 38, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 39, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 40, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 41, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 42, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 43, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 44, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 45, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 46, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 47, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 48, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 49, class: sreg_64, preferred-register: '', flags: [  ] }
+  - { id: 50, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 51, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 52, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 53, class: sreg_32_xm0, preferred-register: '', flags: [  ] }
+  - { id: 54, class: sreg_32_xm0, preferred-register: '', flags: [  ] }
+  - { id: 55, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 56, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 57, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 58, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 59, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 60, class: sgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 61, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 62, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 63, class: vreg_64, preferred-register: '', flags: [  ] }
+  - { id: 64, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 65, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 66, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo', 
+      flags: [  ] }
+  - { id: 67, class: sreg_32_xm0_xexec, preferred-register: '', flags: [  ] }
+  - { id: 68, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 69, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 70, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 71, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 72, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 73, class: vgpr_32, preferred-register: '', flags: [  ] }
+liveins:
+  - { reg: '$vgpr0', virtual-reg: '%6' }
+  - { reg: '$vgpr1', virtual-reg: '%7' }
+  - { reg: '$vgpr2', virtual-reg: '%8' }
+  - { reg: '$vgpr3', virtual-reg: '%9' }
+  - { reg: '$vgpr4', virtual-reg: '%10' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  functionContext: ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  isCalleeSavedInfoValid: false
+  localFrameSize:  0
+fixedStack:      []
+stack:           []
+entry_values:    []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo:
+  explicitKernArgSize: 0
+  maxKernArgAlign: 4
+  ldsSize:         0
+  gdsSize:         0
+  dynLDSAlign:     1
+  isEntryFunction: true
+  isChainFunction: false
+  noSignedZerosFPMath: false
+  memoryBound:     false
+  waveLimiter:     false
+  hasSpilledSGPRs: false
+  hasSpilledVGPRs: false
+  scratchRSrcReg:  '$private_rsrc_reg'
+  frameOffsetReg:  '$fp_reg'
+  stackPtrOffsetReg: '$sgpr32'
+  bytesInStackArgArea: 0
+  returnsVoid:     false
+  psInputAddr:     15
+  psInputEnable:   15
+  maxMemoryClusterDWords: 8
+  mode:
+    ieee:            false
+    dx10-clamp:      true
+    fp32-input-denormals: true
+    fp32-output-denormals: true
+    fp64-fp16-input-denormals: true
+    fp64-fp16-output-denormals: true
+  highBitsOf32BitAddress: 0
+  occupancy:       16
+  vgprForAGPRCopy: ''
+  sgprForEXECCopy: '$sgpr105'
+  longBranchReservedReg: ''
+  hasInitWholeWave: false
+  dynamicVGPRBlockSize: 0
+  scratchReservedForDynamicVGPRs: 0
+  isWholeWaveFunction: false
+body:             |
+  bb.0:
+    successors: %bb.3(0x40000000), %bb.1(0x40000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
+  
+    %10:vgpr_32 = COPY killed $vgpr4
+    %9:vgpr_32 = COPY killed $vgpr3
+    %8:vgpr_32 = COPY killed $vgpr2
+    %7:vgpr_32 = COPY killed $vgpr1
+    %6:vgpr_32 = COPY killed $vgpr0
+    %14:vgpr_32 = V_AND_B32_e64 1, killed %8, implicit $exec
+    %15:sreg_32 = V_CMP_NE_U32_e64 1, killed %14, implicit $exec
+    %0:sreg_32 = SI_IF killed %15, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.3
+  
+  bb.1:
+    successors: %bb.2(0x40000000), %bb.4(0x40000000)
+  
+    %1:vreg_64 = PHI undef %12:vreg_64, %bb.0, %4, %bb.3
+    %72:vgpr_32 = PHI %6, %bb.0, undef %73:vgpr_32, %bb.3
+    %2:sreg_32 = SI_ELSE killed %0, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+  
+  bb.2:
+    successors: %bb.4(0x80000000)
+  
+    %33:vgpr_32 = DS_READ_U8_gfx9 %72, 0, 0, implicit $exec
+    %34:vgpr_32 = DS_READ_U8_gfx9 %72, 1, 0, implicit $exec
+    %35:vgpr_32 = DS_READ_U8_gfx9 %72, 2, 0, implicit $exec
+    %36:vgpr_32 = DS_READ_U8_gfx9 %72, 3, 0, implicit $exec
+    %37:vgpr_32 = DS_READ_U8_gfx9 %72, 4, 0, implicit $exec
+    %38:vgpr_32 = DS_READ_U8_gfx9 %72, 5, 0, implicit $exec
+    %39:vgpr_32 = DS_READ_U8_gfx9 %72, 6, 0, implicit $exec
+    %40:vgpr_32 = DS_READ_U8_gfx9 killed %72, 7, 0, implicit $exec
+    %42:vgpr_32 = V_LSHL_OR_B32_e64 killed %38, 8, killed %37, implicit $exec
+    %43:vgpr_32 = V_LSHL_OR_B32_e64 killed %40, 8, killed %39, implicit $exec
+    %45:vgpr_32 = V_LSHL_OR_B32_e64 killed %43, 16, killed %42, implicit $exec
+    %46:vgpr_32 = V_LSHL_OR_B32_e64 killed %34, 8, killed %33, implicit $exec
+    %47:vgpr_32 = V_LSHL_OR_B32_e64 killed %36, 8, killed %35, implicit $exec
+    %48:vgpr_32 = V_LSHL_OR_B32_e64 killed %47, 16, killed %46, implicit $exec
+    %62:vreg_64 = REG_SEQUENCE killed %48, %subreg.sub0, killed %45, %subreg.sub1
+    %3:vreg_64 = COPY killed %62
+    S_BRANCH %bb.4
+  
+  bb.3:
+    successors: %bb.1(0x80000000)
+  
+    %16:vgpr_32 = DS_READ_U8_gfx9 %7, 0, 0, implicit $exec
+    %17:vgpr_32 = DS_READ_U8_gfx9 %7, 1, 0, implicit $exec
+    %18:vgpr_32 = DS_READ_U8_gfx9 %7, 2, 0, implicit $exec
+    %19:vgpr_32 = DS_READ_U8_gfx9 %7, 3, 0, implicit $exec
+    %20:vgpr_32 = DS_READ_U8_gfx9 %7, 4, 0, implicit $exec
+    %21:vgpr_32 = DS_READ_U8_gfx9 %7, 5, 0, implicit $exec
+    %22:vgpr_32 = DS_READ_U8_gfx9 %7, 6, 0, implicit $exec
+    %23:vgpr_32 = DS_READ_U8_gfx9 killed %7, 7, 0, implicit $exec
+    %25:vgpr_32 = V_LSHL_OR_B32_e64 killed %21, 8, killed %20, implicit $exec
+    %26:vgpr_32 = V_LSHL_OR_B32_e64 killed %23, 8, killed %22, implicit $exec
+    %28:vgpr_32 = V_LSHL_OR_B32_e64 killed %26, 16, killed %25, implicit $exec
+    %29:vgpr_32 = V_LSHL_OR_B32_e64 killed %17, 8, killed %16, implicit $exec
+    %30:vgpr_32 = V_LSHL_OR_B32_e64 killed %19, 8, killed %18, implicit $exec
+    %31:vgpr_32 = V_LSHL_OR_B32_e64 killed %30, 16, killed %29, implicit $exec
+    %61:vreg_64 = REG_SEQUENCE killed %31, %subreg.sub0, killed %28, %subreg.sub1
+    %4:vreg_64 = COPY killed %61
+    S_BRANCH %bb.1
+  
+  bb.4:
+    %5:vreg_64 = PHI %1, %bb.1, %3, %bb.2
+    SI_END_CF killed %2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %64:vgpr_32, %66:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %5.sub0, killed %9, 0, implicit $exec
+    %65:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %5.sub1, killed %10, killed %66, 0, implicit $exec
+    %53:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %64, implicit $exec
+    %54:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %65, implicit $exec
+    $sgpr0 = COPY killed %53
+    $sgpr1 = COPY killed %54
+    SI_RETURN_TO_EPILOG killed $sgpr0, killed $sgpr1
+...
+---
+
+
+
+# Test: Verify instruction-specific distance analysis for linear control flow
+# Focus on key instructions and their immediate distance patterns
+
+
+
+
+
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
new file mode 100644
index 0000000000000..eb086237d8a53
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
@@ -0,0 +1,388 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+
+
+# Verify MBB_0 basic structure and initial distances
+
+# Verify PHI instructions show no distance data
+
+# Verify key LoopTag patterns - %8 shows LoopTag+D for all uses in loop
+
+# Verify normal finite distances outside the loop
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test4 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %9:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %9[ 13 ]
+# CHECK: Instr: %11:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %9[ 12 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Instr: %10:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %0:sreg_32 = PHI %10, %bb.0, %7, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %1:vgpr_32 = PHI %8, %bb.0, %6, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %2:vgpr_32 = PHI %11, %bb.0, %5, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+16 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %3:sreg_32 = PHI %10, %bb.0, %4, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %2[ LoopTag+16 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+16 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Instr: %12:vgpr_32 = DS_READ_U8_gfx9 %1, 0, 0, implicit $exec :: (load (s8) from %ir.p, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %2[ LoopTag+15 ]
+# CHECK: Vreg: %9[ 10 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+15 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Instr: %13:vgpr_32 = DS_READ_U8_gfx9 %1, 1, 0, implicit $exec :: (load (s8) from %ir.p + 1, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %2[ LoopTag+14 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+14 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %12[ 3 ]
+# CHECK: Instr: %14:vgpr_32 = DS_READ_U8_gfx9 %1, 2, 0, implicit $exec :: (load (s8) from %ir.p + 2, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %2[ LoopTag+13 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+13 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %12[ 2 ]
+# CHECK: Instr: %15:vgpr_32 = DS_READ_U8_gfx9 %1, 3, 0, implicit $exec :: (load (s8) from %ir.p + 3, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %2[ LoopTag+12 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+12 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: %16:vgpr_32 = V_LSHL_OR_B32_e64 killed %13, 8, killed %12, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+11 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %8[ LoopTag+11 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %17:vgpr_32 = V_LSHL_OR_B32_e64 killed %15, 8, killed %14, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+10 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %8[ LoopTag+10 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Instr: %18:vgpr_32 = V_LSHL_OR_B32_e64 killed %17, 16, killed %16, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %2[ LoopTag+9 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %8[ LoopTag+9 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Instr: %5:vgpr_32 = V_ADD_U32_e64 %3, killed %18, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %2[ LoopTag+8 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %8[ LoopTag+8 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Instr: %4:sreg_32 = S_ADD_I32 killed %3, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %2[ LoopTag+7 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+7 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %5[ 5 ]
+# CHECK: Instr: %6:vgpr_32 = V_ADD_U32_e64 4, killed %1, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %2[ LoopTag+6 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+6 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Instr: %19:sreg_32 = V_CMP_GE_U32_e64 %4, %9, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+5 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %8[ LoopTag+5 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Instr: %7:sreg_32 = SI_IF_BREAK killed %19, killed %0, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+4 ]
+# CHECK: Vreg: %9[ 13 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %8[ LoopTag+4 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: SI_LOOP %7, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+3 ]
+# CHECK: Vreg: %9[ 12 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %8[ LoopTag+3 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+2 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+2 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+2 ]
+# CHECK: Vreg: %9[ 11 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %8[ LoopTag+2 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: SI_END_CF killed %7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Instr: DS_WRITE_B32_gfx9 killed %8, killed %2, 0, 0, implicit $exec :: (store (s32) into %ir.p, addrspace 3)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Instr: S_ENDPGM 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps void @test4(ptr addrspace(3) %p, i32 %TC) {
+  entry:
+    br label %loop
+  
+  loop:
+    %phi = phi i32 [ 100, %entry ], [ %add, %loop ]
+    %phi.inc = phi i32 [ 0, %entry ], [ %inc, %loop ]
+    %sext = sext i32 %phi.inc to i64
+    %gep = getelementptr inbounds i32, ptr addrspace(3) %p, i64 %sext
+    %ld = load i32, ptr addrspace(3) %gep, align 1
+    %add = add i32 %ld, %phi.inc
+    %inc = add i32 %phi.inc, 1
+    %cond = icmp ult i32 %inc, %TC
+    br i1 %cond, label %loop, label %exit
+  
+  exit:
+    store i32 %phi, ptr addrspace(3) %p
+    ret void
+  }
+
+---
+name:            test4
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+noVRegs:         false
+hasFakeUses:     false
+callsEHReturn:   false
+callsUnwindInit: false
+hasEHContTarget: false
+hasEHScopes:     false
+hasEHFunclets:   false
+isOutlined:      false
+debugInstrRef:   true
+failsVerification: false
+tracksDebugUserValues: false
+registers:
+  - { id: 0, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 1, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 2, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 3, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 4, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 5, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 6, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 7, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 8, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 9, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 10, class: sreg_32, preferred-register: '', flags: [  ] }
+  - { id: 11, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 12, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 13, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 14, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 15, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 16, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 17, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 18, class: vgpr_32, preferred-register: '', flags: [  ] }
+  - { id: 19, class: sreg_32, preferred-register: '', flags: [  ] }
+liveins:
+  - { reg: '$vgpr0', virtual-reg: '%8' }
+  - { reg: '$vgpr1', virtual-reg: '%9' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  hasTailCall:     false
+  localFrameSize:  0
+machineFunctionInfo:
+  explicitKernArgSize: 0
+  maxKernArgAlign: 1
+  ldsSize:         0
+  gdsSize:         0
+  dynLDSAlign:     1
+  isEntryFunction: true
+  isChainFunction: false
+  noSignedZerosFPMath: false
+  memoryBound:     true
+  waveLimiter:     true
+  hasSpilledSGPRs: false
+  hasSpilledVGPRs: false
+  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
+  frameOffsetReg:  '$sgpr32'
+  stackPtrOffsetReg: '$sgpr32'
+  bytesInStackArgArea: 0
+  returnsVoid:     true
+  argumentInfo:
+    privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
+    dispatchPtr:     { reg: '$sgpr4_sgpr5' }
+    queuePtr:        { reg: '$sgpr6_sgpr7' }
+    kernargSegmentPtr: { reg: '$sgpr8_sgpr9' }
+    dispatchID:      { reg: '$sgpr10_sgpr11' }
+    flatScratchInit: { reg: '$sgpr12_sgpr13' }
+    implicitArgPtr:  { reg: '$sgpr14_sgpr15' }
+    workGroupIDX:    { reg: '$sgpr16' }
+    workGroupIDY:    { reg: '$sgpr17' }
+    workGroupIDZ:    { reg: '$sgpr18' }
+    workGroupInfo:   { reg: '$sgpr19' }
+    privateSegmentWaveByteOffset: { reg: '$sgpr20' }
+body:             |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+
+    %9:vgpr_32 = COPY killed $vgpr1
+    %8:vgpr_32 = COPY killed $vgpr0
+    %11:vgpr_32 = V_MOV_B32_e32 100, implicit $exec
+    %10:sreg_32 = S_MOV_B32 0
+
+  bb.1:
+    %0:sreg_32 = PHI %10, %bb.0, %7, %bb.1
+    %1:vgpr_32 = PHI %8, %bb.0, %6, %bb.1
+    %2:vgpr_32 = PHI %11, %bb.0, %5, %bb.1
+    %3:sreg_32 = PHI %10, %bb.0, %4, %bb.1
+    %12:vgpr_32 = DS_READ_U8_gfx9 %1, 0, 0, implicit $exec :: (load (s8) from %ir.p, addrspace 3)
+    %13:vgpr_32 = DS_READ_U8_gfx9 %1, 1, 0, implicit $exec :: (load (s8) from %ir.p + 1, addrspace 3)
+    %14:vgpr_32 = DS_READ_U8_gfx9 %1, 2, 0, implicit $exec :: (load (s8) from %ir.p + 2, addrspace 3)
+    %15:vgpr_32 = DS_READ_U8_gfx9 %1, 3, 0, implicit $exec :: (load (s8) from %ir.p + 3, addrspace 3)
+    %16:vgpr_32 = V_LSHL_OR_B32_e64 killed %13, 8, killed %12, implicit $exec
+    %17:vgpr_32 = V_LSHL_OR_B32_e64 killed %15, 8, killed %14, implicit $exec
+    %18:vgpr_32 = V_LSHL_OR_B32_e64 killed %17, 16, killed %16, implicit $exec
+    %5:vgpr_32 = V_ADD_U32_e64 %3, killed %18, 0, implicit $exec
+    %4:sreg_32 = S_ADD_I32 killed %3, 1, implicit-def dead $scc
+    %6:vgpr_32 = V_ADD_U32_e64 4, killed %1, 0, implicit $exec
+    %19:sreg_32 = V_CMP_GE_U32_e64 %4, %9, implicit $exec
+    %7:sreg_32 = SI_IF_BREAK killed %19, killed %0, implicit-def dead $scc
+    SI_LOOP %7, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+
+  bb.2:
+    SI_END_CF killed %7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    DS_WRITE_B32_gfx9 killed %8, killed %2, 0, 0, implicit $exec :: (store (s32) into %ir.p, addrspace 3)
+    S_ENDPGM 0
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
new file mode 100644
index 0000000000000..93414a7e4267e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
@@ -0,0 +1,268 @@
+# This test validates the enhanced three-tier distance ranking system in AMDGPU Next Use Analysis.
+#
+# === THREE-TIER DISTANCE SYSTEM ===
+#
+# The analysis uses a sophisticated ranking system to handle complex control flow:
+#
+# Tier 1: FINITE DISTANCES (0 to ~1e12)
+#   - Standard instruction-to-instruction distances within basic blocks
+#   - Cross-block distances for normal control flow
+#   - Used when next use is reachable through finite instruction count
+#
+# Tier 2: LOOP-TAG DISTANCES (LoopTag + finite, where LoopTag = 2^40)
+#   - Applied when crossing loop boundaries (loop-exiting edges)
+#   - Indicates "outside current loop context" with additional finite offset
+#   - Examples: LoopTag+7, LoopTag+15
+#   - For nested loops: LoopTag*2+offset, LoopTag*3+offset, etc.
+#
+# Tier 3: DEAD-TAG DISTANCES (DeadTag + finite, where DeadTag = 2^60)
+#   - Reserved for truly dead registers (no reachable next use)
+#   - Much larger than LoopTag to ensure proper ranking
+#
+# === RANKING HIERARCHY ===
+#
+# The ranking ensures register spiller prioritizes correctly:
+#   finite < LoopTag+finite < LoopTag*2+finite < ... < DeadTag+finite
+#
+# This means:
+# - Registers used soon (finite distances) have highest priority
+# - Registers used outside loops (LoopTag) have medium priority
+# - Dead registers (DeadTag) have lowest priority for spilling
+#
+# === TEST VALIDATION ===
+#
+# This test uses a nested loop structure:
+#   bb.0 → bb.1 ⇄ bb.2 → bb.3 ⇄ bb.3 → bb.4 → bb.1
+#          outer loop    inner loop
+#
+# Key validation points:
+# 1. Variables crossing inner→outer loop boundaries get LoopTag distances
+# 2. Variables crossing outer→exit boundaries get higher LoopTag multiples
+# 3. Instruction-specific distance progression validates offset calculations
+# 4. Three-tier ranking prevents incorrect spilling decisions
+# 5. **LIMITATION**: This test only validates finite + LoopTag tiers
+#    DEAD distances require explicit getNextUseDistance() API calls
+#    See unit tests for DEAD tier validation
+#
+
+# NOTE: Test three-tier ranking with proper nested loops
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test_proper_nested_loops ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:sgpr_32 = S_MOV_B32 10
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:sgpr_32 = S_MOV_B32 5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Instr: %2:sgpr_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Instr: %8:sgpr_32 = S_MOV_B32 999
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Instr: S_BRANCH %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %3:sgpr_32 = PHI %2, %bb.0, %7, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %8[ LoopTag+4 ]
+# CHECK: Instr: S_CMP_LT_I32 %3, %0, implicit-def $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %8[ LoopTag+3 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Instr: S_CBRANCH_SCC1 %bb.2, implicit $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %8[ LoopTag+2 ]
+# CHECK: Vreg: %3[ 9 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %8[ LoopTag+1 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %8[ LoopTag+1 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %4:sgpr_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %8[ LoopTag+12 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %8[ LoopTag+11 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %8[ LoopTag+11 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %5:sgpr_32 = PHI %4, %bb.2, %6, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+8 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %8[ LoopTag*2+11 ]
+# CHECK: Vreg: %3[ LoopTag+6 ]
+# CHECK: Instr: S_NOP 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+7 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %8[ LoopTag*2+10 ]
+# CHECK: Vreg: %3[ LoopTag+5 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Instr: S_CMP_LT_I32 %5, %1, implicit-def $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+6 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %8[ LoopTag*2+9 ]
+# CHECK: Vreg: %3[ LoopTag+4 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: %6:sgpr_32 = S_ADD_U32 %5, 1, implicit-def $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+5 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %8[ LoopTag*2+8 ]
+# CHECK: Vreg: %3[ LoopTag+3 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Instr: S_CBRANCH_SCC1 %bb.3, implicit $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+4 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %8[ LoopTag*2+7 ]
+# CHECK: Vreg: %3[ LoopTag+2 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+3 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %8[ LoopTag*2+6 ]
+# CHECK: Vreg: %3[ LoopTag+1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+3 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %8[ LoopTag*2+6 ]
+# CHECK: Vreg: %3[ LoopTag+1 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %7:sgpr_32 = S_ADD_U32 %3, 1, implicit-def $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %8[ LoopTag+5 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %8[ LoopTag+4 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %8[ LoopTag+4 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %9:sgpr_32 = S_ADD_U32 %3, %8, implicit-def $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Instr: S_ENDPGM 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+---
+name:            test_proper_nested_loops
+alignment:       1
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sgpr_32 }  # outer_limit
+  - { id: 1, class: sgpr_32 }  # inner_limit  
+  - { id: 2, class: sgpr_32 }  # outer_i
+  - { id: 3, class: sgpr_32 }  # outer_phi
+  - { id: 4, class: sgpr_32 }  # inner_i
+  - { id: 5, class: sgpr_32 }  # inner_phi
+  - { id: 6, class: sgpr_32 }  # inner_next
+  - { id: 7, class: sgpr_32 }  # outer_next
+  - { id: 8, class: sgpr_32 } # var_defined_in_outer_exits_to_end
+  - { id: 9, class: sgpr_32 } # final_result
+body: |
+  bb.0:
+    %0:sgpr_32 = S_MOV_B32 10
+    %1:sgpr_32 = S_MOV_B32 5
+    %2:sgpr_32 = S_MOV_B32 0
+    %8:sgpr_32 = S_MOV_B32 999
+    S_BRANCH %bb.1
+
+  bb.1:
+    %3:sgpr_32 = PHI %2, %bb.0, %7, %bb.4
+    S_CMP_LT_I32 %3, %0, implicit-def $scc
+    S_CBRANCH_SCC1 %bb.2, implicit $scc
+    S_BRANCH %bb.5
+
+  bb.2:
+    %4:sgpr_32 = S_MOV_B32 0
+    S_BRANCH %bb.3
+
+  bb.3:
+    %5:sgpr_32 = PHI %4, %bb.2, %6, %bb.3
+    S_NOP 0
+    S_CMP_LT_I32 %5, %1, implicit-def $scc
+    %6:sgpr_32 = S_ADD_U32 %5, 1, implicit-def $scc
+    S_CBRANCH_SCC1 %bb.3, implicit $scc
+    S_BRANCH %bb.4
+
+  bb.4:
+    %7:sgpr_32 = S_ADD_U32 %3, 1, implicit-def $scc
+    S_BRANCH %bb.1
+
+  bb.5:
+    %9:sgpr_32 = S_ADD_U32 %3, %8, implicit-def $scc
+    S_ENDPGM 0
+
+
+# Test 1: Basic finite distances in entry block - instruction-specific validation
+
+# Test 2: Three-tier ranking in inner loop - exact instruction context
+
+# Test 3: Loop exit distances validation
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three_loops_sequence_nested_in_outer_loop.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three_loops_sequence_nested_in_outer_loop.mir
new file mode 100644
index 0000000000000..99ce35b8318d4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three_loops_sequence_nested_in_outer_loop.mir
@@ -0,0 +1,5011 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#                      bb.0.entry
+#                          |
+#                      bb.1.loop1
+#                          |
+#                       bb.2.bb
+#                        / |
+#    bb.3.loop3.preheader  |
+#              |           |
+#    +---->bb.8.loop3      |
+#    +---------+           |
+#              |           |
+#    bb.9.loop4.preheader  |
+#              |           |
+#    +--->bb.10.loop4      |
+#    +---------+           |
+#              |           |
+#    bb.12.exit.loopexit1  |
+#                    \     |
+#                   bb.7.Flow
+#                    /     |
+#    bb.4.loop2.preheader  |
+#              |           |
+#    +---->bb.6.loop2      |
+#    +---------+           |
+#              |           |
+#    bb.11.exit.loopexit   |
+#                    \     |
+#                   bb.5.Flow12
+#                       |
+#                   bb.13.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test16 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr16
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr15
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 126 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr14
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 125 ]
+# CHECK: Vreg: %1[ 161 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 124 ]
+# CHECK: Vreg: %2[ 124 ]
+# CHECK: Vreg: %1[ 160 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 123 ]
+# CHECK: Vreg: %2[ 123 ]
+# CHECK: Vreg: %1[ 159 ]
+# CHECK: Vreg: %3[ 114 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 122 ]
+# CHECK: Vreg: %2[ 122 ]
+# CHECK: Vreg: %4[ 101 ]
+# CHECK: Vreg: %1[ 158 ]
+# CHECK: Vreg: %3[ 113 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 121 ]
+# CHECK: Vreg: %2[ 121 ]
+# CHECK: Vreg: %4[ 100 ]
+# CHECK: Vreg: %1[ 157 ]
+# CHECK: Vreg: %3[ 112 ]
+# CHECK: Vreg: %5[ 11 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 120 ]
+# CHECK: Vreg: %2[ 120 ]
+# CHECK: Vreg: %4[ 99 ]
+# CHECK: Vreg: %6[ 10 ]
+# CHECK: Vreg: %1[ 156 ]
+# CHECK: Vreg: %3[ 111 ]
+# CHECK: Vreg: %5[ 10 ]
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 119 ]
+# CHECK: Vreg: %7[ 10 ]
+# CHECK: Vreg: %2[ 119 ]
+# CHECK: Vreg: %4[ 98 ]
+# CHECK: Vreg: %6[ 9 ]
+# CHECK: Vreg: %1[ 155 ]
+# CHECK: Vreg: %3[ 110 ]
+# CHECK: Vreg: %5[ 9 ]
+# CHECK: Instr: %9:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 118 ]
+# CHECK: Vreg: %7[ 9 ]
+# CHECK: Vreg: %2[ 118 ]
+# CHECK: Vreg: %4[ 97 ]
+# CHECK: Vreg: %6[ 8 ]
+# CHECK: Vreg: %1[ 154 ]
+# CHECK: Vreg: %8[ 9 ]
+# CHECK: Vreg: %3[ 109 ]
+# CHECK: Vreg: %5[ 8 ]
+# CHECK: Instr: %10:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 117 ]
+# CHECK: Vreg: %7[ 8 ]
+# CHECK: Vreg: %2[ 117 ]
+# CHECK: Vreg: %9[ 9 ]
+# CHECK: Vreg: %4[ 96 ]
+# CHECK: Vreg: %6[ 7 ]
+# CHECK: Vreg: %1[ 153 ]
+# CHECK: Vreg: %8[ 8 ]
+# CHECK: Vreg: %3[ 108 ]
+# CHECK: Vreg: %5[ 7 ]
+# CHECK: Instr: %11:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 116 ]
+# CHECK: Vreg: %7[ 7 ]
+# CHECK: Vreg: %2[ 116 ]
+# CHECK: Vreg: %9[ 8 ]
+# CHECK: Vreg: %4[ 95 ]
+# CHECK: Vreg: %6[ 6 ]
+# CHECK: Vreg: %1[ 152 ]
+# CHECK: Vreg: %8[ 7 ]
+# CHECK: Vreg: %3[ 107 ]
+# CHECK: Vreg: %10[ 8 ]
+# CHECK: Vreg: %5[ 6 ]
+# CHECK: Instr: %12:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 115 ]
+# CHECK: Vreg: %7[ 6 ]
+# CHECK: Vreg: %2[ 115 ]
+# CHECK: Vreg: %9[ 7 ]
+# CHECK: Vreg: %4[ 94 ]
+# CHECK: Vreg: %11[ 8 ]
+# CHECK: Vreg: %6[ 5 ]
+# CHECK: Vreg: %1[ 151 ]
+# CHECK: Vreg: %8[ 6 ]
+# CHECK: Vreg: %3[ 106 ]
+# CHECK: Vreg: %10[ 7 ]
+# CHECK: Vreg: %5[ 5 ]
+# CHECK: Instr: %13:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 114 ]
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %2[ 114 ]
+# CHECK: Vreg: %9[ 6 ]
+# CHECK: Vreg: %4[ 93 ]
+# CHECK: Vreg: %11[ 7 ]
+# CHECK: Vreg: %6[ 4 ]
+# CHECK: Vreg: %1[ 150 ]
+# CHECK: Vreg: %8[ 5 ]
+# CHECK: Vreg: %3[ 105 ]
+# CHECK: Vreg: %10[ 6 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Vreg: %12[ 7 ]
+# CHECK: Instr: %14:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 113 ]
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %2[ 113 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %4[ 92 ]
+# CHECK: Vreg: %11[ 6 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %1[ 149 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: Vreg: %3[ 104 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Vreg: %12[ 6 ]
+# CHECK: Instr: %15:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 112 ]
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %2[ 112 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 91 ]
+# CHECK: Vreg: %11[ 5 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %13[ 6 ]
+# CHECK: Vreg: %1[ 148 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %3[ 103 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Vreg: %12[ 5 ]
+# CHECK: Instr: %16:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 111 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %14[ 5 ]
+# CHECK: Vreg: %2[ 111 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 90 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %13[ 5 ]
+# CHECK: Vreg: %1[ 147 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %3[ 102 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Vreg: %12[ 4 ]
+# CHECK: Instr: %17:vreg_64 = REG_SEQUENCE killed %6, %subreg.sub0, killed %5, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 110 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %14[ 4 ]
+# CHECK: Vreg: %2[ 110 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %16[ 5 ]
+# CHECK: Vreg: %4[ 89 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %1[ 146 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %3[ 101 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %12[ 3 ]
+# CHECK: Instr: %18:vreg_64 = REG_SEQUENCE killed %8, %subreg.sub0, killed %7, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 109 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %2[ 109 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %16[ 4 ]
+# CHECK: Vreg: %4[ 88 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %1[ 145 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %3[ 100 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %17[ 46 ]
+# CHECK: Vreg: %12[ 2 ]
+# CHECK: Instr: %19:vreg_64 = REG_SEQUENCE killed %10, %subreg.sub0, killed %9, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 108 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %2[ 108 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %16[ 3 ]
+# CHECK: Vreg: %4[ 87 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %18:sub0[ 53 ]
+# CHECK: Vreg: %18:sub1[ 54 ]
+# CHECK: Vreg: %18[ 141 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 144 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %3[ 99 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %17[ 45 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: %20:vreg_64 = REG_SEQUENCE killed %12, %subreg.sub0, killed %11, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 107 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %2[ 107 ]
+# CHECK: Vreg: %16[ 2 ]
+# CHECK: Vreg: %4[ 86 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %18:sub0[ 52 ]
+# CHECK: Vreg: %18:sub1[ 53 ]
+# CHECK: Vreg: %18[ 140 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 143 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %3[ 98 ]
+# CHECK: Vreg: %17[ 44 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Vreg: %19[ 98 ]
+# CHECK: Instr: %21:vreg_64 = REG_SEQUENCE killed %14, %subreg.sub0, killed %13, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 106 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %2[ 106 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %4[ 85 ]
+# CHECK: Vreg: %18:sub0[ 51 ]
+# CHECK: Vreg: %18:sub1[ 52 ]
+# CHECK: Vreg: %18[ 139 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %20[ 92 ]
+# CHECK: Vreg: %1[ 142 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %3[ 97 ]
+# CHECK: Vreg: %17[ 43 ]
+# CHECK: Vreg: %19[ 97 ]
+# CHECK: Instr: %22:vreg_64 = REG_SEQUENCE killed %16, %subreg.sub0, killed %15, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 105 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %2[ 105 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %4[ 84 ]
+# CHECK: Vreg: %18:sub0[ 50 ]
+# CHECK: Vreg: %18:sub1[ 51 ]
+# CHECK: Vreg: %18[ 138 ]
+# CHECK: Vreg: %20[ 91 ]
+# CHECK: Vreg: %1[ 141 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %3[ 96 ]
+# CHECK: Vreg: %17[ 42 ]
+# CHECK: Vreg: %19[ 96 ]
+# CHECK: Instr: %23:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 104 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %2[ 104 ]
+# CHECK: Vreg: %4[ 83 ]
+# CHECK: Vreg: %18:sub0[ 49 ]
+# CHECK: Vreg: %18:sub1[ 50 ]
+# CHECK: Vreg: %18[ 137 ]
+# CHECK: Vreg: %20[ 90 ]
+# CHECK: Vreg: %1[ 140 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 95 ]
+# CHECK: Vreg: %17[ 41 ]
+# CHECK: Vreg: %19[ 95 ]
+# CHECK: Instr: %24:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 103 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %2[ 103 ]
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %4[ 82 ]
+# CHECK: Vreg: %18:sub0[ 48 ]
+# CHECK: Vreg: %18:sub1[ 49 ]
+# CHECK: Vreg: %18[ 136 ]
+# CHECK: Vreg: %20[ 89 ]
+# CHECK: Vreg: %1[ 139 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 94 ]
+# CHECK: Vreg: %17[ 40 ]
+# CHECK: Vreg: %19[ 94 ]
+# CHECK: Instr: %25:vgpr_32 = V_LSHL_OR_B32_e64 killed %24, 8, killed %23, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 102 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %2[ 102 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %4[ 81 ]
+# CHECK: Vreg: %18:sub0[ 47 ]
+# CHECK: Vreg: %18:sub1[ 48 ]
+# CHECK: Vreg: %18[ 135 ]
+# CHECK: Vreg: %20[ 88 ]
+# CHECK: Vreg: %1[ 138 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %3[ 93 ]
+# CHECK: Vreg: %17[ 39 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %19[ 93 ]
+# CHECK: Instr: %26:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 101 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %2[ 101 ]
+# CHECK: Vreg: %4[ 80 ]
+# CHECK: Vreg: %18:sub0[ 46 ]
+# CHECK: Vreg: %18:sub1[ 47 ]
+# CHECK: Vreg: %18[ 134 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %20[ 87 ]
+# CHECK: Vreg: %1[ 137 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 92 ]
+# CHECK: Vreg: %17[ 38 ]
+# CHECK: Vreg: %19[ 92 ]
+# CHECK: Instr: %27:vgpr_32 = GLOBAL_LOAD_UBYTE %22, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 100 ]
+# CHECK: Vreg: %26[ 1 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %2[ 100 ]
+# CHECK: Vreg: %4[ 79 ]
+# CHECK: Vreg: %18:sub0[ 45 ]
+# CHECK: Vreg: %18:sub1[ 46 ]
+# CHECK: Vreg: %18[ 133 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %20[ 86 ]
+# CHECK: Vreg: %1[ 136 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ 91 ]
+# CHECK: Vreg: %17[ 37 ]
+# CHECK: Vreg: %19[ 91 ]
+# CHECK: Instr: %28:vgpr_32 = V_LSHL_OR_B32_e64 killed %27, 8, killed %26, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 99 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %2[ 99 ]
+# CHECK: Vreg: %4[ 78 ]
+# CHECK: Vreg: %18:sub0[ 44 ]
+# CHECK: Vreg: %18:sub1[ 45 ]
+# CHECK: Vreg: %18[ 132 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %20[ 85 ]
+# CHECK: Vreg: %1[ 135 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %22[ 32 ]
+# CHECK: Vreg: %3[ 90 ]
+# CHECK: Vreg: %17[ 36 ]
+# CHECK: Vreg: %19[ 90 ]
+# CHECK: Instr: %29:vgpr_32 = V_LSHL_OR_B32_e64 killed %28, 16, killed %25, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 98 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %2[ 98 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %18:sub0[ 43 ]
+# CHECK: Vreg: %18:sub1[ 44 ]
+# CHECK: Vreg: %18[ 131 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %20[ 84 ]
+# CHECK: Vreg: %1[ 134 ]
+# CHECK: Vreg: %22[ 31 ]
+# CHECK: Vreg: %3[ 89 ]
+# CHECK: Vreg: %17[ 35 ]
+# CHECK: Vreg: %19[ 89 ]
+# CHECK: Instr: %30:sreg_32 = S_MOV_B32 1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 97 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %2[ 97 ]
+# CHECK: Vreg: %4[ 76 ]
+# CHECK: Vreg: %18:sub0[ 42 ]
+# CHECK: Vreg: %18:sub1[ 43 ]
+# CHECK: Vreg: %18[ 130 ]
+# CHECK: Vreg: %20[ 83 ]
+# CHECK: Vreg: %1[ 133 ]
+# CHECK: Vreg: %22[ 30 ]
+# CHECK: Vreg: %3[ 88 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17[ 34 ]
+# CHECK: Vreg: %19[ 88 ]
+# CHECK: Instr: %31:vgpr_32 = V_ADD_U32_e64 1, %29, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 96 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 96 ]
+# CHECK: Vreg: %4[ 75 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %18:sub0[ 41 ]
+# CHECK: Vreg: %18:sub1[ 42 ]
+# CHECK: Vreg: %18[ 129 ]
+# CHECK: Vreg: %20[ 82 ]
+# CHECK: Vreg: %1[ 132 ]
+# CHECK: Vreg: %22[ 29 ]
+# CHECK: Vreg: %3[ 87 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 33 ]
+# CHECK: Vreg: %19[ 87 ]
+# CHECK: Instr: %32:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 95 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %2[ 95 ]
+# CHECK: Vreg: %4[ 74 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %18:sub0[ 40 ]
+# CHECK: Vreg: %18:sub1[ 41 ]
+# CHECK: Vreg: %18[ 128 ]
+# CHECK: Vreg: %20[ 81 ]
+# CHECK: Vreg: %1[ 131 ]
+# CHECK: Vreg: %22[ 28 ]
+# CHECK: Vreg: %3[ 86 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17[ 32 ]
+# CHECK: Vreg: %31[ 1 ]
+# CHECK: Vreg: %19[ 86 ]
+# CHECK: Instr: %33:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 94 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 94 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18:sub0[ 39 ]
+# CHECK: Vreg: %18:sub1[ 40 ]
+# CHECK: Vreg: %18[ 127 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 80 ]
+# CHECK: Vreg: %1[ 130 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %3[ 85 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 31 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19[ 85 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 94 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 94 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18:sub0[ 39 ]
+# CHECK: Vreg: %18:sub1[ 40 ]
+# CHECK: Vreg: %18[ 127 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %20[ 80 ]
+# CHECK: Vreg: %1[ 130 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %3[ 85 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 31 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19[ 85 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %34:sreg_32 = PHI %33, %bb.0, %35, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+94 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+94 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %18:sub0[ 39 ]
+# CHECK: Vreg: %18:sub1[ 40 ]
+# CHECK: Vreg: %18[ LoopTag+127 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+80 ]
+# CHECK: Vreg: %1[ LoopTag+130 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %3[ LoopTag+85 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 31 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+85 ]
+# CHECK: Instr: %36:vgpr_32 = PHI %31, %bb.0, %37, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+94 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+94 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %18:sub0[ 39 ]
+# CHECK: Vreg: %18:sub1[ 40 ]
+# CHECK: Vreg: %18[ LoopTag+127 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+80 ]
+# CHECK: Vreg: %1[ LoopTag+130 ]
+# CHECK: Vreg: %34[ 74 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %3[ LoopTag+85 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 31 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+85 ]
+# CHECK: Instr: %38:sreg_32 = PHI %32, %bb.0, %39, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+94 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+94 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18:sub0[ 39 ]
+# CHECK: Vreg: %18:sub1[ 40 ]
+# CHECK: Vreg: %18[ LoopTag+127 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+80 ]
+# CHECK: Vreg: %1[ LoopTag+130 ]
+# CHECK: Vreg: %34[ 74 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %3[ LoopTag+85 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 58 ]
+# CHECK: Vreg: %17[ 31 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+85 ]
+# CHECK: Instr: %40:sreg_32 = PHI %30, %bb.0, %41, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+94 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+94 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %18:sub0[ 39 ]
+# CHECK: Vreg: %18:sub1[ 40 ]
+# CHECK: Vreg: %18[ LoopTag+127 ]
+# CHECK: Vreg: %20[ LoopTag+80 ]
+# CHECK: Vreg: %1[ LoopTag+130 ]
+# CHECK: Vreg: %34[ 74 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %3[ LoopTag+85 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 58 ]
+# CHECK: Vreg: %17[ 31 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %38[ 13 ]
+# CHECK: Vreg: %19[ LoopTag+85 ]
+# CHECK: Instr: %42:vgpr_32 = PHI %29, %bb.0, %43, %bb.1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+94 ]
+# CHECK: Vreg: %40[ 8 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+94 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %18:sub0[ 39 ]
+# CHECK: Vreg: %18:sub1[ 40 ]
+# CHECK: Vreg: %18[ LoopTag+127 ]
+# CHECK: Vreg: %20[ LoopTag+80 ]
+# CHECK: Vreg: %1[ LoopTag+130 ]
+# CHECK: Vreg: %34[ 74 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %3[ LoopTag+85 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 58 ]
+# CHECK: Vreg: %17[ 31 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %38[ 13 ]
+# CHECK: Vreg: %19[ LoopTag+85 ]
+# CHECK: Instr: %44:vgpr_32 = GLOBAL_LOAD_UBYTE %21, 0, 0, implicit $exec :: (load (s8) from %ir.p2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+93 ]
+# CHECK: Vreg: %40[ 7 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+93 ]
+# CHECK: Vreg: %42[ LoopTag+105 ]
+# CHECK: Vreg: %4[ 72 ]
+# CHECK: Vreg: %18:sub0[ 38 ]
+# CHECK: Vreg: %18:sub1[ 39 ]
+# CHECK: Vreg: %18[ LoopTag+126 ]
+# CHECK: Vreg: %20[ LoopTag+79 ]
+# CHECK: Vreg: %1[ LoopTag+129 ]
+# CHECK: Vreg: %34[ 73 ]
+# CHECK: Vreg: %22[ 26 ]
+# CHECK: Vreg: %3[ LoopTag+84 ]
+# CHECK: Vreg: %29[ 28 ]
+# CHECK: Vreg: %36[ 57 ]
+# CHECK: Vreg: %17[ 30 ]
+# CHECK: Vreg: %38[ 12 ]
+# CHECK: Vreg: %19[ LoopTag+84 ]
+# CHECK: Instr: %45:vgpr_32 = GLOBAL_LOAD_UBYTE %21, 1, 0, implicit $exec :: (load (s8) from %ir.p2 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+92 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+92 ]
+# CHECK: Vreg: %42[ LoopTag+104 ]
+# CHECK: Vreg: %4[ 71 ]
+# CHECK: Vreg: %18:sub0[ 37 ]
+# CHECK: Vreg: %18:sub1[ 38 ]
+# CHECK: Vreg: %18[ LoopTag+125 ]
+# CHECK: Vreg: %44[ 1 ]
+# CHECK: Vreg: %20[ LoopTag+78 ]
+# CHECK: Vreg: %1[ LoopTag+128 ]
+# CHECK: Vreg: %34[ 72 ]
+# CHECK: Vreg: %22[ 25 ]
+# CHECK: Vreg: %3[ LoopTag+83 ]
+# CHECK: Vreg: %29[ 27 ]
+# CHECK: Vreg: %36[ 56 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %38[ 11 ]
+# CHECK: Vreg: %19[ LoopTag+83 ]
+# CHECK: Instr: %46:vgpr_32 = V_LSHL_OR_B32_e64 killed %45, 8, killed %44, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+91 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+91 ]
+# CHECK: Vreg: %42[ LoopTag+103 ]
+# CHECK: Vreg: %4[ 70 ]
+# CHECK: Vreg: %18:sub0[ 36 ]
+# CHECK: Vreg: %18:sub1[ 37 ]
+# CHECK: Vreg: %18[ LoopTag+124 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+77 ]
+# CHECK: Vreg: %1[ LoopTag+127 ]
+# CHECK: Vreg: %34[ 71 ]
+# CHECK: Vreg: %22[ 24 ]
+# CHECK: Vreg: %3[ LoopTag+82 ]
+# CHECK: Vreg: %29[ 26 ]
+# CHECK: Vreg: %36[ 55 ]
+# CHECK: Vreg: %17[ 28 ]
+# CHECK: Vreg: %38[ 10 ]
+# CHECK: Vreg: %19[ LoopTag+82 ]
+# CHECK: Instr: %47:vgpr_32 = GLOBAL_LOAD_UBYTE %21, 2, 0, implicit $exec :: (load (s8) from %ir.p2 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+90 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+90 ]
+# CHECK: Vreg: %42[ LoopTag+102 ]
+# CHECK: Vreg: %4[ 69 ]
+# CHECK: Vreg: %18:sub0[ 35 ]
+# CHECK: Vreg: %18:sub1[ 36 ]
+# CHECK: Vreg: %18[ LoopTag+123 ]
+# CHECK: Vreg: %20[ LoopTag+76 ]
+# CHECK: Vreg: %1[ LoopTag+126 ]
+# CHECK: Vreg: %46[ 3 ]
+# CHECK: Vreg: %34[ 70 ]
+# CHECK: Vreg: %22[ 23 ]
+# CHECK: Vreg: %3[ LoopTag+81 ]
+# CHECK: Vreg: %29[ 25 ]
+# CHECK: Vreg: %36[ 54 ]
+# CHECK: Vreg: %17[ 27 ]
+# CHECK: Vreg: %38[ 9 ]
+# CHECK: Vreg: %19[ LoopTag+81 ]
+# CHECK: Instr: %48:vgpr_32 = GLOBAL_LOAD_UBYTE %21, 3, 0, implicit $exec :: (load (s8) from %ir.p2 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+89 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ LoopTag+89 ]
+# CHECK: Vreg: %47[ 1 ]
+# CHECK: Vreg: %42[ LoopTag+101 ]
+# CHECK: Vreg: %4[ 68 ]
+# CHECK: Vreg: %18:sub0[ 34 ]
+# CHECK: Vreg: %18:sub1[ 35 ]
+# CHECK: Vreg: %18[ LoopTag+122 ]
+# CHECK: Vreg: %20[ LoopTag+75 ]
+# CHECK: Vreg: %1[ LoopTag+125 ]
+# CHECK: Vreg: %46[ 2 ]
+# CHECK: Vreg: %34[ 69 ]
+# CHECK: Vreg: %22[ 22 ]
+# CHECK: Vreg: %3[ LoopTag+80 ]
+# CHECK: Vreg: %29[ 24 ]
+# CHECK: Vreg: %36[ 53 ]
+# CHECK: Vreg: %17[ 26 ]
+# CHECK: Vreg: %38[ 8 ]
+# CHECK: Vreg: %19[ LoopTag+80 ]
+# CHECK: Instr: %49:vgpr_32 = V_LSHL_OR_B32_e64 killed %48, 8, killed %47, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+88 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 73 ]
+# CHECK: Vreg: %2[ LoopTag+88 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+100 ]
+# CHECK: Vreg: %4[ 67 ]
+# CHECK: Vreg: %18:sub0[ 33 ]
+# CHECK: Vreg: %18:sub1[ 34 ]
+# CHECK: Vreg: %18[ LoopTag+121 ]
+# CHECK: Vreg: %20[ LoopTag+74 ]
+# CHECK: Vreg: %1[ LoopTag+124 ]
+# CHECK: Vreg: %46[ 1 ]
+# CHECK: Vreg: %34[ 68 ]
+# CHECK: Vreg: %22[ 21 ]
+# CHECK: Vreg: %3[ LoopTag+79 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %29[ 23 ]
+# CHECK: Vreg: %36[ 52 ]
+# CHECK: Vreg: %17[ 25 ]
+# CHECK: Vreg: %38[ 7 ]
+# CHECK: Vreg: %19[ LoopTag+79 ]
+# CHECK: Instr: %50:vgpr_32 = V_LSHL_OR_B32_e64 killed %49, 16, killed %46, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+87 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 72 ]
+# CHECK: Vreg: %2[ LoopTag+87 ]
+# CHECK: Vreg: %42[ LoopTag+99 ]
+# CHECK: Vreg: %4[ 66 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %18:sub0[ 32 ]
+# CHECK: Vreg: %18:sub1[ 33 ]
+# CHECK: Vreg: %18[ LoopTag+120 ]
+# CHECK: Vreg: %20[ LoopTag+73 ]
+# CHECK: Vreg: %1[ LoopTag+123 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %34[ 67 ]
+# CHECK: Vreg: %22[ 20 ]
+# CHECK: Vreg: %3[ LoopTag+78 ]
+# CHECK: Vreg: %29[ 22 ]
+# CHECK: Vreg: %36[ 51 ]
+# CHECK: Vreg: %17[ 24 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Vreg: %19[ LoopTag+78 ]
+# CHECK: Instr: %51:sgpr_32 = S_CVT_F32_U32 %40, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+86 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 71 ]
+# CHECK: Vreg: %2[ LoopTag+86 ]
+# CHECK: Vreg: %42[ LoopTag+98 ]
+# CHECK: Vreg: %4[ 65 ]
+# CHECK: Vreg: %18:sub0[ 31 ]
+# CHECK: Vreg: %18:sub1[ 32 ]
+# CHECK: Vreg: %18[ LoopTag+119 ]
+# CHECK: Vreg: %20[ LoopTag+72 ]
+# CHECK: Vreg: %1[ LoopTag+122 ]
+# CHECK: Vreg: %34[ 66 ]
+# CHECK: Vreg: %22[ 19 ]
+# CHECK: Vreg: %3[ LoopTag+77 ]
+# CHECK: Vreg: %29[ 21 ]
+# CHECK: Vreg: %36[ 50 ]
+# CHECK: Vreg: %17[ 23 ]
+# CHECK: Vreg: %50[ 8 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Vreg: %19[ LoopTag+77 ]
+# CHECK: Instr: %52:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %51, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+85 ]
+# CHECK: Vreg: %40[ 8 ]
+# CHECK: Vreg: %21[ 70 ]
+# CHECK: Vreg: %2[ LoopTag+85 ]
+# CHECK: Vreg: %42[ LoopTag+97 ]
+# CHECK: Vreg: %4[ 64 ]
+# CHECK: Vreg: %18:sub0[ 30 ]
+# CHECK: Vreg: %18:sub1[ 31 ]
+# CHECK: Vreg: %18[ LoopTag+118 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+71 ]
+# CHECK: Vreg: %1[ LoopTag+121 ]
+# CHECK: Vreg: %34[ 65 ]
+# CHECK: Vreg: %22[ 18 ]
+# CHECK: Vreg: %3[ LoopTag+76 ]
+# CHECK: Vreg: %29[ 20 ]
+# CHECK: Vreg: %36[ 49 ]
+# CHECK: Vreg: %17[ 22 ]
+# CHECK: Vreg: %50[ 7 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Vreg: %19[ LoopTag+76 ]
+# CHECK: Instr: %53:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %52, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+84 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %40[ 7 ]
+# CHECK: Vreg: %21[ 69 ]
+# CHECK: Vreg: %2[ LoopTag+84 ]
+# CHECK: Vreg: %42[ LoopTag+96 ]
+# CHECK: Vreg: %4[ 63 ]
+# CHECK: Vreg: %18:sub0[ 29 ]
+# CHECK: Vreg: %18:sub1[ 30 ]
+# CHECK: Vreg: %18[ LoopTag+117 ]
+# CHECK: Vreg: %20[ LoopTag+70 ]
+# CHECK: Vreg: %1[ LoopTag+120 ]
+# CHECK: Vreg: %34[ 64 ]
+# CHECK: Vreg: %22[ 17 ]
+# CHECK: Vreg: %3[ LoopTag+75 ]
+# CHECK: Vreg: %29[ 19 ]
+# CHECK: Vreg: %36[ 48 ]
+# CHECK: Vreg: %17[ 21 ]
+# CHECK: Vreg: %50[ 6 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Vreg: %19[ LoopTag+75 ]
+# CHECK: Instr: %54:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %53, 1333788670, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+83 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 68 ]
+# CHECK: Vreg: %2[ LoopTag+83 ]
+# CHECK: Vreg: %42[ LoopTag+95 ]
+# CHECK: Vreg: %4[ 62 ]
+# CHECK: Vreg: %18:sub0[ 28 ]
+# CHECK: Vreg: %18:sub1[ 29 ]
+# CHECK: Vreg: %18[ LoopTag+116 ]
+# CHECK: Vreg: %20[ LoopTag+69 ]
+# CHECK: Vreg: %1[ LoopTag+119 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ 63 ]
+# CHECK: Vreg: %22[ 16 ]
+# CHECK: Vreg: %3[ LoopTag+74 ]
+# CHECK: Vreg: %29[ 18 ]
+# CHECK: Vreg: %36[ 47 ]
+# CHECK: Vreg: %17[ 20 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Vreg: %19[ LoopTag+74 ]
+# CHECK: Instr: %55:sreg_32 = nofpexcept S_CVT_U32_F32 killed %54, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+82 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %21[ 67 ]
+# CHECK: Vreg: %2[ LoopTag+82 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+94 ]
+# CHECK: Vreg: %4[ 61 ]
+# CHECK: Vreg: %18:sub0[ 27 ]
+# CHECK: Vreg: %18:sub1[ 28 ]
+# CHECK: Vreg: %18[ LoopTag+115 ]
+# CHECK: Vreg: %20[ LoopTag+68 ]
+# CHECK: Vreg: %1[ LoopTag+118 ]
+# CHECK: Vreg: %34[ 62 ]
+# CHECK: Vreg: %22[ 15 ]
+# CHECK: Vreg: %3[ LoopTag+73 ]
+# CHECK: Vreg: %29[ 17 ]
+# CHECK: Vreg: %36[ 46 ]
+# CHECK: Vreg: %17[ 19 ]
+# CHECK: Vreg: %50[ 4 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Vreg: %19[ LoopTag+73 ]
+# CHECK: Instr: %56:sreg_32 = S_MUL_I32 %38, %55
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+81 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %21[ 66 ]
+# CHECK: Vreg: %2[ LoopTag+81 ]
+# CHECK: Vreg: %42[ LoopTag+93 ]
+# CHECK: Vreg: %4[ 60 ]
+# CHECK: Vreg: %18:sub0[ 26 ]
+# CHECK: Vreg: %18:sub1[ 27 ]
+# CHECK: Vreg: %18[ LoopTag+114 ]
+# CHECK: Vreg: %20[ LoopTag+67 ]
+# CHECK: Vreg: %1[ LoopTag+117 ]
+# CHECK: Vreg: %34[ 61 ]
+# CHECK: Vreg: %22[ 14 ]
+# CHECK: Vreg: %3[ LoopTag+72 ]
+# CHECK: Vreg: %29[ 16 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 45 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %50[ 3 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+72 ]
+# CHECK: Instr: %57:sreg_32 = S_MUL_HI_U32 %55, killed %56
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+80 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %21[ 65 ]
+# CHECK: Vreg: %2[ LoopTag+80 ]
+# CHECK: Vreg: %42[ LoopTag+92 ]
+# CHECK: Vreg: %4[ 59 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %18:sub0[ 25 ]
+# CHECK: Vreg: %18:sub1[ 26 ]
+# CHECK: Vreg: %18[ LoopTag+113 ]
+# CHECK: Vreg: %20[ LoopTag+66 ]
+# CHECK: Vreg: %1[ LoopTag+116 ]
+# CHECK: Vreg: %34[ 60 ]
+# CHECK: Vreg: %22[ 13 ]
+# CHECK: Vreg: %3[ LoopTag+71 ]
+# CHECK: Vreg: %29[ 15 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 44 ]
+# CHECK: Vreg: %17[ 17 ]
+# CHECK: Vreg: %50[ 2 ]
+# CHECK: Vreg: %38[ 57 ]
+# CHECK: Vreg: %19[ LoopTag+71 ]
+# CHECK: Instr: %58:sreg_32 = S_ADD_I32 killed %55, killed %57, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+79 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 64 ]
+# CHECK: Vreg: %2[ LoopTag+79 ]
+# CHECK: Vreg: %42[ LoopTag+91 ]
+# CHECK: Vreg: %4[ 58 ]
+# CHECK: Vreg: %18:sub0[ 24 ]
+# CHECK: Vreg: %18:sub1[ 25 ]
+# CHECK: Vreg: %18[ LoopTag+112 ]
+# CHECK: Vreg: %20[ LoopTag+65 ]
+# CHECK: Vreg: %1[ LoopTag+115 ]
+# CHECK: Vreg: %34[ 59 ]
+# CHECK: Vreg: %22[ 12 ]
+# CHECK: Vreg: %3[ LoopTag+70 ]
+# CHECK: Vreg: %29[ 14 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ 43 ]
+# CHECK: Vreg: %17[ 16 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Vreg: %38[ 56 ]
+# CHECK: Vreg: %19[ LoopTag+70 ]
+# CHECK: Instr: %59:vgpr_32 = V_MUL_HI_U32_e64 %50, killed %58, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+78 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 63 ]
+# CHECK: Vreg: %2[ LoopTag+78 ]
+# CHECK: Vreg: %42[ LoopTag+90 ]
+# CHECK: Vreg: %4[ 57 ]
+# CHECK: Vreg: %18:sub0[ 23 ]
+# CHECK: Vreg: %18:sub1[ 24 ]
+# CHECK: Vreg: %18[ LoopTag+111 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+64 ]
+# CHECK: Vreg: %1[ LoopTag+114 ]
+# CHECK: Vreg: %34[ 58 ]
+# CHECK: Vreg: %22[ 11 ]
+# CHECK: Vreg: %3[ LoopTag+69 ]
+# CHECK: Vreg: %29[ 13 ]
+# CHECK: Vreg: %36[ 42 ]
+# CHECK: Vreg: %17[ 15 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %38[ 55 ]
+# CHECK: Vreg: %19[ LoopTag+69 ]
+# CHECK: Instr: %60:vgpr_32 = V_MUL_LO_U32_e64 %59, %40, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+77 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 62 ]
+# CHECK: Vreg: %2[ LoopTag+77 ]
+# CHECK: Vreg: %42[ LoopTag+89 ]
+# CHECK: Vreg: %4[ 56 ]
+# CHECK: Vreg: %18:sub0[ 22 ]
+# CHECK: Vreg: %18:sub1[ 23 ]
+# CHECK: Vreg: %18[ LoopTag+110 ]
+# CHECK: Vreg: %20[ LoopTag+63 ]
+# CHECK: Vreg: %1[ LoopTag+113 ]
+# CHECK: Vreg: %34[ 57 ]
+# CHECK: Vreg: %22[ 10 ]
+# CHECK: Vreg: %3[ LoopTag+68 ]
+# CHECK: Vreg: %29[ 12 ]
+# CHECK: Vreg: %36[ 41 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %38[ 54 ]
+# CHECK: Vreg: %19[ LoopTag+68 ]
+# CHECK: Instr: %61:vgpr_32 = V_SUB_U32_e64 %50, killed %60, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+76 ]
+# CHECK: Vreg: %59[ 2 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 61 ]
+# CHECK: Vreg: %2[ LoopTag+76 ]
+# CHECK: Vreg: %42[ LoopTag+88 ]
+# CHECK: Vreg: %4[ 55 ]
+# CHECK: Vreg: %18:sub0[ 21 ]
+# CHECK: Vreg: %18:sub1[ 22 ]
+# CHECK: Vreg: %18[ LoopTag+109 ]
+# CHECK: Vreg: %20[ LoopTag+62 ]
+# CHECK: Vreg: %1[ LoopTag+112 ]
+# CHECK: Vreg: %34[ 56 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %22[ 9 ]
+# CHECK: Vreg: %3[ LoopTag+67 ]
+# CHECK: Vreg: %29[ 11 ]
+# CHECK: Vreg: %36[ 40 ]
+# CHECK: Vreg: %17[ 13 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %38[ 53 ]
+# CHECK: Vreg: %19[ LoopTag+67 ]
+# CHECK: Instr: %62:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %40, %61, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+75 ]
+# CHECK: Vreg: %59[ 1 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 60 ]
+# CHECK: Vreg: %2[ LoopTag+75 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+87 ]
+# CHECK: Vreg: %4[ 54 ]
+# CHECK: Vreg: %18:sub0[ 20 ]
+# CHECK: Vreg: %18:sub1[ 21 ]
+# CHECK: Vreg: %18[ LoopTag+108 ]
+# CHECK: Vreg: %20[ LoopTag+61 ]
+# CHECK: Vreg: %1[ LoopTag+111 ]
+# CHECK: Vreg: %34[ 55 ]
+# CHECK: Vreg: %22[ 8 ]
+# CHECK: Vreg: %3[ LoopTag+66 ]
+# CHECK: Vreg: %29[ 10 ]
+# CHECK: Vreg: %36[ 39 ]
+# CHECK: Vreg: %17[ 12 ]
+# CHECK: Vreg: %50[ LoopTag+71 ]
+# CHECK: Vreg: %38[ 52 ]
+# CHECK: Vreg: %19[ LoopTag+66 ]
+# CHECK: Instr: %63:vgpr_32 = V_ADD_U32_e64 1, %59, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+74 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 59 ]
+# CHECK: Vreg: %2[ LoopTag+74 ]
+# CHECK: Vreg: %61[ 2 ]
+# CHECK: Vreg: %42[ LoopTag+86 ]
+# CHECK: Vreg: %4[ 53 ]
+# CHECK: Vreg: %18:sub0[ 19 ]
+# CHECK: Vreg: %18:sub1[ 20 ]
+# CHECK: Vreg: %18[ LoopTag+107 ]
+# CHECK: Vreg: %20[ LoopTag+60 ]
+# CHECK: Vreg: %1[ LoopTag+110 ]
+# CHECK: Vreg: %34[ 54 ]
+# CHECK: Vreg: %22[ 7 ]
+# CHECK: Vreg: %3[ LoopTag+65 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %36[ 38 ]
+# CHECK: Vreg: %17[ 11 ]
+# CHECK: Vreg: %62[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+70 ]
+# CHECK: Vreg: %38[ 51 ]
+# CHECK: Vreg: %19[ LoopTag+65 ]
+# CHECK: Instr: %64:vgpr_32 = V_CNDMASK_B32_e64 0, killed %59, 0, killed %63, %62, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+73 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 58 ]
+# CHECK: Vreg: %2[ LoopTag+73 ]
+# CHECK: Vreg: %61[ 1 ]
+# CHECK: Vreg: %42[ LoopTag+85 ]
+# CHECK: Vreg: %4[ 52 ]
+# CHECK: Vreg: %18:sub0[ 18 ]
+# CHECK: Vreg: %18:sub1[ 19 ]
+# CHECK: Vreg: %18[ LoopTag+106 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+59 ]
+# CHECK: Vreg: %1[ LoopTag+109 ]
+# CHECK: Vreg: %34[ 53 ]
+# CHECK: Vreg: %22[ 6 ]
+# CHECK: Vreg: %3[ LoopTag+64 ]
+# CHECK: Vreg: %29[ 8 ]
+# CHECK: Vreg: %36[ 37 ]
+# CHECK: Vreg: %17[ 10 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+69 ]
+# CHECK: Vreg: %38[ 50 ]
+# CHECK: Vreg: %19[ LoopTag+64 ]
+# CHECK: Instr: %65:vgpr_32 = V_SUBREV_U32_e64 %40, %61, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+72 ]
+# CHECK: Vreg: %64[ 3 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 57 ]
+# CHECK: Vreg: %2[ LoopTag+72 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+84 ]
+# CHECK: Vreg: %4[ 51 ]
+# CHECK: Vreg: %18:sub0[ 17 ]
+# CHECK: Vreg: %18:sub1[ 18 ]
+# CHECK: Vreg: %18[ LoopTag+105 ]
+# CHECK: Vreg: %20[ LoopTag+58 ]
+# CHECK: Vreg: %1[ LoopTag+108 ]
+# CHECK: Vreg: %34[ 52 ]
+# CHECK: Vreg: %22[ 5 ]
+# CHECK: Vreg: %3[ LoopTag+63 ]
+# CHECK: Vreg: %29[ 7 ]
+# CHECK: Vreg: %36[ 36 ]
+# CHECK: Vreg: %17[ 9 ]
+# CHECK: Vreg: %62[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+68 ]
+# CHECK: Vreg: %38[ 49 ]
+# CHECK: Vreg: %19[ LoopTag+63 ]
+# CHECK: Instr: %66:vgpr_32 = V_CNDMASK_B32_e64 0, killed %61, 0, killed %65, killed %62, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+71 ]
+# CHECK: Vreg: %64[ 2 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 56 ]
+# CHECK: Vreg: %2[ LoopTag+71 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+83 ]
+# CHECK: Vreg: %4[ 50 ]
+# CHECK: Vreg: %18:sub0[ 16 ]
+# CHECK: Vreg: %18:sub1[ 17 ]
+# CHECK: Vreg: %18[ LoopTag+104 ]
+# CHECK: Vreg: %20[ LoopTag+57 ]
+# CHECK: Vreg: %1[ LoopTag+107 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %34[ 51 ]
+# CHECK: Vreg: %22[ 4 ]
+# CHECK: Vreg: %3[ LoopTag+62 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %36[ 35 ]
+# CHECK: Vreg: %17[ 8 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+67 ]
+# CHECK: Vreg: %38[ 48 ]
+# CHECK: Vreg: %19[ LoopTag+62 ]
+# CHECK: Instr: %67:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %40, killed %66, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+70 ]
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 55 ]
+# CHECK: Vreg: %2[ LoopTag+70 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+82 ]
+# CHECK: Vreg: %4[ 49 ]
+# CHECK: Vreg: %18:sub0[ 15 ]
+# CHECK: Vreg: %18:sub1[ 16 ]
+# CHECK: Vreg: %18[ LoopTag+103 ]
+# CHECK: Vreg: %20[ LoopTag+56 ]
+# CHECK: Vreg: %1[ LoopTag+106 ]
+# CHECK: Vreg: %34[ 50 ]
+# CHECK: Vreg: %22[ 3 ]
+# CHECK: Vreg: %3[ LoopTag+61 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %36[ 34 ]
+# CHECK: Vreg: %17[ 7 ]
+# CHECK: Vreg: %50[ LoopTag+66 ]
+# CHECK: Vreg: %38[ 47 ]
+# CHECK: Vreg: %19[ LoopTag+61 ]
+# CHECK: Instr: %68:vgpr_32 = V_ADD_U32_e64 1, %64, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+69 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %21[ 54 ]
+# CHECK: Vreg: %2[ LoopTag+69 ]
+# CHECK: Vreg: %42[ LoopTag+81 ]
+# CHECK: Vreg: %4[ 48 ]
+# CHECK: Vreg: %18:sub0[ 14 ]
+# CHECK: Vreg: %18:sub1[ 15 ]
+# CHECK: Vreg: %18[ LoopTag+102 ]
+# CHECK: Vreg: %20[ LoopTag+55 ]
+# CHECK: Vreg: %1[ LoopTag+105 ]
+# CHECK: Vreg: %34[ 49 ]
+# CHECK: Vreg: %22[ 2 ]
+# CHECK: Vreg: %3[ LoopTag+60 ]
+# CHECK: Vreg: %67[ 1 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %36[ 33 ]
+# CHECK: Vreg: %17[ 6 ]
+# CHECK: Vreg: %50[ LoopTag+65 ]
+# CHECK: Vreg: %38[ 46 ]
+# CHECK: Vreg: %19[ LoopTag+60 ]
+# CHECK: Instr: %69:vgpr_32 = V_CNDMASK_B32_e64 0, killed %64, 0, killed %68, killed %67, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+68 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 53 ]
+# CHECK: Vreg: %2[ LoopTag+68 ]
+# CHECK: Vreg: %42[ LoopTag+80 ]
+# CHECK: Vreg: %4[ 47 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %18:sub0[ 13 ]
+# CHECK: Vreg: %18:sub1[ 14 ]
+# CHECK: Vreg: %18[ LoopTag+101 ]
+# CHECK: Vreg: %20[ LoopTag+54 ]
+# CHECK: Vreg: %1[ LoopTag+104 ]
+# CHECK: Vreg: %34[ 48 ]
+# CHECK: Vreg: %22[ 1 ]
+# CHECK: Vreg: %3[ LoopTag+59 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %36[ 32 ]
+# CHECK: Vreg: %17[ 5 ]
+# CHECK: Vreg: %50[ LoopTag+64 ]
+# CHECK: Vreg: %38[ 45 ]
+# CHECK: Vreg: %19[ LoopTag+59 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %22, killed %69, 0, 0, implicit $exec :: (store (s32) into %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+67 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 52 ]
+# CHECK: Vreg: %2[ LoopTag+67 ]
+# CHECK: Vreg: %42[ LoopTag+79 ]
+# CHECK: Vreg: %4[ 46 ]
+# CHECK: Vreg: %18:sub0[ 12 ]
+# CHECK: Vreg: %18:sub1[ 13 ]
+# CHECK: Vreg: %18[ LoopTag+100 ]
+# CHECK: Vreg: %20[ LoopTag+53 ]
+# CHECK: Vreg: %1[ LoopTag+103 ]
+# CHECK: Vreg: %34[ 47 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %3[ LoopTag+58 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %36[ 31 ]
+# CHECK: Vreg: %17[ 4 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+63 ]
+# CHECK: Vreg: %38[ 44 ]
+# CHECK: Vreg: %19[ LoopTag+58 ]
+# CHECK: Instr: %41:sreg_32 = S_ADD_I32 %40, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+66 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 51 ]
+# CHECK: Vreg: %2[ LoopTag+66 ]
+# CHECK: Vreg: %42[ LoopTag+78 ]
+# CHECK: Vreg: %4[ 45 ]
+# CHECK: Vreg: %18:sub0[ 11 ]
+# CHECK: Vreg: %18:sub1[ 12 ]
+# CHECK: Vreg: %18[ LoopTag+99 ]
+# CHECK: Vreg: %20[ LoopTag+52 ]
+# CHECK: Vreg: %1[ LoopTag+102 ]
+# CHECK: Vreg: %34[ 46 ]
+# CHECK: Vreg: %22[ 77 ]
+# CHECK: Vreg: %3[ LoopTag+57 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %36[ 30 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Vreg: %50[ LoopTag+62 ]
+# CHECK: Vreg: %38[ 43 ]
+# CHECK: Vreg: %19[ LoopTag+57 ]
+# CHECK: Instr: %70:vgpr_32 = V_ADD_U32_e64 %40, %29, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+65 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 50 ]
+# CHECK: Vreg: %2[ LoopTag+65 ]
+# CHECK: Vreg: %42[ LoopTag+77 ]
+# CHECK: Vreg: %4[ 44 ]
+# CHECK: Vreg: %18:sub0[ 10 ]
+# CHECK: Vreg: %18:sub1[ 11 ]
+# CHECK: Vreg: %18[ LoopTag+98 ]
+# CHECK: Vreg: %20[ LoopTag+51 ]
+# CHECK: Vreg: %1[ LoopTag+101 ]
+# CHECK: Vreg: %34[ 45 ]
+# CHECK: Vreg: %41[ 44 ]
+# CHECK: Vreg: %22[ 76 ]
+# CHECK: Vreg: %3[ LoopTag+56 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 29 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %50[ LoopTag+61 ]
+# CHECK: Vreg: %38[ 42 ]
+# CHECK: Vreg: %19[ LoopTag+56 ]
+# CHECK: Instr: %71:vgpr_32 = V_LSHRREV_B32_e64 24, %70, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+64 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 49 ]
+# CHECK: Vreg: %2[ LoopTag+64 ]
+# CHECK: Vreg: %42[ LoopTag+76 ]
+# CHECK: Vreg: %4[ 43 ]
+# CHECK: Vreg: %18:sub0[ 9 ]
+# CHECK: Vreg: %18:sub1[ 10 ]
+# CHECK: Vreg: %18[ LoopTag+97 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+50 ]
+# CHECK: Vreg: %1[ LoopTag+100 ]
+# CHECK: Vreg: %34[ 44 ]
+# CHECK: Vreg: %41[ 43 ]
+# CHECK: Vreg: %22[ 75 ]
+# CHECK: Vreg: %3[ LoopTag+55 ]
+# CHECK: Vreg: %29[ LoopTag+53 ]
+# CHECK: Vreg: %36[ 28 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+60 ]
+# CHECK: Vreg: %38[ 41 ]
+# CHECK: Vreg: %19[ LoopTag+55 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %17, killed %71, 3, 0, implicit $exec :: (store (s8) into %ir.p6 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+63 ]
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %21[ 48 ]
+# CHECK: Vreg: %2[ LoopTag+63 ]
+# CHECK: Vreg: %42[ LoopTag+75 ]
+# CHECK: Vreg: %4[ 42 ]
+# CHECK: Vreg: %18:sub0[ 8 ]
+# CHECK: Vreg: %18:sub1[ 9 ]
+# CHECK: Vreg: %18[ LoopTag+96 ]
+# CHECK: Vreg: %70[ 1 ]
+# CHECK: Vreg: %20[ LoopTag+49 ]
+# CHECK: Vreg: %1[ LoopTag+99 ]
+# CHECK: Vreg: %34[ 43 ]
+# CHECK: Vreg: %41[ 42 ]
+# CHECK: Vreg: %22[ 74 ]
+# CHECK: Vreg: %3[ LoopTag+54 ]
+# CHECK: Vreg: %29[ LoopTag+52 ]
+# CHECK: Vreg: %36[ 27 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+59 ]
+# CHECK: Vreg: %38[ 40 ]
+# CHECK: Vreg: %19[ LoopTag+54 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE_D16_HI %17, %70, 2, 0, implicit $exec :: (store (s8) into %ir.p6 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+62 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %21[ 47 ]
+# CHECK: Vreg: %2[ LoopTag+62 ]
+# CHECK: Vreg: %42[ LoopTag+74 ]
+# CHECK: Vreg: %4[ 41 ]
+# CHECK: Vreg: %18:sub0[ 7 ]
+# CHECK: Vreg: %18:sub1[ 8 ]
+# CHECK: Vreg: %18[ LoopTag+95 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+48 ]
+# CHECK: Vreg: %1[ LoopTag+98 ]
+# CHECK: Vreg: %34[ 42 ]
+# CHECK: Vreg: %41[ 41 ]
+# CHECK: Vreg: %22[ 73 ]
+# CHECK: Vreg: %3[ LoopTag+53 ]
+# CHECK: Vreg: %29[ LoopTag+51 ]
+# CHECK: Vreg: %36[ 26 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+58 ]
+# CHECK: Vreg: %38[ 39 ]
+# CHECK: Vreg: %19[ LoopTag+53 ]
+# CHECK: Instr: %72:vgpr_32 = V_LSHRREV_B32_e64 8, %70, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+61 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %21[ 46 ]
+# CHECK: Vreg: %2[ LoopTag+61 ]
+# CHECK: Vreg: %42[ LoopTag+73 ]
+# CHECK: Vreg: %4[ 40 ]
+# CHECK: Vreg: %18:sub0[ 6 ]
+# CHECK: Vreg: %18:sub1[ 7 ]
+# CHECK: Vreg: %18[ LoopTag+94 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+47 ]
+# CHECK: Vreg: %1[ LoopTag+97 ]
+# CHECK: Vreg: %34[ 41 ]
+# CHECK: Vreg: %41[ 40 ]
+# CHECK: Vreg: %22[ 72 ]
+# CHECK: Vreg: %3[ LoopTag+52 ]
+# CHECK: Vreg: %29[ LoopTag+50 ]
+# CHECK: Vreg: %36[ 25 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+57 ]
+# CHECK: Vreg: %38[ 38 ]
+# CHECK: Vreg: %19[ LoopTag+52 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %17, killed %72, 1, 0, implicit $exec :: (store (s8) into %ir.p6 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+60 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 45 ]
+# CHECK: Vreg: %2[ LoopTag+60 ]
+# CHECK: Vreg: %42[ LoopTag+72 ]
+# CHECK: Vreg: %4[ 39 ]
+# CHECK: Vreg: %18:sub0[ 5 ]
+# CHECK: Vreg: %18:sub1[ 6 ]
+# CHECK: Vreg: %18[ LoopTag+93 ]
+# CHECK: Vreg: %70[ 1 ]
+# CHECK: Vreg: %20[ LoopTag+46 ]
+# CHECK: Vreg: %1[ LoopTag+96 ]
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %34[ 40 ]
+# CHECK: Vreg: %41[ 39 ]
+# CHECK: Vreg: %22[ 71 ]
+# CHECK: Vreg: %3[ LoopTag+51 ]
+# CHECK: Vreg: %29[ LoopTag+49 ]
+# CHECK: Vreg: %36[ 24 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+56 ]
+# CHECK: Vreg: %38[ 37 ]
+# CHECK: Vreg: %19[ LoopTag+51 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %17, %70, 0, 0, implicit $exec :: (store (s8) into %ir.p6, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+59 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 44 ]
+# CHECK: Vreg: %2[ LoopTag+59 ]
+# CHECK: Vreg: %42[ LoopTag+71 ]
+# CHECK: Vreg: %4[ 38 ]
+# CHECK: Vreg: %18:sub0[ 4 ]
+# CHECK: Vreg: %18:sub1[ 5 ]
+# CHECK: Vreg: %18[ LoopTag+92 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+45 ]
+# CHECK: Vreg: %1[ LoopTag+95 ]
+# CHECK: Vreg: %34[ 39 ]
+# CHECK: Vreg: %41[ 38 ]
+# CHECK: Vreg: %22[ 70 ]
+# CHECK: Vreg: %3[ LoopTag+50 ]
+# CHECK: Vreg: %29[ LoopTag+48 ]
+# CHECK: Vreg: %36[ 23 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+55 ]
+# CHECK: Vreg: %38[ 36 ]
+# CHECK: Vreg: %19[ LoopTag+50 ]
+# CHECK: Instr: %73:sreg_32_xm0 = S_ASHR_I32 %40, 31, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+58 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 43 ]
+# CHECK: Vreg: %2[ LoopTag+58 ]
+# CHECK: Vreg: %42[ LoopTag+70 ]
+# CHECK: Vreg: %4[ 37 ]
+# CHECK: Vreg: %18:sub0[ 3 ]
+# CHECK: Vreg: %18:sub1[ 4 ]
+# CHECK: Vreg: %18[ LoopTag+91 ]
+# CHECK: Vreg: %70[ 21 ]
+# CHECK: Vreg: %20[ LoopTag+44 ]
+# CHECK: Vreg: %1[ LoopTag+94 ]
+# CHECK: Vreg: %34[ 38 ]
+# CHECK: Vreg: %41[ 37 ]
+# CHECK: Vreg: %22[ 69 ]
+# CHECK: Vreg: %3[ LoopTag+49 ]
+# CHECK: Vreg: %29[ LoopTag+47 ]
+# CHECK: Vreg: %36[ 22 ]
+# CHECK: Vreg: %17[ 73 ]
+# CHECK: Vreg: %50[ LoopTag+54 ]
+# CHECK: Vreg: %38[ 35 ]
+# CHECK: Vreg: %19[ LoopTag+49 ]
+# CHECK: Instr: %74:sreg_64 = REG_SEQUENCE %40, %subreg.sub0, killed %73, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+57 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 42 ]
+# CHECK: Vreg: %2[ LoopTag+57 ]
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+69 ]
+# CHECK: Vreg: %4[ 36 ]
+# CHECK: Vreg: %18:sub0[ 2 ]
+# CHECK: Vreg: %18:sub1[ 3 ]
+# CHECK: Vreg: %18[ LoopTag+90 ]
+# CHECK: Vreg: %70[ 20 ]
+# CHECK: Vreg: %20[ LoopTag+43 ]
+# CHECK: Vreg: %1[ LoopTag+93 ]
+# CHECK: Vreg: %34[ 37 ]
+# CHECK: Vreg: %41[ 36 ]
+# CHECK: Vreg: %22[ 68 ]
+# CHECK: Vreg: %3[ LoopTag+48 ]
+# CHECK: Vreg: %29[ LoopTag+46 ]
+# CHECK: Vreg: %36[ 21 ]
+# CHECK: Vreg: %17[ 72 ]
+# CHECK: Vreg: %50[ LoopTag+53 ]
+# CHECK: Vreg: %38[ 34 ]
+# CHECK: Vreg: %19[ LoopTag+48 ]
+# CHECK: Instr: %75:sreg_64 = nsw S_LSHL_B64 killed %74, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+56 ]
+# CHECK: Vreg: %40[ 37 ]
+# CHECK: Vreg: %21[ 41 ]
+# CHECK: Vreg: %2[ LoopTag+56 ]
+# CHECK: Vreg: %42[ LoopTag+68 ]
+# CHECK: Vreg: %4[ 35 ]
+# CHECK: Vreg: %18:sub0[ 1 ]
+# CHECK: Vreg: %18:sub1[ 2 ]
+# CHECK: Vreg: %18[ LoopTag+89 ]
+# CHECK: Vreg: %70[ 19 ]
+# CHECK: Vreg: %20[ LoopTag+42 ]
+# CHECK: Vreg: %1[ LoopTag+92 ]
+# CHECK: Vreg: %34[ 36 ]
+# CHECK: Vreg: %41[ 35 ]
+# CHECK: Vreg: %22[ 67 ]
+# CHECK: Vreg: %3[ LoopTag+47 ]
+# CHECK: Vreg: %29[ LoopTag+45 ]
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Vreg: %36[ 20 ]
+# CHECK: Vreg: %17[ 71 ]
+# CHECK: Vreg: %50[ LoopTag+52 ]
+# CHECK: Vreg: %38[ 33 ]
+# CHECK: Vreg: %19[ LoopTag+47 ]
+# CHECK: Instr: %76:vgpr_32, %77:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %18.sub0, %75.sub0, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+55 ]
+# CHECK: Vreg: %40[ 36 ]
+# CHECK: Vreg: %21[ 40 ]
+# CHECK: Vreg: %2[ LoopTag+55 ]
+# CHECK: Vreg: %42[ LoopTag+67 ]
+# CHECK: Vreg: %4[ 34 ]
+# CHECK: Vreg: %75:sub0[ 0 ]
+# CHECK: Vreg: %75:sub1[ 1 ]
+# CHECK: Vreg: %18:sub0[ 0 ]
+# CHECK: Vreg: %18:sub1[ 1 ]
+# CHECK: Vreg: %18[ LoopTag+88 ]
+# CHECK: Vreg: %70[ 18 ]
+# CHECK: Vreg: %20[ LoopTag+41 ]
+# CHECK: Vreg: %1[ LoopTag+91 ]
+# CHECK: Vreg: %34[ 35 ]
+# CHECK: Vreg: %41[ 34 ]
+# CHECK: Vreg: %22[ 66 ]
+# CHECK: Vreg: %3[ LoopTag+46 ]
+# CHECK: Vreg: %29[ LoopTag+44 ]
+# CHECK: Vreg: %36[ 19 ]
+# CHECK: Vreg: %17[ 70 ]
+# CHECK: Vreg: %50[ LoopTag+51 ]
+# CHECK: Vreg: %38[ 32 ]
+# CHECK: Vreg: %19[ LoopTag+46 ]
+# CHECK: Instr: %78:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %75.sub1, %18.sub1, killed %77, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+54 ]
+# CHECK: Vreg: %40[ 35 ]
+# CHECK: Vreg: %21[ 39 ]
+# CHECK: Vreg: %2[ LoopTag+54 ]
+# CHECK: Vreg: %42[ LoopTag+66 ]
+# CHECK: Vreg: %4[ 33 ]
+# CHECK: Vreg: %75:sub1[ 0 ]
+# CHECK: Vreg: %18:sub1[ 0 ]
+# CHECK: Vreg: %18:sub0[ 77 ]
+# CHECK: Vreg: %18[ LoopTag+87 ]
+# CHECK: Vreg: %70[ 17 ]
+# CHECK: Vreg: %77[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+40 ]
+# CHECK: Vreg: %1[ LoopTag+90 ]
+# CHECK: Vreg: %34[ 34 ]
+# CHECK: Vreg: %41[ 33 ]
+# CHECK: Vreg: %22[ 65 ]
+# CHECK: Vreg: %3[ LoopTag+45 ]
+# CHECK: Vreg: %29[ LoopTag+43 ]
+# CHECK: Vreg: %36[ 18 ]
+# CHECK: Vreg: %17[ 69 ]
+# CHECK: Vreg: %50[ LoopTag+50 ]
+# CHECK: Vreg: %76[ 1 ]
+# CHECK: Vreg: %38[ 31 ]
+# CHECK: Vreg: %19[ LoopTag+45 ]
+# CHECK: Instr: %79:vreg_64 = REG_SEQUENCE killed %76, %subreg.sub0, killed %78, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+53 ]
+# CHECK: Vreg: %78[ 0 ]
+# CHECK: Vreg: %40[ 34 ]
+# CHECK: Vreg: %21[ 38 ]
+# CHECK: Vreg: %2[ LoopTag+53 ]
+# CHECK: Vreg: %42[ LoopTag+65 ]
+# CHECK: Vreg: %4[ 32 ]
+# CHECK: Vreg: %18:sub0[ 76 ]
+# CHECK: Vreg: %18:sub1[ 77 ]
+# CHECK: Vreg: %18[ LoopTag+86 ]
+# CHECK: Vreg: %70[ 16 ]
+# CHECK: Vreg: %20[ LoopTag+39 ]
+# CHECK: Vreg: %1[ LoopTag+89 ]
+# CHECK: Vreg: %34[ 33 ]
+# CHECK: Vreg: %41[ 32 ]
+# CHECK: Vreg: %22[ 64 ]
+# CHECK: Vreg: %3[ LoopTag+44 ]
+# CHECK: Vreg: %29[ LoopTag+42 ]
+# CHECK: Vreg: %36[ 17 ]
+# CHECK: Vreg: %17[ 68 ]
+# CHECK: Vreg: %50[ LoopTag+49 ]
+# CHECK: Vreg: %76[ 0 ]
+# CHECK: Vreg: %38[ 30 ]
+# CHECK: Vreg: %19[ LoopTag+44 ]
+# CHECK: Instr: %80:vgpr_32 = GLOBAL_LOAD_UBYTE %79, 0, 0, implicit $exec :: (load (s8) from %ir.gep, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+52 ]
+# CHECK: Vreg: %40[ 33 ]
+# CHECK: Vreg: %21[ 37 ]
+# CHECK: Vreg: %2[ LoopTag+52 ]
+# CHECK: Vreg: %42[ LoopTag+64 ]
+# CHECK: Vreg: %4[ 31 ]
+# CHECK: Vreg: %18:sub0[ 75 ]
+# CHECK: Vreg: %18:sub1[ 76 ]
+# CHECK: Vreg: %18[ LoopTag+85 ]
+# CHECK: Vreg: %70[ 15 ]
+# CHECK: Vreg: %20[ LoopTag+38 ]
+# CHECK: Vreg: %1[ LoopTag+88 ]
+# CHECK: Vreg: %34[ 32 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %41[ 31 ]
+# CHECK: Vreg: %22[ 63 ]
+# CHECK: Vreg: %3[ LoopTag+43 ]
+# CHECK: Vreg: %29[ LoopTag+41 ]
+# CHECK: Vreg: %36[ 16 ]
+# CHECK: Vreg: %17[ 67 ]
+# CHECK: Vreg: %50[ LoopTag+48 ]
+# CHECK: Vreg: %38[ 29 ]
+# CHECK: Vreg: %19[ LoopTag+43 ]
+# CHECK: Instr: %81:vgpr_32 = GLOBAL_LOAD_UBYTE %79, 1, 0, implicit $exec :: (load (s8) from %ir.gep + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+51 ]
+# CHECK: Vreg: %40[ 32 ]
+# CHECK: Vreg: %21[ 36 ]
+# CHECK: Vreg: %2[ LoopTag+51 ]
+# CHECK: Vreg: %80[ 1 ]
+# CHECK: Vreg: %42[ LoopTag+63 ]
+# CHECK: Vreg: %4[ 30 ]
+# CHECK: Vreg: %18:sub0[ 74 ]
+# CHECK: Vreg: %18:sub1[ 75 ]
+# CHECK: Vreg: %18[ LoopTag+84 ]
+# CHECK: Vreg: %70[ 14 ]
+# CHECK: Vreg: %20[ LoopTag+37 ]
+# CHECK: Vreg: %1[ LoopTag+87 ]
+# CHECK: Vreg: %34[ 31 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %41[ 30 ]
+# CHECK: Vreg: %22[ 62 ]
+# CHECK: Vreg: %3[ LoopTag+42 ]
+# CHECK: Vreg: %29[ LoopTag+40 ]
+# CHECK: Vreg: %36[ 15 ]
+# CHECK: Vreg: %17[ 66 ]
+# CHECK: Vreg: %50[ LoopTag+47 ]
+# CHECK: Vreg: %38[ 28 ]
+# CHECK: Vreg: %19[ LoopTag+42 ]
+# CHECK: Instr: %82:vgpr_32 = V_LSHL_OR_B32_e64 killed %81, 8, killed %80, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+50 ]
+# CHECK: Vreg: %40[ 31 ]
+# CHECK: Vreg: %21[ 35 ]
+# CHECK: Vreg: %2[ LoopTag+50 ]
+# CHECK: Vreg: %80[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+62 ]
+# CHECK: Vreg: %4[ 29 ]
+# CHECK: Vreg: %18:sub0[ 73 ]
+# CHECK: Vreg: %18:sub1[ 74 ]
+# CHECK: Vreg: %18[ LoopTag+83 ]
+# CHECK: Vreg: %70[ 13 ]
+# CHECK: Vreg: %20[ LoopTag+36 ]
+# CHECK: Vreg: %1[ LoopTag+86 ]
+# CHECK: Vreg: %34[ 30 ]
+# CHECK: Vreg: %79[ 1 ]
+# CHECK: Vreg: %41[ 29 ]
+# CHECK: Vreg: %22[ 61 ]
+# CHECK: Vreg: %3[ LoopTag+41 ]
+# CHECK: Vreg: %29[ LoopTag+39 ]
+# CHECK: Vreg: %36[ 14 ]
+# CHECK: Vreg: %17[ 65 ]
+# CHECK: Vreg: %81[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+46 ]
+# CHECK: Vreg: %38[ 27 ]
+# CHECK: Vreg: %19[ LoopTag+41 ]
+# CHECK: Instr: %83:vgpr_32 = GLOBAL_LOAD_UBYTE %79, 2, 0, implicit $exec :: (load (s8) from %ir.gep + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+49 ]
+# CHECK: Vreg: %40[ 30 ]
+# CHECK: Vreg: %21[ 34 ]
+# CHECK: Vreg: %2[ LoopTag+49 ]
+# CHECK: Vreg: %42[ LoopTag+61 ]
+# CHECK: Vreg: %4[ 28 ]
+# CHECK: Vreg: %18:sub0[ 72 ]
+# CHECK: Vreg: %18:sub1[ 73 ]
+# CHECK: Vreg: %18[ LoopTag+82 ]
+# CHECK: Vreg: %82[ 3 ]
+# CHECK: Vreg: %70[ 12 ]
+# CHECK: Vreg: %20[ LoopTag+35 ]
+# CHECK: Vreg: %1[ LoopTag+85 ]
+# CHECK: Vreg: %34[ 29 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %41[ 28 ]
+# CHECK: Vreg: %22[ 60 ]
+# CHECK: Vreg: %3[ LoopTag+40 ]
+# CHECK: Vreg: %29[ LoopTag+38 ]
+# CHECK: Vreg: %36[ 13 ]
+# CHECK: Vreg: %17[ 64 ]
+# CHECK: Vreg: %50[ LoopTag+45 ]
+# CHECK: Vreg: %38[ 26 ]
+# CHECK: Vreg: %19[ LoopTag+40 ]
+# CHECK: Instr: %84:vgpr_32 = GLOBAL_LOAD_UBYTE killed %79, 3, 0, implicit $exec :: (load (s8) from %ir.gep + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+48 ]
+# CHECK: Vreg: %83[ 1 ]
+# CHECK: Vreg: %40[ 29 ]
+# CHECK: Vreg: %21[ 33 ]
+# CHECK: Vreg: %2[ LoopTag+48 ]
+# CHECK: Vreg: %42[ LoopTag+60 ]
+# CHECK: Vreg: %4[ 27 ]
+# CHECK: Vreg: %18:sub0[ 71 ]
+# CHECK: Vreg: %18:sub1[ 72 ]
+# CHECK: Vreg: %18[ LoopTag+81 ]
+# CHECK: Vreg: %82[ 2 ]
+# CHECK: Vreg: %70[ 11 ]
+# CHECK: Vreg: %20[ LoopTag+34 ]
+# CHECK: Vreg: %1[ LoopTag+84 ]
+# CHECK: Vreg: %34[ 28 ]
+# CHECK: Vreg: %79[ 0 ]
+# CHECK: Vreg: %41[ 27 ]
+# CHECK: Vreg: %22[ 59 ]
+# CHECK: Vreg: %3[ LoopTag+39 ]
+# CHECK: Vreg: %29[ LoopTag+37 ]
+# CHECK: Vreg: %36[ 12 ]
+# CHECK: Vreg: %17[ 63 ]
+# CHECK: Vreg: %50[ LoopTag+44 ]
+# CHECK: Vreg: %38[ 25 ]
+# CHECK: Vreg: %19[ LoopTag+39 ]
+# CHECK: Instr: %85:vgpr_32 = V_LSHL_OR_B32_e64 killed %84, 8, killed %83, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+47 ]
+# CHECK: Vreg: %83[ 0 ]
+# CHECK: Vreg: %40[ 28 ]
+# CHECK: Vreg: %21[ 32 ]
+# CHECK: Vreg: %2[ LoopTag+47 ]
+# CHECK: Vreg: %42[ LoopTag+59 ]
+# CHECK: Vreg: %4[ 26 ]
+# CHECK: Vreg: %18:sub0[ 70 ]
+# CHECK: Vreg: %18:sub1[ 71 ]
+# CHECK: Vreg: %18[ LoopTag+80 ]
+# CHECK: Vreg: %82[ 1 ]
+# CHECK: Vreg: %70[ 10 ]
+# CHECK: Vreg: %20[ LoopTag+33 ]
+# CHECK: Vreg: %1[ LoopTag+83 ]
+# CHECK: Vreg: %84[ 0 ]
+# CHECK: Vreg: %34[ 27 ]
+# CHECK: Vreg: %41[ 26 ]
+# CHECK: Vreg: %22[ 58 ]
+# CHECK: Vreg: %3[ LoopTag+38 ]
+# CHECK: Vreg: %29[ LoopTag+36 ]
+# CHECK: Vreg: %36[ 11 ]
+# CHECK: Vreg: %17[ 62 ]
+# CHECK: Vreg: %50[ LoopTag+43 ]
+# CHECK: Vreg: %38[ 24 ]
+# CHECK: Vreg: %19[ LoopTag+38 ]
+# CHECK: Instr: %86:vgpr_32 = V_LSHL_OR_B32_e64 killed %85, 16, killed %82, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+46 ]
+# CHECK: Vreg: %40[ 27 ]
+# CHECK: Vreg: %21[ 31 ]
+# CHECK: Vreg: %2[ LoopTag+46 ]
+# CHECK: Vreg: %85[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+58 ]
+# CHECK: Vreg: %4[ 25 ]
+# CHECK: Vreg: %18:sub0[ 69 ]
+# CHECK: Vreg: %18:sub1[ 70 ]
+# CHECK: Vreg: %18[ LoopTag+79 ]
+# CHECK: Vreg: %82[ 0 ]
+# CHECK: Vreg: %70[ 9 ]
+# CHECK: Vreg: %20[ LoopTag+32 ]
+# CHECK: Vreg: %1[ LoopTag+82 ]
+# CHECK: Vreg: %34[ 26 ]
+# CHECK: Vreg: %41[ 25 ]
+# CHECK: Vreg: %22[ 57 ]
+# CHECK: Vreg: %3[ LoopTag+37 ]
+# CHECK: Vreg: %29[ LoopTag+35 ]
+# CHECK: Vreg: %36[ 10 ]
+# CHECK: Vreg: %17[ 61 ]
+# CHECK: Vreg: %50[ LoopTag+42 ]
+# CHECK: Vreg: %38[ 23 ]
+# CHECK: Vreg: %19[ LoopTag+37 ]
+# CHECK: Instr: %87:vgpr_32 = V_CVT_F32_U32_e64 %86, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+45 ]
+# CHECK: Vreg: %40[ 26 ]
+# CHECK: Vreg: %21[ 30 ]
+# CHECK: Vreg: %2[ LoopTag+45 ]
+# CHECK: Vreg: %42[ LoopTag+57 ]
+# CHECK: Vreg: %4[ 24 ]
+# CHECK: Vreg: %18:sub0[ 68 ]
+# CHECK: Vreg: %18:sub1[ 69 ]
+# CHECK: Vreg: %18[ LoopTag+78 ]
+# CHECK: Vreg: %70[ 8 ]
+# CHECK: Vreg: %20[ LoopTag+31 ]
+# CHECK: Vreg: %1[ LoopTag+81 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %41[ 24 ]
+# CHECK: Vreg: %22[ 56 ]
+# CHECK: Vreg: %3[ LoopTag+36 ]
+# CHECK: Vreg: %29[ LoopTag+34 ]
+# CHECK: Vreg: %36[ 9 ]
+# CHECK: Vreg: %17[ 60 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+41 ]
+# CHECK: Vreg: %38[ 22 ]
+# CHECK: Vreg: %19[ LoopTag+36 ]
+# CHECK: Instr: %88:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %87, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+44 ]
+# CHECK: Vreg: %40[ 25 ]
+# CHECK: Vreg: %21[ 29 ]
+# CHECK: Vreg: %2[ LoopTag+44 ]
+# CHECK: Vreg: %42[ LoopTag+56 ]
+# CHECK: Vreg: %87[ 0 ]
+# CHECK: Vreg: %4[ 23 ]
+# CHECK: Vreg: %18:sub0[ 67 ]
+# CHECK: Vreg: %18:sub1[ 68 ]
+# CHECK: Vreg: %18[ LoopTag+77 ]
+# CHECK: Vreg: %70[ 7 ]
+# CHECK: Vreg: %20[ LoopTag+30 ]
+# CHECK: Vreg: %1[ LoopTag+80 ]
+# CHECK: Vreg: %34[ 24 ]
+# CHECK: Vreg: %41[ 23 ]
+# CHECK: Vreg: %22[ 55 ]
+# CHECK: Vreg: %3[ LoopTag+35 ]
+# CHECK: Vreg: %29[ LoopTag+33 ]
+# CHECK: Vreg: %36[ 8 ]
+# CHECK: Vreg: %17[ 59 ]
+# CHECK: Vreg: %86[ 3 ]
+# CHECK: Vreg: %50[ LoopTag+40 ]
+# CHECK: Vreg: %38[ 21 ]
+# CHECK: Vreg: %19[ LoopTag+35 ]
+# CHECK: Instr: %89:vgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, 1333788670, 0, killed %88, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+43 ]
+# CHECK: Vreg: %40[ 24 ]
+# CHECK: Vreg: %21[ 28 ]
+# CHECK: Vreg: %2[ LoopTag+43 ]
+# CHECK: Vreg: %42[ LoopTag+55 ]
+# CHECK: Vreg: %4[ 22 ]
+# CHECK: Vreg: %18:sub0[ 66 ]
+# CHECK: Vreg: %18:sub1[ 67 ]
+# CHECK: Vreg: %18[ LoopTag+76 ]
+# CHECK: Vreg: %70[ 6 ]
+# CHECK: Vreg: %20[ LoopTag+29 ]
+# CHECK: Vreg: %1[ LoopTag+79 ]
+# CHECK: Vreg: %34[ 23 ]
+# CHECK: Vreg: %41[ 22 ]
+# CHECK: Vreg: %22[ 54 ]
+# CHECK: Vreg: %3[ LoopTag+34 ]
+# CHECK: Vreg: %29[ LoopTag+32 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Vreg: %17[ 58 ]
+# CHECK: Vreg: %86[ 2 ]
+# CHECK: Vreg: %88[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+39 ]
+# CHECK: Vreg: %38[ 20 ]
+# CHECK: Vreg: %19[ LoopTag+34 ]
+# CHECK: Instr: %90:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, killed %89, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+42 ]
+# CHECK: Vreg: %40[ 23 ]
+# CHECK: Vreg: %21[ 27 ]
+# CHECK: Vreg: %2[ LoopTag+42 ]
+# CHECK: Vreg: %42[ LoopTag+54 ]
+# CHECK: Vreg: %4[ 21 ]
+# CHECK: Vreg: %18:sub0[ 65 ]
+# CHECK: Vreg: %18:sub1[ 66 ]
+# CHECK: Vreg: %18[ LoopTag+75 ]
+# CHECK: Vreg: %89[ 0 ]
+# CHECK: Vreg: %70[ 5 ]
+# CHECK: Vreg: %20[ LoopTag+28 ]
+# CHECK: Vreg: %1[ LoopTag+78 ]
+# CHECK: Vreg: %34[ 22 ]
+# CHECK: Vreg: %41[ 21 ]
+# CHECK: Vreg: %22[ 53 ]
+# CHECK: Vreg: %3[ LoopTag+33 ]
+# CHECK: Vreg: %29[ LoopTag+31 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %17[ 57 ]
+# CHECK: Vreg: %86[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+38 ]
+# CHECK: Vreg: %38[ 19 ]
+# CHECK: Vreg: %19[ LoopTag+33 ]
+# CHECK: Instr: %91:vgpr_32 = V_SUB_U32_e64 0, %86, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+41 ]
+# CHECK: Vreg: %90[ 1 ]
+# CHECK: Vreg: %40[ 22 ]
+# CHECK: Vreg: %21[ 26 ]
+# CHECK: Vreg: %2[ LoopTag+41 ]
+# CHECK: Vreg: %42[ LoopTag+53 ]
+# CHECK: Vreg: %4[ 20 ]
+# CHECK: Vreg: %18:sub0[ 64 ]
+# CHECK: Vreg: %18:sub1[ 65 ]
+# CHECK: Vreg: %18[ LoopTag+74 ]
+# CHECK: Vreg: %70[ 4 ]
+# CHECK: Vreg: %20[ LoopTag+27 ]
+# CHECK: Vreg: %1[ LoopTag+77 ]
+# CHECK: Vreg: %34[ 21 ]
+# CHECK: Vreg: %41[ 20 ]
+# CHECK: Vreg: %22[ 52 ]
+# CHECK: Vreg: %3[ LoopTag+32 ]
+# CHECK: Vreg: %29[ LoopTag+30 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %17[ 56 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+37 ]
+# CHECK: Vreg: %38[ 18 ]
+# CHECK: Vreg: %19[ LoopTag+32 ]
+# CHECK: Instr: %92:vgpr_32 = V_MUL_LO_U32_e64 killed %91, %90, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+40 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %40[ 21 ]
+# CHECK: Vreg: %21[ 25 ]
+# CHECK: Vreg: %2[ LoopTag+40 ]
+# CHECK: Vreg: %42[ LoopTag+52 ]
+# CHECK: Vreg: %4[ 19 ]
+# CHECK: Vreg: %18:sub0[ 63 ]
+# CHECK: Vreg: %18:sub1[ 64 ]
+# CHECK: Vreg: %18[ LoopTag+73 ]
+# CHECK: Vreg: %70[ 3 ]
+# CHECK: Vreg: %20[ LoopTag+26 ]
+# CHECK: Vreg: %1[ LoopTag+76 ]
+# CHECK: Vreg: %91[ 0 ]
+# CHECK: Vreg: %34[ 20 ]
+# CHECK: Vreg: %41[ 19 ]
+# CHECK: Vreg: %22[ 51 ]
+# CHECK: Vreg: %3[ LoopTag+31 ]
+# CHECK: Vreg: %29[ LoopTag+29 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %17[ 55 ]
+# CHECK: Vreg: %86[ 5 ]
+# CHECK: Vreg: %50[ LoopTag+36 ]
+# CHECK: Vreg: %38[ 17 ]
+# CHECK: Vreg: %19[ LoopTag+31 ]
+# CHECK: Instr: %93:vgpr_32 = V_MUL_HI_U32_e64 %90, killed %92, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+39 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %40[ 20 ]
+# CHECK: Vreg: %21[ 24 ]
+# CHECK: Vreg: %2[ LoopTag+39 ]
+# CHECK: Vreg: %92[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+51 ]
+# CHECK: Vreg: %4[ 18 ]
+# CHECK: Vreg: %18:sub0[ 62 ]
+# CHECK: Vreg: %18:sub1[ 63 ]
+# CHECK: Vreg: %18[ LoopTag+72 ]
+# CHECK: Vreg: %70[ 2 ]
+# CHECK: Vreg: %20[ LoopTag+25 ]
+# CHECK: Vreg: %1[ LoopTag+75 ]
+# CHECK: Vreg: %34[ 19 ]
+# CHECK: Vreg: %41[ 18 ]
+# CHECK: Vreg: %22[ 50 ]
+# CHECK: Vreg: %3[ LoopTag+30 ]
+# CHECK: Vreg: %29[ LoopTag+28 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %17[ 54 ]
+# CHECK: Vreg: %86[ 4 ]
+# CHECK: Vreg: %50[ LoopTag+35 ]
+# CHECK: Vreg: %38[ 16 ]
+# CHECK: Vreg: %19[ LoopTag+30 ]
+# CHECK: Instr: %94:vgpr_32 = V_ADD_U32_e64 killed %90, killed %93, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+38 ]
+# CHECK: Vreg: %90[ 0 ]
+# CHECK: Vreg: %40[ 19 ]
+# CHECK: Vreg: %21[ 23 ]
+# CHECK: Vreg: %2[ LoopTag+38 ]
+# CHECK: Vreg: %42[ LoopTag+50 ]
+# CHECK: Vreg: %4[ 17 ]
+# CHECK: Vreg: %18:sub0[ 61 ]
+# CHECK: Vreg: %18:sub1[ 62 ]
+# CHECK: Vreg: %18[ LoopTag+71 ]
+# CHECK: Vreg: %70[ 1 ]
+# CHECK: Vreg: %20[ LoopTag+24 ]
+# CHECK: Vreg: %1[ LoopTag+74 ]
+# CHECK: Vreg: %34[ 18 ]
+# CHECK: Vreg: %41[ 17 ]
+# CHECK: Vreg: %22[ 49 ]
+# CHECK: Vreg: %3[ LoopTag+29 ]
+# CHECK: Vreg: %29[ LoopTag+27 ]
+# CHECK: Vreg: %93[ 0 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 53 ]
+# CHECK: Vreg: %86[ 3 ]
+# CHECK: Vreg: %50[ LoopTag+34 ]
+# CHECK: Vreg: %38[ 15 ]
+# CHECK: Vreg: %19[ LoopTag+29 ]
+# CHECK: Instr: %95:vgpr_32 = V_MUL_HI_U32_e64 %70, %94, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+37 ]
+# CHECK: Vreg: %40[ 18 ]
+# CHECK: Vreg: %21[ 22 ]
+# CHECK: Vreg: %2[ LoopTag+37 ]
+# CHECK: Vreg: %42[ LoopTag+49 ]
+# CHECK: Vreg: %4[ 16 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %18:sub0[ 60 ]
+# CHECK: Vreg: %18:sub1[ 61 ]
+# CHECK: Vreg: %18[ LoopTag+70 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+23 ]
+# CHECK: Vreg: %1[ LoopTag+73 ]
+# CHECK: Vreg: %34[ 17 ]
+# CHECK: Vreg: %41[ 16 ]
+# CHECK: Vreg: %22[ 48 ]
+# CHECK: Vreg: %3[ LoopTag+28 ]
+# CHECK: Vreg: %29[ LoopTag+26 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %17[ 52 ]
+# CHECK: Vreg: %86[ 2 ]
+# CHECK: Vreg: %50[ LoopTag+33 ]
+# CHECK: Vreg: %38[ 14 ]
+# CHECK: Vreg: %19[ LoopTag+28 ]
+# CHECK: Instr: %96:vgpr_32 = V_MUL_HI_U32_e64 %36, killed %94, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+36 ]
+# CHECK: Vreg: %40[ 17 ]
+# CHECK: Vreg: %21[ 21 ]
+# CHECK: Vreg: %2[ LoopTag+36 ]
+# CHECK: Vreg: %42[ LoopTag+48 ]
+# CHECK: Vreg: %4[ 15 ]
+# CHECK: Vreg: %94[ 0 ]
+# CHECK: Vreg: %18:sub0[ 59 ]
+# CHECK: Vreg: %18:sub1[ 60 ]
+# CHECK: Vreg: %18[ LoopTag+69 ]
+# CHECK: Vreg: %70[ 2 ]
+# CHECK: Vreg: %20[ LoopTag+22 ]
+# CHECK: Vreg: %1[ LoopTag+72 ]
+# CHECK: Vreg: %34[ 16 ]
+# CHECK: Vreg: %41[ 15 ]
+# CHECK: Vreg: %22[ 47 ]
+# CHECK: Vreg: %3[ LoopTag+27 ]
+# CHECK: Vreg: %29[ LoopTag+25 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 51 ]
+# CHECK: Vreg: %86[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+32 ]
+# CHECK: Vreg: %95[ 4 ]
+# CHECK: Vreg: %38[ 13 ]
+# CHECK: Vreg: %19[ LoopTag+27 ]
+# CHECK: Instr: %97:vgpr_32 = V_MUL_LO_U32_e64 %86, %96, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+35 ]
+# CHECK: Vreg: %40[ 16 ]
+# CHECK: Vreg: %21[ 20 ]
+# CHECK: Vreg: %2[ LoopTag+35 ]
+# CHECK: Vreg: %42[ LoopTag+47 ]
+# CHECK: Vreg: %4[ 14 ]
+# CHECK: Vreg: %18:sub0[ 58 ]
+# CHECK: Vreg: %18:sub1[ 59 ]
+# CHECK: Vreg: %18[ LoopTag+68 ]
+# CHECK: Vreg: %70[ 1 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+21 ]
+# CHECK: Vreg: %1[ LoopTag+71 ]
+# CHECK: Vreg: %34[ 15 ]
+# CHECK: Vreg: %41[ 14 ]
+# CHECK: Vreg: %22[ 46 ]
+# CHECK: Vreg: %3[ LoopTag+26 ]
+# CHECK: Vreg: %29[ LoopTag+24 ]
+# CHECK: Vreg: %36[ 13 ]
+# CHECK: Vreg: %17[ 50 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+31 ]
+# CHECK: Vreg: %95[ 3 ]
+# CHECK: Vreg: %38[ 12 ]
+# CHECK: Vreg: %19[ LoopTag+26 ]
+# CHECK: Instr: %98:vgpr_32 = V_SUB_U32_e64 %70, killed %97, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+34 ]
+# CHECK: Vreg: %97[ 0 ]
+# CHECK: Vreg: %40[ 15 ]
+# CHECK: Vreg: %21[ 19 ]
+# CHECK: Vreg: %2[ LoopTag+34 ]
+# CHECK: Vreg: %42[ LoopTag+46 ]
+# CHECK: Vreg: %4[ 13 ]
+# CHECK: Vreg: %18:sub0[ 57 ]
+# CHECK: Vreg: %18:sub1[ 58 ]
+# CHECK: Vreg: %18[ LoopTag+67 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %96[ 4 ]
+# CHECK: Vreg: %20[ LoopTag+20 ]
+# CHECK: Vreg: %1[ LoopTag+70 ]
+# CHECK: Vreg: %34[ 14 ]
+# CHECK: Vreg: %41[ 13 ]
+# CHECK: Vreg: %22[ 45 ]
+# CHECK: Vreg: %3[ LoopTag+25 ]
+# CHECK: Vreg: %29[ LoopTag+23 ]
+# CHECK: Vreg: %36[ 12 ]
+# CHECK: Vreg: %17[ 49 ]
+# CHECK: Vreg: %86[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+30 ]
+# CHECK: Vreg: %95[ 2 ]
+# CHECK: Vreg: %38[ 11 ]
+# CHECK: Vreg: %19[ LoopTag+25 ]
+# CHECK: Instr: %99:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 %98, %86, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+33 ]
+# CHECK: Vreg: %40[ 14 ]
+# CHECK: Vreg: %21[ 18 ]
+# CHECK: Vreg: %2[ LoopTag+33 ]
+# CHECK: Vreg: %42[ LoopTag+45 ]
+# CHECK: Vreg: %4[ 12 ]
+# CHECK: Vreg: %18:sub0[ 56 ]
+# CHECK: Vreg: %18:sub1[ 57 ]
+# CHECK: Vreg: %18[ LoopTag+66 ]
+# CHECK: Vreg: %70[ 4 ]
+# CHECK: Vreg: %96[ 3 ]
+# CHECK: Vreg: %20[ LoopTag+19 ]
+# CHECK: Vreg: %1[ LoopTag+69 ]
+# CHECK: Vreg: %34[ 13 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %41[ 12 ]
+# CHECK: Vreg: %22[ 44 ]
+# CHECK: Vreg: %3[ LoopTag+24 ]
+# CHECK: Vreg: %29[ LoopTag+22 ]
+# CHECK: Vreg: %36[ 11 ]
+# CHECK: Vreg: %17[ 48 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+29 ]
+# CHECK: Vreg: %95[ 1 ]
+# CHECK: Vreg: %38[ 10 ]
+# CHECK: Vreg: %19[ LoopTag+24 ]
+# CHECK: Instr: %100:vgpr_32 = V_ADD_U32_e64 1, %95, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+32 ]
+# CHECK: Vreg: %40[ 13 ]
+# CHECK: Vreg: %21[ 17 ]
+# CHECK: Vreg: %2[ LoopTag+32 ]
+# CHECK: Vreg: %99[ 1 ]
+# CHECK: Vreg: %42[ LoopTag+44 ]
+# CHECK: Vreg: %4[ 11 ]
+# CHECK: Vreg: %18:sub0[ 55 ]
+# CHECK: Vreg: %18:sub1[ 56 ]
+# CHECK: Vreg: %18[ LoopTag+65 ]
+# CHECK: Vreg: %70[ 3 ]
+# CHECK: Vreg: %96[ 2 ]
+# CHECK: Vreg: %20[ LoopTag+18 ]
+# CHECK: Vreg: %1[ LoopTag+68 ]
+# CHECK: Vreg: %34[ 12 ]
+# CHECK: Vreg: %98[ 5 ]
+# CHECK: Vreg: %41[ 11 ]
+# CHECK: Vreg: %22[ 43 ]
+# CHECK: Vreg: %3[ LoopTag+23 ]
+# CHECK: Vreg: %29[ LoopTag+21 ]
+# CHECK: Vreg: %36[ 10 ]
+# CHECK: Vreg: %17[ 47 ]
+# CHECK: Vreg: %86[ 4 ]
+# CHECK: Vreg: %50[ LoopTag+28 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %38[ 9 ]
+# CHECK: Vreg: %19[ LoopTag+23 ]
+# CHECK: Instr: %101:vgpr_32 = V_CNDMASK_B32_e64 0, killed %95, 0, killed %100, %99, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+31 ]
+# CHECK: Vreg: %40[ 12 ]
+# CHECK: Vreg: %21[ 16 ]
+# CHECK: Vreg: %2[ LoopTag+31 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+43 ]
+# CHECK: Vreg: %4[ 10 ]
+# CHECK: Vreg: %18:sub0[ 54 ]
+# CHECK: Vreg: %18:sub1[ 55 ]
+# CHECK: Vreg: %18[ LoopTag+64 ]
+# CHECK: Vreg: %70[ 2 ]
+# CHECK: Vreg: %96[ 1 ]
+# CHECK: Vreg: %20[ LoopTag+17 ]
+# CHECK: Vreg: %1[ LoopTag+67 ]
+# CHECK: Vreg: %34[ 11 ]
+# CHECK: Vreg: %98[ 4 ]
+# CHECK: Vreg: %41[ 10 ]
+# CHECK: Vreg: %22[ 42 ]
+# CHECK: Vreg: %3[ LoopTag+22 ]
+# CHECK: Vreg: %29[ LoopTag+20 ]
+# CHECK: Vreg: %36[ 9 ]
+# CHECK: Vreg: %17[ 46 ]
+# CHECK: Vreg: %100[ 0 ]
+# CHECK: Vreg: %86[ 3 ]
+# CHECK: Vreg: %50[ LoopTag+27 ]
+# CHECK: Vreg: %95[ 0 ]
+# CHECK: Vreg: %38[ 8 ]
+# CHECK: Vreg: %19[ LoopTag+22 ]
+# CHECK: Instr: %102:vgpr_32 = V_NOT_B32_e32 killed %96, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+30 ]
+# CHECK: Vreg: %40[ 11 ]
+# CHECK: Vreg: %21[ 15 ]
+# CHECK: Vreg: %2[ LoopTag+30 ]
+# CHECK: Vreg: %99[ 3 ]
+# CHECK: Vreg: %42[ LoopTag+42 ]
+# CHECK: Vreg: %4[ 9 ]
+# CHECK: Vreg: %101[ 5 ]
+# CHECK: Vreg: %18:sub0[ 53 ]
+# CHECK: Vreg: %18:sub1[ 54 ]
+# CHECK: Vreg: %18[ LoopTag+63 ]
+# CHECK: Vreg: %70[ 1 ]
+# CHECK: Vreg: %96[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+16 ]
+# CHECK: Vreg: %1[ LoopTag+66 ]
+# CHECK: Vreg: %34[ 10 ]
+# CHECK: Vreg: %98[ 3 ]
+# CHECK: Vreg: %41[ 9 ]
+# CHECK: Vreg: %22[ 41 ]
+# CHECK: Vreg: %3[ LoopTag+21 ]
+# CHECK: Vreg: %29[ LoopTag+19 ]
+# CHECK: Vreg: %36[ 8 ]
+# CHECK: Vreg: %17[ 45 ]
+# CHECK: Vreg: %86[ 2 ]
+# CHECK: Vreg: %50[ LoopTag+26 ]
+# CHECK: Vreg: %38[ 7 ]
+# CHECK: Vreg: %19[ LoopTag+21 ]
+# CHECK: Instr: %103:vreg_64 = REG_SEQUENCE killed %70, %subreg.sub0, undef %104:vgpr_32, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+29 ]
+# CHECK: Vreg: %102[ 1 ]
+# CHECK: Vreg: %40[ 10 ]
+# CHECK: Vreg: %21[ 14 ]
+# CHECK: Vreg: %2[ LoopTag+29 ]
+# CHECK: Vreg: %99[ 2 ]
+# CHECK: Vreg: %42[ LoopTag+41 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %101[ 4 ]
+# CHECK: Vreg: %18:sub0[ 52 ]
+# CHECK: Vreg: %18:sub1[ 53 ]
+# CHECK: Vreg: %18[ LoopTag+62 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+15 ]
+# CHECK: Vreg: %1[ LoopTag+65 ]
+# CHECK: Vreg: %34[ 9 ]
+# CHECK: Vreg: %98[ 2 ]
+# CHECK: Vreg: %41[ 8 ]
+# CHECK: Vreg: %22[ 40 ]
+# CHECK: Vreg: %3[ LoopTag+20 ]
+# CHECK: Vreg: %29[ LoopTag+18 ]
+# CHECK: Vreg: %36[ 7 ]
+# CHECK: Vreg: %17[ 44 ]
+# CHECK: Vreg: %86[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+25 ]
+# CHECK: Vreg: %38[ 6 ]
+# CHECK: Vreg: %19[ LoopTag+20 ]
+# CHECK: Instr: %105:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 %86, killed %102, killed %103, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+28 ]
+# CHECK: Vreg: %102[ 0 ]
+# CHECK: Vreg: %40[ 9 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %2[ LoopTag+28 ]
+# CHECK: Vreg: %99[ 1 ]
+# CHECK: Vreg: %42[ LoopTag+40 ]
+# CHECK: Vreg: %4[ 7 ]
+# CHECK: Vreg: %101[ 3 ]
+# CHECK: Vreg: %18:sub0[ 51 ]
+# CHECK: Vreg: %18:sub1[ 52 ]
+# CHECK: Vreg: %18[ LoopTag+61 ]
+# CHECK: Vreg: %103[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+14 ]
+# CHECK: Vreg: %1[ LoopTag+64 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %98[ 1 ]
+# CHECK: Vreg: %41[ 7 ]
+# CHECK: Vreg: %22[ 39 ]
+# CHECK: Vreg: %3[ LoopTag+19 ]
+# CHECK: Vreg: %29[ LoopTag+17 ]
+# CHECK: Vreg: %36[ 6 ]
+# CHECK: Vreg: %17[ 43 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+24 ]
+# CHECK: Vreg: %38[ 5 ]
+# CHECK: Vreg: %19[ LoopTag+19 ]
+# CHECK: Instr: %106:vgpr_32 = V_CNDMASK_B32_e64 0, killed %98, 0, killed %105.sub0, killed %99, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+27 ]
+# CHECK: Vreg: %40[ 8 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %2[ LoopTag+27 ]
+# CHECK: Vreg: %99[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+39 ]
+# CHECK: Vreg: %4[ 6 ]
+# CHECK: Vreg: %101[ 2 ]
+# CHECK: Vreg: %18:sub0[ 50 ]
+# CHECK: Vreg: %18:sub1[ 51 ]
+# CHECK: Vreg: %18[ LoopTag+60 ]
+# CHECK: Vreg: %20[ LoopTag+13 ]
+# CHECK: Vreg: %1[ LoopTag+63 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %98[ 0 ]
+# CHECK: Vreg: %41[ 6 ]
+# CHECK: Vreg: %22[ 38 ]
+# CHECK: Vreg: %3[ LoopTag+18 ]
+# CHECK: Vreg: %105:sub0[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+16 ]
+# CHECK: Vreg: %36[ 5 ]
+# CHECK: Vreg: %17[ 42 ]
+# CHECK: Vreg: %86[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+23 ]
+# CHECK: Vreg: %38[ 4 ]
+# CHECK: Vreg: %19[ LoopTag+18 ]
+# CHECK: Instr: %107:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 killed %106, killed %86, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+26 ]
+# CHECK: Vreg: %40[ 7 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %2[ LoopTag+26 ]
+# CHECK: Vreg: %42[ LoopTag+38 ]
+# CHECK: Vreg: %106[ 0 ]
+# CHECK: Vreg: %4[ 5 ]
+# CHECK: Vreg: %101[ 1 ]
+# CHECK: Vreg: %18:sub0[ 49 ]
+# CHECK: Vreg: %18:sub1[ 50 ]
+# CHECK: Vreg: %18[ LoopTag+59 ]
+# CHECK: Vreg: %20[ LoopTag+12 ]
+# CHECK: Vreg: %1[ LoopTag+62 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %41[ 5 ]
+# CHECK: Vreg: %22[ 37 ]
+# CHECK: Vreg: %3[ LoopTag+17 ]
+# CHECK: Vreg: %29[ LoopTag+15 ]
+# CHECK: Vreg: %36[ 4 ]
+# CHECK: Vreg: %17[ 41 ]
+# CHECK: Vreg: %86[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+22 ]
+# CHECK: Vreg: %38[ 3 ]
+# CHECK: Vreg: %19[ LoopTag+17 ]
+# CHECK: Instr: %108:vgpr_32 = V_ADD_U32_e64 1, %101, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %40[ 6 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %2[ LoopTag+25 ]
+# CHECK: Vreg: %42[ LoopTag+37 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %18:sub0[ 48 ]
+# CHECK: Vreg: %18:sub1[ 49 ]
+# CHECK: Vreg: %18[ LoopTag+58 ]
+# CHECK: Vreg: %20[ LoopTag+11 ]
+# CHECK: Vreg: %1[ LoopTag+61 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %41[ 4 ]
+# CHECK: Vreg: %22[ 36 ]
+# CHECK: Vreg: %3[ LoopTag+16 ]
+# CHECK: Vreg: %29[ LoopTag+14 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Vreg: %17[ 40 ]
+# CHECK: Vreg: %107[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+21 ]
+# CHECK: Vreg: %38[ 2 ]
+# CHECK: Vreg: %19[ LoopTag+16 ]
+# CHECK: Instr: %43:vgpr_32 = V_CNDMASK_B32_e64 0, killed %101, 0, killed %108, killed %107, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %40[ 5 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %2[ LoopTag+24 ]
+# CHECK: Vreg: %42[ LoopTag+36 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %101[ 0 ]
+# CHECK: Vreg: %18:sub0[ 47 ]
+# CHECK: Vreg: %18:sub1[ 48 ]
+# CHECK: Vreg: %18[ LoopTag+57 ]
+# CHECK: Vreg: %108[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+10 ]
+# CHECK: Vreg: %1[ LoopTag+60 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %41[ 3 ]
+# CHECK: Vreg: %22[ 35 ]
+# CHECK: Vreg: %3[ LoopTag+15 ]
+# CHECK: Vreg: %29[ LoopTag+13 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Vreg: %17[ 39 ]
+# CHECK: Vreg: %107[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+20 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Vreg: %19[ LoopTag+15 ]
+# CHECK: Instr: %39:sreg_32 = S_ADD_I32 killed %38, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+23 ]
+# CHECK: Vreg: %40[ 4 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %2[ LoopTag+23 ]
+# CHECK: Vreg: %42[ LoopTag+35 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %18:sub0[ 46 ]
+# CHECK: Vreg: %18:sub1[ 47 ]
+# CHECK: Vreg: %18[ LoopTag+56 ]
+# CHECK: Vreg: %20[ LoopTag+9 ]
+# CHECK: Vreg: %1[ LoopTag+59 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %41[ 2 ]
+# CHECK: Vreg: %22[ 34 ]
+# CHECK: Vreg: %3[ LoopTag+14 ]
+# CHECK: Vreg: %29[ LoopTag+12 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %17[ 38 ]
+# CHECK: Vreg: %43[ 7 ]
+# CHECK: Vreg: %50[ LoopTag+19 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+14 ]
+# CHECK: Instr: %37:vgpr_32 = V_ADD_U32_e64 1, killed %36, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+22 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %2[ LoopTag+22 ]
+# CHECK: Vreg: %42[ LoopTag+34 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %18:sub0[ 45 ]
+# CHECK: Vreg: %18:sub1[ 46 ]
+# CHECK: Vreg: %18[ LoopTag+55 ]
+# CHECK: Vreg: %39[ 6 ]
+# CHECK: Vreg: %20[ LoopTag+8 ]
+# CHECK: Vreg: %1[ LoopTag+58 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %22[ 33 ]
+# CHECK: Vreg: %3[ LoopTag+13 ]
+# CHECK: Vreg: %29[ LoopTag+11 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %17[ 37 ]
+# CHECK: Vreg: %43[ 6 ]
+# CHECK: Vreg: %50[ LoopTag+18 ]
+# CHECK: Vreg: %19[ LoopTag+13 ]
+# CHECK: Instr: %109:sreg_32 = V_CMP_GE_U32_e64 %41, %4, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %2[ LoopTag+21 ]
+# CHECK: Vreg: %42[ LoopTag+33 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %37[ 5 ]
+# CHECK: Vreg: %18:sub0[ 44 ]
+# CHECK: Vreg: %18:sub1[ 45 ]
+# CHECK: Vreg: %18[ LoopTag+54 ]
+# CHECK: Vreg: %39[ 5 ]
+# CHECK: Vreg: %20[ LoopTag+7 ]
+# CHECK: Vreg: %1[ LoopTag+57 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 32 ]
+# CHECK: Vreg: %3[ LoopTag+12 ]
+# CHECK: Vreg: %29[ LoopTag+10 ]
+# CHECK: Vreg: %17[ 36 ]
+# CHECK: Vreg: %43[ 5 ]
+# CHECK: Vreg: %50[ LoopTag+17 ]
+# CHECK: Vreg: %19[ LoopTag+12 ]
+# CHECK: Instr: %35:sreg_32 = SI_IF_BREAK killed %109, killed %34, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+20 ]
+# CHECK: Vreg: %109[ 0 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %2[ LoopTag+20 ]
+# CHECK: Vreg: %42[ LoopTag+32 ]
+# CHECK: Vreg: %4[ 77 ]
+# CHECK: Vreg: %37[ 4 ]
+# CHECK: Vreg: %18:sub0[ 43 ]
+# CHECK: Vreg: %18:sub1[ 44 ]
+# CHECK: Vreg: %18[ LoopTag+53 ]
+# CHECK: Vreg: %39[ 4 ]
+# CHECK: Vreg: %20[ LoopTag+6 ]
+# CHECK: Vreg: %1[ LoopTag+56 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %41[ 2 ]
+# CHECK: Vreg: %22[ 31 ]
+# CHECK: Vreg: %3[ LoopTag+11 ]
+# CHECK: Vreg: %29[ LoopTag+9 ]
+# CHECK: Vreg: %17[ 35 ]
+# CHECK: Vreg: %43[ 4 ]
+# CHECK: Vreg: %50[ LoopTag+16 ]
+# CHECK: Vreg: %19[ LoopTag+11 ]
+# CHECK: Instr: %110:vgpr_32 = COPY killed %40, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %2[ LoopTag+19 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %42[ LoopTag+31 ]
+# CHECK: Vreg: %4[ 76 ]
+# CHECK: Vreg: %37[ 3 ]
+# CHECK: Vreg: %18:sub0[ 42 ]
+# CHECK: Vreg: %18:sub1[ 43 ]
+# CHECK: Vreg: %18[ LoopTag+52 ]
+# CHECK: Vreg: %39[ 3 ]
+# CHECK: Vreg: %20[ LoopTag+5 ]
+# CHECK: Vreg: %1[ LoopTag+55 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %22[ 30 ]
+# CHECK: Vreg: %3[ LoopTag+10 ]
+# CHECK: Vreg: %29[ LoopTag+8 ]
+# CHECK: Vreg: %17[ 34 ]
+# CHECK: Vreg: %43[ 3 ]
+# CHECK: Vreg: %50[ LoopTag+15 ]
+# CHECK: Vreg: %19[ LoopTag+10 ]
+# CHECK: Instr: %111:vgpr_32 = COPY %41, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+18 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ LoopTag+18 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %42[ LoopTag+30 ]
+# CHECK: Vreg: %4[ 75 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %18:sub0[ 41 ]
+# CHECK: Vreg: %18:sub1[ 42 ]
+# CHECK: Vreg: %18[ LoopTag+51 ]
+# CHECK: Vreg: %39[ 2 ]
+# CHECK: Vreg: %20[ LoopTag+4 ]
+# CHECK: Vreg: %1[ LoopTag+54 ]
+# CHECK: Vreg: %110[ LoopTag+14 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 29 ]
+# CHECK: Vreg: %3[ LoopTag+9 ]
+# CHECK: Vreg: %29[ LoopTag+7 ]
+# CHECK: Vreg: %17[ 33 ]
+# CHECK: Vreg: %43[ 2 ]
+# CHECK: Vreg: %50[ LoopTag+14 ]
+# CHECK: Vreg: %19[ LoopTag+9 ]
+# CHECK: Instr: SI_LOOP %35, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+17 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %2[ LoopTag+17 ]
+# CHECK: Vreg: %111[ LoopTag+9 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+29 ]
+# CHECK: Vreg: %4[ 74 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %18:sub0[ 40 ]
+# CHECK: Vreg: %18:sub1[ 41 ]
+# CHECK: Vreg: %18[ LoopTag+50 ]
+# CHECK: Vreg: %39[ 1 ]
+# CHECK: Vreg: %20[ LoopTag+3 ]
+# CHECK: Vreg: %1[ LoopTag+53 ]
+# CHECK: Vreg: %110[ LoopTag+13 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %22[ 28 ]
+# CHECK: Vreg: %3[ LoopTag+8 ]
+# CHECK: Vreg: %29[ LoopTag+6 ]
+# CHECK: Vreg: %17[ 32 ]
+# CHECK: Vreg: %43[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+13 ]
+# CHECK: Vreg: %19[ LoopTag+8 ]
+# CHECK: Instr: S_BRANCH %bb.2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+16 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+16 ]
+# CHECK: Vreg: %111[ LoopTag+8 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+28 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %18:sub0[ 39 ]
+# CHECK: Vreg: %18:sub1[ 40 ]
+# CHECK: Vreg: %18[ LoopTag+49 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+2 ]
+# CHECK: Vreg: %1[ LoopTag+52 ]
+# CHECK: Vreg: %110[ LoopTag+12 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %3[ LoopTag+7 ]
+# CHECK: Vreg: %29[ LoopTag+5 ]
+# CHECK: Vreg: %17[ 31 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+12 ]
+# CHECK: Vreg: %19[ LoopTag+7 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+16 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ LoopTag+16 ]
+# CHECK: Vreg: %111[ LoopTag+8 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+28 ]
+# CHECK: Vreg: %4[ 73 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %18:sub0[ 39 ]
+# CHECK: Vreg: %18:sub1[ 40 ]
+# CHECK: Vreg: %18[ LoopTag+49 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %20[ LoopTag+2 ]
+# CHECK: Vreg: %1[ LoopTag+52 ]
+# CHECK: Vreg: %110[ LoopTag+12 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %22[ 27 ]
+# CHECK: Vreg: %3[ LoopTag+7 ]
+# CHECK: Vreg: %29[ LoopTag+5 ]
+# CHECK: Vreg: %17[ 31 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+12 ]
+# CHECK: Vreg: %19[ LoopTag+7 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: SI_END_CF killed %35, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 15 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %2[ 15 ]
+# CHECK: Vreg: %111[ 7 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %42[ 27 ]
+# CHECK: Vreg: %18[ 48 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %110[ 11 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %17[ 24 ]
+# CHECK: Vreg: %50[ 11 ]
+# CHECK: Vreg: %19[ 6 ]
+# CHECK: Instr: %112:vgpr_32 = GLOBAL_LOAD_USHORT %20, 0, 0, implicit $exec :: (load (s16) from %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 14 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %2[ 14 ]
+# CHECK: Vreg: %111[ 6 ]
+# CHECK: Vreg: %42[ 26 ]
+# CHECK: Vreg: %18[ 47 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 50 ]
+# CHECK: Vreg: %110[ 10 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %17[ 23 ]
+# CHECK: Vreg: %50[ 10 ]
+# CHECK: Vreg: %19[ 5 ]
+# CHECK: Instr: %113:vgpr_32 = GLOBAL_LOAD_USHORT killed %20, 2, 0, implicit $exec :: (load (s16) from %ir.p3 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 13 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %2[ 13 ]
+# CHECK: Vreg: %111[ 5 ]
+# CHECK: Vreg: %42[ 25 ]
+# CHECK: Vreg: %18[ 46 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 49 ]
+# CHECK: Vreg: %110[ 9 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %112[ 1 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %17[ 22 ]
+# CHECK: Vreg: %50[ 9 ]
+# CHECK: Vreg: %19[ 4 ]
+# CHECK: Instr: %114:vgpr_32 = V_LSHL_OR_B32_e64 killed %113, 16, killed %112, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %2[ 12 ]
+# CHECK: Vreg: %111[ 4 ]
+# CHECK: Vreg: %42[ 24 ]
+# CHECK: Vreg: %113[ 0 ]
+# CHECK: Vreg: %18[ 45 ]
+# CHECK: Vreg: %1[ 48 ]
+# CHECK: Vreg: %110[ 8 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Vreg: %112[ 0 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17[ 21 ]
+# CHECK: Vreg: %50[ 8 ]
+# CHECK: Vreg: %19[ 3 ]
+# CHECK: Instr: %115:sreg_32 = V_CMP_LT_U32_e64 %114, %29, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %2[ 11 ]
+# CHECK: Vreg: %111[ 3 ]
+# CHECK: Vreg: %42[ 23 ]
+# CHECK: Vreg: %18[ 44 ]
+# CHECK: Vreg: %1[ 47 ]
+# CHECK: Vreg: %110[ 7 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 20 ]
+# CHECK: Vreg: %50[ 7 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Instr: %116:sreg_32 = SI_IF killed %115, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %2[ 10 ]
+# CHECK: Vreg: %111[ 2 ]
+# CHECK: Vreg: %42[ 22 ]
+# CHECK: Vreg: %18[ 43 ]
+# CHECK: Vreg: %115[ 0 ]
+# CHECK: Vreg: %1[ 46 ]
+# CHECK: Vreg: %110[ 6 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %17[ 19 ]
+# CHECK: Vreg: %50[ 6 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: S_BRANCH %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %111[ 1 ]
+# CHECK: Vreg: %42[ 21 ]
+# CHECK: Vreg: %18[ 42 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %111[ 1 ]
+# CHECK: Vreg: %42[ 21 ]
+# CHECK: Vreg: %18[ 42 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %117:vgpr_32 = V_ADD3_U32_e64 %29, %111, -1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 61 ]
+# CHECK: Vreg: %116[ 53 ]
+# CHECK: Vreg: %21[ 21 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %42[ 20 ]
+# CHECK: Vreg: %18[ 41 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %110[ 57 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %17[ 17 ]
+# CHECK: Vreg: %50[ 57 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Vreg: %19[ 14 ]
+# CHECK: Instr: %118:vgpr_32 = V_ADD_U32_e64 -10, %114, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 60 ]
+# CHECK: Vreg: %116[ 52 ]
+# CHECK: Vreg: %21[ 20 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %111[ 62 ]
+# CHECK: Vreg: %42[ 19 ]
+# CHECK: Vreg: %18[ 40 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %110[ 56 ]
+# CHECK: Vreg: %117[ 3 ]
+# CHECK: Vreg: %29[ 57 ]
+# CHECK: Vreg: %17[ 16 ]
+# CHECK: Vreg: %50[ 56 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Vreg: %19[ 13 ]
+# CHECK: Instr: %119:sreg_32 = S_MOV_B32 9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 59 ]
+# CHECK: Vreg: %116[ 51 ]
+# CHECK: Vreg: %21[ 19 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %111[ 61 ]
+# CHECK: Vreg: %118[ 2 ]
+# CHECK: Vreg: %42[ 18 ]
+# CHECK: Vreg: %18[ 39 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %110[ 55 ]
+# CHECK: Vreg: %117[ 2 ]
+# CHECK: Vreg: %29[ 56 ]
+# CHECK: Vreg: %17[ 15 ]
+# CHECK: Vreg: %50[ 55 ]
+# CHECK: Vreg: %114[ 48 ]
+# CHECK: Vreg: %19[ 12 ]
+# CHECK: Instr: %120:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %116[ 50 ]
+# CHECK: Vreg: %21[ 18 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %111[ 60 ]
+# CHECK: Vreg: %118[ 1 ]
+# CHECK: Vreg: %42[ 17 ]
+# CHECK: Vreg: %18[ 38 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %110[ 54 ]
+# CHECK: Vreg: %117[ 1 ]
+# CHECK: Vreg: %29[ 55 ]
+# CHECK: Vreg: %119[ 1 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %50[ 54 ]
+# CHECK: Vreg: %114[ 47 ]
+# CHECK: Vreg: %19[ 11 ]
+# CHECK: Instr: S_BRANCH %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 57 ]
+# CHECK: Vreg: %116[ 49 ]
+# CHECK: Vreg: %21[ 17 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ 59 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %42[ 16 ]
+# CHECK: Vreg: %120[ 0 ]
+# CHECK: Vreg: %18[ 37 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %110[ 53 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %29[ 54 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %17[ 13 ]
+# CHECK: Vreg: %50[ 53 ]
+# CHECK: Vreg: %114[ 46 ]
+# CHECK: Vreg: %19[ 10 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 57 ]
+# CHECK: Vreg: %116[ 49 ]
+# CHECK: Vreg: %21[ 17 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ 59 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %42[ 16 ]
+# CHECK: Vreg: %120[ 0 ]
+# CHECK: Vreg: %18[ 37 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %110[ 53 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %29[ 54 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %17[ 13 ]
+# CHECK: Vreg: %50[ 53 ]
+# CHECK: Vreg: %114[ 46 ]
+# CHECK: Vreg: %19[ 10 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: %121:sreg_32 = S_MOV_B32 -1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %135[ 4 ]
+# CHECK: Vreg: %142[ 11 ]
+# CHECK: Vreg: %111[ 8 ]
+# CHECK: Vreg: %139[ 9 ]
+# CHECK: Vreg: %129[ 19 ]
+# CHECK: Vreg: %110[ 21 ]
+# CHECK: Vreg: %29[ 22 ]
+# CHECK: Vreg: %50[ 21 ]
+# CHECK: Vreg: %147[ 17 ]
+# CHECK: Instr: %122:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 24 ]
+# CHECK: Vreg: %135[ 3 ]
+# CHECK: Vreg: %142[ 10 ]
+# CHECK: Vreg: %111[ 7 ]
+# CHECK: Vreg: %139[ 8 ]
+# CHECK: Vreg: %129[ 18 ]
+# CHECK: Vreg: %110[ 20 ]
+# CHECK: Vreg: %29[ 21 ]
+# CHECK: Vreg: %50[ 20 ]
+# CHECK: Vreg: %121[ 1 ]
+# CHECK: Vreg: %147[ 16 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %135[ 2 ]
+# CHECK: Vreg: %142[ 9 ]
+# CHECK: Vreg: %111[ 6 ]
+# CHECK: Vreg: %139[ 7 ]
+# CHECK: Vreg: %122[ 0 ]
+# CHECK: Vreg: %129[ 17 ]
+# CHECK: Vreg: %110[ 19 ]
+# CHECK: Vreg: %29[ 20 ]
+# CHECK: Vreg: %50[ 19 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %147[ 15 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 23 ]
+# CHECK: Vreg: %135[ 2 ]
+# CHECK: Vreg: %142[ 9 ]
+# CHECK: Vreg: %111[ 6 ]
+# CHECK: Vreg: %139[ 7 ]
+# CHECK: Vreg: %122[ 0 ]
+# CHECK: Vreg: %129[ 17 ]
+# CHECK: Vreg: %110[ 19 ]
+# CHECK: Vreg: %29[ 20 ]
+# CHECK: Vreg: %50[ 19 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %147[ 15 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: %123:vgpr_32 = PHI %124, %bb.7, %125, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %128[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %110[ 3 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %50[ 3 ]
+# CHECK: Instr: %126:vgpr_32 = PHI %127, %bb.7, %128, %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %128[ 0 ]
+# CHECK: Vreg: %123[ 6 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %110[ 3 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %50[ 3 ]
+# CHECK: Instr: SI_END_CF killed %129, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 6 ]
+# CHECK: Vreg: %123[ 5 ]
+# CHECK: Vreg: %129[ 0 ]
+# CHECK: Vreg: %110[ 2 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %126[ 3 ]
+# CHECK: Vreg: %50[ 2 ]
+# CHECK: Instr: S_BRANCH %bb.13
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %123[ 4 ]
+# CHECK: Vreg: %110[ 1 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %126[ 2 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 5 ]
+# CHECK: Vreg: %123[ 4 ]
+# CHECK: Vreg: %110[ 1 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %126[ 2 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: %130:sreg_32 = PHI %122, %bb.4, %131, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+23 ]
+# CHECK: Vreg: %135[ 2 ]
+# CHECK: Vreg: %142[ 9 ]
+# CHECK: Vreg: %111[ 6 ]
+# CHECK: Vreg: %139[ 7 ]
+# CHECK: Vreg: %122[ 0 ]
+# CHECK: Vreg: %129[ LoopTag+17 ]
+# CHECK: Vreg: %110[ LoopTag+19 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+20 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+19 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %147[ LoopTag+15 ]
+# CHECK: Instr: %132:sreg_32 = PHI %121, %bb.4, %133, %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+23 ]
+# CHECK: Vreg: %135[ 2 ]
+# CHECK: Vreg: %142[ 9 ]
+# CHECK: Vreg: %130[ 10 ]
+# CHECK: Vreg: %111[ 6 ]
+# CHECK: Vreg: %139[ 7 ]
+# CHECK: Vreg: %129[ LoopTag+17 ]
+# CHECK: Vreg: %110[ LoopTag+19 ]
+# CHECK: Vreg: %29[ LoopTag+20 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+19 ]
+# CHECK: Vreg: %121[ 0 ]
+# CHECK: Vreg: %147[ LoopTag+15 ]
+# CHECK: Instr: %133:sreg_32 = S_ADD_I32 %132, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+22 ]
+# CHECK: Vreg: %135[ 1 ]
+# CHECK: Vreg: %142[ 8 ]
+# CHECK: Vreg: %130[ 9 ]
+# CHECK: Vreg: %111[ 5 ]
+# CHECK: Vreg: %132[ 0 ]
+# CHECK: Vreg: %139[ 6 ]
+# CHECK: Vreg: %129[ LoopTag+16 ]
+# CHECK: Vreg: %110[ LoopTag+18 ]
+# CHECK: Vreg: %29[ LoopTag+19 ]
+# CHECK: Vreg: %50[ LoopTag+18 ]
+# CHECK: Vreg: %147[ LoopTag+14 ]
+# CHECK: Instr: %134:vgpr_32 = GLOBAL_LOAD_USHORT %135, 0, 0, implicit $exec :: (load (s16) from %ir.p4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %135[ 0 ]
+# CHECK: Vreg: %142[ 7 ]
+# CHECK: Vreg: %130[ 8 ]
+# CHECK: Vreg: %111[ 4 ]
+# CHECK: Vreg: %132[ 6 ]
+# CHECK: Vreg: %139[ 5 ]
+# CHECK: Vreg: %129[ LoopTag+15 ]
+# CHECK: Vreg: %110[ LoopTag+17 ]
+# CHECK: Vreg: %29[ LoopTag+18 ]
+# CHECK: Vreg: %133[ 3 ]
+# CHECK: Vreg: %50[ LoopTag+17 ]
+# CHECK: Vreg: %147[ LoopTag+13 ]
+# CHECK: Instr: %136:vgpr_32 = GLOBAL_LOAD_USHORT %135, 2, 0, implicit $exec :: (load (s16) from %ir.p4 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+20 ]
+# CHECK: Vreg: %135[ 0 ]
+# CHECK: Vreg: %142[ 6 ]
+# CHECK: Vreg: %130[ 7 ]
+# CHECK: Vreg: %111[ 3 ]
+# CHECK: Vreg: %132[ 5 ]
+# CHECK: Vreg: %139[ 4 ]
+# CHECK: Vreg: %134[ 1 ]
+# CHECK: Vreg: %129[ LoopTag+14 ]
+# CHECK: Vreg: %110[ LoopTag+16 ]
+# CHECK: Vreg: %29[ LoopTag+17 ]
+# CHECK: Vreg: %133[ 2 ]
+# CHECK: Vreg: %50[ LoopTag+16 ]
+# CHECK: Vreg: %147[ LoopTag+12 ]
+# CHECK: Instr: %137:vgpr_32 = V_LSHL_OR_B32_e64 killed %136, 16, killed %134, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %135[ 11 ]
+# CHECK: Vreg: %142[ 5 ]
+# CHECK: Vreg: %130[ 6 ]
+# CHECK: Vreg: %111[ 2 ]
+# CHECK: Vreg: %132[ 4 ]
+# CHECK: Vreg: %139[ 3 ]
+# CHECK: Vreg: %134[ 0 ]
+# CHECK: Vreg: %129[ LoopTag+13 ]
+# CHECK: Vreg: %110[ LoopTag+15 ]
+# CHECK: Vreg: %136[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+16 ]
+# CHECK: Vreg: %133[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+15 ]
+# CHECK: Vreg: %147[ LoopTag+11 ]
+# CHECK: Instr: %125:vgpr_32 = V_MUL_LO_U32_e64 killed %137, %133, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+18 ]
+# CHECK: Vreg: %135[ 10 ]
+# CHECK: Vreg: %142[ 4 ]
+# CHECK: Vreg: %130[ 5 ]
+# CHECK: Vreg: %111[ 1 ]
+# CHECK: Vreg: %137[ 0 ]
+# CHECK: Vreg: %132[ 3 ]
+# CHECK: Vreg: %139[ 2 ]
+# CHECK: Vreg: %129[ LoopTag+12 ]
+# CHECK: Vreg: %110[ LoopTag+14 ]
+# CHECK: Vreg: %29[ LoopTag+15 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+14 ]
+# CHECK: Vreg: %147[ LoopTag+10 ]
+# CHECK: Instr: %138:vgpr_32 = V_SUB_U32_e64 %125, %111, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+17 ]
+# CHECK: Vreg: %135[ 9 ]
+# CHECK: Vreg: %142[ 3 ]
+# CHECK: Vreg: %130[ 4 ]
+# CHECK: Vreg: %111[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %132[ 2 ]
+# CHECK: Vreg: %139[ 1 ]
+# CHECK: Vreg: %129[ LoopTag+11 ]
+# CHECK: Vreg: %110[ LoopTag+13 ]
+# CHECK: Vreg: %29[ LoopTag+14 ]
+# CHECK: Vreg: %133[ 5 ]
+# CHECK: Vreg: %50[ LoopTag+13 ]
+# CHECK: Vreg: %147[ LoopTag+9 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %139, killed %138, 0, 0, implicit $exec :: (store (s32) into %ir.p2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+16 ]
+# CHECK: Vreg: %135[ 8 ]
+# CHECK: Vreg: %142[ 2 ]
+# CHECK: Vreg: %130[ 3 ]
+# CHECK: Vreg: %111[ 12 ]
+# CHECK: Vreg: %125[ LoopTag+9 ]
+# CHECK: Vreg: %132[ 1 ]
+# CHECK: Vreg: %139[ 0 ]
+# CHECK: Vreg: %129[ LoopTag+10 ]
+# CHECK: Vreg: %110[ LoopTag+12 ]
+# CHECK: Vreg: %29[ LoopTag+13 ]
+# CHECK: Vreg: %138[ 0 ]
+# CHECK: Vreg: %133[ 4 ]
+# CHECK: Vreg: %50[ LoopTag+12 ]
+# CHECK: Vreg: %147[ LoopTag+8 ]
+# CHECK: Instr: %140:sreg_32 = S_ADD_I32 killed %132, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %135[ 7 ]
+# CHECK: Vreg: %142[ 1 ]
+# CHECK: Vreg: %130[ 2 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %125[ LoopTag+8 ]
+# CHECK: Vreg: %132[ 0 ]
+# CHECK: Vreg: %139[ 12 ]
+# CHECK: Vreg: %129[ LoopTag+9 ]
+# CHECK: Vreg: %110[ LoopTag+11 ]
+# CHECK: Vreg: %29[ LoopTag+12 ]
+# CHECK: Vreg: %133[ 3 ]
+# CHECK: Vreg: %50[ LoopTag+11 ]
+# CHECK: Vreg: %147[ LoopTag+7 ]
+# CHECK: Instr: %141:sreg_32 = V_CMP_GE_U32_e64 killed %140, %142, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+14 ]
+# CHECK: Vreg: %135[ 6 ]
+# CHECK: Vreg: %142[ 0 ]
+# CHECK: Vreg: %130[ 1 ]
+# CHECK: Vreg: %111[ 10 ]
+# CHECK: Vreg: %125[ LoopTag+7 ]
+# CHECK: Vreg: %139[ 11 ]
+# CHECK: Vreg: %129[ LoopTag+8 ]
+# CHECK: Vreg: %110[ LoopTag+10 ]
+# CHECK: Vreg: %29[ LoopTag+11 ]
+# CHECK: Vreg: %133[ 2 ]
+# CHECK: Vreg: %50[ LoopTag+10 ]
+# CHECK: Vreg: %140[ 0 ]
+# CHECK: Vreg: %147[ LoopTag+6 ]
+# CHECK: Instr: %131:sreg_32 = SI_IF_BREAK killed %141, killed %130, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+13 ]
+# CHECK: Vreg: %135[ 5 ]
+# CHECK: Vreg: %142[ 12 ]
+# CHECK: Vreg: %130[ 0 ]
+# CHECK: Vreg: %111[ 9 ]
+# CHECK: Vreg: %125[ LoopTag+6 ]
+# CHECK: Vreg: %139[ 10 ]
+# CHECK: Vreg: %141[ 0 ]
+# CHECK: Vreg: %129[ LoopTag+7 ]
+# CHECK: Vreg: %110[ LoopTag+9 ]
+# CHECK: Vreg: %29[ LoopTag+10 ]
+# CHECK: Vreg: %133[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+9 ]
+# CHECK: Vreg: %147[ LoopTag+5 ]
+# CHECK: Instr: %143:vgpr_32 = COPY %133, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %135[ 4 ]
+# CHECK: Vreg: %142[ 11 ]
+# CHECK: Vreg: %111[ 8 ]
+# CHECK: Vreg: %125[ LoopTag+5 ]
+# CHECK: Vreg: %139[ 9 ]
+# CHECK: Vreg: %129[ LoopTag+6 ]
+# CHECK: Vreg: %110[ LoopTag+8 ]
+# CHECK: Vreg: %131[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+9 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+8 ]
+# CHECK: Vreg: %147[ LoopTag+4 ]
+# CHECK: Instr: SI_LOOP %131, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+11 ]
+# CHECK: Vreg: %135[ 3 ]
+# CHECK: Vreg: %142[ 10 ]
+# CHECK: Vreg: %111[ 7 ]
+# CHECK: Vreg: %125[ LoopTag+4 ]
+# CHECK: Vreg: %139[ 8 ]
+# CHECK: Vreg: %129[ LoopTag+5 ]
+# CHECK: Vreg: %110[ LoopTag+7 ]
+# CHECK: Vreg: %143[ LoopTag+3 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+8 ]
+# CHECK: Vreg: %133[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+7 ]
+# CHECK: Vreg: %147[ LoopTag+3 ]
+# CHECK: Instr: S_BRANCH %bb.11
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %135[ 2 ]
+# CHECK: Vreg: %142[ 9 ]
+# CHECK: Vreg: %111[ 6 ]
+# CHECK: Vreg: %125[ LoopTag+3 ]
+# CHECK: Vreg: %139[ 7 ]
+# CHECK: Vreg: %129[ LoopTag+4 ]
+# CHECK: Vreg: %110[ LoopTag+6 ]
+# CHECK: Vreg: %143[ LoopTag+2 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+7 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+6 ]
+# CHECK: Vreg: %147[ LoopTag+2 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %135[ 2 ]
+# CHECK: Vreg: %142[ 9 ]
+# CHECK: Vreg: %111[ 6 ]
+# CHECK: Vreg: %125[ LoopTag+3 ]
+# CHECK: Vreg: %139[ 7 ]
+# CHECK: Vreg: %129[ LoopTag+4 ]
+# CHECK: Vreg: %110[ LoopTag+6 ]
+# CHECK: Vreg: %143[ LoopTag+2 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+7 ]
+# CHECK: Vreg: %133[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+6 ]
+# CHECK: Vreg: %147[ LoopTag+2 ]
+# CHECK: --- MBB_7 ---
+# CHECK: Instr: %124:vgpr_32 = PHI undef %144:vgpr_32, %bb.2, %145, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Instr: %127:vgpr_32 = PHI undef %144:vgpr_32, %bb.2, %146, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %124[ 2 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Instr: %147:vgpr_32 = PHI %114, %bb.2, undef %148:vgpr_32, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %127[ 2 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %124[ 2 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Instr: %135:vreg_64 = PHI %19, %bb.2, undef %149:vreg_64, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %127[ 2 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %124[ 2 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %147[ 20 ]
+# CHECK: Instr: %139:vreg_64 = PHI %21, %bb.2, undef %150:vreg_64, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %135[ 7 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %127[ 2 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %124[ 2 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %147[ 20 ]
+# CHECK: Instr: %142:vgpr_32 = PHI %3, %bb.2, undef %151:vgpr_32, %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %135[ 7 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %139[ 12 ]
+# CHECK: Vreg: %127[ 2 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %124[ 2 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %147[ 20 ]
+# CHECK: Instr: %129:sreg_32 = SI_ELSE killed %116, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %135[ 6 ]
+# CHECK: Vreg: %116[ 0 ]
+# CHECK: Vreg: %142[ 13 ]
+# CHECK: Vreg: %111[ 10 ]
+# CHECK: Vreg: %139[ 11 ]
+# CHECK: Vreg: %127[ 1 ]
+# CHECK: Vreg: %110[ 4 ]
+# CHECK: Vreg: %124[ 1 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %50[ 4 ]
+# CHECK: Vreg: %147[ 19 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %135[ 5 ]
+# CHECK: Vreg: %142[ 12 ]
+# CHECK: Vreg: %111[ 9 ]
+# CHECK: Vreg: %139[ 10 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %110[ 3 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %50[ 3 ]
+# CHECK: Vreg: %147[ 18 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %135[ 5 ]
+# CHECK: Vreg: %142[ 12 ]
+# CHECK: Vreg: %111[ 9 ]
+# CHECK: Vreg: %139[ 10 ]
+# CHECK: Vreg: %127[ 0 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %110[ 3 ]
+# CHECK: Vreg: %124[ 0 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %50[ 3 ]
+# CHECK: Vreg: %147[ 18 ]
+# CHECK: --- MBB_8 ---
+# CHECK: Instr: %152:sreg_32 = PHI %120, %bb.3, %153, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+57 ]
+# CHECK: Vreg: %116[ LoopTag+49 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ LoopTag+59 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+16 ]
+# CHECK: Vreg: %120[ 0 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+40 ]
+# CHECK: Vreg: %110[ LoopTag+53 ]
+# CHECK: Vreg: %155[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+54 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+13 ]
+# CHECK: Vreg: %50[ LoopTag+53 ]
+# CHECK: Vreg: %114[ LoopTag+46 ]
+# CHECK: Vreg: %19[ LoopTag+10 ]
+# CHECK: Instr: %154:vgpr_32 = PHI %118, %bb.3, %155, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+57 ]
+# CHECK: Vreg: %116[ LoopTag+49 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ LoopTag+59 ]
+# CHECK: Vreg: %118[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+16 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %1[ LoopTag+40 ]
+# CHECK: Vreg: %110[ LoopTag+53 ]
+# CHECK: Vreg: %155[ 0 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+54 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+13 ]
+# CHECK: Vreg: %152[ 5 ]
+# CHECK: Vreg: %50[ LoopTag+53 ]
+# CHECK: Vreg: %114[ LoopTag+46 ]
+# CHECK: Vreg: %19[ LoopTag+10 ]
+# CHECK: Instr: %156:sreg_32 = PHI %119, %bb.3, %157, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+57 ]
+# CHECK: Vreg: %154[ 0 ]
+# CHECK: Vreg: %116[ LoopTag+49 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ LoopTag+59 ]
+# CHECK: Vreg: %42[ LoopTag+16 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %1[ LoopTag+40 ]
+# CHECK: Vreg: %110[ LoopTag+53 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+54 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %119[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+13 ]
+# CHECK: Vreg: %152[ 5 ]
+# CHECK: Vreg: %50[ LoopTag+53 ]
+# CHECK: Vreg: %114[ LoopTag+46 ]
+# CHECK: Vreg: %19[ LoopTag+10 ]
+# CHECK: Instr: %158:vgpr_32 = PHI %117, %bb.3, %154, %bb.8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+57 ]
+# CHECK: Vreg: %154[ 0 ]
+# CHECK: Vreg: %116[ LoopTag+49 ]
+# CHECK: Vreg: %21[ LoopTag+17 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ LoopTag+59 ]
+# CHECK: Vreg: %156[ 1 ]
+# CHECK: Vreg: %42[ LoopTag+16 ]
+# CHECK: Vreg: %18[ LoopTag+37 ]
+# CHECK: Vreg: %1[ LoopTag+40 ]
+# CHECK: Vreg: %110[ LoopTag+53 ]
+# CHECK: Vreg: %117[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+54 ]
+# CHECK: Vreg: %17[ LoopTag+13 ]
+# CHECK: Vreg: %152[ 5 ]
+# CHECK: Vreg: %50[ LoopTag+53 ]
+# CHECK: Vreg: %114[ LoopTag+46 ]
+# CHECK: Vreg: %19[ LoopTag+10 ]
+# CHECK: Instr: %157:sreg_32 = nuw S_ADD_I32 %156, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+56 ]
+# CHECK: Vreg: %154[ 2 ]
+# CHECK: Vreg: %116[ LoopTag+48 ]
+# CHECK: Vreg: %21[ LoopTag+16 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %111[ LoopTag+58 ]
+# CHECK: Vreg: %156[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+15 ]
+# CHECK: Vreg: %158[ LoopTag+10 ]
+# CHECK: Vreg: %18[ LoopTag+36 ]
+# CHECK: Vreg: %1[ LoopTag+39 ]
+# CHECK: Vreg: %110[ LoopTag+52 ]
+# CHECK: Vreg: %29[ LoopTag+53 ]
+# CHECK: Vreg: %17[ LoopTag+12 ]
+# CHECK: Vreg: %152[ 4 ]
+# CHECK: Vreg: %50[ LoopTag+52 ]
+# CHECK: Vreg: %114[ LoopTag+45 ]
+# CHECK: Vreg: %19[ LoopTag+9 ]
+# CHECK: Instr: %159:sreg_32 = S_ADD_I32 killed %156, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+55 ]
+# CHECK: Vreg: %154[ 1 ]
+# CHECK: Vreg: %116[ LoopTag+47 ]
+# CHECK: Vreg: %21[ LoopTag+15 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %111[ LoopTag+57 ]
+# CHECK: Vreg: %156[ 0 ]
+# CHECK: Vreg: %42[ LoopTag+14 ]
+# CHECK: Vreg: %158[ LoopTag+9 ]
+# CHECK: Vreg: %18[ LoopTag+35 ]
+# CHECK: Vreg: %1[ LoopTag+38 ]
+# CHECK: Vreg: %110[ LoopTag+51 ]
+# CHECK: Vreg: %29[ LoopTag+52 ]
+# CHECK: Vreg: %157[ 4 ]
+# CHECK: Vreg: %17[ LoopTag+11 ]
+# CHECK: Vreg: %152[ 3 ]
+# CHECK: Vreg: %50[ LoopTag+51 ]
+# CHECK: Vreg: %114[ LoopTag+44 ]
+# CHECK: Vreg: %19[ LoopTag+8 ]
+# CHECK: Instr: %155:vgpr_32 = V_ADD_U32_e64 -1, %154, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+54 ]
+# CHECK: Vreg: %154[ 0 ]
+# CHECK: Vreg: %116[ LoopTag+46 ]
+# CHECK: Vreg: %21[ LoopTag+14 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %111[ LoopTag+56 ]
+# CHECK: Vreg: %42[ LoopTag+13 ]
+# CHECK: Vreg: %158[ LoopTag+8 ]
+# CHECK: Vreg: %18[ LoopTag+34 ]
+# CHECK: Vreg: %1[ LoopTag+37 ]
+# CHECK: Vreg: %110[ LoopTag+50 ]
+# CHECK: Vreg: %29[ LoopTag+51 ]
+# CHECK: Vreg: %157[ 3 ]
+# CHECK: Vreg: %17[ LoopTag+10 ]
+# CHECK: Vreg: %152[ 2 ]
+# CHECK: Vreg: %50[ LoopTag+50 ]
+# CHECK: Vreg: %114[ LoopTag+43 ]
+# CHECK: Vreg: %159[ 1 ]
+# CHECK: Vreg: %19[ LoopTag+7 ]
+# CHECK: Instr: %160:sreg_32 = V_CMP_GE_U32_e64 killed %159, %2, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+53 ]
+# CHECK: Vreg: %154[ LoopTag+6 ]
+# CHECK: Vreg: %116[ LoopTag+45 ]
+# CHECK: Vreg: %21[ LoopTag+13 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %111[ LoopTag+55 ]
+# CHECK: Vreg: %42[ LoopTag+12 ]
+# CHECK: Vreg: %158[ LoopTag+7 ]
+# CHECK: Vreg: %18[ LoopTag+33 ]
+# CHECK: Vreg: %1[ LoopTag+36 ]
+# CHECK: Vreg: %110[ LoopTag+49 ]
+# CHECK: Vreg: %155[ 4 ]
+# CHECK: Vreg: %29[ LoopTag+50 ]
+# CHECK: Vreg: %157[ 2 ]
+# CHECK: Vreg: %17[ LoopTag+9 ]
+# CHECK: Vreg: %152[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+49 ]
+# CHECK: Vreg: %114[ LoopTag+42 ]
+# CHECK: Vreg: %159[ 0 ]
+# CHECK: Vreg: %19[ LoopTag+6 ]
+# CHECK: Instr: %153:sreg_32 = SI_IF_BREAK killed %160, killed %152, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+52 ]
+# CHECK: Vreg: %154[ LoopTag+5 ]
+# CHECK: Vreg: %116[ LoopTag+44 ]
+# CHECK: Vreg: %21[ LoopTag+12 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %111[ LoopTag+54 ]
+# CHECK: Vreg: %42[ LoopTag+11 ]
+# CHECK: Vreg: %158[ LoopTag+6 ]
+# CHECK: Vreg: %18[ LoopTag+32 ]
+# CHECK: Vreg: %160[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+35 ]
+# CHECK: Vreg: %110[ LoopTag+48 ]
+# CHECK: Vreg: %155[ 3 ]
+# CHECK: Vreg: %29[ LoopTag+49 ]
+# CHECK: Vreg: %157[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+8 ]
+# CHECK: Vreg: %152[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+48 ]
+# CHECK: Vreg: %114[ LoopTag+41 ]
+# CHECK: Vreg: %19[ LoopTag+5 ]
+# CHECK: Instr: %161:vgpr_32 = COPY %157, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+51 ]
+# CHECK: Vreg: %154[ LoopTag+4 ]
+# CHECK: Vreg: %116[ LoopTag+43 ]
+# CHECK: Vreg: %21[ LoopTag+11 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %111[ LoopTag+53 ]
+# CHECK: Vreg: %42[ LoopTag+10 ]
+# CHECK: Vreg: %158[ LoopTag+5 ]
+# CHECK: Vreg: %18[ LoopTag+31 ]
+# CHECK: Vreg: %153[ 1 ]
+# CHECK: Vreg: %1[ LoopTag+34 ]
+# CHECK: Vreg: %110[ LoopTag+47 ]
+# CHECK: Vreg: %155[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+48 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+7 ]
+# CHECK: Vreg: %50[ LoopTag+47 ]
+# CHECK: Vreg: %114[ LoopTag+40 ]
+# CHECK: Vreg: %19[ LoopTag+4 ]
+# CHECK: Instr: SI_LOOP %153, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+50 ]
+# CHECK: Vreg: %154[ LoopTag+3 ]
+# CHECK: Vreg: %116[ LoopTag+42 ]
+# CHECK: Vreg: %161[ LoopTag+39 ]
+# CHECK: Vreg: %21[ LoopTag+10 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %111[ LoopTag+52 ]
+# CHECK: Vreg: %42[ LoopTag+9 ]
+# CHECK: Vreg: %158[ LoopTag+4 ]
+# CHECK: Vreg: %18[ LoopTag+30 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+33 ]
+# CHECK: Vreg: %110[ LoopTag+46 ]
+# CHECK: Vreg: %155[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+47 ]
+# CHECK: Vreg: %157[ 1 ]
+# CHECK: Vreg: %17[ LoopTag+6 ]
+# CHECK: Vreg: %50[ LoopTag+46 ]
+# CHECK: Vreg: %114[ LoopTag+39 ]
+# CHECK: Vreg: %19[ LoopTag+3 ]
+# CHECK: Instr: S_BRANCH %bb.9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+49 ]
+# CHECK: Vreg: %154[ LoopTag+2 ]
+# CHECK: Vreg: %116[ LoopTag+41 ]
+# CHECK: Vreg: %161[ LoopTag+38 ]
+# CHECK: Vreg: %21[ LoopTag+9 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ LoopTag+51 ]
+# CHECK: Vreg: %42[ LoopTag+8 ]
+# CHECK: Vreg: %158[ LoopTag+3 ]
+# CHECK: Vreg: %18[ LoopTag+29 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+32 ]
+# CHECK: Vreg: %110[ LoopTag+45 ]
+# CHECK: Vreg: %155[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+46 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+5 ]
+# CHECK: Vreg: %50[ LoopTag+45 ]
+# CHECK: Vreg: %114[ LoopTag+38 ]
+# CHECK: Vreg: %19[ LoopTag+2 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+49 ]
+# CHECK: Vreg: %154[ LoopTag+2 ]
+# CHECK: Vreg: %116[ LoopTag+41 ]
+# CHECK: Vreg: %161[ LoopTag+38 ]
+# CHECK: Vreg: %21[ LoopTag+9 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %111[ LoopTag+51 ]
+# CHECK: Vreg: %42[ LoopTag+8 ]
+# CHECK: Vreg: %158[ LoopTag+3 ]
+# CHECK: Vreg: %18[ LoopTag+29 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %1[ LoopTag+32 ]
+# CHECK: Vreg: %110[ LoopTag+45 ]
+# CHECK: Vreg: %155[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+46 ]
+# CHECK: Vreg: %157[ 0 ]
+# CHECK: Vreg: %17[ LoopTag+5 ]
+# CHECK: Vreg: %50[ LoopTag+45 ]
+# CHECK: Vreg: %114[ LoopTag+38 ]
+# CHECK: Vreg: %19[ LoopTag+2 ]
+# CHECK: --- MBB_9 ---
+# CHECK: Instr: SI_END_CF killed %153, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 48 ]
+# CHECK: Vreg: %154[ 1 ]
+# CHECK: Vreg: %116[ 40 ]
+# CHECK: Vreg: %161[ 37 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %111[ 50 ]
+# CHECK: Vreg: %42[ 7 ]
+# CHECK: Vreg: %158[ 2 ]
+# CHECK: Vreg: %18[ 28 ]
+# CHECK: Vreg: %153[ 0 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %110[ 44 ]
+# CHECK: Vreg: %29[ 45 ]
+# CHECK: Vreg: %17[ 4 ]
+# CHECK: Vreg: %50[ 44 ]
+# CHECK: Vreg: %114[ 37 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD killed %19, killed %154, 0, 0, implicit $exec :: (store (s32) into %ir.p4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %154[ 0 ]
+# CHECK: Vreg: %116[ 39 ]
+# CHECK: Vreg: %161[ 36 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %111[ 49 ]
+# CHECK: Vreg: %42[ 6 ]
+# CHECK: Vreg: %158[ 1 ]
+# CHECK: Vreg: %18[ 27 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %110[ 43 ]
+# CHECK: Vreg: %29[ 44 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Vreg: %50[ 43 ]
+# CHECK: Vreg: %114[ 36 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %162:vreg_64 = REG_SEQUENCE %158, %subreg.sub0, undef %163:vgpr_32, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %116[ 38 ]
+# CHECK: Vreg: %161[ 35 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %111[ 48 ]
+# CHECK: Vreg: %42[ 5 ]
+# CHECK: Vreg: %158[ 0 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %110[ 42 ]
+# CHECK: Vreg: %29[ 43 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %50[ 42 ]
+# CHECK: Vreg: %114[ 35 ]
+# CHECK: Instr: %164:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %116[ 37 ]
+# CHECK: Vreg: %161[ 34 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %111[ 47 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %158[ 16 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %110[ 41 ]
+# CHECK: Vreg: %162:sub0[ 14 ]
+# CHECK: Vreg: %29[ 42 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %50[ 41 ]
+# CHECK: Vreg: %114[ 34 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %116[ 37 ]
+# CHECK: Vreg: %161[ 34 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %111[ 47 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %158[ 16 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %110[ 41 ]
+# CHECK: Vreg: %162:sub0[ 14 ]
+# CHECK: Vreg: %29[ 42 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %50[ 41 ]
+# CHECK: Vreg: %114[ 34 ]
+# CHECK: --- MBB_10 ---
+# CHECK: Instr: %165:sreg_32 = PHI %164, %bb.9, %166, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+45 ]
+# CHECK: Vreg: %116[ LoopTag+37 ]
+# CHECK: Vreg: %161[ LoopTag+34 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %111[ LoopTag+47 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %170[ 0 ]
+# CHECK: Vreg: %158[ 16 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %110[ LoopTag+41 ]
+# CHECK: Vreg: %162:sub0[ 14 ]
+# CHECK: Vreg: %29[ LoopTag+42 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+41 ]
+# CHECK: Vreg: %114[ LoopTag+34 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Instr: %167:sreg_32 = PHI %164, %bb.9, %168, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+45 ]
+# CHECK: Vreg: %116[ LoopTag+37 ]
+# CHECK: Vreg: %161[ LoopTag+34 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %111[ LoopTag+47 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %170[ 0 ]
+# CHECK: Vreg: %158[ 16 ]
+# CHECK: Vreg: %165[ 29 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %110[ LoopTag+41 ]
+# CHECK: Vreg: %162:sub0[ 14 ]
+# CHECK: Vreg: %29[ LoopTag+42 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+41 ]
+# CHECK: Vreg: %114[ LoopTag+34 ]
+# CHECK: Instr: %169:sreg_32 = PHI %164, %bb.9, %170, %bb.10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+45 ]
+# CHECK: Vreg: %116[ LoopTag+37 ]
+# CHECK: Vreg: %161[ LoopTag+34 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %111[ LoopTag+47 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %170[ 0 ]
+# CHECK: Vreg: %158[ 16 ]
+# CHECK: Vreg: %165[ 29 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %167[ 11 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %110[ LoopTag+41 ]
+# CHECK: Vreg: %162:sub0[ 14 ]
+# CHECK: Vreg: %29[ LoopTag+42 ]
+# CHECK: Vreg: %164[ 0 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+41 ]
+# CHECK: Vreg: %114[ LoopTag+34 ]
+# CHECK: Instr: %171:vgpr_32 = GLOBAL_LOAD_USHORT %17, 0, 0, implicit $exec :: (load (s16) from %ir.p6, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+44 ]
+# CHECK: Vreg: %116[ LoopTag+36 ]
+# CHECK: Vreg: %161[ LoopTag+33 ]
+# CHECK: Vreg: %21[ 4 ]
+# CHECK: Vreg: %111[ LoopTag+46 ]
+# CHECK: Vreg: %42[ 3 ]
+# CHECK: Vreg: %158[ 15 ]
+# CHECK: Vreg: %165[ 28 ]
+# CHECK: Vreg: %18[ 24 ]
+# CHECK: Vreg: %167[ 10 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %110[ LoopTag+40 ]
+# CHECK: Vreg: %162:sub0[ 13 ]
+# CHECK: Vreg: %169[ 3 ]
+# CHECK: Vreg: %29[ LoopTag+41 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+40 ]
+# CHECK: Vreg: %114[ LoopTag+33 ]
+# CHECK: Instr: %172:vgpr_32 = GLOBAL_LOAD_USHORT %17, 2, 0, implicit $exec :: (load (s16) from %ir.p6 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+43 ]
+# CHECK: Vreg: %116[ LoopTag+35 ]
+# CHECK: Vreg: %161[ LoopTag+32 ]
+# CHECK: Vreg: %21[ 3 ]
+# CHECK: Vreg: %111[ LoopTag+45 ]
+# CHECK: Vreg: %42[ 2 ]
+# CHECK: Vreg: %158[ 14 ]
+# CHECK: Vreg: %165[ 27 ]
+# CHECK: Vreg: %18[ 23 ]
+# CHECK: Vreg: %167[ 9 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %110[ LoopTag+39 ]
+# CHECK: Vreg: %162:sub0[ 12 ]
+# CHECK: Vreg: %169[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+40 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %171[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+39 ]
+# CHECK: Vreg: %114[ LoopTag+32 ]
+# CHECK: Instr: %173:vgpr_32 = V_LSHL_OR_B32_e64 killed %172, 16, killed %171, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+42 ]
+# CHECK: Vreg: %116[ LoopTag+34 ]
+# CHECK: Vreg: %161[ LoopTag+31 ]
+# CHECK: Vreg: %21[ 2 ]
+# CHECK: Vreg: %111[ LoopTag+44 ]
+# CHECK: Vreg: %42[ 1 ]
+# CHECK: Vreg: %158[ 13 ]
+# CHECK: Vreg: %165[ 26 ]
+# CHECK: Vreg: %18[ 22 ]
+# CHECK: Vreg: %172[ 0 ]
+# CHECK: Vreg: %167[ 8 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %110[ LoopTag+38 ]
+# CHECK: Vreg: %162:sub0[ 11 ]
+# CHECK: Vreg: %169[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+39 ]
+# CHECK: Vreg: %17[ 30 ]
+# CHECK: Vreg: %171[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+38 ]
+# CHECK: Vreg: %114[ LoopTag+31 ]
+# CHECK: Instr: %174:vgpr_32 = V_ADD_U32_e64 %169, %42, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+41 ]
+# CHECK: Vreg: %173[ LoopTag+31 ]
+# CHECK: Vreg: %116[ LoopTag+33 ]
+# CHECK: Vreg: %161[ LoopTag+30 ]
+# CHECK: Vreg: %21[ 1 ]
+# CHECK: Vreg: %111[ LoopTag+43 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %158[ 12 ]
+# CHECK: Vreg: %165[ 25 ]
+# CHECK: Vreg: %18[ 21 ]
+# CHECK: Vreg: %167[ 7 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %110[ LoopTag+37 ]
+# CHECK: Vreg: %162:sub0[ 10 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+38 ]
+# CHECK: Vreg: %17[ 29 ]
+# CHECK: Vreg: %50[ LoopTag+37 ]
+# CHECK: Vreg: %114[ LoopTag+30 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %21, killed %174, 0, 0, implicit $exec :: (store (s32) into %ir.p2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+40 ]
+# CHECK: Vreg: %173[ LoopTag+30 ]
+# CHECK: Vreg: %116[ LoopTag+32 ]
+# CHECK: Vreg: %161[ LoopTag+29 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %111[ LoopTag+42 ]
+# CHECK: Vreg: %42[ 31 ]
+# CHECK: Vreg: %158[ 11 ]
+# CHECK: Vreg: %165[ 24 ]
+# CHECK: Vreg: %18[ 20 ]
+# CHECK: Vreg: %167[ 6 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %110[ LoopTag+36 ]
+# CHECK: Vreg: %174[ 0 ]
+# CHECK: Vreg: %162:sub0[ 9 ]
+# CHECK: Vreg: %169[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+37 ]
+# CHECK: Vreg: %17[ 28 ]
+# CHECK: Vreg: %50[ LoopTag+36 ]
+# CHECK: Vreg: %114[ LoopTag+29 ]
+# CHECK: Instr: %175:sgpr_32 = S_CVT_F32_U32 %169, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+39 ]
+# CHECK: Vreg: %173[ LoopTag+29 ]
+# CHECK: Vreg: %116[ LoopTag+31 ]
+# CHECK: Vreg: %161[ LoopTag+28 ]
+# CHECK: Vreg: %21[ 31 ]
+# CHECK: Vreg: %111[ LoopTag+41 ]
+# CHECK: Vreg: %42[ 30 ]
+# CHECK: Vreg: %158[ 10 ]
+# CHECK: Vreg: %165[ 23 ]
+# CHECK: Vreg: %18[ 19 ]
+# CHECK: Vreg: %167[ 5 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %110[ LoopTag+35 ]
+# CHECK: Vreg: %162:sub0[ 8 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+36 ]
+# CHECK: Vreg: %17[ 27 ]
+# CHECK: Vreg: %50[ LoopTag+35 ]
+# CHECK: Vreg: %114[ LoopTag+28 ]
+# CHECK: Instr: %176:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %175, 0, 0, implicit $mode, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+38 ]
+# CHECK: Vreg: %173[ LoopTag+28 ]
+# CHECK: Vreg: %116[ LoopTag+30 ]
+# CHECK: Vreg: %161[ LoopTag+27 ]
+# CHECK: Vreg: %21[ 30 ]
+# CHECK: Vreg: %111[ LoopTag+40 ]
+# CHECK: Vreg: %175[ 0 ]
+# CHECK: Vreg: %42[ 29 ]
+# CHECK: Vreg: %158[ 9 ]
+# CHECK: Vreg: %165[ 22 ]
+# CHECK: Vreg: %18[ 18 ]
+# CHECK: Vreg: %167[ 4 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %110[ LoopTag+34 ]
+# CHECK: Vreg: %162:sub0[ 7 ]
+# CHECK: Vreg: %169[ 8 ]
+# CHECK: Vreg: %29[ LoopTag+35 ]
+# CHECK: Vreg: %17[ 26 ]
+# CHECK: Vreg: %50[ LoopTag+34 ]
+# CHECK: Vreg: %114[ LoopTag+27 ]
+# CHECK: Instr: %177:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %176, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+37 ]
+# CHECK: Vreg: %173[ LoopTag+27 ]
+# CHECK: Vreg: %116[ LoopTag+29 ]
+# CHECK: Vreg: %161[ LoopTag+26 ]
+# CHECK: Vreg: %21[ 29 ]
+# CHECK: Vreg: %111[ LoopTag+39 ]
+# CHECK: Vreg: %42[ 28 ]
+# CHECK: Vreg: %158[ 8 ]
+# CHECK: Vreg: %165[ 21 ]
+# CHECK: Vreg: %18[ 17 ]
+# CHECK: Vreg: %167[ 3 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %110[ LoopTag+33 ]
+# CHECK: Vreg: %162:sub0[ 6 ]
+# CHECK: Vreg: %169[ 7 ]
+# CHECK: Vreg: %176[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+34 ]
+# CHECK: Vreg: %17[ 25 ]
+# CHECK: Vreg: %50[ LoopTag+33 ]
+# CHECK: Vreg: %114[ LoopTag+26 ]
+# CHECK: Instr: %178:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %177, 1333788670, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+36 ]
+# CHECK: Vreg: %173[ LoopTag+26 ]
+# CHECK: Vreg: %116[ LoopTag+28 ]
+# CHECK: Vreg: %161[ LoopTag+25 ]
+# CHECK: Vreg: %21[ 28 ]
+# CHECK: Vreg: %111[ LoopTag+38 ]
+# CHECK: Vreg: %42[ 27 ]
+# CHECK: Vreg: %177[ 0 ]
+# CHECK: Vreg: %158[ 7 ]
+# CHECK: Vreg: %165[ 20 ]
+# CHECK: Vreg: %18[ 16 ]
+# CHECK: Vreg: %167[ 2 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %110[ LoopTag+32 ]
+# CHECK: Vreg: %162:sub0[ 5 ]
+# CHECK: Vreg: %169[ 6 ]
+# CHECK: Vreg: %29[ LoopTag+33 ]
+# CHECK: Vreg: %17[ 24 ]
+# CHECK: Vreg: %50[ LoopTag+32 ]
+# CHECK: Vreg: %114[ LoopTag+25 ]
+# CHECK: Instr: %179:sreg_32 = nofpexcept S_CVT_U32_F32 killed %178, implicit $mode
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+35 ]
+# CHECK: Vreg: %173[ LoopTag+25 ]
+# CHECK: Vreg: %116[ LoopTag+27 ]
+# CHECK: Vreg: %161[ LoopTag+24 ]
+# CHECK: Vreg: %21[ 27 ]
+# CHECK: Vreg: %111[ LoopTag+37 ]
+# CHECK: Vreg: %42[ 26 ]
+# CHECK: Vreg: %158[ 6 ]
+# CHECK: Vreg: %165[ 19 ]
+# CHECK: Vreg: %18[ 15 ]
+# CHECK: Vreg: %167[ 1 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %110[ LoopTag+31 ]
+# CHECK: Vreg: %162:sub0[ 4 ]
+# CHECK: Vreg: %169[ 5 ]
+# CHECK: Vreg: %29[ LoopTag+32 ]
+# CHECK: Vreg: %17[ 23 ]
+# CHECK: Vreg: %50[ LoopTag+31 ]
+# CHECK: Vreg: %114[ LoopTag+24 ]
+# CHECK: Vreg: %178[ 0 ]
+# CHECK: Instr: %180:sreg_32 = S_MUL_I32 %167, %179
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+34 ]
+# CHECK: Vreg: %173[ LoopTag+24 ]
+# CHECK: Vreg: %116[ LoopTag+26 ]
+# CHECK: Vreg: %161[ LoopTag+23 ]
+# CHECK: Vreg: %21[ 26 ]
+# CHECK: Vreg: %111[ LoopTag+36 ]
+# CHECK: Vreg: %42[ 25 ]
+# CHECK: Vreg: %158[ 5 ]
+# CHECK: Vreg: %165[ 18 ]
+# CHECK: Vreg: %18[ 14 ]
+# CHECK: Vreg: %179[ 0 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %110[ LoopTag+30 ]
+# CHECK: Vreg: %162:sub0[ 3 ]
+# CHECK: Vreg: %169[ 4 ]
+# CHECK: Vreg: %29[ LoopTag+31 ]
+# CHECK: Vreg: %17[ 22 ]
+# CHECK: Vreg: %50[ LoopTag+30 ]
+# CHECK: Vreg: %114[ LoopTag+23 ]
+# CHECK: Instr: %181:sreg_32 = S_MUL_HI_U32 %179, killed %180
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+33 ]
+# CHECK: Vreg: %173[ LoopTag+23 ]
+# CHECK: Vreg: %116[ LoopTag+25 ]
+# CHECK: Vreg: %161[ LoopTag+22 ]
+# CHECK: Vreg: %180[ 0 ]
+# CHECK: Vreg: %21[ 25 ]
+# CHECK: Vreg: %111[ LoopTag+35 ]
+# CHECK: Vreg: %42[ 24 ]
+# CHECK: Vreg: %158[ 4 ]
+# CHECK: Vreg: %165[ 17 ]
+# CHECK: Vreg: %18[ 13 ]
+# CHECK: Vreg: %179[ 0 ]
+# CHECK: Vreg: %167[ 15 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %110[ LoopTag+29 ]
+# CHECK: Vreg: %162:sub0[ 2 ]
+# CHECK: Vreg: %169[ 3 ]
+# CHECK: Vreg: %29[ LoopTag+30 ]
+# CHECK: Vreg: %17[ 21 ]
+# CHECK: Vreg: %50[ LoopTag+29 ]
+# CHECK: Vreg: %114[ LoopTag+22 ]
+# CHECK: Instr: %182:sreg_32 = S_ADD_I32 killed %179, killed %181, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+32 ]
+# CHECK: Vreg: %173[ LoopTag+22 ]
+# CHECK: Vreg: %116[ LoopTag+24 ]
+# CHECK: Vreg: %161[ LoopTag+21 ]
+# CHECK: Vreg: %21[ 24 ]
+# CHECK: Vreg: %111[ LoopTag+34 ]
+# CHECK: Vreg: %42[ 23 ]
+# CHECK: Vreg: %158[ 3 ]
+# CHECK: Vreg: %165[ 16 ]
+# CHECK: Vreg: %18[ 12 ]
+# CHECK: Vreg: %179[ 0 ]
+# CHECK: Vreg: %167[ 14 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %110[ LoopTag+28 ]
+# CHECK: Vreg: %181[ 0 ]
+# CHECK: Vreg: %162:sub0[ 1 ]
+# CHECK: Vreg: %169[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+29 ]
+# CHECK: Vreg: %17[ 20 ]
+# CHECK: Vreg: %50[ LoopTag+28 ]
+# CHECK: Vreg: %114[ LoopTag+21 ]
+# CHECK: Instr: %183:vgpr_32 = V_MUL_HI_U32_e64 %162.sub0, killed %182, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+31 ]
+# CHECK: Vreg: %173[ LoopTag+21 ]
+# CHECK: Vreg: %116[ LoopTag+23 ]
+# CHECK: Vreg: %161[ LoopTag+20 ]
+# CHECK: Vreg: %21[ 23 ]
+# CHECK: Vreg: %111[ LoopTag+33 ]
+# CHECK: Vreg: %182[ 0 ]
+# CHECK: Vreg: %42[ 22 ]
+# CHECK: Vreg: %158[ 2 ]
+# CHECK: Vreg: %165[ 15 ]
+# CHECK: Vreg: %18[ 11 ]
+# CHECK: Vreg: %167[ 13 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %110[ LoopTag+27 ]
+# CHECK: Vreg: %162:sub0[ 0 ]
+# CHECK: Vreg: %169[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+28 ]
+# CHECK: Vreg: %17[ 19 ]
+# CHECK: Vreg: %50[ LoopTag+27 ]
+# CHECK: Vreg: %114[ LoopTag+20 ]
+# CHECK: Instr: %184:vgpr_32 = V_MUL_LO_U32_e64 %183, %169, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+30 ]
+# CHECK: Vreg: %173[ LoopTag+20 ]
+# CHECK: Vreg: %116[ LoopTag+22 ]
+# CHECK: Vreg: %161[ LoopTag+19 ]
+# CHECK: Vreg: %21[ 22 ]
+# CHECK: Vreg: %111[ LoopTag+32 ]
+# CHECK: Vreg: %42[ 21 ]
+# CHECK: Vreg: %158[ 1 ]
+# CHECK: Vreg: %165[ 14 ]
+# CHECK: Vreg: %18[ 10 ]
+# CHECK: Vreg: %167[ 12 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %110[ LoopTag+26 ]
+# CHECK: Vreg: %162:sub0[ 31 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+27 ]
+# CHECK: Vreg: %183[ 0 ]
+# CHECK: Vreg: %17[ 18 ]
+# CHECK: Vreg: %50[ LoopTag+26 ]
+# CHECK: Vreg: %114[ LoopTag+19 ]
+# CHECK: Instr: %185:vgpr_32 = V_SUB_U32_e64 %158, killed %184, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+29 ]
+# CHECK: Vreg: %173[ LoopTag+19 ]
+# CHECK: Vreg: %116[ LoopTag+21 ]
+# CHECK: Vreg: %161[ LoopTag+18 ]
+# CHECK: Vreg: %21[ 21 ]
+# CHECK: Vreg: %111[ LoopTag+31 ]
+# CHECK: Vreg: %42[ 20 ]
+# CHECK: Vreg: %158[ 0 ]
+# CHECK: Vreg: %184[ 0 ]
+# CHECK: Vreg: %165[ 13 ]
+# CHECK: Vreg: %18[ 9 ]
+# CHECK: Vreg: %167[ 11 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %110[ LoopTag+25 ]
+# CHECK: Vreg: %162:sub0[ 30 ]
+# CHECK: Vreg: %169[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+26 ]
+# CHECK: Vreg: %183[ 2 ]
+# CHECK: Vreg: %17[ 17 ]
+# CHECK: Vreg: %50[ LoopTag+25 ]
+# CHECK: Vreg: %114[ LoopTag+18 ]
+# CHECK: Instr: %186:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %169, %185, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+28 ]
+# CHECK: Vreg: %173[ LoopTag+18 ]
+# CHECK: Vreg: %116[ LoopTag+20 ]
+# CHECK: Vreg: %161[ LoopTag+17 ]
+# CHECK: Vreg: %21[ 20 ]
+# CHECK: Vreg: %111[ LoopTag+30 ]
+# CHECK: Vreg: %42[ 19 ]
+# CHECK: Vreg: %158[ 31 ]
+# CHECK: Vreg: %165[ 12 ]
+# CHECK: Vreg: %18[ 8 ]
+# CHECK: Vreg: %167[ 10 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %110[ LoopTag+24 ]
+# CHECK: Vreg: %162:sub0[ 29 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+25 ]
+# CHECK: Vreg: %183[ 1 ]
+# CHECK: Vreg: %17[ 16 ]
+# CHECK: Vreg: %50[ LoopTag+24 ]
+# CHECK: Vreg: %114[ LoopTag+17 ]
+# CHECK: Vreg: %185[ 0 ]
+# CHECK: Instr: %187:vgpr_32 = V_ADD_U32_e64 1, %183, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+27 ]
+# CHECK: Vreg: %173[ LoopTag+17 ]
+# CHECK: Vreg: %116[ LoopTag+19 ]
+# CHECK: Vreg: %161[ LoopTag+16 ]
+# CHECK: Vreg: %21[ 19 ]
+# CHECK: Vreg: %111[ LoopTag+29 ]
+# CHECK: Vreg: %42[ 18 ]
+# CHECK: Vreg: %158[ 30 ]
+# CHECK: Vreg: %165[ 11 ]
+# CHECK: Vreg: %18[ 7 ]
+# CHECK: Vreg: %186[ 1 ]
+# CHECK: Vreg: %167[ 9 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %110[ LoopTag+23 ]
+# CHECK: Vreg: %162:sub0[ 28 ]
+# CHECK: Vreg: %169[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+24 ]
+# CHECK: Vreg: %183[ 0 ]
+# CHECK: Vreg: %17[ 15 ]
+# CHECK: Vreg: %50[ LoopTag+23 ]
+# CHECK: Vreg: %114[ LoopTag+16 ]
+# CHECK: Vreg: %185[ 2 ]
+# CHECK: Instr: %188:vgpr_32 = V_CNDMASK_B32_e64 0, killed %183, 0, killed %187, %186, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+26 ]
+# CHECK: Vreg: %173[ LoopTag+16 ]
+# CHECK: Vreg: %116[ LoopTag+18 ]
+# CHECK: Vreg: %161[ LoopTag+15 ]
+# CHECK: Vreg: %187[ 0 ]
+# CHECK: Vreg: %21[ 18 ]
+# CHECK: Vreg: %111[ LoopTag+28 ]
+# CHECK: Vreg: %42[ 17 ]
+# CHECK: Vreg: %158[ 29 ]
+# CHECK: Vreg: %165[ 10 ]
+# CHECK: Vreg: %18[ 6 ]
+# CHECK: Vreg: %186[ 0 ]
+# CHECK: Vreg: %167[ 8 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %110[ LoopTag+22 ]
+# CHECK: Vreg: %162:sub0[ 27 ]
+# CHECK: Vreg: %169[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+23 ]
+# CHECK: Vreg: %183[ 0 ]
+# CHECK: Vreg: %17[ 14 ]
+# CHECK: Vreg: %50[ LoopTag+22 ]
+# CHECK: Vreg: %114[ LoopTag+15 ]
+# CHECK: Vreg: %185[ 1 ]
+# CHECK: Instr: %189:vgpr_32 = V_SUBREV_U32_e64 %169, %185, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %173[ LoopTag+15 ]
+# CHECK: Vreg: %116[ LoopTag+17 ]
+# CHECK: Vreg: %161[ LoopTag+14 ]
+# CHECK: Vreg: %21[ 17 ]
+# CHECK: Vreg: %111[ LoopTag+27 ]
+# CHECK: Vreg: %42[ 16 ]
+# CHECK: Vreg: %158[ 28 ]
+# CHECK: Vreg: %165[ 9 ]
+# CHECK: Vreg: %18[ 5 ]
+# CHECK: Vreg: %186[ 1 ]
+# CHECK: Vreg: %167[ 7 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %110[ LoopTag+21 ]
+# CHECK: Vreg: %162:sub0[ 26 ]
+# CHECK: Vreg: %188[ 3 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+22 ]
+# CHECK: Vreg: %17[ 13 ]
+# CHECK: Vreg: %50[ LoopTag+21 ]
+# CHECK: Vreg: %114[ LoopTag+14 ]
+# CHECK: Vreg: %185[ 0 ]
+# CHECK: Instr: %190:vgpr_32 = V_CNDMASK_B32_e64 0, killed %185, 0, killed %189, killed %186, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %173[ LoopTag+14 ]
+# CHECK: Vreg: %116[ LoopTag+16 ]
+# CHECK: Vreg: %161[ LoopTag+13 ]
+# CHECK: Vreg: %21[ 16 ]
+# CHECK: Vreg: %111[ LoopTag+26 ]
+# CHECK: Vreg: %189[ 0 ]
+# CHECK: Vreg: %42[ 15 ]
+# CHECK: Vreg: %158[ 27 ]
+# CHECK: Vreg: %165[ 8 ]
+# CHECK: Vreg: %18[ 4 ]
+# CHECK: Vreg: %186[ 0 ]
+# CHECK: Vreg: %167[ 6 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %110[ LoopTag+20 ]
+# CHECK: Vreg: %162:sub0[ 25 ]
+# CHECK: Vreg: %188[ 2 ]
+# CHECK: Vreg: %169[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+21 ]
+# CHECK: Vreg: %17[ 12 ]
+# CHECK: Vreg: %50[ LoopTag+20 ]
+# CHECK: Vreg: %114[ LoopTag+13 ]
+# CHECK: Vreg: %185[ 0 ]
+# CHECK: Instr: %191:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %169, killed %190, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+23 ]
+# CHECK: Vreg: %173[ LoopTag+13 ]
+# CHECK: Vreg: %116[ LoopTag+15 ]
+# CHECK: Vreg: %161[ LoopTag+12 ]
+# CHECK: Vreg: %21[ 15 ]
+# CHECK: Vreg: %111[ LoopTag+25 ]
+# CHECK: Vreg: %42[ 14 ]
+# CHECK: Vreg: %158[ 26 ]
+# CHECK: Vreg: %165[ 7 ]
+# CHECK: Vreg: %18[ 3 ]
+# CHECK: Vreg: %167[ 5 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %110[ LoopTag+19 ]
+# CHECK: Vreg: %162:sub0[ 24 ]
+# CHECK: Vreg: %188[ 1 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+20 ]
+# CHECK: Vreg: %17[ 11 ]
+# CHECK: Vreg: %190[ 0 ]
+# CHECK: Vreg: %50[ LoopTag+19 ]
+# CHECK: Vreg: %114[ LoopTag+12 ]
+# CHECK: Instr: %192:vgpr_32 = V_ADD_U32_e64 1, %188, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+22 ]
+# CHECK: Vreg: %173[ LoopTag+12 ]
+# CHECK: Vreg: %116[ LoopTag+14 ]
+# CHECK: Vreg: %161[ LoopTag+11 ]
+# CHECK: Vreg: %21[ 14 ]
+# CHECK: Vreg: %111[ LoopTag+24 ]
+# CHECK: Vreg: %42[ 13 ]
+# CHECK: Vreg: %158[ 25 ]
+# CHECK: Vreg: %165[ 6 ]
+# CHECK: Vreg: %18[ 2 ]
+# CHECK: Vreg: %191[ 1 ]
+# CHECK: Vreg: %167[ 4 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %110[ LoopTag+18 ]
+# CHECK: Vreg: %162:sub0[ 23 ]
+# CHECK: Vreg: %188[ 0 ]
+# CHECK: Vreg: %169[ 3 ]
+# CHECK: Vreg: %29[ LoopTag+19 ]
+# CHECK: Vreg: %17[ 10 ]
+# CHECK: Vreg: %50[ LoopTag+18 ]
+# CHECK: Vreg: %114[ LoopTag+11 ]
+# CHECK: Instr: %193:vgpr_32 = V_CNDMASK_B32_e64 0, killed %188, 0, killed %192, killed %191, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %173[ LoopTag+11 ]
+# CHECK: Vreg: %192[ 0 ]
+# CHECK: Vreg: %116[ LoopTag+13 ]
+# CHECK: Vreg: %161[ LoopTag+10 ]
+# CHECK: Vreg: %21[ 13 ]
+# CHECK: Vreg: %111[ LoopTag+23 ]
+# CHECK: Vreg: %42[ 12 ]
+# CHECK: Vreg: %158[ 24 ]
+# CHECK: Vreg: %165[ 5 ]
+# CHECK: Vreg: %18[ 1 ]
+# CHECK: Vreg: %191[ 0 ]
+# CHECK: Vreg: %167[ 3 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %110[ LoopTag+17 ]
+# CHECK: Vreg: %162:sub0[ 22 ]
+# CHECK: Vreg: %188[ 0 ]
+# CHECK: Vreg: %169[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+18 ]
+# CHECK: Vreg: %17[ 9 ]
+# CHECK: Vreg: %50[ LoopTag+17 ]
+# CHECK: Vreg: %114[ LoopTag+10 ]
+# CHECK: Instr: GLOBAL_STORE_DWORD %18, killed %193, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+20 ]
+# CHECK: Vreg: %173[ LoopTag+10 ]
+# CHECK: Vreg: %116[ LoopTag+12 ]
+# CHECK: Vreg: %161[ LoopTag+9 ]
+# CHECK: Vreg: %21[ 12 ]
+# CHECK: Vreg: %111[ LoopTag+22 ]
+# CHECK: Vreg: %42[ 11 ]
+# CHECK: Vreg: %158[ 23 ]
+# CHECK: Vreg: %165[ 4 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %167[ 2 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %110[ LoopTag+16 ]
+# CHECK: Vreg: %193[ 0 ]
+# CHECK: Vreg: %162:sub0[ 21 ]
+# CHECK: Vreg: %169[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+17 ]
+# CHECK: Vreg: %17[ 8 ]
+# CHECK: Vreg: %50[ LoopTag+16 ]
+# CHECK: Vreg: %114[ LoopTag+9 ]
+# CHECK: Instr: %170:sreg_32 = S_ADD_I32 %169, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %173[ LoopTag+9 ]
+# CHECK: Vreg: %116[ LoopTag+11 ]
+# CHECK: Vreg: %161[ LoopTag+8 ]
+# CHECK: Vreg: %21[ 11 ]
+# CHECK: Vreg: %111[ LoopTag+21 ]
+# CHECK: Vreg: %42[ 10 ]
+# CHECK: Vreg: %158[ 22 ]
+# CHECK: Vreg: %165[ 3 ]
+# CHECK: Vreg: %18[ 31 ]
+# CHECK: Vreg: %167[ 1 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %110[ LoopTag+15 ]
+# CHECK: Vreg: %162:sub0[ 20 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+16 ]
+# CHECK: Vreg: %17[ 7 ]
+# CHECK: Vreg: %50[ LoopTag+15 ]
+# CHECK: Vreg: %114[ LoopTag+8 ]
+# CHECK: Instr: %168:sreg_32 = S_ADD_I32 killed %167, -1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+18 ]
+# CHECK: Vreg: %173[ LoopTag+8 ]
+# CHECK: Vreg: %116[ LoopTag+10 ]
+# CHECK: Vreg: %161[ LoopTag+7 ]
+# CHECK: Vreg: %21[ 10 ]
+# CHECK: Vreg: %111[ LoopTag+20 ]
+# CHECK: Vreg: %42[ 9 ]
+# CHECK: Vreg: %170[ 1 ]
+# CHECK: Vreg: %158[ 21 ]
+# CHECK: Vreg: %165[ 2 ]
+# CHECK: Vreg: %18[ 30 ]
+# CHECK: Vreg: %167[ 0 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %110[ LoopTag+14 ]
+# CHECK: Vreg: %162:sub0[ 19 ]
+# CHECK: Vreg: %169[ 3 ]
+# CHECK: Vreg: %29[ LoopTag+15 ]
+# CHECK: Vreg: %17[ 6 ]
+# CHECK: Vreg: %50[ LoopTag+14 ]
+# CHECK: Vreg: %114[ LoopTag+7 ]
+# CHECK: Instr: %194:sreg_32 = V_CMP_GE_U32_e64 %170, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+17 ]
+# CHECK: Vreg: %173[ LoopTag+7 ]
+# CHECK: Vreg: %116[ LoopTag+9 ]
+# CHECK: Vreg: %161[ LoopTag+6 ]
+# CHECK: Vreg: %168[ 4 ]
+# CHECK: Vreg: %21[ 9 ]
+# CHECK: Vreg: %111[ LoopTag+19 ]
+# CHECK: Vreg: %42[ 8 ]
+# CHECK: Vreg: %170[ 0 ]
+# CHECK: Vreg: %158[ 20 ]
+# CHECK: Vreg: %165[ 1 ]
+# CHECK: Vreg: %18[ 29 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %110[ LoopTag+13 ]
+# CHECK: Vreg: %162:sub0[ 18 ]
+# CHECK: Vreg: %169[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+14 ]
+# CHECK: Vreg: %17[ 5 ]
+# CHECK: Vreg: %50[ LoopTag+13 ]
+# CHECK: Vreg: %114[ LoopTag+6 ]
+# CHECK: Instr: %166:sreg_32 = SI_IF_BREAK killed %194, killed %165, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+16 ]
+# CHECK: Vreg: %173[ LoopTag+6 ]
+# CHECK: Vreg: %116[ LoopTag+8 ]
+# CHECK: Vreg: %161[ LoopTag+5 ]
+# CHECK: Vreg: %168[ 3 ]
+# CHECK: Vreg: %21[ 8 ]
+# CHECK: Vreg: %194[ 0 ]
+# CHECK: Vreg: %111[ LoopTag+18 ]
+# CHECK: Vreg: %42[ 7 ]
+# CHECK: Vreg: %170[ 3 ]
+# CHECK: Vreg: %158[ 19 ]
+# CHECK: Vreg: %165[ 0 ]
+# CHECK: Vreg: %18[ 28 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %110[ LoopTag+12 ]
+# CHECK: Vreg: %162:sub0[ 17 ]
+# CHECK: Vreg: %169[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+13 ]
+# CHECK: Vreg: %17[ 4 ]
+# CHECK: Vreg: %50[ LoopTag+12 ]
+# CHECK: Vreg: %114[ LoopTag+5 ]
+# CHECK: Instr: %195:vgpr_32 = COPY killed %169, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %173[ LoopTag+5 ]
+# CHECK: Vreg: %116[ LoopTag+7 ]
+# CHECK: Vreg: %161[ LoopTag+4 ]
+# CHECK: Vreg: %168[ 2 ]
+# CHECK: Vreg: %21[ 7 ]
+# CHECK: Vreg: %111[ LoopTag+17 ]
+# CHECK: Vreg: %42[ 6 ]
+# CHECK: Vreg: %170[ 2 ]
+# CHECK: Vreg: %158[ 18 ]
+# CHECK: Vreg: %18[ 27 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %110[ LoopTag+11 ]
+# CHECK: Vreg: %162:sub0[ 16 ]
+# CHECK: Vreg: %169[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+12 ]
+# CHECK: Vreg: %17[ 3 ]
+# CHECK: Vreg: %50[ LoopTag+11 ]
+# CHECK: Vreg: %114[ LoopTag+4 ]
+# CHECK: Vreg: %166[ 1 ]
+# CHECK: Instr: SI_LOOP %166, %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+14 ]
+# CHECK: Vreg: %173[ LoopTag+4 ]
+# CHECK: Vreg: %116[ LoopTag+6 ]
+# CHECK: Vreg: %161[ LoopTag+3 ]
+# CHECK: Vreg: %168[ 1 ]
+# CHECK: Vreg: %21[ 6 ]
+# CHECK: Vreg: %111[ LoopTag+16 ]
+# CHECK: Vreg: %42[ 5 ]
+# CHECK: Vreg: %170[ 1 ]
+# CHECK: Vreg: %158[ 17 ]
+# CHECK: Vreg: %18[ 26 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %110[ LoopTag+10 ]
+# CHECK: Vreg: %162:sub0[ 15 ]
+# CHECK: Vreg: %195[ LoopTag+4 ]
+# CHECK: Vreg: %29[ LoopTag+11 ]
+# CHECK: Vreg: %17[ 2 ]
+# CHECK: Vreg: %50[ LoopTag+10 ]
+# CHECK: Vreg: %114[ LoopTag+3 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.12
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+13 ]
+# CHECK: Vreg: %173[ LoopTag+3 ]
+# CHECK: Vreg: %116[ LoopTag+5 ]
+# CHECK: Vreg: %161[ LoopTag+2 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %111[ LoopTag+15 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %170[ 0 ]
+# CHECK: Vreg: %158[ 16 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %110[ LoopTag+9 ]
+# CHECK: Vreg: %162:sub0[ 14 ]
+# CHECK: Vreg: %195[ LoopTag+3 ]
+# CHECK: Vreg: %29[ LoopTag+10 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+9 ]
+# CHECK: Vreg: %114[ LoopTag+2 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+13 ]
+# CHECK: Vreg: %173[ LoopTag+3 ]
+# CHECK: Vreg: %116[ LoopTag+5 ]
+# CHECK: Vreg: %161[ LoopTag+2 ]
+# CHECK: Vreg: %168[ 0 ]
+# CHECK: Vreg: %21[ 5 ]
+# CHECK: Vreg: %111[ LoopTag+15 ]
+# CHECK: Vreg: %42[ 4 ]
+# CHECK: Vreg: %170[ 0 ]
+# CHECK: Vreg: %158[ 16 ]
+# CHECK: Vreg: %18[ 25 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %110[ LoopTag+9 ]
+# CHECK: Vreg: %162:sub0[ 14 ]
+# CHECK: Vreg: %195[ LoopTag+3 ]
+# CHECK: Vreg: %29[ LoopTag+10 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %50[ LoopTag+9 ]
+# CHECK: Vreg: %114[ LoopTag+2 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: --- MBB_11 ---
+# CHECK: Instr: SI_END_CF killed %131, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %125[ 2 ]
+# CHECK: Vreg: %129[ 3 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %143[ 1 ]
+# CHECK: Vreg: %131[ 0 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Vreg: %147[ 1 ]
+# CHECK: Instr: %128:vgpr_32 = V_MUL_LO_U32_e64 killed %147, killed %143, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 8 ]
+# CHECK: Vreg: %125[ 1 ]
+# CHECK: Vreg: %129[ 2 ]
+# CHECK: Vreg: %110[ 4 ]
+# CHECK: Vreg: %143[ 0 ]
+# CHECK: Vreg: %29[ 5 ]
+# CHECK: Vreg: %50[ 4 ]
+# CHECK: Vreg: %147[ 0 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %128[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %110[ 3 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %50[ 3 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 7 ]
+# CHECK: Vreg: %128[ 0 ]
+# CHECK: Vreg: %125[ 0 ]
+# CHECK: Vreg: %129[ 1 ]
+# CHECK: Vreg: %110[ 3 ]
+# CHECK: Vreg: %29[ 4 ]
+# CHECK: Vreg: %50[ 3 ]
+# CHECK: --- MBB_12 ---
+# CHECK: Instr: SI_END_CF killed %166, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 12 ]
+# CHECK: Vreg: %173[ 2 ]
+# CHECK: Vreg: %116[ 4 ]
+# CHECK: Vreg: %161[ 1 ]
+# CHECK: Vreg: %111[ 14 ]
+# CHECK: Vreg: %110[ 8 ]
+# CHECK: Vreg: %195[ 2 ]
+# CHECK: Vreg: %29[ 9 ]
+# CHECK: Vreg: %50[ 8 ]
+# CHECK: Vreg: %114[ 1 ]
+# CHECK: Vreg: %166[ 0 ]
+# CHECK: Instr: %146:vgpr_32 = V_MUL_LO_U32_e64 killed %114, killed %161, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 11 ]
+# CHECK: Vreg: %173[ 1 ]
+# CHECK: Vreg: %116[ 3 ]
+# CHECK: Vreg: %161[ 0 ]
+# CHECK: Vreg: %111[ 13 ]
+# CHECK: Vreg: %110[ 7 ]
+# CHECK: Vreg: %195[ 1 ]
+# CHECK: Vreg: %29[ 8 ]
+# CHECK: Vreg: %50[ 7 ]
+# CHECK: Vreg: %114[ 0 ]
+# CHECK: Instr: %145:vgpr_32 = V_MUL_LO_U32_e64 killed %173, killed %195, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 10 ]
+# CHECK: Vreg: %173[ 0 ]
+# CHECK: Vreg: %116[ 2 ]
+# CHECK: Vreg: %111[ 12 ]
+# CHECK: Vreg: %146[ 1 ]
+# CHECK: Vreg: %110[ 6 ]
+# CHECK: Vreg: %195[ 0 ]
+# CHECK: Vreg: %29[ 7 ]
+# CHECK: Vreg: %50[ 6 ]
+# CHECK: Instr: S_BRANCH %bb.7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 9 ]
+# CHECK: Vreg: %116[ 1 ]
+# CHECK: Vreg: %111[ 11 ]
+# CHECK: Vreg: %146[ 0 ]
+# CHECK: Vreg: %110[ 5 ]
+# CHECK: Vreg: %29[ 6 ]
+# CHECK: Vreg: %145[ 0 ]
+# CHECK: Vreg: %50[ 5 ]
+# CHECK: --- MBB_13 ---
+# CHECK: Instr: %196:vgpr_32 = V_MUL_LO_U32_e64 killed %50, killed %110, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %123[ 3 ]
+# CHECK: Vreg: %110[ 0 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %126[ 1 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Instr: %197:vgpr_32 = V_ADD_U32_e64 killed %29, killed %126, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %123[ 2 ]
+# CHECK: Vreg: %196[ 1 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %126[ 0 ]
+# CHECK: Instr: %198:vgpr_32 = V_SUB_U32_e64 killed %196, killed %197, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %123[ 1 ]
+# CHECK: Vreg: %196[ 0 ]
+# CHECK: Vreg: %197[ 0 ]
+# CHECK: Instr: %199:vgpr_32 = V_ADD_U32_e64 killed %198, killed %123, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %123[ 0 ]
+# CHECK: Vreg: %198[ 0 ]
+# CHECK: Instr: %200:vgpr_32 = V_ADD3_U32_e64 killed %199, killed %0, -100, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %199[ 0 ]
+# CHECK: Instr: %201:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %200, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %200[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %201
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %201[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test16(ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, ptr addrspace(1) %p4, ptr addrspace(1) %p5, ptr addrspace(1) %p6, i32 %TC1, i32 %TC2, i32 %TC3, i32 %TC4, i32 %Val) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  %add1 = add i32 %ld1, 100
+  br label %1
+  1:
+  %phi.inc1 = phi i32 [ 1, %0 ], [ %inc1, %1 ]
+  %phi.div = phi i32 [ %ld1, %0 ], [ %div2, %1 ]
+  %ld2 = load i32, ptr addrspace(1) %p2, align 1
+  %mul1 = mul i32 %ld2, %phi.inc1
+  %div1 = udiv i32 %ld2, %phi.inc1
+  store i32 %div1, ptr addrspace(1) %p1, align 4
+  %inc1 = add i32 %phi.inc1, 1
+  %add2 = add i32 %ld1, %phi.inc1
+  store i32 %add2, ptr addrspace(1) %p6, align 1
+  %sext = sext i32 %phi.inc1 to i64
+  %gep = getelementptr inbounds i32, ptr addrspace(1) %p5, i64 %sext
+  %ld3 = load i32, ptr addrspace(1) %gep, align 1
+  %div2 = udiv i32 %add2, %ld3
+  %cond1 = icmp ult i32 %inc1, %TC1
+  br i1 %cond1, label %1, label %2
+  2:
+  %ld4 = load i32, ptr addrspace(1) %p3, align 2
+  %cond2 = icmp uge i32 %ld4, %ld1
+  br i1 %cond2, label %3, label %4
+  3:
+  %phi.inc2 = phi i32 [ 0, %2 ], [ %inc2, %3 ]
+  %ld5 = load i32, ptr addrspace(1) %p4, align 2
+  %mul2 = mul i32 %ld4, %phi.inc2
+  %mul3 = mul i32 %ld5, %phi.inc2
+  %sub1 = sub i32 %mul3, %inc1
+  store i32 %sub1, ptr addrspace(1) %p2, align 4
+  %inc2 = add i32 %phi.inc2, 1
+  %cond3 = icmp ult i32 %inc2, %TC2
+  br i1 %cond3, label %3, label %6
+  4:
+  %phi.inc3 = phi i32 [ 10, %2 ], [ %inc3, %4 ]
+  %phi.sub = phi i32 [ %add2, %2 ], [ %sub2, %4 ]
+  %mul4 = mul i32 %ld4, %phi.inc3
+  %sub2 = sub i32 %ld4, %phi.inc3
+  store i32 %sub2, ptr addrspace(1) %p4, align 4
+  %inc3 = add i32 %phi.inc3, 1
+  %cond4 = icmp ult i32 %inc3, %TC3
+  br i1 %cond4, label %4, label %5
+  5:
+  %phi.inc4 = phi i32 [ 0, %4 ], [ %inc4, %5 ]
+  %ld6 = load i32, ptr addrspace(1) %p6, align 2
+  %mul5 = mul i32 %ld6, %phi.inc4
+  %add3 = add i32 %phi.div, %phi.inc4
+  store i32 %add3, ptr addrspace(1) %p2, align 4
+  %div3 = udiv i32 %phi.sub, %phi.inc4
+  store i32 %div3, ptr addrspace(1) %p5, align 4
+  %inc4 = add i32 %phi.inc4, 1
+  %cond5 = icmp ult i32 %inc4, %TC4
+  br i1 %cond5, label %5, label %6
+  6:
+  %phi1 = phi i32 [ %mul2, %3 ], [ %mul4, %5 ]
+  %phi2 = phi i32 [ %mul3, %3 ], [ %mul5, %5 ]
+  %add4 = add i32 %phi1, %add1
+  %sub3 = sub i32 %mul1, %add4
+  %add5 = add i32 %phi2, %sub3
+  %add6 = add i32 %add5, %Val
+  ret i32 %add6
+  }
+...
+
+---
+name:            test16
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14, $vgpr15, $vgpr16
+  
+    %76:vgpr_32 = COPY killed $vgpr16
+    %75:vgpr_32 = COPY killed $vgpr15
+    %74:vgpr_32 = COPY killed $vgpr14
+    %73:vgpr_32 = COPY killed $vgpr13
+    %72:vgpr_32 = COPY killed $vgpr12
+    %71:vgpr_32 = COPY killed $vgpr11
+    %70:vgpr_32 = COPY killed $vgpr10
+    %69:vgpr_32 = COPY killed $vgpr9
+    %68:vgpr_32 = COPY killed $vgpr8
+    %67:vgpr_32 = COPY killed $vgpr7
+    %66:vgpr_32 = COPY killed $vgpr6
+    %65:vgpr_32 = COPY killed $vgpr5
+    %64:vgpr_32 = COPY killed $vgpr4
+    %63:vgpr_32 = COPY killed $vgpr3
+    %62:vgpr_32 = COPY killed $vgpr2
+    %61:vgpr_32 = COPY killed $vgpr1
+    %60:vgpr_32 = COPY killed $vgpr0
+    %243:vreg_64 = REG_SEQUENCE killed %70, %subreg.sub0, killed %71, %subreg.sub1
+    %242:vreg_64 = REG_SEQUENCE killed %68, %subreg.sub0, killed %69, %subreg.sub1
+    %241:vreg_64 = REG_SEQUENCE killed %66, %subreg.sub0, killed %67, %subreg.sub1
+    %240:vreg_64 = REG_SEQUENCE killed %64, %subreg.sub0, killed %65, %subreg.sub1
+    %239:vreg_64 = REG_SEQUENCE killed %62, %subreg.sub0, killed %63, %subreg.sub1
+    %238:vreg_64 = REG_SEQUENCE killed %60, %subreg.sub0, killed %61, %subreg.sub1
+    %92:vgpr_32 = GLOBAL_LOAD_UBYTE %238, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %94:vgpr_32 = GLOBAL_LOAD_UBYTE %238, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %97:vgpr_32 = V_LSHL_OR_B32_e64 killed %94, 8, killed %92, implicit $exec
+    %98:vgpr_32 = GLOBAL_LOAD_UBYTE %238, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %100:vgpr_32 = GLOBAL_LOAD_UBYTE %238, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %102:vgpr_32 = V_LSHL_OR_B32_e64 killed %100, 8, killed %98, implicit $exec
+    %0:vgpr_32 = V_LSHL_OR_B32_e64 killed %102, 16, killed %97, implicit $exec
+    %85:sreg_32 = S_MOV_B32 1
+    %1:vgpr_32 = V_ADD_U32_e64 1, %0, 0, implicit $exec
+    %84:sreg_32 = S_MOV_B32 -1
+    %83:sreg_32 = S_MOV_B32 0
+  
+  bb.1:
+    successors: %bb.2(0x04000000), %bb.1(0x7c000000)
+  
+    %2:sreg_32 = PHI %83, %bb.0, %12, %bb.1
+    %3:vgpr_32 = PHI %1, %bb.0, %11, %bb.1
+    %4:sreg_32 = PHI %84, %bb.0, %10, %bb.1
+    %5:sreg_32 = PHI %85, %bb.0, %8, %bb.1
+    %6:vgpr_32 = PHI %0, %bb.0, %9, %bb.1
+    %104:vgpr_32 = GLOBAL_LOAD_UBYTE %239, 0, 0, implicit $exec :: (load (s8) from %ir.p2, addrspace 1)
+    %105:vgpr_32 = GLOBAL_LOAD_UBYTE %239, 1, 0, implicit $exec :: (load (s8) from %ir.p2 + 1, addrspace 1)
+    %107:vgpr_32 = V_LSHL_OR_B32_e64 killed %105, 8, killed %104, implicit $exec
+    %108:vgpr_32 = GLOBAL_LOAD_UBYTE %239, 2, 0, implicit $exec :: (load (s8) from %ir.p2 + 2, addrspace 1)
+    %109:vgpr_32 = GLOBAL_LOAD_UBYTE %239, 3, 0, implicit $exec :: (load (s8) from %ir.p2 + 3, addrspace 1)
+    %110:vgpr_32 = V_LSHL_OR_B32_e64 killed %109, 8, killed %108, implicit $exec
+    %7:vgpr_32 = V_LSHL_OR_B32_e64 killed %110, 16, killed %107, implicit $exec
+    %112:sgpr_32 = S_CVT_F32_U32 %5, implicit $mode
+    %113:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %112, 0, 0, implicit $mode, implicit $exec
+    %116:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %113, implicit $exec
+    %115:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %116, 1333788670, implicit $mode
+    %117:sreg_32 = nofpexcept S_CVT_U32_F32 killed %115, implicit $mode
+    %118:sreg_32 = S_MUL_I32 %4, %117
+    %119:sreg_32 = S_MUL_HI_U32 %117, killed %118
+    %120:sreg_32 = S_ADD_I32 killed %117, killed %119, implicit-def dead $scc
+    %121:vgpr_32 = V_MUL_HI_U32_e64 %7, killed %120, implicit $exec
+    %122:vgpr_32 = V_MUL_LO_U32_e64 %121, %5, implicit $exec
+    %123:vgpr_32 = V_SUB_U32_e64 %7, killed %122, 0, implicit $exec
+    %124:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %5, %123, implicit $exec
+    %126:vgpr_32 = V_ADD_U32_e64 1, %121, 0, implicit $exec
+    %127:vgpr_32 = V_CNDMASK_B32_e64 0, killed %121, 0, killed %126, %124, implicit $exec
+    %128:vgpr_32 = V_SUBREV_U32_e64 %5, %123, 0, implicit $exec
+    %129:vgpr_32 = V_CNDMASK_B32_e64 0, killed %123, 0, killed %128, killed %124, implicit $exec
+    %130:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %5, killed %129, implicit $exec
+    %131:vgpr_32 = V_ADD_U32_e64 1, %127, 0, implicit $exec
+    %132:vgpr_32 = V_CNDMASK_B32_e64 0, killed %127, 0, killed %131, killed %130, implicit $exec
+    GLOBAL_STORE_DWORD %238, killed %132, 0, 0, implicit $exec :: (store (s32) into %ir.p1, addrspace 1)
+    %8:sreg_32 = S_ADD_I32 %5, 1, implicit-def dead $scc
+    %133:vgpr_32 = V_ADD_U32_e64 %5, %0, 0, implicit $exec
+    %135:vgpr_32 = V_LSHRREV_B32_e64 24, %133, implicit $exec
+    GLOBAL_STORE_BYTE %243, killed %135, 3, 0, implicit $exec :: (store (s8) into %ir.p6 + 3, addrspace 1)
+    GLOBAL_STORE_BYTE_D16_HI %243, %133, 2, 0, implicit $exec :: (store (s8) into %ir.p6 + 2, addrspace 1)
+    %136:vgpr_32 = V_LSHRREV_B32_e64 8, %133, implicit $exec
+    GLOBAL_STORE_BYTE %243, killed %136, 1, 0, implicit $exec :: (store (s8) into %ir.p6 + 1, addrspace 1)
+    GLOBAL_STORE_BYTE %243, %133, 0, 0, implicit $exec :: (store (s8) into %ir.p6, addrspace 1)
+    %137:sreg_32_xm0 = S_ASHR_I32 %5, 31, implicit-def dead $scc
+    %139:sreg_64 = REG_SEQUENCE %5, %subreg.sub0, killed %137, %subreg.sub1
+    %141:sreg_64 = nsw S_LSHL_B64 killed %139, 2, implicit-def dead $scc
+    %249:vgpr_32, %251:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %242.sub0, %141.sub0, 0, implicit $exec
+    %250:vgpr_32, dead $sgpr_null = V_ADDC_U32_e64 killed %141.sub1, %242.sub1, killed %251, 0, implicit $exec
+    %142:vreg_64 = REG_SEQUENCE killed %249, %subreg.sub0, killed %250, %subreg.sub1
+    %143:vgpr_32 = GLOBAL_LOAD_UBYTE %142, 0, 0, implicit $exec :: (load (s8) from %ir.gep, addrspace 1)
+    %144:vgpr_32 = GLOBAL_LOAD_UBYTE %142, 1, 0, implicit $exec :: (load (s8) from %ir.gep + 1, addrspace 1)
+    %145:vgpr_32 = V_LSHL_OR_B32_e64 killed %144, 8, killed %143, implicit $exec
+    %146:vgpr_32 = GLOBAL_LOAD_UBYTE %142, 2, 0, implicit $exec :: (load (s8) from %ir.gep + 2, addrspace 1)
+    %147:vgpr_32 = GLOBAL_LOAD_UBYTE killed %142, 3, 0, implicit $exec :: (load (s8) from %ir.gep + 3, addrspace 1)
+    %148:vgpr_32 = V_LSHL_OR_B32_e64 killed %147, 8, killed %146, implicit $exec
+    %149:vgpr_32 = V_LSHL_OR_B32_e64 killed %148, 16, killed %145, implicit $exec
+    %150:vgpr_32 = V_CVT_F32_U32_e64 %149, 0, 0, implicit $mode, implicit $exec
+    %151:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %150, 0, 0, implicit $mode, implicit $exec
+    %152:vgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept V_MUL_F32_e64 0, 1333788670, 0, killed %151, 0, 0, implicit $mode, implicit $exec
+    %153:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, killed %152, 0, 0, implicit $mode, implicit $exec
+    %155:vgpr_32 = V_SUB_U32_e64 0, %149, 0, implicit $exec
+    %156:vgpr_32 = V_MUL_LO_U32_e64 killed %155, %153, implicit $exec
+    %157:vgpr_32 = V_MUL_HI_U32_e64 %153, killed %156, implicit $exec
+    %158:vgpr_32 = V_ADD_U32_e64 killed %153, killed %157, 0, implicit $exec
+    %159:vgpr_32 = V_MUL_HI_U32_e64 %133, %158, implicit $exec
+    %160:vgpr_32 = V_MUL_HI_U32_e64 %3, killed %158, implicit $exec
+    %161:vgpr_32 = V_MUL_LO_U32_e64 %149, %160, implicit $exec
+    %162:vgpr_32 = V_SUB_U32_e64 %133, killed %161, 0, implicit $exec
+    %163:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 %162, %149, implicit $exec
+    %164:vgpr_32 = V_ADD_U32_e64 1, %159, 0, implicit $exec
+    %165:vgpr_32 = V_CNDMASK_B32_e64 0, killed %159, 0, killed %164, %163, implicit $exec
+    %166:vgpr_32 = V_NOT_B32_e32 killed %160, implicit $exec
+    %236:vreg_64 = REG_SEQUENCE killed %133, %subreg.sub0, undef %237:vgpr_32, %subreg.sub1
+    %170:vreg_64, $sgpr_null = V_MAD_U64_U32_e64 %149, killed %166, killed %236, 0, implicit $exec
+    %173:vgpr_32 = V_CNDMASK_B32_e64 0, killed %162, 0, killed %170.sub0, killed %163, implicit $exec
+    %174:sreg_32_xm0_xexec = V_CMP_GE_U32_e64 killed %173, killed %149, implicit $exec
+    %175:vgpr_32 = V_ADD_U32_e64 1, %165, 0, implicit $exec
+    %9:vgpr_32 = V_CNDMASK_B32_e64 0, killed %165, 0, killed %175, killed %174, implicit $exec
+    %10:sreg_32 = S_ADD_I32 killed %4, -1, implicit-def dead $scc
+    %11:vgpr_32 = V_ADD_U32_e64 1, killed %3, 0, implicit $exec
+    %177:sreg_32 = V_CMP_GE_U32_e64 %8, %72, implicit $exec
+    %12:sreg_32 = SI_IF_BREAK killed %177, killed %2, implicit-def dead $scc
+    %244:vgpr_32 = COPY killed %5, implicit $exec
+    %245:vgpr_32 = COPY %8, implicit $exec
+    SI_LOOP %12, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.2
+  
+  bb.2:
+    successors: %bb.3(0x40000000), %bb.7(0x40000000)
+  
+    SI_END_CF killed %12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %179:vgpr_32 = GLOBAL_LOAD_USHORT %240, 0, 0, implicit $exec :: (load (s16) from %ir.p3, addrspace 1)
+    %180:vgpr_32 = GLOBAL_LOAD_USHORT killed %240, 2, 0, implicit $exec :: (load (s16) from %ir.p3 + 2, addrspace 1)
+    %18:vgpr_32 = V_LSHL_OR_B32_e64 killed %180, 16, killed %179, implicit $exec
+    %182:sreg_32 = V_CMP_LT_U32_e64 %18, %0, implicit $exec
+    %19:sreg_32 = SI_IF killed %182, %bb.7, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.3
+  
+  bb.3:
+    successors: %bb.8(0x80000000)
+  
+    %20:vgpr_32 = V_ADD3_U32_e64 %0, %245, -1, implicit $exec
+    %21:vgpr_32 = V_ADD_U32_e64 -10, %18, 0, implicit $exec
+    %184:sreg_32 = S_MOV_B32 9
+    %183:sreg_32 = S_MOV_B32 0
+    S_BRANCH %bb.8
+  
+  bb.4:
+    successors: %bb.6(0x80000000)
+  
+    %221:sreg_32 = S_MOV_B32 -1
+    %220:sreg_32 = S_MOV_B32 0
+    S_BRANCH %bb.6
+  
+  bb.5:
+    successors: %bb.13(0x80000000)
+  
+    %22:vgpr_32 = PHI %29, %bb.7, %27, %bb.11
+    %23:vgpr_32 = PHI %30, %bb.7, %54, %bb.11
+    SI_END_CF killed %31, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.13
+  
+  bb.6:
+    successors: %bb.11(0x04000000), %bb.6(0x7c000000)
+  
+    %24:sreg_32 = PHI %220, %bb.4, %28, %bb.6
+    %25:sreg_32 = PHI %221, %bb.4, %26, %bb.6
+    %26:sreg_32 = S_ADD_I32 %25, 1, implicit-def dead $scc
+    %222:vgpr_32 = GLOBAL_LOAD_USHORT %254, 0, 0, implicit $exec :: (load (s16) from %ir.p4, addrspace 1)
+    %223:vgpr_32 = GLOBAL_LOAD_USHORT %254, 2, 0, implicit $exec :: (load (s16) from %ir.p4 + 2, addrspace 1)
+    %224:vgpr_32 = V_LSHL_OR_B32_e64 killed %223, 16, killed %222, implicit $exec
+    %27:vgpr_32 = V_MUL_LO_U32_e64 killed %224, %26, implicit $exec
+    %225:vgpr_32 = V_SUB_U32_e64 %27, %245, 0, implicit $exec
+    GLOBAL_STORE_DWORD %256, killed %225, 0, 0, implicit $exec :: (store (s32) into %ir.p2, addrspace 1)
+    %226:sreg_32 = S_ADD_I32 killed %25, 2, implicit-def dead $scc
+    %227:sreg_32 = V_CMP_GE_U32_e64 killed %226, %258, implicit $exec
+    %28:sreg_32 = SI_IF_BREAK killed %227, killed %24, implicit-def dead $scc
+    %247:vgpr_32 = COPY %26, implicit $exec
+    SI_LOOP %28, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.11
+  
+  bb.7:
+    successors: %bb.4(0x40000000), %bb.5(0x40000000)
+  
+    %29:vgpr_32 = PHI undef %178:vgpr_32, %bb.2, %59, %bb.12
+    %30:vgpr_32 = PHI undef %178:vgpr_32, %bb.2, %58, %bb.12
+    %252:vgpr_32 = PHI %18, %bb.2, undef %253:vgpr_32, %bb.12
+    %254:vreg_64 = PHI %241, %bb.2, undef %255:vreg_64, %bb.12
+    %256:vreg_64 = PHI %239, %bb.2, undef %257:vreg_64, %bb.12
+    %258:vgpr_32 = PHI %73, %bb.2, undef %259:vgpr_32, %bb.12
+    %31:sreg_32 = SI_ELSE killed %19, %bb.5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.4
+  
+  bb.8:
+    successors: %bb.9(0x04000000), %bb.8(0x7c000000)
+  
+    %32:sreg_32 = PHI %183, %bb.3, %38, %bb.8
+    %33:vgpr_32 = PHI %21, %bb.3, %37, %bb.8
+    %34:sreg_32 = PHI %184, %bb.3, %36, %bb.8
+    %35:vgpr_32 = PHI %20, %bb.3, %33, %bb.8
+    %36:sreg_32 = nuw S_ADD_I32 %34, 1, implicit-def dead $scc
+    %189:sreg_32 = S_ADD_I32 killed %34, 2, implicit-def dead $scc
+    %37:vgpr_32 = V_ADD_U32_e64 -1, %33, 0, implicit $exec
+    %191:sreg_32 = V_CMP_GE_U32_e64 killed %189, %74, implicit $exec
+    %38:sreg_32 = SI_IF_BREAK killed %191, killed %32, implicit-def dead $scc
+    %246:vgpr_32 = COPY %36, implicit $exec
+    SI_LOOP %38, %bb.8, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.9
+  
+  bb.9:
+    successors: %bb.10(0x80000000)
+  
+    SI_END_CF killed %38, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    GLOBAL_STORE_DWORD killed %241, killed %33, 0, 0, implicit $exec :: (store (s32) into %ir.p4, addrspace 1)
+    %234:vreg_64 = REG_SEQUENCE %35, %subreg.sub0, undef %235:vgpr_32, %subreg.sub1
+    %192:sreg_32 = S_MOV_B32 0
+  
+  bb.10:
+    successors: %bb.12(0x04000000), %bb.10(0x7c000000)
+  
+    %44:sreg_32 = PHI %192, %bb.9, %50, %bb.10
+    %45:sreg_32 = PHI %192, %bb.9, %49, %bb.10
+    %46:sreg_32 = PHI %192, %bb.9, %48, %bb.10
+    %195:vgpr_32 = GLOBAL_LOAD_USHORT %243, 0, 0, implicit $exec :: (load (s16) from %ir.p6, addrspace 1)
+    %196:vgpr_32 = GLOBAL_LOAD_USHORT %243, 2, 0, implicit $exec :: (load (s16) from %ir.p6 + 2, addrspace 1)
+    %47:vgpr_32 = V_LSHL_OR_B32_e64 killed %196, 16, killed %195, implicit $exec
+    %198:vgpr_32 = V_ADD_U32_e64 %46, %6, 0, implicit $exec
+    GLOBAL_STORE_DWORD %239, killed %198, 0, 0, implicit $exec :: (store (s32) into %ir.p2, addrspace 1)
+    %199:sgpr_32 = S_CVT_F32_U32 %46, implicit $mode
+    %200:vgpr_32 = nofpexcept V_RCP_IFLAG_F32_e64 0, killed %199, 0, 0, implicit $mode, implicit $exec
+    %203:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %200, implicit $exec
+    %202:sgpr_32 = nnan ninf nsz arcp contract afn reassoc nofpexcept S_MUL_F32 killed %203, 1333788670, implicit $mode
+    %204:sreg_32 = nofpexcept S_CVT_U32_F32 killed %202, implicit $mode
+    %205:sreg_32 = S_MUL_I32 %45, %204
+    %206:sreg_32 = S_MUL_HI_U32 %204, killed %205
+    %207:sreg_32 = S_ADD_I32 killed %204, killed %206, implicit-def dead $scc
+    %208:vgpr_32 = V_MUL_HI_U32_e64 %234.sub0, killed %207, implicit $exec
+    %209:vgpr_32 = V_MUL_LO_U32_e64 %208, %46, implicit $exec
+    %210:vgpr_32 = V_SUB_U32_e64 %35, killed %209, 0, implicit $exec
+    %211:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %46, %210, implicit $exec
+    %212:vgpr_32 = V_ADD_U32_e64 1, %208, 0, implicit $exec
+    %213:vgpr_32 = V_CNDMASK_B32_e64 0, killed %208, 0, killed %212, %211, implicit $exec
+    %214:vgpr_32 = V_SUBREV_U32_e64 %46, %210, 0, implicit $exec
+    %215:vgpr_32 = V_CNDMASK_B32_e64 0, killed %210, 0, killed %214, killed %211, implicit $exec
+    %216:sreg_32_xm0_xexec = V_CMP_LE_U32_e64 %46, killed %215, implicit $exec
+    %217:vgpr_32 = V_ADD_U32_e64 1, %213, 0, implicit $exec
+    %218:vgpr_32 = V_CNDMASK_B32_e64 0, killed %213, 0, killed %217, killed %216, implicit $exec
+    GLOBAL_STORE_DWORD %242, killed %218, 0, 0, implicit $exec :: (store (s32) into %ir.p5, addrspace 1)
+    %48:sreg_32 = S_ADD_I32 %46, 1, implicit-def dead $scc
+    %49:sreg_32 = S_ADD_I32 killed %45, -1, implicit-def dead $scc
+    %219:sreg_32 = V_CMP_GE_U32_e64 %48, %75, implicit $exec
+    %50:sreg_32 = SI_IF_BREAK killed %219, killed %44, implicit-def dead $scc
+    %248:vgpr_32 = COPY killed %46, implicit $exec
+    SI_LOOP %50, %bb.10, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.12
+  
+  bb.11:
+    successors: %bb.5(0x80000000)
+  
+    SI_END_CF killed %28, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %54:vgpr_32 = V_MUL_LO_U32_e64 killed %252, killed %247, implicit $exec
+    S_BRANCH %bb.5
+  
+  bb.12:
+    successors: %bb.7(0x80000000)
+  
+    SI_END_CF killed %50, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %58:vgpr_32 = V_MUL_LO_U32_e64 killed %18, killed %246, implicit $exec
+    %59:vgpr_32 = V_MUL_LO_U32_e64 killed %47, killed %248, implicit $exec
+    S_BRANCH %bb.7
+  
+  bb.13:
+    %228:vgpr_32 = V_MUL_LO_U32_e64 killed %7, killed %244, implicit $exec
+    %229:vgpr_32 = V_ADD_U32_e64 killed %0, killed %23, 0, implicit $exec
+    %230:vgpr_32 = V_SUB_U32_e64 killed %228, killed %229, 0, implicit $exec
+    %231:vgpr_32 = V_ADD_U32_e64 killed %230, killed %22, 0, implicit $exec
+    %232:vgpr_32 = V_ADD3_U32_e64 killed %231, killed %76, -100, implicit $exec
+    %233:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %232, implicit $exec
+    $sgpr0 = COPY killed %233
+    SI_RETURN_TO_EPILOG killed $sgpr0
+...
+---
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
new file mode 100644
index 0000000000000..8e70b6cf75cb7
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
@@ -0,0 +1,1649 @@
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=amdgpu-next-use -debug-only=amdgpu-next-use %s -o /dev/null 2>&1 | FileCheck %s
+# 
+# MIR CFG:
+#
+#                     bb.0.entry
+#                         |
+#                 bb.1.loop1.header<-------+
+#                         |                |
+#                 bb.2.loop2.header<---+   |
+#                         |            |   |
+#                     bb.3.loop3<--+   |   |
+#                         |        |   |   |
+#                         +--------+   |   |
+#                         |            |   |
+#                 bb.4.loop2.latch-----+   |
+#                         |                |
+#                 bb.5.loop1.latch---------+
+#                         |
+#                     bb.6.exit
+#
+
+
+
+
+# CHECK-LABEL: === NextUseAnalysis Results for test9 ===
+# CHECK: --- MBB_0 ---
+# CHECK: Instr: %0:vgpr_32 = COPY killed $vgpr11
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Instr: %1:vgpr_32 = COPY killed $vgpr10
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 64 ]
+# CHECK: Instr: %2:vgpr_32 = COPY killed $vgpr9
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 63 ]
+# CHECK: Vreg: %1[ 54 ]
+# CHECK: Instr: %3:vgpr_32 = COPY killed $vgpr8
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 62 ]
+# CHECK: Vreg: %2[ 9 ]
+# CHECK: Vreg: %1[ 53 ]
+# CHECK: Instr: %4:vgpr_32 = COPY killed $vgpr7
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 61 ]
+# CHECK: Vreg: %2[ 8 ]
+# CHECK: Vreg: %1[ 52 ]
+# CHECK: Vreg: %3[ 8 ]
+# CHECK: Instr: %5:vgpr_32 = COPY killed $vgpr6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 60 ]
+# CHECK: Vreg: %2[ 7 ]
+# CHECK: Vreg: %4[ 8 ]
+# CHECK: Vreg: %1[ 51 ]
+# CHECK: Vreg: %3[ 7 ]
+# CHECK: Instr: %6:vgpr_32 = COPY killed $vgpr5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 59 ]
+# CHECK: Vreg: %2[ 6 ]
+# CHECK: Vreg: %4[ 7 ]
+# CHECK: Vreg: %1[ 50 ]
+# CHECK: Vreg: %3[ 6 ]
+# CHECK: Vreg: %5[ 7 ]
+# CHECK: Instr: %7:vgpr_32 = COPY killed $vgpr4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 58 ]
+# CHECK: Vreg: %2[ 5 ]
+# CHECK: Vreg: %4[ 6 ]
+# CHECK: Vreg: %6[ 7 ]
+# CHECK: Vreg: %1[ 49 ]
+# CHECK: Vreg: %3[ 5 ]
+# CHECK: Vreg: %5[ 6 ]
+# CHECK: Instr: %8:vgpr_32 = COPY killed $vgpr3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 57 ]
+# CHECK: Vreg: %7[ 6 ]
+# CHECK: Vreg: %2[ 4 ]
+# CHECK: Vreg: %4[ 5 ]
+# CHECK: Vreg: %6[ 6 ]
+# CHECK: Vreg: %1[ 48 ]
+# CHECK: Vreg: %3[ 4 ]
+# CHECK: Vreg: %5[ 5 ]
+# CHECK: Instr: %9:vgpr_32 = COPY killed $vgpr2
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 56 ]
+# CHECK: Vreg: %7[ 5 ]
+# CHECK: Vreg: %2[ 3 ]
+# CHECK: Vreg: %4[ 4 ]
+# CHECK: Vreg: %6[ 5 ]
+# CHECK: Vreg: %1[ 47 ]
+# CHECK: Vreg: %8[ 6 ]
+# CHECK: Vreg: %3[ 3 ]
+# CHECK: Vreg: %5[ 4 ]
+# CHECK: Instr: %10:vgpr_32 = COPY killed $vgpr1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 55 ]
+# CHECK: Vreg: %7[ 4 ]
+# CHECK: Vreg: %2[ 2 ]
+# CHECK: Vreg: %9[ 5 ]
+# CHECK: Vreg: %4[ 3 ]
+# CHECK: Vreg: %6[ 4 ]
+# CHECK: Vreg: %1[ 46 ]
+# CHECK: Vreg: %8[ 5 ]
+# CHECK: Vreg: %3[ 2 ]
+# CHECK: Vreg: %5[ 3 ]
+# CHECK: Instr: %11:vgpr_32 = COPY killed $vgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 54 ]
+# CHECK: Vreg: %7[ 3 ]
+# CHECK: Vreg: %2[ 1 ]
+# CHECK: Vreg: %9[ 4 ]
+# CHECK: Vreg: %4[ 2 ]
+# CHECK: Vreg: %6[ 3 ]
+# CHECK: Vreg: %1[ 45 ]
+# CHECK: Vreg: %8[ 4 ]
+# CHECK: Vreg: %3[ 1 ]
+# CHECK: Vreg: %10[ 5 ]
+# CHECK: Vreg: %5[ 2 ]
+# CHECK: Instr: %12:vreg_64 = REG_SEQUENCE killed %3, %subreg.sub0, killed %2, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 53 ]
+# CHECK: Vreg: %7[ 2 ]
+# CHECK: Vreg: %2[ 0 ]
+# CHECK: Vreg: %9[ 3 ]
+# CHECK: Vreg: %4[ 1 ]
+# CHECK: Vreg: %11[ 4 ]
+# CHECK: Vreg: %6[ 2 ]
+# CHECK: Vreg: %1[ 44 ]
+# CHECK: Vreg: %8[ 3 ]
+# CHECK: Vreg: %3[ 0 ]
+# CHECK: Vreg: %10[ 4 ]
+# CHECK: Vreg: %5[ 1 ]
+# CHECK: Instr: %13:vreg_64 = REG_SEQUENCE killed %5, %subreg.sub0, killed %4, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 52 ]
+# CHECK: Vreg: %7[ 1 ]
+# CHECK: Vreg: %9[ 2 ]
+# CHECK: Vreg: %4[ 0 ]
+# CHECK: Vreg: %11[ 3 ]
+# CHECK: Vreg: %6[ 1 ]
+# CHECK: Vreg: %1[ 43 ]
+# CHECK: Vreg: %8[ 2 ]
+# CHECK: Vreg: %10[ 3 ]
+# CHECK: Vreg: %5[ 0 ]
+# CHECK: Vreg: %12[ 37 ]
+# CHECK: Instr: %14:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, killed %6, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 51 ]
+# CHECK: Vreg: %7[ 0 ]
+# CHECK: Vreg: %9[ 1 ]
+# CHECK: Vreg: %11[ 2 ]
+# CHECK: Vreg: %6[ 0 ]
+# CHECK: Vreg: %13[ 20 ]
+# CHECK: Vreg: %1[ 42 ]
+# CHECK: Vreg: %8[ 1 ]
+# CHECK: Vreg: %10[ 2 ]
+# CHECK: Vreg: %12[ 36 ]
+# CHECK: Instr: %15:vreg_64 = REG_SEQUENCE killed %9, %subreg.sub0, killed %8, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 50 ]
+# CHECK: Vreg: %14[ 27 ]
+# CHECK: Vreg: %9[ 0 ]
+# CHECK: Vreg: %11[ 1 ]
+# CHECK: Vreg: %13[ 19 ]
+# CHECK: Vreg: %1[ 41 ]
+# CHECK: Vreg: %8[ 0 ]
+# CHECK: Vreg: %10[ 1 ]
+# CHECK: Vreg: %12[ 35 ]
+# CHECK: Instr: %16:vreg_64 = REG_SEQUENCE killed %11, %subreg.sub0, killed %10, %subreg.sub1
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 49 ]
+# CHECK: Vreg: %14[ 26 ]
+# CHECK: Vreg: %11[ 0 ]
+# CHECK: Vreg: %13[ 18 ]
+# CHECK: Vreg: %1[ 40 ]
+# CHECK: Vreg: %15[ 10 ]
+# CHECK: Vreg: %10[ 0 ]
+# CHECK: Vreg: %12[ 34 ]
+# CHECK: Instr: %17:vgpr_32 = GLOBAL_LOAD_UBYTE %16, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 48 ]
+# CHECK: Vreg: %14[ 25 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %13[ 17 ]
+# CHECK: Vreg: %1[ 39 ]
+# CHECK: Vreg: %15[ 9 ]
+# CHECK: Vreg: %12[ 33 ]
+# CHECK: Instr: %18:vgpr_32 = GLOBAL_LOAD_UBYTE %16, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %14[ 24 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %13[ 16 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %15[ 8 ]
+# CHECK: Vreg: %17[ 1 ]
+# CHECK: Vreg: %12[ 32 ]
+# CHECK: Instr: %19:vgpr_32 = V_LSHL_OR_B32_e64 killed %18, 8, killed %17, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %14[ 23 ]
+# CHECK: Vreg: %16[ 1 ]
+# CHECK: Vreg: %18[ 0 ]
+# CHECK: Vreg: %13[ 15 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %15[ 7 ]
+# CHECK: Vreg: %17[ 0 ]
+# CHECK: Vreg: %12[ 31 ]
+# CHECK: Instr: %20:vgpr_32 = GLOBAL_LOAD_UBYTE %16, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %14[ 22 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %13[ 14 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %12[ 30 ]
+# CHECK: Vreg: %19[ 3 ]
+# CHECK: Instr: %21:vgpr_32 = GLOBAL_LOAD_UBYTE killed %16, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 44 ]
+# CHECK: Vreg: %14[ 21 ]
+# CHECK: Vreg: %16[ 0 ]
+# CHECK: Vreg: %13[ 13 ]
+# CHECK: Vreg: %20[ 1 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %12[ 29 ]
+# CHECK: Vreg: %19[ 2 ]
+# CHECK: Instr: %22:vgpr_32 = V_LSHL_OR_B32_e64 killed %21, 8, killed %20, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Vreg: %14[ 20 ]
+# CHECK: Vreg: %21[ 0 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %20[ 0 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %12[ 28 ]
+# CHECK: Vreg: %19[ 1 ]
+# CHECK: Instr: %23:vgpr_32 = V_LSHL_OR_B32_e64 killed %22, 16, killed %19, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 42 ]
+# CHECK: Vreg: %14[ 19 ]
+# CHECK: Vreg: %13[ 11 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %22[ 0 ]
+# CHECK: Vreg: %12[ 27 ]
+# CHECK: Vreg: %19[ 0 ]
+# CHECK: Instr: %24:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %14[ 18 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %12[ 26 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %14[ 18 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %12[ 26 ]
+# CHECK: --- MBB_1 ---
+# CHECK: Instr: %25:sreg_32 = PHI %24, %bb.0, %26, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %14[ 18 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %12[ 26 ]
+# CHECK: Instr: %27:sreg_32 = PHI %24, %bb.0, %28, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %14[ 18 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %25[ 49 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %12[ 26 ]
+# CHECK: Instr: %29:vgpr_32 = PHI %23, %bb.0, %30, %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %14[ 18 ]
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %25[ 49 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %27[ 47 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %24[ 1 ]
+# CHECK: Vreg: %12[ 26 ]
+# CHECK: Instr: %31:vgpr_32 = V_MOV_B32_e32 13, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %14[ 17 ]
+# CHECK: Vreg: %23[ LoopTag+53 ]
+# CHECK: Vreg: %25[ 48 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %27[ 46 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %29[ 38 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %12[ 25 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %14[ 17 ]
+# CHECK: Vreg: %23[ LoopTag+53 ]
+# CHECK: Vreg: %25[ 48 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %27[ 46 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %29[ 38 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %12[ 25 ]
+# CHECK: --- MBB_2 ---
+# CHECK: Instr: %32:sreg_32 = PHI %24, %bb.1, %33, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %14[ 17 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+53 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %25[ LoopTag+48 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %27[ LoopTag+46 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %29[ 38 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %12[ 25 ]
+# CHECK: Instr: %34:sreg_32 = PHI %24, %bb.1, %35, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %14[ 17 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+53 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %25[ LoopTag+48 ]
+# CHECK: Vreg: %32[ 41 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %27[ LoopTag+46 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %29[ 38 ]
+# CHECK: Vreg: %24[ 0 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %12[ 25 ]
+# CHECK: Instr: %36:vgpr_32 = PHI %31, %bb.1, %37, %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %14[ 17 ]
+# CHECK: Vreg: %23[ LoopTag*2+53 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %25[ LoopTag+48 ]
+# CHECK: Vreg: %32[ 41 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %27[ LoopTag+46 ]
+# CHECK: Vreg: %34[ 8 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %29[ 38 ]
+# CHECK: Vreg: %31[ 0 ]
+# CHECK: Vreg: %12[ 25 ]
+# CHECK: Instr: %38:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 0, 0, implicit $exec :: (load (s8) from %ir.p2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 39 ]
+# CHECK: Vreg: %14[ 16 ]
+# CHECK: Vreg: %23[ LoopTag*2+52 ]
+# CHECK: Vreg: %25[ LoopTag+47 ]
+# CHECK: Vreg: %32[ 40 ]
+# CHECK: Vreg: %13[ 8 ]
+# CHECK: Vreg: %1[ 30 ]
+# CHECK: Vreg: %27[ LoopTag+45 ]
+# CHECK: Vreg: %34[ 7 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %29[ 37 ]
+# CHECK: Vreg: %36[ LoopTag*2+53 ]
+# CHECK: Vreg: %12[ 24 ]
+# CHECK: Instr: %39:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 1, 0, implicit $exec :: (load (s8) from %ir.p2 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 38 ]
+# CHECK: Vreg: %14[ 15 ]
+# CHECK: Vreg: %23[ LoopTag*2+51 ]
+# CHECK: Vreg: %25[ LoopTag+46 ]
+# CHECK: Vreg: %32[ 39 ]
+# CHECK: Vreg: %13[ 7 ]
+# CHECK: Vreg: %1[ 29 ]
+# CHECK: Vreg: %27[ LoopTag+44 ]
+# CHECK: Vreg: %34[ 6 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %29[ 36 ]
+# CHECK: Vreg: %36[ LoopTag*2+52 ]
+# CHECK: Vreg: %12[ 23 ]
+# CHECK: Vreg: %38[ 1 ]
+# CHECK: Instr: %40:vgpr_32 = V_LSHL_OR_B32_e64 killed %39, 8, killed %38, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 37 ]
+# CHECK: Vreg: %14[ 14 ]
+# CHECK: Vreg: %23[ LoopTag*2+50 ]
+# CHECK: Vreg: %25[ LoopTag+45 ]
+# CHECK: Vreg: %32[ 38 ]
+# CHECK: Vreg: %13[ 6 ]
+# CHECK: Vreg: %39[ 0 ]
+# CHECK: Vreg: %1[ 28 ]
+# CHECK: Vreg: %27[ LoopTag+43 ]
+# CHECK: Vreg: %34[ 5 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %29[ 35 ]
+# CHECK: Vreg: %36[ LoopTag*2+51 ]
+# CHECK: Vreg: %12[ 22 ]
+# CHECK: Vreg: %38[ 0 ]
+# CHECK: Instr: %41:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 2, 0, implicit $exec :: (load (s8) from %ir.p2 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 36 ]
+# CHECK: Vreg: %14[ 13 ]
+# CHECK: Vreg: %40[ 3 ]
+# CHECK: Vreg: %23[ LoopTag*2+49 ]
+# CHECK: Vreg: %25[ LoopTag+44 ]
+# CHECK: Vreg: %32[ 37 ]
+# CHECK: Vreg: %13[ 5 ]
+# CHECK: Vreg: %1[ 27 ]
+# CHECK: Vreg: %27[ LoopTag+42 ]
+# CHECK: Vreg: %34[ 4 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %29[ 34 ]
+# CHECK: Vreg: %36[ LoopTag*2+50 ]
+# CHECK: Vreg: %12[ 21 ]
+# CHECK: Instr: %42:vgpr_32 = GLOBAL_LOAD_UBYTE %15, 3, 0, implicit $exec :: (load (s8) from %ir.p2 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 35 ]
+# CHECK: Vreg: %14[ 12 ]
+# CHECK: Vreg: %40[ 2 ]
+# CHECK: Vreg: %23[ LoopTag*2+48 ]
+# CHECK: Vreg: %25[ LoopTag+43 ]
+# CHECK: Vreg: %32[ 36 ]
+# CHECK: Vreg: %13[ 4 ]
+# CHECK: Vreg: %1[ 26 ]
+# CHECK: Vreg: %27[ LoopTag+41 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %15[ 0 ]
+# CHECK: Vreg: %41[ 1 ]
+# CHECK: Vreg: %29[ 33 ]
+# CHECK: Vreg: %36[ LoopTag*2+49 ]
+# CHECK: Vreg: %12[ 20 ]
+# CHECK: Instr: %43:vgpr_32 = V_LSHL_OR_B32_e64 killed %42, 8, killed %41, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 34 ]
+# CHECK: Vreg: %14[ 11 ]
+# CHECK: Vreg: %40[ 1 ]
+# CHECK: Vreg: %42[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+47 ]
+# CHECK: Vreg: %25[ LoopTag+42 ]
+# CHECK: Vreg: %32[ 35 ]
+# CHECK: Vreg: %13[ 3 ]
+# CHECK: Vreg: %1[ 25 ]
+# CHECK: Vreg: %27[ LoopTag+40 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %15[ 38 ]
+# CHECK: Vreg: %41[ 0 ]
+# CHECK: Vreg: %29[ 32 ]
+# CHECK: Vreg: %36[ LoopTag*2+48 ]
+# CHECK: Vreg: %12[ 19 ]
+# CHECK: Instr: %44:vgpr_32 = V_LSHL_OR_B32_e64 killed %43, 16, killed %40, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 33 ]
+# CHECK: Vreg: %14[ 10 ]
+# CHECK: Vreg: %40[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+46 ]
+# CHECK: Vreg: %25[ LoopTag+41 ]
+# CHECK: Vreg: %32[ 34 ]
+# CHECK: Vreg: %13[ 2 ]
+# CHECK: Vreg: %1[ 24 ]
+# CHECK: Vreg: %27[ LoopTag+39 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 37 ]
+# CHECK: Vreg: %29[ 31 ]
+# CHECK: Vreg: %36[ LoopTag*2+47 ]
+# CHECK: Vreg: %43[ 0 ]
+# CHECK: Vreg: %12[ 18 ]
+# CHECK: Instr: %45:vgpr_32 = V_ADD_U32_e64 %34, %44, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 32 ]
+# CHECK: Vreg: %14[ 9 ]
+# CHECK: Vreg: %23[ LoopTag*2+45 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ LoopTag+40 ]
+# CHECK: Vreg: %32[ 33 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 23 ]
+# CHECK: Vreg: %27[ LoopTag+38 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 36 ]
+# CHECK: Vreg: %29[ 30 ]
+# CHECK: Vreg: %36[ LoopTag*2+46 ]
+# CHECK: Vreg: %12[ 17 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE_D16_HI %13, %45, 2, 0, implicit $exec :: (store (s8) into %ir.p4 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 31 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %23[ LoopTag*2+44 ]
+# CHECK: Vreg: %44[ LoopTag+36 ]
+# CHECK: Vreg: %25[ LoopTag+39 ]
+# CHECK: Vreg: %32[ 32 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 22 ]
+# CHECK: Vreg: %27[ LoopTag+37 ]
+# CHECK: Vreg: %34[ 30 ]
+# CHECK: Vreg: %15[ 35 ]
+# CHECK: Vreg: %29[ 29 ]
+# CHECK: Vreg: %36[ LoopTag*2+45 ]
+# CHECK: Vreg: %12[ 16 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %13, %45, 0, 0, implicit $exec :: (store (s8) into %ir.p4, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 30 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %14[ 7 ]
+# CHECK: Vreg: %23[ LoopTag*2+43 ]
+# CHECK: Vreg: %44[ LoopTag+35 ]
+# CHECK: Vreg: %25[ LoopTag+38 ]
+# CHECK: Vreg: %32[ 31 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 21 ]
+# CHECK: Vreg: %27[ LoopTag+36 ]
+# CHECK: Vreg: %34[ 29 ]
+# CHECK: Vreg: %15[ 34 ]
+# CHECK: Vreg: %29[ 28 ]
+# CHECK: Vreg: %36[ LoopTag*2+44 ]
+# CHECK: Vreg: %12[ 15 ]
+# CHECK: Instr: %46:vgpr_32 = V_LSHRREV_B32_e64 24, %45, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 29 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %23[ LoopTag*2+42 ]
+# CHECK: Vreg: %44[ LoopTag+34 ]
+# CHECK: Vreg: %25[ LoopTag+37 ]
+# CHECK: Vreg: %32[ 30 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 20 ]
+# CHECK: Vreg: %27[ LoopTag+35 ]
+# CHECK: Vreg: %34[ 28 ]
+# CHECK: Vreg: %15[ 33 ]
+# CHECK: Vreg: %29[ 27 ]
+# CHECK: Vreg: %36[ LoopTag*2+43 ]
+# CHECK: Vreg: %12[ 14 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %13, killed %46, 3, 0, implicit $exec :: (store (s8) into %ir.p4 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 28 ]
+# CHECK: Vreg: %45[ 1 ]
+# CHECK: Vreg: %14[ 5 ]
+# CHECK: Vreg: %23[ LoopTag*2+41 ]
+# CHECK: Vreg: %44[ LoopTag+33 ]
+# CHECK: Vreg: %25[ LoopTag+36 ]
+# CHECK: Vreg: %32[ 29 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %46[ 0 ]
+# CHECK: Vreg: %27[ LoopTag+34 ]
+# CHECK: Vreg: %34[ 27 ]
+# CHECK: Vreg: %15[ 32 ]
+# CHECK: Vreg: %29[ 26 ]
+# CHECK: Vreg: %36[ LoopTag*2+42 ]
+# CHECK: Vreg: %12[ 13 ]
+# CHECK: Instr: %47:vgpr_32 = V_LSHRREV_B32_e64 8, killed %45, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 27 ]
+# CHECK: Vreg: %45[ 0 ]
+# CHECK: Vreg: %14[ 4 ]
+# CHECK: Vreg: %23[ LoopTag*2+40 ]
+# CHECK: Vreg: %44[ LoopTag+32 ]
+# CHECK: Vreg: %25[ LoopTag+35 ]
+# CHECK: Vreg: %32[ 28 ]
+# CHECK: Vreg: %13[ 1 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %27[ LoopTag+33 ]
+# CHECK: Vreg: %34[ 26 ]
+# CHECK: Vreg: %15[ 31 ]
+# CHECK: Vreg: %29[ 25 ]
+# CHECK: Vreg: %36[ LoopTag*2+41 ]
+# CHECK: Vreg: %12[ 12 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %13, killed %47, 1, 0, implicit $exec :: (store (s8) into %ir.p4 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 26 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %47[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+39 ]
+# CHECK: Vreg: %44[ LoopTag+31 ]
+# CHECK: Vreg: %25[ LoopTag+34 ]
+# CHECK: Vreg: %32[ 27 ]
+# CHECK: Vreg: %13[ 0 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %27[ LoopTag+32 ]
+# CHECK: Vreg: %34[ 25 ]
+# CHECK: Vreg: %15[ 30 ]
+# CHECK: Vreg: %29[ 24 ]
+# CHECK: Vreg: %36[ LoopTag*2+40 ]
+# CHECK: Vreg: %12[ 11 ]
+# CHECK: Instr: %48:sreg_32 = S_MOV_B32 0
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %23[ LoopTag*2+38 ]
+# CHECK: Vreg: %44[ LoopTag+30 ]
+# CHECK: Vreg: %25[ LoopTag+33 ]
+# CHECK: Vreg: %32[ 26 ]
+# CHECK: Vreg: %13[ 37 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %27[ LoopTag+31 ]
+# CHECK: Vreg: %34[ 24 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %29[ 23 ]
+# CHECK: Vreg: %36[ LoopTag*2+39 ]
+# CHECK: Vreg: %12[ 10 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 25 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %23[ LoopTag*2+38 ]
+# CHECK: Vreg: %44[ LoopTag+30 ]
+# CHECK: Vreg: %25[ LoopTag+33 ]
+# CHECK: Vreg: %32[ 26 ]
+# CHECK: Vreg: %13[ 37 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %27[ LoopTag+31 ]
+# CHECK: Vreg: %34[ 24 ]
+# CHECK: Vreg: %15[ 29 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %29[ 23 ]
+# CHECK: Vreg: %36[ LoopTag*2+39 ]
+# CHECK: Vreg: %12[ 10 ]
+# CHECK: --- MBB_3 ---
+# CHECK: Instr: %49:sreg_32 = PHI %48, %bb.2, %50, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %23[ LoopTag*3+38 ]
+# CHECK: Vreg: %44[ LoopTag*2+30 ]
+# CHECK: Vreg: %25[ LoopTag*2+33 ]
+# CHECK: Vreg: %32[ LoopTag+26 ]
+# CHECK: Vreg: %13[ LoopTag+37 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %27[ LoopTag*2+31 ]
+# CHECK: Vreg: %34[ LoopTag+24 ]
+# CHECK: Vreg: %15[ LoopTag+29 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+23 ]
+# CHECK: Vreg: %36[ LoopTag*3+39 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %12[ 10 ]
+# CHECK: Instr: %51:sreg_32 = PHI %48, %bb.2, %52, %bb.3
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+25 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %23[ LoopTag*3+38 ]
+# CHECK: Vreg: %49[ 17 ]
+# CHECK: Vreg: %44[ LoopTag*2+30 ]
+# CHECK: Vreg: %25[ LoopTag*2+33 ]
+# CHECK: Vreg: %32[ LoopTag+26 ]
+# CHECK: Vreg: %13[ LoopTag+37 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %27[ LoopTag*2+31 ]
+# CHECK: Vreg: %34[ LoopTag+24 ]
+# CHECK: Vreg: %15[ LoopTag+29 ]
+# CHECK: Vreg: %48[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+23 ]
+# CHECK: Vreg: %36[ LoopTag*3+39 ]
+# CHECK: Vreg: %12[ 10 ]
+# CHECK: Instr: %52:sreg_32 = S_ADD_I32 killed %51, 3, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+24 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %23[ LoopTag*3+37 ]
+# CHECK: Vreg: %49[ 16 ]
+# CHECK: Vreg: %44[ LoopTag*2+29 ]
+# CHECK: Vreg: %25[ LoopTag*2+32 ]
+# CHECK: Vreg: %51[ 0 ]
+# CHECK: Vreg: %32[ LoopTag+25 ]
+# CHECK: Vreg: %13[ LoopTag+36 ]
+# CHECK: Vreg: %1[ 15 ]
+# CHECK: Vreg: %27[ LoopTag*2+30 ]
+# CHECK: Vreg: %34[ LoopTag+23 ]
+# CHECK: Vreg: %15[ LoopTag+28 ]
+# CHECK: Vreg: %29[ LoopTag+22 ]
+# CHECK: Vreg: %36[ LoopTag*3+38 ]
+# CHECK: Vreg: %12[ 9 ]
+# CHECK: Instr: %53:vgpr_32 = GLOBAL_LOAD_UBYTE %14, 0, 0, implicit $exec :: (load (s8) from %ir.p3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+23 ]
+# CHECK: Vreg: %52[ 7 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*3+36 ]
+# CHECK: Vreg: %49[ 15 ]
+# CHECK: Vreg: %44[ LoopTag*2+28 ]
+# CHECK: Vreg: %25[ LoopTag*2+31 ]
+# CHECK: Vreg: %32[ LoopTag+24 ]
+# CHECK: Vreg: %13[ LoopTag+35 ]
+# CHECK: Vreg: %1[ 14 ]
+# CHECK: Vreg: %27[ LoopTag*2+29 ]
+# CHECK: Vreg: %34[ LoopTag+22 ]
+# CHECK: Vreg: %15[ LoopTag+27 ]
+# CHECK: Vreg: %29[ LoopTag+21 ]
+# CHECK: Vreg: %36[ LoopTag*3+37 ]
+# CHECK: Vreg: %12[ 8 ]
+# CHECK: Instr: %54:vgpr_32 = GLOBAL_LOAD_UBYTE %14, 1, 0, implicit $exec :: (load (s8) from %ir.p3 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+22 ]
+# CHECK: Vreg: %52[ 6 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*3+35 ]
+# CHECK: Vreg: %49[ 14 ]
+# CHECK: Vreg: %44[ LoopTag*2+27 ]
+# CHECK: Vreg: %25[ LoopTag*2+30 ]
+# CHECK: Vreg: %32[ LoopTag+23 ]
+# CHECK: Vreg: %13[ LoopTag+34 ]
+# CHECK: Vreg: %1[ 13 ]
+# CHECK: Vreg: %27[ LoopTag*2+28 ]
+# CHECK: Vreg: %53[ 1 ]
+# CHECK: Vreg: %34[ LoopTag+21 ]
+# CHECK: Vreg: %15[ LoopTag+26 ]
+# CHECK: Vreg: %29[ LoopTag+20 ]
+# CHECK: Vreg: %36[ LoopTag*3+36 ]
+# CHECK: Vreg: %12[ 7 ]
+# CHECK: Instr: %55:vgpr_32 = V_LSHL_OR_B32_e64 killed %54, 8, killed %53, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+21 ]
+# CHECK: Vreg: %52[ 5 ]
+# CHECK: Vreg: %14[ 1 ]
+# CHECK: Vreg: %54[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*3+34 ]
+# CHECK: Vreg: %49[ 13 ]
+# CHECK: Vreg: %44[ LoopTag*2+26 ]
+# CHECK: Vreg: %25[ LoopTag*2+29 ]
+# CHECK: Vreg: %32[ LoopTag+22 ]
+# CHECK: Vreg: %13[ LoopTag+33 ]
+# CHECK: Vreg: %1[ 12 ]
+# CHECK: Vreg: %27[ LoopTag*2+27 ]
+# CHECK: Vreg: %53[ 0 ]
+# CHECK: Vreg: %34[ LoopTag+20 ]
+# CHECK: Vreg: %15[ LoopTag+25 ]
+# CHECK: Vreg: %29[ LoopTag+19 ]
+# CHECK: Vreg: %36[ LoopTag*3+35 ]
+# CHECK: Vreg: %12[ 6 ]
+# CHECK: Instr: %56:vgpr_32 = GLOBAL_LOAD_UBYTE %14, 2, 0, implicit $exec :: (load (s8) from %ir.p3 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+20 ]
+# CHECK: Vreg: %52[ 4 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*3+33 ]
+# CHECK: Vreg: %49[ 12 ]
+# CHECK: Vreg: %44[ LoopTag*2+25 ]
+# CHECK: Vreg: %25[ LoopTag*2+28 ]
+# CHECK: Vreg: %32[ LoopTag+21 ]
+# CHECK: Vreg: %13[ LoopTag+32 ]
+# CHECK: Vreg: %1[ 11 ]
+# CHECK: Vreg: %27[ LoopTag*2+26 ]
+# CHECK: Vreg: %34[ LoopTag+19 ]
+# CHECK: Vreg: %15[ LoopTag+24 ]
+# CHECK: Vreg: %29[ LoopTag+18 ]
+# CHECK: Vreg: %55[ 3 ]
+# CHECK: Vreg: %36[ LoopTag*3+34 ]
+# CHECK: Vreg: %12[ 5 ]
+# CHECK: Instr: %57:vgpr_32 = GLOBAL_LOAD_UBYTE %14, 3, 0, implicit $exec :: (load (s8) from %ir.p3 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+19 ]
+# CHECK: Vreg: %52[ 3 ]
+# CHECK: Vreg: %14[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*3+32 ]
+# CHECK: Vreg: %49[ 11 ]
+# CHECK: Vreg: %56[ 1 ]
+# CHECK: Vreg: %44[ LoopTag*2+24 ]
+# CHECK: Vreg: %25[ LoopTag*2+27 ]
+# CHECK: Vreg: %32[ LoopTag+20 ]
+# CHECK: Vreg: %13[ LoopTag+31 ]
+# CHECK: Vreg: %1[ 10 ]
+# CHECK: Vreg: %27[ LoopTag*2+25 ]
+# CHECK: Vreg: %34[ LoopTag+18 ]
+# CHECK: Vreg: %15[ LoopTag+23 ]
+# CHECK: Vreg: %29[ LoopTag+17 ]
+# CHECK: Vreg: %55[ 2 ]
+# CHECK: Vreg: %36[ LoopTag*3+33 ]
+# CHECK: Vreg: %12[ 4 ]
+# CHECK: Instr: %58:vgpr_32 = V_LSHL_OR_B32_e64 killed %57, 8, killed %56, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+18 ]
+# CHECK: Vreg: %52[ 2 ]
+# CHECK: Vreg: %14[ 15 ]
+# CHECK: Vreg: %23[ LoopTag*3+31 ]
+# CHECK: Vreg: %49[ 10 ]
+# CHECK: Vreg: %56[ 0 ]
+# CHECK: Vreg: %44[ LoopTag*2+23 ]
+# CHECK: Vreg: %25[ LoopTag*2+26 ]
+# CHECK: Vreg: %32[ LoopTag+19 ]
+# CHECK: Vreg: %13[ LoopTag+30 ]
+# CHECK: Vreg: %1[ 9 ]
+# CHECK: Vreg: %27[ LoopTag*2+24 ]
+# CHECK: Vreg: %34[ LoopTag+17 ]
+# CHECK: Vreg: %15[ LoopTag+22 ]
+# CHECK: Vreg: %29[ LoopTag+16 ]
+# CHECK: Vreg: %55[ 1 ]
+# CHECK: Vreg: %36[ LoopTag*3+32 ]
+# CHECK: Vreg: %12[ 3 ]
+# CHECK: Vreg: %57[ 0 ]
+# CHECK: Instr: %59:vgpr_32 = V_LSHL_OR_B32_e64 killed %58, 16, killed %55, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+17 ]
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %14[ 14 ]
+# CHECK: Vreg: %23[ LoopTag*3+30 ]
+# CHECK: Vreg: %49[ 9 ]
+# CHECK: Vreg: %44[ LoopTag*2+22 ]
+# CHECK: Vreg: %25[ LoopTag*2+25 ]
+# CHECK: Vreg: %32[ LoopTag+18 ]
+# CHECK: Vreg: %13[ LoopTag+29 ]
+# CHECK: Vreg: %58[ 0 ]
+# CHECK: Vreg: %1[ 8 ]
+# CHECK: Vreg: %27[ LoopTag*2+23 ]
+# CHECK: Vreg: %34[ LoopTag+16 ]
+# CHECK: Vreg: %15[ LoopTag+21 ]
+# CHECK: Vreg: %29[ LoopTag+15 ]
+# CHECK: Vreg: %55[ 0 ]
+# CHECK: Vreg: %36[ LoopTag*3+31 ]
+# CHECK: Vreg: %12[ 2 ]
+# CHECK: Instr: %60:vgpr_32 = V_ADD_U32_e64 %52, %59, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+16 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 13 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*3+29 ]
+# CHECK: Vreg: %49[ 8 ]
+# CHECK: Vreg: %44[ LoopTag*2+21 ]
+# CHECK: Vreg: %25[ LoopTag*2+24 ]
+# CHECK: Vreg: %32[ LoopTag+17 ]
+# CHECK: Vreg: %13[ LoopTag+28 ]
+# CHECK: Vreg: %1[ 7 ]
+# CHECK: Vreg: %27[ LoopTag*2+22 ]
+# CHECK: Vreg: %34[ LoopTag+15 ]
+# CHECK: Vreg: %15[ LoopTag+20 ]
+# CHECK: Vreg: %29[ LoopTag+14 ]
+# CHECK: Vreg: %36[ LoopTag*3+30 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE_D16_HI %12, %60, 2, 0, implicit $exec :: (store (s8) into %ir.p5 + 2, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+15 ]
+# CHECK: Vreg: %52[ 6 ]
+# CHECK: Vreg: %14[ 12 ]
+# CHECK: Vreg: %59[ LoopTag+12 ]
+# CHECK: Vreg: %23[ LoopTag*3+28 ]
+# CHECK: Vreg: %49[ 7 ]
+# CHECK: Vreg: %44[ LoopTag*2+20 ]
+# CHECK: Vreg: %25[ LoopTag*2+23 ]
+# CHECK: Vreg: %32[ LoopTag+16 ]
+# CHECK: Vreg: %13[ LoopTag+27 ]
+# CHECK: Vreg: %1[ 6 ]
+# CHECK: Vreg: %27[ LoopTag*2+21 ]
+# CHECK: Vreg: %34[ LoopTag+14 ]
+# CHECK: Vreg: %15[ LoopTag+19 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+13 ]
+# CHECK: Vreg: %36[ LoopTag*3+29 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %12, %60, 0, 0, implicit $exec :: (store (s8) into %ir.p5, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+14 ]
+# CHECK: Vreg: %52[ 5 ]
+# CHECK: Vreg: %14[ 11 ]
+# CHECK: Vreg: %59[ LoopTag+11 ]
+# CHECK: Vreg: %23[ LoopTag*3+27 ]
+# CHECK: Vreg: %49[ 6 ]
+# CHECK: Vreg: %44[ LoopTag*2+19 ]
+# CHECK: Vreg: %25[ LoopTag*2+22 ]
+# CHECK: Vreg: %32[ LoopTag+15 ]
+# CHECK: Vreg: %13[ LoopTag+26 ]
+# CHECK: Vreg: %1[ 5 ]
+# CHECK: Vreg: %27[ LoopTag*2+20 ]
+# CHECK: Vreg: %34[ LoopTag+13 ]
+# CHECK: Vreg: %15[ LoopTag+18 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+12 ]
+# CHECK: Vreg: %36[ LoopTag*3+28 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %61:vgpr_32 = V_LSHRREV_B32_e64 24, %60, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+13 ]
+# CHECK: Vreg: %52[ 4 ]
+# CHECK: Vreg: %14[ 10 ]
+# CHECK: Vreg: %59[ LoopTag+10 ]
+# CHECK: Vreg: %23[ LoopTag*3+26 ]
+# CHECK: Vreg: %49[ 5 ]
+# CHECK: Vreg: %44[ LoopTag*2+18 ]
+# CHECK: Vreg: %25[ LoopTag*2+21 ]
+# CHECK: Vreg: %32[ LoopTag+14 ]
+# CHECK: Vreg: %13[ LoopTag+25 ]
+# CHECK: Vreg: %1[ 4 ]
+# CHECK: Vreg: %27[ LoopTag*2+19 ]
+# CHECK: Vreg: %34[ LoopTag+12 ]
+# CHECK: Vreg: %15[ LoopTag+17 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+11 ]
+# CHECK: Vreg: %36[ LoopTag*3+27 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %12, killed %61, 3, 0, implicit $exec :: (store (s8) into %ir.p5 + 3, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+12 ]
+# CHECK: Vreg: %52[ 3 ]
+# CHECK: Vreg: %14[ 9 ]
+# CHECK: Vreg: %59[ LoopTag+9 ]
+# CHECK: Vreg: %61[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*3+25 ]
+# CHECK: Vreg: %49[ 4 ]
+# CHECK: Vreg: %44[ LoopTag*2+17 ]
+# CHECK: Vreg: %25[ LoopTag*2+20 ]
+# CHECK: Vreg: %32[ LoopTag+13 ]
+# CHECK: Vreg: %13[ LoopTag+24 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %27[ LoopTag*2+18 ]
+# CHECK: Vreg: %34[ LoopTag+11 ]
+# CHECK: Vreg: %15[ LoopTag+16 ]
+# CHECK: Vreg: %60[ 1 ]
+# CHECK: Vreg: %29[ LoopTag+10 ]
+# CHECK: Vreg: %36[ LoopTag*3+26 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %62:vgpr_32 = V_LSHRREV_B32_e64 8, killed %60, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+11 ]
+# CHECK: Vreg: %52[ 2 ]
+# CHECK: Vreg: %14[ 8 ]
+# CHECK: Vreg: %59[ LoopTag+8 ]
+# CHECK: Vreg: %23[ LoopTag*3+24 ]
+# CHECK: Vreg: %49[ 3 ]
+# CHECK: Vreg: %44[ LoopTag*2+16 ]
+# CHECK: Vreg: %25[ LoopTag*2+19 ]
+# CHECK: Vreg: %32[ LoopTag+12 ]
+# CHECK: Vreg: %13[ LoopTag+23 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %27[ LoopTag*2+17 ]
+# CHECK: Vreg: %34[ LoopTag+10 ]
+# CHECK: Vreg: %15[ LoopTag+15 ]
+# CHECK: Vreg: %60[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+9 ]
+# CHECK: Vreg: %36[ LoopTag*3+25 ]
+# CHECK: Vreg: %12[ 1 ]
+# CHECK: Instr: GLOBAL_STORE_BYTE %12, killed %62, 1, 0, implicit $exec :: (store (s8) into %ir.p5 + 1, addrspace 1)
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+10 ]
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %14[ 7 ]
+# CHECK: Vreg: %59[ LoopTag+7 ]
+# CHECK: Vreg: %23[ LoopTag*3+23 ]
+# CHECK: Vreg: %49[ 2 ]
+# CHECK: Vreg: %44[ LoopTag*2+15 ]
+# CHECK: Vreg: %25[ LoopTag*2+18 ]
+# CHECK: Vreg: %32[ LoopTag+11 ]
+# CHECK: Vreg: %13[ LoopTag+22 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %27[ LoopTag*2+16 ]
+# CHECK: Vreg: %34[ LoopTag+9 ]
+# CHECK: Vreg: %15[ LoopTag+14 ]
+# CHECK: Vreg: %29[ LoopTag+8 ]
+# CHECK: Vreg: %36[ LoopTag*3+24 ]
+# CHECK: Vreg: %62[ 0 ]
+# CHECK: Vreg: %12[ 0 ]
+# CHECK: Instr: %63:sreg_32 = V_CMP_GE_U32_e64 %52, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+9 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 6 ]
+# CHECK: Vreg: %59[ LoopTag+6 ]
+# CHECK: Vreg: %23[ LoopTag*3+22 ]
+# CHECK: Vreg: %49[ 1 ]
+# CHECK: Vreg: %44[ LoopTag*2+14 ]
+# CHECK: Vreg: %25[ LoopTag*2+17 ]
+# CHECK: Vreg: %32[ LoopTag+10 ]
+# CHECK: Vreg: %13[ LoopTag+21 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %27[ LoopTag*2+15 ]
+# CHECK: Vreg: %34[ LoopTag+8 ]
+# CHECK: Vreg: %15[ LoopTag+13 ]
+# CHECK: Vreg: %29[ LoopTag+7 ]
+# CHECK: Vreg: %36[ LoopTag*3+23 ]
+# CHECK: Vreg: %12[ 14 ]
+# CHECK: Instr: %50:sreg_32 = SI_IF_BREAK killed %63, killed %49, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+8 ]
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %14[ 5 ]
+# CHECK: Vreg: %59[ LoopTag+5 ]
+# CHECK: Vreg: %23[ LoopTag*3+21 ]
+# CHECK: Vreg: %49[ 0 ]
+# CHECK: Vreg: %63[ 0 ]
+# CHECK: Vreg: %44[ LoopTag*2+13 ]
+# CHECK: Vreg: %25[ LoopTag*2+16 ]
+# CHECK: Vreg: %32[ LoopTag+9 ]
+# CHECK: Vreg: %13[ LoopTag+20 ]
+# CHECK: Vreg: %1[ 19 ]
+# CHECK: Vreg: %27[ LoopTag*2+14 ]
+# CHECK: Vreg: %34[ LoopTag+7 ]
+# CHECK: Vreg: %15[ LoopTag+12 ]
+# CHECK: Vreg: %29[ LoopTag+6 ]
+# CHECK: Vreg: %36[ LoopTag*3+22 ]
+# CHECK: Vreg: %12[ 13 ]
+# CHECK: Instr: %64:vgpr_32 = COPY %52, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+7 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 4 ]
+# CHECK: Vreg: %59[ LoopTag+4 ]
+# CHECK: Vreg: %23[ LoopTag*3+20 ]
+# CHECK: Vreg: %44[ LoopTag*2+12 ]
+# CHECK: Vreg: %25[ LoopTag*2+15 ]
+# CHECK: Vreg: %32[ LoopTag+8 ]
+# CHECK: Vreg: %13[ LoopTag+19 ]
+# CHECK: Vreg: %1[ 18 ]
+# CHECK: Vreg: %27[ LoopTag*2+13 ]
+# CHECK: Vreg: %34[ LoopTag+6 ]
+# CHECK: Vreg: %15[ LoopTag+11 ]
+# CHECK: Vreg: %29[ LoopTag+5 ]
+# CHECK: Vreg: %36[ LoopTag*3+21 ]
+# CHECK: Vreg: %50[ 1 ]
+# CHECK: Vreg: %12[ 12 ]
+# CHECK: Instr: SI_LOOP %50, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+6 ]
+# CHECK: Vreg: %64[ LoopTag+3 ]
+# CHECK: Vreg: %52[ 1 ]
+# CHECK: Vreg: %14[ 3 ]
+# CHECK: Vreg: %59[ LoopTag+3 ]
+# CHECK: Vreg: %23[ LoopTag*3+19 ]
+# CHECK: Vreg: %44[ LoopTag*2+11 ]
+# CHECK: Vreg: %25[ LoopTag*2+14 ]
+# CHECK: Vreg: %32[ LoopTag+7 ]
+# CHECK: Vreg: %13[ LoopTag+18 ]
+# CHECK: Vreg: %1[ 17 ]
+# CHECK: Vreg: %27[ LoopTag*2+12 ]
+# CHECK: Vreg: %34[ LoopTag+5 ]
+# CHECK: Vreg: %15[ LoopTag+10 ]
+# CHECK: Vreg: %29[ LoopTag+4 ]
+# CHECK: Vreg: %36[ LoopTag*3+20 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %12[ 11 ]
+# CHECK: Instr: S_BRANCH %bb.4
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ LoopTag+5 ]
+# CHECK: Vreg: %64[ LoopTag+2 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %59[ LoopTag+2 ]
+# CHECK: Vreg: %23[ LoopTag*3+18 ]
+# CHECK: Vreg: %44[ LoopTag*2+10 ]
+# CHECK: Vreg: %25[ LoopTag*2+13 ]
+# CHECK: Vreg: %32[ LoopTag+6 ]
+# CHECK: Vreg: %13[ LoopTag+17 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %27[ LoopTag*2+11 ]
+# CHECK: Vreg: %34[ LoopTag+4 ]
+# CHECK: Vreg: %15[ LoopTag+9 ]
+# CHECK: Vreg: %29[ LoopTag+3 ]
+# CHECK: Vreg: %36[ LoopTag*3+19 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %12[ 10 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ LoopTag+5 ]
+# CHECK: Vreg: %64[ LoopTag+2 ]
+# CHECK: Vreg: %52[ 0 ]
+# CHECK: Vreg: %14[ 2 ]
+# CHECK: Vreg: %59[ LoopTag+2 ]
+# CHECK: Vreg: %23[ LoopTag*3+18 ]
+# CHECK: Vreg: %44[ LoopTag*2+10 ]
+# CHECK: Vreg: %25[ LoopTag*2+13 ]
+# CHECK: Vreg: %32[ LoopTag+6 ]
+# CHECK: Vreg: %13[ LoopTag+17 ]
+# CHECK: Vreg: %1[ 16 ]
+# CHECK: Vreg: %27[ LoopTag*2+11 ]
+# CHECK: Vreg: %34[ LoopTag+4 ]
+# CHECK: Vreg: %15[ LoopTag+9 ]
+# CHECK: Vreg: %29[ LoopTag+3 ]
+# CHECK: Vreg: %36[ LoopTag*3+19 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %12[ 10 ]
+# CHECK: --- MBB_4 ---
+# CHECK: Instr: SI_END_CF killed %50, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 4 ]
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %14[ 24 ]
+# CHECK: Vreg: %59[ 1 ]
+# CHECK: Vreg: %23[ LoopTag*2+17 ]
+# CHECK: Vreg: %44[ LoopTag+9 ]
+# CHECK: Vreg: %25[ LoopTag+12 ]
+# CHECK: Vreg: %32[ 5 ]
+# CHECK: Vreg: %13[ 16 ]
+# CHECK: Vreg: %1[ 38 ]
+# CHECK: Vreg: %27[ LoopTag+10 ]
+# CHECK: Vreg: %34[ 3 ]
+# CHECK: Vreg: %15[ 8 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %36[ LoopTag*2+18 ]
+# CHECK: Vreg: %50[ 0 ]
+# CHECK: Vreg: %12[ 32 ]
+# CHECK: Instr: %65:vgpr_32 = V_ADD_U32_e64 killed %59, %64, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 3 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %14[ 23 ]
+# CHECK: Vreg: %59[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+16 ]
+# CHECK: Vreg: %44[ LoopTag+8 ]
+# CHECK: Vreg: %25[ LoopTag+11 ]
+# CHECK: Vreg: %32[ 4 ]
+# CHECK: Vreg: %13[ 15 ]
+# CHECK: Vreg: %1[ 37 ]
+# CHECK: Vreg: %27[ LoopTag+9 ]
+# CHECK: Vreg: %34[ 2 ]
+# CHECK: Vreg: %15[ 7 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %36[ LoopTag*2+17 ]
+# CHECK: Vreg: %12[ 31 ]
+# CHECK: Instr: %37:vgpr_32 = V_MUL_LO_U32_e64 %29, %65, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 2 ]
+# CHECK: Vreg: %64[ LoopTag+7 ]
+# CHECK: Vreg: %14[ 22 ]
+# CHECK: Vreg: %23[ LoopTag*2+15 ]
+# CHECK: Vreg: %44[ LoopTag+7 ]
+# CHECK: Vreg: %25[ LoopTag+10 ]
+# CHECK: Vreg: %32[ 3 ]
+# CHECK: Vreg: %13[ 14 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %1[ 36 ]
+# CHECK: Vreg: %27[ LoopTag+8 ]
+# CHECK: Vreg: %34[ 1 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ LoopTag*2+16 ]
+# CHECK: Vreg: %12[ 30 ]
+# CHECK: Instr: %35:sreg_32 = S_ADD_I32 killed %34, 2, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 1 ]
+# CHECK: Vreg: %64[ LoopTag+6 ]
+# CHECK: Vreg: %14[ 21 ]
+# CHECK: Vreg: %23[ LoopTag*2+14 ]
+# CHECK: Vreg: %37[ 4 ]
+# CHECK: Vreg: %44[ LoopTag+6 ]
+# CHECK: Vreg: %25[ LoopTag+9 ]
+# CHECK: Vreg: %32[ 2 ]
+# CHECK: Vreg: %13[ 13 ]
+# CHECK: Vreg: %65[ LoopTag*2+15 ]
+# CHECK: Vreg: %1[ 35 ]
+# CHECK: Vreg: %27[ LoopTag+7 ]
+# CHECK: Vreg: %34[ 0 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %29[ 42 ]
+# CHECK: Vreg: %36[ LoopTag*2+15 ]
+# CHECK: Vreg: %12[ 29 ]
+# CHECK: Instr: %66:sreg_32 = V_CMP_GE_U32_e64 %35, %0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 0 ]
+# CHECK: Vreg: %64[ LoopTag+5 ]
+# CHECK: Vreg: %14[ 20 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+13 ]
+# CHECK: Vreg: %37[ 3 ]
+# CHECK: Vreg: %44[ LoopTag+5 ]
+# CHECK: Vreg: %25[ LoopTag+8 ]
+# CHECK: Vreg: %32[ 1 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %65[ LoopTag*2+14 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %27[ LoopTag+6 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %29[ 41 ]
+# CHECK: Vreg: %36[ LoopTag*2+14 ]
+# CHECK: Vreg: %12[ 28 ]
+# CHECK: Instr: %33:sreg_32 = SI_IF_BREAK killed %66, killed %32, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 42 ]
+# CHECK: Vreg: %64[ LoopTag+4 ]
+# CHECK: Vreg: %14[ 19 ]
+# CHECK: Vreg: %66[ 0 ]
+# CHECK: Vreg: %35[ 2 ]
+# CHECK: Vreg: %23[ LoopTag*2+12 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %44[ LoopTag+4 ]
+# CHECK: Vreg: %25[ LoopTag+7 ]
+# CHECK: Vreg: %32[ 0 ]
+# CHECK: Vreg: %13[ 11 ]
+# CHECK: Vreg: %65[ LoopTag*2+13 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %27[ LoopTag+5 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %29[ 40 ]
+# CHECK: Vreg: %36[ LoopTag*2+13 ]
+# CHECK: Vreg: %12[ 27 ]
+# CHECK: Instr: SI_LOOP %33, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %64[ LoopTag+3 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %14[ 18 ]
+# CHECK: Vreg: %35[ 1 ]
+# CHECK: Vreg: %23[ LoopTag*2+11 ]
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %44[ LoopTag+3 ]
+# CHECK: Vreg: %25[ LoopTag+6 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %65[ LoopTag*2+12 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %27[ LoopTag+4 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %29[ 39 ]
+# CHECK: Vreg: %36[ LoopTag*2+12 ]
+# CHECK: Vreg: %12[ 26 ]
+# CHECK: Instr: S_BRANCH %bb.5
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %64[ LoopTag+2 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %14[ 17 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+10 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ LoopTag+2 ]
+# CHECK: Vreg: %25[ LoopTag+5 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %65[ LoopTag*2+11 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %27[ LoopTag+3 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %29[ 38 ]
+# CHECK: Vreg: %36[ LoopTag*2+11 ]
+# CHECK: Vreg: %12[ 25 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 40 ]
+# CHECK: Vreg: %64[ LoopTag+2 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %14[ 17 ]
+# CHECK: Vreg: %35[ 0 ]
+# CHECK: Vreg: %23[ LoopTag*2+10 ]
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %44[ LoopTag+2 ]
+# CHECK: Vreg: %25[ LoopTag+5 ]
+# CHECK: Vreg: %13[ 9 ]
+# CHECK: Vreg: %65[ LoopTag*2+11 ]
+# CHECK: Vreg: %1[ 31 ]
+# CHECK: Vreg: %27[ LoopTag+3 ]
+# CHECK: Vreg: %15[ 1 ]
+# CHECK: Vreg: %29[ 38 ]
+# CHECK: Vreg: %36[ LoopTag*2+11 ]
+# CHECK: Vreg: %12[ 25 ]
+# CHECK: --- MBB_5 ---
+# CHECK: Instr: SI_END_CF killed %33, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 47 ]
+# CHECK: Vreg: %64[ 1 ]
+# CHECK: Vreg: %33[ 0 ]
+# CHECK: Vreg: %14[ 24 ]
+# CHECK: Vreg: %23[ LoopTag+9 ]
+# CHECK: Vreg: %37[ LoopTag+11 ]
+# CHECK: Vreg: %44[ 1 ]
+# CHECK: Vreg: %25[ 4 ]
+# CHECK: Vreg: %13[ 16 ]
+# CHECK: Vreg: %65[ LoopTag+10 ]
+# CHECK: Vreg: %1[ 3 ]
+# CHECK: Vreg: %27[ 2 ]
+# CHECK: Vreg: %15[ 8 ]
+# CHECK: Vreg: %29[ LoopTag+10 ]
+# CHECK: Vreg: %36[ LoopTag+10 ]
+# CHECK: Vreg: %12[ 32 ]
+# CHECK: Instr: %30:vgpr_32 = V_SUB_U32_e64 killed %44, killed %64, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 46 ]
+# CHECK: Vreg: %64[ 0 ]
+# CHECK: Vreg: %14[ 23 ]
+# CHECK: Vreg: %23[ LoopTag+8 ]
+# CHECK: Vreg: %37[ LoopTag+10 ]
+# CHECK: Vreg: %44[ 0 ]
+# CHECK: Vreg: %25[ 3 ]
+# CHECK: Vreg: %13[ 15 ]
+# CHECK: Vreg: %65[ LoopTag+9 ]
+# CHECK: Vreg: %1[ 2 ]
+# CHECK: Vreg: %27[ 1 ]
+# CHECK: Vreg: %15[ 7 ]
+# CHECK: Vreg: %29[ LoopTag+9 ]
+# CHECK: Vreg: %36[ LoopTag+9 ]
+# CHECK: Vreg: %12[ 31 ]
+# CHECK: Instr: %28:sreg_32 = S_ADD_I32 killed %27, 1, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 45 ]
+# CHECK: Vreg: %14[ 22 ]
+# CHECK: Vreg: %23[ LoopTag+7 ]
+# CHECK: Vreg: %30[ 4 ]
+# CHECK: Vreg: %37[ LoopTag+9 ]
+# CHECK: Vreg: %25[ 2 ]
+# CHECK: Vreg: %13[ 14 ]
+# CHECK: Vreg: %65[ LoopTag+8 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %27[ 0 ]
+# CHECK: Vreg: %15[ 6 ]
+# CHECK: Vreg: %29[ LoopTag+8 ]
+# CHECK: Vreg: %36[ LoopTag+8 ]
+# CHECK: Vreg: %12[ 30 ]
+# CHECK: Instr: %67:sreg_32 = V_CMP_GE_U32_e64 %28, %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 44 ]
+# CHECK: Vreg: %14[ 21 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+6 ]
+# CHECK: Vreg: %30[ 3 ]
+# CHECK: Vreg: %37[ LoopTag+8 ]
+# CHECK: Vreg: %25[ 1 ]
+# CHECK: Vreg: %13[ 13 ]
+# CHECK: Vreg: %65[ LoopTag+7 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %15[ 5 ]
+# CHECK: Vreg: %29[ LoopTag+7 ]
+# CHECK: Vreg: %36[ LoopTag+7 ]
+# CHECK: Vreg: %12[ 29 ]
+# CHECK: Instr: %26:sreg_32 = SI_IF_BREAK killed %67, killed %25, implicit-def dead $scc
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 43 ]
+# CHECK: Vreg: %14[ 20 ]
+# CHECK: Vreg: %28[ 2 ]
+# CHECK: Vreg: %23[ LoopTag+5 ]
+# CHECK: Vreg: %30[ 2 ]
+# CHECK: Vreg: %37[ LoopTag+7 ]
+# CHECK: Vreg: %25[ 0 ]
+# CHECK: Vreg: %13[ 12 ]
+# CHECK: Vreg: %65[ LoopTag+6 ]
+# CHECK: Vreg: %1[ 34 ]
+# CHECK: Vreg: %15[ 4 ]
+# CHECK: Vreg: %67[ 0 ]
+# CHECK: Vreg: %29[ LoopTag+6 ]
+# CHECK: Vreg: %36[ LoopTag+6 ]
+# CHECK: Vreg: %12[ 28 ]
+# CHECK: Instr: SI_LOOP %26, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 42 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %14[ 19 ]
+# CHECK: Vreg: %28[ 1 ]
+# CHECK: Vreg: %23[ LoopTag+4 ]
+# CHECK: Vreg: %30[ 1 ]
+# CHECK: Vreg: %37[ LoopTag+6 ]
+# CHECK: Vreg: %13[ 11 ]
+# CHECK: Vreg: %65[ LoopTag+5 ]
+# CHECK: Vreg: %1[ 33 ]
+# CHECK: Vreg: %15[ 3 ]
+# CHECK: Vreg: %29[ LoopTag+5 ]
+# CHECK: Vreg: %36[ LoopTag+5 ]
+# CHECK: Vreg: %12[ 27 ]
+# CHECK: Instr: S_BRANCH %bb.6
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %14[ 18 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+3 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+5 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %65[ LoopTag+4 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+4 ]
+# CHECK: Vreg: %36[ LoopTag+4 ]
+# CHECK: Vreg: %12[ 26 ]
+# CHECK: Block End Distances:
+# CHECK: Vreg: %0[ 41 ]
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %14[ 18 ]
+# CHECK: Vreg: %28[ 0 ]
+# CHECK: Vreg: %23[ LoopTag+3 ]
+# CHECK: Vreg: %30[ 0 ]
+# CHECK: Vreg: %37[ LoopTag+5 ]
+# CHECK: Vreg: %13[ 10 ]
+# CHECK: Vreg: %65[ LoopTag+4 ]
+# CHECK: Vreg: %1[ 32 ]
+# CHECK: Vreg: %15[ 2 ]
+# CHECK: Vreg: %29[ LoopTag+4 ]
+# CHECK: Vreg: %36[ LoopTag+4 ]
+# CHECK: Vreg: %12[ 26 ]
+# CHECK: --- MBB_6 ---
+# CHECK: Instr: SI_END_CF killed %26, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %26[ 0 ]
+# CHECK: Vreg: %23[ 2 ]
+# CHECK: Vreg: %37[ 4 ]
+# CHECK: Vreg: %65[ 3 ]
+# CHECK: Vreg: %1[ 1 ]
+# CHECK: Vreg: %29[ 3 ]
+# CHECK: Vreg: %36[ 3 ]
+# CHECK: Instr: %68:vgpr_32 = V_MAX_U32_e64 1, killed %1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %23[ 1 ]
+# CHECK: Vreg: %37[ 3 ]
+# CHECK: Vreg: %65[ 2 ]
+# CHECK: Vreg: %1[ 0 ]
+# CHECK: Vreg: %29[ 2 ]
+# CHECK: Vreg: %36[ 2 ]
+# CHECK: Instr: %69:vgpr_32 = V_ADD_U32_e64 killed %68, killed %23, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %23[ 0 ]
+# CHECK: Vreg: %68[ 0 ]
+# CHECK: Vreg: %37[ 2 ]
+# CHECK: Vreg: %65[ 1 ]
+# CHECK: Vreg: %29[ 1 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Instr: %70:vgpr_32 = V_ADD3_U32_e64 %36, killed %29, %65, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %37[ 1 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %29[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %69[ 3 ]
+# CHECK: Instr: %71:vgpr_32 = V_ADD_U32_e64 killed %65, killed %37, 0, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %37[ 0 ]
+# CHECK: Vreg: %70[ 1 ]
+# CHECK: Vreg: %65[ 0 ]
+# CHECK: Vreg: %36[ 1 ]
+# CHECK: Vreg: %69[ 2 ]
+# CHECK: Instr: %72:vgpr_32 = V_ADD3_U32_e64 killed %71, killed %70, killed %36, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %71[ 0 ]
+# CHECK: Vreg: %70[ 0 ]
+# CHECK: Vreg: %36[ 0 ]
+# CHECK: Vreg: %69[ 1 ]
+# CHECK: Instr: %73:vgpr_32 = V_ADD3_U32_e64 killed %69, killed %72, -1, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %72[ 0 ]
+# CHECK: Vreg: %69[ 0 ]
+# CHECK: Instr: %74:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %73, implicit $exec
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %73[ 0 ]
+# CHECK: Instr: $sgpr0 = COPY killed %74
+# CHECK-NEXT: Next-use distances:
+# CHECK: Vreg: %74[ 0 ]
+# CHECK: Instr: SI_RETURN_TO_EPILOG killed $sgpr0
+# CHECK-NEXT: Next-use distances:
+# CHECK: (no register uses)
+# CHECK: Block End Distances:
+# CHECK: (no registers live at block end)
+# CHECK: === End NextUseAnalysis Results ===
+
+--- |
+  define amdgpu_ps i32 @test9(ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, ptr addrspace(1) %p4, ptr addrspace(1) %p5, i32 %TC1, i32 %TC2, i32 %TC3) {
+  0:
+  %ld1 = load i32, ptr addrspace(1) %p1, align 1
+  br label %1
+  1:
+  %phi.inc1 = phi i32 [ 0, %0 ], [ %inc1, %5 ]
+  %phi1 = phi i32 [ %ld1, %0 ], [ %sub, %5 ]
+  %add1 = add i32 %ld1, %phi.inc1
+  br label %2
+  2:
+  %phi.inc2 = phi i32 [ 0, %1 ], [ %inc2, %4 ]
+  %phi2 = phi i32 [ 13, %1 ], [ %mul, %4 ]
+  %ld2 = load i32, ptr addrspace(1) %p2, align 1
+  %add2 = add i32 %ld2, %phi.inc2
+  store i32 %add2, ptr addrspace(1) %p4, align 1
+  br label %3
+  3:
+  %phi.inc3 = phi i32 [ 0, %2 ], [ %inc3, %3 ]
+  %inc3 = add i32 %phi.inc3, 3
+  %sub = sub i32 %ld2, %inc3
+  %ld3 = load i32, ptr addrspace(1) %p3, align 1
+  %add3 = add i32 %ld3, %inc3
+  store i32 %add3, ptr addrspace(1) %p5, align 1
+  %cond3 = icmp ult i32 %inc3, %TC1
+  br i1 %cond3, label %3, label %4
+  4:
+  %mul = mul i32 %phi1, %add3
+  %inc2 = add i32 %phi.inc2, 2
+  %cond2 = icmp ult i32 %inc2, %TC2
+  br i1 %cond2, label %2, label %5
+  5:
+  %add4 = add i32 %phi2, %phi1
+  %add5 = add i32 %add3, %add4
+  %inc1 = add i32 %phi.inc1, 1
+  %cond1 = icmp ult i32 %inc1, %TC1
+  br i1 %cond1, label %1, label %6
+  6:
+  %add6 = add i32 %add3, %mul
+  %add7 = add i32 %add6, %add5
+  %add8 = add i32 %add7, %phi2
+  %add9 = add i32 %add8, %add1
+  ret i32 %add9
+  }
+...
+
+---
+name:            test9
+alignment:       1
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+noPhis:          false
+isSSA:           true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    successors: %bb.1(0x80000000)
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11
+  
+    %45:vgpr_32 = COPY killed $vgpr11
+    %44:vgpr_32 = COPY killed $vgpr10
+    %43:vgpr_32 = COPY killed $vgpr9
+    %42:vgpr_32 = COPY killed $vgpr8
+    %41:vgpr_32 = COPY killed $vgpr7
+    %40:vgpr_32 = COPY killed $vgpr6
+    %39:vgpr_32 = COPY killed $vgpr5
+    %38:vgpr_32 = COPY killed $vgpr4
+    %37:vgpr_32 = COPY killed $vgpr3
+    %36:vgpr_32 = COPY killed $vgpr2
+    %35:vgpr_32 = COPY killed $vgpr1
+    %34:vgpr_32 = COPY killed $vgpr0
+    %104:vreg_64 = REG_SEQUENCE killed %42, %subreg.sub0, killed %43, %subreg.sub1
+    %103:vreg_64 = REG_SEQUENCE killed %40, %subreg.sub0, killed %41, %subreg.sub1
+    %102:vreg_64 = REG_SEQUENCE killed %38, %subreg.sub0, killed %39, %subreg.sub1
+    %101:vreg_64 = REG_SEQUENCE killed %36, %subreg.sub0, killed %37, %subreg.sub1
+    %100:vreg_64 = REG_SEQUENCE killed %34, %subreg.sub0, killed %35, %subreg.sub1
+    %56:vgpr_32 = GLOBAL_LOAD_UBYTE %100, 0, 0, implicit $exec :: (load (s8) from %ir.p1, addrspace 1)
+    %58:vgpr_32 = GLOBAL_LOAD_UBYTE %100, 1, 0, implicit $exec :: (load (s8) from %ir.p1 + 1, addrspace 1)
+    %61:vgpr_32 = V_LSHL_OR_B32_e64 killed %58, 8, killed %56, implicit $exec
+    %62:vgpr_32 = GLOBAL_LOAD_UBYTE %100, 2, 0, implicit $exec :: (load (s8) from %ir.p1 + 2, addrspace 1)
+    %64:vgpr_32 = GLOBAL_LOAD_UBYTE killed %100, 3, 0, implicit $exec :: (load (s8) from %ir.p1 + 3, addrspace 1)
+    %66:vgpr_32 = V_LSHL_OR_B32_e64 killed %64, 8, killed %62, implicit $exec
+    %0:vgpr_32 = V_LSHL_OR_B32_e64 killed %66, 16, killed %61, implicit $exec
+    %50:sreg_32 = S_MOV_B32 0
+  
+  bb.1:
+    successors: %bb.2(0x80000000)
+  
+    %1:sreg_32 = PHI %50, %bb.0, %28, %bb.5
+    %2:sreg_32 = PHI %50, %bb.0, %27, %bb.5
+    %3:vgpr_32 = PHI %0, %bb.0, %26, %bb.5
+    %69:vgpr_32 = V_MOV_B32_e32 13, implicit $exec
+  
+  bb.2:
+    successors: %bb.3(0x80000000)
+  
+    %4:sreg_32 = PHI %50, %bb.1, %19, %bb.4
+    %5:sreg_32 = PHI %50, %bb.1, %18, %bb.4
+    %6:vgpr_32 = PHI %69, %bb.1, %17, %bb.4
+    %71:vgpr_32 = GLOBAL_LOAD_UBYTE %101, 0, 0, implicit $exec :: (load (s8) from %ir.p2, addrspace 1)
+    %72:vgpr_32 = GLOBAL_LOAD_UBYTE %101, 1, 0, implicit $exec :: (load (s8) from %ir.p2 + 1, addrspace 1)
+    %74:vgpr_32 = V_LSHL_OR_B32_e64 killed %72, 8, killed %71, implicit $exec
+    %75:vgpr_32 = GLOBAL_LOAD_UBYTE %101, 2, 0, implicit $exec :: (load (s8) from %ir.p2 + 2, addrspace 1)
+    %76:vgpr_32 = GLOBAL_LOAD_UBYTE %101, 3, 0, implicit $exec :: (load (s8) from %ir.p2 + 3, addrspace 1)
+    %77:vgpr_32 = V_LSHL_OR_B32_e64 killed %76, 8, killed %75, implicit $exec
+    %7:vgpr_32 = V_LSHL_OR_B32_e64 killed %77, 16, killed %74, implicit $exec
+    %78:vgpr_32 = V_ADD_U32_e64 %5, %7, 0, implicit $exec
+    GLOBAL_STORE_BYTE_D16_HI %103, %78, 2, 0, implicit $exec :: (store (s8) into %ir.p4 + 2, addrspace 1)
+    GLOBAL_STORE_BYTE %103, %78, 0, 0, implicit $exec :: (store (s8) into %ir.p4, addrspace 1)
+    %79:vgpr_32 = V_LSHRREV_B32_e64 24, %78, implicit $exec
+    GLOBAL_STORE_BYTE %103, killed %79, 3, 0, implicit $exec :: (store (s8) into %ir.p4 + 3, addrspace 1)
+    %80:vgpr_32 = V_LSHRREV_B32_e64 8, killed %78, implicit $exec
+    GLOBAL_STORE_BYTE %103, killed %80, 1, 0, implicit $exec :: (store (s8) into %ir.p4 + 1, addrspace 1)
+    %70:sreg_32 = S_MOV_B32 0
+  
+  bb.3:
+    successors: %bb.4(0x04000000), %bb.3(0x7c000000)
+  
+    %8:sreg_32 = PHI %70, %bb.2, %12, %bb.3
+    %9:sreg_32 = PHI %70, %bb.2, %10, %bb.3
+    %10:sreg_32 = S_ADD_I32 killed %9, 3, implicit-def dead $scc
+    %81:vgpr_32 = GLOBAL_LOAD_UBYTE %102, 0, 0, implicit $exec :: (load (s8) from %ir.p3, addrspace 1)
+    %82:vgpr_32 = GLOBAL_LOAD_UBYTE %102, 1, 0, implicit $exec :: (load (s8) from %ir.p3 + 1, addrspace 1)
+    %83:vgpr_32 = V_LSHL_OR_B32_e64 killed %82, 8, killed %81, implicit $exec
+    %84:vgpr_32 = GLOBAL_LOAD_UBYTE %102, 2, 0, implicit $exec :: (load (s8) from %ir.p3 + 2, addrspace 1)
+    %85:vgpr_32 = GLOBAL_LOAD_UBYTE %102, 3, 0, implicit $exec :: (load (s8) from %ir.p3 + 3, addrspace 1)
+    %86:vgpr_32 = V_LSHL_OR_B32_e64 killed %85, 8, killed %84, implicit $exec
+    %11:vgpr_32 = V_LSHL_OR_B32_e64 killed %86, 16, killed %83, implicit $exec
+    %87:vgpr_32 = V_ADD_U32_e64 %10, %11, 0, implicit $exec
+    GLOBAL_STORE_BYTE_D16_HI %104, %87, 2, 0, implicit $exec :: (store (s8) into %ir.p5 + 2, addrspace 1)
+    GLOBAL_STORE_BYTE %104, %87, 0, 0, implicit $exec :: (store (s8) into %ir.p5, addrspace 1)
+    %88:vgpr_32 = V_LSHRREV_B32_e64 24, %87, implicit $exec
+    GLOBAL_STORE_BYTE %104, killed %88, 3, 0, implicit $exec :: (store (s8) into %ir.p5 + 3, addrspace 1)
+    %89:vgpr_32 = V_LSHRREV_B32_e64 8, killed %87, implicit $exec
+    GLOBAL_STORE_BYTE %104, killed %89, 1, 0, implicit $exec :: (store (s8) into %ir.p5 + 1, addrspace 1)
+    %90:sreg_32 = V_CMP_GE_U32_e64 %10, %44, implicit $exec
+    %12:sreg_32 = SI_IF_BREAK killed %90, killed %8, implicit-def dead $scc
+    %105:vgpr_32 = COPY %10, implicit $exec
+    SI_LOOP %12, %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.4
+  
+  bb.4:
+    successors: %bb.5(0x04000000), %bb.2(0x7c000000)
+  
+    SI_END_CF killed %12, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %16:vgpr_32 = V_ADD_U32_e64 killed %11, %105, 0, implicit $exec
+    %17:vgpr_32 = V_MUL_LO_U32_e64 %3, %16, implicit $exec
+    %18:sreg_32 = S_ADD_I32 killed %5, 2, implicit-def dead $scc
+    %91:sreg_32 = V_CMP_GE_U32_e64 %18, %45, implicit $exec
+    %19:sreg_32 = SI_IF_BREAK killed %91, killed %4, implicit-def dead $scc
+    SI_LOOP %19, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.5
+  
+  bb.5:
+    successors: %bb.6(0x04000000), %bb.1(0x7c000000)
+  
+    SI_END_CF killed %19, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %26:vgpr_32 = V_SUB_U32_e64 killed %7, killed %105, 0, implicit $exec
+    %27:sreg_32 = S_ADD_I32 killed %2, 1, implicit-def dead $scc
+    %92:sreg_32 = V_CMP_GE_U32_e64 %27, %44, implicit $exec
+    %28:sreg_32 = SI_IF_BREAK killed %92, killed %1, implicit-def dead $scc
+    SI_LOOP %28, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    S_BRANCH %bb.6
+  
+  bb.6:
+    SI_END_CF killed %28, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+    %93:vgpr_32 = V_MAX_U32_e64 1, killed %44, implicit $exec
+    %94:vgpr_32 = V_ADD_U32_e64 killed %93, killed %0, 0, implicit $exec
+    %95:vgpr_32 = V_ADD3_U32_e64 %6, killed %3, %16, implicit $exec
+    %96:vgpr_32 = V_ADD_U32_e64 killed %16, killed %17, 0, implicit $exec
+    %97:vgpr_32 = V_ADD3_U32_e64 killed %96, killed %95, killed %6, implicit $exec
+    %98:vgpr_32 = V_ADD3_U32_e64 killed %94, killed %97, -1, implicit $exec
+    %99:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %98, implicit $exec
+    $sgpr0 = COPY killed %99
+    SI_RETURN_TO_EPILOG killed $sgpr0
+...
+---
diff --git a/llvm/unittests/Target/AMDGPU/CMakeLists.txt b/llvm/unittests/Target/AMDGPU/CMakeLists.txt
index d6cbaf3f3fb5d..5473fbd8e3ffe 100644
--- a/llvm/unittests/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/unittests/Target/AMDGPU/CMakeLists.txt
@@ -24,5 +24,6 @@ add_llvm_target_unittest(AMDGPUTests
   DwarfRegMappings.cpp
   ExecMayBeModifiedBeforeAnyUse.cpp
   LiveRegUnits.cpp
+  NextUseAnalysisTest.cpp
   PALMetadata.cpp
   )
diff --git a/llvm/unittests/Target/AMDGPU/NextUseAnalysisTest.cpp b/llvm/unittests/Target/AMDGPU/NextUseAnalysisTest.cpp
new file mode 100644
index 0000000000000..cc8e42510db26
--- /dev/null
+++ b/llvm/unittests/Target/AMDGPU/NextUseAnalysisTest.cpp
@@ -0,0 +1,694 @@
+//===- llvm/unittests/Target/AMDGPU/NextUseAnalysisTest.cpp ---------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// ============================================================================
+// NEXTUSE ANALYSIS UNIT TESTING STRATEGY
+// ============================================================================
+//
+// TEST FRAMEWORK WORKFLOW:
+// This test suite parses existing LIT tests from
+// llvm/test/CodeGen/AMDGPU/NextUseAnalysis/ and runs NextUseAnalysis once per
+// MachineFunction, then queries next-use distances for each instruction in each
+// block, using the parsed CHECK patterns as expected results.
+//
+// COVERAGE EVICTION CONCEPT:
+// Coverage eviction occurs when a full register use eliminates sub-register
+// uses of the same virtual register because the full register use covers all
+// sub-register lanes. This happens during the insert() operation when uses are
+// stored.
+//
+// REGISTER USE ORDERING AND CONTROL FLOW SEMANTICS:
+// Different LaneMask (full register/sub-register) uses of the same register are
+// stored in distance-increasing order. This ordering reveals the control flow
+// structure:
+//
+// 1. FullRegUse -> SubRegUse: Uses converged at predecessor from independent
+// paths.
+//    Both are reachable through different branches. Without coverage eviction,
+//    this indicates paths diverged and merged at this block.
+//
+// 2. SubRegUse -> FullRegUse: Sub-register use precedes full register use in
+//    linear or fully post-dominated control flow. The full register use would
+//    have evicted sub-register uses if they were on the same path.
+//
+// SPILLING DECISION OPTIMIZATION:
+// For optimal spilling decisions, we need the CLOSEST distance among all valid
+// paths. Without branch prediction or PGO data, we treat all execution paths as
+// equally likely, so the optimal choice is always the nearest next-use.
+//
+// FULL vs SUB-REGISTER PRECEDENCE LOGIC:
+// - If full register use has closer distance than sub-register use:
+//   Use full register distance for ALL sub-register queries of that VReg
+// - If sub-register use is closer: Use sub-register distance
+// - Rationale: Full register use implies ALL sub-register components are used,
+//   so it provides the true "next use" for any sub-register query
+//
+// This strategy ensures unit tests reflect real compiler optimization decisions
+// while validating the correctness of the NextUseAnalysis algorithm.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPUTargetMachine.h"
+#include "AMDGPUUnitTests.h"
+#include "GCNSubtarget.h"
+#include "llvm/CodeGen/MIRParser/MIRParser.h"
+#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/Register.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/IR/LegacyPassManager.h"
+#include "llvm/IR/Module.h"
+#include "llvm/InitializePasses.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/FileSystem.h"
+#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/SourceMgr.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Support/Timer.h"
+#include "gtest/gtest.h"
+#include <filesystem>
+#include <fstream>
+#include <regex>
+
+#include "AMDGPUNextUseAnalysis.h"
+
+using namespace llvm;
+
+namespace {
+
+// Helper wrapper to store analysis results for unit testing
+class NextUseAnalysisTestWrapper : public AMDGPUNextUseAnalysisWrapper {
+public:
+  static std::unique_ptr<NextUseResult> Captured;
+
+  bool runOnMachineFunction(MachineFunction &MF) override {
+    bool Changed = AMDGPUNextUseAnalysisWrapper::runOnMachineFunction(MF);
+    // Store the result for unit test access
+    Captured = std::make_unique<NextUseResult>(std::move(getNU()));
+    return Changed;
+  }
+};
+
+std::unique_ptr<NextUseResult> NextUseAnalysisTestWrapper::Captured;
+
+
+class NextUseAnalysisTestBase : public testing::Test {
+protected:
+  std::unique_ptr<LLVMContext> Ctx;
+  std::unique_ptr<Module> M;
+  std::unique_ptr<const GCNTargetMachine> TM;
+  MachineModuleInfo *MMI = nullptr;
+
+  // Add TRI and MRI as class members - initialized from first MachineFunction
+  const SIRegisterInfo *TRI = nullptr;
+  const MachineRegisterInfo *MRI = nullptr;
+
+  // Helper function to convert MachineInstr to string representation
+  std::string machineInstrToString(const MachineInstr &MI) {
+    std::string Str;
+    raw_string_ostream OS(Str);
+    MI.print(OS, /*IsStandalone=*/false, /*SkipOpers=*/false,
+             /*SkipDebugLoc=*/true, /*AddNewLine=*/false);
+    return OS.str();
+  }
+
+  inline unsigned getSubRegIndexForLaneMask(LaneBitmask Mask,
+                                            const SIRegisterInfo *TRI) {
+    for (unsigned Idx = 1; Idx < TRI->getNumSubRegIndices(); ++Idx) {
+      if (TRI->getSubRegIndexLaneMask(Idx) == Mask)
+        return Idx;
+    }
+    return AMDGPU::NoRegister;
+  }
+
+  // Helper function to map sub-register names to LaneBitmask values using LLVM
+  // API
+  LaneBitmask getSubRegLaneMask(const std::string &subRegName, Register VReg,
+                                const SIRegisterInfo *TRI,
+                                const MachineRegisterInfo *MRI) {
+    if (subRegName.empty()) {
+      return MRI->getMaxLaneMaskForVReg(VReg); // Proper full register mask
+    }
+
+    for (unsigned i = 1, e = TRI->getNumSubRegIndices(); i < e; ++i) {
+      const char *Name = TRI->getSubRegIndexName(i);
+      if (Name && subRegName == Name) {
+        return TRI->getSubRegIndexLaneMask(i);
+      }
+    }
+
+    // If unknown sub-register, default to full register
+    return MRI->getMaxLaneMaskForVReg(VReg);
+  }
+
+  // Helper function to parse expected distances from CHECK patterns
+  llvm::DenseMap<VRegMaskPair, unsigned>
+  parseExpectedDistances(const std::vector<std::string> &checkPatterns,
+                         const std::string &instrString,
+                         const SIRegisterInfo *TRI,
+                         const MachineRegisterInfo *MRI) {
+    llvm::DenseMap<VRegMaskPair, unsigned> expectedDistances;
+
+    // Clean up the instruction string - remove newlines and extra spaces
+    std::string cleanInstrString = instrString;
+    cleanInstrString.erase(
+        std::remove(cleanInstrString.begin(), cleanInstrString.end(), '\n'),
+        cleanInstrString.end());
+
+    // Find the CHECK pattern that matches this instruction
+    for (size_t i = 0; i < checkPatterns.size(); ++i) {
+      const std::string &pattern = checkPatterns[i];
+
+      // Look for instruction patterns like "CHECK: Instr: %9:vgpr_32 = COPY
+      // killed $vgpr1"
+      if (pattern.find("CHECK: Instr:") != std::string::npos) {
+        // Extract the instruction part after "Instr: "
+        size_t instrPos = pattern.find("Instr: ") + 7;
+        std::string checkInstr = pattern.substr(instrPos);
+
+        // Matching: compare the actual instruction content
+        // Remove leading/trailing whitespace from both
+        checkInstr =
+            std::regex_replace(checkInstr, std::regex("^\\s+|\\s+$"), "");
+        std::string trimmedInstrString =
+            std::regex_replace(cleanInstrString, std::regex("^\\s+|\\s+$"), "");
+
+        // Extract the core instruction (everything after the first space)
+        size_t firstSpace = checkInstr.find(' ');
+        size_t instrFirstSpace = trimmedInstrString.find(' ');
+
+        if (firstSpace != std::string::npos &&
+            instrFirstSpace != std::string::npos) {
+          std::string checkCore = checkInstr.substr(firstSpace + 1);
+          std::string instrCore =
+              trimmedInstrString.substr(instrFirstSpace + 1);
+
+          // Match if the core instruction parts are identical
+          if (checkCore == instrCore) {
+            // Also verify the destination register matches
+            std::regex destRegex(R"(^(%\d+:[a-zA-Z_0-9]+)\s*=)");
+            std::smatch checkMatch, instrMatch;
+
+            if (std::regex_search(checkInstr, checkMatch, destRegex) &&
+                std::regex_search(trimmedInstrString, instrMatch, destRegex) &&
+                checkMatch[1].str() == instrMatch[1].str()) {
+
+              // Found exact match, look for subsequent Vreg distance patterns
+              // Track full register uses by virtual register to apply precedence
+              llvm::DenseMap<Register, unsigned> fullRegDistances;
+              
+              for (size_t j = i + 1; j < checkPatterns.size(); ++j) {
+                const std::string &distPattern = checkPatterns[j];
+
+                // Stop if we hit another instruction or non-Vreg pattern
+                if (distPattern.find("CHECK: Instr:") != std::string::npos ||
+                    distPattern.find("CHECK: ---") != std::string::npos ||
+                    distPattern.find("CHECK-LABEL:") != std::string::npos ||
+                    distPattern.find("CHECK: Block End Distances:") !=
+                        std::string::npos) {
+                  break;
+                }
+
+                // Enhanced regex to capture sub-register patterns like "CHECK:
+                // Vreg: %15:sub0[ 22 ]" Group 1: register number, Group 2: full
+                // sub-register part (optional), Group 3: sub-register name,
+                // Group 4: distance
+                std::regex vregRegex(
+                    R"(CHECK:\s*Vreg:\s*%(\d+)(:([a-zA-Z_0-9]+))?\[\s*(\d+)\s*\])");
+                std::smatch vregMatch;
+
+                if (std::regex_search(distPattern, vregMatch, vregRegex) &&
+                    vregMatch.size() >= 5) {
+                  unsigned regNum = std::stoul(vregMatch[1].str());
+                  std::string subRegName =
+                      vregMatch[3].str(); // May be empty for full register
+                  unsigned distance = std::stoul(vregMatch[4].str());                  Register VReg = Register::index2VirtReg(regNum);
+                  LaneBitmask mask = getSubRegLaneMask(subRegName, VReg, TRI, MRI);
+                  
+                  // Check if this is a full register use
+                  if (subRegName.empty() || mask == MRI->getMaxLaneMaskForVReg(VReg)) {
+                    // This is a full register use - record it for precedence
+                    fullRegDistances[VReg] = distance;
+                    VRegMaskPair VMP(VReg, mask);
+                    expectedDistances[VMP] = distance;
+                  } else {
+                    // This is a sub-register use  
+                    // Check if we already have a full register use for this VReg with closer distance
+                    auto FullIt = fullRegDistances.find(VReg);
+                    if (FullIt != fullRegDistances.end() && FullIt->second < distance) {
+                      // Full register use exists and is closer - use its distance
+                      VRegMaskPair VMP(VReg, mask);
+                      expectedDistances[VMP] = FullIt->second;
+                    } else {
+                      // No full register use or sub-register is closer - use sub-register distance
+                      VRegMaskPair VMP(VReg, mask);
+                      expectedDistances[VMP] = distance;
+                    }
+                  }
+                }
+              }
+              break;
+            }
+          }
+        }
+      }
+    }
+
+    return expectedDistances;
+  }
+
+  void SetUp() override {
+    // Only enable debug output if environment variable is set
+    const char *debugEnv = std::getenv("AMDGPU_NUA_DEBUG");
+    if (debugEnv && std::string(debugEnv) == "1") {
+      DebugFlag = true;
+      setCurrentDebugType("amdgpu-next-use");
+    }
+    Ctx = std::make_unique<LLVMContext>();
+    TM = createAMDGPUTargetMachine("amdgcn-amd-", "gfx1200", "");
+    if (!TM) {
+      GTEST_SKIP() << "AMDGPU target not available";
+    }
+    static bool InitializedOnce = false;
+    if (!InitializedOnce) {
+      // Initialize required passes
+      PassRegistry &PR = *PassRegistry::getPassRegistry();
+      initializeMachineModuleInfoWrapperPassPass(PR);
+      initializeMachineDominatorTreeWrapperPassPass(PR);
+      initializeSlotIndexesWrapperPassPass(PR);
+      initializeMachineLoopInfoWrapperPassPass(PR);
+      InitializedOnce = true;
+    }
+  }
+
+  // Helper to find all .mir files in a directory
+  std::vector<std::string> findMirFiles(const std::string& dirPath) {
+    std::vector<std::string> mirFiles;
+    
+    if (!std::filesystem::exists(dirPath)) {
+      return mirFiles;
+    }
+    
+    for (const auto& entry : std::filesystem::directory_iterator(dirPath)) {
+      if (entry.is_regular_file() && entry.path().extension() == ".mir") {
+        mirFiles.push_back(entry.path().filename().string());
+      }
+    }
+    
+    std::sort(mirFiles.begin(), mirFiles.end());
+    return mirFiles;
+  }
+  
+  // Helper to parse CHECK patterns from file comments
+  std::vector<std::string> parseCheckPatterns(const std::string& filePath) {
+    std::vector<std::string> patterns;
+    std::ifstream file(filePath);
+    std::string line;
+    
+    while (std::getline(file, line)) {
+      if (line.find("# CHECK") == 0) {
+        patterns.push_back(line);
+      }
+    }
+    
+    return patterns;
+  }
+
+  std::unique_ptr<Module> parseMIRString(const std::string &MIRContent,
+                                         LLVMContext &Ctx,
+                                         const TargetMachine &TM,
+                                         legacy::PassManager &PM) {
+    // 1) Add MMI wrapper first, get a handle to its MMI
+    auto *MMIWP = new MachineModuleInfoWrapperPass(&TM);
+    PM.add(MMIWP);
+    MMI = &MMIWP->getMMI();
+
+    // 2) Parse MIR from string
+    auto MemBuffer = MemoryBuffer::getMemBuffer(MIRContent, "inline_mir");
+
+    SMDiagnostic Err;
+    auto MIRParser = createMIRParser(std::move(MemBuffer), Ctx);
+    if (!MIRParser) {
+      return nullptr;
+    }
+
+    auto M = MIRParser->parseIRModule();
+    if (!M) {
+      return nullptr;
+    }
+
+    M->setTargetTriple(TM.getTargetTriple());
+    M->setDataLayout(TM.createDataLayout());
+    MMIWP->doInitialization(*M);
+
+    if (MIRParser->parseMachineFunctions(*M, *MMI))
+      return nullptr;
+    return M;
+  }
+
+  std::unique_ptr<Module> parseMIRFile(const std::string &FilePath,
+                                       LLVMContext &Ctx,
+                                       const TargetMachine &TM,
+                                       legacy::PassManager &PM) {
+    // Read file content
+    ErrorOr<std::unique_ptr<MemoryBuffer>> FileBuffer =
+        MemoryBuffer::getFile(FilePath);
+    if (!FileBuffer) {
+      return nullptr;
+    }
+
+    // Reuse parseMIRString with file content
+    return parseMIRString(FileBuffer.get()->getBuffer().str(), Ctx, TM, PM);
+  }
+
+  NextUseResult &runNextUseAnalysis(MachineFunction &MF,
+                                    legacy::PassManager &PM) {
+    // Add our analysis pass at pre-emit stage (after most optimizations)
+    PM.add(new NextUseAnalysisTestWrapper());
+
+    PM.run(const_cast<Module &>(*MMI->getModule()));
+
+    // Get the analysis result from the wrapper that was run
+    return *NextUseAnalysisTestWrapper::Captured;
+  }
+};
+
+// Parameterized test for all .mir files
+class NextUseAnalysisParameterizedTest : public NextUseAnalysisTestBase, 
+                                         public testing::WithParamInterface<std::string> {
+};
+
+// Allow uninstantiated test when test files are not available
+GTEST_ALLOW_UNINSTANTIATED_PARAMETERIZED_TEST(NextUseAnalysisParameterizedTest);
+
+std::string getTestDirectory() {
+  // First try environment variable
+  const char *testDirEnv = std::getenv("AMDGPU_NUA_TEST_DIR");
+  if (testDirEnv) {
+    return std::string(testDirEnv);
+  }
+
+  // Try to find relative to unit test binary
+  // Unit tests are typically in build/unittests/Target/AMDGPU/
+  // Source tests are in llvm/test/CodeGen/AMDGPU/NextUseAnalysis/
+  std::filesystem::path currentPath = std::filesystem::current_path();
+
+  // Look for the source tree from build directory
+  std::vector<std::string> possiblePaths = {
+      "../../../llvm/test/CodeGen/AMDGPU/NextUseAnalysis",
+      "../../../../llvm/test/CodeGen/AMDGPU/NextUseAnalysis",
+      "../../../../../llvm/test/CodeGen/AMDGPU/NextUseAnalysis"};
+
+  for (const auto &path : possiblePaths) {
+    std::filesystem::path testPath = currentPath / path;
+    if (std::filesystem::exists(testPath)) {
+      return testPath.string();
+    }
+  }
+
+  return ""; // Not found
+}
+
+// Generate test parameters from available .mir files
+std::vector<std::string> getMirFiles() {
+  const char *testFileEnv = std::getenv("AMDGPU_NUA_TEST_FILE");
+
+  // If specific file is requested, test only that
+  if (testFileEnv) {
+    return {std::string(testFileEnv)};
+  }
+
+  // Use the same directory resolution as the test
+  std::string testDir = getTestDirectory();
+
+  // If no test directory found, return empty vector
+  if (testDir.empty()) {
+    return {};
+  }
+
+  // Find all .mir files in the directory
+  std::vector<std::string> mirFiles;
+
+  for (const auto &entry : std::filesystem::directory_iterator(testDir)) {
+    if (entry.is_regular_file() && entry.path().extension() == ".mir") {
+      mirFiles.push_back(entry.path().filename().string());
+    }
+  }
+
+  std::sort(mirFiles.begin(), mirFiles.end());
+  return mirFiles;
+}
+
+TEST_P(NextUseAnalysisParameterizedTest, ProcessMirFile) {
+  std::string mirFileName = GetParam();
+  
+  // Get test directory from environment or use default
+  std::string testDir = getTestDirectory();
+
+  if (testDir.empty()) {
+    GTEST_SKIP()
+        << "NextUseAnalysis test directory not found. "
+        << "Set AMDGPU_NUA_TEST_DIR environment variable or ensure "
+        << "tests are run from build directory with source tree available.";
+  }
+
+  std::string fullPath = testDir + "/" + mirFileName;
+  
+  // Parse CHECK patterns from the file
+  auto checkPatterns = parseCheckPatterns(fullPath);
+  ASSERT_FALSE(checkPatterns.empty()) << "No CHECK patterns found in " << mirFileName;
+  
+  LLVMContext Ctx;
+  legacy::PassManager PM;
+  auto Module = parseMIRFile(fullPath, Ctx, *TM, PM);
+  ASSERT_TRUE(Module) << "Failed to parse MIR file: " << mirFileName;
+
+  for (auto &F : Module->functions()) {
+    MachineFunction *MF = MMI->getMachineFunction(F);
+    ASSERT_TRUE(MF) << "MachineFunction not found";
+
+    // Initialize TRI and MRI from first MachineFunction if not already done
+    if (!TRI) {
+      TRI = MF->getSubtarget<GCNSubtarget>().getRegisterInfo();
+      MRI = &MF->getRegInfo();
+    }
+
+    // Run NextUseAnalysis
+    NextUseResult &NU = runNextUseAnalysis(*MF, PM);
+
+    for (auto &MBB : *MF) {
+      for (auto &MI : MBB) {
+        // Convert MachineInstr to string for pattern matching
+        std::string instrString = machineInstrToString(MI);
+
+        // Parse expected distances from CHECK patterns for this instruction
+        auto expectedDistances =
+            parseExpectedDistances(checkPatterns, instrString, TRI, MRI);
+
+        // Validate each expected distance
+        for (const auto &expected : expectedDistances) {
+          VRegMaskPair VMP = expected.first;
+          unsigned expectedDistance = expected.second;
+
+          unsigned actualDistance =
+              NU.getNextUseDistance(MI.getIterator(), VMP);
+
+          EXPECT_EQ(actualDistance, expectedDistance)
+              << "Distance mismatch for register "
+              << printReg(VMP.getVReg(), TRI,
+                          getSubRegIndexForLaneMask(VMP.getLaneMask(), TRI),
+                          MRI)
+              << " in instruction: " << instrString.substr(0, 50) << "..."
+              << " Expected: " << expectedDistance
+              << " Actual: " << actualDistance;
+        }
+      }
+    }
+  }
+}
+
+// Test getSortedSubregUses API with minimal SSA MIR pattern
+TEST_F(NextUseAnalysisParameterizedTest, GetSortedSubregUsesDistanceOrdering) {
+  // Minimal MIR pattern based on real SSA spiller case:
+  // Large register with sub-register accesses at different distances
+  // sub0 is accessed last (furthest distance) and should appear first in sorted
+  // result
+  const char *MIR = R"MIR(
+--- |
+  target triple = "amdgcn"
+  define void @getSortedSubregUses_test() { ret void }
+
+---
+name: getSortedSubregUses_test
+body: |
+  bb.0:
+    ; Create large register with all 32 sub-registers
+    %0:vreg_1024 = IMPLICIT_DEF
+
+    ; Query point: %0 is now live and has upcoming sub-register uses
+    %1:vgpr_32 = COPY $vgpr0      ; Query getSortedSubregUses here
+
+    ; Multiple sub-register accesses in reverse order (sub31 -> sub0)
+    ; This creates different next-use distances for each sub-register
+    %10:vgpr_32 = COPY %0.sub31   ; Distance = 1 (closest)
+    %11:vgpr_32 = COPY %0.sub30   ; Distance = 2
+    %12:vgpr_32 = COPY %0.sub29   ; Distance = 3
+    %13:vgpr_32 = COPY %0.sub28   ; Distance = 4
+
+    ; Create REG_SEQUENCE with some of the copied values
+    %20:vreg_128 = REG_SEQUENCE %13, %subreg.sub0, %12, %subreg.sub1, %11, %subreg.sub2, %10, %subreg.sub3
+
+    ; Continue with more sub-register accesses
+    %14:vgpr_32 = COPY %0.sub3    ; Distance = 6
+    %15:vgpr_32 = COPY %0.sub2    ; Distance = 7
+    %16:vgpr_32 = COPY %0.sub1    ; Distance = 8
+    %17:vgpr_32 = COPY %0.sub0    ; Distance = 9 (furthest)
+
+    ; Use the copied sub-registers
+    %21:vreg_128 = REG_SEQUENCE %17, %subreg.sub0, %16, %subreg.sub1, %15, %subreg.sub2, %14, %subreg.sub3
+
+    ; Store to make them live
+    GLOBAL_STORE_DWORDX4 undef %30:vreg_64, %20, 0, 0, implicit $exec :: (store (s128), addrspace 1)
+    GLOBAL_STORE_DWORDX4 undef %31:vreg_64, %21, 0, 0, implicit $exec :: (store (s128), addrspace 1)
+
+...
+)MIR";
+
+  // Parse MIR from string using the new helper function
+  LLVMContext Ctx;
+  legacy::PassManager PM;
+  auto Module = parseMIRString(MIR, Ctx, *TM, PM);
+  ASSERT_TRUE(Module) << "Failed to parse MIR";
+
+  // Get the MachineFunction
+  auto &F = *Module->functions().begin();
+  MachineFunction *MF = MMI->getMachineFunction(F);
+  ASSERT_TRUE(MF) << "MachineFunction not found";
+
+  // Initialize TRI and MRI if not already done
+  if (!TRI) {
+    TRI = MF->getSubtarget<GCNSubtarget>().getRegisterInfo();
+    MRI = &MF->getRegInfo();
+  }
+
+  // Run NextUseAnalysis using the existing method
+  NextUseResult &NU = runNextUseAnalysis(*MF, PM);
+
+  // Find the COPY instruction (our query point where %0 is live but not yet
+  // used)
+  MachineBasicBlock &MBB = *MF->begin();
+  auto QueryIt =
+      std::find_if(MBB.begin(), MBB.end(), [](const MachineInstr &MI) {
+        return MI.getOpcode() == TargetOpcode::COPY &&
+               MI.getOperand(0).isReg() &&
+               MI.getOperand(0).getReg() == Register::index2VirtReg(1); // %1
+      });
+  ASSERT_NE(QueryIt, MBB.end())
+      << "Could not find COPY instruction for query point";
+
+  // Get the virtual register number for %0 (defined by the previous
+  // IMPLICIT_DEF)
+  auto ImplicitDefIt =
+      std::find_if(MBB.begin(), MBB.end(), [](const MachineInstr &MI) {
+        return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF;
+      });
+  ASSERT_NE(ImplicitDefIt, MBB.end())
+      << "Could not find IMPLICIT_DEF instruction";
+
+  Register VReg = ImplicitDefIt->getOperand(0).getReg();
+  ASSERT_TRUE(VReg.isVirtual()) << "Expected virtual register";
+
+  // Test getSortedSubregUses at the COPY instruction (after %0 is defined,
+  // before it's used)
+  LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg(VReg);
+  VRegMaskPair VMP(VReg, FullMask);
+
+  SmallVector<VRegMaskPair> SortedUses = NU.getSortedSubregUses(QueryIt, VMP);
+
+  // Verify that we got results
+  ASSERT_FALSE(SortedUses.empty())
+      << "getSortedSubregUses should return sub-register uses";
+
+  // The key test: sub0 (accessed last at distance 9) should appear first
+  // in the sorted result since getSortedSubregUses returns furthest uses first
+  bool FoundSub0First = false;
+  if (!SortedUses.empty()) {
+    // Get the lane mask for sub0
+    LaneBitmask Sub0Mask = TRI->getSubRegIndexLaneMask(AMDGPU::sub0);
+
+    // Check if the first entry corresponds to sub0
+    if (SortedUses[0].getLaneMask() == Sub0Mask) {
+      FoundSub0First = true;
+    }
+  }
+
+  EXPECT_TRUE(FoundSub0First) << "sub0 (furthest use) should appear first in "
+                                 "getSortedSubregUses result";
+
+  // Verify that we got results
+  ASSERT_FALSE(SortedUses.empty())
+      << "getSortedSubregUses should return sub-register uses";
+
+  // Verify we have exactly 8 sub-register uses (sub0, sub1, sub2, sub3, sub28,
+  // sub29, sub30, sub31)
+  ASSERT_EQ(SortedUses.size(), 8u)
+      << "Expected exactly 8 sub-register uses, got " << SortedUses.size();
+
+  // Define expected sub-registers in order of decreasing distance (furthest
+  // first) Based on our MIR: sub0 (dist 9), sub1 (dist 8), sub2 (dist 7), sub3
+  // (dist 6),
+  //                   sub28 (dist 4), sub29 (dist 3), sub30 (dist 2), sub31
+  //                   (dist 1)
+  std::vector<unsigned> expectedSubRegs = {
+      AMDGPU::sub0,  // Distance 9 (furthest)
+      AMDGPU::sub1,  // Distance 8
+      AMDGPU::sub2,  // Distance 7
+      AMDGPU::sub3,  // Distance 6
+      AMDGPU::sub28, // Distance 4
+      AMDGPU::sub29, // Distance 3
+      AMDGPU::sub30, // Distance 2
+      AMDGPU::sub31  // Distance 1 (closest)
+  };
+
+  // Verify exact order: furthest uses first
+  for (size_t i = 0; i < expectedSubRegs.size(); ++i) {
+    LaneBitmask ExpectedMask = TRI->getSubRegIndexLaneMask(expectedSubRegs[i]);
+    LaneBitmask ActualMask = SortedUses[i].getLaneMask();
+
+    EXPECT_EQ(ActualMask, ExpectedMask)
+        << "Position " << i << ": Expected sub-register "
+        << TRI->getSubRegIndexName(expectedSubRegs[i]) << " (mask "
+        << ExpectedMask.getAsInteger() << "), "
+        << "but got mask " << ActualMask.getAsInteger();
+  }
+
+  // Additional verification: all entries should reference the same VReg (%0)
+  for (const auto &Use : SortedUses) {
+    EXPECT_EQ(Use.getVReg(), VReg)
+        << "All sorted uses should reference the same virtual register";
+  }
+}
+
+INSTANTIATE_TEST_SUITE_P(
+  AllMirFiles,
+  NextUseAnalysisParameterizedTest,
+  testing::ValuesIn(getMirFiles()),
+  [](const testing::TestParamInfo<std::string>& info) {
+    std::string name = info.param;
+    // Replace non-alphanumeric characters with underscores for valid test names
+    std::replace_if(name.begin(), name.end(), [](char c) { 
+      return !std::isalnum(c); 
+    }, '_');
+    return name;
+  }
+);
+
+} // end anonymous namespace