From b1919dde1492495ed8bf53d852deabc3808c41df Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Fri, 30 May 2025 06:43:53 -0700 Subject: [PATCH 01/30] [llvm-exegesis] [AArch64] Resolve " Not all operands were initialized by the snippet generator" by omit OPERAND_UNKNOWN to Immediate --- .../llvm-exegesis/lib/AArch64/Target.cpp | 22 +++++++++++++++++++ .../llvm-exegesis/lib/SnippetGenerator.cpp | 6 +++++ 2 files changed, 28 insertions(+) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index a1eb5a46f21fc..d768673944bd4 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -162,6 +162,10 @@ class ExegesisAArch64Target : public ExegesisTarget { ExegesisAArch64Target() : ExegesisTarget(AArch64CpuPfmCounters, AArch64_MC::isOpcodeAvailable) {} + Error randomizeTargetMCOperand( + const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue, + const BitVector &ForbiddenRegs) const override; + private: std::vector setRegTo(const MCSubtargetInfo &STI, MCRegister Reg, const APInt &Value) const override { @@ -229,6 +233,24 @@ class ExegesisAArch64Target : public ExegesisTarget { } }; +Error ExegesisAArch64Target::randomizeTargetMCOperand( + const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue, + const BitVector &ForbiddenRegs) const { + unsigned Opcode = Instr.getOpcode(); + switch (Opcode) { + case AArch64::MOVIv2s_msl: + case AArch64::MOVIv4s_msl: + case AArch64::MVNIv2s_msl: + case AArch64::MVNIv4s_msl: + AssignedValue = MCOperand::createImm(8); // or 16, as needed + break; + default: + AssignedValue = MCOperand::createImm(0); + break; + } + return Error::success(); +} + } // namespace static ExegesisTarget *getTheExegesisAArch64Target() { diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp index 04064ae1d8441..de2bc4d54d1d5 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp @@ -276,6 +276,12 @@ static Error randomizeMCOperand(const LLVMState &State, AssignedValue = MCOperand::createReg(randomBit(AllowedRegs)); break; } + /// Omit unknown operands to default immediate value based on the instruction +#ifdef __aarch64__ + case MCOI::OperandType::OPERAND_UNKNOWN: + return State.getExegesisTarget().randomizeTargetMCOperand( + Instr, Var, AssignedValue, ForbiddenRegs); +#endif default: break; } From af68e0ff850d0ff5b2a8e517145a99421cd6fb9e Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Sun, 1 Jun 2025 11:52:13 -0700 Subject: [PATCH 02/30] [llvm-exegesis] [AArch64] Include OPERAND_PCREL operand handling in snippet generation, omiting immediate valued 0. --- .../llvm-exegesis/lib/AArch64/Target.cpp | 32 ++++++++++++------- .../llvm-exegesis/lib/SnippetGenerator.cpp | 4 ++- 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index d768673944bd4..4e8150ae79ee8 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -236,19 +236,29 @@ class ExegesisAArch64Target : public ExegesisTarget { Error ExegesisAArch64Target::randomizeTargetMCOperand( const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue, const BitVector &ForbiddenRegs) const { - unsigned Opcode = Instr.getOpcode(); - switch (Opcode) { - case AArch64::MOVIv2s_msl: - case AArch64::MOVIv4s_msl: - case AArch64::MVNIv2s_msl: - case AArch64::MVNIv4s_msl: - AssignedValue = MCOperand::createImm(8); // or 16, as needed - break; - default: + const Operand &Op = Instr.getPrimaryOperand(Var); + switch (Op.getExplicitOperandInfo().OperandType) { + case MCOI::OperandType::OPERAND_UNKNOWN: { + unsigned Opcode = Instr.getOpcode(); + switch (Opcode) { + case AArch64::MOVIv2s_msl: + case AArch64::MOVIv4s_msl: + case AArch64::MVNIv2s_msl: + case AArch64::MVNIv4s_msl: + AssignedValue = MCOperand::createImm(8); // or 16, as needed + break; + default: + AssignedValue = MCOperand::createImm(0); + break; + } + return Error::success(); + } + case MCOI::OperandType::OPERAND_PCREL: AssignedValue = MCOperand::createImm(0); - break; + return Error::success(); + default: + llvm_unreachable("Unexpected operand type in randomizeTargetMCOperand"); } - return Error::success(); } } // namespace diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp index de2bc4d54d1d5..fef2c0f6077dc 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp @@ -276,9 +276,11 @@ static Error randomizeMCOperand(const LLVMState &State, AssignedValue = MCOperand::createReg(randomBit(AllowedRegs)); break; } - /// Omit unknown operands to default immediate value based on the instruction + /// Omit unknown and pc-relative operands to imm value based on the instruction + // TODO: Is aarch64 gaurd neccessary ? #ifdef __aarch64__ case MCOI::OperandType::OPERAND_UNKNOWN: + case MCOI::OperandType::OPERAND_PCREL: return State.getExegesisTarget().randomizeTargetMCOperand( Instr, Var, AssignedValue, ForbiddenRegs); #endif From 5697760a959d24cd83a43830ebcb0365b9cae730 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Sun, 1 Jun 2025 23:00:27 -0700 Subject: [PATCH 03/30] [llvm-exegesis] [AArch64] WIP. Introduce handling for OPERAND_FIRST_TARGET. --- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 4e8150ae79ee8..c152122171949 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -256,6 +256,9 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( case MCOI::OperandType::OPERAND_PCREL: AssignedValue = MCOperand::createImm(0); return Error::success(); + case MCOI::OperandType::OPERAND_FIRST_TARGET: + AssignedValue = MCOperand::createImm(0); + return Error::success(); default: llvm_unreachable("Unexpected operand type in randomizeTargetMCOperand"); } From 75c2e65b11f90528914f9938bbf49dbd033567c4 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Sun, 1 Jun 2025 23:01:28 -0700 Subject: [PATCH 04/30] [llvm-exegesis] [AArch64] Explore opcode-specific immediate values for omitted opcode type. --- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index c152122171949..38c3bafb88952 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -237,6 +237,8 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue, const BitVector &ForbiddenRegs) const { const Operand &Op = Instr.getPrimaryOperand(Var); + // Introducing some illegal instructions for (15) a few opcodes + // TODO: Look into immediate values to be opcode specific switch (Op.getExplicitOperandInfo().OperandType) { case MCOI::OperandType::OPERAND_UNKNOWN: { unsigned Opcode = Instr.getOpcode(); From 9d425dc4f9f8053b7b969c0f35395a8905273155 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Mon, 2 Jun 2025 03:06:06 -0700 Subject: [PATCH 05/30] [llvm-exegesis] [AArch64] Refactor operand handling in randomizeTargetMCOperand. --- .../llvm-exegesis/lib/AArch64/Target.cpp | 46 ++++++++++--------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 38c3bafb88952..8fc5feded832b 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -237,33 +237,35 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue, const BitVector &ForbiddenRegs) const { const Operand &Op = Instr.getPrimaryOperand(Var); + const auto OperandType = Op.getExplicitOperandInfo().OperandType; // Introducing some illegal instructions for (15) a few opcodes // TODO: Look into immediate values to be opcode specific - switch (Op.getExplicitOperandInfo().OperandType) { - case MCOI::OperandType::OPERAND_UNKNOWN: { - unsigned Opcode = Instr.getOpcode(); - switch (Opcode) { - case AArch64::MOVIv2s_msl: - case AArch64::MOVIv4s_msl: - case AArch64::MVNIv2s_msl: - case AArch64::MVNIv4s_msl: - AssignedValue = MCOperand::createImm(8); // or 16, as needed - break; - default: + switch (OperandType) { + case MCOI::OperandType::OPERAND_UNKNOWN: { + unsigned Opcode = Instr.getOpcode(); + switch (Opcode) { + case AArch64::MOVIv2s_msl: + case AArch64::MOVIv4s_msl: + case AArch64::MVNIv2s_msl: + case AArch64::MVNIv4s_msl: + AssignedValue = MCOperand::createImm(8); // or 16, as needed + return Error::success(); + default: + AssignedValue = MCOperand::createImm(0); + return Error::success(); + } + } + case MCOI::OperandType::OPERAND_PCREL: + case MCOI::OperandType::OPERAND_FIRST_TARGET: AssignedValue = MCOperand::createImm(0); + return Error::success(); + default: break; - } - return Error::success(); - } - case MCOI::OperandType::OPERAND_PCREL: - AssignedValue = MCOperand::createImm(0); - return Error::success(); - case MCOI::OperandType::OPERAND_FIRST_TARGET: - AssignedValue = MCOperand::createImm(0); - return Error::success(); - default: - llvm_unreachable("Unexpected operand type in randomizeTargetMCOperand"); } + + return make_error( + Twine("Unimplemented operand type: MCOI::OperandType:") + .concat(Twine(static_cast(OperandType)))); } } // namespace From 9a1feb2d99b4dc9bd5cea7f6ea117bb21d3d72bb Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Mon, 2 Jun 2025 22:28:44 -0700 Subject: [PATCH 06/30] [llvm-exegesis] [AArch64] Update comments for operand handling and remove out of scope operand type. --- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 1 - llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 8fc5feded832b..285d888770a53 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -256,7 +256,6 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( } } case MCOI::OperandType::OPERAND_PCREL: - case MCOI::OperandType::OPERAND_FIRST_TARGET: AssignedValue = MCOperand::createImm(0); return Error::success(); default: diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp index fef2c0f6077dc..d4381c3b123f0 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp @@ -277,7 +277,7 @@ static Error randomizeMCOperand(const LLVMState &State, break; } /// Omit unknown and pc-relative operands to imm value based on the instruction - // TODO: Is aarch64 gaurd neccessary ? + // TODO: Neccesity of AArch64 guard ? #ifdef __aarch64__ case MCOI::OperandType::OPERAND_UNKNOWN: case MCOI::OperandType::OPERAND_PCREL: From f56787028235b5328ea5dc3a20637532a1db4c68 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Tue, 3 Jun 2025 00:58:47 -0700 Subject: [PATCH 07/30] [llvm-exegesis] [AArch64] Format changes. --- .../llvm-exegesis/lib/AArch64/Target.cpp | 40 +++++++++---------- .../llvm-exegesis/lib/SnippetGenerator.cpp | 3 +- 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 285d888770a53..8ee7983f87731 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -162,9 +162,9 @@ class ExegesisAArch64Target : public ExegesisTarget { ExegesisAArch64Target() : ExegesisTarget(AArch64CpuPfmCounters, AArch64_MC::isOpcodeAvailable) {} - Error randomizeTargetMCOperand( - const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue, - const BitVector &ForbiddenRegs) const override; + Error randomizeTargetMCOperand(const Instruction &Instr, const Variable &Var, + MCOperand &AssignedValue, + const BitVector &ForbiddenRegs) const override; private: std::vector setRegTo(const MCSubtargetInfo &STI, MCRegister Reg, @@ -241,25 +241,25 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( // Introducing some illegal instructions for (15) a few opcodes // TODO: Look into immediate values to be opcode specific switch (OperandType) { - case MCOI::OperandType::OPERAND_UNKNOWN: { - unsigned Opcode = Instr.getOpcode(); - switch (Opcode) { - case AArch64::MOVIv2s_msl: - case AArch64::MOVIv4s_msl: - case AArch64::MVNIv2s_msl: - case AArch64::MVNIv4s_msl: - AssignedValue = MCOperand::createImm(8); // or 16, as needed - return Error::success(); - default: - AssignedValue = MCOperand::createImm(0); - return Error::success(); - } - } - case MCOI::OperandType::OPERAND_PCREL: - AssignedValue = MCOperand::createImm(0); + case MCOI::OperandType::OPERAND_UNKNOWN: { + unsigned Opcode = Instr.getOpcode(); + switch (Opcode) { + case AArch64::MOVIv2s_msl: + case AArch64::MOVIv4s_msl: + case AArch64::MVNIv2s_msl: + case AArch64::MVNIv4s_msl: + AssignedValue = MCOperand::createImm(8); // or 16, as needed return Error::success(); default: - break; + AssignedValue = MCOperand::createImm(0); + return Error::success(); + } + } + case MCOI::OperandType::OPERAND_PCREL: + AssignedValue = MCOperand::createImm(0); + return Error::success(); + default: + break; } return make_error( diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp index d4381c3b123f0..6859a9d496250 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp @@ -276,7 +276,8 @@ static Error randomizeMCOperand(const LLVMState &State, AssignedValue = MCOperand::createReg(randomBit(AllowedRegs)); break; } - /// Omit unknown and pc-relative operands to imm value based on the instruction + /// Omit unknown and pc-relative operands to imm value based on the + /// instruction // TODO: Neccesity of AArch64 guard ? #ifdef __aarch64__ case MCOI::OperandType::OPERAND_UNKNOWN: From 66fdd3973e378b199348e9d7de2043ef1785421f Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Tue, 3 Jun 2025 07:35:58 -0700 Subject: [PATCH 08/30] [llvm-exegesis] [AArch64] Remove unneccessary AArch64 guard --- llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp | 3 --- 1 file changed, 3 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp index 6859a9d496250..156739bd9de34 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp @@ -278,13 +278,10 @@ static Error randomizeMCOperand(const LLVMState &State, } /// Omit unknown and pc-relative operands to imm value based on the /// instruction - // TODO: Neccesity of AArch64 guard ? -#ifdef __aarch64__ case MCOI::OperandType::OPERAND_UNKNOWN: case MCOI::OperandType::OPERAND_PCREL: return State.getExegesisTarget().randomizeTargetMCOperand( Instr, Var, AssignedValue, ForbiddenRegs); -#endif default: break; } From 59452e553938b59c1897a551a709da14ce0612b9 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 11 Jun 2025 08:44:16 -0700 Subject: [PATCH 09/30] [llvm-exegesis] [AArch64] Add handling for OPERAND_FIRST_TARGET in randomizeTargetMCOperand to omit to Immediate --- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 8ee7983f87731..4aa4b60815de7 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -248,7 +248,7 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( case AArch64::MOVIv4s_msl: case AArch64::MVNIv2s_msl: case AArch64::MVNIv4s_msl: - AssignedValue = MCOperand::createImm(8); // or 16, as needed + AssignedValue = MCOperand::createImm(8); // or 16 return Error::success(); default: AssignedValue = MCOperand::createImm(0); @@ -256,6 +256,7 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( } } case MCOI::OperandType::OPERAND_PCREL: + case MCOI::OperandType::OPERAND_FIRST_TARGET: AssignedValue = MCOperand::createImm(0); return Error::success(); default: From 1726beaed75c7bc7427ea5f92f7078d941f494b4 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 11 Jun 2025 08:49:23 -0700 Subject: [PATCH 10/30] [llvm-exegesis] [AArch64] Documenting opcodes requiring some specific omittion to resolve illegal instruction --- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 4aa4b60815de7..fe6703f7ffd3f 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -238,8 +238,8 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( const BitVector &ForbiddenRegs) const { const Operand &Op = Instr.getPrimaryOperand(Var); const auto OperandType = Op.getExplicitOperandInfo().OperandType; - // Introducing some illegal instructions for (15) a few opcodes - // TODO: Look into immediate values to be opcode specific + // TODO: Look into immediate values to be opcode specific for + // MRS, MSR, MSRpstatesvcrImm1, SYSLxt, SYSxt, UDF (illegal instruction) switch (OperandType) { case MCOI::OperandType::OPERAND_UNKNOWN: { unsigned Opcode = Instr.getOpcode(); From c26aa00fff88807a6fc8d69d21f1ca44db161310 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Mon, 16 Jun 2025 08:12:15 -0700 Subject: [PATCH 11/30] [llvm-exegesis] [AArch64] Add tests for operand omission scenarios in error-resolution.s --- .../llvm-exegesis/AArch64/error-resolution.s | 82 +++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s diff --git a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s new file mode 100644 index 0000000000000..35ad6e870e1b1 --- /dev/null +++ b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s @@ -0,0 +1,82 @@ +# REQUIRES: aarch64-registered-target + + + +// Test for omitting OperandType::OPERAND_UNKNOWN + +// ADDXri: ADD Xd, Xn, #imm{, shift} +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=ADDXri 2>&1 | FileCheck %s --check-prefix=ADDXri_latency +# ADDXri_latency-NOT: Not all operands were initialized by the snippet generator for ADDXri opcode +# ADDXri_latency: --- +# ADDXri_latency-NEXT: mode: latency +# ADDXri_latency-NEXT: key: +# ADDXri_latency-NEXT: instructions: +# ADDXri_latency-NEXT: ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0 +# ADDXri_latency: ... + +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=ADDXri 2>&1 | FileCheck %s --check-prefix=ADDXri_throughput +# ADDXri_throughput-NOT: Not all operands were initialized by the snippet generator for ADDXri opcode +# ADDXri_throughput: --- +# ADDXri_throughput-NEXT: mode: inverse_throughput +# ADDXri_throughput-NEXT: key: +# ADDXri_throughput-NEXT: instructions: +# ADDXri_throughput-NEXT: ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0 +# ADDXri_throughput: ... + +// MOVIv2s_msl: MOVI vd, #imm{, shift} +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_latency +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_throughput +# MOVIv2s_msl_latency-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode + +// TODO: Update this test when serial execution strategy is added +# MOVIv2s_msl_latency: MOVIv2s_msl: No strategy found to make the execution serial + + +# MOVIv2s_msl_throughput-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode +# MOVIv2s_msl_throughput: --- +# MOVIv2s_msl_throughput-NEXT: mode: inverse_throughput +# MOVIv2s_msl_throughput-NEXT: key: +# MOVIv2s_msl_throughput-NEXT: instructions: +# MOVIv2s_msl_throughput-NEXT: MOVIv2s_msl [[REG1:D[0-9]+|LR]] i_0x1 i_0x8 +# MOVIv2s_msl_throughput: ... + + + +// Test for omitting OperandType::OPERAND_PCREL +// LDRDl: LDRD ldr1, ldr2, [pc, #imm] +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=LDRDl 2>&1 | FileCheck %s --check-prefix=LDRDl_latency +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=LDRDl 2>&1 | FileCheck %s --check-prefix=LDRDl_throughput + +# LDRDl_latency-NOT: Not all operands were initialized by the snippet generator for LDRDl opcodes +# LDRDl_throughput-NOT: Not all operands were initialized by the snippet generator for LDRDl opcodes + +# LDRDl_throughput: --- +# LDRDl_throughput-NEXT: mode: inverse_throughput +# LDRDl_throughput-NEXT: key: +# LDRDl_throughput-NEXT: instructions: +# LDRDl_throughput-NEXT: LDRDl [[REG1:D[0-9]+|LR]] i_0x0 +# LDRDl_throughput: ... + + + +// Test for omitting OperandType::OPERAND_FIRST_TARGET + +// UMOVvi16_idx0: UMOV wd, vn.h[index] +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_latency +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_throughput + +# UMOVvi16_idx0_latency-NOT: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode +# UMOVvi16_idx0_latency: --- +# UMOVvi16_idx0_latency-NEXT: mode: latency +# UMOVvi16_idx0_latency-NEXT: key: +# UMOVvi16_idx0_latency-NEXT: instructions: +# UMOVvi16_idx0_latency-NEXT: UMOVvi16_idx0 [[REG1:W[0-9]+|LR]] [[REG2:Q[0-9]+|LR]] i_0x0 +# UMOVvi16_idx0_latency: ... + +# UMOVvi16_idx0_throughput-NOT: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode +# UMOVvi16_idx0_throughput: --- +# UMOVvi16_idx0_throughput-NEXT: mode: inverse_throughput +# UMOVvi16_idx0_throughput-NEXT: key: +# UMOVvi16_idx0_throughput-NEXT: instructions: +# UMOVvi16_idx0_throughput-NEXT: UMOVvi16_idx0 [[REG1:W[0-9]+|LR]] [[REG2:Q[0-9]+|LR]] i_0x0 +# UMOVvi16_idx0_throughput: ... From f43b8e20427a48a14c659c91ae66189d98cb603b Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Thu, 26 Jun 2025 23:01:42 -0700 Subject: [PATCH 12/30] [llvm-exegesis] [AArch64] Reporting limitation in initializing operand type in randomizeTargetMCOperand --- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index fe6703f7ffd3f..ccdeff1090c41 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -238,8 +238,17 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( const BitVector &ForbiddenRegs) const { const Operand &Op = Instr.getPrimaryOperand(Var); const auto OperandType = Op.getExplicitOperandInfo().OperandType; - // TODO: Look into immediate values to be opcode specific for - // MRS, MSR, MSRpstatesvcrImm1, SYSLxt, SYSxt, UDF (illegal instruction) + // FIXME: Implement opcode-specific immediate value handling for system + // instructions: + // - MRS/MSR: Use valid system register encodings (e.g., NZCV, FPCR, FPSR) + // - MSRpstatesvcrImm1: Use valid PSTATE field encodings (e.g., SPSel, + // DAIFSet) + // - SYSLxt/SYSxt: Use valid system instruction encodings with proper + // CRn/CRm/op values + // - UDF: Use valid undefined instruction immediate ranges (0-65535) + // Currently defaulting to immediate value 0, which may cause invalid + // encodings or unreliable benchmark results for these system-level + // instructions. switch (OperandType) { case MCOI::OperandType::OPERAND_UNKNOWN: { unsigned Opcode = Instr.getOpcode(); From c26beda3a49dac1abe7f3729cd018365675764ed Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 2 Jul 2025 02:11:26 -0700 Subject: [PATCH 13/30] [llvm-exegesis] [AArch64] Enhance randomizeTargetMCOperand to support MSL immediate operands for 32-bit SIMD constants --- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index ccdeff1090c41..66bc2242e7c32 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -253,11 +253,23 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( case MCOI::OperandType::OPERAND_UNKNOWN: { unsigned Opcode = Instr.getOpcode(); switch (Opcode) { + // MSL (Masking Shift Left) immediate operand for 32-bit splatted SIMD constants + // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s( case AArch64::MOVIv2s_msl: - case AArch64::MOVIv4s_msl: case AArch64::MVNIv2s_msl: + // Type 7: Pattern 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF + // Creates 2-element 32-bit vector with 8-bit immediate at positions [15:8] and [47:40] + // Shift value 264 (0x108) for Type 7 pattern encoding + // Corresponds to AArch64_AM::encodeAdvSIMDModImmType7() + AssignedValue = MCOperand::createImm(264); + return Error::success(); + case AArch64::MOVIv4s_msl: case AArch64::MVNIv4s_msl: - AssignedValue = MCOperand::createImm(8); // or 16 + // Type 8: Pattern 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF + // Creates 4-element 32-bit vector with 8-bit immediate at positions [23:16] and [55:48] + // Shift value 272 (0x110) for Type 8 pattern encoding + // Corresponds to AArch64_AM::encodeAdvSIMDModImmType8() + AssignedValue = MCOperand::createImm(272); return Error::success(); default: AssignedValue = MCOperand::createImm(0); From ef67b173b6faf09e29403584851969d40cc4059a Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 2 Jul 2025 02:32:16 -0700 Subject: [PATCH 14/30] [llvm-exegesis] [AArch64] Update test to reflect changes in immediate value handling for MOVIv2s_msl --- llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s index 35ad6e870e1b1..f51f0ab12d295 100644 --- a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s +++ b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s @@ -28,8 +28,7 @@ # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_throughput # MOVIv2s_msl_latency-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode -// TODO: Update this test when serial execution strategy is added -# MOVIv2s_msl_latency: MOVIv2s_msl: No strategy found to make the execution serial +// TODO: Add test to check if the immediate value is correct when serial execution strategy is added for MOVIv2s_msl # MOVIv2s_msl_throughput-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode @@ -37,7 +36,7 @@ # MOVIv2s_msl_throughput-NEXT: mode: inverse_throughput # MOVIv2s_msl_throughput-NEXT: key: # MOVIv2s_msl_throughput-NEXT: instructions: -# MOVIv2s_msl_throughput-NEXT: MOVIv2s_msl [[REG1:D[0-9]+|LR]] i_0x1 i_0x8 +# MOVIv2s_msl_throughput-NEXT: MOVIv2s_msl [[REG1:D[0-9]+|LR]] i_0x1 i_0x108 # MOVIv2s_msl_throughput: ... From aea88617ad74263a710f6703b9c3c549f19a4e5f Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 2 Jul 2025 02:55:42 -0700 Subject: [PATCH 15/30] [llvm-exegesis] [AArch64] Clang Format --- .../tools/llvm-exegesis/lib/AArch64/Target.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 66bc2242e7c32..7af3845797cf0 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -253,22 +253,22 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( case MCOI::OperandType::OPERAND_UNKNOWN: { unsigned Opcode = Instr.getOpcode(); switch (Opcode) { - // MSL (Masking Shift Left) immediate operand for 32-bit splatted SIMD constants - // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s( + // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants + // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s() case AArch64::MOVIv2s_msl: case AArch64::MVNIv2s_msl: // Type 7: Pattern 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF - // Creates 2-element 32-bit vector with 8-bit immediate at positions [15:8] and [47:40] - // Shift value 264 (0x108) for Type 7 pattern encoding - // Corresponds to AArch64_AM::encodeAdvSIMDModImmType7() + // Creates 2-element 32-bit vector with 8-bit imm at positions [15:8] & + // [47:40] Shift value 264 (0x108) for Type 7 pattern encoding Corresponds + // to AArch64_AM::encodeAdvSIMDModImmType7() AssignedValue = MCOperand::createImm(264); return Error::success(); case AArch64::MOVIv4s_msl: case AArch64::MVNIv4s_msl: - // Type 8: Pattern 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF - // Creates 4-element 32-bit vector with 8-bit immediate at positions [23:16] and [55:48] - // Shift value 272 (0x110) for Type 8 pattern encoding - // Corresponds to AArch64_AM::encodeAdvSIMDModImmType8() + // Type 8: Pattern 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF + // Creates 4-element 32-bit vector with 8-bit imm at positions [23:16] & + // [55:48] Shift value 272 (0x110) for Type 8 pattern encoding Corresponds + // to AArch64_AM::encodeAdvSIMDModImmType8() AssignedValue = MCOperand::createImm(272); return Error::success(); default: From 0f09343233abb90405e4ed2c55dd3354fc97f56c Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 13 Aug 2025 03:24:02 -0700 Subject: [PATCH 16/30] [AArch64] Introduce new operand types for MSL shifts and update related definitions --- .../lib/Target/AArch64/AArch64InstrFormats.td | 45 +++++++++++++++++-- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 8 ++-- .../MCTargetDesc/AArch64MCTargetDesc.h | 2 + 3 files changed, 47 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 5489541fcb318..bd45bcf8eb812 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -1317,11 +1317,23 @@ def logical_vec_hw_shift : Operand { } // A vector move shifter operand: -// {0} - imm1: #8 or #16 -def move_vec_shift : Operand { +// {0} - imm1: #8 +def move_vec_shift_2s : Operand { + let OperandNamespace = "AArch64"; let PrintMethod = "printShifter"; + let OperandType = "OPERAND_MSL_SHIFT_2S"; + let ParserMatchClass = MoveVecShifterOperand; let EncoderMethod = "getMoveVecShifterOpValue"; +} + +// A vector move shifter operand: +// {0} - imm1: #16 +def move_vec_shift_4s : Operand { + let OperandNamespace = "AArch64"; + let PrintMethod = "printShifter"; + let OperandType = "OPERAND_MSL_SHIFT_4S"; let ParserMatchClass = MoveVecShifterOperand; + let EncoderMethod = "getMoveVecShifterOpValue"; } let DiagnosticType = "AddSubSecondSource" in { @@ -1561,6 +1573,20 @@ let OperandNamespace = "AArch64" in { defm VectorIndex032b : VectorIndex; } + // Add new aarch64 specific OperandType + let OperandType = "OPERAND_MSL_SHIFT_2S" in { + def msl_shift_2s : Operand { + let PrintMethod = "printImm"; + let ParserMatchClass = MoveVecShifterOperand; + } + } + +let OperandType = "OPERAND_MSL_SHIFT_4S" in { + def msl_shift_4s : Operand { + let PrintMethod = "printImm"; + let ParserMatchClass = MoveVecShifterOperand; + } + } } defm VectorIndex1 : VectorIndex; @@ -8898,11 +8924,22 @@ multiclass SIMDModifiedImmVectorShiftTied hw_cmode, (i32 imm:$shift)))]>; } -class SIMDModifiedImmMoveMSL cmode, +class SIMDModifiedImmMoveMSL_2s cmode, + RegisterOperand vectype, string asm, + string kind, list pattern> + : BaseSIMDModifiedImmVector { + bits<1> shift; + let Inst{15-13} = cmode{3-1}; + let Inst{12} = shift; +} + +class SIMDModifiedImmMoveMSL_4s cmode, RegisterOperand vectype, string asm, string kind, list pattern> : BaseSIMDModifiedImmVector { bits<1> shift; let Inst{15-13} = cmode{3-1}; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 72445172059bf..1586b094f2e12 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -8085,10 +8085,10 @@ def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), let isReMaterializable = 1, isAsCheapAsAMove = 1 in { // EDIT per word: 2s & 4s with MSL shifter -def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s", +def MOVIv2s_msl : SIMDModifiedImmMoveMSL_2s<0, 0, {1,1,0,?}, V64, "movi", ".2s", [(set (v2i32 V64:$Rd), (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; -def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s", +def MOVIv4s_msl : SIMDModifiedImmMoveMSL_4s<1, 0, {1,1,0,?}, V128, "movi", ".4s", [(set (v4i32 V128:$Rd), (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; @@ -8131,10 +8131,10 @@ def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), // EDIT per word: 2s & 4s with MSL shifter let isReMaterializable = 1, isAsCheapAsAMove = 1 in { -def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s", +def MVNIv2s_msl : SIMDModifiedImmMoveMSL_2s<0, 1, {1,1,0,?}, V64, "mvni", ".2s", [(set (v2i32 V64:$Rd), (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; -def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s", +def MVNIv4s_msl : SIMDModifiedImmMoveMSL_4s<1, 1, {1,1,0,?}, V128, "mvni", ".4s", [(set (v4i32 V128:$Rd), (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h index 91bdc880998b2..df7e3660b1e6f 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -70,6 +70,8 @@ bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII); namespace AArch64 { enum OperandType { OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET, + OPERAND_MSL_SHIFT_2S, + OPERAND_MSL_SHIFT_4S, }; } // namespace AArch64 From 5a564016026adefea35ff2577d2cc52c02d26c52 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 13 Aug 2025 03:24:49 -0700 Subject: [PATCH 17/30] [AArch64] Update randomizeTargetMCOperand to handle MSL immediate operands --- .../llvm-exegesis/lib/AArch64/Target.cpp | 34 ++++++++----------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 7af3845797cf0..a6a6ccfbd412f 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -250,34 +250,30 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( // encodings or unreliable benchmark results for these system-level // instructions. switch (OperandType) { - case MCOI::OperandType::OPERAND_UNKNOWN: { - unsigned Opcode = Instr.getOpcode(); - switch (Opcode) { + case MCOI::OperandType::OPERAND_UNKNOWN: { + AssignedValue = MCOperand::createImm(0); + return Error::success(); + } // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s() - case AArch64::MOVIv2s_msl: - case AArch64::MVNIv2s_msl: + case llvm::AArch64::OPERAND_MSL_SHIFT_2S: { // Type 7: Pattern 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF // Creates 2-element 32-bit vector with 8-bit imm at positions [15:8] & // [47:40] Shift value 264 (0x108) for Type 7 pattern encoding Corresponds // to AArch64_AM::encodeAdvSIMDModImmType7() AssignedValue = MCOperand::createImm(264); return Error::success(); - case AArch64::MOVIv4s_msl: - case AArch64::MVNIv4s_msl: - // Type 8: Pattern 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF - // Creates 4-element 32-bit vector with 8-bit imm at positions [23:16] & - // [55:48] Shift value 272 (0x110) for Type 8 pattern encoding Corresponds - // to AArch64_AM::encodeAdvSIMDModImmType8() - AssignedValue = MCOperand::createImm(272); - return Error::success(); - default: - AssignedValue = MCOperand::createImm(0); - return Error::success(); } - } - case MCOI::OperandType::OPERAND_PCREL: - case MCOI::OperandType::OPERAND_FIRST_TARGET: + case llvm::AArch64::OPERAND_MSL_SHIFT_4S: { + // Type 8: Pattern 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF + // Creates 4-element 32-bit vector with 8-bit imm at positions [23:16] & + // [55:48] Shift value 272 (0x110) for Type 8 pattern encoding Corresponds + // to AArch64_AM::encodeAdvSIMDModImmType8() + AssignedValue = MCOperand::createImm(272); + return Error::success(); + } + case MCOI::OperandType::OPERAND_PCREL: + case MCOI::OperandType::OPERAND_FIRST_TARGET: AssignedValue = MCOperand::createImm(0); return Error::success(); default: From cd435fb312fa86983436545ac699ef90195e4188 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 13 Aug 2025 23:10:47 -0700 Subject: [PATCH 18/30] [AArch64] Clang Format --- .../MCTargetDesc/AArch64MCTargetDesc.h | 4 +- .../llvm-exegesis/lib/AArch64/Target.cpp | 48 +++++++++---------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h index df7e3660b1e6f..61e5525f3b741 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -65,7 +65,7 @@ void initLLVMToCVRegMapping(MCRegisterInfo *MRI); bool isHForm(const MCInst &MI, const MCInstrInfo *MCII); bool isQForm(const MCInst &MI, const MCInstrInfo *MCII); bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII); -} +} // namespace AArch64_MC namespace AArch64 { enum OperandType { @@ -75,7 +75,7 @@ enum OperandType { }; } // namespace AArch64 -} // End llvm namespace +} // namespace llvm // Defines symbolic names for AArch64 registers. This defines a mapping from // register name to register number. diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index a6a6ccfbd412f..a71910f42b703 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -250,30 +250,30 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( // encodings or unreliable benchmark results for these system-level // instructions. switch (OperandType) { - case MCOI::OperandType::OPERAND_UNKNOWN: { - AssignedValue = MCOperand::createImm(0); - return Error::success(); - } - // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants - // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s() - case llvm::AArch64::OPERAND_MSL_SHIFT_2S: { - // Type 7: Pattern 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF - // Creates 2-element 32-bit vector with 8-bit imm at positions [15:8] & - // [47:40] Shift value 264 (0x108) for Type 7 pattern encoding Corresponds - // to AArch64_AM::encodeAdvSIMDModImmType7() - AssignedValue = MCOperand::createImm(264); - return Error::success(); - } - case llvm::AArch64::OPERAND_MSL_SHIFT_4S: { - // Type 8: Pattern 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF - // Creates 4-element 32-bit vector with 8-bit imm at positions [23:16] & - // [55:48] Shift value 272 (0x110) for Type 8 pattern encoding Corresponds - // to AArch64_AM::encodeAdvSIMDModImmType8() - AssignedValue = MCOperand::createImm(272); - return Error::success(); - } - case MCOI::OperandType::OPERAND_PCREL: - case MCOI::OperandType::OPERAND_FIRST_TARGET: + case MCOI::OperandType::OPERAND_UNKNOWN: { + AssignedValue = MCOperand::createImm(0); + return Error::success(); + } + // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants + // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s() + case llvm::AArch64::OPERAND_MSL_SHIFT_2S: { + // Type 7: Pattern 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF + // Creates 2-element 32-bit vector with 8-bit imm at positions [15:8] & + // [47:40] Shift value 264 (0x108) for Type 7 pattern encoding Corresponds + // to AArch64_AM::encodeAdvSIMDModImmType7() + AssignedValue = MCOperand::createImm(264); + return Error::success(); + } + case llvm::AArch64::OPERAND_MSL_SHIFT_4S: { + // Type 8: Pattern 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF + // Creates 4-element 32-bit vector with 8-bit imm at positions [23:16] & + // [55:48] Shift value 272 (0x110) for Type 8 pattern encoding Corresponds + // to AArch64_AM::encodeAdvSIMDModImmType8() + AssignedValue = MCOperand::createImm(272); + return Error::success(); + } + case MCOI::OperandType::OPERAND_PCREL: + case MCOI::OperandType::OPERAND_FIRST_TARGET: AssignedValue = MCOperand::createImm(0); return Error::success(); default: From 9ae23afff081032f9ffbbd1cdbd06ebc01c31343 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Thu, 14 Aug 2025 01:31:38 -0700 Subject: [PATCH 19/30] [llvm-exegesis] [AArch64] Updated tescase to check introduced OPERAND_TYPES i.e. OPERAND_MSL_SHIFT_4S and OPERAND_MSL_SHIFT_2S --- .../llvm-exegesis/AArch64/error-resolution.s | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s index f51f0ab12d295..30019da11ad0b 100644 --- a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s +++ b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s @@ -23,6 +23,30 @@ # ADDXri_throughput-NEXT: ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0 # ADDXri_throughput: ... + + +// Test for omitting OperandType::OPERAND_MSL_SHIFT_4S + +// MOVIv2s_msl: MOVI vd, #imm{, shift} +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv4s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv4s_msl_latency +# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv4s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv4s_msl_throughput +# MOVIv4s_msl_latency-NOT: Not all operands were initialized by the snippet generator for MOVIv4s_msl opcode + +// TODO: Add test to check if the immediate value is correct when serial execution strategy is added for MOVIv4s_msl + + +# MOVIv4s_msl_throughput-NOT: Not all operands were initialized by the snippet generator for MOVIv4s_msl opcode +# MOVIv4s_msl_throughput: --- +# MOVIv4s_msl_throughput-NEXT: mode: inverse_throughput +# MOVIv4s_msl_throughput-NEXT: key: +# MOVIv4s_msl_throughput-NEXT: instructions: +# MOVIv4s_msl_throughput-NEXT: MOVIv4s_msl [[REG1:Q[0-9]+|LR]] i_0x1 i_0x110 +# MOVIv4s_msl_throughput: ... + + + +// Test for omitting OperandType::OPERAND_MSL_SHIFT_2S + // MOVIv2s_msl: MOVI vd, #imm{, shift} # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_latency # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_throughput From 555ddf767aae3c4f797e3109ee918787793017a4 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Tue, 19 Aug 2025 03:33:00 -0700 Subject: [PATCH 20/30] [AArch64] Introduce single `OPERAND_MSL_SHIFT` for both 2s and 4s opcodes --- .../lib/Target/AArch64/AArch64InstrFormats.td | 45 ++++--------------- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 8 ++-- .../MCTargetDesc/AArch64MCTargetDesc.h | 3 +- 3 files changed, 14 insertions(+), 42 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 5b00a6474ec86..9edebd50843f7 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -1317,21 +1317,11 @@ def logical_vec_hw_shift : Operand { } // A vector move shifter operand: -// {0} - imm1: #8 -def move_vec_shift_2s : Operand { +// {0} - imm1: #8 or #16 +def move_vec_shift : Operand { let OperandNamespace = "AArch64"; let PrintMethod = "printShifter"; - let OperandType = "OPERAND_MSL_SHIFT_2S"; - let ParserMatchClass = MoveVecShifterOperand; - let EncoderMethod = "getMoveVecShifterOpValue"; -} - -// A vector move shifter operand: -// {0} - imm1: #16 -def move_vec_shift_4s : Operand { - let OperandNamespace = "AArch64"; - let PrintMethod = "printShifter"; - let OperandType = "OPERAND_MSL_SHIFT_4S"; + let OperandType = "OPERAND_MSL_SHIFT"; let ParserMatchClass = MoveVecShifterOperand; let EncoderMethod = "getMoveVecShifterOpValue"; } @@ -1573,16 +1563,9 @@ let OperandNamespace = "AArch64" in { defm VectorIndex032b : VectorIndex; } - // Add new aarch64 specific OperandType - let OperandType = "OPERAND_MSL_SHIFT_2S" in { - def msl_shift_2s : Operand { - let PrintMethod = "printImm"; - let ParserMatchClass = MoveVecShifterOperand; - } - } - -let OperandType = "OPERAND_MSL_SHIFT_4S" in { - def msl_shift_4s : Operand { + // MSL shift operand type + let OperandType = "OPERAND_MSL_SHIFT" in { + def msl_shift : Operand { let PrintMethod = "printImm"; let ParserMatchClass = MoveVecShifterOperand; } @@ -8908,26 +8891,16 @@ multiclass SIMDModifiedImmVectorShiftTied hw_cmode, (i32 imm:$shift)))]>; } -class SIMDModifiedImmMoveMSL_2s cmode, +class SIMDModifiedImmMoveMSL cmode, RegisterOperand vectype, string asm, string kind, list pattern> : BaseSIMDModifiedImmVector { - bits<1> shift; - let Inst{15-13} = cmode{3-1}; - let Inst{12} = shift; -} - -class SIMDModifiedImmMoveMSL_4s cmode, - RegisterOperand vectype, string asm, - string kind, list pattern> - : BaseSIMDModifiedImmVector { bits<1> shift; let Inst{15-13} = cmode{3-1}; let Inst{12} = shift; + let Inst{30} = Q; } class SIMDModifiedImmVectorNoShift cmode, diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 64bb509e0cbad..8cfbff938a395 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -8193,10 +8193,10 @@ def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), let isReMaterializable = 1, isAsCheapAsAMove = 1 in { // EDIT per word: 2s & 4s with MSL shifter -def MOVIv2s_msl : SIMDModifiedImmMoveMSL_2s<0, 0, {1,1,0,?}, V64, "movi", ".2s", +def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s", [(set (v2i32 V64:$Rd), (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; -def MOVIv4s_msl : SIMDModifiedImmMoveMSL_4s<1, 0, {1,1,0,?}, V128, "movi", ".4s", +def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s", [(set (v4i32 V128:$Rd), (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>; @@ -8239,10 +8239,10 @@ def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), // EDIT per word: 2s & 4s with MSL shifter let isReMaterializable = 1, isAsCheapAsAMove = 1 in { -def MVNIv2s_msl : SIMDModifiedImmMoveMSL_2s<0, 1, {1,1,0,?}, V64, "mvni", ".2s", +def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s", [(set (v2i32 V64:$Rd), (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; -def MVNIv4s_msl : SIMDModifiedImmMoveMSL_4s<1, 1, {1,1,0,?}, V128, "mvni", ".4s", +def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s", [(set (v4i32 V128:$Rd), (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>; } diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h index 61e5525f3b741..a4f6aa165b0db 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -70,8 +70,7 @@ bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII); namespace AArch64 { enum OperandType { OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET, - OPERAND_MSL_SHIFT_2S, - OPERAND_MSL_SHIFT_4S, + OPERAND_MSL_SHIFT }; } // namespace AArch64 From aa609469211d6dfd53db89a29d9ee9430cc942bb Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Tue, 19 Aug 2025 03:33:42 -0700 Subject: [PATCH 21/30] [AArch64] Update MSL shift handling toopcode specific switch case --- .../llvm-exegesis/lib/AArch64/Target.cpp | 47 ++++++++++++------- 1 file changed, 31 insertions(+), 16 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 9b137ea75f629..a232317f873f8 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -10,7 +10,14 @@ #include "AArch64RegisterInfo.h" #if defined(__aarch64__) && defined(__linux__) -#include // For PR_PAC_* constants +#include // For PR_PAC_* constants +#include +#ifndef PR_PAC_SET_ENABLED_KEYS +#define PR_PAC_SET_ENABLED_KEYS 60 +#endif +#ifndef PR_PAC_GET_ENABLED_KEYS +#define PR_PAC_GET_ENABLED_KEYS 61 +#endif #ifndef PR_PAC_APIAKEY #define PR_PAC_APIAKEY (1UL << 0) #endif @@ -179,21 +186,29 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( } // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s() - case llvm::AArch64::OPERAND_MSL_SHIFT_2S: { - // Type 7: Pattern 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF - // Creates 2-element 32-bit vector with 8-bit imm at positions [15:8] & - // [47:40] Shift value 264 (0x108) for Type 7 pattern encoding Corresponds - // to AArch64_AM::encodeAdvSIMDModImmType7() - AssignedValue = MCOperand::createImm(264); - return Error::success(); - } - case llvm::AArch64::OPERAND_MSL_SHIFT_4S: { - // Type 8: Pattern 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF - // Creates 4-element 32-bit vector with 8-bit imm at positions [23:16] & - // [55:48] Shift value 272 (0x110) for Type 8 pattern encoding Corresponds - // to AArch64_AM::encodeAdvSIMDModImmType8() - AssignedValue = MCOperand::createImm(272); - return Error::success(); + case llvm::AArch64::OPERAND_MSL_SHIFT: { + unsigned Opcode = Instr.getOpcode(); + switch (Opcode) { + case AArch64::MOVIv2s_msl: + case AArch64::MVNIv2s_msl: + // Type 7: Pattern 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF + // Creates 2-element 32-bit vector with 8-bit imm at positions [15:8] & + // [47:40] Shift value 264 (0x108) for Type 7 pattern encoding Corresponds + // to AArch64_AM::encodeAdvSIMDModImmType7() + AssignedValue = MCOperand::createImm(264); + return Error::success(); + case AArch64::MOVIv4s_msl: + case AArch64::MVNIv4s_msl: + // Type 8: Pattern 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF + // Creates 4-element 32-bit vector with 8-bit imm at positions [23:16] & + // [55:48] Shift value 272 (0x110) for Type 8 pattern encoding Corresponds + // to AArch64_AM::encodeAdvSIMDModImmType8() + AssignedValue = MCOperand::createImm(272); + return Error::success(); + default: + return make_error( + Twine("Unsupported MSL shift opcode: ").concat(Twine(Opcode))); + } } case MCOI::OperandType::OPERAND_PCREL: case MCOI::OperandType::OPERAND_FIRST_TARGET: From 6b593fe0edfd873467e1a2e1457fe208145ddbb2 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Tue, 19 Aug 2025 07:44:51 -0700 Subject: [PATCH 22/30] [AArch64] Cleanup unrequired changes --- llvm/lib/Target/AArch64/AArch64InstrFormats.td | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 9edebd50843f7..8f8d648f1fc41 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -1322,8 +1322,8 @@ def move_vec_shift : Operand { let OperandNamespace = "AArch64"; let PrintMethod = "printShifter"; let OperandType = "OPERAND_MSL_SHIFT"; - let ParserMatchClass = MoveVecShifterOperand; let EncoderMethod = "getMoveVecShifterOpValue"; + let ParserMatchClass = MoveVecShifterOperand; } let DiagnosticType = "AddSubSecondSource" in { @@ -1563,13 +1563,6 @@ let OperandNamespace = "AArch64" in { defm VectorIndex032b : VectorIndex; } - // MSL shift operand type - let OperandType = "OPERAND_MSL_SHIFT" in { - def msl_shift : Operand { - let PrintMethod = "printImm"; - let ParserMatchClass = MoveVecShifterOperand; - } - } } defm VectorIndex1 : VectorIndex; From ab92f0f3857d47dfa35f1bd04276bd478521dbf6 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 20 Aug 2025 02:29:33 -0700 Subject: [PATCH 23/30] [llvm-exegesis] [AArch64] Revert redundant PR_PAC_* constants --- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index a232317f873f8..acc2369ac6666 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -10,14 +10,7 @@ #include "AArch64RegisterInfo.h" #if defined(__aarch64__) && defined(__linux__) -#include // For PR_PAC_* constants -#include -#ifndef PR_PAC_SET_ENABLED_KEYS -#define PR_PAC_SET_ENABLED_KEYS 60 -#endif -#ifndef PR_PAC_GET_ENABLED_KEYS -#define PR_PAC_GET_ENABLED_KEYS 61 -#endif +#include // For PR_PAC_* constants #ifndef PR_PAC_APIAKEY #define PR_PAC_APIAKEY (1UL << 0) #endif From dbbed99c1661da6b6709100a8ed9d8430b078c9a Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 20 Aug 2025 06:11:23 -0700 Subject: [PATCH 24/30] [llvm-exegesis] [AArch64] Simplifies shift value for all move_vec_shift to be msl #8 --- .../llvm-exegesis/AArch64/error-resolution.s | 2 +- .../llvm-exegesis/lib/AArch64/Target.cpp | 26 +++++-------------- 2 files changed, 7 insertions(+), 21 deletions(-) diff --git a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s index 30019da11ad0b..d6f6cd778a810 100644 --- a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s +++ b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s @@ -40,7 +40,7 @@ # MOVIv4s_msl_throughput-NEXT: mode: inverse_throughput # MOVIv4s_msl_throughput-NEXT: key: # MOVIv4s_msl_throughput-NEXT: instructions: -# MOVIv4s_msl_throughput-NEXT: MOVIv4s_msl [[REG1:Q[0-9]+|LR]] i_0x1 i_0x110 +# MOVIv4s_msl_throughput-NEXT: MOVIv4s_msl [[REG1:Q[0-9]+|LR]] i_0x1 i_0x108 # MOVIv4s_msl_throughput: ... diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index acc2369ac6666..edd3e62e5a5c6 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -180,28 +180,14 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s() case llvm::AArch64::OPERAND_MSL_SHIFT: { - unsigned Opcode = Instr.getOpcode(); - switch (Opcode) { - case AArch64::MOVIv2s_msl: - case AArch64::MVNIv2s_msl: - // Type 7: Pattern 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF - // Creates 2-element 32-bit vector with 8-bit imm at positions [15:8] & - // [47:40] Shift value 264 (0x108) for Type 7 pattern encoding Corresponds - // to AArch64_AM::encodeAdvSIMDModImmType7() + // There are two valid encodings: + // - Type 7: imm at [15:8], [47:40], shift = 264 (0x108) → msl #8 + // - Type 8: imm at [23:16], [55:48], shift = 272 (0x110) → msl #16 + // Corresponds AArch64_AM::encodeAdvSIMDModImmType7() + // But, v2s_msl and v4s_msl instructions accept either form, + // Thus, Arbitrarily chosing 264 (msl #8) for simplicity. AssignedValue = MCOperand::createImm(264); return Error::success(); - case AArch64::MOVIv4s_msl: - case AArch64::MVNIv4s_msl: - // Type 8: Pattern 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF - // Creates 4-element 32-bit vector with 8-bit imm at positions [23:16] & - // [55:48] Shift value 272 (0x110) for Type 8 pattern encoding Corresponds - // to AArch64_AM::encodeAdvSIMDModImmType8() - AssignedValue = MCOperand::createImm(272); - return Error::success(); - default: - return make_error( - Twine("Unsupported MSL shift opcode: ").concat(Twine(Opcode))); - } } case MCOI::OperandType::OPERAND_PCREL: case MCOI::OperandType::OPERAND_FIRST_TARGET: From bda8043b3307cd0ddbc5cf29c3484fbb536267b2 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 20 Aug 2025 06:17:14 -0700 Subject: [PATCH 25/30] [AArch64] Shifted defination OPERAND_MSL_SHIFT for readability NFC --- .../lib/Target/AArch64/AArch64InstrFormats.td | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 8f8d648f1fc41..c1f51918fbf78 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -1238,6 +1238,17 @@ def timm32_0_255 : Operand, TImmLeaf { + let PrintMethod = "printShifter"; + let OperandNamespace = "AArch64"; + let EncoderMethod = "getMoveVecShifterOpValue"; + let ParserMatchClass = MoveVecShifterOperand; + } +} // let OperandType = "OPERAND_MSL_SHIFT" + // An arithmetic shifter operand: // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr // {5-0} - imm6 @@ -1316,16 +1327,6 @@ def logical_vec_hw_shift : Operand { let ParserMatchClass = LogicalVecHalfWordShifterOperand; } -// A vector move shifter operand: -// {0} - imm1: #8 or #16 -def move_vec_shift : Operand { - let OperandNamespace = "AArch64"; - let PrintMethod = "printShifter"; - let OperandType = "OPERAND_MSL_SHIFT"; - let EncoderMethod = "getMoveVecShifterOpValue"; - let ParserMatchClass = MoveVecShifterOperand; -} - let DiagnosticType = "AddSubSecondSource" in { def AddSubImmOperand : AsmOperandClass { let Name = "AddSubImm"; @@ -8893,7 +8894,6 @@ class SIMDModifiedImmMoveMSL cmode, bits<1> shift; let Inst{15-13} = cmode{3-1}; let Inst{12} = shift; - let Inst{30} = Q; } class SIMDModifiedImmVectorNoShift cmode, From 2d7fc2f32a35492469f6085fdb99177cd991f333 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 20 Aug 2025 06:49:36 -0700 Subject: [PATCH 26/30] clang format --- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index edd3e62e5a5c6..f4ea4d8fdf2bf 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -180,14 +180,14 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s() case llvm::AArch64::OPERAND_MSL_SHIFT: { - // There are two valid encodings: - // - Type 7: imm at [15:8], [47:40], shift = 264 (0x108) → msl #8 - // - Type 8: imm at [23:16], [55:48], shift = 272 (0x110) → msl #16 - // Corresponds AArch64_AM::encodeAdvSIMDModImmType7() - // But, v2s_msl and v4s_msl instructions accept either form, - // Thus, Arbitrarily chosing 264 (msl #8) for simplicity. - AssignedValue = MCOperand::createImm(264); - return Error::success(); + // There are two valid encodings: + // - Type 7: imm at [15:8], [47:40], shift = 264 (0x108) → msl #8 + // - Type 8: imm at [23:16], [55:48], shift = 272 (0x110) → msl #16 + // Corresponds AArch64_AM::encodeAdvSIMDModImmType7() + // But, v2s_msl and v4s_msl instructions accept either form, + // Thus, Arbitrarily chosing 264 (msl #8) for simplicity. + AssignedValue = MCOperand::createImm(264); + return Error::success(); } case MCOI::OperandType::OPERAND_PCREL: case MCOI::OperandType::OPERAND_FIRST_TARGET: From 93ec6498dbfa2deae4979debbe433e356618048b Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Tue, 26 Aug 2025 05:52:30 -0700 Subject: [PATCH 27/30] [AArch64] Refactor move_vec_shift operand def and update operand type handling and testcase --- .../lib/Target/AArch64/AArch64InstrFormats.td | 21 ++++++++--------- .../MCTargetDesc/AArch64MCTargetDesc.h | 2 +- .../llvm-exegesis/AArch64/error-resolution.s | 23 ------------------- .../llvm-exegesis/lib/AArch64/Target.cpp | 8 ++----- .../llvm-exegesis/lib/SnippetGenerator.cpp | 4 +--- 5 files changed, 14 insertions(+), 44 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index c1f51918fbf78..c925d41511a23 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -1238,17 +1238,6 @@ def timm32_0_255 : Operand, TImmLeaf { - let PrintMethod = "printShifter"; - let OperandNamespace = "AArch64"; - let EncoderMethod = "getMoveVecShifterOpValue"; - let ParserMatchClass = MoveVecShifterOperand; - } -} // let OperandType = "OPERAND_MSL_SHIFT" - // An arithmetic shifter operand: // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr // {5-0} - imm6 @@ -1327,6 +1316,16 @@ def logical_vec_hw_shift : Operand { let ParserMatchClass = LogicalVecHalfWordShifterOperand; } +// A vector move shifter operand: +// {0} - imm1: #8 or #16 +def move_vec_shift : Operand { + let PrintMethod = "printShifter"; + let EncoderMethod = "getMoveVecShifterOpValue"; + let ParserMatchClass = MoveVecShifterOperand; + let OperandType = "OPERAND_SHIFT_MSL"; + let OperandNamespace = "AArch64"; +} + let DiagnosticType = "AddSubSecondSource" in { def AddSubImmOperand : AsmOperandClass { let Name = "AddSubImm"; diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h index a4f6aa165b0db..7774d07a214bf 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -70,7 +70,7 @@ bool isFpOrNEON(const MCInst &MI, const MCInstrInfo *MCII); namespace AArch64 { enum OperandType { OPERAND_IMPLICIT_IMM_0 = MCOI::OPERAND_FIRST_TARGET, - OPERAND_MSL_SHIFT + OPERAND_SHIFT_MSL, }; } // namespace AArch64 diff --git a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s index d6f6cd778a810..e7a3243eb3817 100644 --- a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s +++ b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s @@ -2,29 +2,6 @@ -// Test for omitting OperandType::OPERAND_UNKNOWN - -// ADDXri: ADD Xd, Xn, #imm{, shift} -# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=ADDXri 2>&1 | FileCheck %s --check-prefix=ADDXri_latency -# ADDXri_latency-NOT: Not all operands were initialized by the snippet generator for ADDXri opcode -# ADDXri_latency: --- -# ADDXri_latency-NEXT: mode: latency -# ADDXri_latency-NEXT: key: -# ADDXri_latency-NEXT: instructions: -# ADDXri_latency-NEXT: ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0 -# ADDXri_latency: ... - -# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=ADDXri 2>&1 | FileCheck %s --check-prefix=ADDXri_throughput -# ADDXri_throughput-NOT: Not all operands were initialized by the snippet generator for ADDXri opcode -# ADDXri_throughput: --- -# ADDXri_throughput-NEXT: mode: inverse_throughput -# ADDXri_throughput-NEXT: key: -# ADDXri_throughput-NEXT: instructions: -# ADDXri_throughput-NEXT: ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0 -# ADDXri_throughput: ... - - - // Test for omitting OperandType::OPERAND_MSL_SHIFT_4S // MOVIv2s_msl: MOVI vd, #imm{, shift} diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index f4ea4d8fdf2bf..8198aada6ba4e 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -173,13 +173,9 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( // encodings or unreliable benchmark results for these system-level // instructions. switch (OperandType) { - case MCOI::OperandType::OPERAND_UNKNOWN: { - AssignedValue = MCOperand::createImm(0); - return Error::success(); - } // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s() - case llvm::AArch64::OPERAND_MSL_SHIFT: { + case llvm::AArch64::OPERAND_SHIFT_MSL: { // There are two valid encodings: // - Type 7: imm at [15:8], [47:40], shift = 264 (0x108) → msl #8 // - Type 8: imm at [23:16], [55:48], shift = 272 (0x110) → msl #16 @@ -189,8 +185,8 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( AssignedValue = MCOperand::createImm(264); return Error::success(); } + case llvm::AArch64::OPERAND_IMPLICIT_IMM_0: case MCOI::OperandType::OPERAND_PCREL: - case MCOI::OperandType::OPERAND_FIRST_TARGET: AssignedValue = MCOperand::createImm(0); return Error::success(); default: diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp index 156739bd9de34..7023f1bfae193 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp @@ -276,9 +276,7 @@ static Error randomizeMCOperand(const LLVMState &State, AssignedValue = MCOperand::createReg(randomBit(AllowedRegs)); break; } - /// Omit unknown and pc-relative operands to imm value based on the - /// instruction - case MCOI::OperandType::OPERAND_UNKNOWN: + /// Omit pc-relative operands to imm value based on the instruction case MCOI::OperandType::OPERAND_PCREL: return State.getExegesisTarget().randomizeTargetMCOperand( Instr, Var, AssignedValue, ForbiddenRegs); From 9787b4d8ea7cf1772474fd2cfa236bdff02c7ec7 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Wed, 27 Aug 2025 08:09:37 -0700 Subject: [PATCH 28/30] [[lvm-exegesis] [AArch64] Updated PCREL imm value to 8 and Updated comments. --- .../llvm-exegesis/AArch64/error-resolution.s | 10 +++------- .../llvm-exegesis/lib/AArch64/Target.cpp | 20 +++++++++++++------ 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s index e7a3243eb3817..168cc585e6532 100644 --- a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s +++ b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s @@ -2,7 +2,7 @@ -// Test for omitting OperandType::OPERAND_MSL_SHIFT_4S +// Test for omitting OperandType::OPERAND_SHIFT_MSL // MOVIv2s_msl: MOVI vd, #imm{, shift} # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv4s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv4s_msl_latency @@ -20,10 +20,6 @@ # MOVIv4s_msl_throughput-NEXT: MOVIv4s_msl [[REG1:Q[0-9]+|LR]] i_0x1 i_0x108 # MOVIv4s_msl_throughput: ... - - -// Test for omitting OperandType::OPERAND_MSL_SHIFT_2S - // MOVIv2s_msl: MOVI vd, #imm{, shift} # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_latency # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_throughput @@ -54,12 +50,12 @@ # LDRDl_throughput-NEXT: mode: inverse_throughput # LDRDl_throughput-NEXT: key: # LDRDl_throughput-NEXT: instructions: -# LDRDl_throughput-NEXT: LDRDl [[REG1:D[0-9]+|LR]] i_0x0 +# LDRDl_throughput-NEXT: LDRDl [[REG1:D[0-9]+|LR]] i_0x8 # LDRDl_throughput: ... -// Test for omitting OperandType::OPERAND_FIRST_TARGET +// Test for omitting OperandType::OPERAND_IMPLICIT_IMM_0 // UMOVvi16_idx0: UMOV wd, vn.h[index] # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_latency diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 8198aada6ba4e..36ff44e00b084 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -161,17 +161,23 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( const BitVector &ForbiddenRegs) const { const Operand &Op = Instr.getPrimaryOperand(Var); const auto OperandType = Op.getExplicitOperandInfo().OperandType; - // FIXME: Implement opcode-specific immediate value handling for system - // instructions: + // NOTE: To resolve "Not all operands were initialized by snippet generator" + // Requires OperandType to be defined for such opcode's operands in AArch64 + // tablegen files. And omit introduced OperandType(s). + + // Hacky temporary fix works by defaulting all OPERAND_UNKNOWN to + // immediate value 0, but this introduce illegal instruction error for below + // system instructions will need to be omitted with OperandType or opcode + // specific values to avoid generating invalid encodings or unreliable + // benchmark results for these system-level instructions. + // Implement opcode-specific immediate value handling for system instrs: // - MRS/MSR: Use valid system register encodings (e.g., NZCV, FPCR, FPSR) // - MSRpstatesvcrImm1: Use valid PSTATE field encodings (e.g., SPSel, // DAIFSet) // - SYSLxt/SYSxt: Use valid system instruction encodings with proper // CRn/CRm/op values // - UDF: Use valid undefined instruction immediate ranges (0-65535) - // Currently defaulting to immediate value 0, which may cause invalid - // encodings or unreliable benchmark results for these system-level - // instructions. + switch (OperandType) { // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s() @@ -186,9 +192,11 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( return Error::success(); } case llvm::AArch64::OPERAND_IMPLICIT_IMM_0: - case MCOI::OperandType::OPERAND_PCREL: AssignedValue = MCOperand::createImm(0); return Error::success(); + case MCOI::OperandType::OPERAND_PCREL: + AssignedValue = MCOperand::createImm(8); + return Error::success(); default: break; } From ac072288bcb05c7561f2e8b5967a2f36a425754a Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Tue, 2 Sep 2025 01:30:11 -0700 Subject: [PATCH 29/30] [llvm-exegesis] [AArch64] Correct UMOVvi16_idx0 latency testcase --- .../tools/llvm-exegesis/AArch64/error-resolution.s | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s index 168cc585e6532..66ca6fb31d78f 100644 --- a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s +++ b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s @@ -61,15 +61,9 @@ # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_latency # RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_throughput -# UMOVvi16_idx0_latency-NOT: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode -# UMOVvi16_idx0_latency: --- -# UMOVvi16_idx0_latency-NEXT: mode: latency -# UMOVvi16_idx0_latency-NEXT: key: -# UMOVvi16_idx0_latency-NEXT: instructions: -# UMOVvi16_idx0_latency-NEXT: UMOVvi16_idx0 [[REG1:W[0-9]+|LR]] [[REG2:Q[0-9]+|LR]] i_0x0 -# UMOVvi16_idx0_latency: ... - -# UMOVvi16_idx0_throughput-NOT: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode +# UMOVvi16_idx0_latency-NOT: UMOVvi16_idx0: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode. + +# UMOVvi16_idx0_throughput-NOT: UMOVvi16_idx0: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode. # UMOVvi16_idx0_throughput: --- # UMOVvi16_idx0_throughput-NEXT: mode: inverse_throughput # UMOVvi16_idx0_throughput-NEXT: key: From a5c23a37a9f81dff8b5dbf60b2ace705ddb25d34 Mon Sep 17 00:00:00 2001 From: lakshayk-nv Date: Tue, 2 Sep 2025 21:51:23 -0700 Subject: [PATCH 30/30] [llvm-exegesis] [AArch64] Fixed comment clarity on hacky fix by omitting OPERAND_UNKNOWN --- llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp index 36ff44e00b084..76b642ca8d3e1 100644 --- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp @@ -165,11 +165,11 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand( // Requires OperandType to be defined for such opcode's operands in AArch64 // tablegen files. And omit introduced OperandType(s). - // Hacky temporary fix works by defaulting all OPERAND_UNKNOWN to - // immediate value 0, but this introduce illegal instruction error for below - // system instructions will need to be omitted with OperandType or opcode - // specific values to avoid generating invalid encodings or unreliable - // benchmark results for these system-level instructions. + // Hacky Fix: Defaulting all OPERAND_UNKNOWN to immediate value 0 works with a + // limitation that it introduces illegal instruction error for system + // instructions. System instructions will need to be omitted with OperandType + // or opcode specific values to avoid generating invalid encodings or + // unreliable benchmark results for these system-level instructions. // Implement opcode-specific immediate value handling for system instrs: // - MRS/MSR: Use valid system register encodings (e.g., NZCV, FPCR, FPSR) // - MSRpstatesvcrImm1: Use valid PSTATE field encodings (e.g., SPSel,