From b5ab7a90291f046bc0c0bfd1825916a655d0ca3c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 5 Sep 2025 18:11:53 +0900 Subject: [PATCH] PPC: Move definitions of predicates with features The way this was previously structured does not allow access to the predicates inside of PPCRegisterInfo --- llvm/lib/Target/PowerPC/PPC.td | 37 +++++++++++++++++++++++++ llvm/lib/Target/PowerPC/PPCInstrInfo.td | 36 ------------------------ 2 files changed, 37 insertions(+), 36 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index ea7c2203662bd..db6427cfe8482 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -353,6 +353,43 @@ def FeaturePredictableSelectIsExpensive : def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true", "MFLR is a fast instruction">; +//===----------------------------------------------------------------------===// +// PowerPC Instruction Predicate Definitions. +def In32BitMode : Predicate<"!Subtarget->isPPC64()">; +def In64BitMode : Predicate<"Subtarget->isPPC64()">; +def IsBookE : Predicate<"Subtarget->isBookE()">; +def IsNotBookE : Predicate<"!Subtarget->isBookE()">; +def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; +def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; +def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; +def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; +def IsE500 : Predicate<"Subtarget->isE500()">; +def HasSPE : Predicate<"Subtarget->hasSPE()">; +def HasICBT : Predicate<"Subtarget->hasICBT()">; +def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; +def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; +def NoNaNsFPMath + : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; +def NaNsFPMath + : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; +def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; +def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; +def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; +def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; +def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; +def HasFPU : Predicate<"Subtarget->hasFPU()">; +def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; +def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; + +// AIX assembler may not be modern enough to support some extended mne. +def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, + AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; +def IsAIX : Predicate<"Subtarget->isAIXABI()">; +def NotAIX : Predicate<"!Subtarget->isAIXABI()">; +def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; +def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; + + // Since new processors generally contain a superset of features of those that // came before them, the idea is to make implementations of new processors // less error prone and easier to read. diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index c12cf85113128..1c45050cdf9ca 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -713,42 +713,6 @@ let WantsParent = true in { def PDForm : ComplexPattern; } -//===----------------------------------------------------------------------===// -// PowerPC Instruction Predicate Definitions. -def In32BitMode : Predicate<"!Subtarget->isPPC64()">; -def In64BitMode : Predicate<"Subtarget->isPPC64()">; -def IsBookE : Predicate<"Subtarget->isBookE()">; -def IsNotBookE : Predicate<"!Subtarget->isBookE()">; -def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; -def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; -def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; -def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; -def IsE500 : Predicate<"Subtarget->isE500()">; -def HasSPE : Predicate<"Subtarget->hasSPE()">; -def HasICBT : Predicate<"Subtarget->hasICBT()">; -def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; -def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; -def NoNaNsFPMath - : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; -def NaNsFPMath - : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; -def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; -def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; -def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; -def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; -def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; -def HasFPU : Predicate<"Subtarget->hasFPU()">; -def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; -def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; - -// AIX assembler may not be modern enough to support some extended mne. -def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, - AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; -def IsAIX : Predicate<"Subtarget->isAIXABI()">; -def NotAIX : Predicate<"!Subtarget->isAIXABI()">; -def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; -def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; - //===----------------------------------------------------------------------===// // PowerPC Multiclass Definitions. multiclass XForm_base_r3xo_r opcode, bits<10> xo, dag OOL, dag IOL,