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+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+====================================================================================
+Syntax of GFX12 Instructions
+====================================================================================
+
+.. contents::
+  :local:
+
+Introduction
+============
+
+This document describes the syntax of GFX12 instructions.
+
+Notation
+========
+
+Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
+
+Overview
+========
+
+An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.
+
+Instructions
+============
+
+
+SMEM
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                **DST**      **SRC0**     **SRC1**     **SRC2**     **SRC3**          **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_atc_probe                :ref:`sdata<amdgpu_synid_gfx12_sdata_d725ab>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_atc_probe_buffer         :ref:`sdata<amdgpu_synid_gfx12_sdata_d725ab>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_load_b128         :ref:`sdata<amdgpu_synid_gfx12_sdata_4585b8>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_load_b256         :ref:`sdata<amdgpu_synid_gfx12_sdata_0974a4>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_load_b32          :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_load_b512         :ref:`sdata<amdgpu_synid_gfx12_sdata_6c003b>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_load_b64          :ref:`sdata<amdgpu_synid_gfx12_sdata_354189>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_load_b96          :ref:`sdata<amdgpu_synid_gfx12_sdata_dd9dd8>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_load_i16          :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_load_i8           :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_load_u16          :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_load_u8           :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_nop                                                                 :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_buffer_prefetch_data              :ref:`sbase<amdgpu_synid_gfx12_sbase_453b95>`,   :ref:`ioffset<amdgpu_synid_gfx12_ioffset>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_8ec073>`, :ref:`sdata<amdgpu_synid_gfx12_sdata_5c7b50>`         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_dcache_inv                                                                 :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_load_b128                :ref:`sdata<amdgpu_synid_gfx12_sdata_4585b8>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_load_b256                :ref:`sdata<amdgpu_synid_gfx12_sdata_0974a4>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_load_b32                 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_load_b512                :ref:`sdata<amdgpu_synid_gfx12_sdata_6c003b>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_load_b64                 :ref:`sdata<amdgpu_synid_gfx12_sdata_354189>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_load_b96                 :ref:`sdata<amdgpu_synid_gfx12_sdata_dd9dd8>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_load_i16                 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_load_i8                  :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_load_u16                 :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_load_u8                  :ref:`sdata<amdgpu_synid_gfx12_sdata_836716>`,   :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`                         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_prefetch_data                     :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`ioffset<amdgpu_synid_gfx12_ioffset>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`, :ref:`sdata<amdgpu_synid_gfx12_sdata_5c7b50>`         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_prefetch_data_pc_rel              :ref:`ioffset<amdgpu_synid_gfx12_ioffset>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`, :ref:`sdata<amdgpu_synid_gfx12_sdata_5c7b50>`                  :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_prefetch_inst                     :ref:`sbase<amdgpu_synid_gfx12_sbase_47adb7>`,   :ref:`ioffset<amdgpu_synid_gfx12_ioffset>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`, :ref:`sdata<amdgpu_synid_gfx12_sdata_5c7b50>`         :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    s_prefetch_inst_pc_rel              :ref:`ioffset<amdgpu_synid_gfx12_ioffset>`, :ref:`soffset<amdgpu_synid_gfx12_soffset_ec005a>`, :ref:`sdata<amdgpu_synid_gfx12_sdata_5c7b50>`                  :ref:`offset24s<amdgpu_synid_smem_offset24s>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+
+SOP1
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_abs_i32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_alloc_vgpr                             :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_and_not0_saveexec_b32        :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_and_not0_saveexec_b64        :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_and_not0_wrexec_b32          :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_and_not0_wrexec_b64          :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_and_not1_saveexec_b32        :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_and_not1_saveexec_b64        :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_and_not1_wrexec_b32          :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_and_not1_wrexec_b64          :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_and_saveexec_b32             :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_and_saveexec_b64             :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_barrier_init                           :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+    s_barrier_join                           :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+    s_barrier_signal                         :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+    s_barrier_signal_isfirst                 :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+    s_bcnt0_i32_b32                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_bcnt0_i32_b64                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_bcnt1_i32_b32                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_bcnt1_i32_b64                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_bitreplicate_b64_b32         :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_bitset0_b32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_bitset0_b64                  :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_bitset1_b32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_bitset1_b64                  :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_brev_b32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_brev_b64                     :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_ceil_f16                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_ceil_f32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_cls_i32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_cls_i32_i64                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_clz_i32_u32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_clz_i32_u64                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_cmov_b32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_cmov_b64                     :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_ctz_i32_b32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_ctz_i32_b64                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_cvt_f16_f32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_cvt_f32_f16                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_cvt_f32_i32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_cvt_f32_u32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_cvt_hi_f32_f16               :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_cvt_i32_f32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_cvt_u32_f32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_floor_f16                    :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_floor_f32                    :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_get_barrier_state            :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+    s_get_lock_state               :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+    s_getpc_b64                    :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`
+    s_mov_b32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_mov_b64                      :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_mov_fed_b32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_mov_from_global_b32          :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_007f9c>`
+    s_mov_from_global_b64          :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_2797bc>`
+    s_mov_regrd_b32                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_mov_to_global_b32            :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_mov_to_global_b64            :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_movreld_b32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_movreld_b64                  :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_movrels_b32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_007f9c>`
+    s_movrels_b64                  :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_2797bc>`
+    s_movrelsd_2_b32               :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_007f9c>`
+    s_nand_saveexec_b32            :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_nand_saveexec_b64            :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_nor_saveexec_b32             :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_nor_saveexec_b64             :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_not_b32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_not_b64                      :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_or_not0_saveexec_b32         :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_or_not0_saveexec_b64         :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_or_not1_saveexec_b32         :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_or_not1_saveexec_b64         :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_or_saveexec_b32              :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_or_saveexec_b64              :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_quadmask_b32                 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_quadmask_b64                 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_rfe_b64                                :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_2797bc>`
+    s_rndne_f16                    :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_rndne_f32                    :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_sendmsg_rtn_b32              :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_245536>`
+    s_sendmsg_rtn_b64              :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_245536>`
+    s_setpc_b64                              :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_2797bc>`
+    s_sext_i32_i16                 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_sext_i32_i8                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_sleep_var                              :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_swap_to_global_b32           :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_007f9c>`
+    s_swappc_b64                   :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_2797bc>`
+    s_trunc_f16                    :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_trunc_f32                    :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_try_lock                               :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+    s_unlock                                 :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+    s_wakeup_barrier                         :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_1a9ca5>`
+    s_wqm_b32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_wqm_b64                      :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_xnor_saveexec_b32            :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_xnor_saveexec_b64            :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+    s_xor_saveexec_b32             :ref:`sdst<amdgpu_synid_gfx12_sdst_836716>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`
+    s_xor_saveexec_b64             :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`
+
+SOP2
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_absdiff_i32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_add_co_ci_u32                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_add_co_i32                   :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_add_co_u32                   :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_add_f16                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_add_f32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_add_nc_u64                   :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_and_b32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_and_b64                      :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_and_not1_b32                 :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_and_not1_b64                 :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_ashr_i32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_ashr_i64                     :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_bfe_i32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_bfe_i64                      :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_bfe_u32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_bfe_u64                      :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_bfm_b32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_bfm_b64                      :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cselect_b32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cselect_b64                  :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_cvt_pk_rtz_f16_f32           :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_fmaak_f32                    :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`,    :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    s_fmac_f16                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_fmac_f32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_fmamk_f32                    :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`,  :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_lshl1_add_u32                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_lshl2_add_u32                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_lshl3_add_u32                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_lshl4_add_u32                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_lshl_b32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_lshl_b64                     :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_lshr_b32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_lshr_b64                     :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_max_i32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_max_num_f16                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_max_num_f32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_max_u32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_maximum_f16                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_maximum_f32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_min_i32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_min_num_f16                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_min_num_f32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_min_u32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_minimum_f16                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_minimum_f32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_mul_f16                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_mul_f32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_mul_hi_i32                   :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_mul_hi_u32                   :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_mul_i32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_mul_u64                      :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_nand_b32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_nand_b64                     :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_nor_b32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_nor_b64                      :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_or_b32                       :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_or_b64                       :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_or_not1_b32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_or_not1_b64                  :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_pack_hh_b32_b16              :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_pack_hl_b32_b16              :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_pack_lh_b32_b16              :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_pack_ll_b32_b16              :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_sub_co_ci_u32                :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_sub_co_i32                   :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_sub_co_u32                   :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_sub_f16                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_sub_f32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_sub_nc_u64                   :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_xnor_b32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_xnor_b64                     :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_xor_b32                      :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_xor_b64                      :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+
+SOPC
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_bitcmp0_b32                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_bitcmp0_b64                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_bitcmp1_b32                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_bitcmp1_b64                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_eq_f16                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_eq_f32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_eq_i32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_eq_u32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_eq_u64                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_cmp_ge_f16                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_ge_f32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_ge_i32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_ge_u32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_gt_f16                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_gt_f32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_gt_i32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_gt_u32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_le_f16                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_le_f32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_le_i32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_le_u32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_lg_f16                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_lg_f32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_lg_i32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_lg_u32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_lg_u64                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_bbb4c6>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_bbb4c6>`
+    s_cmp_lt_f16                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_lt_f32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_lt_i32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_lt_u32                   :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_neq_f16                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_neq_f32                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_nge_f16                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_nge_f32                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_ngt_f16                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_ngt_f32                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_nle_f16                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_nle_f32                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_nlg_f16                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_nlg_f32                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_nlt_f16                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_nlt_f32                  :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_o_f16                    :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_o_f32                    :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_u_f16                    :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+    s_cmp_u_f32                    :ref:`ssrc0<amdgpu_synid_gfx12_ssrc0_c4593f>`,    :ref:`ssrc1<amdgpu_synid_gfx12_ssrc1_c4593f>`
+
+SOPK
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_addk_co_i32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_call_b64                     :ref:`sdst<amdgpu_synid_gfx12_sdst_354189>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cmovk_i32                    :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_eq_i32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_eq_u32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_ge_i32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_ge_u32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_gt_i32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_gt_u32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_le_i32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_le_u32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_lg_i32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_lg_u32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_lt_i32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_cmpk_lt_u32                  :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_getreg_b32                   :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_7ed651>`
+    s_getreg_regrd_b32             :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_7ed651>`
+    s_movk_i32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_mulk_i32                     :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_setreg_b32                   :ref:`simm16<amdgpu_synid_gfx12_simm16_cc1716>`,   :ref:`sdst<amdgpu_synid_gfx12_sdst_20064d>`
+    s_setreg_imm32_b32             :ref:`simm16<amdgpu_synid_gfx12_simm16_cc1716>`,   :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    s_subvector_loop_begin         :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_subvector_loop_end           :ref:`sdst<amdgpu_synid_gfx12_sdst_ced58d>`,     :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_version                                :ref:`simm16<amdgpu_synid_gfx12_simm16_15ccdd>`
+
+SOPP
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **SRC**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    s_barrier
+    s_barrier_leave
+    s_barrier_wait                 :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_branch                       :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cbranch_cdbgsys              :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cbranch_cdbgsys_and_user     :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cbranch_cdbgsys_or_user      :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cbranch_cdbguser             :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cbranch_execnz               :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cbranch_execz                :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cbranch_scc0                 :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cbranch_scc1                 :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cbranch_vccnz                :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_cbranch_vccz                 :ref:`simm16<amdgpu_synid_gfx12_simm16_3d2a4f>`
+    s_clause                       :ref:`simm16<amdgpu_synid_gfx12_simm16_730a13>`
+    s_code_end
+    s_decperflevel                 :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_delay_alu                    :ref:`simm16<amdgpu_synid_gfx12_simm16_c98889>`
+    s_denorm_mode                  :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_endpgm
+    s_endpgm_ordered_ps_done
+    s_endpgm_saved
+    s_icache_inv
+    s_incperflevel                 :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_nop                          :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_round_mode                   :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_sendmsg                      :ref:`simm16<amdgpu_synid_gfx12_simm16_ee8b30>`
+    s_sendmsghalt                  :ref:`simm16<amdgpu_synid_gfx12_simm16_ee8b30>`
+    s_set_inst_prefetch_distance   :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_sethalt                      :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_setkill                      :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_setprio                      :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_singleuse_vdst               :ref:`simm16<amdgpu_synid_gfx12_simm16_81e671>`
+    s_sleep                        :ref:`simm16<amdgpu_synid_gfx12_simm16_81e671>`
+    s_trap                         :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_ttracedata
+    s_ttracedata_imm               :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_wait_alu                     :ref:`simm16<amdgpu_synid_gfx12_simm16_81e671>`
+    s_wait_bvhcnt                  :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_wait_dscnt                   :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_wait_event                   :ref:`simm16<amdgpu_synid_gfx12_simm16_81e671>`
+    s_wait_expcnt                  :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_wait_idle
+    s_wait_kmcnt                   :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_wait_loadcnt                 :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_wait_loadcnt_dscnt           :ref:`simm16<amdgpu_synid_gfx12_simm16_81e671>`
+    s_wait_samplecnt               :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_wait_storecnt                :ref:`simm16<amdgpu_synid_gfx12_simm16_39b593>`
+    s_wait_storecnt_dscnt          :ref:`simm16<amdgpu_synid_gfx12_simm16_81e671>`
+    s_waitcnt                      :ref:`simm16<amdgpu_synid_gfx12_simm16_218bea>`
+    s_wakeup
+
+VBUFFER
+-------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                     **DST**      **SRC0**     **SRC1**     **SRC2**      **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    buffer_atomic_add_f32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_add_u32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_add_u64           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_and_b32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_and_b64           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_cmpswap_b32       :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_cmpswap_b64       :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_cond_sub_u32      :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_dec_u32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_dec_u64           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_inc_u32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_inc_u64           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_max_i32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_max_i64           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_max_num_f32       :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_max_u32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_max_u64           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_min_i32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_min_i64           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_min_num_f32       :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_min_u32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_min_u64           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_or_b32            :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_or_b64            :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_pk_add_bf16       :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_pk_add_f16        :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_sub_clamp_u32     :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_sub_u32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_sub_u64           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_swap_b32          :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_swap_b64          :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_xor_b32           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_atomic_xor_b64           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_gl0_inv                                                       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_gl1_inv                                                       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_b128                :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_b32                 :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_b64                 :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_b96                 :ref:`vdata<amdgpu_synid_gfx12_vdata_48e42f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_block               :ref:`vdata<amdgpu_synid_gfx12_vdata_2eda77>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_b16             :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_format_x        :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_format_xy       :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_format_xyz      :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_format_xyzw     :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_hi_b16          :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_hi_format_x     :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_hi_i8           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_hi_u8           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_i8              :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_d16_u8              :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_format_x            :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_format_xy           :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_format_xyz          :ref:`vdata<amdgpu_synid_gfx12_vdata_48e42f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_format_xyzw         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_i16                 :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_i8                  :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_lds_b32                      :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_lds_format_x                 :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_lds_i16                      :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_lds_i8                       :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_lds_u16                      :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_lds_u8                       :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_u16                 :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_load_u8                  :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_nop                                                           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_b128               :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_b16                :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_b32                :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_b64                :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_b8                 :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_b96                :ref:`vdata<amdgpu_synid_gfx12_vdata_48e42f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_block              :ref:`vdata<amdgpu_synid_gfx12_vdata_2eda77>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_d16_format_x       :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_d16_format_xy      :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_d16_format_xyz     :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_d16_format_xyzw    :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_d16_hi_b16         :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_d16_hi_b8          :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_d16_hi_format_x    :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_format_x           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_format_xy          :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_format_xyz         :ref:`vdata<amdgpu_synid_gfx12_vdata_48e42f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    buffer_store_format_xyzw        :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_load_d16_format_x       :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_load_d16_format_xy      :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_load_d16_format_xyz     :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_load_d16_format_xyzw    :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_load_format_x           :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_load_format_xy          :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_load_format_xyz         :ref:`vdata<amdgpu_synid_gfx12_vdata_48e42f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_load_format_xyzw        :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_store_d16_format_x      :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_store_d16_format_xy     :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_store_d16_format_xyz    :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_store_d16_format_xyzw   :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_store_format_x          :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_store_format_xy         :ref:`vdata<amdgpu_synid_gfx12_vdata_bdb32f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_store_format_xyz        :ref:`vdata<amdgpu_synid_gfx12_vdata_48e42f>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    tbuffer_store_format_xyzw       :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,   :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,   :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`,    :ref:`soffset<amdgpu_synid_gfx12_soffset_c5b88c>`   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+
+VDS
+---
+
+.. parsed-literal::
+
+    **INSTRUCTION**                             **DST**       **SRC0**      **SRC1**      **SRC2**        **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    ds_add_f32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_add_f64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_add_rtn_f32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_add_rtn_u32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_add_rtn_u64                          :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_add_u32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_add_u64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_and_b32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_and_b64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_and_rtn_b32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_and_rtn_b64                          :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_append                               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`                                      :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bpermute_b32                         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bpermute_fi_b32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bpermute_fi_from_global_b32          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bpermute_fi_to_global_b32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bpermute_fi_to_simd_b32              :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bpermute_from_global_b32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bpermute_to_global_b32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bpermute_to_simd_b32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bvh_stack_push4_pop1_rtn_b32         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_e016a1>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bvh_stack_push8_pop1_rtn_b32         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_731030>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_bvh_stack_push8_pop2_rtn_b64         :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_731030>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_cmpstore_b32                                   :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_6802ce>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_cmpstore_b64                                   :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`,    :ref:`data1<amdgpu_synid_gfx12_data1_fd235e>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_cmpstore_rtn_b32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_6802ce>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_cmpstore_rtn_b64                     :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`,    :ref:`data1<amdgpu_synid_gfx12_data1_fd235e>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_cond_sub_rtn_u32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_cond_sub_u32                                   :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_condxchg32_rtn_b64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_consume                              :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`                                      :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_dec_rtn_u32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_dec_rtn_u64                          :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_dec_u32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_dec_u64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_inc_rtn_u32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_inc_rtn_u64                          :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_inc_u32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_inc_u64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_2addr_b32                       :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_2addr_b64                       :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_2addr_stride64_b32              :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_2addr_stride64_b64              :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_addtid_b32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`                                      :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_b128                            :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_b32                             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_b64                             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_b96                             :ref:`vdst<amdgpu_synid_gfx12_vdst_48e42f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_i16                             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_i8                              :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_i8_d16                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_i8_d16_hi                       :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_u16                             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_u16_d16                         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_u16_d16_hi                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_u8                              :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_u8_d16                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_load_u8_d16_hi                       :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_i32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_i64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_num_f32                                    :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_num_f64                                    :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_num_rtn_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_num_rtn_f64                      :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_rtn_i32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_rtn_i64                          :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_rtn_u32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_rtn_u64                          :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_u32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_max_u64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_i32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_i64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_num_f32                                    :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_num_f64                                    :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_num_rtn_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_num_rtn_f64                      :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_rtn_i32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_rtn_i64                          :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_rtn_u32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_rtn_u64                          :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_u32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_min_u64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_mskor_b32                                      :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_6802ce>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_mskor_b64                                      :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`,    :ref:`data1<amdgpu_synid_gfx12_data1_fd235e>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_mskor_rtn_b32                        :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_6802ce>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_mskor_rtn_b64                        :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`,    :ref:`data1<amdgpu_synid_gfx12_data1_fd235e>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_nop                                                                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_or_b32                                         :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_or_b64                                         :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_or_rtn_b32                           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_or_rtn_b64                           :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_permute_b32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_permute_from_global_b32              :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_permute_to_global_b32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_permute_to_simd_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_pk_add_bf16                                    :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_pk_add_f16                                     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_pk_add_rtn_bf16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_pk_add_rtn_f16                       :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_rsub_rtn_u32                         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_rsub_rtn_u64                         :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_rsub_u32                                       :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_rsub_u64                                       :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_2addr_b32                                :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_6802ce>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_2addr_b64                                :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`,    :ref:`data1<amdgpu_synid_gfx12_data1_fd235e>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_2addr_stride64_b32                       :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_6802ce>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_2addr_stride64_b64                       :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`,    :ref:`data1<amdgpu_synid_gfx12_data1_fd235e>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_addtid_b32                               :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_b128                                     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_e016a1>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_b16                                      :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_b16_d16_hi                               :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_b32                                      :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_b64                                      :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_b8                                       :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_b8_d16_hi                                :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_store_b96                                      :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_56f215>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_storexchg_2addr_rtn_b32              :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_6802ce>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_storexchg_2addr_rtn_b64              :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`,    :ref:`data1<amdgpu_synid_gfx12_data1_fd235e>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_storexchg_2addr_stride64_rtn_b32     :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_6802ce>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_storexchg_2addr_stride64_rtn_b64     :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`,    :ref:`data1<amdgpu_synid_gfx12_data1_fd235e>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_storexchg_rtn_b32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_storexchg_rtn_b64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_sub_clamp_rtn_u32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_sub_clamp_u32                                  :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_sub_rtn_u32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_sub_rtn_u64                          :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_sub_u32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_sub_u64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_swizzle_b32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`                            :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_wrap_rtn_b32                         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`,    :ref:`data1<amdgpu_synid_gfx12_data1_6802ce>`       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_xor_b32                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_xor_b64                                        :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_xor_rtn_b32                          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_6802ce>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+    ds_xor_rtn_b64                          :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`addr<amdgpu_synid_gfx12_addr>`,     :ref:`data0<amdgpu_synid_gfx12_data0_fd235e>`                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>`
+
+VDSDIR
+------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**            **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    ds_direct_load                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`                     :ref:`wait_va_vdst<amdgpu_synid_wait_va_vdst>` :ref:`wait_vdst<amdgpu_synid_wait_vdst>` :ref:`wait_vm_vsrc<amdgpu_synid_wait_vm_vsrc>`
+    ds_param_load                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`attr<amdgpu_synid_gfx12_attr>`           :ref:`wait_va_vdst<amdgpu_synid_wait_va_vdst>` :ref:`wait_vdst<amdgpu_synid_wait_vdst>` :ref:`wait_vm_vsrc<amdgpu_synid_wait_vm_vsrc>`
+
+VERIF
+-----
+
+.. parsed-literal::
+
+    **INSTRUCTION**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    fake_s_delay_alu
+    fake_s_nop
+    fake_s_wait_alu
+    fake_s_wait_bvhcnt
+    fake_s_wait_dscnt
+    fake_s_wait_expcnt
+    fake_s_wait_kmcnt
+    fake_s_wait_loadcnt
+    fake_s_wait_samplecnt
+    fake_s_wait_storecnt
+    fake_s_waitcnt
+    fake_v_nop
+    ill_0
+    ill_1
+    ill_beef
+    metadata
+    verif_s_adjdelay_alu
+
+VEXPORT
+-------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**      **SRC3**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    export                         :ref:`tgt<amdgpu_synid_gfx12_tgt>`,      :ref:`vsrc0<amdgpu_synid_gfx12_vsrc0>`,    :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`,    :ref:`vsrc2<amdgpu_synid_gfx12_vsrc2>`,    :ref:`vsrc3<amdgpu_synid_gfx12_vsrc3>`          :ref:`done<amdgpu_synid_done>` :ref:`row_en<amdgpu_synid_row_en>`
+
+VFLAT
+-----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    flat_atomic_add_f32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_add_u32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_add_u64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_and_b32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_and_b64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_cmpswap_b32        :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_cmpswap_b64        :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_e016a1>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_cond_sub_u32       :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_dec_u32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_dec_u64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_inc_u32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_inc_u64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_max_i32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_max_i64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_max_num_f32        :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_max_u32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_max_u64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_min_i32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_min_i64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_min_num_f32        :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_min_u32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_min_u64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_or_b32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_or_b64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_pk_add_bf16        :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_pk_add_f16         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_sub_clamp_u32      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_sub_u32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_sub_u64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_swap_b32           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_swap_b64           :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_xor_b32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_atomic_xor_b64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_b128                 :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_b64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_b96                  :ref:`vdst<amdgpu_synid_gfx12_vdst_48e42f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_d16_b16              :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_d16_hi_b16           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_d16_hi_i8            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_d16_hi_u8            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_d16_i8               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_d16_u8               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_i8                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_u16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_load_u8                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_store_b128                          :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_e016a1>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_store_b16                           :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_store_b32                           :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_store_b64                           :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_store_b8                            :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_store_b96                           :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_56f215>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_store_d16_hi_b16                    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    flat_store_d16_hi_b8                     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+
+VGLOBAL
+-------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                       **DST**       **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    global_atomic_add_f32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_add_u32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_add_u64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_and_b32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_and_b64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_cmpswap_b32         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_cmpswap_b64         :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_e016a1>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_cond_sub_u32        :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_dec_u32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_dec_u64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_inc_u32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_inc_u64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_max_i32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_max_i64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_max_num_f32         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_max_u32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_max_u64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_min_i32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_min_i64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_min_num_f32         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_min_u32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_min_u64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_or_b32              :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_or_b64              :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_ordered_add_b64     :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_pk_add_bf16         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_pk_add_f16          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_sub_clamp_u32       :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_sub_u32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_sub_u64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_swap_b32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_swap_b64            :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_xor_b32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_atomic_xor_b64             :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_inv                                                                     :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_addtid_b32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_b128                  :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_b32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_b64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_b96                   :ref:`vdst<amdgpu_synid_gfx12_vdst_48e42f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_block                 :ref:`vdst<amdgpu_synid_gfx12_vdst_2eda77>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_d16_b16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_d16_hi_b16            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_d16_hi_i8             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_d16_hi_u8             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_d16_i8                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_d16_u8                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_i8                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_lds_addtid_b32                  :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_lds_b32                         :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_lds_i16                         :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_lds_i8                          :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_lds_u16                         :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_lds_u8                          :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_tr_b128               :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_tr_b64                :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_load_u8                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_store_addtid_b32                     :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_store_b128                           :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_e016a1>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_store_b16                            :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_store_b32                            :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_store_b64                            :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_store_b8                             :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_store_b96                            :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_56f215>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_store_block                          :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_89fd7b>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_store_d16_hi_b16                     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_store_d16_hi_b8                      :ref:`vaddr<amdgpu_synid_gfx12_vaddr_f2b449>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_cdc95c>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_wb                                                                      :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    global_wbinv                                                                   :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+
+VIMAGE
+------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                      **DST**       **SRC0**      **SRC1**       **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    image_atomic_add_flt             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_add_uint            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_and                 :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_cmpswap             :ref:`vdata<amdgpu_synid_gfx12_vdata_89680f>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_dec_uint            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_inc_uint            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_max_flt             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_max_int             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_max_uint            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_min_flt             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_min_int             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_min_uint            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_or                  :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_pk_add_bf16         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_pk_add_f16          :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_sub_uint            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_swap                :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_atomic_xor                 :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_bvh64_intersect_ray        :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c12f43>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_bvh8_intersect_ray         :ref:`vdata<amdgpu_synid_gfx12_vdata_aac3e8>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_a972b9>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_bvh_dual_intersect_ray     :ref:`vdata<amdgpu_synid_gfx12_vdata_aac3e8>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c12f43>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_bvh_intersect_ray          :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_a972b9>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_5fe6d8>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_get_resinfo                :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_load                       :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_load_mip                   :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_load_mip_pck               :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_load_mip_pck_sgn           :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_load_pck                   :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_load_pck_sgn               :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_rsvd_atomic_umax_8         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_rsvd_atomic_umin_8         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_store                      :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_store_mip                  :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_store_mip_pck              :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_store_pck                  :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`,    :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`,    :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`       :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+
+VINTERP
+-------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_interp_p10_f16_f32           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`,     :ref:`src1<amdgpu_synid_gfx12_src1_6802ce>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`wait_exp<amdgpu_synid_wait_exp>`
+    v_interp_p10_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`,     :ref:`src1<amdgpu_synid_gfx12_src1_6802ce>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`wait_exp<amdgpu_synid_wait_exp>`
+    v_interp_p10_rtz_f16_f32       :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`,     :ref:`src1<amdgpu_synid_gfx12_src1_6802ce>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`wait_exp<amdgpu_synid_wait_exp>`
+    v_interp_p2_f16_f32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`,     :ref:`src1<amdgpu_synid_gfx12_src1_6802ce>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`wait_exp<amdgpu_synid_wait_exp>`
+    v_interp_p2_f32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`,     :ref:`src1<amdgpu_synid_gfx12_src1_6802ce>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`wait_exp<amdgpu_synid_wait_exp>`
+    v_interp_p2_rtz_f16_f32        :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`,     :ref:`src1<amdgpu_synid_gfx12_src1_6802ce>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`wait_exp<amdgpu_synid_wait_exp>`
+
+VOP1
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC**            **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_bfrev_b32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f16                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f64                     :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cls_i32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_clz_i32_u32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cos_f16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cos_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ctz_i32_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_u16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_bf8                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_fp8                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_i32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_u32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_ubyte0               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_ubyte1               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_ubyte2               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_ubyte3               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f64_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f64_i32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f64_u32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_floor_i32_f32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i16_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i32_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i32_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i32_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_nearest_i32_f32          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_norm_i16_f16             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_norm_u16_f16             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_off_f32_i4               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_f32_bf8               :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_f32_fp8               :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u16_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u32_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u32_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u32_u16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_exp_f16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_exp_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_exp_i16_f16            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_exp_i32_f32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_exp_i32_f64            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f64               :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_log_f16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_log_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mov_b16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mov_b32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mov_fed_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mov_from_global_b32          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mov_to_global_b32            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_movreld_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_movrels_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_movrelsd_2_b32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_movrelsd_b32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_nop                                                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_not_b16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_not_b32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_permlane64_b32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pipeflush                                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f64                      :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_iflag_f32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_readfirstlane_b32            :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f64                      :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sat_pk_u8_i16                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f16                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f64                     :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_swap_b16                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_swap_b32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_swaprel_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_writelane_regwr_b32          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOP2
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST0**      **DST1**      **SRC0**      **SRC1**       **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add_co_ci_u32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`sdst<amdgpu_synid_gfx12_sdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vcc<amdgpu_synid_gfx12_vcc>`::ref:`m<amdgpu_synid_gfx12_m>`          :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f64                      :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_nc_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_nc_u64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_and_b32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ashrrev_i32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cndmask_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vcc<amdgpu_synid_gfx12_vcc>`::ref:`m<amdgpu_synid_gfx12_m>`          :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_rtz_f16_f32           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmaak_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`::ref:`m<amdgpu_synid_gfx12_m>`      :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmaak_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`::ref:`m<amdgpu_synid_gfx12_m>`      :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmaak_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`literal<amdgpu_synid_gfx12_literal_1f74c7>`::ref:`m<amdgpu_synid_gfx12_m>`      :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmac_f16                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmac_f32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmac_f64                     :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmamk_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`::ref:`m<amdgpu_synid_gfx12_m>`, :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmamk_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`::ref:`m<amdgpu_synid_gfx12_m>`, :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmamk_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`literal<amdgpu_synid_gfx12_literal_1f74c7>`::ref:`m<amdgpu_synid_gfx12_m>`, :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_illegal                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_lshlrev_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_lshlrev_b64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_lshrrev_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_i32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_num_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_num_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_num_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_u32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_i32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_num_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_num_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_num_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_u32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_dx9_zero_f32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f64                      :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_hi_i32_i24               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_hi_u32_u24               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_i32_i24                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_u32_u24                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_u64                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_or_b32                       :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_fmac_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_co_ci_u32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`sdst<amdgpu_synid_gfx12_sdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vcc<amdgpu_synid_gfx12_vcc>`::ref:`m<amdgpu_synid_gfx12_m>`          :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_nc_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_nc_u64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_co_ci_u32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`sdst<amdgpu_synid_gfx12_sdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vcc<amdgpu_synid_gfx12_vcc>`::ref:`m<amdgpu_synid_gfx12_m>`          :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_nc_u32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_xnor_b32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_xor_b32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOP3
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST0**      **DST1**      **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_add3_u32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_co_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`sdst<amdgpu_synid_gfx12_sdst_e701cc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_lshl_u32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_nc_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_nc_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_nc_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_alignbit_b32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_alignbyte_b32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_and_b16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_and_or_b32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ashrrev_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ashrrev_i64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_bcnt_u32_b32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_bfe_i32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_bfe_u32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_bfi_b32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_bfm_b32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cndmask_b16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_2797bc>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cubeid_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cubema_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cubesc_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cubetc_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_bf8_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_fp8_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_i16_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_i16_i32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_norm_i16_f16          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_norm_i16_f32          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_norm_u16_f16          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_norm_u16_f32          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_u16_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_u16_u32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_pk_u8_f32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_sr_bf8_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_sr_fp8_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f16                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f64                :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fmas_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fmas_f64                 :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_scale_f32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`sdst<amdgpu_synid_gfx12_sdst_e701cc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_scale_f64                :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`sdst<amdgpu_synid_gfx12_sdst_e701cc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_bf16_bf16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_f16_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_dx9_zero_f32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f64                      :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_lerp_u8                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_lshl_add_u32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_lshl_add_u64                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_lshl_or_b32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_lshlrev_b16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_lshrrev_b16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_lshrrev_b64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_co_i64_i32               :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`sdst<amdgpu_synid_gfx12_sdst_e701cc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_co_u64_u32               :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`sdst<amdgpu_synid_gfx12_sdst_e701cc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i24                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u24                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_i16                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_i32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_num_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_num_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_u16                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_u32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_i16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_u16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maximum3_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maximum3_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maximum_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maximum_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maximum_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maximumminimum_f16           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maximumminimum_f32           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maxmin_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maxmin_num_f16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maxmin_num_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_maxmin_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mbcnt_hi_u32_b32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mbcnt_lo_u32_b32             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_i16                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_i32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_num_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_num_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_u16                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_u32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_i16                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_i32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_num_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_num_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_u16                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_u32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_i16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_u16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minimum3_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minimum3_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minimum_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minimum_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minimum_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minimummaximum_f16           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minimummaximum_f32           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minmax_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minmax_num_f16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minmax_num_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_minmax_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mqsad_pk_u16_u8              :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mqsad_u32_u8                 :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_e016a1>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_msad_u8                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_hi_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_hi_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_lo_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_lo_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mullit_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_or3_b32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_or_b16                       :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pack_b32_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_perm_b32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_permlane16_b32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_c4593f>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_c4593f>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_permlane16_var_b32           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_permlanex16_b32              :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_c4593f>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_c4593f>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_permlanex16_var_b32          :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_qsad_pk_u16_u8               :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_readlane_b32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_977794>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_readlane_regrd_b32           :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_977794>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_s_exp_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_85aab6>`::ref:`m<amdgpu_synid_gfx12_m>`                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_s_exp_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_c4593f>`::ref:`m<amdgpu_synid_gfx12_m>`                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_s_log_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_85aab6>`::ref:`m<amdgpu_synid_gfx12_m>`                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_s_log_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_c4593f>`::ref:`m<amdgpu_synid_gfx12_m>`                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_s_rcp_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_85aab6>`::ref:`m<amdgpu_synid_gfx12_m>`                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_s_rcp_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_c4593f>`::ref:`m<amdgpu_synid_gfx12_m>`                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_s_rsq_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_85aab6>`::ref:`m<amdgpu_synid_gfx12_m>`                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_s_rsq_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_c4593f>`::ref:`m<amdgpu_synid_gfx12_m>`                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_s_sqrt_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_85aab6>`::ref:`m<amdgpu_synid_gfx12_m>`                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_s_sqrt_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_836716>`,               :ref:`src0<amdgpu_synid_gfx12_src0_c4593f>`::ref:`m<amdgpu_synid_gfx12_m>`                             :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_hi_u8                    :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u8                       :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_co_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`sdst<amdgpu_synid_gfx12_sdst_e701cc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_nc_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_nc_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_nc_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_co_u32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`sdst<amdgpu_synid_gfx12_sdst_e701cc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_trig_preop_f64               :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_writelane_b32                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_c4593f>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_977794>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_xad_u32                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_xor3_b32                     :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`         :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_xor_b16                      :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,               :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`                   :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOP3P
+-----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_dot2_f32_bf16                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_dot2_f32_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_dot4_f32_bf8_bf8             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_dot4_f32_bf8_fp8             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_dot4_f32_fp8_bf8             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_dot4_f32_fp8_fp8             :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_dot4_i32_iu8                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_dot4_u32_u8                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_dot8_i32_iu4                 :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_dot8_u32_u4                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_fma_mix_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_fma_mixhi_f16                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_fma_mixlo_f16                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_pk_add_bf16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_add_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_add_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_add_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_ashrrev_i16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_fma_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_pk_fma_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5cae62>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5cae62>`
+    v_pk_lshlrev_b16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_lshrrev_b16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_mad_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_pk_mad_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`,     :ref:`src2<amdgpu_synid_gfx12_src2_5727cf>`
+    v_pk_max_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_max_num_f16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_max_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_maximum_f16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_min_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_min_num_f16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_min_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_minimum_f16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_mul_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_mul_lo_u16                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_sub_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_pk_sub_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`,     :ref:`src1<amdgpu_synid_gfx12_src1_5727cf>`
+    v_swmmac_bf16_16x16x32_bf16    :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`src0<amdgpu_synid_gfx12_src0_e016a1>`,     :ref:`src1<amdgpu_synid_gfx12_src1_731030>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_swmmac_f16_16x16x32_f16      :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`src0<amdgpu_synid_gfx12_src0_e016a1>`,     :ref:`src1<amdgpu_synid_gfx12_src1_731030>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_swmmac_f32_16x16x32_bf16     :ref:`vdst<amdgpu_synid_gfx12_vdst_47d3bc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_e016a1>`,     :ref:`src1<amdgpu_synid_gfx12_src1_731030>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_swmmac_f32_16x16x32_bf8_bf8  :ref:`vdst<amdgpu_synid_gfx12_vdst_47d3bc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_e016a1>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_swmmac_f32_16x16x32_bf8_fp8  :ref:`vdst<amdgpu_synid_gfx12_vdst_47d3bc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_e016a1>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_swmmac_f32_16x16x32_f16      :ref:`vdst<amdgpu_synid_gfx12_vdst_47d3bc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_e016a1>`,     :ref:`src1<amdgpu_synid_gfx12_src1_731030>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_swmmac_f32_16x16x32_fp8_bf8  :ref:`vdst<amdgpu_synid_gfx12_vdst_47d3bc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_e016a1>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_swmmac_f32_16x16x32_fp8_fp8  :ref:`vdst<amdgpu_synid_gfx12_vdst_47d3bc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_e016a1>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_swmmac_i32_16x16x32_iu4      :ref:`vdst<amdgpu_synid_gfx12_vdst_47d3bc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`,     :ref:`src1<amdgpu_synid_gfx12_src1_fd235e>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_swmmac_i32_16x16x32_iu8      :ref:`vdst<amdgpu_synid_gfx12_vdst_47d3bc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_e016a1>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_swmmac_i32_16x16x64_iu4      :ref:`vdst<amdgpu_synid_gfx12_vdst_47d3bc>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_e016a1>`,     :ref:`src2<amdgpu_synid_gfx12_src2_6802ce>`
+    v_wmma_bf16_16x16x16_bf16      :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_e016a1>`,     :ref:`src1<amdgpu_synid_gfx12_src1_e016a1>`,     :ref:`src2<amdgpu_synid_gfx12_src2_7b936a>`
+    v_wmma_f16_16x16x16_f16        :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_e016a1>`,     :ref:`src1<amdgpu_synid_gfx12_src1_e016a1>`,     :ref:`src2<amdgpu_synid_gfx12_src2_7b936a>`
+    v_wmma_f32_16x16x16_bf16       :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_e016a1>`,     :ref:`src1<amdgpu_synid_gfx12_src1_e016a1>`,     :ref:`src2<amdgpu_synid_gfx12_src2_96fbd3>`
+    v_wmma_f32_16x16x16_bf8_bf8    :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_fd235e>`,     :ref:`src2<amdgpu_synid_gfx12_src2_96fbd3>`
+    v_wmma_f32_16x16x16_bf8_fp8    :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_fd235e>`,     :ref:`src2<amdgpu_synid_gfx12_src2_96fbd3>`
+    v_wmma_f32_16x16x16_f16        :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_e016a1>`,     :ref:`src1<amdgpu_synid_gfx12_src1_e016a1>`,     :ref:`src2<amdgpu_synid_gfx12_src2_96fbd3>`
+    v_wmma_f32_16x16x16_fp8_bf8    :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_fd235e>`,     :ref:`src2<amdgpu_synid_gfx12_src2_96fbd3>`
+    v_wmma_f32_16x16x16_fp8_fp8    :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_fd235e>`,     :ref:`src2<amdgpu_synid_gfx12_src2_96fbd3>`
+    v_wmma_i32_16x16x16_iu4        :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_6802ce>`,     :ref:`src1<amdgpu_synid_gfx12_src1_6802ce>`,     :ref:`src2<amdgpu_synid_gfx12_src2_96fbd3>`
+    v_wmma_i32_16x16x16_iu8        :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_fd235e>`,     :ref:`src2<amdgpu_synid_gfx12_src2_96fbd3>`
+    v_wmma_i32_16x16x32_iu4        :ref:`vdst<amdgpu_synid_gfx12_vdst_227281>`,     :ref:`src0<amdgpu_synid_gfx12_src0_fd235e>`,     :ref:`src1<amdgpu_synid_gfx12_src1_fd235e>`,     :ref:`src2<amdgpu_synid_gfx12_src2_96fbd3>`
+
+VOPC
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_cmp_class_f16                :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_class_f32                :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_class_f64                :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_i64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_u64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_i32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_i64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_u32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_u64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_i64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_u64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_i64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_u64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_i64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_u64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_i64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_u64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ne_i16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ne_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ne_i64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ne_u16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ne_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ne_u64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_t_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_t_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_t_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_t_i32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_t_i64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_t_u32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_t_u64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f16                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f32                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f64                    :ref:`vdst<amdgpu_synid_gfx12_vdst_006c40>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f16               :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f32               :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f64               :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_i32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_i64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_u16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_u32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_u64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_i64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_u64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_i32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_i64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_u16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_u32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_u64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_i32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_i64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_u16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_u32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_u64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_i32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_i64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_u16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_u32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_u64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_i32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_i64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_u16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_u32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_u64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ne_i16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ne_i32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ne_i64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ne_u16                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ne_u32                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ne_u64                  :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f64                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f64                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f64                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f64                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f64                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f16                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f32                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f64                 :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_t_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_t_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_t_f64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_t_i32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_t_i64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_t_u32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_t_u64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f16                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f32                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5727cf>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_6802ce>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f64                   :ref:`vdst<amdgpu_synid_gfx12_vdst_7de8e7>`,     :ref:`src0<amdgpu_synid_gfx12_src0_5cae62>`::ref:`m<amdgpu_synid_gfx12_m>`,   :ref:`vsrc1<amdgpu_synid_gfx12_vsrc1_fd235e>`::ref:`m<amdgpu_synid_gfx12_m>`        :ref:`omod<amdgpu_synid_omod>` :ref:`clamp<amdgpu_synid_clamp>`
+
+VOPD
+----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                                **DST0**   **DST1**   **SRC0**   **SRC1**    **SRC2**    **SRC3**    **SRC4**    **SRC5**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_dual_add_f32_x_add_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_add_nc_u32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_and_b32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_cndmask_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_add_f32_x_dot2acc_f32_bf16          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_dot2acc_f32_f16           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_fmaak_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_add_f32_x_fmac_f32                  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_fmamk_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_add_f32_x_lshlrev_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_max_num_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_min_num_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_mov_b32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_add_f32_x_mul_dx9_zero_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_mul_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_sub_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_add_f32_x_subrev_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_cndmask_b32_x_add_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_add_nc_u32            :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_and_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_cndmask_b32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_dot2acc_f32_bf16      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_dot2acc_f32_f16       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_fmaak_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`,    :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_cndmask_b32_x_fmac_f32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_fmamk_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`,    :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_cndmask_b32_x_lshlrev_b32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_max_num_f32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_min_num_f32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_mov_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_mul_dx9_zero_f32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_mul_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_sub_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_cndmask_b32_x_subrev_f32            :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_dot2acc_f32_bf16_x_add_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_add_nc_u32       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_and_b32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_cndmask_b32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_dot2acc_f32_bf16_x_dot2acc_f32_bf16 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_dot2acc_f32_f16  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_fmaak_f32        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_dot2acc_f32_bf16_x_fmac_f32         :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_fmamk_f32        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_dot2acc_f32_bf16_x_lshlrev_b32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_max_num_f32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_min_num_f32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_mov_b32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_dot2acc_f32_bf16_x_mul_dx9_zero_f32 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_mul_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_sub_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_bf16_x_subrev_f32       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_add_f32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_add_nc_u32        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_and_b32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_cndmask_b32       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_dot2acc_f32_f16_x_dot2acc_f32_bf16  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_dot2acc_f32_f16   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_fmaak_f32         :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_dot2acc_f32_f16_x_fmac_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_fmamk_f32         :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_dot2acc_f32_f16_x_lshlrev_b32       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_max_num_f32       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_min_num_f32       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_mov_b32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_dot2acc_f32_f16_x_mul_dx9_zero_f32  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_mul_f32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_sub_f32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_dot2acc_f32_f16_x_subrev_f32        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmaak_f32_x_add_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_add_nc_u32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_and_b32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_cndmask_b32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`,    :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_dot2acc_f32_bf16        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_dot2acc_f32_f16         :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_fmaak_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_fmac_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_fmamk_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_lshlrev_b32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_max_num_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_min_num_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_mov_b32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_mul_dx9_zero_f32        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_mul_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_sub_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmaak_f32_x_subrev_f32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmac_f32_x_add_f32                  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_add_nc_u32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_and_b32                  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_cndmask_b32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_fmac_f32_x_dot2acc_f32_bf16         :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_dot2acc_f32_f16          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_fmaak_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmac_f32_x_fmac_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_fmamk_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmac_f32_x_lshlrev_b32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_max_num_f32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_min_num_f32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_mov_b32                  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_fmac_f32_x_mul_dx9_zero_f32         :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_mul_f32                  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_sub_f32                  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmac_f32_x_subrev_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_fmamk_f32_x_add_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_add_nc_u32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_and_b32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_cndmask_b32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`,    :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_dot2acc_f32_bf16        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_dot2acc_f32_f16         :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_fmaak_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_fmac_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_fmamk_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_lshlrev_b32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_max_num_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_min_num_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_mov_b32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_mul_dx9_zero_f32        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_mul_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_sub_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmamk_f32_x_subrev_f32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_max_num_f32_x_add_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_add_nc_u32            :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_and_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_cndmask_b32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_max_num_f32_x_dot2acc_f32_bf16      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_dot2acc_f32_f16       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_fmaak_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_max_num_f32_x_fmac_f32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_fmamk_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_max_num_f32_x_lshlrev_b32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_max_num_f32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_min_num_f32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_mov_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_max_num_f32_x_mul_dx9_zero_f32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_mul_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_sub_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_max_num_f32_x_subrev_f32            :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_add_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_add_nc_u32            :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_and_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_cndmask_b32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_min_num_f32_x_dot2acc_f32_bf16      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_dot2acc_f32_f16       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_fmaak_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_min_num_f32_x_fmac_f32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_fmamk_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_min_num_f32_x_lshlrev_b32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_max_num_f32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_min_num_f32           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_mov_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_min_num_f32_x_mul_dx9_zero_f32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_mul_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_sub_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_min_num_f32_x_subrev_f32            :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_add_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_add_nc_u32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_and_b32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_cndmask_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_mov_b32_x_dot2acc_f32_bf16          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_dot2acc_f32_f16           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_fmaak_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_mov_b32_x_fmac_f32                  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_fmamk_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_mov_b32_x_lshlrev_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_max_num_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_min_num_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_mov_b32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_mov_b32_x_mul_dx9_zero_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_mul_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_sub_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mov_b32_x_subrev_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_add_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_add_nc_u32       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_and_b32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_cndmask_b32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_mul_dx9_zero_f32_x_dot2acc_f32_bf16 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_dot2acc_f32_f16  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_fmaak_f32        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_mul_dx9_zero_f32_x_fmac_f32         :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_fmamk_f32        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_mul_dx9_zero_f32_x_lshlrev_b32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_max_num_f32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_min_num_f32      :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_mov_b32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_mul_dx9_zero_f32_x_mul_dx9_zero_f32 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_mul_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_sub_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_dx9_zero_f32_x_subrev_f32       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_add_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_add_nc_u32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_and_b32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_cndmask_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_mul_f32_x_dot2acc_f32_bf16          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_dot2acc_f32_f16           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_fmaak_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_mul_f32_x_fmac_f32                  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_fmamk_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_mul_f32_x_lshlrev_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_max_num_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_min_num_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_mov_b32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_mul_f32_x_mul_dx9_zero_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_mul_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_sub_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_mul_f32_x_subrev_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_add_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_add_nc_u32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_and_b32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_cndmask_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_sub_f32_x_dot2acc_f32_bf16          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_dot2acc_f32_f16           :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_fmaak_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_sub_f32_x_fmac_f32                  :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_fmamk_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_sub_f32_x_lshlrev_b32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_max_num_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_min_num_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_mov_b32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_sub_f32_x_mul_dx9_zero_f32          :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_mul_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_sub_f32                   :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_sub_f32_x_subrev_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_add_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_add_nc_u32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_and_b32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_cndmask_b32            :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_subrev_f32_x_dot2acc_f32_bf16       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_dot2acc_f32_f16        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_fmaak_f32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_subrev_f32_x_fmac_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_fmamk_f32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`, :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_subrev_f32_x_lshlrev_b32            :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_max_num_f32            :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_min_num_f32            :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_mov_b32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`
+    v_dual_subrev_f32_x_mul_dx9_zero_f32       :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_mul_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_sub_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_subrev_f32_x_subrev_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`, :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`, :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`, :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`, :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,  :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+
+VOPDX
+-----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_dual_add_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+    v_dual_cndmask_b32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`,   :ref:`vcc<amdgpu_synid_gfx12_vcc>`
+    v_dual_dot2acc_f32_bf16        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+    v_dual_dot2acc_f32_f16         :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+    v_dual_fmaak_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`,   :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`
+    v_dual_fmac_f32                :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+    v_dual_fmamk_f32               :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`literal<amdgpu_synid_gfx12_literal_81e671>`,  :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+    v_dual_max_num_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+    v_dual_min_num_f32             :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+    v_dual_mov_b32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`
+    v_dual_mul_dx9_zero_f32        :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+    v_dual_mul_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+    v_dual_sub_f32                 :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+    v_dual_subrev_f32              :ref:`vdstx<amdgpu_synid_gfx12_vdstx>`,    :ref:`srcx0<amdgpu_synid_gfx12_srcx0>`,    :ref:`vsrcx1<amdgpu_synid_gfx12_vsrcx1>`
+
+VOPDY
+-----
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    v_dual_add_nc_u32              :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`,    :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,    :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_and_b32                 :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`,    :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,    :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+    v_dual_lshlrev_b32             :ref:`vdsty<amdgpu_synid_gfx12_vdsty>`,    :ref:`srcy0<amdgpu_synid_gfx12_srcy0>`,    :ref:`vsrcy1<amdgpu_synid_gfx12_vsrcy1>`
+
+VSAMPLE
+-------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                **DST**    **SRC0**   **SRC1**  **SRC2**  **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    image_gather4              :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_b            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_b_cl         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_c            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_c_b          :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_c_b_cl       :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_c_cl         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_c_l          :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_c_lz         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_c_lz_o       :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_cl           :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_l            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_lz           :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_lz_o         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4_o            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_gather4h             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_get_lod              :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_msaa_load            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_d82160>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`        :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample               :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_b             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_b_cl          :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_b_cl_o        :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_b_o           :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_b           :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_b_cl        :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_b_cl_o      :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_b_o         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_cl          :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_cl_o        :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_d           :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_d_cl        :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_d_cl_g16    :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_d_cl_o      :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_d_cl_o_g16  :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_d_g16       :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_d_o         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_d_o_g16     :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_l           :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_l_o         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_lz          :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_lz_o        :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_c_o           :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_cl            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_cl_o          :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_d             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_d_cl          :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_d_cl_g16      :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_d_cl_o        :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_d_cl_o_g16    :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_d_g16         :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_d_o           :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_d_o_g16       :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_l             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_l_o           :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_lz            :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_lz_o          :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    image_sample_o             :ref:`vdata<amdgpu_synid_gfx12_vdata_69a144>`, :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`, :ref:`rsrc<amdgpu_synid_gfx12_rsrc_c9f929>`, :ref:`samp<amdgpu_synid_gfx12_samp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`dim<amdgpu_synid_dim>` :ref:`r128<amdgpu_synid_r128>` :ref:`a16<amdgpu_synid_a16>` :ref:`d16<amdgpu_synid_d16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+
+VSCRATCH
+--------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    scratch_load_b128              :ref:`vdst<amdgpu_synid_gfx12_vdst_69a144>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_b32               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_b64               :ref:`vdst<amdgpu_synid_gfx12_vdst_bdb32f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_b96               :ref:`vdst<amdgpu_synid_gfx12_vdst_48e42f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_block             :ref:`vdst<amdgpu_synid_gfx12_vdst_2eda77>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_d16_b16           :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_d16_hi_b16        :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_d16_hi_i8         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_d16_hi_u8         :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_d16_i8            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_d16_u8            :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_i16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_i8                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_lds_b32                     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_lds_i16                     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_lds_i8                      :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_lds_u16                     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_lds_u8                      :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_u16               :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_load_u8                :ref:`vdst<amdgpu_synid_gfx12_vdst_89680f>`,     :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_store_b128                       :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_e016a1>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_store_b16                        :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_store_b32                        :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_store_b64                        :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_fd235e>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_store_b8                         :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_store_b96                        :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_56f215>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_store_block                      :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_89fd7b>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_store_d16_hi_b16                 :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+    scratch_store_d16_hi_b8                  :ref:`vaddr<amdgpu_synid_gfx12_vaddr_c8b8d4>`,    :ref:`vsrc<amdgpu_synid_gfx12_vsrc_6802ce>`,     :ref:`saddr<amdgpu_synid_gfx12_saddr_d42b64>`          :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`th<amdgpu_synid_th>` :ref:`scope<amdgpu_synid_scope>` :ref:`nv<amdgpu_synid_nv>`
+
+.. |---| unicode:: U+02014 .. em dash
+
+.. toctree::
+    :hidden:
+
+    gfx12_addr
+    gfx12_attr
+    gfx12_data0_56f215
+    gfx12_data0_6802ce
+    gfx12_data0_e016a1
+    gfx12_data0_fd235e
+    gfx12_data1_6802ce
+    gfx12_data1_731030
+    gfx12_data1_e016a1
+    gfx12_data1_fd235e
+    gfx12_ioffset
+    gfx12_literal_1f74c7
+    gfx12_literal_81e671
+    gfx12_m
+    gfx12_rsrc_5fe6d8
+    gfx12_rsrc_c9f929
+    gfx12_saddr_cdc95c
+    gfx12_saddr_d42b64
+    gfx12_samp
+    gfx12_sbase_453b95
+    gfx12_sbase_47adb7
+    gfx12_sdata_0974a4
+    gfx12_sdata_354189
+    gfx12_sdata_4585b8
+    gfx12_sdata_5c7b50
+    gfx12_sdata_6c003b
+    gfx12_sdata_836716
+    gfx12_sdata_d725ab
+    gfx12_sdata_dd9dd8
+    gfx12_sdst_006c40
+    gfx12_sdst_20064d
+    gfx12_sdst_354189
+    gfx12_sdst_836716
+    gfx12_sdst_ced58d
+    gfx12_sdst_e701cc
+    gfx12_simm16_15ccdd
+    gfx12_simm16_218bea
+    gfx12_simm16_39b593
+    gfx12_simm16_3d2a4f
+    gfx12_simm16_730a13
+    gfx12_simm16_7ed651
+    gfx12_simm16_81e671
+    gfx12_simm16_c98889
+    gfx12_simm16_cc1716
+    gfx12_simm16_ee8b30
+    gfx12_soffset_8ec073
+    gfx12_soffset_c5b88c
+    gfx12_soffset_ec005a
+    gfx12_src0_5727cf
+    gfx12_src0_5cae62
+    gfx12_src0_6802ce
+    gfx12_src0_85aab6
+    gfx12_src0_c4593f
+    gfx12_src0_e016a1
+    gfx12_src0_fd235e
+    gfx12_src1_5727cf
+    gfx12_src1_5cae62
+    gfx12_src1_6802ce
+    gfx12_src1_731030
+    gfx12_src1_977794
+    gfx12_src1_c4593f
+    gfx12_src1_e016a1
+    gfx12_src1_fd235e
+    gfx12_src2_2797bc
+    gfx12_src2_5727cf
+    gfx12_src2_5cae62
+    gfx12_src2_6802ce
+    gfx12_src2_7b936a
+    gfx12_src2_96fbd3
+    gfx12_src2_c4593f
+    gfx12_src2_e016a1
+    gfx12_srcx0
+    gfx12_srcy0
+    gfx12_ssrc0_007f9c
+    gfx12_ssrc0_1a9ca5
+    gfx12_ssrc0_245536
+    gfx12_ssrc0_2797bc
+    gfx12_ssrc0_bbb4c6
+    gfx12_ssrc0_c4593f
+    gfx12_ssrc1_bbb4c6
+    gfx12_ssrc1_c4593f
+    gfx12_tgt
+    gfx12_vaddr_a972b9
+    gfx12_vaddr_c12f43
+    gfx12_vaddr_c8b8d4
+    gfx12_vaddr_d82160
+    gfx12_vaddr_f2b449
+    gfx12_vcc
+    gfx12_vdata_2eda77
+    gfx12_vdata_48e42f
+    gfx12_vdata_69a144
+    gfx12_vdata_89680f
+    gfx12_vdata_aac3e8
+    gfx12_vdata_bdb32f
+    gfx12_vdst_006c40
+    gfx12_vdst_227281
+    gfx12_vdst_2eda77
+    gfx12_vdst_47d3bc
+    gfx12_vdst_48e42f
+    gfx12_vdst_69a144
+    gfx12_vdst_7de8e7
+    gfx12_vdst_836716
+    gfx12_vdst_89680f
+    gfx12_vdst_bdb32f
+    gfx12_vdstx
+    gfx12_vdsty
+    gfx12_vsrc0
+    gfx12_vsrc1_6802ce
+    gfx12_vsrc1_fd235e
+    gfx12_vsrc2
+    gfx12_vsrc3
+    gfx12_vsrc_56f215
+    gfx12_vsrc_6802ce
+    gfx12_vsrc_89fd7b
+    gfx12_vsrc_e016a1
+    gfx12_vsrc_fd235e
+    gfx12_vsrcx1
+    gfx12_vsrcy1
+    gfx12_clause
+    gfx12_delay
+    gfx12_hwreg
+    gfx12_imm16
+    gfx12_label
+    gfx12_sendmsg
+    gfx12_sendmsg_rtn
+    gfx12_version
+    gfx12_waitcnt
diff --git a/llvm/docs/AMDGPU/gfx12_addr.rst b/llvm/docs/AMDGPU/gfx12_addr.rst
new file mode 100644
index 0000000000000..d2fc0e0cb2f4b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_addr.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_addr:
+
+addr
+====
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_attr.rst b/llvm/docs/AMDGPU/gfx12_attr.rst
new file mode 100644
index 0000000000000..a6c5c275b349f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_attr.rst
@@ -0,0 +1,28 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_attr:
+
+attr
+====
+
+Interpolation attribute and channel:
+
+    ============== ===================================
+    Syntax         Description
+    ============== ===================================
+    attr{0..32}.x  Attribute 0..32 with *x* channel.
+    attr{0..32}.y  Attribute 0..32 with *y* channel.
+    attr{0..32}.z  Attribute 0..32 with *z* channel.
+    attr{0..32}.w  Attribute 0..32 with *w* channel.
+    ============== ===================================
+
+Examples:
+
+.. parsed-literal::
+
+    ds_param_load v1, attr0.x
diff --git a/llvm/docs/AMDGPU/gfx12_clause.rst b/llvm/docs/AMDGPU/gfx12_clause.rst
new file mode 100644
index 0000000000000..88feb3b1d9974
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_clause.rst
@@ -0,0 +1,7 @@
+.. _amdgpu_synid_clause:
+
+clause
+======
+
+Description of a clause following this instruction.
+
diff --git a/llvm/docs/AMDGPU/gfx12_data0_56f215.rst b/llvm/docs/AMDGPU/gfx12_data0_56f215.rst
new file mode 100644
index 0000000000000..d8dde0013ed64
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_data0_56f215.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data0_56f215:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_data0_6802ce.rst b/llvm/docs/AMDGPU/gfx12_data0_6802ce.rst
new file mode 100644
index 0000000000000..02fe36f489229
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_data0_6802ce.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data0_6802ce:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_data0_e016a1.rst b/llvm/docs/AMDGPU/gfx12_data0_e016a1.rst
new file mode 100644
index 0000000000000..914715bf30ea9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_data0_e016a1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data0_e016a1:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_data0_fd235e.rst b/llvm/docs/AMDGPU/gfx12_data0_fd235e.rst
new file mode 100644
index 0000000000000..7617c61a94be3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_data0_fd235e.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data0_fd235e:
+
+data0
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_data1_6802ce.rst b/llvm/docs/AMDGPU/gfx12_data1_6802ce.rst
new file mode 100644
index 0000000000000..318db2daaeec3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_data1_6802ce.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data1_6802ce:
+
+data1
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_data1_731030.rst b/llvm/docs/AMDGPU/gfx12_data1_731030.rst
new file mode 100644
index 0000000000000..1a6eda65328ae
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_data1_731030.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data1_731030:
+
+data1
+=====
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_data1_e016a1.rst b/llvm/docs/AMDGPU/gfx12_data1_e016a1.rst
new file mode 100644
index 0000000000000..dee4148c3d6d1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_data1_e016a1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data1_e016a1:
+
+data1
+=====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_data1_fd235e.rst b/llvm/docs/AMDGPU/gfx12_data1_fd235e.rst
new file mode 100644
index 0000000000000..c8d4a88857d1f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_data1_fd235e.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_data1_fd235e:
+
+data1
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_delay.rst b/llvm/docs/AMDGPU/gfx12_delay.rst
new file mode 100644
index 0000000000000..600ece7fccfc5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_delay.rst
@@ -0,0 +1,74 @@
+.. _amdgpu_synid_delay:
+
+delay
+=====
+
+A delay between dependent SALU/VALU instructions.
+This operand may specify a delay for 2 instructions:
+the one after the current *s_delay_alu* instruction
+and for the second instruction indicated by *SKIP*.
+
+The bits of this operand have the following meaning:
+
+    ===== ========================================================== ============
+    Bits  Description                                                Value Range
+    ===== ========================================================== ============
+    3:0   ID0: indicates a delay for the first instruction.          0..11
+    6:4   SKIP: indicates the position of the second instruction.    0..5
+    10:7  ID1: indicates a delay for the second instruction.         0..11
+    ===== ========================================================== ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A combination of *instid0*, *instskip*, *instid1* values described below.
+
+    ======================== =========================== ===============
+    Syntax                   Description                 Default Value
+    ======================== =========================== ===============
+    instid0(<*ID name*>)     A symbolic *ID0* value.     instid0(NO_DEP)
+    instskip(<*SKIP name*>)  A symbolic *SKIP* value.    instskip(SAME)
+    instid1(<*ID name*>)     A symbolic *ID1* value.     instid1(NO_DEP)
+    ======================== =========================== ===============
+
+These values may be specified in any order.
+When more than one value is specified, the values must be separated from each other by a '|'.
+
+Valid *ID names* are defined below.
+
+    =================== ===================================================================
+    Name                Description
+    =================== ===================================================================
+    NO_DEP              No dependency on any prior instruction. This is the default value.
+    VALU_DEP_1          Dependency on a previous VALU instruction, 1 opcode back.
+    VALU_DEP_2          Dependency on a previous VALU instruction, 2 opcodes back.
+    VALU_DEP_3          Dependency on a previous VALU instruction, 3 opcodes back.
+    VALU_DEP_4          Dependency on a previous VALU instruction, 4 opcodes back.
+    TRANS32_DEP_1       Dependency on a previous TRANS32 instruction, 1 opcode back.
+    TRANS32_DEP_2       Dependency on a previous TRANS32 instruction, 2 opcodes back.
+    TRANS32_DEP_3       Dependency on a previous TRANS32 instruction, 3 opcodes back.
+    FMA_ACCUM_CYCLE_1   Single cycle penalty for FMA accumulation.
+    SALU_CYCLE_1        1 cycle penalty for a prior SALU instruction.
+    SALU_CYCLE_2        2 cycle penalty for a prior SALU instruction.
+    SALU_CYCLE_3        3 cycle penalty for a prior SALU instruction.
+    =================== ===================================================================
+
+Legal *SKIP names* are described in the following table.
+
+    ======== ============================================================================
+    Name     Description
+    ======== ============================================================================
+    SAME     Apply second dependency to the same instruction. This is the default value.
+    NEXT     Apply second dependency to the next instruction.
+    SKIP_1   Skip 1 instruction then apply dependency.
+    SKIP_2   Skip 2 instructions then apply dependency.
+    SKIP_3   Skip 3 instructions then apply dependency.
+    SKIP_4   Skip 4 instructions then apply dependency.
+    ======== ============================================================================
+
+Examples:
+
+.. parsed-literal::
+
+    s_delay_alu instid0(VALU_DEP_1)
+    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
diff --git a/llvm/docs/AMDGPU/gfx12_hwreg.rst b/llvm/docs/AMDGPU/gfx12_hwreg.rst
new file mode 100644
index 0000000000000..d99cb20df24ae
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_hwreg.rst
@@ -0,0 +1,76 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_hwreg:
+
+hwreg
+=====
+
+Bits of a hardware register being accessed.
+
+The bits of this operand have the following meaning:
+
+    ======= ===================== ============
+    Bits    Description           Value Range
+    ======= ===================== ============
+    5:0     Register *id*.        0..63
+    10:6    First bit *offset*.   0..31
+    15:11   *Size* in bits.       1..32
+    ======= ===================== ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* An *hwreg* value described below.
+
+    ==================================== ============================================================================
+    Hwreg Value Syntax                   Description
+    ==================================== ============================================================================
+    hwreg({0..63})                       All bits of a register indicated by its *id*.
+    hwreg(<*name*>)                      All bits of a register indicated by its *name*.
+    hwreg({0..63}, {0..31}, {1..32})     Register bits indicated by register *id*, first bit *offset* and *size*.
+    hwreg(<*name*>, {0..31}, {1..32})    Register bits indicated by register *name*, first bit *offset* and *size*.
+    ==================================== ============================================================================
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+Defined register *names* include:
+
+    =================== ==========================================
+    Name                Description
+    =================== ==========================================
+    HW_REG_MODE         Shader writeable mode bits.
+    HW_REG_STATUS       Shader read-only status.
+    HW_REG_TRAPSTS      Trap status.
+    HW_REG_HW_ID1       Id of wave, simd, compute unit, etc.
+    HW_REG_HW_ID2       Id of queue, pipeline, etc.
+    HW_REG_GPR_ALLOC    Per-wave SGPR and VGPR allocation.
+    HW_REG_LDS_ALLOC    Per-wave LDS allocation.
+    HW_REG_IB_STS       Counters of outstanding instructions.
+    HW_REG_SH_MEM_BASES Memory aperture.
+    HW_REG_FLAT_SCR_LO  flat_scratch_lo register.
+    HW_REG_FLAT_SCR_HI  flat_scratch_hi register.
+    =================== ==========================================
+
+Examples:
+
+.. parsed-literal::
+
+    reg = 1
+    offset = 2
+    size = 4
+    hwreg_enc = reg | (offset << 6) | ((size - 1) << 11)
+
+    s_getreg_b32 s2, 0x1881
+    s_getreg_b32 s2, hwreg_enc                     // the same as above
+    s_getreg_b32 s2, hwreg(1, 2, 4)                // the same as above
+    s_getreg_b32 s2, hwreg(reg, offset, size)      // the same as above
+
+    s_getreg_b32 s2, hwreg(15)
+    s_getreg_b32 s2, hwreg(51, 1, 31)
+    s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
diff --git a/llvm/docs/AMDGPU/gfx12_imm16.rst b/llvm/docs/AMDGPU/gfx12_imm16.rst
new file mode 100644
index 0000000000000..44e6d5856a558
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_imm16.rst
@@ -0,0 +1,7 @@
+.. _amdgpu_synid_imm16:
+
+imm16
+======
+
+An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+
diff --git a/llvm/docs/AMDGPU/gfx12_ioffset.rst b/llvm/docs/AMDGPU/gfx12_ioffset.rst
new file mode 100644
index 0000000000000..0901b774f8144
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_ioffset.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_ioffset:
+
+ioffset
+=======
+
+*Size:* 1 dword.
+
+*Operands:* 
diff --git a/llvm/docs/AMDGPU/gfx12_label.rst b/llvm/docs/AMDGPU/gfx12_label.rst
new file mode 100644
index 0000000000000..bdd6e1cb1ee8d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_label.rst
@@ -0,0 +1,29 @@
+.. _amdgpu_synid_label:
+
+label
+=====
+
+A branch target which is a 16-bit signed integer treated as a PC-relative dword offset.
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
+* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
+
+Examples:
+
+.. parsed-literal::
+
+  offset = 30
+  label_1:
+  label_2 = . + 4
+
+  s_branch 32
+  s_branch offset + 2
+  s_branch label_1
+  s_branch label_2
+  s_branch label_3
+  s_branch label_4
+
+  label_3 = label_2 + 4
+  label_4:
diff --git a/llvm/docs/AMDGPU/gfx12_literal_1f74c7.rst b/llvm/docs/AMDGPU/gfx12_literal_1f74c7.rst
new file mode 100644
index 0000000000000..7442c5d5c89dc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_literal_1f74c7.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_literal_1f74c7:
+
+literal
+=======
+
+*Size:* 2 dwords.
+
+*Operands:* 
diff --git a/llvm/docs/AMDGPU/gfx12_literal_81e671.rst b/llvm/docs/AMDGPU/gfx12_literal_81e671.rst
new file mode 100644
index 0000000000000..ab1b05601ff68
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_literal_81e671.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_literal_81e671:
+
+literal
+=======
+
+*Size:* 1 dword.
+
+*Operands:* 
diff --git a/llvm/docs/AMDGPU/gfx12_m.rst b/llvm/docs/AMDGPU/gfx12_m.rst
new file mode 100644
index 0000000000000..7cfee90bae2ce
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_m.rst
@@ -0,0 +1,13 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_m:
+
+m
+=
+
+This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
diff --git a/llvm/docs/AMDGPU/gfx12_rsrc_5fe6d8.rst b/llvm/docs/AMDGPU/gfx12_rsrc_5fe6d8.rst
new file mode 100644
index 0000000000000..d1a475f205329
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_rsrc_5fe6d8.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_rsrc_5fe6d8:
+
+rsrc
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_rsrc_c9f929.rst b/llvm/docs/AMDGPU/gfx12_rsrc_c9f929.rst
new file mode 100644
index 0000000000000..180ae068d2ceb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_rsrc_c9f929.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_rsrc_c9f929:
+
+rsrc
+====
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_saddr_cdc95c.rst b/llvm/docs/AMDGPU/gfx12_saddr_cdc95c.rst
new file mode 100644
index 0000000000000..4b3511fc76671
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_saddr_cdc95c.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_saddr_cdc95c:
+
+saddr
+=====
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_saddr_d42b64.rst b/llvm/docs/AMDGPU/gfx12_saddr_d42b64.rst
new file mode 100644
index 0000000000000..d3de11dfaade8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_saddr_d42b64.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_saddr_d42b64:
+
+saddr
+=====
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_samp.rst b/llvm/docs/AMDGPU/gfx12_samp.rst
new file mode 100644
index 0000000000000..2bb15e58db5fe
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_samp.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_samp:
+
+samp
+====
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_sbase_453b95.rst b/llvm/docs/AMDGPU/gfx12_sbase_453b95.rst
new file mode 100644
index 0000000000000..54c2deed4e5f1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sbase_453b95.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sbase_453b95:
+
+sbase
+=====
+
+A 128-bit buffer resource constant for scalar memory operations which provides a base address, a size and a stride.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_sbase_47adb7.rst b/llvm/docs/AMDGPU/gfx12_sbase_47adb7.rst
new file mode 100644
index 0000000000000..2308b3d44585c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sbase_47adb7.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sbase_47adb7:
+
+sbase
+=====
+
+A 64-bit base address for scalar memory operations.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdata_0974a4.rst b/llvm/docs/AMDGPU/gfx12_sdata_0974a4.rst
new file mode 100644
index 0000000000000..d498f8c705210
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdata_0974a4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdata_0974a4:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdata_354189.rst b/llvm/docs/AMDGPU/gfx12_sdata_354189.rst
new file mode 100644
index 0000000000000..c50665474c461
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdata_354189.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdata_354189:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdata_4585b8.rst b/llvm/docs/AMDGPU/gfx12_sdata_4585b8.rst
new file mode 100644
index 0000000000000..42f66f33e6ad4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdata_4585b8.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdata_4585b8:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdata_5c7b50.rst b/llvm/docs/AMDGPU/gfx12_sdata_5c7b50.rst
new file mode 100644
index 0000000000000..028461a4a07da
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdata_5c7b50.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdata_5c7b50:
+
+sdata
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* 
diff --git a/llvm/docs/AMDGPU/gfx12_sdata_6c003b.rst b/llvm/docs/AMDGPU/gfx12_sdata_6c003b.rst
new file mode 100644
index 0000000000000..87e19a95f2b8b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdata_6c003b.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdata_6c003b:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 16 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdata_836716.rst b/llvm/docs/AMDGPU/gfx12_sdata_836716.rst
new file mode 100644
index 0000000000000..be1bce94e7062
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdata_836716.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdata_836716:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdata_d725ab.rst b/llvm/docs/AMDGPU/gfx12_sdata_d725ab.rst
new file mode 100644
index 0000000000000..c882df8dad6c1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdata_d725ab.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdata_d725ab:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`simm8<amdgpu_synid_simm8>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdata_dd9dd8.rst b/llvm/docs/AMDGPU/gfx12_sdata_dd9dd8.rst
new file mode 100644
index 0000000000000..64658894fee95
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdata_dd9dd8.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdata_dd9dd8:
+
+sdata
+=====
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdst_006c40.rst b/llvm/docs/AMDGPU/gfx12_sdst_006c40.rst
new file mode 100644
index 0000000000000..f269b05c65edc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdst_006c40.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdst_006c40:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdst_20064d.rst b/llvm/docs/AMDGPU/gfx12_sdst_20064d.rst
new file mode 100644
index 0000000000000..83c11a2e03eae
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdst_20064d.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdst_20064d:
+
+sdst
+====
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdst_354189.rst b/llvm/docs/AMDGPU/gfx12_sdst_354189.rst
new file mode 100644
index 0000000000000..8433406a20591
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdst_354189.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdst_354189:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdst_836716.rst b/llvm/docs/AMDGPU/gfx12_sdst_836716.rst
new file mode 100644
index 0000000000000..abce5696f6716
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdst_836716.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdst_836716:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdst_ced58d.rst b/llvm/docs/AMDGPU/gfx12_sdst_ced58d.rst
new file mode 100644
index 0000000000000..e0072d90a4cfd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdst_ced58d.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdst_ced58d:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_sdst_e701cc.rst b/llvm/docs/AMDGPU/gfx12_sdst_e701cc.rst
new file mode 100644
index 0000000000000..33e8c376af67f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sdst_e701cc.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_sdst_e701cc:
+
+sdst
+====
+
+Instruction output.
+
+*Size:* 1 dword if wavefront size is 32, otherwise 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_sendmsg.rst b/llvm/docs/AMDGPU/gfx12_sendmsg.rst
new file mode 100644
index 0000000000000..cb51be04555fe
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sendmsg.rst
@@ -0,0 +1,48 @@
+.. _amdgpu_synid_sendmsg:
+
+sendmsg
+=======
+
+An 8-bit value in simm16[7:0] encodes the message type.
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A *sendmsg* value described below.
+
+
+    ==================================== ====================================================
+    Sendmsg Value Syntax                 Description
+    ==================================== ====================================================
+    sendmsg(<*type*>)                    A message identified by its *type*.
+    ==================================== ====================================================
+
+*Type* may be specified using message *name* or message *id*.
+
+Numeric values may be specified as positive :ref:`integer numbers<amdgpu_synid_integer_number>`
+or :ref:`absolute expressions<amdgpu_synid_absolute_expression>`.
+
+
+Only the following message types are valid.
+
+    ====================== ===========
+    Message type           simm16[7:0]
+    ====================== ===========
+    Reserved               0 
+    MSG_INTERRUPT          1
+    MSG_HS_TESSFACTOR      2
+    MSG_DEALLOC_VGPRS      3
+    MSG_GS_ALLOC_REQ       9
+    ====================== ===========
+
+Examples:
+
+.. parsed-literal::
+
+    // numeric message code
+    msg = 0x1
+    s_sendmsg 0x3
+    s_sendmsg msg + 2
+
+    // sendmsg with strict arguments validation
+    s_sendmsg sendmsg(MSG_INTERRUPT)
diff --git a/llvm/docs/AMDGPU/gfx12_sendmsg_rtn.rst b/llvm/docs/AMDGPU/gfx12_sendmsg_rtn.rst
new file mode 100644
index 0000000000000..ebb591dc101e7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_sendmsg_rtn.rst
@@ -0,0 +1,30 @@
+.. _amdgpu_synid_sendmsg_rtn:
+
+sendmsg_rtn
+===========
+
+An 8-bit value in the instruction to encode the message type.
+
+This operand may be specified as one of the following:
+
+    * An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+    * A *sendmsg* value described below.
+
+    ==================================== ====================================================
+    Sendmsg Value Syntax                 Description
+    ==================================== ====================================================
+    sendmsg(MSG_RTN_GET_DOORBELL)        Get doorbell ID.
+    sendmsg(MSG_RTN_GET_DDID)            Get Draw/Dispatch ID.
+    sendmsg(MSG_RTN_GET_TMA)             Get TMA value.
+    sendmsg(MSG_RTN_GET_TBA)             Get TBA value.
+    sendmsg(MSG_RTN_GET_REALTIME)        Get REALTIME value.
+    sendmsg(MSG_RTN_SAVE_WAVE)           Report that this wave is ready to be context-saved.
+    ==================================== ====================================================
+
+Examples:
+
+.. parsed-literal::
+
+    s_sendmsg_rtn_b32 s0, 132
+    s_sendmsg_rtn_b32 s0, sendmsg(MSG_GET_REALTIME)
+
diff --git a/llvm/docs/AMDGPU/gfx12_simm16_15ccdd.rst b/llvm/docs/AMDGPU/gfx12_simm16_15ccdd.rst
new file mode 100644
index 0000000000000..0cb123393a309
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_simm16_15ccdd.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_simm16_15ccdd:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`version<amdgpu_synid_version>`
diff --git a/llvm/docs/AMDGPU/gfx12_simm16_218bea.rst b/llvm/docs/AMDGPU/gfx12_simm16_218bea.rst
new file mode 100644
index 0000000000000..e08605e0bfbfb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_simm16_218bea.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_simm16_218bea:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`waitcnt<amdgpu_synid_waitcnt>`
diff --git a/llvm/docs/AMDGPU/gfx12_simm16_39b593.rst b/llvm/docs/AMDGPU/gfx12_simm16_39b593.rst
new file mode 100644
index 0000000000000..babb4b689a519
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_simm16_39b593.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_simm16_39b593:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`imm16<amdgpu_synid_imm16>`
diff --git a/llvm/docs/AMDGPU/gfx12_simm16_3d2a4f.rst b/llvm/docs/AMDGPU/gfx12_simm16_3d2a4f.rst
new file mode 100644
index 0000000000000..cc8dbc6742803
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_simm16_3d2a4f.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_simm16_3d2a4f:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`label<amdgpu_synid_label>`
diff --git a/llvm/docs/AMDGPU/gfx12_simm16_730a13.rst b/llvm/docs/AMDGPU/gfx12_simm16_730a13.rst
new file mode 100644
index 0000000000000..93596db9287be
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_simm16_730a13.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_simm16_730a13:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`clause<amdgpu_synid_clause>`
diff --git a/llvm/docs/AMDGPU/gfx12_simm16_7ed651.rst b/llvm/docs/AMDGPU/gfx12_simm16_7ed651.rst
new file mode 100644
index 0000000000000..fc63930c30334
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_simm16_7ed651.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_simm16_7ed651:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`hwreg<amdgpu_synid_hwreg>`
diff --git a/llvm/docs/AMDGPU/gfx12_simm16_81e671.rst b/llvm/docs/AMDGPU/gfx12_simm16_81e671.rst
new file mode 100644
index 0000000000000..16dcf397b48cf
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_simm16_81e671.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_simm16_81e671:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* 
diff --git a/llvm/docs/AMDGPU/gfx12_simm16_c98889.rst b/llvm/docs/AMDGPU/gfx12_simm16_c98889.rst
new file mode 100644
index 0000000000000..03e007af73690
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_simm16_c98889.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_simm16_c98889:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`delay<amdgpu_synid_delay>`
diff --git a/llvm/docs/AMDGPU/gfx12_simm16_cc1716.rst b/llvm/docs/AMDGPU/gfx12_simm16_cc1716.rst
new file mode 100644
index 0000000000000..e53f8125c3398
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_simm16_cc1716.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_simm16_cc1716:
+
+simm16
+======
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`hwreg<amdgpu_synid_hwreg>`
diff --git a/llvm/docs/AMDGPU/gfx12_simm16_ee8b30.rst b/llvm/docs/AMDGPU/gfx12_simm16_ee8b30.rst
new file mode 100644
index 0000000000000..9bdac9b6056e7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_simm16_ee8b30.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_simm16_ee8b30:
+
+simm16
+======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`sendmsg<amdgpu_synid_sendmsg>`
diff --git a/llvm/docs/AMDGPU/gfx12_soffset_8ec073.rst b/llvm/docs/AMDGPU/gfx12_soffset_8ec073.rst
new file mode 100644
index 0000000000000..44de0304b46cf
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_soffset_8ec073.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_soffset_8ec073:
+
+soffset
+=======
+
+An unsigned 20-bit offset added to the base address to get memory address.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_soffset_c5b88c.rst b/llvm/docs/AMDGPU/gfx12_soffset_c5b88c.rst
new file mode 100644
index 0000000000000..d115150d11d71
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_soffset_c5b88c.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_soffset_c5b88c:
+
+soffset
+=======
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_soffset_ec005a.rst b/llvm/docs/AMDGPU/gfx12_soffset_ec005a.rst
new file mode 100644
index 0000000000000..bd571b6499603
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_soffset_ec005a.rst
@@ -0,0 +1,20 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_soffset_ec005a:
+
+soffset
+=======
+
+An offset added to the base address to get memory address.
+
+* If offset is specified as a register, it supplies an unsigned byte offset.
+* If offset is specified as a 21-bit immediate, it supplies a signed byte offset.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_src0_5727cf.rst b/llvm/docs/AMDGPU/gfx12_src0_5727cf.rst
new file mode 100644
index 0000000000000..15fde5c33daab
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src0_5727cf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src0_5727cf:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_src0_5cae62.rst b/llvm/docs/AMDGPU/gfx12_src0_5cae62.rst
new file mode 100644
index 0000000000000..fa02f046b1804
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src0_5cae62.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src0_5cae62:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx12_src0_6802ce.rst b/llvm/docs/AMDGPU/gfx12_src0_6802ce.rst
new file mode 100644
index 0000000000000..e17a719c8b02c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src0_6802ce.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src0_6802ce:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_src0_85aab6.rst b/llvm/docs/AMDGPU/gfx12_src0_85aab6.rst
new file mode 100644
index 0000000000000..effa6f69c6acb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src0_85aab6.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src0_85aab6:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_src0_c4593f.rst b/llvm/docs/AMDGPU/gfx12_src0_c4593f.rst
new file mode 100644
index 0000000000000..bbe6191f49944
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src0_c4593f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src0_c4593f:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_src0_e016a1.rst b/llvm/docs/AMDGPU/gfx12_src0_e016a1.rst
new file mode 100644
index 0000000000000..c2d23d737610d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src0_e016a1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src0_e016a1:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_src0_fd235e.rst b/llvm/docs/AMDGPU/gfx12_src0_fd235e.rst
new file mode 100644
index 0000000000000..dc048af280704
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src0_fd235e.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src0_fd235e:
+
+src0
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_src1_5727cf.rst b/llvm/docs/AMDGPU/gfx12_src1_5727cf.rst
new file mode 100644
index 0000000000000..d1d08370eab76
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src1_5727cf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src1_5727cf:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_src1_5cae62.rst b/llvm/docs/AMDGPU/gfx12_src1_5cae62.rst
new file mode 100644
index 0000000000000..3ad591ce779a7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src1_5cae62.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src1_5cae62:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx12_src1_6802ce.rst b/llvm/docs/AMDGPU/gfx12_src1_6802ce.rst
new file mode 100644
index 0000000000000..84ff631fc275d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src1_6802ce.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src1_6802ce:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_src1_731030.rst b/llvm/docs/AMDGPU/gfx12_src1_731030.rst
new file mode 100644
index 0000000000000..8c67699145a1f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src1_731030.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src1_731030:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_src1_977794.rst b/llvm/docs/AMDGPU/gfx12_src1_977794.rst
new file mode 100644
index 0000000000000..765134002d94b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src1_977794.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src1_977794:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_src1_c4593f.rst b/llvm/docs/AMDGPU/gfx12_src1_c4593f.rst
new file mode 100644
index 0000000000000..aba4da84faee5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src1_c4593f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src1_c4593f:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_src1_e016a1.rst b/llvm/docs/AMDGPU/gfx12_src1_e016a1.rst
new file mode 100644
index 0000000000000..438585390ec88
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src1_e016a1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src1_e016a1:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_src1_fd235e.rst b/llvm/docs/AMDGPU/gfx12_src1_fd235e.rst
new file mode 100644
index 0000000000000..5863e93170ef6
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src1_fd235e.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src1_fd235e:
+
+src1
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_src2_2797bc.rst b/llvm/docs/AMDGPU/gfx12_src2_2797bc.rst
new file mode 100644
index 0000000000000..b393e2ac36b96
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src2_2797bc.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src2_2797bc:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_src2_5727cf.rst b/llvm/docs/AMDGPU/gfx12_src2_5727cf.rst
new file mode 100644
index 0000000000000..9ffaa079f6b91
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src2_5727cf.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src2_5727cf:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_src2_5cae62.rst b/llvm/docs/AMDGPU/gfx12_src2_5cae62.rst
new file mode 100644
index 0000000000000..46d65cb3bad5b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src2_5cae62.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src2_5cae62:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx12_src2_6802ce.rst b/llvm/docs/AMDGPU/gfx12_src2_6802ce.rst
new file mode 100644
index 0000000000000..0ad2ede9df4ac
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src2_6802ce.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src2_6802ce:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_src2_7b936a.rst b/llvm/docs/AMDGPU/gfx12_src2_7b936a.rst
new file mode 100644
index 0000000000000..9f1ea3c3ab944
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src2_7b936a.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src2_7b936a:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx12_src2_96fbd3.rst b/llvm/docs/AMDGPU/gfx12_src2_96fbd3.rst
new file mode 100644
index 0000000000000..884d089d544c2
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src2_96fbd3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src2_96fbd3:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`fconst<amdgpu_synid_fconst>`
diff --git a/llvm/docs/AMDGPU/gfx12_src2_c4593f.rst b/llvm/docs/AMDGPU/gfx12_src2_c4593f.rst
new file mode 100644
index 0000000000000..849230b5a56a2
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src2_c4593f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src2_c4593f:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_src2_e016a1.rst b/llvm/docs/AMDGPU/gfx12_src2_e016a1.rst
new file mode 100644
index 0000000000000..266c4eaedf72d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_src2_e016a1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_src2_e016a1:
+
+src2
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_srcx0.rst b/llvm/docs/AMDGPU/gfx12_srcx0.rst
new file mode 100644
index 0000000000000..57b05a18c3100
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_srcx0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_srcx0:
+
+srcx0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_srcy0.rst b/llvm/docs/AMDGPU/gfx12_srcy0.rst
new file mode 100644
index 0000000000000..350b7428668ba
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_srcy0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_srcy0:
+
+srcy0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_ssrc0_007f9c.rst b/llvm/docs/AMDGPU/gfx12_ssrc0_007f9c.rst
new file mode 100644
index 0000000000000..c3f33e4f78fdd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_ssrc0_007f9c.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_ssrc0_007f9c:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_ssrc0_1a9ca5.rst b/llvm/docs/AMDGPU/gfx12_ssrc0_1a9ca5.rst
new file mode 100644
index 0000000000000..5aa3f2d3585ac
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_ssrc0_1a9ca5.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_ssrc0_1a9ca5:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`m0<amdgpu_synid_m0>`
diff --git a/llvm/docs/AMDGPU/gfx12_ssrc0_245536.rst b/llvm/docs/AMDGPU/gfx12_ssrc0_245536.rst
new file mode 100644
index 0000000000000..36925daf7a86c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_ssrc0_245536.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_ssrc0_245536:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`sendmsg_rtn<amdgpu_synid_sendmsg_rtn>`
diff --git a/llvm/docs/AMDGPU/gfx12_ssrc0_2797bc.rst b/llvm/docs/AMDGPU/gfx12_ssrc0_2797bc.rst
new file mode 100644
index 0000000000000..4eae7050ea714
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_ssrc0_2797bc.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_ssrc0_2797bc:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx12_ssrc0_bbb4c6.rst b/llvm/docs/AMDGPU/gfx12_ssrc0_bbb4c6.rst
new file mode 100644
index 0000000000000..a29f83d36d48f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_ssrc0_bbb4c6.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_ssrc0_bbb4c6:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx12_ssrc0_c4593f.rst b/llvm/docs/AMDGPU/gfx12_ssrc0_c4593f.rst
new file mode 100644
index 0000000000000..33ca4d608d7df
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_ssrc0_c4593f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_ssrc0_c4593f:
+
+ssrc0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_ssrc1_bbb4c6.rst b/llvm/docs/AMDGPU/gfx12_ssrc1_bbb4c6.rst
new file mode 100644
index 0000000000000..1f3ea343f3a09
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_ssrc1_bbb4c6.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_ssrc1_bbb4c6:
+
+ssrc1
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx12_ssrc1_c4593f.rst b/llvm/docs/AMDGPU/gfx12_ssrc1_c4593f.rst
new file mode 100644
index 0000000000000..f81d0f203f07b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_ssrc1_c4593f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_ssrc1_c4593f:
+
+ssrc1
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`fconst<amdgpu_synid_fconst>`, :ref:`literal<amdgpu_synid_literal>`, :ref:`exec_hi<amdgpu_synid_exec_hi>`, :ref:`exec_lo<amdgpu_synid_exec_lo>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_tgt.rst b/llvm/docs/AMDGPU/gfx12_tgt.rst
new file mode 100644
index 0000000000000..83a25aa466bfb
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_tgt.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_tgt:
+
+tgt
+===
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* 
diff --git a/llvm/docs/AMDGPU/gfx12_vaddr_a972b9.rst b/llvm/docs/AMDGPU/gfx12_vaddr_a972b9.rst
new file mode 100644
index 0000000000000..223b50d6ef205
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vaddr_a972b9.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vaddr_a972b9:
+
+vaddr
+=====
+
+*Size:* 11 dwords.
+
+*Operands:* 
diff --git a/llvm/docs/AMDGPU/gfx12_vaddr_c12f43.rst b/llvm/docs/AMDGPU/gfx12_vaddr_c12f43.rst
new file mode 100644
index 0000000000000..5a93efec9f86a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vaddr_c12f43.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vaddr_c12f43:
+
+vaddr
+=====
+
+*Size:* 12 dwords.
+
+*Operands:* 
diff --git a/llvm/docs/AMDGPU/gfx12_vaddr_c8b8d4.rst b/llvm/docs/AMDGPU/gfx12_vaddr_c8b8d4.rst
new file mode 100644
index 0000000000000..1998e1ddc9504
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vaddr_c8b8d4.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vaddr_c8b8d4:
+
+vaddr
+=====
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vaddr_d82160.rst b/llvm/docs/AMDGPU/gfx12_vaddr_d82160.rst
new file mode 100644
index 0000000000000..92d09a2399a2f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vaddr_d82160.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vaddr_d82160:
+
+vaddr
+=====
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vaddr_f2b449.rst b/llvm/docs/AMDGPU/gfx12_vaddr_f2b449.rst
new file mode 100644
index 0000000000000..10d7e0ad1fce4
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vaddr_f2b449.rst
@@ -0,0 +1,15 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vaddr_f2b449:
+
+vaddr
+=====
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vcc.rst b/llvm/docs/AMDGPU/gfx12_vcc.rst
new file mode 100644
index 0000000000000..e8509ff50a32f
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vcc.rst
@@ -0,0 +1,16 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vcc:
+
+vcc
+===
+
+Vector condition code. This operand depends on wavefront size:
+
+* Should be :ref:`vcc_lo<amdgpu_synid_vcc_lo>` if wavefront size is 32.
+* Should be :ref:`vcc<amdgpu_synid_vcc>` if wavefront size is 64.
diff --git a/llvm/docs/AMDGPU/gfx12_vdata_2eda77.rst b/llvm/docs/AMDGPU/gfx12_vdata_2eda77.rst
new file mode 100644
index 0000000000000..839ec86ce2634
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdata_2eda77.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdata_2eda77:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdata_48e42f.rst b/llvm/docs/AMDGPU/gfx12_vdata_48e42f.rst
new file mode 100644
index 0000000000000..d2ab49a951684
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdata_48e42f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdata_48e42f:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdata_69a144.rst b/llvm/docs/AMDGPU/gfx12_vdata_69a144.rst
new file mode 100644
index 0000000000000..22ac087b51e8e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdata_69a144.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdata_69a144:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdata_89680f.rst b/llvm/docs/AMDGPU/gfx12_vdata_89680f.rst
new file mode 100644
index 0000000000000..5f4f4782e410d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdata_89680f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdata_89680f:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdata_aac3e8.rst b/llvm/docs/AMDGPU/gfx12_vdata_aac3e8.rst
new file mode 100644
index 0000000000000..2e285ef86eebc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdata_aac3e8.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdata_aac3e8:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* 10 dwords.
+
+*Operands:* 
diff --git a/llvm/docs/AMDGPU/gfx12_vdata_bdb32f.rst b/llvm/docs/AMDGPU/gfx12_vdata_bdb32f.rst
new file mode 100644
index 0000000000000..109c7672541a5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdata_bdb32f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdata_bdb32f:
+
+vdata
+=====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdst_006c40.rst b/llvm/docs/AMDGPU/gfx12_vdst_006c40.rst
new file mode 100644
index 0000000000000..dc3ac95500037
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdst_006c40.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdst_006c40:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`vcc<amdgpu_synid_vcc>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdst_227281.rst b/llvm/docs/AMDGPU/gfx12_vdst_227281.rst
new file mode 100644
index 0000000000000..13fd9513245dd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdst_227281.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdst_227281:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords if wavefront size is 64, otherwise 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdst_2eda77.rst b/llvm/docs/AMDGPU/gfx12_vdst_2eda77.rst
new file mode 100644
index 0000000000000..9372e484cf5d9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdst_2eda77.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdst_2eda77:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdst_47d3bc.rst b/llvm/docs/AMDGPU/gfx12_vdst_47d3bc.rst
new file mode 100644
index 0000000000000..056fe3f197417
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdst_47d3bc.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdst_47d3bc:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 8 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdst_48e42f.rst b/llvm/docs/AMDGPU/gfx12_vdst_48e42f.rst
new file mode 100644
index 0000000000000..84ab35b36b7b3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdst_48e42f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdst_48e42f:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdst_69a144.rst b/llvm/docs/AMDGPU/gfx12_vdst_69a144.rst
new file mode 100644
index 0000000000000..70873ff9502b8
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdst_69a144.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdst_69a144:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdst_7de8e7.rst b/llvm/docs/AMDGPU/gfx12_vdst_7de8e7.rst
new file mode 100644
index 0000000000000..7248ea9449236
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdst_7de8e7.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdst_7de8e7:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdst_836716.rst b/llvm/docs/AMDGPU/gfx12_vdst_836716.rst
new file mode 100644
index 0000000000000..1cd43ee9f620a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdst_836716.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdst_836716:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`vcc_hi<amdgpu_synid_vcc_hi>`, :ref:`vcc_lo<amdgpu_synid_vcc_lo>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdst_89680f.rst b/llvm/docs/AMDGPU/gfx12_vdst_89680f.rst
new file mode 100644
index 0000000000000..b4f055cc1574d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdst_89680f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdst_89680f:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdst_bdb32f.rst b/llvm/docs/AMDGPU/gfx12_vdst_bdb32f.rst
new file mode 100644
index 0000000000000..e2a4a47987b7c
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdst_bdb32f.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdst_bdb32f:
+
+vdst
+====
+
+Instruction output.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdstx.rst b/llvm/docs/AMDGPU/gfx12_vdstx.rst
new file mode 100644
index 0000000000000..4b95d4d0d84ba
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdstx.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdstx:
+
+vdstx
+=====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vdsty.rst b/llvm/docs/AMDGPU/gfx12_vdsty.rst
new file mode 100644
index 0000000000000..cf0b4641308be
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vdsty.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vdsty:
+
+vdsty
+=====
+
+Instruction output.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_version.rst b/llvm/docs/AMDGPU/gfx12_version.rst
new file mode 100644
index 0000000000000..4e490ca4954a9
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_version.rst
@@ -0,0 +1,7 @@
+.. _amdgpu_synid_version:
+
+version
+=======
+
+Microcode version header.
+
diff --git a/llvm/docs/AMDGPU/gfx12_vsrc0.rst b/llvm/docs/AMDGPU/gfx12_vsrc0.rst
new file mode 100644
index 0000000000000..fb381690c3692
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrc0.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrc0:
+
+vsrc0
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrc1_6802ce.rst b/llvm/docs/AMDGPU/gfx12_vsrc1_6802ce.rst
new file mode 100644
index 0000000000000..449054574be9b
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrc1_6802ce.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrc1_6802ce:
+
+vsrc1
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrc1_fd235e.rst b/llvm/docs/AMDGPU/gfx12_vsrc1_fd235e.rst
new file mode 100644
index 0000000000000..d6567c2fd9cef
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrc1_fd235e.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrc1_fd235e:
+
+vsrc1
+=====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrc2.rst b/llvm/docs/AMDGPU/gfx12_vsrc2.rst
new file mode 100644
index 0000000000000..fe20832437431
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrc2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrc2:
+
+vsrc2
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrc3.rst b/llvm/docs/AMDGPU/gfx12_vsrc3.rst
new file mode 100644
index 0000000000000..18df9e4418f0e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrc3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrc3:
+
+vsrc3
+=====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrc_56f215.rst b/llvm/docs/AMDGPU/gfx12_vsrc_56f215.rst
new file mode 100644
index 0000000000000..166da38acb079
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrc_56f215.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrc_56f215:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 3 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrc_6802ce.rst b/llvm/docs/AMDGPU/gfx12_vsrc_6802ce.rst
new file mode 100644
index 0000000000000..e879c2bad2038
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrc_6802ce.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrc_6802ce:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrc_89fd7b.rst b/llvm/docs/AMDGPU/gfx12_vsrc_89fd7b.rst
new file mode 100644
index 0000000000000..c521e7261c59e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrc_89fd7b.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrc_89fd7b:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 32 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrc_e016a1.rst b/llvm/docs/AMDGPU/gfx12_vsrc_e016a1.rst
new file mode 100644
index 0000000000000..84eb2eda944b7
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrc_e016a1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrc_e016a1:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 4 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrc_fd235e.rst b/llvm/docs/AMDGPU/gfx12_vsrc_fd235e.rst
new file mode 100644
index 0000000000000..640a235730f93
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrc_fd235e.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrc_fd235e:
+
+vsrc
+====
+
+Instruction input.
+
+*Size:* 2 dwords.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrcx1.rst b/llvm/docs/AMDGPU/gfx12_vsrcx1.rst
new file mode 100644
index 0000000000000..9dab58c459b2e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrcx1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrcx1:
+
+vsrcx1
+======
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_vsrcy1.rst b/llvm/docs/AMDGPU/gfx12_vsrcy1.rst
new file mode 100644
index 0000000000000..496b2d66d2ff5
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_vsrcy1.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_gfx12_vsrcy1:
+
+vsrcy1
+======
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx12_waitcnt.rst b/llvm/docs/AMDGPU/gfx12_waitcnt.rst
new file mode 100644
index 0000000000000..454122212f64e
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx12_waitcnt.rst
@@ -0,0 +1,55 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid_waitcnt:
+
+waitcnt
+=======
+
+Counts of outstanding instructions to wait for.
+
+The bits of this operand have the following meaning:
+
+   ===== ================================================ ============
+   Bits  Description                                      Value Range
+   ===== ================================================ ============
+   2:0   EXP_CNT: export and LDSDIR count.                0..7
+   3:3   Unused                                           \-
+   9:4   LGKM_CNT: LDS, GDS, Constant and Message count.  0..63
+   15:10 VM_CNT: vector memory operations count.          0..63
+   ===== ================================================ ============
+
+This operand may be specified as one of the following:
+
+* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..0xFFFF.
+* A combination of *vmcnt*, *expcnt*, *lgkmcnt* and other values described below.
+
+    ====================== ======================================================================
+    Syntax                 Description
+    ====================== ======================================================================
+    vmcnt(<*N*>)           A VM_CNT value. *N* must not exceed the largest VM_CNT value.
+    expcnt(<*N*>)          An EXP_CNT value. *N* must not exceed the largest EXP_CNT value.
+    lgkmcnt(<*N*>)         An LGKM_CNT value. *N* must not exceed the largest LGKM_CNT value.
+    vmcnt_sat(<*N*>)       A VM_CNT value computed as min(*N*, the largest VM_CNT value).
+    expcnt_sat(<*N*>)      An EXP_CNT value computed as min(*N*, the largest EXP_CNT value).
+    lgkmcnt_sat(<*N*>)     An LGKM_CNT value computed as min(*N*, the largest LGKM_CNT value).
+    ====================== ======================================================================
+
+These values may be specified in any order. Spaces, ampersands and commas may be used as optional separators.
+
+*N* is either an
+:ref:`integer number<amdgpu_synid_integer_number>` or an
+:ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
+Examples:
+
+.. parsed-literal::
+
+    s_waitcnt vmcnt(1)
+    s_waitcnt expcnt(2) lgkmcnt(3)
+    s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
+    s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
diff --git a/llvm/docs/AMDGPUModifierSyntax.rst b/llvm/docs/AMDGPUModifierSyntax.rst
index 334bdafefbbe2..8a60663b7303c 100644
--- a/llvm/docs/AMDGPUModifierSyntax.rst
+++ b/llvm/docs/AMDGPUModifierSyntax.rst
@@ -1078,6 +1078,73 @@ Examples:
   offset:0xfffff
   offset:-x
 
+.. _amdgpu_synid_smem_offset24s:
+
+offset24s
+~~~~~~~~~
+
+Specifies a signed 24-bit offset, in bytes. The default value is 0.
+
+    ============================= ====================================================================
+    Syntax                        Description
+    ============================= ====================================================================
+    offset:{-0x1000000..0xFFFFFF} Specifies an offset as an
+                                  :ref:`integer number <amdgpu_synid_integer_number>`
+                                  or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+    ============================= ====================================================================
+
+Examples:
+
+.. parsed-literal::
+
+  offset:-1
+  offset:0xfffff
+  offset:-x
+
+.. _amdgpu_synid_th:
+
+th
+~~
+
+Specifies temporal hint of memory operation.
+
+    =============================== =========================================================
+    Syntax                          Description
+    =============================== =========================================================
+    TH_{LOAD|STORE}_RT              Regular
+    TH_{LOAD|STORE}_NT              Non-temporal
+    TH_{LOAD|STORE}_HT              High-temporal
+    TH_{LOAD|STORE}_LU              Last use. Not available in SYS scope.
+    TH_{LOAD|STORE}_WB              Regular (CU, SE); High-temporal with write-back (MALL)
+    TH_{LOAD|STORE}_NT_RT           Non-temporal (CU, SE); Regular (MALL)
+    TH_{LOAD|STORE}_RT_NT           Regular (CU, SE); Non-temporal (MALL)
+    TH_{LOAD|STORE}_NT_HT           Non-temporal (CU, SE); High-temporal (MALL)
+    TH_{LOAD|STORE}_NT_WB           Non-temporal (CU, SE); High-temporal with write-back (MALL)
+    TH_{LOAD|STORE}_BYPASS          Available for SYS scope only.
+    TH_ATOMIC_RT                    Regular
+    TH_ATOMIC_RT_RETURN             Regular. For atomic instructions that return values.
+    TH_ATOMIC_NT                    Non-temporal
+    TH_ATOMIC_NT_RETURN             Non-temporal. For atomic instructions that return values.
+    TH_ATOMIC_CASCADE_RT            Cascading atomic; Regular.
+    TH_ATOMIC_CASCADE_NT            Cascading atomic; Non-temporal.
+    =============================== =========================================================
+
+.. _amdgpu_synid_scope:
+
+scope
+~~~~~
+
+Specifies scope of memory operation.
+
+    =============================== =========================================================
+    Syntax                          Description
+    =============================== =========================================================
+    SCOPE_CU                        Coherency within a Compute Unit.
+    SCOPE_SE                        Coherency within a Shader Engine.
+    SCOPE_DEV                       Coherency within a single device.
+    SCOPE_SYS                       Coherency across the full system.
+    =============================== =========================================================
+
 VINTRP/VINTERP/LDSDIR Modifiers
 -------------------------------
 
@@ -1117,6 +1184,27 @@ The default value is zero. This is a safe value, but it may be suboptimal.
                      issuing this instruction.
     ================ ======================================================
 
+.. _amdgpu_synid_wait_va_vdst:
+
+wait_va_vdst
+~~~~~~~~~~~~
+
+Manually specify a wait on the VA_VDST counter before issuing this instruction. VA_VDST must be less
+than or equal to this value before the instruction is issued. If set to 15, no wait is performed.
+
+If unspecified the current default is zero. This is a safe value but may have poor performance characteristics.
+
+This modifier is a shorthand for the WAR hazard where VALU reads a VGPR that is written by a parameter
+load. Since there is no VA_VSRC counter we must use VA_VDST as a proxy to detect when the
+VALU instruction has completed:
+
+Examples:
+
+.. parsed-literal::
+
+  v_mov_b32 v1, v0
+  ds_param_load v0, . . . wait_va_vdst:0
+
 .. _amdgpu_synid_wait_vdst:
 
 wait_vdst
@@ -1135,6 +1223,27 @@ The default value is zero. This is a safe value, but it may be suboptimal.
                        issuing this instruction.
     ================== ======================================================
 
+.. _amdgpu_synid_wait_vm_vsrc:
+
+wait_vm_vsrc
+~~~~~~~~~~~~
+
+Manually specify a wait on the VM_VSRC counter before issuing this instruction. VM_VSRC must be less
+than or equal to this value before the instruction is issued. If set to 1, no wait is performed.
+
+If unspecified the current default is zero. This is a safe value but may have poor performance characteristics.
+
+This modifier is a shorthand for the WAR hazard where VMEM reads a VGPR that is written by a parameter
+load.
+
+Examples:
+
+.. parsed-literal::
+
+  buffer_load_b32 v1, v0, s0, 0
+  ds_param_load v0, . . . wait_vm_vsrc:0
+
+
 DPP8 Modifiers
 --------------
 
diff --git a/llvm/docs/AMDGPUOperandSyntax.rst b/llvm/docs/AMDGPUOperandSyntax.rst
index e8a76322fe76a..722290fb72e16 100644
--- a/llvm/docs/AMDGPUOperandSyntax.rst
+++ b/llvm/docs/AMDGPUOperandSyntax.rst
@@ -479,6 +479,7 @@ High and low 32 bits of *xnack mask* may be accessed as separate registers:
 
 .. _amdgpu_synid_vcc:
 .. _amdgpu_synid_vcc_lo:
+.. _amdgpu_synid_vcc_hi:
 
 vcc
 ---
@@ -523,6 +524,8 @@ including register indexing and bounds checking.
     =========== ===================================================
 
 .. _amdgpu_synid_exec:
+.. _amdgpu_synid_exec_lo:
+.. _amdgpu_synid_exec_hi:
 
 exec
 ----
@@ -752,6 +755,14 @@ or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
 
 The value must be in the range -0x100000..0x0FFFFF.
 
+.. _amdgpu_synid_simm8:
+
+simm8
+-----
+
+An 8-bit :ref:`integer number<amdgpu_synid_integer_number>`
+or an :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+
 .. _amdgpu_synid_off:
 
 off
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index b6d61a62f50ff..32625d43f637c 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -22,6 +22,7 @@ User Guide for AMDGPU Backend
    AMDGPU/AMDGPUAsmGFX1013
    AMDGPU/AMDGPUAsmGFX1030
    AMDGPU/AMDGPUAsmGFX11
+   AMDGPU/AMDGPUAsmGFX12
    AMDGPUModifierSyntax
    AMDGPUOperandSyntax
    AMDGPUInstructionSyntax
@@ -17720,6 +17721,7 @@ in this description.
                                                                 :doc:`gfx1102<AMDGPU/AMDGPUAsmGFX11>`
 
                                                                 :doc:`gfx1103<AMDGPU/AMDGPUAsmGFX11>`
+    RDNA 4        :doc:`GFX12<AMDGPU/AMDGPUAsmGFX12>`           :doc:`gfx1200<AMDGPU/AMDGPUAsmGFX12>`
     ============= ============================================= =======================================
 
 For more information about instructions, their semantics and supported