diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 8c4bb15a7e617..8b9ee7fca208e 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -245,10 +245,20 @@ CodeGenOptLevel MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
 MipsSubtarget &
 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
                                                const TargetMachine &TM) {
-  StringRef CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
+  const Triple &TT = TM.getTargetTriple();
+  StringRef CPUName = MIPS_MC::selectMipsCPU(TT, CPU);
+
+  std::string FullFS;
+  if (getABI().ArePtrs64bit()) {
+    FullFS = "+ptr64";
+    if (!FS.empty())
+      FullFS = (Twine(FullFS) + "," + FS).str();
+  } else {
+    FullFS = FS.str();
+  }
 
   // Parse features string.
-  ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
+  ParseSubtargetFeatures(CPUName, /*TuneCPU=*/CPUName, FullFS);
   // Initialize scheduling itinerary for the specified CPU.
   InstrItins = getInstrItineraryForCPU(CPUName);