diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 3401f6f04800e..b8f299965faa3 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -12404,14 +12404,14 @@ multiclass VNNI_rmb Op, string OpStr, SDNode OpNode, X86FoldableSchedWrite sched, X86VectorVTInfo VTI, bit IsCommutable> { let ExeDomain = VTI.ExeDomain in { - defm r : AVX512_maskable_3src, EVEX, VVVV, T8, Sched<[sched]>; - defm m : AVX512_maskable_3src Op, string OpStr, SDNode OpNode, EVEX, VVVV, EVEX_CD8<32, CD8VF>, T8, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; - defm mb : AVX512_maskable_3src; + (VPDPWSSDZrr VR512:$src1, VR512:$src2, VR512:$src3)>; def : Pat<(v16i32 (add VR512:$src1, (X86vpmaddwd_su VR512:$src2, (load addr:$src3)))), - (VPDPWSSDZm VR512:$src1, VR512:$src2, addr:$src3)>; + (VPDPWSSDZrm VR512:$src1, VR512:$src2, addr:$src3)>; } let Predicates = [HasVNNI,HasVLX] in { def : Pat<(v8i32 (add VR256X:$src1, (X86vpmaddwd_su VR256X:$src2, VR256X:$src3))), - (VPDPWSSDZ256r VR256X:$src1, VR256X:$src2, VR256X:$src3)>; + (VPDPWSSDZ256rr VR256X:$src1, VR256X:$src2, VR256X:$src3)>; def : Pat<(v8i32 (add VR256X:$src1, (X86vpmaddwd_su VR256X:$src2, (load addr:$src3)))), - (VPDPWSSDZ256m VR256X:$src1, VR256X:$src2, addr:$src3)>; + (VPDPWSSDZ256rm VR256X:$src1, VR256X:$src2, addr:$src3)>; def : Pat<(v4i32 (add VR128X:$src1, (X86vpmaddwd_su VR128X:$src2, VR128X:$src3))), - (VPDPWSSDZ128r VR128X:$src1, VR128X:$src2, VR128X:$src3)>; + (VPDPWSSDZ128rr VR128X:$src1, VR128X:$src2, VR128X:$src3)>; def : Pat<(v4i32 (add VR128X:$src1, (X86vpmaddwd_su VR128X:$src2, (load addr:$src3)))), - (VPDPWSSDZ128m VR128X:$src1, VR128X:$src2, addr:$src3)>; + (VPDPWSSDZ128rm VR128X:$src1, VR128X:$src2, addr:$src3)>; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index a68edf4d2b7ee..f109e29c0bff0 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -2939,78 +2939,78 @@ bool X86InstrInfo::findCommutedOpIndices(const MachineInstr &MI, case X86::VPDPBUUDSYrr: case X86::VPDPBUUDrr: case X86::VPDPBUUDYrr: - case X86::VPDPBSSDSZ128r: - case X86::VPDPBSSDSZ128rk: - case X86::VPDPBSSDSZ128rkz: - case X86::VPDPBSSDSZ256r: - case X86::VPDPBSSDSZ256rk: - case X86::VPDPBSSDSZ256rkz: - case X86::VPDPBSSDSZr: - case X86::VPDPBSSDSZrk: - case X86::VPDPBSSDSZrkz: - case X86::VPDPBSSDZ128r: - case X86::VPDPBSSDZ128rk: - case X86::VPDPBSSDZ128rkz: - case X86::VPDPBSSDZ256r: - case X86::VPDPBSSDZ256rk: - case X86::VPDPBSSDZ256rkz: - case X86::VPDPBSSDZr: - case X86::VPDPBSSDZrk: - case X86::VPDPBSSDZrkz: - case X86::VPDPBUUDSZ128r: - case X86::VPDPBUUDSZ128rk: - case X86::VPDPBUUDSZ128rkz: - case X86::VPDPBUUDSZ256r: - case X86::VPDPBUUDSZ256rk: - case X86::VPDPBUUDSZ256rkz: - case X86::VPDPBUUDSZr: - case X86::VPDPBUUDSZrk: - case X86::VPDPBUUDSZrkz: - case X86::VPDPBUUDZ128r: - case X86::VPDPBUUDZ128rk: - case X86::VPDPBUUDZ128rkz: - case X86::VPDPBUUDZ256r: - case X86::VPDPBUUDZ256rk: - case X86::VPDPBUUDZ256rkz: - case X86::VPDPBUUDZr: - case X86::VPDPBUUDZrk: - case X86::VPDPBUUDZrkz: - case X86::VPDPWSSDZ128r: - case X86::VPDPWSSDZ128rk: - case X86::VPDPWSSDZ128rkz: - case X86::VPDPWSSDZ256r: - case X86::VPDPWSSDZ256rk: - case X86::VPDPWSSDZ256rkz: - case X86::VPDPWSSDZr: - case X86::VPDPWSSDZrk: - case X86::VPDPWSSDZrkz: - case X86::VPDPWSSDSZ128r: - case X86::VPDPWSSDSZ128rk: - case X86::VPDPWSSDSZ128rkz: - case X86::VPDPWSSDSZ256r: - case X86::VPDPWSSDSZ256rk: - case X86::VPDPWSSDSZ256rkz: - case X86::VPDPWSSDSZr: - case X86::VPDPWSSDSZrk: - case X86::VPDPWSSDSZrkz: - case X86::VPDPWUUDZ128r: - case X86::VPDPWUUDZ128rk: - case X86::VPDPWUUDZ128rkz: - case X86::VPDPWUUDZ256r: - case X86::VPDPWUUDZ256rk: - case X86::VPDPWUUDZ256rkz: - case X86::VPDPWUUDZr: - case X86::VPDPWUUDZrk: - case X86::VPDPWUUDZrkz: - case X86::VPDPWUUDSZ128r: - case X86::VPDPWUUDSZ128rk: - case X86::VPDPWUUDSZ128rkz: - case X86::VPDPWUUDSZ256r: - case X86::VPDPWUUDSZ256rk: - case X86::VPDPWUUDSZ256rkz: - case X86::VPDPWUUDSZr: - case X86::VPDPWUUDSZrk: - case X86::VPDPWUUDSZrkz: + case X86::VPDPBSSDSZ128rr: + case X86::VPDPBSSDSZ128rrk: + case X86::VPDPBSSDSZ128rrkz: + case X86::VPDPBSSDSZ256rr: + case X86::VPDPBSSDSZ256rrk: + case X86::VPDPBSSDSZ256rrkz: + case X86::VPDPBSSDSZrr: + case X86::VPDPBSSDSZrrk: + case X86::VPDPBSSDSZrrkz: + case X86::VPDPBSSDZ128rr: + case X86::VPDPBSSDZ128rrk: + case X86::VPDPBSSDZ128rrkz: + case X86::VPDPBSSDZ256rr: + case X86::VPDPBSSDZ256rrk: + case X86::VPDPBSSDZ256rrkz: + case X86::VPDPBSSDZrr: + case X86::VPDPBSSDZrrk: + case X86::VPDPBSSDZrrkz: + case X86::VPDPBUUDSZ128rr: + case X86::VPDPBUUDSZ128rrk: + case X86::VPDPBUUDSZ128rrkz: + case X86::VPDPBUUDSZ256rr: + case X86::VPDPBUUDSZ256rrk: + case X86::VPDPBUUDSZ256rrkz: + case X86::VPDPBUUDSZrr: + case X86::VPDPBUUDSZrrk: + case X86::VPDPBUUDSZrrkz: + case X86::VPDPBUUDZ128rr: + case X86::VPDPBUUDZ128rrk: + case X86::VPDPBUUDZ128rrkz: + case X86::VPDPBUUDZ256rr: + case X86::VPDPBUUDZ256rrk: + case X86::VPDPBUUDZ256rrkz: + case X86::VPDPBUUDZrr: + case X86::VPDPBUUDZrrk: + case X86::VPDPBUUDZrrkz: + case X86::VPDPWSSDZ128rr: + case X86::VPDPWSSDZ128rrk: + case X86::VPDPWSSDZ128rrkz: + case X86::VPDPWSSDZ256rr: + case X86::VPDPWSSDZ256rrk: + case X86::VPDPWSSDZ256rrkz: + case X86::VPDPWSSDZrr: + case X86::VPDPWSSDZrrk: + case X86::VPDPWSSDZrrkz: + case X86::VPDPWSSDSZ128rr: + case X86::VPDPWSSDSZ128rrk: + case X86::VPDPWSSDSZ128rrkz: + case X86::VPDPWSSDSZ256rr: + case X86::VPDPWSSDSZ256rrk: + case X86::VPDPWSSDSZ256rrkz: + case X86::VPDPWSSDSZrr: + case X86::VPDPWSSDSZrrk: + case X86::VPDPWSSDSZrrkz: + case X86::VPDPWUUDZ128rr: + case X86::VPDPWUUDZ128rrk: + case X86::VPDPWUUDZ128rrkz: + case X86::VPDPWUUDZ256rr: + case X86::VPDPWUUDZ256rrk: + case X86::VPDPWUUDZ256rrkz: + case X86::VPDPWUUDZrr: + case X86::VPDPWUUDZrrk: + case X86::VPDPWUUDZrrkz: + case X86::VPDPWUUDSZ128rr: + case X86::VPDPWUUDSZ128rrk: + case X86::VPDPWUUDSZ128rrkz: + case X86::VPDPWUUDSZ256rr: + case X86::VPDPWUUDSZ256rrk: + case X86::VPDPWUUDSZ256rrkz: + case X86::VPDPWUUDSZrr: + case X86::VPDPWUUDSZrrk: + case X86::VPDPWUUDSZrrkz: case X86::VPMADD52HUQrr: case X86::VPMADD52HUQYrr: case X86::VPMADD52HUQZ128r: @@ -10822,15 +10822,15 @@ bool X86InstrInfo::getMachineCombinerPatterns( } break; } - case X86::VPDPWSSDZ128r: - case X86::VPDPWSSDZ128m: - case X86::VPDPWSSDZ256r: - case X86::VPDPWSSDZ256m: - case X86::VPDPWSSDZr: - case X86::VPDPWSSDZm: { - if (Subtarget.hasBWI() && !Subtarget.hasFastDPWSSD()) { - Patterns.push_back(X86MachineCombinerPattern::DPWSSD); - return true; + case X86::VPDPWSSDZ128rr: + case X86::VPDPWSSDZ128rm: + case X86::VPDPWSSDZ256rr: + case X86::VPDPWSSDZ256rm: + case X86::VPDPWSSDZrr: + case X86::VPDPWSSDZrm: { + if (Subtarget.hasBWI() && !Subtarget.hasFastDPWSSD()) { + Patterns.push_back(X86MachineCombinerPattern::DPWSSD); + return true; } break; } @@ -10866,11 +10866,11 @@ genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII, MaddOpc = X86::VPMADDWDrm; AddOpc = X86::VPADDDrr; break; - case X86::VPDPWSSDZ128r: + case X86::VPDPWSSDZ128rr: MaddOpc = X86::VPMADDWDZ128rr; AddOpc = X86::VPADDDZ128rr; break; - case X86::VPDPWSSDZ128m: + case X86::VPDPWSSDZ128rm: MaddOpc = X86::VPMADDWDZ128rm; AddOpc = X86::VPADDDZ128rr; break; @@ -10886,11 +10886,11 @@ genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII, MaddOpc = X86::VPMADDWDYrm; AddOpc = X86::VPADDDYrr; break; - case X86::VPDPWSSDZ256r: + case X86::VPDPWSSDZ256rr: MaddOpc = X86::VPMADDWDZ256rr; AddOpc = X86::VPADDDZ256rr; break; - case X86::VPDPWSSDZ256m: + case X86::VPDPWSSDZ256rm: MaddOpc = X86::VPMADDWDZ256rm; AddOpc = X86::VPADDDZ256rr; break; @@ -10898,11 +10898,11 @@ genAlternativeDpCodeSequence(MachineInstr &Root, const TargetInstrInfo &TII, // --> // vpmaddwd zmm3,zmm3,zmm1 // vpaddd zmm2,zmm2,zmm3 - case X86::VPDPWSSDZr: + case X86::VPDPWSSDZrr: MaddOpc = X86::VPMADDWDZrr; AddOpc = X86::VPADDDZrr; break; - case X86::VPDPWSSDZm: + case X86::VPDPWSSDZrm: MaddOpc = X86::VPMADDWDZrm; AddOpc = X86::VPADDDZrr; break; diff --git a/llvm/lib/Target/X86/X86ScheduleZnver4.td b/llvm/lib/Target/X86/X86ScheduleZnver4.td index a93c7e3a82f17..cc300548a50e6 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver4.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver4.td @@ -1567,7 +1567,7 @@ def Zn4WriteBUSDr_VPMADDr: SchedWriteRes<[Zn4FPFMisc01]> { let NumMicroOps = 1; } def : InstRW<[Zn4WriteBUSDr_VPMADDr], (instregex - "VPDP(BU|WS)(S|P)(S|D|DS)(Z|Z128|Z256)(r|rk|rkz)", + "VPDP(BU|WS)(S|P)(S|D|DS)(Z?|Z128?|Z256?|Y?)r(r|rk|rkz)", "VPMADD52(H|L)UQ(Z|Z128|Z256)(r|rk|rkz)" )>; diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc index 9a5ed0452d08a..5601aebdf0426 100644 --- a/llvm/test/TableGen/x86-fold-tables.inc +++ b/llvm/test/TableGen/x86-fold-tables.inc @@ -5365,84 +5365,84 @@ static const X86FoldTableEntry Table3[] = { {X86::VPCONFLICTQZ256rrk, X86::VPCONFLICTQZ256rmk, 0}, {X86::VPCONFLICTQZrrk, X86::VPCONFLICTQZrmk, 0}, {X86::VPDPBSSDSYrr, X86::VPDPBSSDSYrm, 0}, - {X86::VPDPBSSDSZ128r, X86::VPDPBSSDSZ128m, 0}, - {X86::VPDPBSSDSZ256r, X86::VPDPBSSDSZ256m, 0}, - {X86::VPDPBSSDSZr, X86::VPDPBSSDSZm, 0}, + {X86::VPDPBSSDSZ128rr, X86::VPDPBSSDSZ128rm, 0}, + {X86::VPDPBSSDSZ256rr, X86::VPDPBSSDSZ256rm, 0}, + {X86::VPDPBSSDSZrr, X86::VPDPBSSDSZrm, 0}, {X86::VPDPBSSDSrr, X86::VPDPBSSDSrm, 0}, {X86::VPDPBSSDYrr, X86::VPDPBSSDYrm, 0}, - {X86::VPDPBSSDZ128r, X86::VPDPBSSDZ128m, 0}, - {X86::VPDPBSSDZ256r, X86::VPDPBSSDZ256m, 0}, - {X86::VPDPBSSDZr, X86::VPDPBSSDZm, 0}, + {X86::VPDPBSSDZ128rr, X86::VPDPBSSDZ128rm, 0}, + {X86::VPDPBSSDZ256rr, X86::VPDPBSSDZ256rm, 0}, + {X86::VPDPBSSDZrr, X86::VPDPBSSDZrm, 0}, {X86::VPDPBSSDrr, X86::VPDPBSSDrm, 0}, {X86::VPDPBSUDSYrr, X86::VPDPBSUDSYrm, 0}, - {X86::VPDPBSUDSZ128r, X86::VPDPBSUDSZ128m, 0}, - {X86::VPDPBSUDSZ256r, X86::VPDPBSUDSZ256m, 0}, - {X86::VPDPBSUDSZr, X86::VPDPBSUDSZm, 0}, + {X86::VPDPBSUDSZ128rr, X86::VPDPBSUDSZ128rm, 0}, + {X86::VPDPBSUDSZ256rr, X86::VPDPBSUDSZ256rm, 0}, + {X86::VPDPBSUDSZrr, X86::VPDPBSUDSZrm, 0}, {X86::VPDPBSUDSrr, X86::VPDPBSUDSrm, 0}, {X86::VPDPBSUDYrr, X86::VPDPBSUDYrm, 0}, - {X86::VPDPBSUDZ128r, X86::VPDPBSUDZ128m, 0}, - {X86::VPDPBSUDZ256r, X86::VPDPBSUDZ256m, 0}, - {X86::VPDPBSUDZr, X86::VPDPBSUDZm, 0}, + {X86::VPDPBSUDZ128rr, X86::VPDPBSUDZ128rm, 0}, + {X86::VPDPBSUDZ256rr, X86::VPDPBSUDZ256rm, 0}, + {X86::VPDPBSUDZrr, X86::VPDPBSUDZrm, 0}, {X86::VPDPBSUDrr, X86::VPDPBSUDrm, 0}, {X86::VPDPBUSDSYrr, X86::VPDPBUSDSYrm, 0}, - {X86::VPDPBUSDSZ128r, X86::VPDPBUSDSZ128m, 0}, - {X86::VPDPBUSDSZ256r, X86::VPDPBUSDSZ256m, 0}, - {X86::VPDPBUSDSZr, X86::VPDPBUSDSZm, 0}, + {X86::VPDPBUSDSZ128rr, X86::VPDPBUSDSZ128rm, 0}, + {X86::VPDPBUSDSZ256rr, X86::VPDPBUSDSZ256rm, 0}, + {X86::VPDPBUSDSZrr, X86::VPDPBUSDSZrm, 0}, {X86::VPDPBUSDSrr, X86::VPDPBUSDSrm, 0}, {X86::VPDPBUSDYrr, X86::VPDPBUSDYrm, 0}, - {X86::VPDPBUSDZ128r, X86::VPDPBUSDZ128m, 0}, - {X86::VPDPBUSDZ256r, X86::VPDPBUSDZ256m, 0}, - {X86::VPDPBUSDZr, X86::VPDPBUSDZm, 0}, + {X86::VPDPBUSDZ128rr, X86::VPDPBUSDZ128rm, 0}, + {X86::VPDPBUSDZ256rr, X86::VPDPBUSDZ256rm, 0}, + {X86::VPDPBUSDZrr, X86::VPDPBUSDZrm, 0}, {X86::VPDPBUSDrr, X86::VPDPBUSDrm, 0}, {X86::VPDPBUUDSYrr, X86::VPDPBUUDSYrm, 0}, - {X86::VPDPBUUDSZ128r, X86::VPDPBUUDSZ128m, 0}, - {X86::VPDPBUUDSZ256r, X86::VPDPBUUDSZ256m, 0}, - {X86::VPDPBUUDSZr, X86::VPDPBUUDSZm, 0}, + {X86::VPDPBUUDSZ128rr, X86::VPDPBUUDSZ128rm, 0}, + {X86::VPDPBUUDSZ256rr, X86::VPDPBUUDSZ256rm, 0}, + {X86::VPDPBUUDSZrr, X86::VPDPBUUDSZrm, 0}, {X86::VPDPBUUDSrr, X86::VPDPBUUDSrm, 0}, {X86::VPDPBUUDYrr, X86::VPDPBUUDYrm, 0}, - {X86::VPDPBUUDZ128r, X86::VPDPBUUDZ128m, 0}, - {X86::VPDPBUUDZ256r, X86::VPDPBUUDZ256m, 0}, - {X86::VPDPBUUDZr, X86::VPDPBUUDZm, 0}, + {X86::VPDPBUUDZ128rr, X86::VPDPBUUDZ128rm, 0}, + {X86::VPDPBUUDZ256rr, X86::VPDPBUUDZ256rm, 0}, + {X86::VPDPBUUDZrr, X86::VPDPBUUDZrm, 0}, {X86::VPDPBUUDrr, X86::VPDPBUUDrm, 0}, {X86::VPDPWSSDSYrr, X86::VPDPWSSDSYrm, 0}, - {X86::VPDPWSSDSZ128r, X86::VPDPWSSDSZ128m, 0}, - {X86::VPDPWSSDSZ256r, X86::VPDPWSSDSZ256m, 0}, - {X86::VPDPWSSDSZr, X86::VPDPWSSDSZm, 0}, + {X86::VPDPWSSDSZ128rr, X86::VPDPWSSDSZ128rm, 0}, + {X86::VPDPWSSDSZ256rr, X86::VPDPWSSDSZ256rm, 0}, + {X86::VPDPWSSDSZrr, X86::VPDPWSSDSZrm, 0}, {X86::VPDPWSSDSrr, X86::VPDPWSSDSrm, 0}, {X86::VPDPWSSDYrr, X86::VPDPWSSDYrm, 0}, - {X86::VPDPWSSDZ128r, X86::VPDPWSSDZ128m, 0}, - {X86::VPDPWSSDZ256r, X86::VPDPWSSDZ256m, 0}, - {X86::VPDPWSSDZr, X86::VPDPWSSDZm, 0}, + {X86::VPDPWSSDZ128rr, X86::VPDPWSSDZ128rm, 0}, + {X86::VPDPWSSDZ256rr, X86::VPDPWSSDZ256rm, 0}, + {X86::VPDPWSSDZrr, X86::VPDPWSSDZrm, 0}, {X86::VPDPWSSDrr, X86::VPDPWSSDrm, 0}, {X86::VPDPWSUDSYrr, X86::VPDPWSUDSYrm, 0}, - {X86::VPDPWSUDSZ128r, X86::VPDPWSUDSZ128m, 0}, - {X86::VPDPWSUDSZ256r, X86::VPDPWSUDSZ256m, 0}, - {X86::VPDPWSUDSZr, X86::VPDPWSUDSZm, 0}, + {X86::VPDPWSUDSZ128rr, X86::VPDPWSUDSZ128rm, 0}, + {X86::VPDPWSUDSZ256rr, X86::VPDPWSUDSZ256rm, 0}, + {X86::VPDPWSUDSZrr, X86::VPDPWSUDSZrm, 0}, {X86::VPDPWSUDSrr, X86::VPDPWSUDSrm, 0}, {X86::VPDPWSUDYrr, X86::VPDPWSUDYrm, 0}, - {X86::VPDPWSUDZ128r, X86::VPDPWSUDZ128m, 0}, - {X86::VPDPWSUDZ256r, X86::VPDPWSUDZ256m, 0}, - {X86::VPDPWSUDZr, X86::VPDPWSUDZm, 0}, + {X86::VPDPWSUDZ128rr, X86::VPDPWSUDZ128rm, 0}, + {X86::VPDPWSUDZ256rr, X86::VPDPWSUDZ256rm, 0}, + {X86::VPDPWSUDZrr, X86::VPDPWSUDZrm, 0}, {X86::VPDPWSUDrr, X86::VPDPWSUDrm, 0}, {X86::VPDPWUSDSYrr, X86::VPDPWUSDSYrm, 0}, - {X86::VPDPWUSDSZ128r, X86::VPDPWUSDSZ128m, 0}, - {X86::VPDPWUSDSZ256r, X86::VPDPWUSDSZ256m, 0}, - {X86::VPDPWUSDSZr, X86::VPDPWUSDSZm, 0}, + {X86::VPDPWUSDSZ128rr, X86::VPDPWUSDSZ128rm, 0}, + {X86::VPDPWUSDSZ256rr, X86::VPDPWUSDSZ256rm, 0}, + {X86::VPDPWUSDSZrr, X86::VPDPWUSDSZrm, 0}, {X86::VPDPWUSDSrr, X86::VPDPWUSDSrm, 0}, {X86::VPDPWUSDYrr, X86::VPDPWUSDYrm, 0}, - {X86::VPDPWUSDZ128r, X86::VPDPWUSDZ128m, 0}, - {X86::VPDPWUSDZ256r, X86::VPDPWUSDZ256m, 0}, - {X86::VPDPWUSDZr, X86::VPDPWUSDZm, 0}, + {X86::VPDPWUSDZ128rr, X86::VPDPWUSDZ128rm, 0}, + {X86::VPDPWUSDZ256rr, X86::VPDPWUSDZ256rm, 0}, + {X86::VPDPWUSDZrr, X86::VPDPWUSDZrm, 0}, {X86::VPDPWUSDrr, X86::VPDPWUSDrm, 0}, {X86::VPDPWUUDSYrr, X86::VPDPWUUDSYrm, 0}, - {X86::VPDPWUUDSZ128r, X86::VPDPWUUDSZ128m, 0}, - {X86::VPDPWUUDSZ256r, X86::VPDPWUUDSZ256m, 0}, - {X86::VPDPWUUDSZr, X86::VPDPWUUDSZm, 0}, + {X86::VPDPWUUDSZ128rr, X86::VPDPWUUDSZ128rm, 0}, + {X86::VPDPWUUDSZ256rr, X86::VPDPWUUDSZ256rm, 0}, + {X86::VPDPWUUDSZrr, X86::VPDPWUUDSZrm, 0}, {X86::VPDPWUUDSrr, X86::VPDPWUUDSrm, 0}, {X86::VPDPWUUDYrr, X86::VPDPWUUDYrm, 0}, - {X86::VPDPWUUDZ128r, X86::VPDPWUUDZ128m, 0}, - {X86::VPDPWUUDZ256r, X86::VPDPWUUDZ256m, 0}, - {X86::VPDPWUUDZr, X86::VPDPWUUDZm, 0}, + {X86::VPDPWUUDZ128rr, X86::VPDPWUUDZ128rm, 0}, + {X86::VPDPWUUDZ256rr, X86::VPDPWUUDZ256rm, 0}, + {X86::VPDPWUUDZrr, X86::VPDPWUUDZrm, 0}, {X86::VPDPWUUDrr, X86::VPDPWUUDrm, 0}, {X86::VPERMBZ128rrkz, X86::VPERMBZ128rmkz, 0}, {X86::VPERMBZ256rrkz, X86::VPERMBZ256rmkz, 0}, @@ -6855,102 +6855,102 @@ static const X86FoldTableEntry Table4[] = { {X86::VPAVGWZ128rrk, X86::VPAVGWZ128rmk, 0}, {X86::VPAVGWZ256rrk, X86::VPAVGWZ256rmk, 0}, {X86::VPAVGWZrrk, X86::VPAVGWZrmk, 0}, - {X86::VPDPBSSDSZ128rk, X86::VPDPBSSDSZ128mk, 0}, - {X86::VPDPBSSDSZ128rkz, X86::VPDPBSSDSZ128mkz, 0}, - {X86::VPDPBSSDSZ256rk, X86::VPDPBSSDSZ256mk, 0}, - {X86::VPDPBSSDSZ256rkz, X86::VPDPBSSDSZ256mkz, 0}, - {X86::VPDPBSSDSZrk, X86::VPDPBSSDSZmk, 0}, - {X86::VPDPBSSDSZrkz, X86::VPDPBSSDSZmkz, 0}, - {X86::VPDPBSSDZ128rk, X86::VPDPBSSDZ128mk, 0}, - {X86::VPDPBSSDZ128rkz, X86::VPDPBSSDZ128mkz, 0}, - {X86::VPDPBSSDZ256rk, X86::VPDPBSSDZ256mk, 0}, - {X86::VPDPBSSDZ256rkz, X86::VPDPBSSDZ256mkz, 0}, - {X86::VPDPBSSDZrk, X86::VPDPBSSDZmk, 0}, - {X86::VPDPBSSDZrkz, X86::VPDPBSSDZmkz, 0}, - {X86::VPDPBSUDSZ128rk, X86::VPDPBSUDSZ128mk, 0}, - {X86::VPDPBSUDSZ128rkz, X86::VPDPBSUDSZ128mkz, 0}, - {X86::VPDPBSUDSZ256rk, X86::VPDPBSUDSZ256mk, 0}, - {X86::VPDPBSUDSZ256rkz, X86::VPDPBSUDSZ256mkz, 0}, - {X86::VPDPBSUDSZrk, X86::VPDPBSUDSZmk, 0}, - {X86::VPDPBSUDSZrkz, X86::VPDPBSUDSZmkz, 0}, - {X86::VPDPBSUDZ128rk, X86::VPDPBSUDZ128mk, 0}, - {X86::VPDPBSUDZ128rkz, X86::VPDPBSUDZ128mkz, 0}, - {X86::VPDPBSUDZ256rk, X86::VPDPBSUDZ256mk, 0}, - {X86::VPDPBSUDZ256rkz, X86::VPDPBSUDZ256mkz, 0}, - {X86::VPDPBSUDZrk, X86::VPDPBSUDZmk, 0}, - {X86::VPDPBSUDZrkz, X86::VPDPBSUDZmkz, 0}, - {X86::VPDPBUSDSZ128rk, X86::VPDPBUSDSZ128mk, 0}, - {X86::VPDPBUSDSZ128rkz, X86::VPDPBUSDSZ128mkz, 0}, - {X86::VPDPBUSDSZ256rk, X86::VPDPBUSDSZ256mk, 0}, - {X86::VPDPBUSDSZ256rkz, X86::VPDPBUSDSZ256mkz, 0}, - {X86::VPDPBUSDSZrk, X86::VPDPBUSDSZmk, 0}, - {X86::VPDPBUSDSZrkz, X86::VPDPBUSDSZmkz, 0}, - {X86::VPDPBUSDZ128rk, X86::VPDPBUSDZ128mk, 0}, - {X86::VPDPBUSDZ128rkz, X86::VPDPBUSDZ128mkz, 0}, - {X86::VPDPBUSDZ256rk, X86::VPDPBUSDZ256mk, 0}, - {X86::VPDPBUSDZ256rkz, X86::VPDPBUSDZ256mkz, 0}, - {X86::VPDPBUSDZrk, X86::VPDPBUSDZmk, 0}, - {X86::VPDPBUSDZrkz, X86::VPDPBUSDZmkz, 0}, - {X86::VPDPBUUDSZ128rk, X86::VPDPBUUDSZ128mk, 0}, - {X86::VPDPBUUDSZ128rkz, X86::VPDPBUUDSZ128mkz, 0}, - {X86::VPDPBUUDSZ256rk, X86::VPDPBUUDSZ256mk, 0}, - {X86::VPDPBUUDSZ256rkz, X86::VPDPBUUDSZ256mkz, 0}, - {X86::VPDPBUUDSZrk, X86::VPDPBUUDSZmk, 0}, - {X86::VPDPBUUDSZrkz, X86::VPDPBUUDSZmkz, 0}, - {X86::VPDPBUUDZ128rk, X86::VPDPBUUDZ128mk, 0}, - {X86::VPDPBUUDZ128rkz, X86::VPDPBUUDZ128mkz, 0}, - {X86::VPDPBUUDZ256rk, X86::VPDPBUUDZ256mk, 0}, - {X86::VPDPBUUDZ256rkz, X86::VPDPBUUDZ256mkz, 0}, - {X86::VPDPBUUDZrk, X86::VPDPBUUDZmk, 0}, - {X86::VPDPBUUDZrkz, X86::VPDPBUUDZmkz, 0}, - {X86::VPDPWSSDSZ128rk, X86::VPDPWSSDSZ128mk, 0}, - {X86::VPDPWSSDSZ128rkz, X86::VPDPWSSDSZ128mkz, 0}, - {X86::VPDPWSSDSZ256rk, X86::VPDPWSSDSZ256mk, 0}, - {X86::VPDPWSSDSZ256rkz, X86::VPDPWSSDSZ256mkz, 0}, - {X86::VPDPWSSDSZrk, X86::VPDPWSSDSZmk, 0}, - {X86::VPDPWSSDSZrkz, X86::VPDPWSSDSZmkz, 0}, - {X86::VPDPWSSDZ128rk, X86::VPDPWSSDZ128mk, 0}, - {X86::VPDPWSSDZ128rkz, X86::VPDPWSSDZ128mkz, 0}, - {X86::VPDPWSSDZ256rk, X86::VPDPWSSDZ256mk, 0}, - {X86::VPDPWSSDZ256rkz, X86::VPDPWSSDZ256mkz, 0}, - {X86::VPDPWSSDZrk, X86::VPDPWSSDZmk, 0}, - {X86::VPDPWSSDZrkz, X86::VPDPWSSDZmkz, 0}, - {X86::VPDPWSUDSZ128rk, X86::VPDPWSUDSZ128mk, 0}, - {X86::VPDPWSUDSZ128rkz, X86::VPDPWSUDSZ128mkz, 0}, - {X86::VPDPWSUDSZ256rk, X86::VPDPWSUDSZ256mk, 0}, - {X86::VPDPWSUDSZ256rkz, X86::VPDPWSUDSZ256mkz, 0}, - {X86::VPDPWSUDSZrk, X86::VPDPWSUDSZmk, 0}, - {X86::VPDPWSUDSZrkz, X86::VPDPWSUDSZmkz, 0}, - {X86::VPDPWSUDZ128rk, X86::VPDPWSUDZ128mk, 0}, - {X86::VPDPWSUDZ128rkz, X86::VPDPWSUDZ128mkz, 0}, - {X86::VPDPWSUDZ256rk, X86::VPDPWSUDZ256mk, 0}, - {X86::VPDPWSUDZ256rkz, X86::VPDPWSUDZ256mkz, 0}, - {X86::VPDPWSUDZrk, X86::VPDPWSUDZmk, 0}, - {X86::VPDPWSUDZrkz, X86::VPDPWSUDZmkz, 0}, - {X86::VPDPWUSDSZ128rk, X86::VPDPWUSDSZ128mk, 0}, - {X86::VPDPWUSDSZ128rkz, X86::VPDPWUSDSZ128mkz, 0}, - {X86::VPDPWUSDSZ256rk, X86::VPDPWUSDSZ256mk, 0}, - {X86::VPDPWUSDSZ256rkz, X86::VPDPWUSDSZ256mkz, 0}, - {X86::VPDPWUSDSZrk, X86::VPDPWUSDSZmk, 0}, - {X86::VPDPWUSDSZrkz, X86::VPDPWUSDSZmkz, 0}, - {X86::VPDPWUSDZ128rk, X86::VPDPWUSDZ128mk, 0}, - {X86::VPDPWUSDZ128rkz, X86::VPDPWUSDZ128mkz, 0}, - {X86::VPDPWUSDZ256rk, X86::VPDPWUSDZ256mk, 0}, - {X86::VPDPWUSDZ256rkz, X86::VPDPWUSDZ256mkz, 0}, - {X86::VPDPWUSDZrk, X86::VPDPWUSDZmk, 0}, - {X86::VPDPWUSDZrkz, X86::VPDPWUSDZmkz, 0}, - {X86::VPDPWUUDSZ128rk, X86::VPDPWUUDSZ128mk, 0}, - {X86::VPDPWUUDSZ128rkz, X86::VPDPWUUDSZ128mkz, 0}, - {X86::VPDPWUUDSZ256rk, X86::VPDPWUUDSZ256mk, 0}, - {X86::VPDPWUUDSZ256rkz, X86::VPDPWUUDSZ256mkz, 0}, - {X86::VPDPWUUDSZrk, X86::VPDPWUUDSZmk, 0}, - {X86::VPDPWUUDSZrkz, X86::VPDPWUUDSZmkz, 0}, - {X86::VPDPWUUDZ128rk, X86::VPDPWUUDZ128mk, 0}, - {X86::VPDPWUUDZ128rkz, X86::VPDPWUUDZ128mkz, 0}, - {X86::VPDPWUUDZ256rk, X86::VPDPWUUDZ256mk, 0}, - {X86::VPDPWUUDZ256rkz, X86::VPDPWUUDZ256mkz, 0}, - {X86::VPDPWUUDZrk, X86::VPDPWUUDZmk, 0}, - {X86::VPDPWUUDZrkz, X86::VPDPWUUDZmkz, 0}, + {X86::VPDPBSSDSZ128rrk, X86::VPDPBSSDSZ128rmk, 0}, + {X86::VPDPBSSDSZ128rrkz, X86::VPDPBSSDSZ128rmkz, 0}, + {X86::VPDPBSSDSZ256rrk, X86::VPDPBSSDSZ256rmk, 0}, + {X86::VPDPBSSDSZ256rrkz, X86::VPDPBSSDSZ256rmkz, 0}, + {X86::VPDPBSSDSZrrk, X86::VPDPBSSDSZrmk, 0}, + {X86::VPDPBSSDSZrrkz, X86::VPDPBSSDSZrmkz, 0}, + {X86::VPDPBSSDZ128rrk, X86::VPDPBSSDZ128rmk, 0}, + {X86::VPDPBSSDZ128rrkz, X86::VPDPBSSDZ128rmkz, 0}, + {X86::VPDPBSSDZ256rrk, X86::VPDPBSSDZ256rmk, 0}, + {X86::VPDPBSSDZ256rrkz, X86::VPDPBSSDZ256rmkz, 0}, + {X86::VPDPBSSDZrrk, X86::VPDPBSSDZrmk, 0}, + {X86::VPDPBSSDZrrkz, X86::VPDPBSSDZrmkz, 0}, + {X86::VPDPBSUDSZ128rrk, X86::VPDPBSUDSZ128rmk, 0}, + {X86::VPDPBSUDSZ128rrkz, X86::VPDPBSUDSZ128rmkz, 0}, + {X86::VPDPBSUDSZ256rrk, X86::VPDPBSUDSZ256rmk, 0}, + {X86::VPDPBSUDSZ256rrkz, X86::VPDPBSUDSZ256rmkz, 0}, + {X86::VPDPBSUDSZrrk, X86::VPDPBSUDSZrmk, 0}, + {X86::VPDPBSUDSZrrkz, X86::VPDPBSUDSZrmkz, 0}, + {X86::VPDPBSUDZ128rrk, X86::VPDPBSUDZ128rmk, 0}, + {X86::VPDPBSUDZ128rrkz, X86::VPDPBSUDZ128rmkz, 0}, + {X86::VPDPBSUDZ256rrk, X86::VPDPBSUDZ256rmk, 0}, + {X86::VPDPBSUDZ256rrkz, X86::VPDPBSUDZ256rmkz, 0}, + {X86::VPDPBSUDZrrk, X86::VPDPBSUDZrmk, 0}, + {X86::VPDPBSUDZrrkz, X86::VPDPBSUDZrmkz, 0}, + {X86::VPDPBUSDSZ128rrk, X86::VPDPBUSDSZ128rmk, 0}, + {X86::VPDPBUSDSZ128rrkz, X86::VPDPBUSDSZ128rmkz, 0}, + {X86::VPDPBUSDSZ256rrk, X86::VPDPBUSDSZ256rmk, 0}, + {X86::VPDPBUSDSZ256rrkz, X86::VPDPBUSDSZ256rmkz, 0}, + {X86::VPDPBUSDSZrrk, X86::VPDPBUSDSZrmk, 0}, + {X86::VPDPBUSDSZrrkz, X86::VPDPBUSDSZrmkz, 0}, + {X86::VPDPBUSDZ128rrk, X86::VPDPBUSDZ128rmk, 0}, + {X86::VPDPBUSDZ128rrkz, X86::VPDPBUSDZ128rmkz, 0}, + {X86::VPDPBUSDZ256rrk, X86::VPDPBUSDZ256rmk, 0}, + {X86::VPDPBUSDZ256rrkz, X86::VPDPBUSDZ256rmkz, 0}, + {X86::VPDPBUSDZrrk, X86::VPDPBUSDZrmk, 0}, + {X86::VPDPBUSDZrrkz, X86::VPDPBUSDZrmkz, 0}, + {X86::VPDPBUUDSZ128rrk, X86::VPDPBUUDSZ128rmk, 0}, + {X86::VPDPBUUDSZ128rrkz, X86::VPDPBUUDSZ128rmkz, 0}, + {X86::VPDPBUUDSZ256rrk, X86::VPDPBUUDSZ256rmk, 0}, + {X86::VPDPBUUDSZ256rrkz, X86::VPDPBUUDSZ256rmkz, 0}, + {X86::VPDPBUUDSZrrk, X86::VPDPBUUDSZrmk, 0}, + {X86::VPDPBUUDSZrrkz, X86::VPDPBUUDSZrmkz, 0}, + {X86::VPDPBUUDZ128rrk, X86::VPDPBUUDZ128rmk, 0}, + {X86::VPDPBUUDZ128rrkz, X86::VPDPBUUDZ128rmkz, 0}, + {X86::VPDPBUUDZ256rrk, X86::VPDPBUUDZ256rmk, 0}, + {X86::VPDPBUUDZ256rrkz, X86::VPDPBUUDZ256rmkz, 0}, + {X86::VPDPBUUDZrrk, X86::VPDPBUUDZrmk, 0}, + {X86::VPDPBUUDZrrkz, X86::VPDPBUUDZrmkz, 0}, + {X86::VPDPWSSDSZ128rrk, X86::VPDPWSSDSZ128rmk, 0}, + {X86::VPDPWSSDSZ128rrkz, X86::VPDPWSSDSZ128rmkz, 0}, + {X86::VPDPWSSDSZ256rrk, X86::VPDPWSSDSZ256rmk, 0}, + {X86::VPDPWSSDSZ256rrkz, X86::VPDPWSSDSZ256rmkz, 0}, + {X86::VPDPWSSDSZrrk, X86::VPDPWSSDSZrmk, 0}, + {X86::VPDPWSSDSZrrkz, X86::VPDPWSSDSZrmkz, 0}, + {X86::VPDPWSSDZ128rrk, X86::VPDPWSSDZ128rmk, 0}, + {X86::VPDPWSSDZ128rrkz, X86::VPDPWSSDZ128rmkz, 0}, + {X86::VPDPWSSDZ256rrk, X86::VPDPWSSDZ256rmk, 0}, + {X86::VPDPWSSDZ256rrkz, X86::VPDPWSSDZ256rmkz, 0}, + {X86::VPDPWSSDZrrk, X86::VPDPWSSDZrmk, 0}, + {X86::VPDPWSSDZrrkz, X86::VPDPWSSDZrmkz, 0}, + {X86::VPDPWSUDSZ128rrk, X86::VPDPWSUDSZ128rmk, 0}, + {X86::VPDPWSUDSZ128rrkz, X86::VPDPWSUDSZ128rmkz, 0}, + {X86::VPDPWSUDSZ256rrk, X86::VPDPWSUDSZ256rmk, 0}, + {X86::VPDPWSUDSZ256rrkz, X86::VPDPWSUDSZ256rmkz, 0}, + {X86::VPDPWSUDSZrrk, X86::VPDPWSUDSZrmk, 0}, + {X86::VPDPWSUDSZrrkz, X86::VPDPWSUDSZrmkz, 0}, + {X86::VPDPWSUDZ128rrk, X86::VPDPWSUDZ128rmk, 0}, + {X86::VPDPWSUDZ128rrkz, X86::VPDPWSUDZ128rmkz, 0}, + {X86::VPDPWSUDZ256rrk, X86::VPDPWSUDZ256rmk, 0}, + {X86::VPDPWSUDZ256rrkz, X86::VPDPWSUDZ256rmkz, 0}, + {X86::VPDPWSUDZrrk, X86::VPDPWSUDZrmk, 0}, + {X86::VPDPWSUDZrrkz, X86::VPDPWSUDZrmkz, 0}, + {X86::VPDPWUSDSZ128rrk, X86::VPDPWUSDSZ128rmk, 0}, + {X86::VPDPWUSDSZ128rrkz, X86::VPDPWUSDSZ128rmkz, 0}, + {X86::VPDPWUSDSZ256rrk, X86::VPDPWUSDSZ256rmk, 0}, + {X86::VPDPWUSDSZ256rrkz, X86::VPDPWUSDSZ256rmkz, 0}, + {X86::VPDPWUSDSZrrk, X86::VPDPWUSDSZrmk, 0}, + {X86::VPDPWUSDSZrrkz, X86::VPDPWUSDSZrmkz, 0}, + {X86::VPDPWUSDZ128rrk, X86::VPDPWUSDZ128rmk, 0}, + {X86::VPDPWUSDZ128rrkz, X86::VPDPWUSDZ128rmkz, 0}, + {X86::VPDPWUSDZ256rrk, X86::VPDPWUSDZ256rmk, 0}, + {X86::VPDPWUSDZ256rrkz, X86::VPDPWUSDZ256rmkz, 0}, + {X86::VPDPWUSDZrrk, X86::VPDPWUSDZrmk, 0}, + {X86::VPDPWUSDZrrkz, X86::VPDPWUSDZrmkz, 0}, + {X86::VPDPWUUDSZ128rrk, X86::VPDPWUUDSZ128rmk, 0}, + {X86::VPDPWUUDSZ128rrkz, X86::VPDPWUUDSZ128rmkz, 0}, + {X86::VPDPWUUDSZ256rrk, X86::VPDPWUUDSZ256rmk, 0}, + {X86::VPDPWUUDSZ256rrkz, X86::VPDPWUUDSZ256rmkz, 0}, + {X86::VPDPWUUDSZrrk, X86::VPDPWUUDSZrmk, 0}, + {X86::VPDPWUUDSZrrkz, X86::VPDPWUUDSZrmkz, 0}, + {X86::VPDPWUUDZ128rrk, X86::VPDPWUUDZ128rmk, 0}, + {X86::VPDPWUUDZ128rrkz, X86::VPDPWUUDZ128rmkz, 0}, + {X86::VPDPWUUDZ256rrk, X86::VPDPWUUDZ256rmk, 0}, + {X86::VPDPWUUDZ256rrkz, X86::VPDPWUUDZ256rmkz, 0}, + {X86::VPDPWUUDZrrk, X86::VPDPWUUDZrmk, 0}, + {X86::VPDPWUUDZrrkz, X86::VPDPWUUDZrmkz, 0}, {X86::VPERMBZ128rrk, X86::VPERMBZ128rmk, 0}, {X86::VPERMBZ256rrk, X86::VPERMBZ256rmk, 0}, {X86::VPERMBZrrk, X86::VPERMBZrmk, 0}, @@ -9339,54 +9339,54 @@ static const X86FoldTableEntry BroadcastTable3[] = { {X86::VPCONFLICTQZ128rrk, X86::VPCONFLICTQZ128rmbk, TB_BCAST_Q}, {X86::VPCONFLICTQZ256rrk, X86::VPCONFLICTQZ256rmbk, TB_BCAST_Q}, {X86::VPCONFLICTQZrrk, X86::VPCONFLICTQZrmbk, TB_BCAST_Q}, - {X86::VPDPBSSDSZ128r, X86::VPDPBSSDSZ128mb, TB_BCAST_D}, - {X86::VPDPBSSDSZ256r, X86::VPDPBSSDSZ256mb, TB_BCAST_D}, - {X86::VPDPBSSDSZr, X86::VPDPBSSDSZmb, TB_BCAST_D}, - {X86::VPDPBSSDZ128r, X86::VPDPBSSDZ128mb, TB_BCAST_D}, - {X86::VPDPBSSDZ256r, X86::VPDPBSSDZ256mb, TB_BCAST_D}, - {X86::VPDPBSSDZr, X86::VPDPBSSDZmb, TB_BCAST_D}, - {X86::VPDPBSUDSZ128r, X86::VPDPBSUDSZ128mb, TB_BCAST_D}, - {X86::VPDPBSUDSZ256r, X86::VPDPBSUDSZ256mb, TB_BCAST_D}, - {X86::VPDPBSUDSZr, X86::VPDPBSUDSZmb, TB_BCAST_D}, - {X86::VPDPBSUDZ128r, X86::VPDPBSUDZ128mb, TB_BCAST_D}, - {X86::VPDPBSUDZ256r, X86::VPDPBSUDZ256mb, TB_BCAST_D}, - {X86::VPDPBSUDZr, X86::VPDPBSUDZmb, TB_BCAST_D}, - {X86::VPDPBUSDSZ128r, X86::VPDPBUSDSZ128mb, TB_BCAST_D}, - {X86::VPDPBUSDSZ256r, X86::VPDPBUSDSZ256mb, TB_BCAST_D}, - {X86::VPDPBUSDSZr, X86::VPDPBUSDSZmb, TB_BCAST_D}, - {X86::VPDPBUSDZ128r, X86::VPDPBUSDZ128mb, TB_BCAST_D}, - {X86::VPDPBUSDZ256r, X86::VPDPBUSDZ256mb, TB_BCAST_D}, - {X86::VPDPBUSDZr, X86::VPDPBUSDZmb, TB_BCAST_D}, - {X86::VPDPBUUDSZ128r, X86::VPDPBUUDSZ128mb, TB_BCAST_D}, - {X86::VPDPBUUDSZ256r, X86::VPDPBUUDSZ256mb, TB_BCAST_D}, - {X86::VPDPBUUDSZr, X86::VPDPBUUDSZmb, TB_BCAST_D}, - {X86::VPDPBUUDZ128r, X86::VPDPBUUDZ128mb, TB_BCAST_D}, - {X86::VPDPBUUDZ256r, X86::VPDPBUUDZ256mb, TB_BCAST_D}, - {X86::VPDPBUUDZr, X86::VPDPBUUDZmb, TB_BCAST_D}, - {X86::VPDPWSSDSZ128r, X86::VPDPWSSDSZ128mb, TB_BCAST_D}, - {X86::VPDPWSSDSZ256r, X86::VPDPWSSDSZ256mb, TB_BCAST_D}, - {X86::VPDPWSSDSZr, X86::VPDPWSSDSZmb, TB_BCAST_D}, - {X86::VPDPWSSDZ128r, X86::VPDPWSSDZ128mb, TB_BCAST_D}, - {X86::VPDPWSSDZ256r, X86::VPDPWSSDZ256mb, TB_BCAST_D}, - {X86::VPDPWSSDZr, X86::VPDPWSSDZmb, TB_BCAST_D}, - {X86::VPDPWSUDSZ128r, X86::VPDPWSUDSZ128mb, TB_BCAST_D}, - {X86::VPDPWSUDSZ256r, X86::VPDPWSUDSZ256mb, TB_BCAST_D}, - {X86::VPDPWSUDSZr, X86::VPDPWSUDSZmb, TB_BCAST_D}, - {X86::VPDPWSUDZ128r, X86::VPDPWSUDZ128mb, TB_BCAST_D}, - {X86::VPDPWSUDZ256r, X86::VPDPWSUDZ256mb, TB_BCAST_D}, - {X86::VPDPWSUDZr, X86::VPDPWSUDZmb, TB_BCAST_D}, - {X86::VPDPWUSDSZ128r, X86::VPDPWUSDSZ128mb, TB_BCAST_D}, - {X86::VPDPWUSDSZ256r, X86::VPDPWUSDSZ256mb, TB_BCAST_D}, - {X86::VPDPWUSDSZr, X86::VPDPWUSDSZmb, TB_BCAST_D}, - {X86::VPDPWUSDZ128r, X86::VPDPWUSDZ128mb, TB_BCAST_D}, - {X86::VPDPWUSDZ256r, X86::VPDPWUSDZ256mb, TB_BCAST_D}, - {X86::VPDPWUSDZr, X86::VPDPWUSDZmb, TB_BCAST_D}, - {X86::VPDPWUUDSZ128r, X86::VPDPWUUDSZ128mb, TB_BCAST_D}, - {X86::VPDPWUUDSZ256r, X86::VPDPWUUDSZ256mb, TB_BCAST_D}, - {X86::VPDPWUUDSZr, X86::VPDPWUUDSZmb, TB_BCAST_D}, - {X86::VPDPWUUDZ128r, X86::VPDPWUUDZ128mb, TB_BCAST_D}, - {X86::VPDPWUUDZ256r, X86::VPDPWUUDZ256mb, TB_BCAST_D}, - {X86::VPDPWUUDZr, X86::VPDPWUUDZmb, TB_BCAST_D}, + {X86::VPDPBSSDSZ128rr, X86::VPDPBSSDSZ128rmb, TB_BCAST_D}, + {X86::VPDPBSSDSZ256rr, X86::VPDPBSSDSZ256rmb, TB_BCAST_D}, + {X86::VPDPBSSDSZrr, X86::VPDPBSSDSZrmb, TB_BCAST_D}, + {X86::VPDPBSSDZ128rr, X86::VPDPBSSDZ128rmb, TB_BCAST_D}, + {X86::VPDPBSSDZ256rr, X86::VPDPBSSDZ256rmb, TB_BCAST_D}, + {X86::VPDPBSSDZrr, X86::VPDPBSSDZrmb, TB_BCAST_D}, + {X86::VPDPBSUDSZ128rr, X86::VPDPBSUDSZ128rmb, TB_BCAST_D}, + {X86::VPDPBSUDSZ256rr, X86::VPDPBSUDSZ256rmb, TB_BCAST_D}, + {X86::VPDPBSUDSZrr, X86::VPDPBSUDSZrmb, TB_BCAST_D}, + {X86::VPDPBSUDZ128rr, X86::VPDPBSUDZ128rmb, TB_BCAST_D}, + {X86::VPDPBSUDZ256rr, X86::VPDPBSUDZ256rmb, TB_BCAST_D}, + {X86::VPDPBSUDZrr, X86::VPDPBSUDZrmb, TB_BCAST_D}, + {X86::VPDPBUSDSZ128rr, X86::VPDPBUSDSZ128rmb, TB_BCAST_D}, + {X86::VPDPBUSDSZ256rr, X86::VPDPBUSDSZ256rmb, TB_BCAST_D}, + {X86::VPDPBUSDSZrr, X86::VPDPBUSDSZrmb, TB_BCAST_D}, + {X86::VPDPBUSDZ128rr, X86::VPDPBUSDZ128rmb, TB_BCAST_D}, + {X86::VPDPBUSDZ256rr, X86::VPDPBUSDZ256rmb, TB_BCAST_D}, + {X86::VPDPBUSDZrr, X86::VPDPBUSDZrmb, TB_BCAST_D}, + {X86::VPDPBUUDSZ128rr, X86::VPDPBUUDSZ128rmb, TB_BCAST_D}, + {X86::VPDPBUUDSZ256rr, X86::VPDPBUUDSZ256rmb, TB_BCAST_D}, + {X86::VPDPBUUDSZrr, X86::VPDPBUUDSZrmb, TB_BCAST_D}, + {X86::VPDPBUUDZ128rr, X86::VPDPBUUDZ128rmb, TB_BCAST_D}, + {X86::VPDPBUUDZ256rr, X86::VPDPBUUDZ256rmb, TB_BCAST_D}, + {X86::VPDPBUUDZrr, X86::VPDPBUUDZrmb, TB_BCAST_D}, + {X86::VPDPWSSDSZ128rr, X86::VPDPWSSDSZ128rmb, TB_BCAST_D}, + {X86::VPDPWSSDSZ256rr, X86::VPDPWSSDSZ256rmb, TB_BCAST_D}, + {X86::VPDPWSSDSZrr, X86::VPDPWSSDSZrmb, TB_BCAST_D}, + {X86::VPDPWSSDZ128rr, X86::VPDPWSSDZ128rmb, TB_BCAST_D}, + {X86::VPDPWSSDZ256rr, X86::VPDPWSSDZ256rmb, TB_BCAST_D}, + {X86::VPDPWSSDZrr, X86::VPDPWSSDZrmb, TB_BCAST_D}, + {X86::VPDPWSUDSZ128rr, X86::VPDPWSUDSZ128rmb, TB_BCAST_D}, + {X86::VPDPWSUDSZ256rr, X86::VPDPWSUDSZ256rmb, TB_BCAST_D}, + {X86::VPDPWSUDSZrr, X86::VPDPWSUDSZrmb, TB_BCAST_D}, + {X86::VPDPWSUDZ128rr, X86::VPDPWSUDZ128rmb, TB_BCAST_D}, + {X86::VPDPWSUDZ256rr, X86::VPDPWSUDZ256rmb, TB_BCAST_D}, + {X86::VPDPWSUDZrr, X86::VPDPWSUDZrmb, TB_BCAST_D}, + {X86::VPDPWUSDSZ128rr, X86::VPDPWUSDSZ128rmb, TB_BCAST_D}, + {X86::VPDPWUSDSZ256rr, X86::VPDPWUSDSZ256rmb, TB_BCAST_D}, + {X86::VPDPWUSDSZrr, X86::VPDPWUSDSZrmb, TB_BCAST_D}, + {X86::VPDPWUSDZ128rr, X86::VPDPWUSDZ128rmb, TB_BCAST_D}, + {X86::VPDPWUSDZ256rr, X86::VPDPWUSDZ256rmb, TB_BCAST_D}, + {X86::VPDPWUSDZrr, X86::VPDPWUSDZrmb, TB_BCAST_D}, + {X86::VPDPWUUDSZ128rr, X86::VPDPWUUDSZ128rmb, TB_BCAST_D}, + {X86::VPDPWUUDSZ256rr, X86::VPDPWUUDSZ256rmb, TB_BCAST_D}, + {X86::VPDPWUUDSZrr, X86::VPDPWUUDSZrmb, TB_BCAST_D}, + {X86::VPDPWUUDZ128rr, X86::VPDPWUUDZ128rmb, TB_BCAST_D}, + {X86::VPDPWUUDZ256rr, X86::VPDPWUUDZ256rmb, TB_BCAST_D}, + {X86::VPDPWUUDZrr, X86::VPDPWUUDZrmb, TB_BCAST_D}, {X86::VPERMDZ256rrkz, X86::VPERMDZ256rmbkz, TB_BCAST_D}, {X86::VPERMDZrrkz, X86::VPERMDZrmbkz, TB_BCAST_D}, {X86::VPERMI2DZ128rr, X86::VPERMI2DZ128rmb, TB_BCAST_D}, @@ -10368,102 +10368,102 @@ static const X86FoldTableEntry BroadcastTable4[] = { {X86::VPANDQZ128rrk, X86::VPANDQZ128rmbk, TB_BCAST_Q}, {X86::VPANDQZ256rrk, X86::VPANDQZ256rmbk, TB_BCAST_Q}, {X86::VPANDQZrrk, X86::VPANDQZrmbk, TB_BCAST_Q}, - {X86::VPDPBSSDSZ128rk, X86::VPDPBSSDSZ128mbk, TB_BCAST_D}, - {X86::VPDPBSSDSZ128rkz, X86::VPDPBSSDSZ128mbkz, TB_BCAST_D}, - {X86::VPDPBSSDSZ256rk, X86::VPDPBSSDSZ256mbk, TB_BCAST_D}, - {X86::VPDPBSSDSZ256rkz, X86::VPDPBSSDSZ256mbkz, TB_BCAST_D}, - {X86::VPDPBSSDSZrk, X86::VPDPBSSDSZmbk, TB_BCAST_D}, - {X86::VPDPBSSDSZrkz, X86::VPDPBSSDSZmbkz, TB_BCAST_D}, - {X86::VPDPBSSDZ128rk, X86::VPDPBSSDZ128mbk, TB_BCAST_D}, - {X86::VPDPBSSDZ128rkz, X86::VPDPBSSDZ128mbkz, TB_BCAST_D}, - {X86::VPDPBSSDZ256rk, X86::VPDPBSSDZ256mbk, TB_BCAST_D}, - {X86::VPDPBSSDZ256rkz, X86::VPDPBSSDZ256mbkz, TB_BCAST_D}, - {X86::VPDPBSSDZrk, X86::VPDPBSSDZmbk, TB_BCAST_D}, - {X86::VPDPBSSDZrkz, X86::VPDPBSSDZmbkz, TB_BCAST_D}, - {X86::VPDPBSUDSZ128rk, X86::VPDPBSUDSZ128mbk, TB_BCAST_D}, - {X86::VPDPBSUDSZ128rkz, X86::VPDPBSUDSZ128mbkz, TB_BCAST_D}, - {X86::VPDPBSUDSZ256rk, X86::VPDPBSUDSZ256mbk, TB_BCAST_D}, - {X86::VPDPBSUDSZ256rkz, X86::VPDPBSUDSZ256mbkz, TB_BCAST_D}, - {X86::VPDPBSUDSZrk, X86::VPDPBSUDSZmbk, TB_BCAST_D}, - {X86::VPDPBSUDSZrkz, X86::VPDPBSUDSZmbkz, TB_BCAST_D}, - {X86::VPDPBSUDZ128rk, X86::VPDPBSUDZ128mbk, TB_BCAST_D}, - {X86::VPDPBSUDZ128rkz, X86::VPDPBSUDZ128mbkz, TB_BCAST_D}, - {X86::VPDPBSUDZ256rk, X86::VPDPBSUDZ256mbk, TB_BCAST_D}, - {X86::VPDPBSUDZ256rkz, X86::VPDPBSUDZ256mbkz, TB_BCAST_D}, - {X86::VPDPBSUDZrk, X86::VPDPBSUDZmbk, TB_BCAST_D}, - {X86::VPDPBSUDZrkz, X86::VPDPBSUDZmbkz, TB_BCAST_D}, - {X86::VPDPBUSDSZ128rk, X86::VPDPBUSDSZ128mbk, TB_BCAST_D}, - {X86::VPDPBUSDSZ128rkz, X86::VPDPBUSDSZ128mbkz, TB_BCAST_D}, - {X86::VPDPBUSDSZ256rk, X86::VPDPBUSDSZ256mbk, TB_BCAST_D}, - {X86::VPDPBUSDSZ256rkz, X86::VPDPBUSDSZ256mbkz, TB_BCAST_D}, - {X86::VPDPBUSDSZrk, X86::VPDPBUSDSZmbk, TB_BCAST_D}, - {X86::VPDPBUSDSZrkz, X86::VPDPBUSDSZmbkz, TB_BCAST_D}, - {X86::VPDPBUSDZ128rk, X86::VPDPBUSDZ128mbk, TB_BCAST_D}, - {X86::VPDPBUSDZ128rkz, X86::VPDPBUSDZ128mbkz, TB_BCAST_D}, - {X86::VPDPBUSDZ256rk, X86::VPDPBUSDZ256mbk, TB_BCAST_D}, - {X86::VPDPBUSDZ256rkz, X86::VPDPBUSDZ256mbkz, TB_BCAST_D}, - {X86::VPDPBUSDZrk, X86::VPDPBUSDZmbk, TB_BCAST_D}, - {X86::VPDPBUSDZrkz, X86::VPDPBUSDZmbkz, TB_BCAST_D}, - {X86::VPDPBUUDSZ128rk, X86::VPDPBUUDSZ128mbk, TB_BCAST_D}, - {X86::VPDPBUUDSZ128rkz, X86::VPDPBUUDSZ128mbkz, TB_BCAST_D}, - {X86::VPDPBUUDSZ256rk, X86::VPDPBUUDSZ256mbk, TB_BCAST_D}, - {X86::VPDPBUUDSZ256rkz, X86::VPDPBUUDSZ256mbkz, TB_BCAST_D}, - {X86::VPDPBUUDSZrk, X86::VPDPBUUDSZmbk, TB_BCAST_D}, - {X86::VPDPBUUDSZrkz, X86::VPDPBUUDSZmbkz, TB_BCAST_D}, - {X86::VPDPBUUDZ128rk, X86::VPDPBUUDZ128mbk, TB_BCAST_D}, - {X86::VPDPBUUDZ128rkz, X86::VPDPBUUDZ128mbkz, TB_BCAST_D}, - {X86::VPDPBUUDZ256rk, X86::VPDPBUUDZ256mbk, TB_BCAST_D}, - {X86::VPDPBUUDZ256rkz, X86::VPDPBUUDZ256mbkz, TB_BCAST_D}, - {X86::VPDPBUUDZrk, X86::VPDPBUUDZmbk, TB_BCAST_D}, - {X86::VPDPBUUDZrkz, X86::VPDPBUUDZmbkz, TB_BCAST_D}, - {X86::VPDPWSSDSZ128rk, X86::VPDPWSSDSZ128mbk, TB_BCAST_D}, - {X86::VPDPWSSDSZ128rkz, X86::VPDPWSSDSZ128mbkz, TB_BCAST_D}, - {X86::VPDPWSSDSZ256rk, X86::VPDPWSSDSZ256mbk, TB_BCAST_D}, - {X86::VPDPWSSDSZ256rkz, X86::VPDPWSSDSZ256mbkz, TB_BCAST_D}, - {X86::VPDPWSSDSZrk, X86::VPDPWSSDSZmbk, TB_BCAST_D}, - {X86::VPDPWSSDSZrkz, X86::VPDPWSSDSZmbkz, TB_BCAST_D}, - {X86::VPDPWSSDZ128rk, X86::VPDPWSSDZ128mbk, TB_BCAST_D}, - {X86::VPDPWSSDZ128rkz, X86::VPDPWSSDZ128mbkz, TB_BCAST_D}, - {X86::VPDPWSSDZ256rk, X86::VPDPWSSDZ256mbk, TB_BCAST_D}, - {X86::VPDPWSSDZ256rkz, X86::VPDPWSSDZ256mbkz, TB_BCAST_D}, - {X86::VPDPWSSDZrk, X86::VPDPWSSDZmbk, TB_BCAST_D}, - {X86::VPDPWSSDZrkz, X86::VPDPWSSDZmbkz, TB_BCAST_D}, - {X86::VPDPWSUDSZ128rk, X86::VPDPWSUDSZ128mbk, TB_BCAST_D}, - {X86::VPDPWSUDSZ128rkz, X86::VPDPWSUDSZ128mbkz, TB_BCAST_D}, - {X86::VPDPWSUDSZ256rk, X86::VPDPWSUDSZ256mbk, TB_BCAST_D}, - {X86::VPDPWSUDSZ256rkz, X86::VPDPWSUDSZ256mbkz, TB_BCAST_D}, - {X86::VPDPWSUDSZrk, X86::VPDPWSUDSZmbk, TB_BCAST_D}, - {X86::VPDPWSUDSZrkz, X86::VPDPWSUDSZmbkz, TB_BCAST_D}, - {X86::VPDPWSUDZ128rk, X86::VPDPWSUDZ128mbk, TB_BCAST_D}, - {X86::VPDPWSUDZ128rkz, X86::VPDPWSUDZ128mbkz, TB_BCAST_D}, - {X86::VPDPWSUDZ256rk, X86::VPDPWSUDZ256mbk, TB_BCAST_D}, - {X86::VPDPWSUDZ256rkz, X86::VPDPWSUDZ256mbkz, TB_BCAST_D}, - {X86::VPDPWSUDZrk, X86::VPDPWSUDZmbk, TB_BCAST_D}, - {X86::VPDPWSUDZrkz, X86::VPDPWSUDZmbkz, TB_BCAST_D}, - {X86::VPDPWUSDSZ128rk, X86::VPDPWUSDSZ128mbk, TB_BCAST_D}, - {X86::VPDPWUSDSZ128rkz, X86::VPDPWUSDSZ128mbkz, TB_BCAST_D}, - {X86::VPDPWUSDSZ256rk, X86::VPDPWUSDSZ256mbk, TB_BCAST_D}, - {X86::VPDPWUSDSZ256rkz, X86::VPDPWUSDSZ256mbkz, TB_BCAST_D}, - {X86::VPDPWUSDSZrk, X86::VPDPWUSDSZmbk, TB_BCAST_D}, - {X86::VPDPWUSDSZrkz, X86::VPDPWUSDSZmbkz, TB_BCAST_D}, - {X86::VPDPWUSDZ128rk, X86::VPDPWUSDZ128mbk, TB_BCAST_D}, - {X86::VPDPWUSDZ128rkz, X86::VPDPWUSDZ128mbkz, TB_BCAST_D}, - {X86::VPDPWUSDZ256rk, X86::VPDPWUSDZ256mbk, TB_BCAST_D}, - {X86::VPDPWUSDZ256rkz, X86::VPDPWUSDZ256mbkz, TB_BCAST_D}, - {X86::VPDPWUSDZrk, X86::VPDPWUSDZmbk, TB_BCAST_D}, - {X86::VPDPWUSDZrkz, X86::VPDPWUSDZmbkz, TB_BCAST_D}, - {X86::VPDPWUUDSZ128rk, X86::VPDPWUUDSZ128mbk, TB_BCAST_D}, - {X86::VPDPWUUDSZ128rkz, X86::VPDPWUUDSZ128mbkz, TB_BCAST_D}, - {X86::VPDPWUUDSZ256rk, X86::VPDPWUUDSZ256mbk, TB_BCAST_D}, - {X86::VPDPWUUDSZ256rkz, X86::VPDPWUUDSZ256mbkz, TB_BCAST_D}, - {X86::VPDPWUUDSZrk, X86::VPDPWUUDSZmbk, TB_BCAST_D}, - {X86::VPDPWUUDSZrkz, X86::VPDPWUUDSZmbkz, TB_BCAST_D}, - {X86::VPDPWUUDZ128rk, X86::VPDPWUUDZ128mbk, TB_BCAST_D}, - {X86::VPDPWUUDZ128rkz, X86::VPDPWUUDZ128mbkz, TB_BCAST_D}, - {X86::VPDPWUUDZ256rk, X86::VPDPWUUDZ256mbk, TB_BCAST_D}, - {X86::VPDPWUUDZ256rkz, X86::VPDPWUUDZ256mbkz, TB_BCAST_D}, - {X86::VPDPWUUDZrk, X86::VPDPWUUDZmbk, TB_BCAST_D}, - {X86::VPDPWUUDZrkz, X86::VPDPWUUDZmbkz, TB_BCAST_D}, + {X86::VPDPBSSDSZ128rrk, X86::VPDPBSSDSZ128rmbk, TB_BCAST_D}, + {X86::VPDPBSSDSZ128rrkz, X86::VPDPBSSDSZ128rmbkz, TB_BCAST_D}, + {X86::VPDPBSSDSZ256rrk, X86::VPDPBSSDSZ256rmbk, TB_BCAST_D}, + {X86::VPDPBSSDSZ256rrkz, X86::VPDPBSSDSZ256rmbkz, TB_BCAST_D}, + {X86::VPDPBSSDSZrrk, X86::VPDPBSSDSZrmbk, TB_BCAST_D}, + {X86::VPDPBSSDSZrrkz, X86::VPDPBSSDSZrmbkz, TB_BCAST_D}, + {X86::VPDPBSSDZ128rrk, X86::VPDPBSSDZ128rmbk, TB_BCAST_D}, + {X86::VPDPBSSDZ128rrkz, X86::VPDPBSSDZ128rmbkz, TB_BCAST_D}, + {X86::VPDPBSSDZ256rrk, X86::VPDPBSSDZ256rmbk, TB_BCAST_D}, + {X86::VPDPBSSDZ256rrkz, X86::VPDPBSSDZ256rmbkz, TB_BCAST_D}, + {X86::VPDPBSSDZrrk, X86::VPDPBSSDZrmbk, TB_BCAST_D}, + {X86::VPDPBSSDZrrkz, X86::VPDPBSSDZrmbkz, TB_BCAST_D}, + {X86::VPDPBSUDSZ128rrk, X86::VPDPBSUDSZ128rmbk, TB_BCAST_D}, + {X86::VPDPBSUDSZ128rrkz, X86::VPDPBSUDSZ128rmbkz, TB_BCAST_D}, + {X86::VPDPBSUDSZ256rrk, X86::VPDPBSUDSZ256rmbk, TB_BCAST_D}, + {X86::VPDPBSUDSZ256rrkz, X86::VPDPBSUDSZ256rmbkz, TB_BCAST_D}, + {X86::VPDPBSUDSZrrk, X86::VPDPBSUDSZrmbk, TB_BCAST_D}, + {X86::VPDPBSUDSZrrkz, X86::VPDPBSUDSZrmbkz, TB_BCAST_D}, + {X86::VPDPBSUDZ128rrk, X86::VPDPBSUDZ128rmbk, TB_BCAST_D}, + {X86::VPDPBSUDZ128rrkz, X86::VPDPBSUDZ128rmbkz, TB_BCAST_D}, + {X86::VPDPBSUDZ256rrk, X86::VPDPBSUDZ256rmbk, TB_BCAST_D}, + {X86::VPDPBSUDZ256rrkz, X86::VPDPBSUDZ256rmbkz, TB_BCAST_D}, + {X86::VPDPBSUDZrrk, X86::VPDPBSUDZrmbk, TB_BCAST_D}, + {X86::VPDPBSUDZrrkz, X86::VPDPBSUDZrmbkz, TB_BCAST_D}, + {X86::VPDPBUSDSZ128rrk, X86::VPDPBUSDSZ128rmbk, TB_BCAST_D}, + {X86::VPDPBUSDSZ128rrkz, X86::VPDPBUSDSZ128rmbkz, TB_BCAST_D}, + {X86::VPDPBUSDSZ256rrk, X86::VPDPBUSDSZ256rmbk, TB_BCAST_D}, + {X86::VPDPBUSDSZ256rrkz, X86::VPDPBUSDSZ256rmbkz, TB_BCAST_D}, + {X86::VPDPBUSDSZrrk, X86::VPDPBUSDSZrmbk, TB_BCAST_D}, + {X86::VPDPBUSDSZrrkz, X86::VPDPBUSDSZrmbkz, TB_BCAST_D}, + {X86::VPDPBUSDZ128rrk, X86::VPDPBUSDZ128rmbk, TB_BCAST_D}, + {X86::VPDPBUSDZ128rrkz, X86::VPDPBUSDZ128rmbkz, TB_BCAST_D}, + {X86::VPDPBUSDZ256rrk, X86::VPDPBUSDZ256rmbk, TB_BCAST_D}, + {X86::VPDPBUSDZ256rrkz, X86::VPDPBUSDZ256rmbkz, TB_BCAST_D}, + {X86::VPDPBUSDZrrk, X86::VPDPBUSDZrmbk, TB_BCAST_D}, + {X86::VPDPBUSDZrrkz, X86::VPDPBUSDZrmbkz, TB_BCAST_D}, + {X86::VPDPBUUDSZ128rrk, X86::VPDPBUUDSZ128rmbk, TB_BCAST_D}, + {X86::VPDPBUUDSZ128rrkz, X86::VPDPBUUDSZ128rmbkz, TB_BCAST_D}, + {X86::VPDPBUUDSZ256rrk, X86::VPDPBUUDSZ256rmbk, TB_BCAST_D}, + {X86::VPDPBUUDSZ256rrkz, X86::VPDPBUUDSZ256rmbkz, TB_BCAST_D}, + {X86::VPDPBUUDSZrrk, X86::VPDPBUUDSZrmbk, TB_BCAST_D}, + {X86::VPDPBUUDSZrrkz, X86::VPDPBUUDSZrmbkz, TB_BCAST_D}, + {X86::VPDPBUUDZ128rrk, X86::VPDPBUUDZ128rmbk, TB_BCAST_D}, + {X86::VPDPBUUDZ128rrkz, X86::VPDPBUUDZ128rmbkz, TB_BCAST_D}, + {X86::VPDPBUUDZ256rrk, X86::VPDPBUUDZ256rmbk, TB_BCAST_D}, + {X86::VPDPBUUDZ256rrkz, X86::VPDPBUUDZ256rmbkz, TB_BCAST_D}, + {X86::VPDPBUUDZrrk, X86::VPDPBUUDZrmbk, TB_BCAST_D}, + {X86::VPDPBUUDZrrkz, X86::VPDPBUUDZrmbkz, TB_BCAST_D}, + {X86::VPDPWSSDSZ128rrk, X86::VPDPWSSDSZ128rmbk, TB_BCAST_D}, + {X86::VPDPWSSDSZ128rrkz, X86::VPDPWSSDSZ128rmbkz, TB_BCAST_D}, + {X86::VPDPWSSDSZ256rrk, X86::VPDPWSSDSZ256rmbk, TB_BCAST_D}, + {X86::VPDPWSSDSZ256rrkz, X86::VPDPWSSDSZ256rmbkz, TB_BCAST_D}, + {X86::VPDPWSSDSZrrk, X86::VPDPWSSDSZrmbk, TB_BCAST_D}, + {X86::VPDPWSSDSZrrkz, X86::VPDPWSSDSZrmbkz, TB_BCAST_D}, + {X86::VPDPWSSDZ128rrk, X86::VPDPWSSDZ128rmbk, TB_BCAST_D}, + {X86::VPDPWSSDZ128rrkz, X86::VPDPWSSDZ128rmbkz, TB_BCAST_D}, + {X86::VPDPWSSDZ256rrk, X86::VPDPWSSDZ256rmbk, TB_BCAST_D}, + {X86::VPDPWSSDZ256rrkz, X86::VPDPWSSDZ256rmbkz, TB_BCAST_D}, + {X86::VPDPWSSDZrrk, X86::VPDPWSSDZrmbk, TB_BCAST_D}, + {X86::VPDPWSSDZrrkz, X86::VPDPWSSDZrmbkz, TB_BCAST_D}, + {X86::VPDPWSUDSZ128rrk, X86::VPDPWSUDSZ128rmbk, TB_BCAST_D}, + {X86::VPDPWSUDSZ128rrkz, X86::VPDPWSUDSZ128rmbkz, TB_BCAST_D}, + {X86::VPDPWSUDSZ256rrk, X86::VPDPWSUDSZ256rmbk, TB_BCAST_D}, + {X86::VPDPWSUDSZ256rrkz, X86::VPDPWSUDSZ256rmbkz, TB_BCAST_D}, + {X86::VPDPWSUDSZrrk, X86::VPDPWSUDSZrmbk, TB_BCAST_D}, + {X86::VPDPWSUDSZrrkz, X86::VPDPWSUDSZrmbkz, TB_BCAST_D}, + {X86::VPDPWSUDZ128rrk, X86::VPDPWSUDZ128rmbk, TB_BCAST_D}, + {X86::VPDPWSUDZ128rrkz, X86::VPDPWSUDZ128rmbkz, TB_BCAST_D}, + {X86::VPDPWSUDZ256rrk, X86::VPDPWSUDZ256rmbk, TB_BCAST_D}, + {X86::VPDPWSUDZ256rrkz, X86::VPDPWSUDZ256rmbkz, TB_BCAST_D}, + {X86::VPDPWSUDZrrk, X86::VPDPWSUDZrmbk, TB_BCAST_D}, + {X86::VPDPWSUDZrrkz, X86::VPDPWSUDZrmbkz, TB_BCAST_D}, + {X86::VPDPWUSDSZ128rrk, X86::VPDPWUSDSZ128rmbk, TB_BCAST_D}, + {X86::VPDPWUSDSZ128rrkz, X86::VPDPWUSDSZ128rmbkz, TB_BCAST_D}, + {X86::VPDPWUSDSZ256rrk, X86::VPDPWUSDSZ256rmbk, TB_BCAST_D}, + {X86::VPDPWUSDSZ256rrkz, X86::VPDPWUSDSZ256rmbkz, TB_BCAST_D}, + {X86::VPDPWUSDSZrrk, X86::VPDPWUSDSZrmbk, TB_BCAST_D}, + {X86::VPDPWUSDSZrrkz, X86::VPDPWUSDSZrmbkz, TB_BCAST_D}, + {X86::VPDPWUSDZ128rrk, X86::VPDPWUSDZ128rmbk, TB_BCAST_D}, + {X86::VPDPWUSDZ128rrkz, X86::VPDPWUSDZ128rmbkz, TB_BCAST_D}, + {X86::VPDPWUSDZ256rrk, X86::VPDPWUSDZ256rmbk, TB_BCAST_D}, + {X86::VPDPWUSDZ256rrkz, X86::VPDPWUSDZ256rmbkz, TB_BCAST_D}, + {X86::VPDPWUSDZrrk, X86::VPDPWUSDZrmbk, TB_BCAST_D}, + {X86::VPDPWUSDZrrkz, X86::VPDPWUSDZrmbkz, TB_BCAST_D}, + {X86::VPDPWUUDSZ128rrk, X86::VPDPWUUDSZ128rmbk, TB_BCAST_D}, + {X86::VPDPWUUDSZ128rrkz, X86::VPDPWUUDSZ128rmbkz, TB_BCAST_D}, + {X86::VPDPWUUDSZ256rrk, X86::VPDPWUUDSZ256rmbk, TB_BCAST_D}, + {X86::VPDPWUUDSZ256rrkz, X86::VPDPWUUDSZ256rmbkz, TB_BCAST_D}, + {X86::VPDPWUUDSZrrk, X86::VPDPWUUDSZrmbk, TB_BCAST_D}, + {X86::VPDPWUUDSZrrkz, X86::VPDPWUUDSZrmbkz, TB_BCAST_D}, + {X86::VPDPWUUDZ128rrk, X86::VPDPWUUDZ128rmbk, TB_BCAST_D}, + {X86::VPDPWUUDZ128rrkz, X86::VPDPWUUDZ128rmbkz, TB_BCAST_D}, + {X86::VPDPWUUDZ256rrk, X86::VPDPWUUDZ256rmbk, TB_BCAST_D}, + {X86::VPDPWUUDZ256rrkz, X86::VPDPWUUDZ256rmbkz, TB_BCAST_D}, + {X86::VPDPWUUDZrrk, X86::VPDPWUUDZrmbk, TB_BCAST_D}, + {X86::VPDPWUUDZrrkz, X86::VPDPWUUDZrmbkz, TB_BCAST_D}, {X86::VPERMDZ256rrk, X86::VPERMDZ256rmbk, TB_BCAST_D}, {X86::VPERMDZrrk, X86::VPERMDZrmbk, TB_BCAST_D}, {X86::VPERMI2DZ128rrk, X86::VPERMI2DZ128rmbk, TB_BCAST_D}, diff --git a/llvm/test/TableGen/x86-instr-mapping.inc b/llvm/test/TableGen/x86-instr-mapping.inc index 1629e0eef93ec..5cf5417c0911d 100644 --- a/llvm/test/TableGen/x86-instr-mapping.inc +++ b/llvm/test/TableGen/x86-instr-mapping.inc @@ -952,70 +952,70 @@ static const X86TableEntry X86CompressEVEXTable[] = { { X86::VPCLMULQDQZ128rri, X86::VPCLMULQDQrri }, { X86::VPCLMULQDQZ256rmi, X86::VPCLMULQDQYrmi }, { X86::VPCLMULQDQZ256rri, X86::VPCLMULQDQYrri }, - { X86::VPDPBSSDSZ128m, X86::VPDPBSSDSrm }, - { X86::VPDPBSSDSZ128r, X86::VPDPBSSDSrr }, - { X86::VPDPBSSDSZ256m, X86::VPDPBSSDSYrm }, - { X86::VPDPBSSDSZ256r, X86::VPDPBSSDSYrr }, - { X86::VPDPBSSDZ128m, X86::VPDPBSSDrm }, - { X86::VPDPBSSDZ128r, X86::VPDPBSSDrr }, - { X86::VPDPBSSDZ256m, X86::VPDPBSSDYrm }, - { X86::VPDPBSSDZ256r, X86::VPDPBSSDYrr }, - { X86::VPDPBSUDSZ128m, X86::VPDPBSUDSrm }, - { X86::VPDPBSUDSZ128r, X86::VPDPBSUDSrr }, - { X86::VPDPBSUDSZ256m, X86::VPDPBSUDSYrm }, - { X86::VPDPBSUDSZ256r, X86::VPDPBSUDSYrr }, - { X86::VPDPBSUDZ128m, X86::VPDPBSUDrm }, - { X86::VPDPBSUDZ128r, X86::VPDPBSUDrr }, - { X86::VPDPBSUDZ256m, X86::VPDPBSUDYrm }, - { X86::VPDPBSUDZ256r, X86::VPDPBSUDYrr }, - { X86::VPDPBUSDSZ128m, X86::VPDPBUSDSrm }, - { X86::VPDPBUSDSZ128r, X86::VPDPBUSDSrr }, - { X86::VPDPBUSDSZ256m, X86::VPDPBUSDSYrm }, - { X86::VPDPBUSDSZ256r, X86::VPDPBUSDSYrr }, - { X86::VPDPBUSDZ128m, X86::VPDPBUSDrm }, - { X86::VPDPBUSDZ128r, X86::VPDPBUSDrr }, - { X86::VPDPBUSDZ256m, X86::VPDPBUSDYrm }, - { X86::VPDPBUSDZ256r, X86::VPDPBUSDYrr }, - { X86::VPDPBUUDSZ128m, X86::VPDPBUUDSrm }, - { X86::VPDPBUUDSZ128r, X86::VPDPBUUDSrr }, - { X86::VPDPBUUDSZ256m, X86::VPDPBUUDSYrm }, - { X86::VPDPBUUDSZ256r, X86::VPDPBUUDSYrr }, - { X86::VPDPBUUDZ128m, X86::VPDPBUUDrm }, - { X86::VPDPBUUDZ128r, X86::VPDPBUUDrr }, - { X86::VPDPBUUDZ256m, X86::VPDPBUUDYrm }, - { X86::VPDPBUUDZ256r, X86::VPDPBUUDYrr }, - { X86::VPDPWSSDSZ128m, X86::VPDPWSSDSrm }, - { X86::VPDPWSSDSZ128r, X86::VPDPWSSDSrr }, - { X86::VPDPWSSDSZ256m, X86::VPDPWSSDSYrm }, - { X86::VPDPWSSDSZ256r, X86::VPDPWSSDSYrr }, - { X86::VPDPWSSDZ128m, X86::VPDPWSSDrm }, - { X86::VPDPWSSDZ128r, X86::VPDPWSSDrr }, - { X86::VPDPWSSDZ256m, X86::VPDPWSSDYrm }, - { X86::VPDPWSSDZ256r, X86::VPDPWSSDYrr }, - { X86::VPDPWSUDSZ128m, X86::VPDPWSUDSrm }, - { X86::VPDPWSUDSZ128r, X86::VPDPWSUDSrr }, - { X86::VPDPWSUDSZ256m, X86::VPDPWSUDSYrm }, - { X86::VPDPWSUDSZ256r, X86::VPDPWSUDSYrr }, - { X86::VPDPWSUDZ128m, X86::VPDPWSUDrm }, - { X86::VPDPWSUDZ128r, X86::VPDPWSUDrr }, - { X86::VPDPWSUDZ256m, X86::VPDPWSUDYrm }, - { X86::VPDPWSUDZ256r, X86::VPDPWSUDYrr }, - { X86::VPDPWUSDSZ128m, X86::VPDPWUSDSrm }, - { X86::VPDPWUSDSZ128r, X86::VPDPWUSDSrr }, - { X86::VPDPWUSDSZ256m, X86::VPDPWUSDSYrm }, - { X86::VPDPWUSDSZ256r, X86::VPDPWUSDSYrr }, - { X86::VPDPWUSDZ128m, X86::VPDPWUSDrm }, - { X86::VPDPWUSDZ128r, X86::VPDPWUSDrr }, - { X86::VPDPWUSDZ256m, X86::VPDPWUSDYrm }, - { X86::VPDPWUSDZ256r, X86::VPDPWUSDYrr }, - { X86::VPDPWUUDSZ128m, X86::VPDPWUUDSrm }, - { X86::VPDPWUUDSZ128r, X86::VPDPWUUDSrr }, - { X86::VPDPWUUDSZ256m, X86::VPDPWUUDSYrm }, - { X86::VPDPWUUDSZ256r, X86::VPDPWUUDSYrr }, - { X86::VPDPWUUDZ128m, X86::VPDPWUUDrm }, - { X86::VPDPWUUDZ128r, X86::VPDPWUUDrr }, - { X86::VPDPWUUDZ256m, X86::VPDPWUUDYrm }, - { X86::VPDPWUUDZ256r, X86::VPDPWUUDYrr }, + { X86::VPDPBSSDSZ128rm, X86::VPDPBSSDSrm }, + { X86::VPDPBSSDSZ128rr, X86::VPDPBSSDSrr }, + { X86::VPDPBSSDSZ256rm, X86::VPDPBSSDSYrm }, + { X86::VPDPBSSDSZ256rr, X86::VPDPBSSDSYrr }, + { X86::VPDPBSSDZ128rm, X86::VPDPBSSDrm }, + { X86::VPDPBSSDZ128rr, X86::VPDPBSSDrr }, + { X86::VPDPBSSDZ256rm, X86::VPDPBSSDYrm }, + { X86::VPDPBSSDZ256rr, X86::VPDPBSSDYrr }, + { X86::VPDPBSUDSZ128rm, X86::VPDPBSUDSrm }, + { X86::VPDPBSUDSZ128rr, X86::VPDPBSUDSrr }, + { X86::VPDPBSUDSZ256rm, X86::VPDPBSUDSYrm }, + { X86::VPDPBSUDSZ256rr, X86::VPDPBSUDSYrr }, + { X86::VPDPBSUDZ128rm, X86::VPDPBSUDrm }, + { X86::VPDPBSUDZ128rr, X86::VPDPBSUDrr }, + { X86::VPDPBSUDZ256rm, X86::VPDPBSUDYrm }, + { X86::VPDPBSUDZ256rr, X86::VPDPBSUDYrr }, + { X86::VPDPBUSDSZ128rm, X86::VPDPBUSDSrm }, + { X86::VPDPBUSDSZ128rr, X86::VPDPBUSDSrr }, + { X86::VPDPBUSDSZ256rm, X86::VPDPBUSDSYrm }, + { X86::VPDPBUSDSZ256rr, X86::VPDPBUSDSYrr }, + { X86::VPDPBUSDZ128rm, X86::VPDPBUSDrm }, + { X86::VPDPBUSDZ128rr, X86::VPDPBUSDrr }, + { X86::VPDPBUSDZ256rm, X86::VPDPBUSDYrm }, + { X86::VPDPBUSDZ256rr, X86::VPDPBUSDYrr }, + { X86::VPDPBUUDSZ128rm, X86::VPDPBUUDSrm }, + { X86::VPDPBUUDSZ128rr, X86::VPDPBUUDSrr }, + { X86::VPDPBUUDSZ256rm, X86::VPDPBUUDSYrm }, + { X86::VPDPBUUDSZ256rr, X86::VPDPBUUDSYrr }, + { X86::VPDPBUUDZ128rm, X86::VPDPBUUDrm }, + { X86::VPDPBUUDZ128rr, X86::VPDPBUUDrr }, + { X86::VPDPBUUDZ256rm, X86::VPDPBUUDYrm }, + { X86::VPDPBUUDZ256rr, X86::VPDPBUUDYrr }, + { X86::VPDPWSSDSZ128rm, X86::VPDPWSSDSrm }, + { X86::VPDPWSSDSZ128rr, X86::VPDPWSSDSrr }, + { X86::VPDPWSSDSZ256rm, X86::VPDPWSSDSYrm }, + { X86::VPDPWSSDSZ256rr, X86::VPDPWSSDSYrr }, + { X86::VPDPWSSDZ128rm, X86::VPDPWSSDrm }, + { X86::VPDPWSSDZ128rr, X86::VPDPWSSDrr }, + { X86::VPDPWSSDZ256rm, X86::VPDPWSSDYrm }, + { X86::VPDPWSSDZ256rr, X86::VPDPWSSDYrr }, + { X86::VPDPWSUDSZ128rm, X86::VPDPWSUDSrm }, + { X86::VPDPWSUDSZ128rr, X86::VPDPWSUDSrr }, + { X86::VPDPWSUDSZ256rm, X86::VPDPWSUDSYrm }, + { X86::VPDPWSUDSZ256rr, X86::VPDPWSUDSYrr }, + { X86::VPDPWSUDZ128rm, X86::VPDPWSUDrm }, + { X86::VPDPWSUDZ128rr, X86::VPDPWSUDrr }, + { X86::VPDPWSUDZ256rm, X86::VPDPWSUDYrm }, + { X86::VPDPWSUDZ256rr, X86::VPDPWSUDYrr }, + { X86::VPDPWUSDSZ128rm, X86::VPDPWUSDSrm }, + { X86::VPDPWUSDSZ128rr, X86::VPDPWUSDSrr }, + { X86::VPDPWUSDSZ256rm, X86::VPDPWUSDSYrm }, + { X86::VPDPWUSDSZ256rr, X86::VPDPWUSDSYrr }, + { X86::VPDPWUSDZ128rm, X86::VPDPWUSDrm }, + { X86::VPDPWUSDZ128rr, X86::VPDPWUSDrr }, + { X86::VPDPWUSDZ256rm, X86::VPDPWUSDYrm }, + { X86::VPDPWUSDZ256rr, X86::VPDPWUSDYrr }, + { X86::VPDPWUUDSZ128rm, X86::VPDPWUUDSrm }, + { X86::VPDPWUUDSZ128rr, X86::VPDPWUUDSrr }, + { X86::VPDPWUUDSZ256rm, X86::VPDPWUUDSYrm }, + { X86::VPDPWUUDSZ256rr, X86::VPDPWUUDSYrr }, + { X86::VPDPWUUDZ128rm, X86::VPDPWUUDrm }, + { X86::VPDPWUUDZ128rr, X86::VPDPWUUDrr }, + { X86::VPDPWUUDZ256rm, X86::VPDPWUUDYrm }, + { X86::VPDPWUUDZ256rr, X86::VPDPWUUDYrr }, { X86::VPERMDZ256rm, X86::VPERMDYrm }, { X86::VPERMDZ256rr, X86::VPERMDYrr }, { X86::VPERMILPDZ128mi, X86::VPERMILPDmi }, diff --git a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s index 8152d18f56c30..4b73a7fc0e8b8 100644 --- a/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s +++ b/llvm/test/tools/llvm-mca/X86/AlderlakeP/resources-avxvnni.s @@ -1,29 +1,29 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=alderlake -instruction-tables < %s | FileCheck %s -vpdpbusd %xmm0, %xmm1, %xmm2 -vpdpbusd (%rax), %xmm1, %xmm2 +{vex} vpdpbusd %xmm0, %xmm1, %xmm2 +{vex} vpdpbusd (%rax), %xmm1, %xmm2 -vpdpbusd %ymm0, %ymm1, %ymm2 -vpdpbusd (%rax), %ymm1, %ymm2 +{vex} vpdpbusd %ymm0, %ymm1, %ymm2 +{vex} vpdpbusd (%rax), %ymm1, %ymm2 -vpdpbusds %xmm0, %xmm1, %xmm2 -vpdpbusds (%rax), %xmm1, %xmm2 +{vex} vpdpbusds %xmm0, %xmm1, %xmm2 +{vex} vpdpbusds (%rax), %xmm1, %xmm2 -vpdpbusds %ymm0, %ymm1, %ymm2 -vpdpbusds (%rax), %ymm1, %ymm2 +{vex} vpdpbusds %ymm0, %ymm1, %ymm2 +{vex} vpdpbusds (%rax), %ymm1, %ymm2 -vpdpwssd %xmm0, %xmm1, %xmm2 -vpdpwssd (%rax), %xmm1, %xmm2 +{vex} vpdpwssd %xmm0, %xmm1, %xmm2 +{vex} vpdpwssd (%rax), %xmm1, %xmm2 -vpdpwssd %ymm0, %ymm1, %ymm2 -vpdpwssd (%rax), %ymm1, %ymm2 +{vex} vpdpwssd %ymm0, %ymm1, %ymm2 +{vex} vpdpwssd (%rax), %ymm1, %ymm2 -vpdpwssds %xmm0, %xmm1, %xmm2 -vpdpwssds (%rax), %xmm1, %xmm2 +{vex} vpdpwssds %xmm0, %xmm1, %xmm2 +{vex} vpdpwssds (%rax), %xmm1, %xmm2 -vpdpwssds %ymm0, %ymm1, %ymm2 -vpdpwssds (%rax), %ymm1, %ymm2 +{vex} vpdpwssds %ymm0, %ymm1, %ymm2 +{vex} vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -34,22 +34,22 @@ vpdpwssds (%rax), %ymm1, %ymm2 # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 5 0.50 vpdpbusd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 13 0.50 * vpdpbusd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 0.50 vpdpbusd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 13 0.50 * vpdpbusd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 5 0.50 vpdpbusds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 13 0.50 * vpdpbusds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 0.50 vpdpbusds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 13 0.50 * vpdpbusds (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 5 0.50 vpdpwssd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 13 0.50 * vpdpwssd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 0.50 vpdpwssd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 13 0.50 * vpdpwssd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 5 0.50 vpdpwssds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 13 0.50 * vpdpwssds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 0.50 vpdpwssds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 13 0.50 * vpdpwssds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpbusd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpbusd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpbusd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpbusd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpbusds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpbusds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpbusds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpbusds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpwssd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpwssd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpwssd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpwssd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpwssds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpwssds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpwssds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Resources: # CHECK-NEXT: [0] - ADLPPort00 @@ -72,19 +72,19 @@ vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpbusd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpbusd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpbusd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpbusd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpbusds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpbusds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpbusds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpbusds (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpwssd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpwssd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpwssd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpwssd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpwssds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpwssds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpwssds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpwssds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpbusd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpbusd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpbusd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpbusd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpbusds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpbusds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpbusds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpbusds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpwssd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpwssd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpwssd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpwssd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpwssds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpwssds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpwssds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpwssds (%rax), %ymm1, %ymm2 diff --git a/llvm/test/tools/llvm-mca/X86/Generic/resources-avxvnni.s b/llvm/test/tools/llvm-mca/X86/Generic/resources-avxvnni.s index cb1f166e41d78..386be1795b0c5 100644 --- a/llvm/test/tools/llvm-mca/X86/Generic/resources-avxvnni.s +++ b/llvm/test/tools/llvm-mca/X86/Generic/resources-avxvnni.s @@ -1,29 +1,29 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s -vpdpbusd %xmm0, %xmm1, %xmm2 -vpdpbusd (%rax), %xmm1, %xmm2 +{vex} vpdpbusd %xmm0, %xmm1, %xmm2 +{vex} vpdpbusd (%rax), %xmm1, %xmm2 -vpdpbusd %ymm0, %ymm1, %ymm2 -vpdpbusd (%rax), %ymm1, %ymm2 +{vex} vpdpbusd %ymm0, %ymm1, %ymm2 +{vex} vpdpbusd (%rax), %ymm1, %ymm2 -vpdpbusds %xmm0, %xmm1, %xmm2 -vpdpbusds (%rax), %xmm1, %xmm2 +{vex} vpdpbusds %xmm0, %xmm1, %xmm2 +{vex} vpdpbusds (%rax), %xmm1, %xmm2 -vpdpbusds %ymm0, %ymm1, %ymm2 -vpdpbusds (%rax), %ymm1, %ymm2 +{vex} vpdpbusds %ymm0, %ymm1, %ymm2 +{vex} vpdpbusds (%rax), %ymm1, %ymm2 -vpdpwssd %xmm0, %xmm1, %xmm2 -vpdpwssd (%rax), %xmm1, %xmm2 +{vex} vpdpwssd %xmm0, %xmm1, %xmm2 +{vex} vpdpwssd (%rax), %xmm1, %xmm2 -vpdpwssd %ymm0, %ymm1, %ymm2 -vpdpwssd (%rax), %ymm1, %ymm2 +{vex} vpdpwssd %ymm0, %ymm1, %ymm2 +{vex} vpdpwssd (%rax), %ymm1, %ymm2 -vpdpwssds %xmm0, %xmm1, %xmm2 -vpdpwssds (%rax), %xmm1, %xmm2 +{vex} vpdpwssds %xmm0, %xmm1, %xmm2 +{vex} vpdpwssds (%rax), %xmm1, %xmm2 -vpdpwssds %ymm0, %ymm1, %ymm2 -vpdpwssds (%rax), %ymm1, %ymm2 +{vex} vpdpwssds %ymm0, %ymm1, %ymm2 +{vex} vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -34,22 +34,22 @@ vpdpwssds (%rax), %ymm1, %ymm2 # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 5 1.00 vpdpbusd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 11 1.00 * vpdpbusd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 1.00 vpdpbusd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 12 1.00 * vpdpbusd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 5 1.00 vpdpbusds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 11 1.00 * vpdpbusds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 1.00 vpdpbusds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 12 1.00 * vpdpbusds (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 5 1.00 vpdpwssd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 11 1.00 * vpdpwssd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 1.00 vpdpwssd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 12 1.00 * vpdpwssd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 5 1.00 vpdpwssds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 11 1.00 * vpdpwssds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 1.00 vpdpwssds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 12 1.00 * vpdpwssds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 1.00 {vex} vpdpbusd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * {vex} vpdpbusd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 {vex} vpdpbusd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 1.00 * {vex} vpdpbusd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 1.00 {vex} vpdpbusds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * {vex} vpdpbusds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 {vex} vpdpbusds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 1.00 * {vex} vpdpbusds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 1.00 {vex} vpdpwssd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * {vex} vpdpwssd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 {vex} vpdpwssd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 1.00 * {vex} vpdpwssd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 1.00 {vex} vpdpwssds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 11 1.00 * {vex} vpdpwssds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 1.00 {vex} vpdpwssds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 12 1.00 * {vex} vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Resources: # CHECK-NEXT: [0] - SBDivider @@ -67,19 +67,19 @@ vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions: -# CHECK-NEXT: - - 1.00 - - - - - vpdpbusd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpdpbusd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - vpdpbusd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpdpbusd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: - - 1.00 - - - - - vpdpbusds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpdpbusds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - vpdpbusds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpdpbusds (%rax), %ymm1, %ymm2 -# CHECK-NEXT: - - 1.00 - - - - - vpdpwssd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpdpwssd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - vpdpwssd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpdpwssd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: - - 1.00 - - - - - vpdpwssds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpdpwssds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - 1.00 - - - - - vpdpwssds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 vpdpwssds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - - - {vex} vpdpbusd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 {vex} vpdpbusd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - {vex} vpdpbusd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 {vex} vpdpbusd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - - - {vex} vpdpbusds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 {vex} vpdpbusds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - {vex} vpdpbusds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 {vex} vpdpbusds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - - - {vex} vpdpwssd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 {vex} vpdpwssd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - {vex} vpdpwssd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 {vex} vpdpwssd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - - - {vex} vpdpwssds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 {vex} vpdpwssds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - 1.00 - - - - - {vex} vpdpwssds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - 1.00 - - - 0.50 0.50 {vex} vpdpwssds (%rax), %ymm1, %ymm2 diff --git a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxvnni.s b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxvnni.s index 38d9959675f1b..5356019bbddec 100644 --- a/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxvnni.s +++ b/llvm/test/tools/llvm-mca/X86/LunarlakeP/resources-avxvnni.s @@ -1,29 +1,29 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=lunarlake -instruction-tables < %s | FileCheck %s -vpdpbusd %xmm0, %xmm1, %xmm2 -vpdpbusd (%rax), %xmm1, %xmm2 +{vex} vpdpbusd %xmm0, %xmm1, %xmm2 +{vex} vpdpbusd (%rax), %xmm1, %xmm2 -vpdpbusd %ymm0, %ymm1, %ymm2 -vpdpbusd (%rax), %ymm1, %ymm2 +{vex} vpdpbusd %ymm0, %ymm1, %ymm2 +{vex} vpdpbusd (%rax), %ymm1, %ymm2 -vpdpbusds %xmm0, %xmm1, %xmm2 -vpdpbusds (%rax), %xmm1, %xmm2 +{vex} vpdpbusds %xmm0, %xmm1, %xmm2 +{vex} vpdpbusds (%rax), %xmm1, %xmm2 -vpdpbusds %ymm0, %ymm1, %ymm2 -vpdpbusds (%rax), %ymm1, %ymm2 +{vex} vpdpbusds %ymm0, %ymm1, %ymm2 +{vex} vpdpbusds (%rax), %ymm1, %ymm2 -vpdpwssd %xmm0, %xmm1, %xmm2 -vpdpwssd (%rax), %xmm1, %xmm2 +{vex} vpdpwssd %xmm0, %xmm1, %xmm2 +{vex} vpdpwssd (%rax), %xmm1, %xmm2 -vpdpwssd %ymm0, %ymm1, %ymm2 -vpdpwssd (%rax), %ymm1, %ymm2 +{vex} vpdpwssd %ymm0, %ymm1, %ymm2 +{vex} vpdpwssd (%rax), %ymm1, %ymm2 -vpdpwssds %xmm0, %xmm1, %xmm2 -vpdpwssds (%rax), %xmm1, %xmm2 +{vex} vpdpwssds %xmm0, %xmm1, %xmm2 +{vex} vpdpwssds (%rax), %xmm1, %xmm2 -vpdpwssds %ymm0, %ymm1, %ymm2 -vpdpwssds (%rax), %ymm1, %ymm2 +{vex} vpdpwssds %ymm0, %ymm1, %ymm2 +{vex} vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -34,22 +34,22 @@ vpdpwssds (%rax), %ymm1, %ymm2 # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 4 2.00 vpdpbusd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 1 10 2.00 * vpdpbusd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 2.00 vpdpbusd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 1 11 2.33 * vpdpbusd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 2.00 vpdpbusds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 1 10 2.00 * vpdpbusds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 2.00 vpdpbusds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 1 11 2.33 * vpdpbusds (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 2.00 vpdpwssd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 1 10 2.00 * vpdpwssd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 2.00 vpdpwssd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 1 11 2.33 * vpdpwssd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 2.00 vpdpwssds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 1 10 2.00 * vpdpwssds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 2.00 vpdpwssds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 1 11 2.33 * vpdpwssds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpbusd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 10 2.00 * {vex} vpdpbusd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpbusd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 11 2.33 * {vex} vpdpbusd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpbusds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 10 2.00 * {vex} vpdpbusds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpbusds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 11 2.33 * {vex} vpdpbusds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpwssd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 10 2.00 * {vex} vpdpwssd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpwssd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 11 2.33 * {vex} vpdpwssd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpwssds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 10 2.00 * {vex} vpdpwssds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpwssds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 11 2.33 * {vex} vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Resources: # CHECK-NEXT: [0] - LNLPPort00 @@ -78,19 +78,19 @@ vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] Instructions: -# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpbusd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpdpbusd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpbusd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpdpbusd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpbusds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpdpbusds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpbusds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpdpbusds (%rax), %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpwssd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpdpwssd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpwssd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpdpwssd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpwssds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - vpdpwssds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - vpdpwssds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - vpdpwssds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - {vex} vpdpbusd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - {vex} vpdpbusd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - {vex} vpdpbusd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - {vex} vpdpbusd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - {vex} vpdpbusds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - {vex} vpdpbusds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - {vex} vpdpbusds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - {vex} vpdpbusds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - {vex} vpdpwssd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - {vex} vpdpwssd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - {vex} vpdpwssd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - {vex} vpdpwssd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - {vex} vpdpwssds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 2.00 - - - - 2.00 2.00 - - {vex} vpdpwssds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - - - - - - - - 2.00 2.00 - - {vex} vpdpwssds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 2.33 2.33 2.33 - - - - 2.00 2.00 - - {vex} vpdpwssds (%rax), %ymm1, %ymm2 diff --git a/llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxvnni.s b/llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxvnni.s index 2b64fedbd1f4e..0abd4b888a173 100644 --- a/llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxvnni.s +++ b/llvm/test/tools/llvm-mca/X86/SapphireRapids/resources-avxvnni.s @@ -1,29 +1,29 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids -instruction-tables < %s | FileCheck %s -vpdpbusd %xmm0, %xmm1, %xmm2 -vpdpbusd (%rax), %xmm1, %xmm2 +{vex} vpdpbusd %xmm0, %xmm1, %xmm2 +{vex} vpdpbusd (%rax), %xmm1, %xmm2 -vpdpbusd %ymm0, %ymm1, %ymm2 -vpdpbusd (%rax), %ymm1, %ymm2 +{vex} vpdpbusd %ymm0, %ymm1, %ymm2 +{vex} vpdpbusd (%rax), %ymm1, %ymm2 -vpdpbusds %xmm0, %xmm1, %xmm2 -vpdpbusds (%rax), %xmm1, %xmm2 +{vex} vpdpbusds %xmm0, %xmm1, %xmm2 +{vex} vpdpbusds (%rax), %xmm1, %xmm2 -vpdpbusds %ymm0, %ymm1, %ymm2 -vpdpbusds (%rax), %ymm1, %ymm2 +{vex} vpdpbusds %ymm0, %ymm1, %ymm2 +{vex} vpdpbusds (%rax), %ymm1, %ymm2 -vpdpwssd %xmm0, %xmm1, %xmm2 -vpdpwssd (%rax), %xmm1, %xmm2 +{vex} vpdpwssd %xmm0, %xmm1, %xmm2 +{vex} vpdpwssd (%rax), %xmm1, %xmm2 -vpdpwssd %ymm0, %ymm1, %ymm2 -vpdpwssd (%rax), %ymm1, %ymm2 +{vex} vpdpwssd %ymm0, %ymm1, %ymm2 +{vex} vpdpwssd (%rax), %ymm1, %ymm2 -vpdpwssds %xmm0, %xmm1, %xmm2 -vpdpwssds (%rax), %xmm1, %xmm2 +{vex} vpdpwssds %xmm0, %xmm1, %xmm2 +{vex} vpdpwssds (%rax), %xmm1, %xmm2 -vpdpwssds %ymm0, %ymm1, %ymm2 -vpdpwssds (%rax), %ymm1, %ymm2 +{vex} vpdpwssds %ymm0, %ymm1, %ymm2 +{vex} vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -34,22 +34,22 @@ vpdpwssds (%rax), %ymm1, %ymm2 # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 5 0.50 vpdpbusd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 13 0.50 * vpdpbusd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 0.50 vpdpbusd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 13 0.50 * vpdpbusd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 5 0.50 vpdpbusds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 13 0.50 * vpdpbusds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 0.50 vpdpbusds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 13 0.50 * vpdpbusds (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 5 0.50 vpdpwssd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 13 0.50 * vpdpwssd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 0.50 vpdpwssd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 13 0.50 * vpdpwssd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 5 0.50 vpdpwssds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 2 13 0.50 * vpdpwssds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 5 0.50 vpdpwssds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 2 13 0.50 * vpdpwssds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpbusd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpbusd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpbusd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpbusd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpbusds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpbusds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpbusds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpbusds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpwssd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpwssd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpwssd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpwssd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpwssds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpwssds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 5 0.50 {vex} vpdpwssds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 2 13 0.50 * {vex} vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Resources: # CHECK-NEXT: [0] - SPRPort00 @@ -72,19 +72,19 @@ vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions: -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpbusd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpbusd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpbusd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpbusd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpbusds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpbusds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpbusds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpbusds (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpwssd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpwssd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpwssd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpwssd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpwssds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpwssds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - vpdpwssds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - vpdpwssds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpbusd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpbusd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpbusd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpbusd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpbusds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpbusds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpbusds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpbusds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpwssd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpwssd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpwssd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpwssd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpwssds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpwssds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - {vex} vpdpwssds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 0.50 0.50 0.33 0.33 - - - - - - 0.33 - - {vex} vpdpwssds (%rax), %ymm1, %ymm2 diff --git a/llvm/test/tools/llvm-mca/X86/Znver4/resources-avxvnni.s b/llvm/test/tools/llvm-mca/X86/Znver4/resources-avxvnni.s index f0d426dbd3a63..8ff3d111fa601 100644 --- a/llvm/test/tools/llvm-mca/X86/Znver4/resources-avxvnni.s +++ b/llvm/test/tools/llvm-mca/X86/Znver4/resources-avxvnni.s @@ -1,29 +1,29 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver4 -instruction-tables < %s | FileCheck %s -vpdpbusd %xmm0, %xmm1, %xmm2 -vpdpbusd (%rax), %xmm1, %xmm2 +{vex} vpdpbusd %xmm0, %xmm1, %xmm2 +{vex} vpdpbusd (%rax), %xmm1, %xmm2 -vpdpbusd %ymm0, %ymm1, %ymm2 -vpdpbusd (%rax), %ymm1, %ymm2 +{vex} vpdpbusd %ymm0, %ymm1, %ymm2 +{vex} vpdpbusd (%rax), %ymm1, %ymm2 -vpdpbusds %xmm0, %xmm1, %xmm2 -vpdpbusds (%rax), %xmm1, %xmm2 +{vex} vpdpbusds %xmm0, %xmm1, %xmm2 +{vex} vpdpbusds (%rax), %xmm1, %xmm2 -vpdpbusds %ymm0, %ymm1, %ymm2 -vpdpbusds (%rax), %ymm1, %ymm2 +{vex} vpdpbusds %ymm0, %ymm1, %ymm2 +{vex} vpdpbusds (%rax), %ymm1, %ymm2 -vpdpwssd %xmm0, %xmm1, %xmm2 -vpdpwssd (%rax), %xmm1, %xmm2 +{vex} vpdpwssd %xmm0, %xmm1, %xmm2 +{vex} vpdpwssd (%rax), %xmm1, %xmm2 -vpdpwssd %ymm0, %ymm1, %ymm2 -vpdpwssd (%rax), %ymm1, %ymm2 +{vex} vpdpwssd %ymm0, %ymm1, %ymm2 +{vex} vpdpwssd (%rax), %ymm1, %ymm2 -vpdpwssds %xmm0, %xmm1, %xmm2 -vpdpwssds (%rax), %xmm1, %xmm2 +{vex} vpdpwssds %xmm0, %xmm1, %xmm2 +{vex} vpdpwssds (%rax), %xmm1, %xmm2 -vpdpwssds %ymm0, %ymm1, %ymm2 -vpdpwssds (%rax), %ymm1, %ymm2 +{vex} vpdpwssds %ymm0, %ymm1, %ymm2 +{vex} vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps @@ -34,22 +34,22 @@ vpdpwssds (%rax), %ymm1, %ymm2 # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: -# CHECK-NEXT: 1 4 2.00 vpdpbusd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 2.00 vpdpbusd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 1 10 0.50 * vpdpbusd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 2.00 vpdpbusds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 2.00 vpdpbusds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 1 10 0.50 * vpdpbusds (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 2.00 vpdpwssd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 2.00 vpdpwssd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 1 10 0.50 * vpdpwssd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: 1 4 2.00 vpdpwssds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: 1 4 2.00 vpdpwssds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: 1 10 0.50 * vpdpwssds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpbusd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 10 0.50 * {vex} vpdpbusd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpbusd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 10 0.50 * {vex} vpdpbusd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpbusds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 10 0.50 * {vex} vpdpbusds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpbusds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 10 0.50 * {vex} vpdpbusds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpwssd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 10 0.50 * {vex} vpdpwssd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpwssd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 10 0.50 * {vex} vpdpwssd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpwssds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: 1 10 0.50 * {vex} vpdpwssds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: 1 4 2.00 {vex} vpdpwssds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: 1 10 0.50 * {vex} vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Resources: # CHECK-NEXT: [0] - Zn4AGU0 @@ -82,19 +82,19 @@ vpdpwssds (%rax), %ymm1, %ymm2 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12.0] [12.1] [13] [14.0] [14.1] [14.2] [15.0] [15.1] [15.2] [16.0] [16.1] Instructions: -# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - vpdpbusd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpdpbusd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - vpdpbusd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpdpbusd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - vpdpbusds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpdpbusds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - vpdpbusds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpdpbusds (%rax), %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - vpdpwssd %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpdpwssd (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - vpdpwssd %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpdpwssd (%rax), %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - vpdpwssds %xmm0, %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpdpwssds (%rax), %xmm1, %xmm2 -# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - vpdpwssds %ymm0, %ymm1, %ymm2 -# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - vpdpwssds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - {vex} vpdpbusd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - {vex} vpdpbusd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - {vex} vpdpbusd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - {vex} vpdpbusd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - {vex} vpdpbusds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - {vex} vpdpbusds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - {vex} vpdpbusds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - {vex} vpdpbusds (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - {vex} vpdpwssd %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - {vex} vpdpwssd (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - {vex} vpdpwssd %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - {vex} vpdpwssd (%rax), %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - {vex} vpdpwssds %xmm0, %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - {vex} vpdpwssds (%rax), %xmm1, %xmm2 +# CHECK-NEXT: - - - - - - - - 2.00 2.00 - - - - - - - - - - - - - {vex} vpdpwssds %ymm0, %ymm1, %ymm2 +# CHECK-NEXT: - - - - - - - - 0.50 - - 0.50 0.50 0.50 - 0.33 0.33 0.33 0.33 0.33 0.33 - - {vex} vpdpwssds (%rax), %ymm1, %ymm2