From 280f1886700e08833f15e2aebfc07f7103e547ec Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 10 Sep 2025 11:33:42 -0700 Subject: [PATCH] [AMDGPU] Use subtarget call to determine number of VGPRs Since the register file was increased that is no longer valid to call VGPR_32RegClass.getNumregs() to get a total number of arch registers available on a subtarget. Fixes: SWDEV-554472 --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 9 ++++++--- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 2a977247bc2cb..edce4856f77b0 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -3452,7 +3452,7 @@ bool SITargetLowering::CanLowerReturn( // We must use the stack if return would require unavailable registers. unsigned MaxNumVGPRs = Subtarget->getMaxNumVGPRs(MF); - unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs(); + unsigned TotalNumVGPRs = Subtarget->getAddressableNumArchVGPRs(); for (unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i) if (CCInfo.isAllocated(AMDGPU::VGPR_32RegClass.getRegister(i))) return false; diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 8a1120321af9f..54426d33d3473 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -86,7 +86,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F, // FIXME: MayNeedAGPRs is a misnomer for how this is used. MFMA selection // should be separated from availability of AGPRs if (MFMAVGPRForm || - (ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() && + (ST.getMaxNumVGPRs(F) <= ST.getAddressableNumArchVGPRs() && !mayUseAGPRs(F))) MayNeedAGPRs = false; // We will select all MAI with VGPR operands. } diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp index 9f4f42185d9a0..40da4f96aefdb 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -1399,13 +1399,16 @@ unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) { return IsWave32 ? 1024 : 512; } -unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI) { return 256; } +unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI) { + const auto &Features = STI->getFeatureBits(); + if (Features.test(Feature1024AddressableVGPRs)) + return Features.test(FeatureWavefrontSize32) ? 1024 : 512; + return 256; +} unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI, unsigned DynamicVGPRBlockSize) { const auto &Features = STI->getFeatureBits(); - if (Features.test(FeatureGFX1250Insts)) - return Features.test(FeatureWavefrontSize32) ? 1024 : 512; if (Features.test(FeatureGFX90AInsts)) return 512;