From 7e661f6889d43475994b7073c4667ae3923bf6ff Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 14 Sep 2025 23:48:33 -0700 Subject: [PATCH] [LegalizeTypes] Use getShiftAmountConstant in PromoteIntRes_FunnelShift. --- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 354aeff0c60ea..ba424198ad5b7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -1613,7 +1613,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) { // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)). if (NewBits >= (2 * OldBits) && !isa(Amt) && !TLI.isOperationLegalOrCustom(Opcode, VT)) { - SDValue HiShift = DAG.getConstant(OldBits, DL, VT); + SDValue HiShift = DAG.getShiftAmountConstant(OldBits, VT, DL); Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, HiShift); Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT); SDValue Res = DAG.getNode(ISD::OR, DL, VT, Hi, Lo); @@ -1624,13 +1624,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) { } // Shift Lo up to occupy the upper bits of the promoted type. - SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, AmtVT); - Lo = DAG.getNode(ISD::SHL, DL, VT, Lo, ShiftOffset); + Lo = DAG.getNode(ISD::SHL, DL, VT, Lo, + DAG.getShiftAmountConstant(NewBits - OldBits, VT, DL)); // Increase Amount to shift the result into the lower bits of the promoted // type. if (IsFSHR) - Amt = DAG.getNode(ISD::ADD, DL, AmtVT, Amt, ShiftOffset); + Amt = DAG.getNode(ISD::ADD, DL, AmtVT, Amt, + DAG.getConstant(NewBits - OldBits, DL, VT)); return DAG.getNode(Opcode, DL, VT, Hi, Lo, Amt); }