From 65889829138b30ecb2768ecfd7d366d30a8e344f Mon Sep 17 00:00:00 2001 From: Kaushik Kulkarni Date: Thu, 22 May 2025 11:41:14 -0700 Subject: [PATCH 1/4] [Hexagon] Support lowering of setuo & seto for vector types in Hexagon Resolves instruction selection failure for v64f16 and v32f32 vector types. Patch by: Fateme Hosseini --- .../Target/Hexagon/HexagonISelLoweringHVX.cpp | 4 +++ .../test/CodeGen/Hexagon/inst_setcc_uno_uo.ll | 28 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index f1fa40c1b9036..4af8c6c6c34c2 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -355,6 +355,8 @@ HexagonTargetLowering::initializeHVXLowering() { setCondCodeAction(ISD::SETULE, MVT::v64f16, Expand); setCondCodeAction(ISD::SETUGE, MVT::v64f16, Expand); setCondCodeAction(ISD::SETULT, MVT::v64f16, Expand); + setCondCodeAction(ISD::SETUO, MVT::v64f16, Expand); + setCondCodeAction(ISD::SETO, MVT::v64f16, Expand); setCondCodeAction(ISD::SETNE, MVT::v32f32, Expand); setCondCodeAction(ISD::SETLE, MVT::v32f32, Expand); @@ -368,6 +370,8 @@ HexagonTargetLowering::initializeHVXLowering() { setCondCodeAction(ISD::SETULE, MVT::v32f32, Expand); setCondCodeAction(ISD::SETUGE, MVT::v32f32, Expand); setCondCodeAction(ISD::SETULT, MVT::v32f32, Expand); + setCondCodeAction(ISD::SETUO, MVT::v32f32, Expand); + setCondCodeAction(ISD::SETO, MVT::v32f32, Expand); // Boolean vectors. diff --git a/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll new file mode 100644 index 0000000000000..eeee12e86950f --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll @@ -0,0 +1,28 @@ +;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck %s + +define dso_local void @store_isnan_f32(ptr %a, ptr %isnan_a) local_unnamed_addr { +entry: + %arrayidx = getelementptr inbounds nuw float, ptr %a, i32 0 + %0 = load <32 x float>, ptr %arrayidx, align 4 + %.vectorized = fcmp uno <32 x float> %0, zeroinitializer + %.LS.instance = zext <32 x i1> %.vectorized to <32 x i32> + %arrayidx1 = getelementptr inbounds nuw i32, ptr %isnan_a, i32 0 + store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4 + ret void +} +;; CHECK: store_isnan_f32 +;; CHECK: vcmp.eq({{v[0-9]+.w}},{{v[0-9]+.w}}) + +define dso_local void @store_isnan_f16(ptr %a, ptr %isnan_a) local_unnamed_addr { +entry: + %arrayidx = getelementptr inbounds nuw half, ptr %a, i32 0 + %0 = load <64 x half>, ptr %arrayidx, align 2 + %.vectorized = fcmp uno <64 x half> %0, zeroinitializer + %conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16> + %arrayidx1 = getelementptr inbounds nuw i16, ptr %isnan_a, i32 0 + store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2 + ret void +} + +;; CHECK: store_isnan_f16 +;; CHECK: vcmp.eq({{v[0-9]+.h}},{{v[0-9]+.h}}) From deeed94abb08eba8020bfb736f528eb0e09f15c9 Mon Sep 17 00:00:00 2001 From: Fateme Hosseini Date: Tue, 16 Sep 2025 14:46:38 -0700 Subject: [PATCH 2/4] Add check for setO --- .../test/CodeGen/Hexagon/inst_setcc_uno_uo.ll | 54 +++++++++++++++++-- 1 file changed, 50 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll index eeee12e86950f..a28d4a6850a6c 100644 --- a/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll +++ b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll @@ -10,8 +10,14 @@ entry: store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4 ret void } -;; CHECK: store_isnan_f32 -;; CHECK: vcmp.eq({{v[0-9]+.w}},{{v[0-9]+.w}}) +; CHECK: store_isnan_f32 +; CHECK: [[VZERO32:v[0-9]+]] = vxor([[VZERO32]],[[VZERO32]]) +; CHECK: [[VLOAD32:v[0-9]+]] = vmemu(r0+#0) +; CHECK: [[VONES32:v[0-9]+]] = vsplat([[RONE32:r[0-9]+]]) +; CHECK: {{q[0-9]+}} = vcmp.eq([[VLOAD32]].w,[[VLOAD32]].w) +; CHECK: [[VOUT32:v[0-9]+]] = vmux({{q[0-9]+}},[[VZERO32]],[[VONES32]]) +; CHECK: vmemu(r1+#0) = [[VOUT32]] + define dso_local void @store_isnan_f16(ptr %a, ptr %isnan_a) local_unnamed_addr { entry: @@ -23,6 +29,46 @@ entry: store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2 ret void } +; CHECK: store_isnan_f16 +; CHECK: [[VZERO16:v[0-9]+]] = vxor([[VZERO16]],[[VZERO16]]) +; CHECK: [[VLOAD16:v[0-9]+]] = vmemu(r0+#0) +; CHECK: [[VONES16:v[0-9]+]].h = vsplat([[RONE16:r[0-9]+]]) +; CHECK: {{q[0-9]+}} = vcmp.eq([[VLOAD16]].h,[[VLOAD16]].h) +; CHECK: [[VOUT16:v[0-9]+]] = vmux({{q[0-9]+}},[[VZERO16]],[[VONES16]]) +; CHECK: vmemu(r1+#0) = [[VOUT16]] + +define dso_local void @store_isordered_f32(ptr %a, ptr %isordered_a) local_unnamed_addr { +entry: + %arrayidx = getelementptr inbounds nuw float, ptr %a, i32 0 + %0 = load <32 x float>, ptr %arrayidx, align 4 + %.vectorized = fcmp ord <32 x float> %0, zeroinitializer + %.LS.instance = zext <32 x i1> %.vectorized to <32 x i32> + %arrayidx1 = getelementptr inbounds nuw i32, ptr %isordered_a, i32 0 + store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4 + ret void +} +; CHECK: store_isordered_f32 +; CHECK: [[V_ZERO32:v[0-9]+]] = vxor([[V_ZERO32]],[[V_ZERO32]]) +; CHECK: [[V_LOAD32:v[0-9]+]] = vmemu(r0+#0) +; CHECK: [[V_ONES32:v[0-9]+]] = vsplat([[RO32:r[0-9]+]]) +; CHECK: {{q[0-9]+}} = vcmp.eq([[V_LOAD32]].w,[[V_LOAD32]].w) +; CHECK: [[V_OUT32:v[0-9]+]] = vmux({{q[0-9]+}},[[V_ONES32]],[[V_ZERO32]]) +; CHECK: vmemu(r1+#0) = [[V_OUT32]] -;; CHECK: store_isnan_f16 -;; CHECK: vcmp.eq({{v[0-9]+.h}},{{v[0-9]+.h}}) +define dso_local void @store_isordered_f16(ptr %a, ptr %isordered_a) local_unnamed_addr { +entry: + %arrayidx = getelementptr inbounds nuw half, ptr %a, i32 0 + %0 = load <64 x half>, ptr %arrayidx, align 2 + %.vectorized = fcmp ord <64 x half> %0, zeroinitializer + %conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16> + %arrayidx1 = getelementptr inbounds nuw i16, ptr %isordered_a, i32 0 + store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2 + ret void +} +; CHECK: store_isordered_f16 +; CHECK: [[V_ZERO16:v[0-9]+]] = vxor([[V_ZERO16]],[[V_ZERO16]]) +; CHECK: [[V_LOAD16:v[0-9]+]] = vmemu(r0+#0) +; CHECK: [[V_ONES16:v[0-9]+]].h = vsplat([[RO16:r[0-9]+]]) +; CHECK: {{q[0-9]+}} = vcmp.eq([[V_LOAD16]].h,[[V_LOAD16]].h) +; CHECK: [[V_OUT16:v[0-9]+]] = vmux({{q[0-9]+}},[[V_ONES16]],[[V_ZERO16]]) +; CHECK: vmemu(r1+#0) = [[V_OUT16]] From 6cd424a238b5adfb82e9df38b2f2e211567c61d7 Mon Sep 17 00:00:00 2001 From: Fateme Hosseini Date: Thu, 2 Oct 2025 13:44:49 -0700 Subject: [PATCH 3/4] add checks for second var as an operand --- .../test/CodeGen/Hexagon/inst_setcc_uno_uo.ll | 115 ++++++++++-------- 1 file changed, 67 insertions(+), 48 deletions(-) diff --git a/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll index a28d4a6850a6c..8b121c539229d 100644 --- a/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll +++ b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll @@ -1,74 +1,93 @@ ;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck %s -define dso_local void @store_isnan_f32(ptr %a, ptr %isnan_a) local_unnamed_addr { +define dso_local void @store_isnan_f32(ptr %a, ptr %b, ptr %isnan_cmp) local_unnamed_addr { entry: - %arrayidx = getelementptr inbounds nuw float, ptr %a, i32 0 - %0 = load <32 x float>, ptr %arrayidx, align 4 - %.vectorized = fcmp uno <32 x float> %0, zeroinitializer + %arrayidx_a = getelementptr inbounds nuw float, ptr %a, i32 0 + %arrayidx_b = getelementptr inbounds nuw float, ptr %b, i32 0 + %0 = load <32 x float>, ptr %arrayidx_a, align 4 + %1 = load <32 x float>, ptr %arrayidx_b, align 4 + %.vectorized = fcmp uno <32 x float> %0, %1 %.LS.instance = zext <32 x i1> %.vectorized to <32 x i32> - %arrayidx1 = getelementptr inbounds nuw i32, ptr %isnan_a, i32 0 + %arrayidx1 = getelementptr inbounds nuw i32, ptr %isnan_cmp, i32 0 store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4 ret void } -; CHECK: store_isnan_f32 -; CHECK: [[VZERO32:v[0-9]+]] = vxor([[VZERO32]],[[VZERO32]]) -; CHECK: [[VLOAD32:v[0-9]+]] = vmemu(r0+#0) -; CHECK: [[VONES32:v[0-9]+]] = vsplat([[RONE32:r[0-9]+]]) -; CHECK: {{q[0-9]+}} = vcmp.eq([[VLOAD32]].w,[[VLOAD32]].w) -; CHECK: [[VOUT32:v[0-9]+]] = vmux({{q[0-9]+}},[[VZERO32]],[[VONES32]]) -; CHECK: vmemu(r1+#0) = [[VOUT32]] +; CHECK: store_isnan_f32 +; CHECK: [[RONE32:r[0-9]+]] = #1 +; CHECK: [[VOP2_F32:v[0-9]+]] = vxor([[VOP2_F32]],[[VOP2_F32]]) +; CHECK: [[VOP1_F32:v[0-9]+]] = vmemu(r0+#0) +; CHECK: [[VONES32:v[0-9]+]] = vsplat([[RONE32]]) +; CHECK: [[Q1_F32:q[0-9]+]] = vcmp.eq([[VOP1_F32]].w,[[VOP1_F32]].w) +; CHECK: [[VOP3_F32:v[0-9]+]] = vmemu(r1+#0) +; CHECK: [[Q1_F32]] &= vcmp.eq([[VOP3_F32]].w,[[VOP3_F32]].w) +; CHECK: [[VOUT_F32:v[0-9]+]] = vmux([[Q1_F32]],[[VOP2_F32]],[[VONES32]]) +; CHECK: vmemu(r2+#0) = [[VOUT_F32]] -define dso_local void @store_isnan_f16(ptr %a, ptr %isnan_a) local_unnamed_addr { +define dso_local void @store_isnan_f16(ptr %a, ptr %b, ptr %isnan_cmp) local_unnamed_addr { entry: - %arrayidx = getelementptr inbounds nuw half, ptr %a, i32 0 - %0 = load <64 x half>, ptr %arrayidx, align 2 - %.vectorized = fcmp uno <64 x half> %0, zeroinitializer + %arrayidx_a = getelementptr inbounds nuw half, ptr %a, i32 0 + %arrayidx_b = getelementptr inbounds nuw half, ptr %b, i32 0 + %0 = load <64 x half>, ptr %arrayidx_a, align 2 + %1 = load <64 x half>, ptr %arrayidx_b, align 2 + %.vectorized = fcmp uno <64 x half> %0, %1 %conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16> - %arrayidx1 = getelementptr inbounds nuw i16, ptr %isnan_a, i32 0 + %arrayidx1 = getelementptr inbounds nuw i16, ptr %isnan_cmp, i32 0 store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2 ret void } -; CHECK: store_isnan_f16 -; CHECK: [[VZERO16:v[0-9]+]] = vxor([[VZERO16]],[[VZERO16]]) -; CHECK: [[VLOAD16:v[0-9]+]] = vmemu(r0+#0) -; CHECK: [[VONES16:v[0-9]+]].h = vsplat([[RONE16:r[0-9]+]]) -; CHECK: {{q[0-9]+}} = vcmp.eq([[VLOAD16]].h,[[VLOAD16]].h) -; CHECK: [[VOUT16:v[0-9]+]] = vmux({{q[0-9]+}},[[VZERO16]],[[VONES16]]) -; CHECK: vmemu(r1+#0) = [[VOUT16]] +; CHECK-LABEL: store_isnan_f16 +; CHECK: [[RONE16:r[0-9]+]] = #1 +; CHECK: [[VOP2_F16:v[0-9]+]] = vxor([[VOP2_F16]],[[VOP2_F16]]) +; CHECK: [[VOP1_F16:v[0-9]+]] = vmemu(r0+#0) +; CHECK: [[VONES16:v[0-9]+]].h = vsplat([[RONE16]]) +; CHECK: [[Q1_F16:q[0-9]+]] = vcmp.eq([[VOP1_F16]].h,[[VOP1_F16]].h) +; CHECK: [[VOP3_F16:v[0-9]+]] = vmemu(r1+#0) +; CHECK: [[Q1_F16]] &= vcmp.eq([[VOP3_F16]].h,[[VOP3_F16]].h) +; CHECK: [[VOUT_F16:v[0-9]+]] = vmux([[Q1_F16]],[[VOP2_F16]],[[VONES16]]) +; CHECK: vmemu(r2+#0) = [[VOUT_F32]] -define dso_local void @store_isordered_f32(ptr %a, ptr %isordered_a) local_unnamed_addr { +define dso_local void @store_isordered_f32(ptr %a, ptr %b, ptr %isordered_cmp) local_unnamed_addr { entry: - %arrayidx = getelementptr inbounds nuw float, ptr %a, i32 0 - %0 = load <32 x float>, ptr %arrayidx, align 4 - %.vectorized = fcmp ord <32 x float> %0, zeroinitializer + %arrayidx_a = getelementptr inbounds nuw float, ptr %a, i32 0 + %arrayidx_b = getelementptr inbounds nuw float, ptr %b, i32 0 + %0 = load <32 x float>, ptr %arrayidx_a, align 4 + %1 = load <32 x float>, ptr %arrayidx_b, align 4 + %.vectorized = fcmp ord <32 x float> %0, %1 %.LS.instance = zext <32 x i1> %.vectorized to <32 x i32> - %arrayidx1 = getelementptr inbounds nuw i32, ptr %isordered_a, i32 0 + %arrayidx1 = getelementptr inbounds nuw i32, ptr %isordered_cmp, i32 0 store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4 ret void } -; CHECK: store_isordered_f32 -; CHECK: [[V_ZERO32:v[0-9]+]] = vxor([[V_ZERO32]],[[V_ZERO32]]) -; CHECK: [[V_LOAD32:v[0-9]+]] = vmemu(r0+#0) -; CHECK: [[V_ONES32:v[0-9]+]] = vsplat([[RO32:r[0-9]+]]) -; CHECK: {{q[0-9]+}} = vcmp.eq([[V_LOAD32]].w,[[V_LOAD32]].w) -; CHECK: [[V_OUT32:v[0-9]+]] = vmux({{q[0-9]+}},[[V_ONES32]],[[V_ZERO32]]) -; CHECK: vmemu(r1+#0) = [[V_OUT32]] +; CHECK-LABEL: store_isordered_f32 +; CHECK: [[VOP2_ORD_F32:v[0-9]+]] = vxor([[VOP2_ORD_F32]],[[VOP2_ORD_F32]]) +; CHECK: [[VOP1_ORD_F32:v[0-9]+]] = vmemu(r0+#0) +; CHECK: [[VONES_ORD_F32:v[0-9]+]] = vsplat([[RONE32]]) +; CHECK: [[Q1_ORD_F32:q[0-9]+]] = vcmp.eq([[VOP1_ORD_F32]].w,[[VOP1_ORD_F32]].w) +; CHECK: [[VOP3_ORD_F32:v[0-9]+]] = vmemu(r1+#0) +; CHECK: [[Q1_ORD_F32]] &= vcmp.eq([[VOP3_ORD_F32]].w,[[VOP3_ORD_F32]].w) +; CHECK: [[VOUT_ORD_F32:v[0-9]+]] = vmux([[Q1_ORD_F32]],[[VONES_ORD_F32]],[[VOP2_ORD_F32]]) +; CHECK: vmemu(r2+#0) = [[VOUT_ORD_F32]] -define dso_local void @store_isordered_f16(ptr %a, ptr %isordered_a) local_unnamed_addr { + +define dso_local void @store_isordered_f16(ptr %a, ptr %b, ptr %isordered_cmp) local_unnamed_addr { entry: - %arrayidx = getelementptr inbounds nuw half, ptr %a, i32 0 - %0 = load <64 x half>, ptr %arrayidx, align 2 - %.vectorized = fcmp ord <64 x half> %0, zeroinitializer + %arrayidx_a = getelementptr inbounds nuw half, ptr %a, i32 0 + %arrayidx_b = getelementptr inbounds nuw half, ptr %b, i32 0 + %0 = load <64 x half>, ptr %arrayidx_a, align 2 + %1 = load <64 x half>, ptr %arrayidx_b, align 2 + %.vectorized = fcmp ord <64 x half> %0, %1 %conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16> - %arrayidx1 = getelementptr inbounds nuw i16, ptr %isordered_a, i32 0 + %arrayidx1 = getelementptr inbounds nuw i16, ptr %isordered_cmp, i32 0 store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2 ret void } -; CHECK: store_isordered_f16 -; CHECK: [[V_ZERO16:v[0-9]+]] = vxor([[V_ZERO16]],[[V_ZERO16]]) -; CHECK: [[V_LOAD16:v[0-9]+]] = vmemu(r0+#0) -; CHECK: [[V_ONES16:v[0-9]+]].h = vsplat([[RO16:r[0-9]+]]) -; CHECK: {{q[0-9]+}} = vcmp.eq([[V_LOAD16]].h,[[V_LOAD16]].h) -; CHECK: [[V_OUT16:v[0-9]+]] = vmux({{q[0-9]+}},[[V_ONES16]],[[V_ZERO16]]) -; CHECK: vmemu(r1+#0) = [[V_OUT16]] +; CHECK-LABEL: store_isordered_f16 +; CHECK: [[VOP2_ORD_F16:v[0-9]+]] = vxor([[VOP2_ORD_F16]],[[VOP2_ORD_F16]]) +; CHECK: [[VOP1_ORD_F16:v[0-9]+]] = vmemu(r0+#0) +; CHECK: [[VONES_ORD_F16:v[0-9]+]].h = vsplat([[RONE16]]) +; CHECK: [[Q1_ORD_F16:q[0-9]+]] = vcmp.eq([[VOP1_ORD_F16]].h,[[VOP1_ORD_F16]].h) +; CHECK: [[VOP3_ORD_F16:v[0-9]+]] = vmemu(r1+#0) +; CHECK: [[Q1_ORD_F16]] &= vcmp.eq([[VOP3_ORD_F16]].h,[[VOP3_ORD_F16]].h) +; CHECK: [[VOUT_ORD_F16:v[0-9]+]] = vmux([[Q1_ORD_F16]],[[VONES_ORD_F16]],[[VOP2_ORD_F16]]) +; CHECK: vmemu(r2+#0) = [[VOUT_ORD_F16]] From 59577193bdeeb89d5449b81a294a81e328c36bc2 Mon Sep 17 00:00:00 2001 From: Fateme Hosseini Date: Thu, 2 Oct 2025 14:28:21 -0700 Subject: [PATCH 4/4] clang-format --- llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 4af8c6c6c34c2..48918fa00ae07 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -355,8 +355,8 @@ HexagonTargetLowering::initializeHVXLowering() { setCondCodeAction(ISD::SETULE, MVT::v64f16, Expand); setCondCodeAction(ISD::SETUGE, MVT::v64f16, Expand); setCondCodeAction(ISD::SETULT, MVT::v64f16, Expand); - setCondCodeAction(ISD::SETUO, MVT::v64f16, Expand); - setCondCodeAction(ISD::SETO, MVT::v64f16, Expand); + setCondCodeAction(ISD::SETUO, MVT::v64f16, Expand); + setCondCodeAction(ISD::SETO, MVT::v64f16, Expand); setCondCodeAction(ISD::SETNE, MVT::v32f32, Expand); setCondCodeAction(ISD::SETLE, MVT::v32f32, Expand); @@ -370,8 +370,8 @@ HexagonTargetLowering::initializeHVXLowering() { setCondCodeAction(ISD::SETULE, MVT::v32f32, Expand); setCondCodeAction(ISD::SETUGE, MVT::v32f32, Expand); setCondCodeAction(ISD::SETULT, MVT::v32f32, Expand); - setCondCodeAction(ISD::SETUO, MVT::v32f32, Expand); - setCondCodeAction(ISD::SETO, MVT::v32f32, Expand); + setCondCodeAction(ISD::SETUO, MVT::v32f32, Expand); + setCondCodeAction(ISD::SETO, MVT::v32f32, Expand); // Boolean vectors.