From f072c08dac4d6f1fa65aaf1cf206ac3c634c9e3e Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Wed, 10 Sep 2025 23:07:53 -0700 Subject: [PATCH] [RISCV] Increase GPRPair Allocation Priority This echoes what has been done for the lmul>1 vector registers, increasing priority for pairs compared to single GPRs. The changes here are not particularly large, in part due to the fact that GPRPairs are not generated in many examples, but there look to be small savings in the number of register pair copies (where instead a GPR is copied). --- llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 4 +- llvm/test/CodeGen/RISCV/double-convert.ll | 80 ++++++------ llvm/test/CodeGen/RISCV/double-imm.ll | 10 +- .../CodeGen/RISCV/double-intrinsics-strict.ll | 14 +- llvm/test/CodeGen/RISCV/double-intrinsics.ll | 14 +- llvm/test/CodeGen/RISCV/double-mem.ll | 20 +-- .../CodeGen/RISCV/double-previous-failure.ll | 20 +-- .../CodeGen/RISCV/double-round-conv-sat.ll | 120 +++++++++--------- llvm/test/CodeGen/RISCV/zilsd.ll | 19 ++- 9 files changed, 150 insertions(+), 151 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 82e768d7c1d16..0b0868fe91c6f 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -358,7 +358,7 @@ let RegAltNameIndices = [ABIRegAltName] in { } } -let RegInfos = XLenPairRI, CopyCost = 2 in { +let RegInfos = XLenPairRI, CopyCost = 2, AllocationPriority = 1 in { def GPRPair : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add X10_X11, X12_X13, X14_X15, X16_X17, X6_X7, @@ -373,7 +373,7 @@ def GPRPairNoX0 : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (sub GPRPair def GPRPairC : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add X10_X11, X12_X13, X14_X15, X8_X9 )>; -} // let RegInfos = XLenPairRI, CopyCost = 2 +} // let RegInfos = XLenPairRI, CopyCost = 2, AllocationPriority = 1 //===----------------------------------------------------------------------===// // Floating Point registers diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll index 8124d00e63fa7..4b210bd80792b 100644 --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -729,13 +729,13 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI12_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI12_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI12_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI12_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI12_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI12_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) ; RV32IZFINXZDINX-NEXT: mv s1, a1 ; RV32IZFINXZDINX-NEXT: mv s0, a0 -; RV32IZFINXZDINX-NEXT: fle.d s2, a4, s0 +; RV32IZFINXZDINX-NEXT: fle.d s2, a2, s0 ; RV32IZFINXZDINX-NEXT: call __fixdfdi ; RV32IZFINXZDINX-NEXT: lui a3, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 @@ -981,15 +981,15 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: mv s1, a1 ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi -; RV32IZFINXZDINX-NEXT: fle.d a2, zero, s0 +; RV32IZFINXZDINX-NEXT: fle.d a4, zero, s0 ; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI14_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a3) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI14_0)(a3) ; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI14_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a3) -; RV32IZFINXZDINX-NEXT: neg a2, a2 -; RV32IZFINXZDINX-NEXT: and a0, a2, a0 -; RV32IZFINXZDINX-NEXT: and a1, a2, a1 -; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0 +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: neg a4, a4 +; RV32IZFINXZDINX-NEXT: and a0, a4, a0 +; RV32IZFINXZDINX-NEXT: and a1, a4, a1 +; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0 ; RV32IZFINXZDINX-NEXT: neg a2, a2 ; RV32IZFINXZDINX-NEXT: or a0, a2, a0 ; RV32IZFINXZDINX-NEXT: or a1, a2, a1 @@ -1650,17 +1650,17 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind { ; ; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i16: ; RV32IZFINXZDINX: # %bb.0: # %start -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI26_0) -; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI26_1) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI26_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) -; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_1)(a3) -; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI26_1) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI26_0) +; RV32IZFINXZDINX-NEXT: lui a5, %hi(.LCPI26_1) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI26_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI26_0) ; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI26_1)(a5) +; RV32IZFINXZDINX-NEXT: addi a5, a5, %lo(.LCPI26_1) +; RV32IZFINXZDINX-NEXT: lw a5, 4(a5) ; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0 -; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4 -; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2 +; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2 +; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz ; RV32IZFINXZDINX-NEXT: neg a1, a6 ; RV32IZFINXZDINX-NEXT: and a0, a1, a0 @@ -1848,12 +1848,12 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind { ; ; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i16: ; RV32IZFINXZDINX: # %bb.0: # %start -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI28_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI28_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI28_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI28_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI28_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI28_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) ; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, zero -; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4 +; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz ; RV32IZFINXZDINX-NEXT: ret ; @@ -2026,17 +2026,17 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind { ; ; RV32IZFINXZDINX-LABEL: fcvt_w_s_sat_i8: ; RV32IZFINXZDINX: # %bb.0: # %start -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI30_0) -; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI30_1) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI30_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) -; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_1)(a3) -; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI30_1) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI30_0) +; RV32IZFINXZDINX-NEXT: lui a5, %hi(.LCPI30_1) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI30_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI30_0) ; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI30_1)(a5) +; RV32IZFINXZDINX-NEXT: addi a5, a5, %lo(.LCPI30_1) +; RV32IZFINXZDINX-NEXT: lw a5, 4(a5) ; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0 -; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4 -; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2 +; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2 +; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4 ; RV32IZFINXZDINX-NEXT: fcvt.w.d a0, a0, rtz ; RV32IZFINXZDINX-NEXT: neg a1, a6 ; RV32IZFINXZDINX-NEXT: and a0, a1, a0 @@ -2224,12 +2224,12 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind { ; ; RV32IZFINXZDINX-LABEL: fcvt_wu_s_sat_i8: ; RV32IZFINXZDINX: # %bb.0: # %start -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI32_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI32_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI32_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI32_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI32_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI32_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) ; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, zero -; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4 +; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a2 ; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz ; RV32IZFINXZDINX-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/double-imm.ll b/llvm/test/CodeGen/RISCV/double-imm.ll index 1119fd6d74a25..209dbc1f671a5 100644 --- a/llvm/test/CodeGen/RISCV/double-imm.ll +++ b/llvm/test/CodeGen/RISCV/double-imm.ll @@ -54,11 +54,11 @@ define double @double_imm_op(double %a) nounwind { ; ; CHECKRV32ZDINX-LABEL: double_imm_op: ; CHECKRV32ZDINX: # %bb.0: -; CHECKRV32ZDINX-NEXT: lui a2, %hi(.LCPI1_0) -; CHECKRV32ZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2) -; CHECKRV32ZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0) -; CHECKRV32ZDINX-NEXT: lw a5, 4(a2) -; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a4 +; CHECKRV32ZDINX-NEXT: lui a3, %hi(.LCPI1_0) +; CHECKRV32ZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a3) +; CHECKRV32ZDINX-NEXT: addi a3, a3, %lo(.LCPI1_0) +; CHECKRV32ZDINX-NEXT: lw a3, 4(a3) +; CHECKRV32ZDINX-NEXT: fadd.d a0, a0, a2 ; CHECKRV32ZDINX-NEXT: ret ; ; CHECKRV64ZDINX-LABEL: double_imm_op: diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll b/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll index fddb86de58f51..0c2152965c235 100644 --- a/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll +++ b/llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll @@ -286,15 +286,15 @@ define double @sincos_f64(double %a) nounwind strictfp { ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: mv s0, a1 -; RV32IZFINXZDINX-NEXT: mv s1, a0 +; RV32IZFINXZDINX-NEXT: mv s2, a1 +; RV32IZFINXZDINX-NEXT: mv s3, a0 ; RV32IZFINXZDINX-NEXT: call sin -; RV32IZFINXZDINX-NEXT: mv s2, a0 -; RV32IZFINXZDINX-NEXT: mv s3, a1 -; RV32IZFINXZDINX-NEXT: mv a0, s1 -; RV32IZFINXZDINX-NEXT: mv a1, s0 +; RV32IZFINXZDINX-NEXT: mv s0, a0 +; RV32IZFINXZDINX-NEXT: mv s1, a1 +; RV32IZFINXZDINX-NEXT: mv a0, s3 +; RV32IZFINXZDINX-NEXT: mv a1, s2 ; RV32IZFINXZDINX-NEXT: call cos -; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0 +; RV32IZFINXZDINX-NEXT: fadd.d a0, s0, a0 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll index bb57665fa1801..8638f7ed4ceb8 100644 --- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll @@ -241,15 +241,15 @@ define double @sincos_f64(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: mv s0, a1 -; RV32IZFINXZDINX-NEXT: mv s1, a0 +; RV32IZFINXZDINX-NEXT: mv s2, a1 +; RV32IZFINXZDINX-NEXT: mv s3, a0 ; RV32IZFINXZDINX-NEXT: call sin -; RV32IZFINXZDINX-NEXT: mv s2, a0 -; RV32IZFINXZDINX-NEXT: mv s3, a1 -; RV32IZFINXZDINX-NEXT: mv a0, s1 -; RV32IZFINXZDINX-NEXT: mv a1, s0 +; RV32IZFINXZDINX-NEXT: mv s0, a0 +; RV32IZFINXZDINX-NEXT: mv s1, a1 +; RV32IZFINXZDINX-NEXT: mv a0, s3 +; RV32IZFINXZDINX-NEXT: mv a1, s2 ; RV32IZFINXZDINX-NEXT: call cos -; RV32IZFINXZDINX-NEXT: fadd.d a0, s2, a0 +; RV32IZFINXZDINX-NEXT: fadd.d a0, s0, a0 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 20(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll index 053688f79fe1c..d26b4271383f1 100644 --- a/llvm/test/CodeGen/RISCV/double-mem.ll +++ b/llvm/test/CodeGen/RISCV/double-mem.ll @@ -179,12 +179,12 @@ define dso_local double @fld_fsd_constant(double %a) nounwind { ; ; RV32IZFINXZDINX-LABEL: fld_fsd_constant: ; RV32IZFINXZDINX: # %bb.0: -; RV32IZFINXZDINX-NEXT: lui a2, 912092 -; RV32IZFINXZDINX-NEXT: lw a4, -273(a2) -; RV32IZFINXZDINX-NEXT: lw a5, -269(a2) -; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a4 -; RV32IZFINXZDINX-NEXT: sw a0, -273(a2) -; RV32IZFINXZDINX-NEXT: sw a1, -269(a2) +; RV32IZFINXZDINX-NEXT: lui a4, 912092 +; RV32IZFINXZDINX-NEXT: lw a2, -273(a4) +; RV32IZFINXZDINX-NEXT: lw a3, -269(a4) +; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2 +; RV32IZFINXZDINX-NEXT: sw a0, -273(a4) +; RV32IZFINXZDINX-NEXT: sw a1, -269(a4) ; RV32IZFINXZDINX-NEXT: ret ; ; RV64IZFINXZDINX-LABEL: fld_fsd_constant: @@ -198,10 +198,10 @@ define dso_local double @fld_fsd_constant(double %a) nounwind { ; ; RV32IZFINXZDINXZILSD-LABEL: fld_fsd_constant: ; RV32IZFINXZDINXZILSD: # %bb.0: -; RV32IZFINXZDINXZILSD-NEXT: lui a2, 912092 -; RV32IZFINXZDINXZILSD-NEXT: ld a4, -273(a2) -; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a4 -; RV32IZFINXZDINXZILSD-NEXT: sd a0, -273(a2) +; RV32IZFINXZDINXZILSD-NEXT: lui a4, 912092 +; RV32IZFINXZDINXZILSD-NEXT: ld a2, -273(a4) +; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a2 +; RV32IZFINXZDINXZILSD-NEXT: sd a0, -273(a4) ; RV32IZFINXZDINXZILSD-NEXT: ret %1 = inttoptr i32 3735928559 to ptr %2 = load volatile double, ptr %1 diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll index c0993faa9584a..f922052d8276e 100644 --- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll +++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll @@ -50,18 +50,18 @@ define i32 @main() nounwind { ; RV32IZFINXZDINX-NEXT: lui a1, 262144 ; RV32IZFINXZDINX-NEXT: li a0, 0 ; RV32IZFINXZDINX-NEXT: call test -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) -; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a4 +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI1_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI1_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: flt.d a2, a0, a2 ; RV32IZFINXZDINX-NEXT: bnez a2, .LBB1_3 ; RV32IZFINXZDINX-NEXT: # %bb.1: # %entry -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_1) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_1)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_1) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) -; RV32IZFINXZDINX-NEXT: flt.d a0, a4, a0 +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI1_1) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_1)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI1_1) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0 ; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_3 ; RV32IZFINXZDINX-NEXT: # %bb.2: # %if.end ; RV32IZFINXZDINX-NEXT: call exit diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll index a574e68671a74..ae8157b3edefa 100644 --- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll @@ -99,11 +99,11 @@ define i64 @test_floor_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 ; RV32IZFINXZDINX-NEXT: call __fixdfdi -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI1_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI1_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI1_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) -; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI1_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI1_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI1_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: fle.d a3, a2, s0 ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz a3, .LBB1_2 @@ -221,13 +221,13 @@ define i64 @test_floor_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call floor -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI3_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI3_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI3_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI3_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI3_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI3_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 -; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0 +; RV32IZFINXZDINX-NEXT: flt.d a0, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a0 ; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi @@ -348,11 +348,11 @@ define i64 @test_ceil_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 ; RV32IZFINXZDINX-NEXT: call __fixdfdi -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI5_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI5_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI5_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) -; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI5_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI5_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI5_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: fle.d a3, a2, s0 ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz a3, .LBB5_2 @@ -470,13 +470,13 @@ define i64 @test_ceil_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call ceil -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI7_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI7_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI7_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI7_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI7_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI7_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 -; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0 +; RV32IZFINXZDINX-NEXT: flt.d a0, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a0 ; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi @@ -597,11 +597,11 @@ define i64 @test_trunc_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 ; RV32IZFINXZDINX-NEXT: call __fixdfdi -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI9_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI9_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI9_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) -; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI9_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI9_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI9_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: fle.d a3, a2, s0 ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz a3, .LBB9_2 @@ -719,13 +719,13 @@ define i64 @test_trunc_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call trunc -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI11_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI11_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI11_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI11_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI11_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI11_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 -; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0 +; RV32IZFINXZDINX-NEXT: flt.d a0, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a0 ; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi @@ -846,11 +846,11 @@ define i64 @test_round_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 ; RV32IZFINXZDINX-NEXT: call __fixdfdi -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI13_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI13_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI13_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) -; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI13_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI13_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI13_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: fle.d a3, a2, s0 ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz a3, .LBB13_2 @@ -968,13 +968,13 @@ define i64 @test_round_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call round -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI15_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI15_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI15_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI15_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI15_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI15_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 -; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0 +; RV32IZFINXZDINX-NEXT: flt.d a0, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a0 ; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi @@ -1095,11 +1095,11 @@ define i64 @test_roundeven_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 ; RV32IZFINXZDINX-NEXT: call __fixdfdi -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI17_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI17_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI17_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) -; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI17_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI17_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI17_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: fle.d a3, a2, s0 ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz a3, .LBB17_2 @@ -1217,13 +1217,13 @@ define i64 @test_roundeven_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call roundeven -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI19_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI19_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI19_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI19_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI19_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI19_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 -; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0 +; RV32IZFINXZDINX-NEXT: flt.d a0, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a0 ; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi @@ -1344,11 +1344,11 @@ define i64 @test_rint_si64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 ; RV32IZFINXZDINX-NEXT: call __fixdfdi -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI21_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI21_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI21_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) -; RV32IZFINXZDINX-NEXT: fle.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI21_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI21_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI21_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) +; RV32IZFINXZDINX-NEXT: fle.d a3, a2, s0 ; RV32IZFINXZDINX-NEXT: lui a4, 524288 ; RV32IZFINXZDINX-NEXT: lui a2, 524288 ; RV32IZFINXZDINX-NEXT: beqz a3, .LBB21_2 @@ -1466,13 +1466,13 @@ define i64 @test_rint_ui64(double %x) nounwind { ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: call rint -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI23_0) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI23_0)(a2) -; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI23_0) -; RV32IZFINXZDINX-NEXT: lw a5, 4(a2) +; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI23_0) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI23_0)(a3) +; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI23_0) +; RV32IZFINXZDINX-NEXT: lw a3, 4(a3) ; RV32IZFINXZDINX-NEXT: mv s0, a0 ; RV32IZFINXZDINX-NEXT: mv s1, a1 -; RV32IZFINXZDINX-NEXT: flt.d a0, a4, s0 +; RV32IZFINXZDINX-NEXT: flt.d a0, a2, s0 ; RV32IZFINXZDINX-NEXT: neg s2, a0 ; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi diff --git a/llvm/test/CodeGen/RISCV/zilsd.ll b/llvm/test/CodeGen/RISCV/zilsd.ll index 048ce964f9e18..9e33ff36d0500 100644 --- a/llvm/test/CodeGen/RISCV/zilsd.ll +++ b/llvm/test/CodeGen/RISCV/zilsd.ll @@ -7,10 +7,9 @@ define i64 @load(ptr %a) nounwind { ; CHECK-LABEL: load: ; CHECK: # %bb.0: -; CHECK-NEXT: ld a2, 80(a0) -; CHECK-NEXT: ld zero, 0(a0) -; CHECK-NEXT: mv a0, a2 -; CHECK-NEXT: mv a1, a3 +; CHECK-NEXT: mv a2, a0 +; CHECK-NEXT: ld a0, 80(a0) +; CHECK-NEXT: ld zero, 0(a2) ; CHECK-NEXT: ret %1 = getelementptr i64, ptr %a, i32 10 %2 = load i64, ptr %1 @@ -122,12 +121,12 @@ define void @large_offset(ptr nocapture %p, i64 %d) nounwind { ; CHECK-LABEL: large_offset: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lui a1, 4 -; CHECK-NEXT: add a0, a0, a1 -; CHECK-NEXT: ld a2, -384(a0) -; CHECK-NEXT: addi a2, a2, 1 -; CHECK-NEXT: seqz a1, a2 -; CHECK-NEXT: add a3, a3, a1 -; CHECK-NEXT: sd a2, -384(a0) +; CHECK-NEXT: add a2, a0, a1 +; CHECK-NEXT: ld a0, -384(a2) +; CHECK-NEXT: addi a0, a0, 1 +; CHECK-NEXT: seqz a3, a0 +; CHECK-NEXT: add a1, a1, a3 +; CHECK-NEXT: sd a0, -384(a2) ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i64, ptr %p, i64 2000