From 0700dddc2628645d217d85a7787f414d8a42b9a7 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 17 Sep 2025 15:06:47 +0900 Subject: [PATCH 1/2] GlobalISel: Relax verifier between physreg and typed vreg Accept mismatched register size and type size if the type is legal for the register class. For AMDGPU boolean registers have 2 possible interpretations depending on the use context type. e.g., these are both equally valid: %0:_(s1) = COPY $vcc %1:_(s64) = COPY $vcc vcc is a 64-bit register, which can be interpreted as a 1-bit or 64-bit value depending on the use context. SelectionDAG has never required exact match between the register size and the used value type. You can assign a type with a smaller size to a larger register class. Relax the verifier to match. There are several hacks holding together these copies in various places, and this is preparation to remove one of them. The x86 test change is from what I would consider an X86 usage bug. X86 defines an FR32 register class and F16 register class, but the F16 register class is functionally an alias of F32 with the same members and size. There's no need to have the F16 class. --- llvm/lib/CodeGen/MachineVerifier.cpp | 16 +++-- .../AMDGPU/test_copy_physregs_llt_virtreg.mir | 58 +++++++++++++++++++ .../test_copy_physregs_x86.mir | 32 ++++------ 3 files changed, 80 insertions(+), 26 deletions(-) create mode 100644 llvm/test/MachineVerifier/AMDGPU/test_copy_physregs_llt_virtreg.mir diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 2b24fe49c970b..e911ce8a75828 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -2376,20 +2376,24 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { // If we have only one valid type, this is likely a copy between a virtual // and physical register. - TypeSize SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI); - TypeSize DstSize = TRI->getRegSizeInBits(DstReg, *MRI); + TypeSize SrcSize = TypeSize::getZero(); + TypeSize DstSize = TypeSize::getZero(); if (SrcReg.isPhysical() && DstTy.isValid()) { const TargetRegisterClass *SrcRC = TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy); - if (SrcRC) - SrcSize = TRI->getRegSizeInBits(*SrcRC); + if (!SrcRC) + SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI); + } else { + SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI); } if (DstReg.isPhysical() && SrcTy.isValid()) { const TargetRegisterClass *DstRC = TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy); - if (DstRC) - DstSize = TRI->getRegSizeInBits(*DstRC); + if (!DstRC) + DstSize = TRI->getRegSizeInBits(DstReg, *MRI); + } else { + DstSize = TRI->getRegSizeInBits(DstReg, *MRI); } // The next two checks allow COPY between physical and virtual registers, diff --git a/llvm/test/MachineVerifier/AMDGPU/test_copy_physregs_llt_virtreg.mir b/llvm/test/MachineVerifier/AMDGPU/test_copy_physregs_llt_virtreg.mir new file mode 100644 index 0000000000000..0fd50391a7e3a --- /dev/null +++ b/llvm/test/MachineVerifier/AMDGPU/test_copy_physregs_llt_virtreg.mir @@ -0,0 +1,58 @@ +# RUN: not --crash llc -mtriple=amdgcn -run-pass=none -filetype=null %s 2>&1 | FileCheck -implicit-check-not="Bad machine code" %s + +--- +name: test_valid_copies +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0, $vcc + %0:_(s32) = COPY $vgpr0 + %1:_(s16) = COPY $vgpr0 + %2:_(s64) = COPY $vcc + %3:_(s1) = COPY $vcc + $vgpr0 = COPY %0 + $vgpr0 = COPY %0 + $vcc = COPY %2 + $vcc = COPY %3 +... + +--- +name: test_invalid_copies +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2, $vcc + + ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** + ; CHECK: - instruction: %0:_(s32) = COPY $vgpr0_vgpr1 + %0:_(s32) = COPY $vgpr0_vgpr1 + + ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** + ; CHECK: - instruction: %1:_(s64) = COPY $vgpr2 + %1:_(s64) = COPY $vgpr2 + + ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** + ; CHECK: - instruction: %2:_(s32) = COPY $vcc + %2:_(s32) = COPY $vcc + + ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** + ; CHECK: - instruction: %3:_(s8) = COPY $vgpr2 + %3:_(s8) = COPY $vgpr2 + + ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** + ; CHECK: - instruction: $vgpr0_vgpr1 = COPY %0:_(s32) + $vgpr0_vgpr1 = COPY %0 + + ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** + ; CHECK: - instruction: $vgpr2 = COPY %1:_(s64) + $vgpr2 = COPY %1 + + ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** + ; CHECK: - instruction: $vcc = COPY %2:_(s32) + $vcc = COPY %2 + + ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** + ; CHECK: - instruction: $vgpr2 = COPY %3:_(s8) + $vgpr2 = COPY %3 + +... diff --git a/llvm/test/MachineVerifier/test_copy_physregs_x86.mir b/llvm/test/MachineVerifier/test_copy_physregs_x86.mir index a239379a34e62..f3323c4353142 100644 --- a/llvm/test/MachineVerifier/test_copy_physregs_x86.mir +++ b/llvm/test/MachineVerifier/test_copy_physregs_x86.mir @@ -29,34 +29,26 @@ body: | liveins: $xmm0, $xmm1, $xmm2, $xmm3 ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** - ; CHECK: - instruction: %0:_(s16) = COPY $xmm0 - %0:_(s16) = COPY $xmm0 + ; CHECK: - instruction: %0:_(<4 x s16>) = COPY $xmm1 + %0:_(<4 x s16>) = COPY $xmm1 ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** - ; CHECK: - instruction: %1:_(<4 x s16>) = COPY $xmm1 - %1:_(<4 x s16>) = COPY $xmm1 + ; CHECK: - instruction: %1:_(s256) = COPY $xmm2 + %1:_(s256) = COPY $xmm2 ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** - ; CHECK: - instruction: %2:_(s256) = COPY $xmm2 - %2:_(s256) = COPY $xmm2 + ; CHECK: - instruction: %2:_(<8 x s32>) = COPY $xmm3 + %2:_(<8 x s32>) = COPY $xmm3 ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** - ; CHECK: - instruction: %3:_(<8 x s32>) = COPY $xmm3 - %3:_(<8 x s32>) = COPY $xmm3 + ; CHECK: - instruction: $xmm1 = COPY %0:_(<4 x s16>) + $xmm1 = COPY %0 ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** - ; CHECK: - instruction: $xmm0 = COPY %0:_(s16) - $xmm0 = COPY %0 - - ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** - ; CHECK: - instruction: $xmm1 = COPY %1:_(<4 x s16>) - $xmm1 = COPY %1 + ; CHECK: - instruction: $xmm2 = COPY %1:_(s256) + $xmm2 = COPY %1 ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** - ; CHECK: - instruction: $xmm2 = COPY %2:_(s256) - $xmm2 = COPY %2 - - ; CHECK: *** Bad machine code: Copy Instruction is illegal with mismatching sizes *** - ; CHECK: - instruction: $xmm3 = COPY %3:_(<8 x s32>) - $xmm3 = COPY %3 + ; CHECK: - instruction: $xmm3 = COPY %2:_(<8 x s32>) + $xmm3 = COPY %2 ... From 1926bc3a5b45c5ff39fae40809e61fa4b4b9f662 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 17 Sep 2025 16:46:22 +0900 Subject: [PATCH 2/2] AMDGPU: Fixes for regbankselecting copies of i1 physregs to sgprs If the source register of a copy was a physical sgpr copied to an s1 value, this would assert. --- .../Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 14 +- .../AMDGPU/GlobalISel/regbankselect-copy.mir | 324 ++++++++++++++++-- 2 files changed, 296 insertions(+), 42 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index a74d56f0a6781..848d9a5a9eb98 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -3845,21 +3845,27 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { // want the most straightforward mapping, so just directly handle this. const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI); const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI); - assert(SrcBank && "src bank should have been assigned already"); // For COPY between a physical reg and an s1, there is no type associated so // we need to take the virtual register's type as a hint on how to interpret // s1 values. + unsigned Size; if (!SrcReg.isVirtual() && !DstBank && - MRI.getType(DstReg) == LLT::scalar(1)) + MRI.getType(DstReg) == LLT::scalar(1)) { DstBank = &AMDGPU::VCCRegBank; - else if (!DstReg.isVirtual() && MRI.getType(SrcReg) == LLT::scalar(1)) + Size = 1; + } else if (!DstReg.isVirtual() && MRI.getType(SrcReg) == LLT::scalar(1)) { DstBank = &AMDGPU::VCCRegBank; + Size = 1; + } else { + Size = getSizeInBits(DstReg, MRI, *TRI); + } if (!DstBank) DstBank = SrcBank; + else if (!SrcBank) + SrcBank = DstBank; - unsigned Size = getSizeInBits(DstReg, MRI, *TRI); if (MI.getOpcode() != AMDGPU::G_FREEZE && cannotCopy(*DstBank, *SrcBank, TypeSize::getFixed(Size))) return getInvalidInstructionMapping(); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir index bf8f2d633c1dc..fce3805712794 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir @@ -16,6 +16,12 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32) + ; + ; WAVE32-LABEL: name: copy_s32_vgpr_to_vgpr + ; WAVE32: liveins: $vgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE32-NEXT: $vgpr0 = COPY [[COPY]](s32) %0:_(s32) = COPY $vgpr0 $vgpr0 = COPY %0 @@ -33,6 +39,12 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK-NEXT: $sgpr0 = COPY [[COPY]](s32) + ; + ; WAVE32-LABEL: name: copy_s32_sgpr_to_sgpr + ; WAVE32: liveins: $sgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; WAVE32-NEXT: $sgpr0 = COPY [[COPY]](s32) %0:_(s32) = COPY $sgpr0 $sgpr0 = COPY %0 @@ -50,6 +62,12 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32) + ; + ; WAVE32-LABEL: name: copy_s32_sgpr_to_vgpr + ; WAVE32: liveins: $sgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; WAVE32-NEXT: $vgpr0 = COPY [[COPY]](s32) %0:_(s32) = COPY $sgpr0 $vgpr0 = COPY %0 @@ -67,6 +85,12 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK-NEXT: $agpr0 = COPY [[COPY]](s32) + ; + ; WAVE32-LABEL: name: copy_s32_vgpr_to_agpr + ; WAVE32: liveins: $vgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE32-NEXT: $agpr0 = COPY [[COPY]](s32) %0:_(s32) = COPY $vgpr0 $agpr0 = COPY %0 @@ -84,6 +108,12 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; CHECK-NEXT: $agpr0 = COPY [[COPY]](s32) + ; + ; WAVE32-LABEL: name: copy_s32_sgpr_to_agpr + ; WAVE32: liveins: $sgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; WAVE32-NEXT: $agpr0 = COPY [[COPY]](s32) %0:_(s32) = COPY $sgpr0 $agpr0 = COPY %0 @@ -101,6 +131,12 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0 ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32) + ; + ; WAVE32-LABEL: name: copy_s32_agpr_to_vgpr + ; WAVE32: liveins: $agpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0 + ; WAVE32-NEXT: $vgpr0 = COPY [[COPY]](s32) %0:_(s32) = COPY $agpr0 $vgpr0 = COPY %0 @@ -118,6 +154,12 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0 ; CHECK-NEXT: $agpr0 = COPY [[COPY]](s32) + ; + ; WAVE32-LABEL: name: copy_s32_agpr_to_agpr + ; WAVE32: liveins: $agpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:agpr(s32) = COPY $agpr0 + ; WAVE32-NEXT: $agpr0 = COPY [[COPY]](s32) %0:_(s32) = COPY $agpr0 $agpr0 = COPY %0 @@ -137,6 +179,14 @@ body: | ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]](s1) + ; + ; WAVE32-LABEL: name: copy_s1_sgpr_to_vcc_preassigned + ; WAVE32: liveins: $sgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; WAVE32-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](s1) %0:sgpr(s32) = COPY $sgpr0 %1:sgpr(s1) = G_TRUNC %0 %2:vcc(s1) = COPY %1 @@ -157,6 +207,14 @@ body: | ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]](s1) + ; + ; WAVE32-LABEL: name: copy_s1_vgpr_to_vcc_preassigned + ; WAVE32: liveins: $vgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE32-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](s1) %0:vgpr(s32) = COPY $vgpr0 %1:vgpr(s1) = G_TRUNC %0 %2:vcc(s1) = COPY %1 @@ -177,6 +235,14 @@ body: | ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]](s1) + ; + ; WAVE32-LABEL: name: copy_s1_sgpr_to_vcc + ; WAVE32: liveins: $sgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; WAVE32-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32) + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](s1) %0:_(s32) = COPY $sgpr0 %1:_(s1) = G_TRUNC %0 %2:vcc(s1) = COPY %1 @@ -198,6 +264,14 @@ body: | ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]](s1) + ; + ; WAVE32-LABEL: name: copy_s1_vgpr_to_vcc + ; WAVE32: liveins: $vgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE32-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]](s1) %0:_(s32) = COPY $vgpr0 %1:_(s1) = G_TRUNC %0 %2:vcc(s1) = COPY %1 @@ -215,9 +289,17 @@ body: | ; CHECK: liveins: $sgpr4_sgpr5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5 - ; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[CONST1]], [[CONST2]] + ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] + ; + ; WAVE32-LABEL: name: wave64_copy_sgpr_64_to_s1 + ; WAVE32: liveins: $sgpr4_sgpr5 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5 + ; WAVE32-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; WAVE32-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; WAVE32-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] %0:_(s1) = COPY $sgpr4_sgpr5 %1:_(s32) = G_ZEXT %0:_(s1) ... @@ -229,13 +311,21 @@ legalized: true body: | bb.0: liveins: $sgpr0 + ; CHECK-LABEL: name: wave32_copy_sgpr_32_to_s1 + ; CHECK: liveins: $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] + ; ; WAVE32-LABEL: name: wave32_copy_sgpr_32_to_s1 ; WAVE32: liveins: $sgpr0 ; WAVE32-NEXT: {{ $}} ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr0 - ; WAVE32-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 - ; WAVE32-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 - ; WAVE32-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[CONST1]], [[CONST2]] + ; WAVE32-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; WAVE32-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; WAVE32-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] %0:_(s1) = COPY $sgpr0 %1:_(s32) = G_ZEXT %0:_(s1) ... @@ -250,14 +340,26 @@ body: | ; CHECK-LABEL: name: wave64_copy2_sgpr_64_to_s1 ; CHECK: liveins: $sgpr4_sgpr5, $sgpr6_sgpr7 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5 - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY $sgpr6_sgpr7 - ; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY1]](s1), [[CONST1]], [[CONST2]] - ; CHECK-NEXT: [[CONST3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[CONST4:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[CONST3]], [[CONST4]] + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY $sgpr6_sgpr7 + ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY1]](s1), [[C2]], [[C3]] + ; + ; WAVE32-LABEL: name: wave64_copy2_sgpr_64_to_s1 + ; WAVE32: liveins: $sgpr4_sgpr5, $sgpr6_sgpr7 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5 + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY $sgpr6_sgpr7 + ; WAVE32-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; WAVE32-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; WAVE32-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] + ; WAVE32-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; WAVE32-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; WAVE32-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY1]](s1), [[C2]], [[C3]] %0:_(s1) = COPY $sgpr4_sgpr5 %1:_(s1) = COPY $sgpr6_sgpr7 %2:_(s32) = G_ZEXT %0:_(s1) @@ -271,17 +373,29 @@ legalized: true body: | bb.0: liveins: $sgpr0, $sgpr1 + ; CHECK-LABEL: name: wave32_copy2_sgpr_32_to_s1 + ; CHECK: liveins: $sgpr0, $sgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY $sgpr1 + ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] + ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY1]](s1), [[C2]], [[C3]] + ; ; WAVE32-LABEL: name: wave32_copy2_sgpr_32_to_s1 ; WAVE32: liveins: $sgpr0, $sgpr1 ; WAVE32-NEXT: {{ $}} - ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY $sgpr0 - ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY $sgpr1 - ; WAVE32-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 - ; WAVE32-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 - ; WAVE32-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY1]](s1), [[CONST1]], [[CONST2]] - ; WAVE32-NEXT: [[CONST3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 - ; WAVE32-NEXT: [[CONST4:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 - ; WAVE32-NEXT: [[SELECT2:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[CONST3]], [[CONST4]] + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr0 + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY $sgpr1 + ; WAVE32-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; WAVE32-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; WAVE32-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] + ; WAVE32-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; WAVE32-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; WAVE32-NEXT: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY1]](s1), [[C2]], [[C3]] %0:_(s1) = COPY $sgpr0 %1:_(s1) = COPY $sgpr1 %2:_(s32) = G_ZEXT %0:_(s1) @@ -343,9 +457,17 @@ body: | ; CHECK: liveins: $sgpr4_sgpr5 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5 - ; CHECK-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 - ; CHECK-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 - ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[CONST1]], [[CONST2]] + ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] + ; + ; WAVE32-LABEL: name: wave64_copy_sgpr_64_to_s1_vcc + ; WAVE32: liveins: $sgpr4_sgpr5 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5 + ; WAVE32-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; WAVE32-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; WAVE32-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] %0:vcc(s1) = COPY $sgpr4_sgpr5 %1:_(s32) = G_ZEXT %0:vcc(s1) ... @@ -357,13 +479,21 @@ legalized: true body: | bb.0: liveins: $sgpr0 + ; CHECK-LABEL: name: wave32_copy_sgpr_32_to_s1_vcc + ; CHECK: liveins: $sgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] + ; ; WAVE32-LABEL: name: wave32_copy_sgpr_32_to_s1_vcc ; WAVE32: liveins: $sgpr0 ; WAVE32-NEXT: {{ $}} ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr0 - ; WAVE32-NEXT: [[CONST1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 - ; WAVE32-NEXT: [[CONST2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 - ; WAVE32-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[CONST1]], [[CONST2]] + ; WAVE32-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1 + ; WAVE32-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0 + ; WAVE32-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY]](s1), [[C]], [[C1]] %0:vcc(s1) = COPY $sgpr0 %1:_(s32) = G_ZEXT %0:vcc(s1) ... @@ -380,14 +510,14 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s1) = COPY [[TRUNC]](s1) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s1) = COPY [[TRUNC]](s1) ; ; WAVE32-LABEL: name: copy_virt_reg_to_s1 ; WAVE32: liveins: $vgpr0 ; WAVE32-NEXT: {{ $}} ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; WAVE32-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) - ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:vgpr(s1) = COPY [[TRUNC]](s1) + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr(s1) = COPY [[TRUNC]](s1) %0:_(s32) = COPY $vgpr0 %1:_(s1) = G_TRUNC %0 %2:_(s1) = COPY %1 @@ -405,16 +535,16 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s1) = COPY [[TRUNC]](s1) - ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s1) = COPY [[COPY2]](s1) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s1) = COPY [[TRUNC]](s1) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s1) = COPY [[COPY1]](s1) ; ; WAVE32-LABEL: name: copy_virt_reg_to_s1_vgpr ; WAVE32: liveins: $vgpr0 ; WAVE32-NEXT: {{ $}} ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; WAVE32-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) - ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:vgpr(s1) = COPY [[TRUNC]](s1) - ; WAVE32-NEXT: [[COPY3:%[0-9]+]]:vgpr(s1) = COPY [[COPY2]](s1) + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr(s1) = COPY [[TRUNC]](s1) + ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:vgpr(s1) = COPY [[COPY1]](s1) %0:_(s32) = COPY $vgpr0 %1:_(s1) = G_TRUNC %0 %2:vgpr(s1) = COPY %1 @@ -434,16 +564,16 @@ body: | ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[COPY2]](s1) + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[COPY1]](s1) ; ; WAVE32-LABEL: name: copy_virt_reg_to_s1_vcc ; WAVE32: liveins: $vgpr0 ; WAVE32-NEXT: {{ $}} ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 ; WAVE32-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32) - ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) - ; WAVE32-NEXT: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[COPY2]](s1) + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1) + ; WAVE32-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[COPY1]](s1) %0:_(s32) = COPY $vgpr0 %1:_(s1) = G_TRUNC %0 %2:vcc(s1) = COPY %1 @@ -499,3 +629,121 @@ body: | %1:_(s1) = G_TRUNC %0 $sgpr0 = COPY %1 ... + +--- +name: copy_sgpr_physreg_to_vcc_s1_wave64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr4_sgpr5 + + ; CHECK-LABEL: name: copy_sgpr_physreg_to_vcc_s1_wave64 + ; CHECK: liveins: $sgpr4_sgpr5 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5 + ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]](s1) + ; + ; WAVE32-LABEL: name: copy_sgpr_physreg_to_vcc_s1_wave64 + ; WAVE32: liveins: $sgpr4_sgpr5 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4_sgpr5 + ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY]](s1) + %0:_(s1) = COPY $sgpr4_sgpr5 + S_ENDPGM 0, implicit %0 + +... + +--- +name: copy_vcc_s1_to_sgpr_physreg_wave64 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: copy_vcc_s1_to_sgpr_physreg_wave64 + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $sgpr4_sgpr5 = COPY [[ICMP]](s1) + ; CHECK-NEXT: S_ENDPGM 0, implicit $sgpr4_sgpr5 + ; + ; WAVE32-LABEL: name: copy_vcc_s1_to_sgpr_physreg_wave64 + ; WAVE32: liveins: $vgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; WAVE32-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] + ; WAVE32-NEXT: $sgpr4_sgpr5 = COPY [[ICMP]](s1) + ; WAVE32-NEXT: S_ENDPGM 0, implicit $sgpr4_sgpr5 + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s1) = G_ICMP intpred(eq), %0, %1 + $sgpr4_sgpr5 = COPY %2 + S_ENDPGM 0, implicit $sgpr4_sgpr5 + +... + +--- +name: copy_sgpr_physreg_to_vcc_s1_wave32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr4 + + ; CHECK-LABEL: name: copy_sgpr_physreg_to_vcc_s1_wave32 + ; CHECK: liveins: $sgpr4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4 + ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]](s1) + ; + ; WAVE32-LABEL: name: copy_sgpr_physreg_to_vcc_s1_wave32 + ; WAVE32: liveins: $sgpr4 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY $sgpr4 + ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY]](s1) + %0:_(s1) = COPY $sgpr4 + S_ENDPGM 0, implicit %0 + +... + +--- +name: copy_vcc_s1_to_sgpr_physreg_wave32 +legalized: true +tracksRegLiveness: true +body: | + bb.0: + liveins: $vgpr0 + + ; CHECK-LABEL: name: copy_vcc_s1_to_sgpr_physreg_wave32 + ; CHECK: liveins: $vgpr0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] + ; CHECK-NEXT: $sgpr4 = COPY [[ICMP]](s1) + ; CHECK-NEXT: S_ENDPGM 0, implicit $sgpr4 + ; + ; WAVE32-LABEL: name: copy_vcc_s1_to_sgpr_physreg_wave32 + ; WAVE32: liveins: $vgpr0 + ; WAVE32-NEXT: {{ $}} + ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; WAVE32-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 + ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32) + ; WAVE32-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]] + ; WAVE32-NEXT: $sgpr4 = COPY [[ICMP]](s1) + ; WAVE32-NEXT: S_ENDPGM 0, implicit $sgpr4 + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = G_CONSTANT i32 0 + %2:_(s1) = G_ICMP intpred(eq), %0, %1 + $sgpr4 = COPY %2 + S_ENDPGM 0, implicit $sgpr4 + +...