From 7a444177b306139835c307cc05b44c2cdeea81e2 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 17 Sep 2025 21:51:49 +0900
Subject: [PATCH] AMDGPU: Set RegTupleAlignUnits on _Lo256_Align2 class

---
 llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
index 4e1876db41d3d..8f1dd6244f20d 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td
@@ -1025,7 +1025,9 @@ multiclass VRegClass<int numRegs, list<ValueType> regTypes, dag regList> {
 
     // Aligned register tuples starting with low 256 vgprs
     def _Lo256_Align2 : VRegClassBase<numRegs, regTypes,
-        (trunc (decimate regList, 2), !div(!sub(258, numRegs), 2))>;
+        (trunc (decimate regList, 2), !div(!sub(258, numRegs), 2))> {
+      let RegTupleAlignUnits = 2;
+     }
   }
 }