From 5bb542f2d7e615337cc15a0a3c3d6256138946a2 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 17 Sep 2025 13:27:34 -0700 Subject: [PATCH] [AMDGPU] Update documentation about DWARF registers mapping. NFC --- llvm/docs/AMDGPUUsage.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 26dd6cc243f34..edabdc595a1f0 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -2964,12 +2964,9 @@ mapping. 1088-1129 SGPR64-SGPR105 32 Scalar General Purpose Registers. 1130-1535 *Reserved* *Reserved for future Scalar General Purpose Registers.* - 1536-1791 VGPR0-VGPR255 32*32 Vector General Purpose Registers + 1536-2047 VGPR0-VGPR511 32*32 Vector General Purpose Registers when executing in wavefront 32 mode. - 1792-2047 *Reserved* *Reserved for future Vector - General Purpose Registers when - executing in wavefront 32 mode.* 2048-2303 AGPR0-AGPR255 32*32 Vector Accumulation Registers when executing in wavefront 32 mode. @@ -2988,6 +2985,9 @@ mapping. 3328-3583 *Reserved* *Reserved for future Vector Accumulation Registers when executing in wavefront 64 mode.* + 3584-4095 VGPR512-VGPR1023 32*32 Second Block of Vector General + Purpose Registers When executing + in wavefront 32 mode ============== ================= ======== ================================== The vector registers are represented as the full size for the wavefront. They