From 24b7e3daf41dbfcdfdd1d470b9c719a1ff914939 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 18 Sep 2025 10:55:58 +0900 Subject: [PATCH] AMDGPU: Remove unnecessary AGPR legalize logic The manual legalizeOperands code only need to consider cases that require full instruction context to know if the operand is legal. This does not need to handle basic operand register class constraints. --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index a737ad98c1d80..3847a73b0a497 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -6371,13 +6371,6 @@ void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI, return; } - // No VOP2 instructions support AGPRs. - if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg())) - legalizeOpWithMove(MI, Src0Idx); - - if (Src1.isReg() && RI.isAGPR(MRI, Src1.getReg())) - legalizeOpWithMove(MI, Src1Idx); - // Special case: V_FMAC_F32 and V_FMAC_F16 have src2. if (Opc == AMDGPU::V_FMAC_F32_e32 || Opc == AMDGPU::V_FMAC_F16_e32) { int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2); @@ -6518,12 +6511,6 @@ void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI, continue; } - if (RI.hasAGPRs(RI.getRegClassForReg(MRI, MO.getReg())) && - !isOperandLegal(MI, Idx, &MO)) { - legalizeOpWithMove(MI, Idx); - continue; - } - if (!RI.isSGPRClass(RI.getRegClassForReg(MRI, MO.getReg()))) continue; // VGPRs are legal