From 210d6e3a23c76477e57edad9a98d73abab2eaa79 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke@igalia.com>
Date: Fri, 19 Sep 2025 01:44:07 +0800
Subject: [PATCH] [RISCV] Ignore debug instructions in RISCVVLOptimizer

Don't put them onto the worklist, since they'll crash when we try to check their opcode.

Fixes #159422
---
 llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 3 ++-
 llvm/test/CodeGen/RISCV/rvv/vl-opt.mir     | 8 ++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index a1134663c0e7a..96ad5c680e383 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1665,7 +1665,8 @@ bool RISCVVLOptimizer::runOnMachineFunction(MachineFunction &MF) {
   for (MachineBasicBlock *MBB : post_order(&MF)) {
     assert(MDT->isReachableFromEntry(MBB));
     for (MachineInstr &MI : reverse(*MBB))
-      Worklist.insert(&MI);
+      if (!MI.isDebugInstr())
+        Worklist.insert(&MI);
   }
 
   while (!Worklist.empty()) {
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index 9174b98de0aa9..4d6d0e122b1cf 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -770,3 +770,11 @@ body: |
   bb.2:
     PseudoVSE8_V_M1 %inc, $noreg, %avl2, 3 /* e8 */
 ...
+---
+name: dbg_value
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: dbg_value
+    ; CHECK: DBG_VALUE %0:vr
+    DBG_VALUE %0:vr
+...