diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp index 0e0c4547c751e..a29421acfed31 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp @@ -2815,6 +2815,49 @@ static bool generateVectorLoadStoreInst(const SPIRV::IncomingCall *Call, return true; } +static bool generateAFPInst(const SPIRV::IncomingCall *Call, + MachineIRBuilder &MIRBuilder, + SPIRVGlobalRegistry *GR) { + const auto *Builtin = Call->Builtin; + auto *MRI = MIRBuilder.getMRI(); + unsigned Opcode = + SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; + const Type *RetTy = GR->getTypeForSPIRVType(Call->ReturnType); + bool IsVoid = RetTy->isVoidTy(); + auto MIB = MIRBuilder.buildInstr(Opcode); + Register DestReg; + if (IsVoid) { + LLT PtrTy = MRI->getType(Call->Arguments[0]); + DestReg = MRI->createGenericVirtualRegister(PtrTy); + MRI->setRegClass(DestReg, &SPIRV::pIDRegClass); + SPIRVType *PointeeTy = + GR->getPointeeType(GR->getSPIRVTypeForVReg(Call->Arguments[0])); + MIB.addDef(DestReg); + MIB.addUse(GR->getSPIRVTypeID(PointeeTy)); + } else { + MIB.addDef(Call->ReturnRegister); + MIB.addUse(GR->getSPIRVTypeID(Call->ReturnType)); + } + for (unsigned i = IsVoid ? 1 : 0; i < Call->Arguments.size(); ++i) { + Register Arg = Call->Arguments[i]; + MachineInstr *DefMI = MRI->getUniqueVRegDef(Arg); + if (DefMI->getOpcode() == TargetOpcode::G_CONSTANT && + DefMI->getOperand(1).isCImm()) { + MIB.addImm(getConstFromIntrinsic(Arg, MRI)); + } else { + MIB.addUse(Arg); + } + } + if (IsVoid) { + LLT PtrTy = MRI->getType(Call->Arguments[0]); + MachineMemOperand *MMO = MIRBuilder.getMF().getMachineMemOperand( + MachinePointerInfo(), MachineMemOperand::MOStore, + PtrTy.getSizeInBytes(), Align(4)); + MIRBuilder.buildStore(DestReg, Call->Arguments[0], *MMO); + } + return true; +} + static bool generateLoadStoreInst(const SPIRV::IncomingCall *Call, MachineIRBuilder &MIRBuilder, SPIRVGlobalRegistry *GR) { @@ -3017,6 +3060,8 @@ std::optional lowerBuiltin(const StringRef DemangledCall, return generateTernaryBitwiseFunctionINTELInst(Call.get(), MIRBuilder, GR); case SPIRV::Block2DLoadStore: return generate2DBlockIOINTELInst(Call.get(), MIRBuilder, GR); + case SPIRV::ArbitraryFloatingPoint: + return generateAFPInst(Call.get(), MIRBuilder, GR); case SPIRV::Pipe: return generatePipeInst(Call.get(), MIRBuilder, GR); } diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td index 2a8deb6bf498b..f74e7ef239216 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td @@ -69,6 +69,7 @@ def ExtendedBitOps : BuiltinGroup; def BindlessINTEL : BuiltinGroup; def TernaryBitwiseINTEL : BuiltinGroup; def Block2DLoadStore : BuiltinGroup; +def ArbitraryFloatingPoint: BuiltinGroup; def Pipe : BuiltinGroup; //===----------------------------------------------------------------------===// @@ -737,6 +738,49 @@ defm : DemangledNativeBuiltin<"__spirv_CooperativeMatrixStoreCheckedINTEL", Open defm : DemangledNativeBuiltin<"__spirv_CooperativeMatrixConstructCheckedINTEL", OpenCL_std, CoopMatr, 5, 5, OpCooperativeMatrixConstructCheckedINTEL>; defm : DemangledNativeBuiltin<"__spirv_CooperativeMatrixGetElementCoordINTEL", OpenCL_std, CoopMatr, 2, 2, OpCooperativeMatrixGetElementCoordINTEL>; +// Arbitrary Precision Floating Point builtin records: +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatGTINTEL", OpenCL_std, ArbitraryFloatingPoint, 4, 4, OpArbitraryFloatGTINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatGEINTEL", OpenCL_std, ArbitraryFloatingPoint, 4, 4, OpArbitraryFloatGEINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLTINTEL", OpenCL_std, ArbitraryFloatingPoint, 4, 4, OpArbitraryFloatLTINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLEINTEL", OpenCL_std, ArbitraryFloatingPoint, 4, 4, OpArbitraryFloatLEINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatEQINTEL", OpenCL_std, ArbitraryFloatingPoint, 4, 4, OpArbitraryFloatEQINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatRecipINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatRecipINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCbrtINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCbrtINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatHypotINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatHypotINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSqrtINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatSqrtINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLogINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatLogINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLog2INTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatLog2INTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLog10INTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatLog10INTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatLog1pINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatLog1pINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatExpINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatExpINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatExp2INTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatExp2INTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatExp10INTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatExp10INTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatExpm1INTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatExpm1INTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSinINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatSinINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCosINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCosINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSinCosINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatSinCosINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSinPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatSinPiINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCosPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCosPiINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSinCosPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatSinCosPiINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatAddINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatAddINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatSubINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatSubINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatMulINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatMulINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatDivINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatDivINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatRSqrtINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatRSqrtINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatASinINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatASinINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatASinPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatASinPiINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatACosINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatACosINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatACosPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatACosPiINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatATanINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatATanINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatATanPiINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatATanPiINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatATan2INTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatATan2INTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatPowINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatPowINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatPowRINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatPowRINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatPowNINTEL", OpenCL_std, ArbitraryFloatingPoint, 8, 8, OpArbitraryFloatPowNINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCastINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCastINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCastFromIntINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCastFromIntINTEL>; +defm : DemangledNativeBuiltin<"__spirv_ArbitraryFloatCastToIntINTEL", OpenCL_std, ArbitraryFloatingPoint, 6, 6, OpArbitraryFloatCastToIntINTEL>; + // SPV_INTEL_bindless_images builtin records: defm : DemangledNativeBuiltin<"__spirv_ConvertHandleToImageINTEL", OpenCL_std, BindlessINTEL, 1, 1, OpConvertHandleToImageINTEL>; defm : DemangledNativeBuiltin<"__spirv_ConvertHandleToSamplerINTEL", OpenCL_std, BindlessINTEL, 1, 1, OpConvertHandleToSamplerINTEL>; diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp index 85ea9e156cb97..ee2a2a8cc596c 100644 --- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp @@ -53,6 +53,9 @@ static const std::map> SPIRV::Extension::Extension::SPV_GOOGLE_user_type}, {"SPV_INTEL_arbitrary_precision_integers", SPIRV::Extension::Extension::SPV_INTEL_arbitrary_precision_integers}, + {"SPV_INTEL_arbitrary_precision_floating_point", + SPIRV::Extension::Extension:: + SPV_INTEL_arbitrary_precision_floating_point}, {"SPV_INTEL_cache_controls", SPIRV::Extension::Extension::SPV_INTEL_cache_controls}, {"SPV_INTEL_float_controls2", diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td index 1723bfb639189..fa6239d17ea8f 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td +++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td @@ -971,6 +971,109 @@ def OpAliasScopeListDeclINTEL: Op<5913, (outs ID:$res), (ins variable_ops), def OpBitwiseFunctionINTEL: Op<6242, (outs ID:$res), (ins TYPE:$type, ID:$a, ID:$b, ID:$c, ID:$lut_index), "$res = OpBitwiseFunctionINTEL $type $a $b $c $lut_index">; +// SPV_INTEL_arbitrary_precision_floating_point +def OpArbitraryFloatGTINTEL: Op<5850, (outs ID:$res), (ins TYPE:$type, ID:$A, i32imm:$Ma , ID:$B, i32imm:$Mb), + "$res = OpArbitraryFloatGTINTEL $type $A $Ma $B $Mb">; +def OpArbitraryFloatGEINTEL: Op<5851, (outs ID:$res), (ins TYPE:$type, ID:$A, i32imm:$Ma , ID:$B, i32imm:$Mb), + "$res = OpArbitraryFloatGEINTEL $type $A $Ma $B $Mb">; +def OpArbitraryFloatLTINTEL: Op<5852, (outs ID:$res), (ins TYPE:$type, ID:$A, i32imm:$Ma , ID:$B, i32imm:$Mb), + "$res = OpArbitraryFloatLTINTEL $type $A $Ma $B $Mb">; +def OpArbitraryFloatLEINTEL: Op<5853, (outs ID:$res), (ins TYPE:$type, ID:$A, i32imm:$Ma , ID:$B, i32imm:$Mb), + "$res = OpArbitraryFloatLEINTEL $type $A $Ma $B $Mb">; +def OpArbitraryFloatEQINTEL: Op<5854, (outs ID:$res), (ins TYPE:$type, ID:$A, i32imm:$Ma , ID:$B, i32imm:$Mb), + "$res = OpArbitraryFloatEQINTEL $type $A $Ma $B $Mb">; +def OpArbitraryFloatRecipINTEL: Op<5855, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatRecipINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatCbrtINTEL: Op<5857, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatCbrtINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatHypotINTEL: Op<5858, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, ID:$B, i32imm:$Mb, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatHypotINTEL $type $A $Ma $B $Mb $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatSqrtINTEL: Op<5859, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatSqrtINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatLogINTEL: Op<5860, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatLogINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatLog2INTEL: Op<5861, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatLog2INTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatLog10INTEL: Op<5862, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatLog10INTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatLog1pINTEL: Op<5863, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatLog1pINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatExpINTEL: Op<5864, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatExpINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatExp2INTEL: Op<5865, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatExp2INTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatExp10INTEL: Op<5866, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatExp10INTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatExpm1INTEL: Op<5867, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatExpm1INTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatSinINTEL: Op<5868, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatSinINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatCosINTEL: Op<5869, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatCosINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatSinCosINTEL: Op<5870, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatSinCosINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatSinPiINTEL: Op<5871, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatSinPiINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatCosPiINTEL: Op<5872, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatCosPiINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatSinCosPiINTEL: Op<5840, (outs ID:$res), + (ins TYPE:$type, ID:$A, i32imm:$Ma, i32imm:$Mresult, i32imm:$subnormalMode, i32imm:$RoundingMode, i32imm:$RoundingAccuracy), + "$res = OpArbitraryFloatSinCosPiINTEL $type $A $Ma $Mresult $subnormalMode $RoundingMode $RoundingAccuracy">; +def OpArbitraryFloatAddINTEL: Op<5846, (outs ID:$res), + (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatAddINTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatSubINTEL: Op<5847, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatSubINTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatMulINTEL: Op<5848, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatMulINTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatDivINTEL: Op<5849, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatDivINTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatRSqrtINTEL: Op<5856, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatRSqrtINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatASinINTEL: Op<5873, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatASinINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatASinPiINTEL: Op<5874, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatASinPiINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatACosINTEL : Op<5875, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatACosINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatACosPiINTEL: Op<5876, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatACosPiINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatATanINTEL: Op<5877, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatATanINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatATanPiINTEL: Op<5878, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatATanPiINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatATan2INTEL: Op<5879, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatATan2INTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatPowINTEL: Op<5880, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i32imm:$src2_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatPowINTEL $type $src $src_mwidth $src2 $src2_mwidth $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatPowRINTEL: Op<5881, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i1imm:$src2_sign, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatPowRINTEL $type $src $src_mwidth $src2 $src2_sign $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatPowNINTEL: Op<5882, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, ID:$src2, i1imm:$src2_sign, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundaccuracymode), + "$res = OpArbitraryFloatPowNINTEL $type $src $src_mwidth $src2 $src2_sign $res_mwidth $subnorm $fproundingmode $roundaccuracymode">; +def OpArbitraryFloatCastINTEL: Op<5841, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$src_mwidth, i32imm:$res_mwidth, i32imm:$subnorm, i32imm:$fproundingmode, i32imm:$roundignAccuracy), + "$res = OpArbitraryFloatCastINTEL $type $src $src_mwidth $res_mwidth $subnorm $fproundingmode $roundignAccuracy">; +def OpArbitraryFloatCastFromIntINTEL: Op<5842, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$res_mwidth, i32imm:$fromsign, i32imm:$subnormalmode, i32imm:$fproundingmode, i32imm:$roundignAccuracy), + "$res = OpArbitraryFloatCastFromIntINTEL $type $src $res_mwidth $fromsign $subnormalmode $fproundingmode $roundignAccuracy">; +def OpArbitraryFloatCastToIntINTEL: Op<5838, (outs ID:$res), (ins TYPE:$type, ID:$src, i32imm:$res_mwidth, i32imm:$tosign, i32imm:$subnormalmode, i32imm:$fproundingmode, i32imm:$roundignAccuracy), + "$res = OpArbitraryFloatCastToIntINTEL $type $src $res_mwidth $tosign $subnormalmode $fproundingmode $roundignAccuracy">; + // SPV_INTEL_2d_block_io def OpSubgroup2DBlockLoadINTEL: Op<6231, (outs), (ins ID:$element_size, ID:$block_width, ID:$block_height, ID:$block_count, ID:$src_base_ptr, ID:$memory_width, ID:$memory_height, ID:$memory_pitch, ID:$coord, ID:$dst_ptr), diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index dc717a6ca5870..9a62db4140083 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -2005,6 +2005,58 @@ void addInstrRequirements(const MachineInstr &MI, Reqs.addCapability(SPIRV::Capability::LongCompositesINTEL); break; } + case SPIRV::OpArbitraryFloatEQINTEL: + case SPIRV::OpArbitraryFloatGEINTEL: + case SPIRV::OpArbitraryFloatGTINTEL: + case SPIRV::OpArbitraryFloatLEINTEL: + case SPIRV::OpArbitraryFloatLTINTEL: + case SPIRV::OpArbitraryFloatCbrtINTEL: + case SPIRV::OpArbitraryFloatCosINTEL: + case SPIRV::OpArbitraryFloatCosPiINTEL: + case SPIRV::OpArbitraryFloatExp10INTEL: + case SPIRV::OpArbitraryFloatExp2INTEL: + case SPIRV::OpArbitraryFloatExpINTEL: + case SPIRV::OpArbitraryFloatExpm1INTEL: + case SPIRV::OpArbitraryFloatHypotINTEL: + case SPIRV::OpArbitraryFloatLog10INTEL: + case SPIRV::OpArbitraryFloatLog1pINTEL: + case SPIRV::OpArbitraryFloatLog2INTEL: + case SPIRV::OpArbitraryFloatLogINTEL: + case SPIRV::OpArbitraryFloatRecipINTEL: + case SPIRV::OpArbitraryFloatSinCosINTEL: + case SPIRV::OpArbitraryFloatSinCosPiINTEL: + case SPIRV::OpArbitraryFloatSinINTEL: + case SPIRV::OpArbitraryFloatSinPiINTEL: + case SPIRV::OpArbitraryFloatSqrtINTEL: + case SPIRV::OpArbitraryFloatACosINTEL: + case SPIRV::OpArbitraryFloatACosPiINTEL: + case SPIRV::OpArbitraryFloatAddINTEL: + case SPIRV::OpArbitraryFloatASinINTEL: + case SPIRV::OpArbitraryFloatASinPiINTEL: + case SPIRV::OpArbitraryFloatATan2INTEL: + case SPIRV::OpArbitraryFloatATanINTEL: + case SPIRV::OpArbitraryFloatATanPiINTEL: + case SPIRV::OpArbitraryFloatCastFromIntINTEL: + case SPIRV::OpArbitraryFloatCastINTEL: + case SPIRV::OpArbitraryFloatCastToIntINTEL: + case SPIRV::OpArbitraryFloatDivINTEL: + case SPIRV::OpArbitraryFloatMulINTEL: + case SPIRV::OpArbitraryFloatPowINTEL: + case SPIRV::OpArbitraryFloatPowNINTEL: + case SPIRV::OpArbitraryFloatPowRINTEL: + case SPIRV::OpArbitraryFloatRSqrtINTEL: + case SPIRV::OpArbitraryFloatSubINTEL: { + if (!ST.canUseExtension( + SPIRV::Extension::SPV_INTEL_arbitrary_precision_floating_point)) + report_fatal_error( + "Floating point instructions can't be translated correctly without " + "enabled SPV_INTEL_arbitrary_precision_floating_point extension!", + false); + Reqs.addExtension( + SPIRV::Extension::SPV_INTEL_arbitrary_precision_floating_point); + Reqs.addCapability(SPIRV::Capability::ArbitraryPrecisionFloatingPointINTEL); + break; + } case SPIRV::OpSubgroupMatrixMultiplyAccumulateINTEL: { if (!ST.canUseExtension( SPIRV::Extension::SPV_INTEL_subgroup_matrix_multiply_accumulate)) diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td index 6a32dbabff3d3..494337c808079 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td +++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td @@ -384,6 +384,7 @@ defm SPV_INTEL_2d_block_io : ExtensionOperand<122, [EnvOpenCL]>; defm SPV_INTEL_int4 : ExtensionOperand<123, [EnvOpenCL]>; defm SPV_KHR_float_controls2 : ExtensionOperand<124, [EnvVulkan, EnvOpenCL]>; defm SPV_INTEL_tensor_float32_conversion : ExtensionOperand<125, [EnvOpenCL]>; +defm SPV_INTEL_arbitrary_precision_floating_point: ExtensionOperand<127, [EnvOpenCL]>; defm SPV_KHR_bfloat16 : ExtensionOperand<126, [EnvVulkan, EnvOpenCL]>; //===----------------------------------------------------------------------===// @@ -597,6 +598,7 @@ defm Subgroup2DBlockTransposeINTEL : CapabilityOperand<6230, 0, 0, [SPV_INTEL_2d defm Int4TypeINTEL : CapabilityOperand<5112, 0, 0, [SPV_INTEL_int4], []>; defm Int4CooperativeMatrixINTEL : CapabilityOperand<5114, 0, 0, [SPV_INTEL_int4], [Int4TypeINTEL, CooperativeMatrixKHR]>; defm TensorFloat32RoundingINTEL : CapabilityOperand<6425, 0, 0, [SPV_INTEL_tensor_float32_conversion], []>; +defm ArbitraryPrecisionFloatingPointINTEL : CapabilityOperand<5845, 0, 0,[SPV_INTEL_arbitrary_precision_floating_point], []>; defm BFloat16TypeKHR : CapabilityOperand<5116, 0, 0, [SPV_KHR_bfloat16], []>; defm BFloat16DotProductKHR : CapabilityOperand<5117, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR]>; defm BFloat16CooperativeMatrixKHR : CapabilityOperand<5118, 0, 0, [SPV_KHR_bfloat16], [BFloat16TypeKHR, CooperativeMatrixKHR]>; diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_floating_point/arbitrary_precision_floating_point_test.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_floating_point/arbitrary_precision_floating_point_test.ll new file mode 100644 index 0000000000000..baf8fbd1f0336 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_floating_point/arbitrary_precision_floating_point_test.ll @@ -0,0 +1,127 @@ +; RUN: llc -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_floating_point,+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s +; TODO: %if spirv-tools %{ llc -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_floating_point,+SPV_INTEL_arbitrary_precision_integers %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Kernel +; CHECK: OpCapability ArbitraryPrecisionFloatingPointINTEL +; CHECK: OpCapability ArbitraryPrecisionIntegersINTEL +; CHECK: OpExtension "SPV_INTEL_arbitrary_precision_floating_point" +; CHECK: OpExtension "SPV_INTEL_arbitrary_precision_integers" + +; CHECK-DAG: OpTypeInt 4 0 +; CHECK-DAG: OpTypeInt 50 0 +; CHECK-DAG: OpTypeInt 56 0 +; CHECK-DAG: OpTypeInt 59 0 +; CHECK-DAG: OpTypeInt 5 0 +; CHECK-DAG: OpTypeInt 8 0 +; CHECK-DAG: OpTypeInt 10 0 +; CHECK-DAG: OpTypeInt 11 0 +; CHECK-DAG: OpTypeInt 13 0 +; CHECK-DAG: OpTypeInt 14 0 +; CHECK-DAG: OpTypeInt 15 0 +; CHECK-DAG: OpTypeInt 21 0 +; CHECK-DAG: OpTypeInt 25 0 +; CHECK-DAG: OpTypeInt 27 0 +; CHECK-DAG: OpTypeInt 34 0 +; CHECK-DAG: OpTypeInt 35 0 +; CHECK-DAG: OpTypeInt 38 0 +; CHECK-DAG: OpTypeInt 42 0 +; CHECK-DAG: OpTypeInt 44 0 +; CHECK-DAG: OpTypeInt 49 0 +; CHECK-DAG: OpTypeInt 62 0 +; CHECK-DAG: OpTypeInt 64 0 +; CHECK-DAG: OpTypeBool + +; CHECK: OpLabel +; CHECK: OpArbitraryFloatLogINTEL +; CHECK: OpArbitraryFloatLog2INTEL +; CHECK: OpArbitraryFloatLog10INTEL +; CHECK: OpArbitraryFloatLog1pINTEL +; CHECK: OpArbitraryFloatExpINTEL +; CHECK: OpArbitraryFloatExp2INTEL +; CHECK: OpArbitraryFloatExp10INTEL +; CHECK: OpArbitraryFloatExpm1INTEL +; CHECK: OpArbitraryFloatSinINTEL +; CHECK: OpArbitraryFloatCosINTEL +; CHECK: OpArbitraryFloatSinCosINTEL +; CHECK: OpArbitraryFloatSinPiINTEL +; CHECK: OpArbitraryFloatCosPiINTEL +; CHECK: OpArbitraryFloatSinCosPiINTEL +; CHECK: OpArbitraryFloatASinINTEL +; CHECK: OpArbitraryFloatASinPiINTEL +; CHECK: OpArbitraryFloatACosINTEL +; CHECK: OpArbitraryFloatACosPiINTEL +; CHECK: OpArbitraryFloatATanINTEL +; CHECK: OpArbitraryFloatATanPiINTEL +; CHECK: OpArbitraryFloatATan2INTEL +; CHECK: OpArbitraryFloatPowINTEL +; CHECK: OpArbitraryFloatPowRINTEL +; CHECK: OpArbitraryFloatPowNINTEL +; CHECK: OpArbitraryFloatPowNINTEL + +define dso_local spir_kernel void @_ZTSZ4mainE15kernel_function() { +entry: + %0 = alloca i64, align 8 + %1 = alloca i64, align 8 + %2 = alloca i8, align 1 + call spir_func void @ap_float_ops(i64* %0, i64* %1, i8* %2) + ret void +} + +define internal spir_func void @ap_float_ops(i64* %in1, i64* %in2, i8* %out) { +entry: + %0 = load i64, ptr %in1, align 8 + %1 = load i64, ptr %in2, align 8 + %log = call spir_func i50 @_Z30__spirv_ArbitraryFloatLogINTELILi50ELi50EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i64 %0, i32 19, i32 30, i32 0, i32 2, i32 1) + %log2 = call spir_func i38 @_Z31__spirv_ArbitraryFloatLog2INTELILi38ELi38EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i50 %log, i32 20, i32 19, i32 0, i32 2, i32 1) + %log10 = call spir_func signext i10 @_Z32__spirv_ArbitraryFloatLog10INTELILi8ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i38 %log2, i32 3, i32 5, i32 0, i32 2, i32 1) + %log1p = call spir_func i49 @_Z32__spirv_ArbitraryFloatLog1pINTELILi48ELi49EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i50 %log, i32 30, i32 30, i32 0, i32 2, i32 1) + %exp = call spir_func i42 @_Z30__spirv_ArbitraryFloatExpINTELILi42ELi42EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i49 %log1p, i32 25, i32 25, i32 0, i32 2, i32 1) + %exp2 = call spir_func signext i5 @_Z31__spirv_ArbitraryFloatExp2INTELILi3ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i10 %log10, i32 1, i32 2, i32 0, i32 2, i32 1) + %exp10 = call spir_func signext i25 @_Z32__spirv_ArbitraryFloatExp10INTELILi25ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i42 %exp, i32 16, i32 16, i32 0, i32 2, i32 1) + %expm1 = call spir_func i62 @_Z32__spirv_ArbitraryFloatExpm1INTELILi64ELi62EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i64 %0, i32 42, i32 41, i32 0, i32 2, i32 1) + %sin = call spir_func i34 @_Z30__spirv_ArbitraryFloatSinINTELILi30ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i25 %exp10, i32 15, i32 17, i32 0, i32 2, i32 1) + %cos = call spir_func signext i4 @_Z30__spirv_ArbitraryFloatCosINTELILi4ELi4EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i5 %exp2, i32 2, i32 1, i32 0, i32 2, i32 1) + %sincos = call spir_func i62 @_Z33__spirv_ArbitraryFloatSinCosINTELILi27ELi31EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEiiiiii(i34 %sin, i32 18, i32 20, i32 0, i32 2, i32 1) + %sinpi = call spir_func signext i13 @_Z32__spirv_ArbitraryFloatSinPiINTELILi10ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i10 %log10, i32 6, i32 6, i32 0, i32 2, i32 1) + %cospi = call spir_func i59 @_Z32__spirv_ArbitraryFloatCosPiINTELILi59ELi59EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i62 %expm1, i32 40, i32 40, i32 0, i32 2, i32 1) + %sincospi = call spir_func i64 @_Z35__spirv_ArbitraryFloatSinCosPiINTELILi30ELi32EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEiiiiii(i34 %sin, i32 20, i32 20, i32 0, i32 2, i32 1) + %asin = call spir_func signext i11 @_Z31__spirv_ArbitraryFloatASinINTELILi7ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i4 %cos, i32 4, i32 8, i32 0, i32 2, i32 1) + %asinpi = call spir_func i35 @_Z33__spirv_ArbitraryFloatASinPiINTELILi35ELi35EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i49 %log1p, i32 23, i32 23, i32 0, i32 2, i32 1) + %acos = call spir_func signext i14 @_Z31__spirv_ArbitraryFloatACosINTELILi14ELi14EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i13 %sinpi, i32 9, i32 10, i32 0, i32 2, i32 1) + %acospi = call spir_func signext i8 @_Z33__spirv_ArbitraryFloatACosPiINTELILi8ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i38 %log2, i32 5, i32 4, i32 0, i32 2, i32 1) + %atan = call spir_func i44 @_Z31__spirv_ArbitraryFloatATanINTELILi44ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i59 %cospi, i32 31, i32 31, i32 0, i32 2, i32 1) + %atanpi = call spir_func i34 @_Z33__spirv_ArbitraryFloatATanPiINTELILi40ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i50 %log, i32 38, i32 32, i32 0, i32 2, i32 1) + %atan2 = call spir_func signext i27 @_Z32__spirv_ArbitraryFloatATan2INTELILi24ELi25ELi27EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i25 %exp10, i32 16, i42 %exp, i32 17, i32 18, i32 0, i32 2, i32 1) + %pow = call spir_func signext i21 @_Z30__spirv_ArbitraryFloatPowINTELILi17ELi19ELi21EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i34 %sin, i32 8, i38 %log2, i32 9, i32 10, i32 0, i32 2, i32 1) + %powr = call spir_func i56 @_Z31__spirv_ArbitraryFloatPowRINTELILi54ELi55ELi56EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i59 %cospi, i32 35, i49 %log1p, i32 35, i32 35, i32 0, i32 2, i32 1) + %pown = call spir_func signext i15 @_Z31__spirv_ArbitraryFloatPowNINTELILi12ELi10ELi15EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiii(i14 %acos, i32 7, i10 %log10, i1 zeroext false, i32 9, i32 0, i32 2, i32 1) + %pown2 = call spir_func signext i15 @_Z31__spirv_ArbitraryFloatPowNINTELILi64ELi10ELi15EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiii(i64 %0, i32 7, i10 %log10, i1 zeroext true, i32 9, i32 0, i32 2, i32 1) + %final = trunc i15 %pown2 to i8 + store i8 %final, ptr %out, align 1 + ret void +} +declare dso_local spir_func i50 @_Z30__spirv_ArbitraryFloatLogINTELILi50ELi50EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i50, i32, i32, i32, i32, i32) +declare dso_local spir_func i38 @_Z31__spirv_ArbitraryFloatLog2INTELILi38ELi38EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i50, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i10 @_Z32__spirv_ArbitraryFloatLog10INTELILi8ELi10EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i38 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func i49 @_Z32__spirv_ArbitraryFloatLog1pINTELILi48ELi49EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i50, i32, i32, i32, i32, i32) +declare dso_local spir_func i42 @_Z30__spirv_ArbitraryFloatExpINTELILi42ELi42EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i42, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i5 @_Z31__spirv_ArbitraryFloatExp2INTELILi3ELi5EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i10 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i25 @_Z32__spirv_ArbitraryFloatExp10INTELILi25ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i42 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func i62 @_Z32__spirv_ArbitraryFloatExpm1INTELILi64ELi62EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i64, i32, i32, i32, i32, i32) +declare dso_local spir_func i34 @_Z30__spirv_ArbitraryFloatSinINTELILi30ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i25 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i4 @_Z30__spirv_ArbitraryFloatCosINTELILi4ELi4EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i5 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func i62 @_Z33__spirv_ArbitraryFloatSinCosINTELILi27ELi31EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEiiiiii(i34 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i13 @_Z32__spirv_ArbitraryFloatSinPiINTELILi10ELi13EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i10 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func i59 @_Z32__spirv_ArbitraryFloatCosPiINTELILi59ELi59EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i62, i32, i32, i32, i32, i32) +declare dso_local spir_func i64 @_Z35__spirv_ArbitraryFloatSinCosPiINTELILi30ELi32EEU7_ExtIntIXmlLi2ET0_EEiU7_ExtIntIXT_EEiiiiii(i34 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i11 @_Z31__spirv_ArbitraryFloatASinINTELILi7ELi11EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i4 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func i35 @_Z33__spirv_ArbitraryFloatASinPiINTELILi35ELi35EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i49, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i14 @_Z31__spirv_ArbitraryFloatACosINTELILi14ELi14EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i13 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i8 @_Z33__spirv_ArbitraryFloatACosPiINTELILi8ELi8EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i38 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func i44 @_Z31__spirv_ArbitraryFloatATanINTELILi44ELi44EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i59, i32, i32, i32, i32, i32) +declare dso_local spir_func i34 @_Z33__spirv_ArbitraryFloatATanPiINTELILi40ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i25, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i27 @_Z32__spirv_ArbitraryFloatATan2INTELILi24ELi25ELi27EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i25 signext, i32, i25 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i21 @_Z30__spirv_ArbitraryFloatPowINTELILi17ELi19ELi21EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i17 signext, i32, i19 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func i56 @_Z31__spirv_ArbitraryFloatPowRINTELILi54ELi55ELi56EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i59, i32, i55, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i15 @_Z31__spirv_ArbitraryFloatPowNINTELILi12ELi10ELi15EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiii(i14 signext, i32, i10 signext, i1 zeroext, i32, i32, i32, i32) +declare dso_local spir_func signext i15 @_Z31__spirv_ArbitraryFloatPowNINTELILi64ELi10ELi15EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiii(i64, i32, i10 signext, i1 zeroext, i32, i32, i32, i32) diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_floating_point/arbitrary_precision_floating_point_test_extended.ll b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_floating_point/arbitrary_precision_floating_point_test_extended.ll new file mode 100644 index 0000000000000..b32624dd9b662 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_arbitrary_precision_floating_point/arbitrary_precision_floating_point_test_extended.ll @@ -0,0 +1,96 @@ +; RUN: llc -mtriple=spirv32-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_floating_point,+SPV_INTEL_arbitrary_precision_integers %s -o - | FileCheck %s +; TODO: %if spirv-tools %{ llc -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_arbitrary_precision_floating_point,+SPV_INTEL_arbitrary_precision_integers %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpCapability Kernel +; CHECK: OpCapability ArbitraryPrecisionFloatingPointINTEL +; CHECK: OpCapability ArbitraryPrecisionIntegersINTEL +; CHECK: OpExtension "SPV_INTEL_arbitrary_precision_floating_point" +; CHECK: OpExtension "SPV_INTEL_arbitrary_precision_integers" + +; CHECK-DAG: OpTypeInt 2 0 +; CHECK-DAG: OpTypeInt 13 0 +; CHECK-DAG: OpTypeInt 14 0 +; CHECK-DAG: OpTypeInt 17 0 +; CHECK-DAG: OpTypeInt 18 0 +; CHECK-DAG: OpTypeInt 25 0 +; CHECK-DAG: OpTypeInt 30 0 +; CHECK-DAG: OpTypeInt 34 0 +; CHECK-DAG: OpTypeInt 39 0 +; CHECK-DAG: OpTypeInt 40 0 +; CHECK-DAG: OpTypeInt 42 0 +; CHECK-DAG: OpTypeInt 51 0 +; CHECK-DAG: OpTypeBool + +; CHECK: OpFunction +; CHECK: OpLabel +; CHECK: OpArbitraryFloatCastINTEL +; CHECK: OpArbitraryFloatCastFromIntINTEL +; CHECK: OpArbitraryFloatCastToIntINTEL +; CHECK: OpArbitraryFloatAddINTEL +; CHECK: OpArbitraryFloatSubINTEL +; CHECK: OpArbitraryFloatMulINTEL +; CHECK: OpArbitraryFloatDivINTEL +; CHECK: OpArbitraryFloatGTINTEL +; CHECK: OpArbitraryFloatGEINTEL +; CHECK: OpArbitraryFloatLTINTEL +; CHECK: OpArbitraryFloatLEINTEL +; CHECK: OpArbitraryFloatEQINTEL +; CHECK: OpArbitraryFloatRecipINTEL +; CHECK: OpArbitraryFloatRSqrtINTEL +; CHECK: OpArbitraryFloatCbrtINTEL +; CHECK: OpArbitraryFloatHypotINTEL +; CHECK: OpArbitraryFloatSqrtINTEL + +define dso_local spir_kernel void @test() { +entry: + %0 = alloca i63, align 8 + %1 = alloca i63, align 8 + %2 = alloca i8, align 1 + call spir_func void @ap_float_ops(i63* %0, i63* %1, i8* %2) + ret void +} + +define internal spir_func void @ap_float_ops(i63* %in1, i63* %in2, i8* %out) { +entry: + %0 = load i63, ptr %in1, align 8 + %1 = load i63, ptr %in2, align 8 + %cast = call spir_func i40 @_Z31__spirv_ArbitraryFloatCastINTELILi63ELi40EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i63 %0, i32 28, i32 30, i32 0, i32 2, i32 1) + %cast_from_int = call spir_func signext i25 @_Z38__spirv_ArbitraryFloatCastFromIntINTELILi40ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i40 %cast, i32 16, i1 zeroext false, i32 0, i32 2, i32 1) + %cast_to_int = call spir_func signext i30 @_Z36__spirv_ArbitraryFloatCastToIntINTELILi25ELi30EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i25 signext %cast_from_int, i32 15, i1 zeroext true, i32 0, i32 2, i32 1) + %add = call spir_func signext i14 @_Z30__spirv_ArbitraryFloatAddINTELILi30ELi40ELi14EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i30 signext %cast_to_int, i32 7, i40 %cast, i32 8, i32 9, i32 0, i32 2, i32 1) + %sub = call spir_func signext i13 @_Z30__spirv_ArbitraryFloatSubINTELILi14ELi30ELi13EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i14 signext %add, i32 4, i30 signext %cast_to_int, i32 5, i32 6, i32 0, i32 2, i32 1) + %mul = call spir_func i51 @_Z30__spirv_ArbitraryFloatMulINTELILi63ELi63ELi51EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i63 %0, i32 34, i63 %1, i32 34, i32 34, i32 0, i32 2, i32 1) + %div = call spir_func signext i18 @_Z30__spirv_ArbitraryFloatDivINTELILi51ELi40ELi18EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i51 signext %mul, i32 11, i40 signext %cast, i32 11, i32 12, i32 0, i32 2, i32 1) + %gt = call spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatGTINTELILi63ELi63EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i63 %0, i32 42, i63 %1, i32 41) + %ge = call spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatGEINTELILi51ELi40EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i51 %mul, i32 27, i40 %cast, i32 27) + %lt = call spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatLTINTELILi14ELi30EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i14 signext %add, i32 2, i30 signext %cast_to_int, i32 3) + %le = call spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatLEINTELILi51ELi40EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i51 %mul, i32 27, i40 %cast, i32 28) + %eq = call spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatEQINTELILi18ELi14EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i18 signext %div, i32 12, i14 signext %add, i32 7) + %recip = call spir_func i39 @_Z32__spirv_ArbitraryFloatRecipINTELILi40ELi39EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i40 %cast, i32 29, i32 29, i32 0, i32 2, i32 1) + %rsqrt = call spir_func i34 @_Z32__spirv_ArbitraryFloatRSqrtINTELILi39ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i39 %recip, i32 19, i32 20, i32 0, i32 2, i32 1) + %cbrt = call spir_func signext i2 @_Z31__spirv_ArbitraryFloatCbrtINTELILi13ELi2EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i13 signext %sub, i32 1, i32 1, i32 0, i32 2, i32 1) + %hypot = call spir_func i42 @_Z32__spirv_ArbitraryFloatHypotINTELILi40ELi40ELi42EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i40 %cast, i32 20, i40 %cast, i32 21, i32 22, i32 0, i32 2, i32 1) + %sqrt = call spir_func signext i17 @_Z31__spirv_ArbitraryFloatSqrtINTELILi14ELi17EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i14 signext %add, i32 7, i32 8, i32 0, i32 2, i32 1) + %sin = call spir_func signext i17 @_Z31__spirv_ArbitraryFloatSinINTELILi17ELi17EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i17 signext %sqrt, i32 7, i32 8, i32 0, i32 2, i32 1) + %final = zext i1 %gt to i8 + store i8 %final, ptr %out, align 1 + ret void +} +declare dso_local spir_func i40 @_Z31__spirv_ArbitraryFloatCastINTELILi63ELi40EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i63, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i25 @_Z38__spirv_ArbitraryFloatCastFromIntINTELILi40ELi25EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i40, i32, i1 zeroext, i32, i32, i32) +declare dso_local spir_func signext i30 @_Z36__spirv_ArbitraryFloatCastToIntINTELILi25ELi30EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiibiii(i25 signext, i32, i1 zeroext, i32, i32, i32) +declare dso_local spir_func signext i14 @_Z30__spirv_ArbitraryFloatAddINTELILi30ELi40ELi14EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i30 signext, i32, i40, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i13 @_Z30__spirv_ArbitraryFloatSubINTELILi14ELi30ELi13EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i14 signext, i32, i30 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func i51 @_Z30__spirv_ArbitraryFloatMulINTELILi63ELi63ELi51EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i63, i32, i63, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i18 @_Z30__spirv_ArbitraryFloatDivINTELILi51ELi40ELi18EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i51 signext, i32, i40 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatGTINTELILi63ELi63EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i63, i32, i63, i32) +declare dso_local spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatGEINTELILi51ELi40EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i51, i32, i40, i32) +declare dso_local spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatLTINTELILi14ELi30EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i14 signext, i32, i30 signext, i32) +declare dso_local spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatLEINTELILi51ELi40EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i51, i32, i40, i32) +declare dso_local spir_func zeroext i1 @_Z29__spirv_ArbitraryFloatEQINTELILi18ELi14EEbU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEii(i18 signext, i32, i14 signext, i32) +declare dso_local spir_func i39 @_Z32__spirv_ArbitraryFloatRecipINTELILi40ELi39EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i40, i32, i32, i32, i32, i32) +declare dso_local spir_func i34 @_Z32__spirv_ArbitraryFloatRSqrtINTELILi39ELi34EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i39, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i2 @_Z31__spirv_ArbitraryFloatCbrtINTELILi13ELi2EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i13 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func i42 @_Z32__spirv_ArbitraryFloatHypotINTELILi40ELi40ELi42EEU7_ExtIntIXT1_EEiU7_ExtIntIXT_EEiiU7_ExtIntIXT0_EEiiiiii(i40, i32, i40, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i17 @_Z31__spirv_ArbitraryFloatSqrtINTELILi14ELi17EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i14 signext, i32, i32, i32, i32, i32) +declare dso_local spir_func signext i17 @_Z31__spirv_ArbitraryFloatSinINTELILi17ELi17EEU7_ExtIntIXT0_EEiU7_ExtIntIXT_EEiiiiii(i17 signext, i32, i32, i32, i32, i32)