From 2c8582ec9c037bafe499be1022fd55ad419fece7 Mon Sep 17 00:00:00 2001 From: Min-Yih Hsu Date: Wed, 17 Sep 2025 13:32:38 -0700 Subject: [PATCH 1/2] [RISCV] Update SiFive7's scheduling model on masks and scalar movement instructions Co-Authored-By: Michael Maitland --- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 18 +- llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s | 125 +++ llvm/test/tools/llvm-mca/RISCV/SiFive7/vmv.s | 748 ++++++++++++++++++ 3 files changed, 887 insertions(+), 4 deletions(-) create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFive7/vmv.s diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index d81718c2361de..f2c946347923d 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -929,16 +929,16 @@ multiclass SiFive7WriteResBase.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { defm : LMULWriteResMX<"WriteVMALUV", [VCQ, VA1], mx, IsWorstCase>; - defm : LMULWriteResMX<"WriteVMPopV", [VCQ, VA1], mx, IsWorstCase>; - defm : LMULWriteResMX<"WriteVMFFSV", [VCQ, VA1], mx, IsWorstCase>; defm : LMULWriteResMX<"WriteVMSFSV", [VCQ, VA1], mx, IsWorstCase>; } } + // Simple mask logical used in series foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; @@ -947,13 +947,23 @@ multiclass SiFive7WriteResBase; } } + // Mask reduction + foreach mx = SchedMxList in { + defvar IsWorstCase = SiFive7IsWorstCaseMX.c; + let Latency = 11, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 11)] in { + defm "" : LMULWriteResMX<"WriteVMFFSV", [VCQ, VA1], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVMPopV", [VCQ, VA1], mx, IsWorstCase>; + } + } // 16. Vector Permutation Instructions + let Latency = 11, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 11)] in { + def : WriteRes; + def : WriteRes; + } let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 1)] in { def : WriteRes; - def : WriteRes; def : WriteRes; - def : WriteRes; } foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s new file mode 100644 index 0000000000000..6f46aa2eb959f --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s @@ -0,0 +1,125 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 -instruction-tables=full < %s | FileCheck %s + +vsetvli zero, zero, e32, m1, ta, ma + +vmslt.vv v0, v4, v20 +vmsle.vv v8, v4, v20 +vmsgt.vv v8, v20, v4 +vmsge.vv v8, v20, v4 +vmseq.vv v8, v4, v20 +vmsne.vv v8, v4, v20 +vmsltu.vv v8, v4, v20 +vmsleu.vv v8, v4, v20 +vmsgtu.vv v8, v20, v4 +vmsgeu.vv v8, v20, v4 + +vmflt.vv v0, v4, v20 +vmfle.vv v8, v4, v20 +vmfgt.vv v8, v20, v4 +vmfge.vv v8, v20, v4 +vmfeq.vv v8, v4, v20 +vmfne.vv v8, v4, v20 + +vmadc.vv v8, v4, v20 +vmsbc.vv v8, v4, v20 + +vfirst.m a2, v4 +vpopc.m a2, v4 + +viota.m v8, v4 + +vmsbf.m v8, v4 +vmsif.m v8, v4 +vmsof.m v8, v4 + +# CHECK: Resources: +# CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1 +# CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1 +# CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1 +# CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB +# CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1 +# CHECK-NEXT: [5] - VLEN512SiFive7VA:1 +# CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1 +# CHECK-NEXT: [7] - VLEN512SiFive7VL:1 +# CHECK-NEXT: [8] - VLEN512SiFive7VS:1 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) +# CHECK-NEXT: [7]: Bypass Latency +# CHECK-NEXT: [8]: Resources ( | [] | [, | [] | [, Date: Mon, 22 Sep 2025 16:58:36 -0700 Subject: [PATCH 2/2] fixup! Update occupancies --- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 4 +-- llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s | 10 +++--- llvm/test/tools/llvm-mca/RISCV/SiFive7/vmv.s | 34 +++++++++---------- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index f2c946347923d..2e14ae3af957e 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -950,14 +950,14 @@ multiclass SiFive7WriteResBase.c; - let Latency = 11, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 11)] in { + let Latency = 11, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 3)] in { defm "" : LMULWriteResMX<"WriteVMFFSV", [VCQ, VA1], mx, IsWorstCase>; defm "" : LMULWriteResMX<"WriteVMPopV", [VCQ, VA1], mx, IsWorstCase>; } } // 16. Vector Permutation Instructions - let Latency = 11, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 11)] in { + let Latency = 11, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 3)] in { def : WriteRes; def : WriteRes; } diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s index 6f46aa2eb959f..486b535382f87 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/mask.s @@ -75,8 +75,8 @@ vmsof.m v8, v4 # CHECK-NEXT: 1 5 2.00 5 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMFNE_VV vmfne.vv v8, v4, v20 # CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMADC_VV vmadc.vv v8, v4, v20 # CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VMSBC_VV vmsbc.vv v8, v4, v20 -# CHECK-NEXT: 1 11 11.00 11 VLEN512SiFive7VA[1,12],VLEN512SiFive7VCQ VFIRST_M vfirst.m a2, v4 -# CHECK-NEXT: 1 11 11.00 11 VLEN512SiFive7VA[1,12],VLEN512SiFive7VCQ VCPOP_M vcpop.m a2, v4 +# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFIRST_M vfirst.m a2, v4 +# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VCPOP_M vcpop.m a2, v4 # CHECK-NEXT: 1 4 2.00 4 VLEN512SiFive7VA[1,3],VLEN512SiFive7VCQ VIOTA_M viota.m v8, v4 # CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSBF_M vmsbf.m v8, v4 # CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMSIF_M vmsif.m v8, v4 @@ -94,7 +94,7 @@ vmsof.m v8, v4 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 1.00 - 87.00 24.00 - - +# CHECK-NEXT: - - 1.00 - 71.00 24.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: @@ -117,8 +117,8 @@ vmsof.m v8, v4 # CHECK-NEXT: - - - - 3.00 1.00 - - vmfne.vv v8, v4, v20 # CHECK-NEXT: - - - - 3.00 1.00 - - vmadc.vv v8, v4, v20 # CHECK-NEXT: - - - - 3.00 1.00 - - vmsbc.vv v8, v4, v20 -# CHECK-NEXT: - - - - 12.00 1.00 - - vfirst.m a2, v4 -# CHECK-NEXT: - - - - 12.00 1.00 - - vcpop.m a2, v4 +# CHECK-NEXT: - - - - 4.00 1.00 - - vfirst.m a2, v4 +# CHECK-NEXT: - - - - 4.00 1.00 - - vcpop.m a2, v4 # CHECK-NEXT: - - - - 3.00 1.00 - - viota.m v8, v4 # CHECK-NEXT: - - - - 2.00 1.00 - - vmsbf.m v8, v4 # CHECK-NEXT: - - - - 2.00 1.00 - - vmsif.m v8, v4 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/vmv.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vmv.s index 36cabc54ce7a0..3d3fe4d1b05f3 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/vmv.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/vmv.s @@ -475,28 +475,28 @@ vfmv.f.s f7, v16 # CHECK-NEXT: 1 4 16.00 4 VLEN512SiFive7VA[1,17],VLEN512SiFive7VCQ VMV8R_V vmv8r.v v8, v16 # CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu # CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0 -# CHECK-NEXT: 1 11 11.00 11 VLEN512SiFive7VA[1,12],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16 +# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16 # CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu # CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0 -# CHECK-NEXT: 1 11 11.00 11 VLEN512SiFive7VA[1,12],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16 +# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16 # CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu # CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0 -# CHECK-NEXT: 1 11 11.00 11 VLEN512SiFive7VA[1,12],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16 +# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16 # CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu # CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VMV_S_X vmv.s.x v8, t0 -# CHECK-NEXT: 1 11 11.00 11 VLEN512SiFive7VA[1,12],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16 +# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VMV_X_S vmv.x.s t2, v16 # CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m1, tu, mu # CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5 -# CHECK-NEXT: 1 11 11.00 11 VLEN512SiFive7VA[1,12],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16 +# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16 # CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m2, tu, mu # CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5 -# CHECK-NEXT: 1 11 11.00 11 VLEN512SiFive7VA[1,12],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16 +# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16 # CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m4, tu, mu # CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5 -# CHECK-NEXT: 1 11 11.00 11 VLEN512SiFive7VA[1,12],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16 +# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16 # CHECK-NEXT: 1 3 1.00 U 1 VLEN512SiFive7PipeA,VLEN512SiFive7PipeAB VSETVLI vsetvli zero, zero, e64, m8, tu, mu # CHECK-NEXT: 1 4 1.00 4 VLEN512SiFive7VA[1,2],VLEN512SiFive7VCQ VFMV_S_F vfmv.s.f v8, ft5 -# CHECK-NEXT: 1 11 11.00 11 VLEN512SiFive7VA[1,12],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16 +# CHECK-NEXT: 1 11 3.00 11 VLEN512SiFive7VA[1,4],VLEN512SiFive7VCQ VFMV_F_S vfmv.f.s ft7, v16 # CHECK: Resources: # CHECK-NEXT: [0] - VLEN512SiFive7FDiv @@ -510,7 +510,7 @@ vfmv.f.s f7, v16 # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] -# CHECK-NEXT: - - 112.00 - 996.00 120.00 - - +# CHECK-NEXT: - - 112.00 - 932.00 120.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: @@ -724,25 +724,25 @@ vfmv.f.s f7, v16 # CHECK-NEXT: - - - - 17.00 1.00 - - vmv8r.v v8, v16 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - 2.00 1.00 - - vmv.s.x v8, t0 -# CHECK-NEXT: - - - - 12.00 1.00 - - vmv.x.s t2, v16 +# CHECK-NEXT: - - - - 4.00 1.00 - - vmv.x.s t2, v16 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu # CHECK-NEXT: - - - - 2.00 1.00 - - vmv.s.x v8, t0 -# CHECK-NEXT: - - - - 12.00 1.00 - - vmv.x.s t2, v16 +# CHECK-NEXT: - - - - 4.00 1.00 - - vmv.x.s t2, v16 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu # CHECK-NEXT: - - - - 2.00 1.00 - - vmv.s.x v8, t0 -# CHECK-NEXT: - - - - 12.00 1.00 - - vmv.x.s t2, v16 +# CHECK-NEXT: - - - - 4.00 1.00 - - vmv.x.s t2, v16 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu # CHECK-NEXT: - - - - 2.00 1.00 - - vmv.s.x v8, t0 -# CHECK-NEXT: - - - - 12.00 1.00 - - vmv.x.s t2, v16 +# CHECK-NEXT: - - - - 4.00 1.00 - - vmv.x.s t2, v16 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu # CHECK-NEXT: - - - - 2.00 1.00 - - vfmv.s.f v8, ft5 -# CHECK-NEXT: - - - - 12.00 1.00 - - vfmv.f.s ft7, v16 +# CHECK-NEXT: - - - - 4.00 1.00 - - vfmv.f.s ft7, v16 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu # CHECK-NEXT: - - - - 2.00 1.00 - - vfmv.s.f v8, ft5 -# CHECK-NEXT: - - - - 12.00 1.00 - - vfmv.f.s ft7, v16 +# CHECK-NEXT: - - - - 4.00 1.00 - - vfmv.f.s ft7, v16 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu # CHECK-NEXT: - - - - 2.00 1.00 - - vfmv.s.f v8, ft5 -# CHECK-NEXT: - - - - 12.00 1.00 - - vfmv.f.s ft7, v16 +# CHECK-NEXT: - - - - 4.00 1.00 - - vfmv.f.s ft7, v16 # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu # CHECK-NEXT: - - - - 2.00 1.00 - - vfmv.s.f v8, ft5 -# CHECK-NEXT: - - - - 12.00 1.00 - - vfmv.f.s ft7, v16 +# CHECK-NEXT: - - - - 4.00 1.00 - - vfmv.f.s ft7, v16